From de62893bc0725f8b5f0445250577cd7a10b2d8f8 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Mon, 13 Mar 2006 18:23:03 +0900 Subject: [MIPS] local_r4k_flush_cache_page fix If dcache_size != icache_size or dcache_size != scache_size, or set-associative cache, icache/scache does not flushed properly. Make blast_?cache_page_indexed() masks its index value correctly. Also, use physical address for physically indexed pcache/scache. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- include/asm-mips/r4kcache.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/asm-mips/r4kcache.h') diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h index 9632c27dad1..0bcb79a58ee 100644 --- a/include/asm-mips/r4kcache.h +++ b/include/asm-mips/r4kcache.h @@ -257,7 +257,8 @@ static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \ \ static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \ { \ - unsigned long start = page; \ + unsigned long indexmask = current_cpu_data.desc.waysize - 1; \ + unsigned long start = INDEX_BASE + (page & indexmask); \ unsigned long end = start + PAGE_SIZE; \ unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ unsigned long ws_end = current_cpu_data.desc.ways << \ -- cgit v1.2.3