From b229632abd451ab2c797010b9788e48c9314db4f Mon Sep 17 00:00:00 2001 From: Yoshinori Sato Date: Sun, 5 Nov 2006 16:18:08 +0900 Subject: sh: Add SH-2A platform headers. Mostly SH-2 wrappers.. Signed-off-by: Yoshinori Sato Signed-off-by: Paul Mundt --- include/asm-sh/cpu-sh2/cache.h | 22 ++++++++++ include/asm-sh/cpu-sh2/freq.h | 18 ++++++++ include/asm-sh/cpu-sh2/irq.h | 84 ++++++++++++++++++++++++++++++++++++ include/asm-sh/cpu-sh2/mmu_context.h | 16 +++++++ 4 files changed, 140 insertions(+) create mode 100644 include/asm-sh/cpu-sh2/freq.h create mode 100644 include/asm-sh/cpu-sh2/irq.h create mode 100644 include/asm-sh/cpu-sh2/mmu_context.h (limited to 'include/asm-sh/cpu-sh2') diff --git a/include/asm-sh/cpu-sh2/cache.h b/include/asm-sh/cpu-sh2/cache.h index cd96402e856..20b9796842d 100644 --- a/include/asm-sh/cpu-sh2/cache.h +++ b/include/asm-sh/cpu-sh2/cache.h @@ -12,6 +12,7 @@ #define L1_CACHE_SHIFT 4 +#if defined(CONFIG_CPU_SUBTYPE_SH7604) #define CCR 0xfffffe92 /* Address of Cache Control Register */ #define CCR_CACHE_CE 0x01 /* Cache enable */ @@ -27,5 +28,26 @@ #define CCR_CACHE_ORA CCR_CACHE_TW #define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */ +#elif defined(CONFIG_CPU_SUBTYPE_SH7619) +#define CCR1 0xffffffec +#define CCR CCR1 + +#define CCR_CACHE_CE 0x01 /* Cache enable */ +#define CCR_CACHE_WT 0x06 /* CCR[bit1=1,bit2=1] */ + /* 0x00000000-0x7fffffff: Write-through */ + /* 0x80000000-0x9fffffff: Write-back */ + /* 0xc0000000-0xdfffffff: Write-through */ +#define CCR_CACHE_CB 0x00 /* CCR[bit1=0,bit2=0] */ + /* 0x00000000-0x7fffffff: Write-back */ + /* 0x80000000-0x9fffffff: Write-through */ + /* 0xc0000000-0xdfffffff: Write-back */ +#define CCR_CACHE_CF 0x08 /* Cache invalidate */ + +#define CACHE_OC_ADDRESS_ARRAY 0xf0000000 +#define CACHE_OC_DATA_ARRAY 0xf1000000 + +#define CCR_CACHE_ENABLE CCR_CACHE_CE +#define CCR_CACHE_INVALIDATE CCR_CACHE_CF +#endif #endif /* __ASM_CPU_SH2_CACHE_H */ diff --git a/include/asm-sh/cpu-sh2/freq.h b/include/asm-sh/cpu-sh2/freq.h new file mode 100644 index 00000000000..31de475da70 --- /dev/null +++ b/include/asm-sh/cpu-sh2/freq.h @@ -0,0 +1,18 @@ +/* + * include/asm-sh/cpu-sh2/freq.h + * + * Copyright (C) 2006 Yoshinori Sato + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH2_FREQ_H +#define __ASM_CPU_SH2_FREQ_H + +#if defined(CONFIG_CPU_SUBTYPE_SH7619) +#define FREQCR 0xf815ff80 +#endif + +#endif /* __ASM_CPU_SH2_FREQ_H */ + diff --git a/include/asm-sh/cpu-sh2/irq.h b/include/asm-sh/cpu-sh2/irq.h new file mode 100644 index 00000000000..4032a14d0f4 --- /dev/null +++ b/include/asm-sh/cpu-sh2/irq.h @@ -0,0 +1,84 @@ +#ifndef __ASM_SH_CPU_SH2_IRQ_H +#define __ASM_SH_CPU_SH2_IRQ_H + +/* + * + * linux/include/asm-sh/cpu-sh2/irq.h + * + * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi + * Copyright (C) 2000 Kazumoto Kojima + * Copyright (C) 2003 Paul Mundt + * + */ + +#include + +#if defined(CONFIG_CPU_SUBTYPE_SH7044) +#define INTC_IPRA 0xffff8348UL +#define INTC_IPRB 0xffff834aUL +#define INTC_IPRC 0xffff834cUL +#define INTC_IPRD 0xffff834eUL +#define INTC_IPRE 0xffff8350UL +#define INTC_IPRF 0xffff8352UL +#define INTC_IPRG 0xffff8354UL +#define INTC_IPRH 0xffff8356UL + +#define INTC_ICR 0xffff8358UL +#define INTC_ISR 0xffff835aUL +#elif defined(CONFIG_CPU_SUBTYPE_SH7604) +#define INTC_IPRA 0xfffffee2UL +#define INTC_IPRB 0xfffffe60UL + +#define INTC_VCRA 0xfffffe62UL +#define INTC_VCRB 0xfffffe64UL +#define INTC_VCRC 0xfffffe66UL +#define INTC_VCRD 0xfffffe68UL + +#define INTC_VCRWDT 0xfffffee4UL +#define INTC_VCRDIV 0xffffff0cUL +#define INTC_VCRDMA0 0xffffffa0UL +#define INTC_VCRDMA1 0xffffffa8UL + +#define INTC_ICR 0xfffffee0UL +#elif defined(CONFIG_CPU_SUBTYPE_SH7619) +#define INTC_IPRA 0xf8140006UL +#define INTC_IPRB 0xf8140008UL +#define INTC_IPRC 0xf8080000UL +#define INTC_IPRD 0xf8080002UL +#define INTC_IPRE 0xf8080004UL +#define INTC_IPRF 0xf8080006UL +#define INTC_IPRG 0xf8080008UL + +#define INTC_ICR0 0xf8140000UL +#define INTC_IRQCR 0xf8140002UL +#define INTC_IRQSR 0xf8140004UL + +#define CMI0_IRQ 86 +#define CMI1_IRQ 87 + +#define SCIF_ERI_IRQ 88 +#define SCIF_RXI_IRQ 89 +#define SCIF_BRI_IRQ 90 +#define SCIF_TXI_IRQ 91 +#define SCIF_IPR_ADDR INTC_IPRD +#define SCIF_IPR_POS 3 +#define SCIF_PRIORITY 3 + +#define SCIF1_ERI_IRQ 92 +#define SCIF1_RXI_IRQ 93 +#define SCIF1_BRI_IRQ 94 +#define SCIF1_TXI_IRQ 95 +#define SCIF1_IPR_ADDR INTC_IPRD +#define SCIF1_IPR_POS 2 +#define SCIF1_PRIORITY 3 + +#define SCIF2_BRI_IRQ 96 +#define SCIF2_RXI_IRQ 97 +#define SCIF2_ERI_IRQ 98 +#define SCIF2_TXI_IRQ 99 +#define SCIF2_IPR_ADDR INTC_IPRD +#define SCIF2_IPR_POS 1 +#define SCIF2_PRIORITY 3 +#endif + +#endif /* __ASM_SH_CPU_SH2_IRQ_H */ diff --git a/include/asm-sh/cpu-sh2/mmu_context.h b/include/asm-sh/cpu-sh2/mmu_context.h new file mode 100644 index 00000000000..beeb299e01e --- /dev/null +++ b/include/asm-sh/cpu-sh2/mmu_context.h @@ -0,0 +1,16 @@ +/* + * include/asm-sh/cpu-sh2/mmu_context.h + * + * Copyright (C) 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH2_MMU_CONTEXT_H +#define __ASM_CPU_SH2_MMU_CONTEXT_H + +/* No MMU */ + +#endif /* __ASM_CPU_SH2_MMU_CONTEXT_H */ + -- cgit v1.2.3