From 0df29025fd0379d5950d206314d0b10a2c8a9607 Mon Sep 17 00:00:00 2001 From: Doug Chapman Date: Mon, 28 Jan 2008 15:33:28 -0800 Subject: [IA64] fix userspace compile error in gcc_intrin.h Fixes userspace build errors when linux/ipv6.h is included such as in the dhcpv6 package under fedora. Likely causes other userspace build errors as well. I found this in akpm's tree from 2.6.18 but could not find any case of anyone proposing it for the main tree. Signed-off-by: Doug Chapman Signed-off-by: Andrew Morton Signed-off-by: Tony Luck --- include/asm-ia64/gcc_intrin.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/asm-ia64/gcc_intrin.h b/include/asm-ia64/gcc_intrin.h index 5b6665c754c..de2ed2cbdd8 100644 --- a/include/asm-ia64/gcc_intrin.h +++ b/include/asm-ia64/gcc_intrin.h @@ -24,7 +24,9 @@ extern void ia64_bad_param_for_setreg (void); extern void ia64_bad_param_for_getreg (void); +#ifdef __KERNEL__ register unsigned long ia64_r13 asm ("r13") __used; +#endif #define ia64_setreg(regnum, val) \ ({ \ -- cgit v1.2.3 From 5302ac5019367470e123cb91844a28d6941e6912 Mon Sep 17 00:00:00 2001 From: Zoltan Menyhart Date: Mon, 4 Feb 2008 15:19:16 -0800 Subject: [IA64] Slim-down __clear_bit_unlock - I removed the unnecessary barrier() from __clear_bit_unlock(). ia64_st4_rel_nta() makes sure all the modifications are globally seen before the bit is seen to be off. - I made __clear_bit() modeled after __set_bit() and __change_bit(). - I corrected some comments sating that a memory barrier is provided, yet in reality, it is the acquisition side of the memory barrier only. - I corrected some comments, e.g. test_and_clear_bit() was peaking about "bit to set". Signed-off-by: Zoltan Menyhart, Acked-by: Nick Piggin Signed-off-by: Andrew Morton Signed-off-by: Tony Luck --- include/asm-ia64/bitops.h | 50 ++++++++++++++++++++++++++--------------------- 1 file changed, 28 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/include/asm-ia64/bitops.h b/include/asm-ia64/bitops.h index a1b9719f5fb..953d3df9dd2 100644 --- a/include/asm-ia64/bitops.h +++ b/include/asm-ia64/bitops.h @@ -122,38 +122,40 @@ clear_bit_unlock (int nr, volatile void *addr) } /** - * __clear_bit_unlock - Non-atomically clear a bit with release + * __clear_bit_unlock - Non-atomically clears a bit in memory with release + * @nr: Bit to clear + * @addr: Address to start counting from * - * This is like clear_bit_unlock, but the implementation uses a store + * Similarly to clear_bit_unlock, the implementation uses a store * with release semantics. See also __raw_spin_unlock(). */ static __inline__ void -__clear_bit_unlock(int nr, volatile void *addr) +__clear_bit_unlock(int nr, void *addr) { - __u32 mask, new; - volatile __u32 *m; + __u32 * const m = (__u32 *) addr + (nr >> 5); + __u32 const new = *m & ~(1 << (nr & 31)); - m = (volatile __u32 *)addr + (nr >> 5); - mask = ~(1 << (nr & 31)); - new = *m & mask; - barrier(); ia64_st4_rel_nta(m, new); } /** * __clear_bit - Clears a bit in memory (non-atomic version) + * @nr: the bit to clear + * @addr: the address to start counting from + * + * Unlike clear_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. */ static __inline__ void __clear_bit (int nr, volatile void *addr) { - volatile __u32 *p = (__u32 *) addr + (nr >> 5); - __u32 m = 1 << (nr & 31); - *p &= ~m; + *((__u32 *) addr + (nr >> 5)) &= ~(1 << (nr & 31)); } /** * change_bit - Toggle a bit in memory - * @nr: Bit to clear + * @nr: Bit to toggle * @addr: Address to start counting from * * change_bit() is atomic and may not be reordered. @@ -178,7 +180,7 @@ change_bit (int nr, volatile void *addr) /** * __change_bit - Toggle a bit in memory - * @nr: the bit to set + * @nr: the bit to toggle * @addr: the address to start counting from * * Unlike change_bit(), this function is non-atomic and may be reordered. @@ -197,7 +199,7 @@ __change_bit (int nr, volatile void *addr) * @addr: Address to count from * * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. + * It also implies the acquisition side of the memory barrier. */ static __inline__ int test_and_set_bit (int nr, volatile void *addr) @@ -247,11 +249,11 @@ __test_and_set_bit (int nr, volatile void *addr) /** * test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to set + * @nr: Bit to clear * @addr: Address to count from * * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. + * It also implies the acquisition side of the memory barrier. */ static __inline__ int test_and_clear_bit (int nr, volatile void *addr) @@ -272,7 +274,7 @@ test_and_clear_bit (int nr, volatile void *addr) /** * __test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to set + * @nr: Bit to clear * @addr: Address to count from * * This operation is non-atomic and can be reordered. @@ -292,11 +294,11 @@ __test_and_clear_bit(int nr, volatile void * addr) /** * test_and_change_bit - Change a bit and return its old value - * @nr: Bit to set + * @nr: Bit to change * @addr: Address to count from * * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. + * It also implies the acquisition side of the memory barrier. */ static __inline__ int test_and_change_bit (int nr, volatile void *addr) @@ -315,8 +317,12 @@ test_and_change_bit (int nr, volatile void *addr) return (old & bit) != 0; } -/* - * WARNING: non atomic version. +/** + * __test_and_change_bit - Change a bit and return its old value + * @nr: Bit to change + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. */ static __inline__ int __test_and_change_bit (int nr, void *addr) -- cgit v1.2.3 From fe77efb8b7e80128b914044c175d5dcd75e9fff7 Mon Sep 17 00:00:00 2001 From: Hidetoshi Seto Date: Mon, 7 Jan 2008 10:11:57 +0900 Subject: [IA64] mca style cleanup Unified changelog, 80 columns rule, and address form fix. Signed-off-by: Hidetoshi Seto Signed-off-by: Tony Luck --- include/asm-ia64/mca.h | 6 +++--- include/asm-ia64/mca_asm.h | 3 ++- 2 files changed, 5 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/asm-ia64/mca.h b/include/asm-ia64/mca.h index 823553bf12e..f1663aa94a5 100644 --- a/include/asm-ia64/mca.h +++ b/include/asm-ia64/mca.h @@ -3,9 +3,9 @@ * Purpose: Machine check handling specific defines * * Copyright (C) 1999, 2004 Silicon Graphics, Inc. - * Copyright (C) Vijay Chander (vijay@engr.sgi.com) - * Copyright (C) Srinivasa Thirumalachar (sprasad@engr.sgi.com) - * Copyright (C) Russ Anderson (rja@sgi.com) + * Copyright (C) Vijay Chander + * Copyright (C) Srinivasa Thirumalachar + * Copyright (C) Russ Anderson */ #ifndef _ASM_IA64_MCA_H diff --git a/include/asm-ia64/mca_asm.h b/include/asm-ia64/mca_asm.h index 76203f9a871..dd2a5b13439 100644 --- a/include/asm-ia64/mca_asm.h +++ b/include/asm-ia64/mca_asm.h @@ -1,8 +1,9 @@ /* * File: mca_asm.h + * Purpose: Machine check handling specific defines * * Copyright (C) 1999 Silicon Graphics, Inc. - * Copyright (C) Vijay Chander (vijay@engr.sgi.com) + * Copyright (C) Vijay Chander * Copyright (C) Srinivasa Thirumalachar * Copyright (C) 2000 Hewlett-Packard Co. * Copyright (C) 2000 David Mosberger-Tang -- cgit v1.2.3 From a7d57ecf4216ed29328f8e701bd65ebb66a0284c Mon Sep 17 00:00:00 2001 From: "Zhang, Xiantao" Date: Mon, 4 Feb 2008 15:46:23 -0800 Subject: [IA64] Export three symbols for module use Since kvm/module needs to use some unexported functions in kernel, so export them with this patch. Signed-off-by: Zhang Xiantao Signed-off-by: Tony Luck --- include/asm-ia64/sal.h | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/include/asm-ia64/sal.h b/include/asm-ia64/sal.h index 1f5412d6f9b..2251118894a 100644 --- a/include/asm-ia64/sal.h +++ b/include/asm-ia64/sal.h @@ -649,17 +649,6 @@ typedef struct err_rec { * Now define a couple of inline functions for improved type checking * and convenience. */ -static inline long -ia64_sal_freq_base (unsigned long which, unsigned long *ticks_per_second, - unsigned long *drift_info) -{ - struct ia64_sal_retval isrv; - - SAL_CALL(isrv, SAL_FREQ_BASE, which, 0, 0, 0, 0, 0, 0); - *ticks_per_second = isrv.v0; - *drift_info = isrv.v1; - return isrv.status; -} extern s64 ia64_sal_cache_flush (u64 cache_type); extern void __init check_sal_cache_flush (void); @@ -841,6 +830,9 @@ extern int ia64_sal_oemcall_nolock(struct ia64_sal_retval *, u64, u64, u64, u64, u64, u64, u64, u64); extern int ia64_sal_oemcall_reentrant(struct ia64_sal_retval *, u64, u64, u64, u64, u64, u64, u64, u64); +extern long +ia64_sal_freq_base (unsigned long which, unsigned long *ticks_per_second, + unsigned long *drift_info); #ifdef CONFIG_HOTPLUG_CPU /* * System Abstraction Layer Specification -- cgit v1.2.3 From f00c2d36bf6d7efece79713930763d9a0460283e Mon Sep 17 00:00:00 2001 From: Xiantao Zhang Date: Thu, 31 Jan 2008 17:46:09 +0800 Subject: [IA64] ia64_set_psr should use srlz.i The only in kernel use of ia64_set_psr() needs to follow it with a srlz.i (since it is changing state for PSR.ic). So it is pointless to issue srlz.d inside this function. Signed-off-by: Xiantao Zhang Signed-off-by: Tony Luck --- include/asm-ia64/processor.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h index be3b0ae4327..038642f6d19 100644 --- a/include/asm-ia64/processor.h +++ b/include/asm-ia64/processor.h @@ -472,7 +472,7 @@ ia64_set_psr (__u64 psr) { ia64_stop(); ia64_setreg(_IA64_REG_PSR_L, psr); - ia64_srlz_d(); + ia64_srlz_i(); } /* -- cgit v1.2.3