From 2e56ff206b7c6c28b847ccdbe46ad69b3263ac32 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 19 Jul 2007 16:07:35 -0500 Subject: [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime Make it so we do a runtime check to know if we need to write cfg_addr as big or little endian. This is needed if we want to allow 86xx support to co-exist in the same kernel as other 6xx PPCs. Signed-off-by: Kumar Gala --- include/asm-powerpc/pci-bridge.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h index 13cb0a97347..9ce8f2991ac 100644 --- a/include/asm-powerpc/pci-bridge.h +++ b/include/asm-powerpc/pci-bridge.h @@ -49,11 +49,13 @@ struct pci_controller { * hanging if we don't have link and try to do config cycles to * anything but the PHB. Only allow talking to the PHB if this is * set. + * BIG_ENDIAN - cfg_addr is a big endian register */ #define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001) #define PPC_INDIRECT_TYPE_EXT_REG (0x00000002) #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004) #define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008) +#define PPC_INDIRECT_TYPE_BIG_ENDIAN (0x00000010) u32 indirect_type; /* Currently, we limit ourselves to 1 IO range and 3 mem @@ -88,7 +90,7 @@ extern int early_find_capability(struct pci_controller *hose, int bus, int dev_fn, int cap); extern void setup_indirect_pci(struct pci_controller* hose, - u32 cfg_addr, u32 cfg_data); + u32 cfg_addr, u32 cfg_data, u32 flags); extern void setup_grackle(struct pci_controller *hose); #else -- cgit v1.2.3