From c2f9527979c14a21bbaa31c12a14204aabeb6e45 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Wed, 7 May 2008 11:41:26 +0800 Subject: [Blackfin] arch: Equalize include files: Add VR_CTL masks Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf533/defBF532.h | 2 ++ include/asm-blackfin/mach-bf548/defBF54x_base.h | 20 ++++++++++++++++++ include/asm-blackfin/mach-bf561/defBF561.h | 28 +++++++++++++++++++++++++ 3 files changed, 50 insertions(+) (limited to 'include') diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h index 17e1548cec0..0ab4dd7494c 100644 --- a/include/asm-blackfin/mach-bf533/defBF532.h +++ b/include/asm-blackfin/mach-bf533/defBF532.h @@ -468,6 +468,8 @@ #define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ #define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ #define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ #define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h index 08f90c21fe8..e022e896cb1 100644 --- a/include/asm-blackfin/mach-bf548/defBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h @@ -2329,6 +2329,26 @@ #define KPADWE 0x1000 /* Keypad Wake-Up Enable */ #define ROTWE 0x2000 /* Rotary Wake-Up Enable */ +#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ +#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ +#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ + +#define GAIN_5 0x0000 /* GAIN = 5*/ +#define GAIN_10 0x0004 /* GAIN = 1*/ +#define GAIN_20 0x0008 /* GAIN = 2*/ +#define GAIN_50 0x000C /* GAIN = 5*/ + +#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ +#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ +#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ + /* Bit masks for NFC_CTL */ #define WR_DLY 0xf /* Write Strobe Delay */ diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h index 366c9b9a0cb..1ab50e906fe 100644 --- a/include/asm-blackfin/mach-bf561/defBF561.h +++ b/include/asm-blackfin/mach-bf561/defBF561.h @@ -868,6 +868,34 @@ #define CHIPID_FAMILY 0x0FFFF000 #define CHIPID_MANUFACTURE 0x00000FFE +/* VR_CTL Masks */ +#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ +#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ +#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ +#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ +#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ + +#define GAIN 0x000C /* Voltage Level Gain */ +#define GAIN_5 0x0000 /* GAIN = 5*/ +#define GAIN_10 0x0004 /* GAIN = 1*/ +#define GAIN_20 0x0008 /* GAIN = 2*/ +#define GAIN_50 0x000C /* GAIN = 5*/ + +#define VLEV 0x00F0 /* Internal Voltage Level */ +#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ +#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ +#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ + +#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ +#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ + /* PLL_DIV Masks */ #define SCLK_DIV(x) (x) /* SCLK = VCO / x */ -- cgit v1.2.3 From 14b03204c8060d036b04cbb18bbd6f6f311f4fed Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Wed, 7 May 2008 11:41:26 +0800 Subject: [Blackfin] arch: Functional power management support: Add CPU and platform voltage scaling support Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- include/asm-blackfin/dpmc.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-blackfin/dpmc.h b/include/asm-blackfin/dpmc.h index 686cf83a526..7f34cd384f1 100644 --- a/include/asm-blackfin/dpmc.h +++ b/include/asm-blackfin/dpmc.h @@ -1,7 +1,7 @@ /* * include/asm-blackfin/dpmc.h - Miscellaneous IOCTL commands for Dynamic Power * Management Controller Driver. - * Copyright (C) 2004 Analog Device Inc. + * Copyright (C) 2004-2008 Analog Device Inc. * */ #ifndef _BLACKFIN_DPMC_H_ @@ -65,6 +65,14 @@ void disable_wdog_timer(void); extern unsigned long get_cclk(void); extern unsigned long get_sclk(void); +struct bfin_dpmc_platform_data { + const unsigned int *tuple_tab; + unsigned short tabsize; + unsigned short vr_settling_time; /* in us */ +}; + +#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16)) + #endif /* __KERNEL__ */ #endif /*_BLACKFIN_DPMC_H_*/ -- cgit v1.2.3 From 1bfb4b21c7c39295f5535c139f796df1d51ec009 Mon Sep 17 00:00:00 2001 From: Vitja Makarov Date: Wed, 7 May 2008 11:41:26 +0800 Subject: [Blackfin] arch: Support for CPU_FREQ and NOHZ Singed-off-by: Vitja Makarov --- include/asm-blackfin/time.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/asm-blackfin/time.h b/include/asm-blackfin/time.h index 6e5859b6ea3..ddc43ce3853 100644 --- a/include/asm-blackfin/time.h +++ b/include/asm-blackfin/time.h @@ -24,6 +24,8 @@ #ifndef CONFIG_CPU_FREQ #define TIME_SCALE 1 +#define __bfin_cycles_off (0) +#define __bfin_cycles_mod (0) #else /* * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 . @@ -31,6 +33,8 @@ * adjust the Core Timer Presale Register. This way we don't lose time. */ #define TIME_SCALE 4 +extern unsigned long long __bfin_cycles_off; +extern unsigned int __bfin_cycles_mod; #endif #endif -- cgit v1.2.3 From 0893f1250f87e0a832f47bb60fb69ed0d52be7a3 Mon Sep 17 00:00:00 2001 From: Bernd Schmidt Date: Wed, 7 May 2008 11:41:26 +0800 Subject: [Blackfin] arch: fix gdb testing regression When transferring to IRQ5 from an exception, save SYSCFG in memory across the transfer and clear the trace bit. When we get a single step exception, check whether we can safely clear the trace bit in SYSCFG. We can (and should) clear it after the first instruction of the interrupt handler; the first insn saves SYSCFG to the stack in all handlers. Signed-off-by: Bernd Schmidt Signed-off-by: Bryan Wu --- include/asm-blackfin/entry.h | 5 +++++ include/asm-blackfin/mach-common/context.S | 5 +++++ 2 files changed, 10 insertions(+) (limited to 'include') diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h index 562c6d3a323..c4f721e0d00 100644 --- a/include/asm-blackfin/entry.h +++ b/include/asm-blackfin/entry.h @@ -17,6 +17,11 @@ #define PF_DTRACE_OFF 1 #define PF_DTRACE_BIT 5 +/* + * NOTE! The single-stepping code assumes that all interrupt handlers + * start by saving SYSCFG on the stack with their first instruction. + */ + /* This one is used for exceptions, emulation, and NMI. It doesn't push RETI and doesn't do cli. */ #define SAVE_ALL_SYS save_context_no_interrupts diff --git a/include/asm-blackfin/mach-common/context.S b/include/asm-blackfin/mach-common/context.S index fd0ebe1862b..c0e630edfb9 100644 --- a/include/asm-blackfin/mach-common/context.S +++ b/include/asm-blackfin/mach-common/context.S @@ -27,6 +27,11 @@ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* + * NOTE! The single-stepping code assumes that all interrupt handlers + * start by saving SYSCFG on the stack with their first instruction. + */ + /* * Code to save processor context. * We even save the register which are preserved by a function call -- cgit v1.2.3 From 56f87713022a6bdf00b0a50d086fdaddb54e8e5c Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Sat, 10 May 2008 00:11:59 +0800 Subject: [Blackfin] arch: remove useless IRQ_SW_INT defines IRQ_SW_INT1 and IRQ_SW_INT2 obsolete: Remove useless defines Fix SYS_IRQS Keep numbering scheme, so we don't break existing configurations. Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf533/irq.h | 14 ++++++-------- include/asm-blackfin/mach-bf537/irq.h | 35 ++++++++++++++++------------------- include/asm-blackfin/mach-bf561/irq.h | 13 ++++++------- 3 files changed, 28 insertions(+), 34 deletions(-) (limited to 'include') diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h index 832e6f6122d..5aa38e5da6b 100644 --- a/include/asm-blackfin/mach-bf533/irq.h +++ b/include/asm-blackfin/mach-bf533/irq.h @@ -66,12 +66,13 @@ Core Emulation ** DMA8/9 Interrupt IVG13 28 DMA10/11 Interrupt IVG13 29 Watchdog Timer IVG13 30 - Software Interrupt 1 IVG14 31 - Software Interrupt 2 -- + + Softirq IVG14 31 + System Call -- (lowest priority) IVG15 32 * */ -#define SYS_IRQS 32 -#define NR_PERI_INTS 24 +#define SYS_IRQS 31 +#define NR_PERI_INTS 24 /* The ABSTRACT IRQ definitions */ /** the first seven of the following are fixed, the rest you change if you need to **/ @@ -96,7 +97,7 @@ Core Emulation ** #define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */ #define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */ #define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */ -#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ +#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ #define IRQ_UART_RX 21 /*DMA6 Interrupt (UART RX) */ #define IRQ_UART_TX 22 /*DMA7 Interrupt (UART TX) */ #define IRQ_TMR0 23 /*Timer 0 */ @@ -108,9 +109,6 @@ Core Emulation ** #define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */ #define IRQ_WATCH 30 /*Watch Dog Timer */ -#define IRQ_SW_INT1 31 /*Software Int 1 */ -#define IRQ_SW_INT2 32 /*Software Int 2 (reserved for SYSCALL) */ - #define IRQ_PF0 33 #define IRQ_PF1 34 #define IRQ_PF2 35 diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h index be6f2ff77f3..2e68a8a1e73 100644 --- a/include/asm-blackfin/mach-bf537/irq.h +++ b/include/asm-blackfin/mach-bf537/irq.h @@ -34,24 +34,23 @@ /* * Interrupt source definitions - Event Source Core Event Name -Core Emulation ** - Events (highest priority) EMU 0 - Reset RST 1 - NMI NMI 2 - Exception EVX 3 - Reserved -- 4 - Hardware Error IVHW 5 - Core Timer IVTMR 6 * - -..... - - Software Interrupt 1 IVG14 31 - Software Interrupt 2 -- - (lowest priority) IVG15 32 * + * Event Source Core Event Name + * Core Emulation ** + * Events (highest priority) EMU 0 + * Reset RST 1 + * NMI NMI 2 + * Exception EVX 3 + * Reserved -- 4 + * Hardware Error IVHW 5 + * Core Timer IVTMR 6 + * ..... + * + * Softirq IVG14 + * System Call -- + * (lowest priority) IVG15 */ -#define SYS_IRQS 41 +#define SYS_IRQS 39 #define NR_PERI_INTS 32 /* The ABSTRACT IRQ definitions */ @@ -95,10 +94,8 @@ Core Emulation ** #define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */ #define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */ #define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */ -#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */ +#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */ #define IRQ_WATCH 38 /*Watch Dog Timer */ -#define IRQ_SW_INT1 40 /*Software Int 1 */ -#define IRQ_SW_INT2 41 /*Software Int 2 (reserved for SYSCALL) */ #define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */ #define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */ diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h index 83f0383957d..6698389c556 100644 --- a/include/asm-blackfin/mach-bf561/irq.h +++ b/include/asm-blackfin/mach-bf561/irq.h @@ -118,12 +118,13 @@ Supplemental interrupt 0 IVG7 69 supplemental interrupt 1 IVG7 70 - Software Interrupt 1 IVG14 71 - Software Interrupt 2 IVG15 72 * - (lowest priority) + Softirq IVG14 + System Call -- + (lowest priority) IVG15 + **********************************************************************/ -#define SYS_IRQS 72 +#define SYS_IRQS 71 #define NR_PERI_INTS 64 /* @@ -237,9 +238,7 @@ #define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */ #define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */ #define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */ -#define IRQ_SW_INT1 71 /* Software Interrupt 1 */ -#define IRQ_SW_INT2 72 /* Software Interrupt 2 */ - /* reserved for SYSCALL */ + #define IRQ_PF0 73 #define IRQ_PF1 74 #define IRQ_PF2 75 -- cgit v1.2.3 From 89bf6dc51ac7adb5a7d443648d9eb76909a1df8e Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 7 May 2008 11:41:26 +0800 Subject: Blackfin Serial Driver: macro away the IER differences between processors Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf527/bfin_serial_5xx.h | 2 ++ include/asm-blackfin/mach-bf533/bfin_serial_5xx.h | 2 ++ include/asm-blackfin/mach-bf537/bfin_serial_5xx.h | 2 ++ include/asm-blackfin/mach-bf561/bfin_serial_5xx.h | 2 ++ 4 files changed, 8 insertions(+) (limited to 'include') diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h index f0ab2736a68..1bbfc2d75bd 100644 --- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h @@ -44,6 +44,8 @@ #define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v) #define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v) #define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v) +#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) +#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) #define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v) #define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v) #define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v) diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h index fbe88dee3e2..d22f052d6c8 100644 --- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h @@ -44,6 +44,8 @@ #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) #define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) +#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) +#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) #define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h index fd100a415b9..ae2362c0bf9 100644 --- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h @@ -44,6 +44,8 @@ #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) #define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) +#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) +#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) #define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h index 8a4e66d1db3..c209f0df47f 100644 --- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h @@ -44,6 +44,8 @@ #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v) #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v) #define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v) +#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v)) +#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v)) #define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v) #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) -- cgit v1.2.3 From 45828b812ddb608ddf83eff11601f62b726d13ab Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 7 May 2008 11:41:26 +0800 Subject: Blackfin Serial Driver: abstract away DLAB differences into header Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf527/bfin_serial_5xx.h | 3 +++ include/asm-blackfin/mach-bf533/bfin_serial_5xx.h | 3 +++ include/asm-blackfin/mach-bf537/bfin_serial_5xx.h | 3 +++ include/asm-blackfin/mach-bf548/bfin_serial_5xx.h | 3 +++ include/asm-blackfin/mach-bf561/bfin_serial_5xx.h | 3 +++ 5 files changed, 15 insertions(+) (limited to 'include') diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h index 1bbfc2d75bd..26e3c8076b4 100644 --- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h @@ -50,6 +50,9 @@ #define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v) #define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v) +#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) +#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) + #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) # define CONFIG_SERIAL_BFIN_CTSRTS diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h index d22f052d6c8..d016603b661 100644 --- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h @@ -50,6 +50,9 @@ #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) +#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) +#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) + #ifdef CONFIG_BFIN_UART0_CTSRTS # define CONFIG_SERIAL_BFIN_CTSRTS # ifndef CONFIG_UART0_CTS_PIN diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h index ae2362c0bf9..f79d1a0e912 100644 --- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h @@ -50,6 +50,9 @@ #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) +#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) +#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) + #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) # define CONFIG_SERIAL_BFIN_CTSRTS diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h index 6547027cd3e..5eb46a77d91 100644 --- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h @@ -54,6 +54,9 @@ #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) #define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v) +#define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */ +#define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */ + #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) # define CONFIG_SERIAL_BFIN_CTSRTS diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h index c209f0df47f..7a962876929 100644 --- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h +++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h @@ -50,6 +50,9 @@ #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v) #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v) +#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0) +#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0) + #ifdef CONFIG_BFIN_UART0_CTSRTS # define CONFIG_SERIAL_BFIN_CTSRTS # ifndef CONFIG_UART0_CTS_PIN -- cgit v1.2.3