From 7e36e2f5355ab87f8946041d044b34cda01e2077 Mon Sep 17 00:00:00 2001 From: Rod Whitby Date: Tue, 1 Apr 2008 10:53:23 +0100 Subject: [ARM] 4874/2: ixp4xx: Add support for the Freecom FSG-3 board The Freecom-FSG3 is a small network-attached-storage device with the following feature set: * Intel IXP422 * 4MB Flash (ixp4xx flash driver) * 64MB RAM * 4 USB 2.0 host ports (ehci and ohci drivers) * 1 WAN (eth1) and 3 LAN (eth0) ethernet ports * Supported by the open source ixp4xx ethernet driver * Via VT6421 disk controller (libata and sata-via drivers) * Internal hard disk (PATA supported, SATA not yet supported) * External SATA port (not yet supported) * ISL1208 RTC chip * Winbond 83782 temp sensor and fan controller * MiniPCI slot The ixp4xx_defconfig is also updated to support this device (the leds-fsg driver is to be submitted separately via the leds tree after this initial support is merged, as it depends on header gpio defines). Signed-off-by: Rod Whitby Signed-off-by: Russell King --- include/asm-arm/arch-ixp4xx/fsg.h | 50 ++++++++++++++++++++++++++++++++++ include/asm-arm/arch-ixp4xx/hardware.h | 1 + include/asm-arm/arch-ixp4xx/irqs.h | 7 +++++ 3 files changed, 58 insertions(+) create mode 100644 include/asm-arm/arch-ixp4xx/fsg.h (limited to 'include') diff --git a/include/asm-arm/arch-ixp4xx/fsg.h b/include/asm-arm/arch-ixp4xx/fsg.h new file mode 100644 index 00000000000..c0100cc7981 --- /dev/null +++ b/include/asm-arm/arch-ixp4xx/fsg.h @@ -0,0 +1,50 @@ +/* + * include/asm-arm/arch-ixp4xx/fsg.h + * + * Freecom FSG-3 platform specific definitions + * + * Author: Rod Whitby + * Author: Tomasz Chmielewski + * Maintainers: http://www.nslu2-linux.org + * + * Based on coyote.h by + * Copyright 2004 (c) MontaVista, Software, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_HARDWARE_H__ +#error "Do not include this directly, instead #include " +#endif + +#define FSG_SDA_PIN 12 +#define FSG_SCL_PIN 13 + +/* + * FSG PCI IRQs + */ +#define FSG_PCI_MAX_DEV 3 +#define FSG_PCI_IRQ_LINES 3 + + +/* PCI controller GPIO to IRQ pin mappings */ +#define FSG_PCI_INTA_PIN 6 +#define FSG_PCI_INTB_PIN 7 +#define FSG_PCI_INTC_PIN 5 + +/* Buttons */ + +#define FSG_SB_GPIO 4 /* sync button */ +#define FSG_RB_GPIO 9 /* reset button */ +#define FSG_UB_GPIO 10 /* usb button */ + +/* LEDs */ + +#define FSG_LED_WLAN_BIT 0 +#define FSG_LED_WAN_BIT 1 +#define FSG_LED_SATA_BIT 2 +#define FSG_LED_USB_BIT 4 +#define FSG_LED_RING_BIT 5 +#define FSG_LED_SYNC_BIT 7 diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h index 73e8dc36f6a..fa723a62785 100644 --- a/include/asm-arm/arch-ixp4xx/hardware.h +++ b/include/asm-arm/arch-ixp4xx/hardware.h @@ -45,5 +45,6 @@ #include "nslu2.h" #include "nas100d.h" #include "dsmg600.h" +#include "fsg.h" #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-ixp4xx/irqs.h b/include/asm-arm/arch-ixp4xx/irqs.h index 11801605047..674af4a8414 100644 --- a/include/asm-arm/arch-ixp4xx/irqs.h +++ b/include/asm-arm/arch-ixp4xx/irqs.h @@ -128,4 +128,11 @@ #define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7 #define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6 +/* + * Freecom FSG-3 Board IRQs + */ +#define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6 +#define IRQ_FSG_PCI_INTB IRQ_IXP4XX_GPIO7 +#define IRQ_FSG_PCI_INTC IRQ_IXP4XX_GPIO5 + #endif -- cgit v1.2.3 From 205bee6ad804d7034773b5978c74dde495df2301 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 20 Apr 2008 13:57:26 +0100 Subject: [ARM] dyntick: Remove obsolete and unused ARM dyntick support dyntick is superseded by the clocksource/clockevent infrastructure, using the NO_HZ configuration option. No one implements dyntick on ARM anymore, so it's pointless keeping it around. Remove dyntick support. Signed-off-by: Russell King --- include/asm-arm/dyntick.h | 6 ------ include/asm-arm/hw_irq.h | 11 ----------- include/asm-arm/mach/time.h | 22 ---------------------- 3 files changed, 39 deletions(-) delete mode 100644 include/asm-arm/dyntick.h (limited to 'include') diff --git a/include/asm-arm/dyntick.h b/include/asm-arm/dyntick.h deleted file mode 100644 index 19fab2d2b76..00000000000 --- a/include/asm-arm/dyntick.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASMARM_DYNTICK_H -#define _ASMARM_DYNTICK_H - -#include - -#endif /* _ASMARM_DYNTICK_H */ diff --git a/include/asm-arm/hw_irq.h b/include/asm-arm/hw_irq.h index 98d594a973d..f1a08a50060 100644 --- a/include/asm-arm/hw_irq.h +++ b/include/asm-arm/hw_irq.h @@ -6,15 +6,4 @@ #include -#if defined(CONFIG_NO_IDLE_HZ) -# include -# define handle_dynamic_tick(action) \ - if (!(action->flags & IRQF_TIMER) && system_timer->dyn_tick) { \ - write_seqlock(&xtime_lock); \ - if (system_timer->dyn_tick->state & DYN_TICK_ENABLED) \ - system_timer->dyn_tick->handler(irq, NULL); \ - write_sequnlock(&xtime_lock); \ - } -#endif - #endif diff --git a/include/asm-arm/mach/time.h b/include/asm-arm/mach/time.h index 5dc357013b7..2fd36ea0130 100644 --- a/include/asm-arm/mach/time.h +++ b/include/asm-arm/mach/time.h @@ -41,30 +41,8 @@ struct sys_timer { #ifndef CONFIG_GENERIC_TIME unsigned long (*offset)(void); #endif - -#ifdef CONFIG_NO_IDLE_HZ - struct dyn_tick_timer *dyn_tick; -#endif -}; - -#ifdef CONFIG_NO_IDLE_HZ - -#define DYN_TICK_ENABLED (1 << 1) - -struct dyn_tick_timer { - spinlock_t lock; - unsigned int state; /* Current state */ - int (*enable)(void); /* Enables dynamic tick */ - int (*disable)(void); /* Disables dynamic tick */ - void (*reprogram)(unsigned long); /* Reprograms the timer */ - int (*handler)(int, void *); }; -void timer_dyn_reprogram(void); -#else -#define timer_dyn_reprogram() do { } while (0) -#endif - extern struct sys_timer *system_timer; extern void timer_tick(void); -- cgit v1.2.3 From bedd78ca786c1d18c2a2785c7e40593dc9c9870f Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 20 Apr 2008 12:31:29 +0100 Subject: [RTC] remove old ARM rtc library code Now that all drivers using it are gone, remove the old ARM RTC library. Acked-by: Alessandro Zummo Signed-off-by: Russell King --- include/asm-arm/rtc.h | 43 ------------------------------------------- 1 file changed, 43 deletions(-) delete mode 100644 include/asm-arm/rtc.h (limited to 'include') diff --git a/include/asm-arm/rtc.h b/include/asm-arm/rtc.h deleted file mode 100644 index 1a5c9232a91..00000000000 --- a/include/asm-arm/rtc.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * linux/include/asm-arm/rtc.h - * - * Copyright (C) 2003 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef ASMARM_RTC_H -#define ASMARM_RTC_H - -struct module; - -struct rtc_ops { - struct module *owner; - int (*open)(void); - void (*release)(void); - int (*ioctl)(unsigned int, unsigned long); - - int (*read_time)(struct rtc_time *); - int (*set_time)(struct rtc_time *); - int (*read_alarm)(struct rtc_wkalrm *); - int (*set_alarm)(struct rtc_wkalrm *); - int (*proc)(char *buf); -}; - -void rtc_next_alarm_time(struct rtc_time *, struct rtc_time *, struct rtc_time *); -void rtc_update(unsigned long, unsigned long); -int register_rtc(struct rtc_ops *); -void unregister_rtc(struct rtc_ops *); - -static inline int rtc_periodic_alarm(struct rtc_time *tm) -{ - return (tm->tm_year == -1) || - ((unsigned)tm->tm_mon >= 12) || - ((unsigned)(tm->tm_mday - 1) >= 31) || - ((unsigned)tm->tm_hour > 23) || - ((unsigned)tm->tm_min > 59) || - ((unsigned)tm->tm_sec > 59); -} - -#endif -- cgit v1.2.3 From ca0a789ab9c83d8fdf28f5c2700b316cd5dec2f0 Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Sat, 24 May 2008 17:47:04 +0100 Subject: [ARM] 5057/1: [AT91] Calao Systems - board files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for three AT91-based boards available from Calao Systems: USB_A9260, USB_A9263 and QIL_A9260. Signed-off-by: Grégory Hermant Signed-off-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/arch-at91/timex.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h index f1933b0fa43..6e084eb839d 100644 --- a/include/asm-arm/arch-at91/timex.h +++ b/include/asm-arm/arch-at91/timex.h @@ -27,14 +27,29 @@ #define CLOCK_TICK_RATE (AT91_SLOW_CLOCK) -#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261) +#elif defined(CONFIG_ARCH_AT91SAM9260) + +#if defined(CONFIG_MACH_USB_A9260) || defined(CONFIG_MACH_QIL_A9260) +#define AT91SAM9_MASTER_CLOCK 90000000 +#else +#define AT91SAM9_MASTER_CLOCK 99300000 +#endif + +#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) + +#elif defined(CONFIG_ARCH_AT91SAM9261) #define AT91SAM9_MASTER_CLOCK 99300000 #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) #elif defined(CONFIG_ARCH_AT91SAM9263) +#if defined(CONFIG_MACH_USB_A9263) +#define AT91SAM9_MASTER_CLOCK 90000000 +#else #define AT91SAM9_MASTER_CLOCK 99959500 +#endif + #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) #elif defined(CONFIG_ARCH_AT91SAM9RL) -- cgit v1.2.3 From 53d7168026a440c4cba25468a3d926ddd7ab030a Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Sat, 5 Apr 2008 21:14:03 +0100 Subject: [ARM] 4933/1: AT91CAP9 UDPHS driver: generic AT91 parts. This is patch 1 of 2 adding support for the USB High Speed Device Port on the AT91CAP9 system on chip. The AT91CAP9 uses the same UDPHS IP as the AVR32 and the AT91SAM9RL. This patch makes the generic AT91 adaptations, mainly dealing with the addition of the UDPHS UTMI clock. Signed-off-by: Stelian Pop Acked-by: Haavard Skinnemoen Acked-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/arch-at91/at91_pmc.h | 7 ++++++- include/asm-arm/arch-at91/board.h | 4 ++++ 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h index c2b13c28015..2001e81f226 100644 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ b/include/asm-arm/arch-at91/at91_pmc.h @@ -39,10 +39,14 @@ #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ +#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ +#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ +#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ +#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ -#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */ +#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ @@ -97,6 +101,7 @@ #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ +#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */ #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h index dc189f01c5b..1f247028686 100644 --- a/include/asm-arm/arch-at91/board.h +++ b/include/asm-arm/arch-at91/board.h @@ -36,6 +36,7 @@ #include #include #include +#include /* USB Device */ struct at91_udc_data { @@ -45,6 +46,9 @@ struct at91_udc_data { }; extern void __init at91_add_device_udc(struct at91_udc_data *data); + /* USB High Speed Device */ +extern void __init at91_add_device_usba(struct usba_platform_data *data); + /* Compact Flash */ struct at91_cf_data { u8 irq_pin; /* I/O IRQ */ -- cgit v1.2.3 From 7c8cf66529ebf95f1a5f34d1b69504d442b42630 Mon Sep 17 00:00:00 2001 From: Stelian Pop Date: Sat, 5 Apr 2008 21:15:25 +0100 Subject: [ARM] 4934/1: AT91CAP9 UDPHS driver: board and cpu integration. This is patch 2 of 2 adding support for the USB High Speed Device Port on the AT91CAP9 system on chip. The AT91CAP9 uses the same UDPHS IP as the AVR32 and the AT91SAM9RL. This patch declares the UDPHS ressources in the at91cap9 (cpu and adk board) files, wires up the atmel_usba_udc driver to them, and activates the driver in the defconfig. Signed-off-by: Stelian Pop Acked-by: Haavard Skinnemoen Acked-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/arch-at91/at91cap9.h | 2 +- include/asm-arm/arch-at91/at91cap9_matrix.h | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h index bac83adb505..6f14d9053ac 100644 --- a/include/asm-arm/arch-at91/at91cap9.h +++ b/include/asm-arm/arch-at91/at91cap9.h @@ -118,7 +118,7 @@ #define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */ #define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */ -#define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */ +#define AT91CAP9_UDPHS_FIFO 0x00600000 /* USB High Speed Device Port */ #define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */ #define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 diff --git a/include/asm-arm/arch-at91/at91cap9_matrix.h b/include/asm-arm/arch-at91/at91cap9_matrix.h index a641686b6c3..ddbd4873c84 100644 --- a/include/asm-arm/arch-at91/at91cap9_matrix.h +++ b/include/asm-arm/arch-at91/at91cap9_matrix.h @@ -106,6 +106,11 @@ #define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */ #define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */ +#define AT91_MATRIX_UDPHS (AT91_MATRIX + 0x118) /* USBHS Special Function Register [AT91CAP9 only] */ +#define AT91_MATRIX_SELECT_UDPHS (0 << 31) /* select High Speed UDP */ +#define AT91_MATRIX_SELECT_UDP (1 << 31) /* select standard UDP */ +#define AT91_MATRIX_UDPHS_BYPASS_LOCK (1 << 30) /* bypass lock bit */ + #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */ #define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) -- cgit v1.2.3 From ba45ca435060614e595a107ac323a36b52619d7d Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Tue, 8 Apr 2008 13:59:18 +0100 Subject: [ARM] 4940/1: AT91: UDPHS driver: SAM9RL board and cpu integration. Adds support for the USB High Speed Device Port on the AT91SAM9RL system on chip. The AT91SAM9RL uses the same UDPHS IP as the AVR32 and the AT91CAP9 (atmel_usba_udc driver). Signed-off-by: Nicolas Ferre Acked-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/arch-at91/at91sam9rl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h index 16d2832f6c0..622e56f81d4 100644 --- a/include/asm-arm/arch-at91/at91sam9rl.h +++ b/include/asm-arm/arch-at91/at91sam9rl.h @@ -110,6 +110,6 @@ #define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ #define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ -#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */ +#define AT91SAM9RL_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ #endif -- cgit v1.2.3 From 2239aff6ab2b95af1f628eee7a809f21c41605b3 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Mon, 31 Mar 2008 12:38:31 -0400 Subject: [ARM] cache align destination pointer when copying memory for some processors The implementation for memory copy functions on ARM had a (disabled) provision for aligning the source pointer before loading registers with data. Turns out that aligning the _destination_ pointer is much more useful, as the read side is already sufficiently helped with the use of preload. So this changes the definition of the CALGN() macro to target the destination pointer instead, and turns it on for Feroceon processors where the gain is very noticeable. Signed-off-by: Nicolas Pitre Signed-off-by: Lennert Buytenhek --- include/asm-arm/assembler.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'include') diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h index fce83282082..911393b2c6f 100644 --- a/include/asm-arm/assembler.h +++ b/include/asm-arm/assembler.h @@ -55,6 +55,21 @@ #define PLD(code...) #endif +/* + * This can be used to enable code to cacheline align the destination + * pointer when bulk writing to memory. Experiments on StrongARM and + * XScale didn't show this a worthwhile thing to do when the cache is not + * set to write-allocate (this would need further testing on XScale when WA + * is used). + * + * On Feroceon there is much to gain however, regardless of cache mode. + */ +#ifdef CONFIG_CPU_FEROCEON +#define CALGN(code...) code +#else +#define CALGN(code...) +#endif + /* * Enable and disable interrupts */ -- cgit v1.2.3 From 6eef84a5496c678ab27b72bec0fc785c9cee063b Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Wed, 28 May 2008 16:20:56 +0200 Subject: [ARM] Orion: delete unused IO_SPACE_REMAP define This define isn't used anywhere in the kernel tree -- nuke it. Signed-off-by: Lennert Buytenhek Acked-by: Russell King --- include/asm-arm/arch-orion5x/io.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/asm-arm/arch-orion5x/io.h b/include/asm-arm/arch-orion5x/io.h index 50f8c880220..d9a4b2065e5 100644 --- a/include/asm-arm/arch-orion5x/io.h +++ b/include/asm-arm/arch-orion5x/io.h @@ -14,7 +14,6 @@ #include "orion5x.h" #define IO_SPACE_LIMIT 0xffffffff -#define IO_SPACE_REMAP ORION5X_PCI_SYS_IO_BASE static inline void __iomem * __arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype) -- cgit v1.2.3 From d2b2a6bbc020e5a9a244f318d28515081e922882 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Sat, 31 May 2008 08:30:40 +0200 Subject: [ARM] Orion: add 88F5181L (Orion-VoIP) support Signed-off-by: Lennert Buytenhek Acked-by: Russell King --- include/asm-arm/arch-orion5x/orion5x.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h index 206ddd71e19..20f7b406a79 100644 --- a/include/asm-arm/arch-orion5x/orion5x.h +++ b/include/asm-arm/arch-orion5x/orion5x.h @@ -2,7 +2,7 @@ * include/asm-arm/arch-orion5x/orion5x.h * * Generic definitions of Orion SoC flavors: - * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2. + * Orion-1, Orion-VoIP, Orion-NAS, and Orion-2. * * Maintainer: Tzachi Perelstein * @@ -63,9 +63,11 @@ /******************************************************************************* * Supported Devices & Revisions ******************************************************************************/ -/* Orion-1 (88F5181) */ +/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ #define MV88F5181_DEV_ID 0x5181 #define MV88F5181_REV_B1 3 +#define MV88F5181L_REV_A0 8 +#define MV88F5181L_REV_A1 9 /* Orion-NAS (88F5182) */ #define MV88F5182_DEV_ID 0x5182 #define MV88F5182_REV_A2 2 -- cgit v1.2.3 From 0e3bc0503f7e7b5b0bd4416f43eeeca1b661e66e Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Wed, 4 Jun 2008 03:16:21 +0200 Subject: [ARM] Orion: use linux/serial_reg.h for Orion uncompress.h Signed-off-by: Lennert Buytenhek --- include/asm-arm/arch-orion5x/uncompress.h | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-orion5x/uncompress.h b/include/asm-arm/arch-orion5x/uncompress.h index 5c13d4fafb4..7548cedf2d7 100644 --- a/include/asm-arm/arch-orion5x/uncompress.h +++ b/include/asm-arm/arch-orion5x/uncompress.h @@ -8,23 +8,38 @@ * warranty of any kind, whether express or implied. */ +#include #include -#define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0)) -#define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14)) - -#define LSR_THRE 0x20 +#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE) static void putc(const char c) { - int j = 0x1000; - while (--j && !(*MV_UART_LSR & LSR_THRE)) + unsigned char *base = SERIAL_BASE; + int i; + + for (i = 0; i < 0x1000; i++) { + if (base[UART_LSR << 2] & UART_LSR_THRE) + break; barrier(); - *MV_UART_THR = c; + } + + base[UART_TX << 2] = c; } static void flush(void) { + unsigned char *base = SERIAL_BASE; + unsigned char mask; + int i; + + mask = UART_LSR_TEMT | UART_LSR_THRE; + + for (i = 0; i < 0x1000; i++) { + if ((base[UART_LSR << 2] & mask) == mask) + break; + barrier(); + } } /* -- cgit v1.2.3 From 79e90dd5aa95adfdc3117db8a559da3d0195ba58 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Wed, 28 May 2008 16:43:48 +0200 Subject: [ARM] Orion: nuke orion5x_{read,write} Nuke the Orion-specific orion5x_{read,write} wrappers. Signed-off-by: Lennert Buytenhek --- include/asm-arm/arch-orion5x/io.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-orion5x/io.h b/include/asm-arm/arch-orion5x/io.h index d9a4b2065e5..59f1bc96a23 100644 --- a/include/asm-arm/arch-orion5x/io.h +++ b/include/asm-arm/arch-orion5x/io.h @@ -52,15 +52,12 @@ static inline void __iomem *__io(unsigned long addr) /***************************************************************************** * Helpers to access Orion registers ****************************************************************************/ -#define orion5x_read(r) __raw_readl(r) -#define orion5x_write(r, val) __raw_writel(val, r) - /* * These are not preempt-safe. Locks, if needed, must be taken * care of by the caller. */ -#define orion5x_setbits(r, mask) orion5x_write((r), orion5x_read(r) | (mask)) -#define orion5x_clrbits(r, mask) orion5x_write((r), orion5x_read(r) & ~(mask)) +#define orion5x_setbits(r, mask) writel(readl(r) | (mask), (r)) +#define orion5x_clrbits(r, mask) writel(readl(r) & ~(mask), (r)) #endif -- cgit v1.2.3 From 1219715de70956557b9dedf3ee021a73d4f4ec52 Mon Sep 17 00:00:00 2001 From: Ke Wei Date: Fri, 23 May 2008 10:23:22 +0200 Subject: [ARM] Orion: add a separate BRIDGE_INT_TIMER1_CLR define Some Feroceon-based SoCs have an MBUS bridge interrupt controller that requires writing a one instead of a zero to clear edge interrupt sources such as timer expiry. This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform. Signed-off-by: Lennert Buytenhek --- include/asm-arm/arch-orion5x/orion5x.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h index 20f7b406a79..10257f5c5e9 100644 --- a/include/asm-arm/arch-orion5x/orion5x.h +++ b/include/asm-arm/arch-orion5x/orion5x.h @@ -154,6 +154,7 @@ #define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) #define BRIDGE_INT_TIMER0 0x0002 #define BRIDGE_INT_TIMER1 0x0004 +#define BRIDGE_INT_TIMER1_CLR (~0x0004) #define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200) #define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204) -- cgit v1.2.3 From 777f9bebad3476b7dbf5cd8abbd3414139ca0e48 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Sun, 22 Jun 2008 22:45:02 +0200 Subject: [ARM] add Marvell Loki (88RC8480) SoC support The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU core running at between 400 MHz and 1.0 GHz, and features a 64 bit DDR controller, 512K of internal SRAM, two x4 PCI-Express ports, two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs, two TWSI controllers, and IDMA/XOR engines. This patch adds support for the Marvell LB88RC8480 Development Board, enabling the use of the PCIe interfaces, the ethernet interfaces, the TWSI interfaces and the UARTs. Signed-off-by: Lennert Buytenhek --- include/asm-arm/arch-loki/debug-macro.S | 20 +++++++ include/asm-arm/arch-loki/dma.h | 1 + include/asm-arm/arch-loki/entry-macro.S | 30 ++++++++++ include/asm-arm/arch-loki/hardware.h | 15 +++++ include/asm-arm/arch-loki/io.h | 26 +++++++++ include/asm-arm/arch-loki/irqs.h | 58 ++++++++++++++++++++ include/asm-arm/arch-loki/loki.h | 97 +++++++++++++++++++++++++++++++++ include/asm-arm/arch-loki/memory.h | 14 +++++ include/asm-arm/arch-loki/system.h | 37 +++++++++++++ include/asm-arm/arch-loki/timex.h | 11 ++++ include/asm-arm/arch-loki/uncompress.h | 47 ++++++++++++++++ include/asm-arm/arch-loki/vmalloc.h | 5 ++ 12 files changed, 361 insertions(+) create mode 100644 include/asm-arm/arch-loki/debug-macro.S create mode 100644 include/asm-arm/arch-loki/dma.h create mode 100644 include/asm-arm/arch-loki/entry-macro.S create mode 100644 include/asm-arm/arch-loki/hardware.h create mode 100644 include/asm-arm/arch-loki/io.h create mode 100644 include/asm-arm/arch-loki/irqs.h create mode 100644 include/asm-arm/arch-loki/loki.h create mode 100644 include/asm-arm/arch-loki/memory.h create mode 100644 include/asm-arm/arch-loki/system.h create mode 100644 include/asm-arm/arch-loki/timex.h create mode 100644 include/asm-arm/arch-loki/uncompress.h create mode 100644 include/asm-arm/arch-loki/vmalloc.h (limited to 'include') diff --git a/include/asm-arm/arch-loki/debug-macro.S b/include/asm-arm/arch-loki/debug-macro.S new file mode 100644 index 00000000000..585502e9651 --- /dev/null +++ b/include/asm-arm/arch-loki/debug-macro.S @@ -0,0 +1,20 @@ +/* + * include/asm-arm/arch-loki/debug-macro.S + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =LOKI_REGS_PHYS_BASE + ldrne \rx, =LOKI_REGS_VIRT_BASE + orr \rx, \rx, #0x00012000 + .endm + +#define UART_SHIFT 2 +#include diff --git a/include/asm-arm/arch-loki/dma.h b/include/asm-arm/arch-loki/dma.h new file mode 100644 index 00000000000..40a8c178f10 --- /dev/null +++ b/include/asm-arm/arch-loki/dma.h @@ -0,0 +1 @@ +/* empty */ diff --git a/include/asm-arm/arch-loki/entry-macro.S b/include/asm-arm/arch-loki/entry-macro.S new file mode 100644 index 00000000000..693257cdbeb --- /dev/null +++ b/include/asm-arm/arch-loki/entry-macro.S @@ -0,0 +1,30 @@ +/* + * include/asm-arm/arch-loki/entry-macro.S + * + * Low-level IRQ helper macros for Marvell Loki (88RC8480) platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include + + .macro disable_fiq + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =IRQ_VIRT_BASE + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \irqstat, [\base, #IRQ_CAUSE_OFF] + ldr \tmp, [\base, #IRQ_MASK_OFF] + mov \irqnr, #0 + ands \irqstat, \irqstat, \tmp + clzne \irqnr, \irqstat + rsbne \irqnr, \irqnr, #31 + .endm diff --git a/include/asm-arm/arch-loki/hardware.h b/include/asm-arm/arch-loki/hardware.h new file mode 100644 index 00000000000..f65b01c733b --- /dev/null +++ b/include/asm-arm/arch-loki/hardware.h @@ -0,0 +1,15 @@ +/* + * include/asm-arm/arch-loki/hardware.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include "loki.h" + + +#endif diff --git a/include/asm-arm/arch-loki/io.h b/include/asm-arm/arch-loki/io.h new file mode 100644 index 00000000000..e7418a915e7 --- /dev/null +++ b/include/asm-arm/arch-loki/io.h @@ -0,0 +1,26 @@ +/* + * include/asm-arm/arch-loki/io.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#include "loki.h" + +#define IO_SPACE_LIMIT 0xffffffff + +static inline void __iomem *__io(unsigned long addr) +{ + return (void __iomem *)((addr - LOKI_PCIE0_IO_PHYS_BASE) + + LOKI_PCIE0_IO_VIRT_BASE); +} + +#define __io(a) __io(a) +#define __mem_pci(a) (a) + + +#endif diff --git a/include/asm-arm/arch-loki/irqs.h b/include/asm-arm/arch-loki/irqs.h new file mode 100644 index 00000000000..7e497143807 --- /dev/null +++ b/include/asm-arm/arch-loki/irqs.h @@ -0,0 +1,58 @@ +/* + * include/asm-arm/arch-loki/irqs.h + * + * IRQ definitions for Marvell Loki (88RC8480) SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +#include "loki.h" /* need GPIO_MAX */ + +/* + * Interrupt Controller + */ +#define IRQ_LOKI_PCIE_A_CPU_DRBL 0 +#define IRQ_LOKI_CPU_PCIE_A_DRBL 1 +#define IRQ_LOKI_PCIE_B_CPU_DRBL 2 +#define IRQ_LOKI_CPU_PCIE_B_DRBL 3 +#define IRQ_LOKI_COM_A_ERR 6 +#define IRQ_LOKI_COM_A_IN 7 +#define IRQ_LOKI_COM_A_OUT 8 +#define IRQ_LOKI_COM_B_ERR 9 +#define IRQ_LOKI_COM_B_IN 10 +#define IRQ_LOKI_COM_B_OUT 11 +#define IRQ_LOKI_DMA_A 12 +#define IRQ_LOKI_DMA_B 13 +#define IRQ_LOKI_SAS_A 14 +#define IRQ_LOKI_SAS_B 15 +#define IRQ_LOKI_DDR 16 +#define IRQ_LOKI_XOR 17 +#define IRQ_LOKI_BRIDGE 18 +#define IRQ_LOKI_PCIE_A_ERR 20 +#define IRQ_LOKI_PCIE_A_INT 21 +#define IRQ_LOKI_PCIE_B_ERR 22 +#define IRQ_LOKI_PCIE_B_INT 23 +#define IRQ_LOKI_GBE_A_INT 24 +#define IRQ_LOKI_GBE_B_INT 25 +#define IRQ_LOKI_DEV_ERR 26 +#define IRQ_LOKI_UART0 27 +#define IRQ_LOKI_UART1 28 +#define IRQ_LOKI_TWSI 29 +#define IRQ_LOKI_GPIO_23_0 30 +#define IRQ_LOKI_GPIO_25_24 31 + +/* + * Loki General Purpose Pins + */ +#define IRQ_LOKI_GPIO_START 32 +#define NR_GPIO_IRQS GPIO_MAX + +#define NR_IRQS (IRQ_LOKI_GPIO_START + NR_GPIO_IRQS) + + +#endif diff --git a/include/asm-arm/arch-loki/loki.h b/include/asm-arm/arch-loki/loki.h new file mode 100644 index 00000000000..5dd05ee0a4e --- /dev/null +++ b/include/asm-arm/arch-loki/loki.h @@ -0,0 +1,97 @@ +/* + * include/asm-arm/arch-loki/loki.h + * + * Generic definitions for Marvell Loki (88RC8480) SoC flavors + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_LOKI_H +#define __ASM_ARCH_LOKI_H + +/* + * Marvell Loki (88RC8480) address maps. + * + * phys + * d0000000 on-chip peripheral registers + * e0000000 PCIe 0 Memory space + * e8000000 PCIe 1 Memory space + * f0000000 PCIe 0 I/O space + * f0100000 PCIe 1 I/O space + * + * virt phys size + * fed00000 d0000000 1M on-chip peripheral registers + * fee00000 f0000000 64K PCIe 0 I/O space + * fef00000 f0100000 64K PCIe 1 I/O space + */ + +#define LOKI_REGS_PHYS_BASE 0xd0000000 +#define LOKI_REGS_VIRT_BASE 0xfed00000 +#define LOKI_REGS_SIZE SZ_1M + +#define LOKI_PCIE0_IO_PHYS_BASE 0xf0000000 +#define LOKI_PCIE0_IO_VIRT_BASE 0xfee00000 +#define LOKI_PCIE0_IO_BUS_BASE 0x00000000 +#define LOKI_PCIE0_IO_SIZE SZ_64K + +#define LOKI_PCIE1_IO_PHYS_BASE 0xf0100000 +#define LOKI_PCIE1_IO_VIRT_BASE 0xfef00000 +#define LOKI_PCIE1_IO_BUS_BASE 0x00000000 +#define LOKI_PCIE1_IO_SIZE SZ_64K + +#define LOKI_PCIE0_MEM_PHYS_BASE 0xe0000000 +#define LOKI_PCIE0_MEM_SIZE SZ_128M + +#define LOKI_PCIE1_MEM_PHYS_BASE 0xe8000000 +#define LOKI_PCIE1_MEM_SIZE SZ_128M + +/* + * Register Map + */ +#define DEV_BUS_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x10000) +#define DEV_BUS_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x10000) +#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) +#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) +#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) +#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) + +#define BRIDGE_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x20000) +#define BRIDGE_REG(x) (BRIDGE_VIRT_BASE | (x)) +#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) +#define SOFT_RESET_OUT_EN 0x00000004 +#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) +#define SOFT_RESET 0x00000001 +#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) +#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) +#define BRIDGE_INT_TIMER0 0x0002 +#define BRIDGE_INT_TIMER1 0x0004 +#define BRIDGE_INT_TIMER1_CLR 0x0004 +#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) +#define IRQ_CAUSE_OFF 0x0000 +#define IRQ_MASK_OFF 0x0004 +#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) + +#define PCIE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x30000) + +#define PCIE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x40000) + +#define SAS0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x80000) + +#define SAS1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x90000) + +#define GE0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xa0000) +#define GE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xa0000) + +#define GE1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xb0000) +#define GE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xb0000) + +#define DDR_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xf0000) +#define DDR_REG(x) (DDR_VIRT_BASE | (x)) + + +#define GPIO_MAX 8 + + +#endif diff --git a/include/asm-arm/arch-loki/memory.h b/include/asm-arm/arch-loki/memory.h new file mode 100644 index 00000000000..835101e4987 --- /dev/null +++ b/include/asm-arm/arch-loki/memory.h @@ -0,0 +1,14 @@ +/* + * include/asm-arm/arch-loki/memory.h + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#define PHYS_OFFSET UL(0x00000000) + +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + + +#endif diff --git a/include/asm-arm/arch-loki/system.h b/include/asm-arm/arch-loki/system.h new file mode 100644 index 00000000000..a3568ac8ec3 --- /dev/null +++ b/include/asm-arm/arch-loki/system.h @@ -0,0 +1,37 @@ +/* + * include/asm-arm/arch-loki/system.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include +#include + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode) +{ + /* + * Enable soft reset to assert RSTOUTn. + */ + writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); + + /* + * Assert soft reset. + */ + writel(SOFT_RESET, SYSTEM_SOFT_RESET); + + while (1) + ; +} + + +#endif diff --git a/include/asm-arm/arch-loki/timex.h b/include/asm-arm/arch-loki/timex.h new file mode 100644 index 00000000000..940014f97ca --- /dev/null +++ b/include/asm-arm/arch-loki/timex.h @@ -0,0 +1,11 @@ +/* + * include/asm-arm/arch-loki/timex.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define CLOCK_TICK_RATE (100 * HZ) + +#define LOKI_TCLK 180000000 diff --git a/include/asm-arm/arch-loki/uncompress.h b/include/asm-arm/arch-loki/uncompress.h new file mode 100644 index 00000000000..89a0cf88d3a --- /dev/null +++ b/include/asm-arm/arch-loki/uncompress.h @@ -0,0 +1,47 @@ +/* + * include/asm-arm/arch-loki/uncompress.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include + +#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE) + +static void putc(const char c) +{ + unsigned char *base = SERIAL_BASE; + int i; + + for (i = 0; i < 0x1000; i++) { + if (base[UART_LSR << 2] & UART_LSR_THRE) + break; + barrier(); + } + + base[UART_TX << 2] = c; +} + +static void flush(void) +{ + unsigned char *base = SERIAL_BASE; + unsigned char mask; + int i; + + mask = UART_LSR_TEMT | UART_LSR_THRE; + + for (i = 0; i < 0x1000; i++) { + if ((base[UART_LSR << 2] & mask) == mask) + break; + barrier(); + } +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-loki/vmalloc.h b/include/asm-arm/arch-loki/vmalloc.h new file mode 100644 index 00000000000..f5be0622049 --- /dev/null +++ b/include/asm-arm/arch-loki/vmalloc.h @@ -0,0 +1,5 @@ +/* + * include/asm-arm/arch-loki/vmalloc.h + */ + +#define VMALLOC_END 0xfe800000 -- cgit v1.2.3 From 836a8051d54525e0782f156dcfa3c13d30f22840 Mon Sep 17 00:00:00 2001 From: Stanislav Samsonov Date: Tue, 3 Jun 2008 11:24:40 +0300 Subject: [ARM] Feroceon: L1 cache range operation support This patch adds support for the L1 D cache range operations that are supported by the Marvell Discovery Duo and Marvell Kirkwood ARM SoCs. Signed-off-by: Stanislav Samsonov Acked-by: Saeed Bishara Reviewed-by: Nicolas Pitre Signed-off-by: Lennert Buytenhek --- include/asm-arm/cacheflush.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'include') diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index 759a97b56ee..b85d426bb52 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -95,11 +95,7 @@ #endif #if defined(CONFIG_CPU_FEROCEON) -# ifdef _CACHE -# define MULTI_CACHE 1 -# else -# define _CACHE feroceon -# endif +# define MULTI_CACHE 1 #endif #if defined(CONFIG_CPU_V6) -- cgit v1.2.3 From 99c6dc117d27d6259214812bd0b113aaf467f600 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Sun, 22 Jun 2008 22:45:04 +0200 Subject: [ARM] Feroceon: L2 cache support This patch adds support for the unified Feroceon L2 cache controller as found in e.g. the Marvell Kirkwood and Marvell Discovery Duo families of ARM SoCs. Note that: - Page table walks are outer uncacheable on Kirkwood and Discovery Duo, since the ARMv5 spec provides no way to indicate outer cacheability of page table walks (specifying it in TTBR[4:3] is an ARMv6+ feature). This requires adding L2 cache clean instructions to proc-feroceon.S (dcache_clean_area(), set_pte()) as well as to tlbflush.h ({flush,clean}_pmd_entry()). The latter case is handled by defining a new TLB type (TLB_FEROCEON) which is almost identical to the v4wbi one but provides a TLB_L2CLEAN_FR flag. - The Feroceon L2 cache controller supports L2 range (i.e. 'clean L2 range by MVA' and 'invalidate L2 range by MVA') operations, and this patch uses those range operations for all Linux outer cache operations, as they are faster than the regular per-line operations. L2 range operations are not interruptible on this hardware, which avoids potential livelock issues, but can be bad for interrupt latency, so there is a compile-time tunable (MAX_RANGE_SIZE) which allows you to select the maximum range size to operate on at once. (Valid range is between one cache line and one 4KiB page, and must be a multiple of the line size.) Signed-off-by: Lennert Buytenhek --- include/asm-arm/plat-orion/cache-feroceon-l2.h | 11 ++++++++++ include/asm-arm/tlbflush.h | 30 ++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) create mode 100644 include/asm-arm/plat-orion/cache-feroceon-l2.h (limited to 'include') diff --git a/include/asm-arm/plat-orion/cache-feroceon-l2.h b/include/asm-arm/plat-orion/cache-feroceon-l2.h new file mode 100644 index 00000000000..ba4e016d3ec --- /dev/null +++ b/include/asm-arm/plat-orion/cache-feroceon-l2.h @@ -0,0 +1,11 @@ +/* + * include/asm-arm/plat-orion/cache-feroceon-l2.h + * + * Copyright (C) 2008 Marvell Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +extern void __init feroceon_l2_init(int l2_wt_override); diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h index 8c6bc1bb9d1..909656c747e 100644 --- a/include/asm-arm/tlbflush.h +++ b/include/asm-arm/tlbflush.h @@ -39,6 +39,7 @@ #define TLB_V6_D_ASID (1 << 17) #define TLB_V6_I_ASID (1 << 18) +#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */ #define TLB_DCLEAN (1 << 30) #define TLB_WB (1 << 31) @@ -51,6 +52,7 @@ * v4 - ARMv4 without write buffer * v4wb - ARMv4 with write buffer without I TLB flush entry instruction * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction + * fr - Feroceon (v4wbi with non-outer-cacheable page table walks) * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction */ #undef _TLB @@ -103,6 +105,23 @@ # define v4wbi_always_flags (-1UL) #endif +#define fr_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_L2CLEAN_FR | \ + TLB_V4_I_FULL | TLB_V4_D_FULL | \ + TLB_V4_I_PAGE | TLB_V4_D_PAGE) + +#ifdef CONFIG_CPU_TLB_FEROCEON +# define fr_possible_flags fr_tlb_flags +# define fr_always_flags fr_tlb_flags +# ifdef _TLB +# define MULTI_TLB 1 +# else +# define _TLB v4wbi +# endif +#else +# define fr_possible_flags 0 +# define fr_always_flags (-1UL) +#endif + #define v4wb_tlb_flags (TLB_WB | TLB_DCLEAN | \ TLB_V4_I_FULL | TLB_V4_D_FULL | \ TLB_V4_D_PAGE) @@ -245,12 +264,14 @@ extern struct cpu_tlb_fns cpu_tlb; #define possible_tlb_flags (v3_possible_flags | \ v4_possible_flags | \ v4wbi_possible_flags | \ + fr_possible_flags | \ v4wb_possible_flags | \ v6wbi_possible_flags) #define always_tlb_flags (v3_always_flags & \ v4_always_flags & \ v4wbi_always_flags & \ + fr_always_flags & \ v4wb_always_flags & \ v6wbi_always_flags) @@ -417,6 +438,11 @@ static inline void flush_pmd_entry(pmd_t *pmd) if (tlb_flag(TLB_DCLEAN)) asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" : : "r" (pmd) : "cc"); + + if (tlb_flag(TLB_L2CLEAN_FR)) + asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd" + : : "r" (pmd) : "cc"); + if (tlb_flag(TLB_WB)) dsb(); } @@ -428,6 +454,10 @@ static inline void clean_pmd_entry(pmd_t *pmd) if (tlb_flag(TLB_DCLEAN)) asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" : : "r" (pmd) : "cc"); + + if (tlb_flag(TLB_L2CLEAN_FR)) + asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd" + : : "r" (pmd) : "cc"); } #undef tlb_flag -- cgit v1.2.3 From 651c74c74bf84ba966b52588ba3329606f3fd8d4 Mon Sep 17 00:00:00 2001 From: Saeed Bishara Date: Sun, 22 Jun 2008 22:45:06 +0200 Subject: [ARM] add Marvell Kirkwood (88F6000) SoC support The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface, a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS interface, and IDMA/XOR engines, and depending on the model, also features one or two Gigabit Ethernet interfaces, two SATA II interfaces, one or two TWSI interfaces, one or two UARTs, a TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and an SDIO interface. This patch adds supports for the Marvell DB-88F6281-BP Development Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs, enabling support for the PCIe interface, the USB interface, the ethernet interfaces, the SATA interfaces, the TWSI interfaces, the UARTs, and the NAND controller. Signed-off-by: Saeed Bishara Signed-off-by: Lennert Buytenhek --- include/asm-arm/arch-kirkwood/debug-macro.S | 20 ++++++ include/asm-arm/arch-kirkwood/dma.h | 1 + include/asm-arm/arch-kirkwood/entry-macro.S | 40 ++++++++++++ include/asm-arm/arch-kirkwood/hardware.h | 21 ++++++ include/asm-arm/arch-kirkwood/io.h | 26 ++++++++ include/asm-arm/arch-kirkwood/irqs.h | 63 ++++++++++++++++++ include/asm-arm/arch-kirkwood/kirkwood.h | 99 +++++++++++++++++++++++++++++ include/asm-arm/arch-kirkwood/memory.h | 14 ++++ include/asm-arm/arch-kirkwood/system.h | 37 +++++++++++ include/asm-arm/arch-kirkwood/timex.h | 11 ++++ include/asm-arm/arch-kirkwood/uncompress.h | 47 ++++++++++++++ include/asm-arm/arch-kirkwood/vmalloc.h | 5 ++ 12 files changed, 384 insertions(+) create mode 100644 include/asm-arm/arch-kirkwood/debug-macro.S create mode 100644 include/asm-arm/arch-kirkwood/dma.h create mode 100644 include/asm-arm/arch-kirkwood/entry-macro.S create mode 100644 include/asm-arm/arch-kirkwood/hardware.h create mode 100644 include/asm-arm/arch-kirkwood/io.h create mode 100644 include/asm-arm/arch-kirkwood/irqs.h create mode 100644 include/asm-arm/arch-kirkwood/kirkwood.h create mode 100644 include/asm-arm/arch-kirkwood/memory.h create mode 100644 include/asm-arm/arch-kirkwood/system.h create mode 100644 include/asm-arm/arch-kirkwood/timex.h create mode 100644 include/asm-arm/arch-kirkwood/uncompress.h create mode 100644 include/asm-arm/arch-kirkwood/vmalloc.h (limited to 'include') diff --git a/include/asm-arm/arch-kirkwood/debug-macro.S b/include/asm-arm/arch-kirkwood/debug-macro.S new file mode 100644 index 00000000000..f55fb8ad9ee --- /dev/null +++ b/include/asm-arm/arch-kirkwood/debug-macro.S @@ -0,0 +1,20 @@ +/* + * include/asm-arm/arch-kirkwood/debug-macro.S + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =KIRKWOOD_REGS_PHYS_BASE + ldrne \rx, =KIRKWOOD_REGS_VIRT_BASE + orr \rx, \rx, #0x00012000 + .endm + +#define UART_SHIFT 2 +#include diff --git a/include/asm-arm/arch-kirkwood/dma.h b/include/asm-arm/arch-kirkwood/dma.h new file mode 100644 index 00000000000..40a8c178f10 --- /dev/null +++ b/include/asm-arm/arch-kirkwood/dma.h @@ -0,0 +1 @@ +/* empty */ diff --git a/include/asm-arm/arch-kirkwood/entry-macro.S b/include/asm-arm/arch-kirkwood/entry-macro.S new file mode 100644 index 00000000000..fc6a43d9355 --- /dev/null +++ b/include/asm-arm/arch-kirkwood/entry-macro.S @@ -0,0 +1,40 @@ +/* + * include/asm-arm/arch-kirkwood/entry-macro.S + * + * Low-level IRQ helper macros for Marvell Kirkwood platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include + + .macro disable_fiq + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =IRQ_VIRT_BASE + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + @ check low interrupts + ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF] + ldr \tmp, [\base, #IRQ_MASK_LOW_OFF] + mov \irqnr, #31 + ands \irqstat, \irqstat, \tmp + bne 1001f + + @ if no low interrupts set, check high interrupts + ldr \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF] + ldr \tmp, [\base, #IRQ_MASK_HIGH_OFF] + mov \irqnr, #63 + ands \irqstat, \irqstat, \tmp + + @ find first active interrupt source +1001: clzne \irqstat, \irqstat + subne \irqnr, \irqnr, \irqstat + .endm diff --git a/include/asm-arm/arch-kirkwood/hardware.h b/include/asm-arm/arch-kirkwood/hardware.h new file mode 100644 index 00000000000..e695719771a --- /dev/null +++ b/include/asm-arm/arch-kirkwood/hardware.h @@ -0,0 +1,21 @@ +/* + * include/asm-arm/arch-kirkwood/hardware.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include "kirkwood.h" + +#define pcibios_assign_all_busses() 1 + +#define PCIBIOS_MIN_IO 0x00001000 +#define PCIBIOS_MIN_MEM 0x01000000 +#define PCIMEM_BASE KIRKWOOD_PCIE_MEM_PHYS_BASE /* mem base for VGA */ + + +#endif diff --git a/include/asm-arm/arch-kirkwood/io.h b/include/asm-arm/arch-kirkwood/io.h new file mode 100644 index 00000000000..0ef6e95f5d5 --- /dev/null +++ b/include/asm-arm/arch-kirkwood/io.h @@ -0,0 +1,26 @@ +/* + * include/asm-arm/arch-kirkwood/io.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#include "kirkwood.h" + +#define IO_SPACE_LIMIT 0xffffffff + +static inline void __iomem *__io(unsigned long addr) +{ + return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_PHYS_BASE) + + KIRKWOOD_PCIE_IO_VIRT_BASE); +} + +#define __io(a) __io(a) +#define __mem_pci(a) (a) + + +#endif diff --git a/include/asm-arm/arch-kirkwood/irqs.h b/include/asm-arm/arch-kirkwood/irqs.h new file mode 100644 index 00000000000..2e7b5da6335 --- /dev/null +++ b/include/asm-arm/arch-kirkwood/irqs.h @@ -0,0 +1,63 @@ +/* + * include/asm-arm/arch-kirkwood/irqs.h + * + * IRQ definitions for Marvell Kirkwood SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +#include "kirkwood.h" /* need GPIO_MAX */ + +/* + * Low Interrupt Controller + */ +#define IRQ_KIRKWOOD_HIGH_SUM 0 +#define IRQ_KIRKWOOD_BRIDGE 1 +#define IRQ_KIRKWOOD_HOST2CPU 2 +#define IRQ_KIRKWOOD_CPU2HOST 3 +#define IRQ_KIRKWOOD_XOR_00 5 +#define IRQ_KIRKWOOD_XOR_01 6 +#define IRQ_KIRKWOOD_XOR_10 7 +#define IRQ_KIRKWOOD_XOR_11 8 +#define IRQ_KIRKWOOD_PCIE 9 +#define IRQ_KIRKWOOD_GE00_SUM 11 +#define IRQ_KIRKWOOD_GE01_SUM 15 +#define IRQ_KIRKWOOD_USB 19 +#define IRQ_KIRKWOOD_SATA 21 +#define IRQ_KIRKWOOD_CRYPTO 22 +#define IRQ_KIRKWOOD_SPI 23 +#define IRQ_KIRKWOOD_I2S 24 +#define IRQ_KIRKWOOD_TS_0 26 +#define IRQ_KIRKWOOD_SDIO 28 +#define IRQ_KIRKWOOD_TWSI 29 +#define IRQ_KIRKWOOD_AVB 30 +#define IRQ_KIRKWOOD_TDMI 31 + +/* + * High Interrupt Controller + */ +#define IRQ_KIRKWOOD_UART_0 33 +#define IRQ_KIRKWOOD_UART_1 34 +#define IRQ_KIRKWOOD_GPIO_LOW_0_7 35 +#define IRQ_KIRKWOOD_GPIO_LOW_8_15 36 +#define IRQ_KIRKWOOD_GPIO_LOW_16_23 37 +#define IRQ_KIRKWOOD_GPIO_LOW_24_31 38 +#define IRQ_KIRKWOOD_GPIO_HIGH_0_7 39 +#define IRQ_KIRKWOOD_GPIO_HIGH_8_15 40 +#define IRQ_KIRKWOOD_GPIO_HIGH_16_23 41 + +/* + * KIRKWOOD General Purpose Pins + */ +#define IRQ_KIRKWOOD_GPIO_START 64 +#define NR_GPIO_IRQS GPIO_MAX + +#define NR_IRQS (IRQ_KIRKWOOD_GPIO_START + NR_GPIO_IRQS) + + +#endif diff --git a/include/asm-arm/arch-kirkwood/kirkwood.h b/include/asm-arm/arch-kirkwood/kirkwood.h new file mode 100644 index 00000000000..520250dbd8a --- /dev/null +++ b/include/asm-arm/arch-kirkwood/kirkwood.h @@ -0,0 +1,99 @@ +/* + * include/asm-arm/arch-kirkwood/kirkwood.h + * + * Generic definitions for Marvell Kirkwood SoC flavors: + * 88F6180, 88F6192 and 88F6281. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_KIRKWOOD_H +#define __ASM_ARCH_KIRKWOOD_H + +/* + * Marvell Kirkwood address maps. + * + * phys + * e0000000 PCIe Memory space + * f1000000 on-chip peripheral registers + * f2000000 PCIe I/O space + * f3000000 NAND controller address window + * + * virt phys size + * fee00000 f1000000 1M on-chip peripheral registers + * fef00000 f2000000 1M PCIe I/O space + */ + +#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000 +#define KIRKWOOD_NAND_MEM_SIZE SZ_64K /* 1K is sufficient, but 64K + * is the minimal window size + */ + +#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 +#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000 +#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000 +#define KIRKWOOD_PCIE_IO_SIZE SZ_1M + +#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 +#define KIRKWOOD_REGS_VIRT_BASE 0xfee00000 +#define KIRKWOOD_REGS_SIZE SZ_1M + +#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000 +#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M + +/* + * MBUS bridge registers. + */ +#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000) +#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) +#define CPU_RESET 0x00000002 +//#define L2_WRITETHROUGH 0x00020000 +#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) +#define SOFT_RESET_OUT_EN 0x00000004 +#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) +#define SOFT_RESET 0x00000001 +#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) +#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) +#define BRIDGE_INT_TIMER0 0x0002 +#define BRIDGE_INT_TIMER1 0x0004 +#define BRIDGE_INT_TIMER1_CLR (~0x0004) +#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) +#define IRQ_CAUSE_LOW_OFF 0x0000 +#define IRQ_MASK_LOW_OFF 0x0004 +#define IRQ_CAUSE_HIGH_OFF 0x0010 +#define IRQ_MASK_HIGH_OFF 0x0014 +#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) + +/* + * Register Map + */ +#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000) +#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500) + +#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000) +#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000) +#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030) +#define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034) +#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300) +#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600) +#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) +#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) +#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) +#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) + +#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) + +#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) + +#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x70000) +#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000) + +#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000) + + +#define GPIO_MAX 50 + + +#endif diff --git a/include/asm-arm/arch-kirkwood/memory.h b/include/asm-arm/arch-kirkwood/memory.h new file mode 100644 index 00000000000..e5108f408ce --- /dev/null +++ b/include/asm-arm/arch-kirkwood/memory.h @@ -0,0 +1,14 @@ +/* + * include/asm-arm/arch-kirkwood/memory.h + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#define PHYS_OFFSET UL(0x00000000) + +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + + +#endif diff --git a/include/asm-arm/arch-kirkwood/system.h b/include/asm-arm/arch-kirkwood/system.h new file mode 100644 index 00000000000..8dde7e37985 --- /dev/null +++ b/include/asm-arm/arch-kirkwood/system.h @@ -0,0 +1,37 @@ +/* + * include/asm-arm/arch-kirkwood/system.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include +#include + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode) +{ + /* + * Enable soft reset to assert RSTOUTn. + */ + writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); + + /* + * Assert soft reset. + */ + writel(SOFT_RESET, SYSTEM_SOFT_RESET); + + while (1) + ; +} + + +#endif diff --git a/include/asm-arm/arch-kirkwood/timex.h b/include/asm-arm/arch-kirkwood/timex.h new file mode 100644 index 00000000000..82122e134e3 --- /dev/null +++ b/include/asm-arm/arch-kirkwood/timex.h @@ -0,0 +1,11 @@ +/* + * include/asm-arm/arch-kirkwood/timex.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define CLOCK_TICK_RATE (100 * HZ) + +#define KIRKWOOD_TCLK 166666667 diff --git a/include/asm-arm/arch-kirkwood/uncompress.h b/include/asm-arm/arch-kirkwood/uncompress.h new file mode 100644 index 00000000000..a9062b6d768 --- /dev/null +++ b/include/asm-arm/arch-kirkwood/uncompress.h @@ -0,0 +1,47 @@ +/* + * include/asm-arm/arch-kirkwood/uncompress.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include + +#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE) + +static void putc(const char c) +{ + unsigned char *base = SERIAL_BASE; + int i; + + for (i = 0; i < 0x1000; i++) { + if (base[UART_LSR << 2] & UART_LSR_THRE) + break; + barrier(); + } + + base[UART_TX << 2] = c; +} + +static void flush(void) +{ + unsigned char *base = SERIAL_BASE; + unsigned char mask; + int i; + + mask = UART_LSR_TEMT | UART_LSR_THRE; + + for (i = 0; i < 0x1000; i++) { + if ((base[UART_LSR << 2] & mask) == mask) + break; + barrier(); + } +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-kirkwood/vmalloc.h b/include/asm-arm/arch-kirkwood/vmalloc.h new file mode 100644 index 00000000000..41852c6e77f --- /dev/null +++ b/include/asm-arm/arch-kirkwood/vmalloc.h @@ -0,0 +1,5 @@ +/* + * include/asm-arm/arch-kirkwood/vmalloc.h + */ + +#define VMALLOC_END 0xfe800000 -- cgit v1.2.3 From a9311cfed241ebcd6b5f9be5c8c6d519bf22f9e7 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Sun, 22 Jun 2008 22:45:09 +0200 Subject: [ARM] Orion: PCIe x4/x1 detection support The Discovery Duo (MV78xx0) has two x4 PCIe ports which can either be used in x4 mode or in quad x1 mode. This patch adds an accessor function to the generic plat-orion PCIe handling code to detect in which of the two modes we're running (which is determined by strap pins and/or configured by the bootloader). Signed-off-by: Lennert Buytenhek --- include/asm-arm/plat-orion/pcie.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/asm-arm/plat-orion/pcie.h b/include/asm-arm/plat-orion/pcie.h index 6434ac685d2..e61b7bd97af 100644 --- a/include/asm-arm/plat-orion/pcie.h +++ b/include/asm-arm/plat-orion/pcie.h @@ -14,6 +14,7 @@ u32 orion_pcie_dev_id(void __iomem *base); u32 orion_pcie_rev(void __iomem *base); int orion_pcie_link_up(void __iomem *base); +int orion_pcie_x4_mode(void __iomem *base); int orion_pcie_get_local_bus_nr(void __iomem *base); void orion_pcie_set_local_bus_nr(void __iomem *base, int nr); void orion_pcie_setup(void __iomem *base, -- cgit v1.2.3 From 794d15b25df5dda10efba600d6dd6cd74a7aa9cb Mon Sep 17 00:00:00 2001 From: Stanislav Samsonov Date: Sun, 22 Jun 2008 22:45:10 +0200 Subject: [ARM] add Marvell 78xx0 ARM SoC support The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring (depending on the model) one or two Feroceon CPU cores with 512K of L2 cache and VFP coprocessors running at (depending on the model) between 800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe interfaces that can each run either in x4 or quad x1 mode, three USB 2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI interface, four UARTs, and depending on the model, two or four gigabit ethernet interfaces. This patch adds basic support for the platform, and allows booting on the MV78x00 development board, with functional UARTs, SATA, PCIe, GigE and USB ports. Signed-off-by: Stanislav Samsonov Signed-off-by: Lennert Buytenhek --- include/asm-arm/arch-mv78xx0/debug-macro.S | 20 +++++ include/asm-arm/arch-mv78xx0/dma.h | 1 + include/asm-arm/arch-mv78xx0/entry-macro.S | 39 +++++++++ include/asm-arm/arch-mv78xx0/hardware.h | 21 +++++ include/asm-arm/arch-mv78xx0/io.h | 26 ++++++ include/asm-arm/arch-mv78xx0/irqs.h | 91 +++++++++++++++++++++ include/asm-arm/arch-mv78xx0/memory.h | 14 ++++ include/asm-arm/arch-mv78xx0/mv78xx0.h | 126 +++++++++++++++++++++++++++++ include/asm-arm/arch-mv78xx0/system.h | 37 +++++++++ include/asm-arm/arch-mv78xx0/timex.h | 9 +++ include/asm-arm/arch-mv78xx0/uncompress.h | 47 +++++++++++ include/asm-arm/arch-mv78xx0/vmalloc.h | 5 ++ 12 files changed, 436 insertions(+) create mode 100644 include/asm-arm/arch-mv78xx0/debug-macro.S create mode 100644 include/asm-arm/arch-mv78xx0/dma.h create mode 100644 include/asm-arm/arch-mv78xx0/entry-macro.S create mode 100644 include/asm-arm/arch-mv78xx0/hardware.h create mode 100644 include/asm-arm/arch-mv78xx0/io.h create mode 100644 include/asm-arm/arch-mv78xx0/irqs.h create mode 100644 include/asm-arm/arch-mv78xx0/memory.h create mode 100644 include/asm-arm/arch-mv78xx0/mv78xx0.h create mode 100644 include/asm-arm/arch-mv78xx0/system.h create mode 100644 include/asm-arm/arch-mv78xx0/timex.h create mode 100644 include/asm-arm/arch-mv78xx0/uncompress.h create mode 100644 include/asm-arm/arch-mv78xx0/vmalloc.h (limited to 'include') diff --git a/include/asm-arm/arch-mv78xx0/debug-macro.S b/include/asm-arm/arch-mv78xx0/debug-macro.S new file mode 100644 index 00000000000..d0595bd645e --- /dev/null +++ b/include/asm-arm/arch-mv78xx0/debug-macro.S @@ -0,0 +1,20 @@ +/* + * include/asm-arm/arch-mv78xx0/debug-macro.S + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =MV78XX0_REGS_PHYS_BASE + ldrne \rx, =MV78XX0_REGS_VIRT_BASE + orr \rx, \rx, #0x00012000 + .endm + +#define UART_SHIFT 2 +#include diff --git a/include/asm-arm/arch-mv78xx0/dma.h b/include/asm-arm/arch-mv78xx0/dma.h new file mode 100644 index 00000000000..40a8c178f10 --- /dev/null +++ b/include/asm-arm/arch-mv78xx0/dma.h @@ -0,0 +1 @@ +/* empty */ diff --git a/include/asm-arm/arch-mv78xx0/entry-macro.S b/include/asm-arm/arch-mv78xx0/entry-macro.S new file mode 100644 index 00000000000..e9a606b1266 --- /dev/null +++ b/include/asm-arm/arch-mv78xx0/entry-macro.S @@ -0,0 +1,39 @@ +/* + * include/asm-arm/arch-mv78xx0/entry-macro.S + * + * Low-level IRQ helper macros for Marvell MV78xx0 platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include + + .macro disable_fiq + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =IRQ_VIRT_BASE + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + @ check low interrupts + ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF] + ldr \tmp, [\base, #IRQ_MASK_LOW_OFF] + mov \irqnr, #31 + ands \irqstat, \irqstat, \tmp + + @ if no low interrupts set, check high interrupts + ldreq \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF] + ldreq \tmp, [\base, #IRQ_MASK_HIGH_OFF] + moveq \irqnr, #63 + andeqs \irqstat, \irqstat, \tmp + + @ find first active interrupt source + clzne \irqstat, \irqstat + subne \irqnr, \irqnr, \irqstat + .endm diff --git a/include/asm-arm/arch-mv78xx0/hardware.h b/include/asm-arm/arch-mv78xx0/hardware.h new file mode 100644 index 00000000000..8e17926086c --- /dev/null +++ b/include/asm-arm/arch-mv78xx0/hardware.h @@ -0,0 +1,21 @@ +/* + * include/asm-arm/arch-mv78xx0/hardware.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include "mv78xx0.h" + +#define pcibios_assign_all_busses() 1 + +#define PCIBIOS_MIN_IO 0x00001000 +#define PCIBIOS_MIN_MEM 0x01000000 +#define PCIMEM_BASE MV78XX0_PCIE_MEM_PHYS_BASE /* mem base for VGA */ + + +#endif diff --git a/include/asm-arm/arch-mv78xx0/io.h b/include/asm-arm/arch-mv78xx0/io.h new file mode 100644 index 00000000000..415d4c98e3d --- /dev/null +++ b/include/asm-arm/arch-mv78xx0/io.h @@ -0,0 +1,26 @@ +/* + * include/asm-arm/arch-mv78xx0/io.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#include "mv78xx0.h" + +#define IO_SPACE_LIMIT 0xffffffff + +static inline void __iomem *__io(unsigned long addr) +{ + return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0)) + + MV78XX0_PCIE_IO_VIRT_BASE(0)); +} + +#define __io(a) __io(a) +#define __mem_pci(a) (a) + + +#endif diff --git a/include/asm-arm/arch-mv78xx0/irqs.h b/include/asm-arm/arch-mv78xx0/irqs.h new file mode 100644 index 00000000000..75930450cd6 --- /dev/null +++ b/include/asm-arm/arch-mv78xx0/irqs.h @@ -0,0 +1,91 @@ +/* + * include/asm-arm/arch-mv78xx0/irqs.h + * + * IRQ definitions for Marvell MV78xx0 SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +#include "mv78xx0.h" /* need GPIO_MAX */ + +/* + * MV78xx0 Low Interrupt Controller + */ +#define IRQ_MV78XX0_ERR 0 +#define IRQ_MV78XX0_SPI 1 +#define IRQ_MV78XX0_I2C_0 2 +#define IRQ_MV78XX0_I2C_1 3 +#define IRQ_MV78XX0_IDMA_0 4 +#define IRQ_MV78XX0_IDMA_1 5 +#define IRQ_MV78XX0_IDMA_2 6 +#define IRQ_MV78XX0_IDMA_3 7 +#define IRQ_MV78XX0_TIMER_0 8 +#define IRQ_MV78XX0_TIMER_1 9 +#define IRQ_MV78XX0_TIMER_2 10 +#define IRQ_MV78XX0_TIMER_3 11 +#define IRQ_MV78XX0_UART_0 12 +#define IRQ_MV78XX0_UART_1 13 +#define IRQ_MV78XX0_UART_2 14 +#define IRQ_MV78XX0_UART_3 15 +#define IRQ_MV78XX0_USB_0 16 +#define IRQ_MV78XX0_USB_1 17 +#define IRQ_MV78XX0_USB_2 18 +#define IRQ_MV78XX0_CRYPTO 19 +#define IRQ_MV78XX0_SDIO_0 20 +#define IRQ_MV78XX0_SDIO_1 21 +#define IRQ_MV78XX0_XOR_0 22 +#define IRQ_MV78XX0_XOR_1 23 +#define IRQ_MV78XX0_I2S_0 24 +#define IRQ_MV78XX0_I2S_1 25 +#define IRQ_MV78XX0_SATA 26 +#define IRQ_MV78XX0_TDMI 27 + +/* + * MV78xx0 High Interrupt Controller + */ +#define IRQ_MV78XX0_PCIE_00 32 +#define IRQ_MV78XX0_PCIE_01 33 +#define IRQ_MV78XX0_PCIE_02 34 +#define IRQ_MV78XX0_PCIE_03 35 +#define IRQ_MV78XX0_PCIE_10 36 +#define IRQ_MV78XX0_PCIE_11 37 +#define IRQ_MV78XX0_PCIE_12 38 +#define IRQ_MV78XX0_PCIE_13 39 +#define IRQ_MV78XX0_GE00_SUM 40 +#define IRQ_MV78XX0_GE00_RX 41 +#define IRQ_MV78XX0_GE00_TX 42 +#define IRQ_MV78XX0_GE00_MISC 43 +#define IRQ_MV78XX0_GE01_SUM 44 +#define IRQ_MV78XX0_GE01_RX 45 +#define IRQ_MV78XX0_GE01_TX 46 +#define IRQ_MV78XX0_GE01_MISC 47 +#define IRQ_MV78XX0_GE10_SUM 48 +#define IRQ_MV78XX0_GE10_RX 49 +#define IRQ_MV78XX0_GE10_TX 50 +#define IRQ_MV78XX0_GE10_MISC 51 +#define IRQ_MV78XX0_GE11_SUM 52 +#define IRQ_MV78XX0_GE11_RX 53 +#define IRQ_MV78XX0_GE11_TX 54 +#define IRQ_MV78XX0_GE11_MISC 55 +#define IRQ_MV78XX0_GPIO_0_7 56 +#define IRQ_MV78XX0_GPIO_8_15 57 +#define IRQ_MV78XX0_GPIO_16_23 58 +#define IRQ_MV78XX0_GPIO_24_31 59 +#define IRQ_MV78XX0_DB_IN 60 +#define IRQ_MV78XX0_DB_OUT 61 + +/* + * MV78XX0 General Purpose Pins + */ +#define IRQ_MV78XX0_GPIO_START 64 +#define NR_GPIO_IRQS GPIO_MAX + +#define NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS) + + +#endif diff --git a/include/asm-arm/arch-mv78xx0/memory.h b/include/asm-arm/arch-mv78xx0/memory.h new file mode 100644 index 00000000000..721a6b185b9 --- /dev/null +++ b/include/asm-arm/arch-mv78xx0/memory.h @@ -0,0 +1,14 @@ +/* + * include/asm-arm/arch-mv78xx0/memory.h + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#define PHYS_OFFSET UL(0x00000000) + +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + + +#endif diff --git a/include/asm-arm/arch-mv78xx0/mv78xx0.h b/include/asm-arm/arch-mv78xx0/mv78xx0.h new file mode 100644 index 00000000000..9f5d83c73fa --- /dev/null +++ b/include/asm-arm/arch-mv78xx0/mv78xx0.h @@ -0,0 +1,126 @@ +/* + * include/asm-arm/arch-mv78xx0/mv78xx0.h + * + * Generic definitions for Marvell MV78xx0 SoC flavors: + * MV781x0 and MV782x0. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_MV78XX0_H +#define __ASM_ARCH_MV78XX0_H + +/* + * Marvell MV78xx0 address maps. + * + * phys + * c0000000 PCIe Memory space + * f0800000 PCIe #0 I/O space + * f0900000 PCIe #1 I/O space + * f0a00000 PCIe #2 I/O space + * f0b00000 PCIe #3 I/O space + * f0c00000 PCIe #4 I/O space + * f0d00000 PCIe #5 I/O space + * f0e00000 PCIe #6 I/O space + * f0f00000 PCIe #7 I/O space + * f1000000 on-chip peripheral registers + * + * virt phys size + * fe400000 f102x000 16K core-specific peripheral registers + * fe700000 f0800000 1M PCIe #0 I/O space + * fe800000 f0900000 1M PCIe #1 I/O space + * fe900000 f0a00000 1M PCIe #2 I/O space + * fea00000 f0b00000 1M PCIe #3 I/O space + * feb00000 f0c00000 1M PCIe #4 I/O space + * fec00000 f0d00000 1M PCIe #5 I/O space + * fed00000 f0e00000 1M PCIe #6 I/O space + * fee00000 f0f00000 1M PCIe #7 I/O space + * fef00000 f1000000 1M on-chip peripheral registers + */ +#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 +#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 +#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000 +#define MV78XX0_CORE_REGS_SIZE SZ_16K + +#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) +#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20)) +#define MV78XX0_PCIE_IO_SIZE SZ_1M + +#define MV78XX0_REGS_PHYS_BASE 0xf1000000 +#define MV78XX0_REGS_VIRT_BASE 0xfef00000 +#define MV78XX0_REGS_SIZE SZ_1M + +#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 +#define MV78XX0_PCIE_MEM_SIZE 0x30000000 + +/* + * Core-specific peripheral registers. + */ +#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) +#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) +#define L2_WRITETHROUGH 0x00020000 +#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) +#define SOFT_RESET_OUT_EN 0x00000004 +#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) +#define SOFT_RESET 0x00000001 +#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) +#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) +#define BRIDGE_INT_TIMER0 0x0002 +#define BRIDGE_INT_TIMER1 0x0004 +#define BRIDGE_INT_TIMER1_CLR (~0x0004) +#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) +#define IRQ_CAUSE_LOW_OFF 0x0004 +#define IRQ_CAUSE_HIGH_OFF 0x0008 +#define IRQ_MASK_LOW_OFF 0x0010 +#define IRQ_MASK_HIGH_OFF 0x0014 +#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) + +/* + * Register Map + */ +#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) +#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500) +#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1700) + +#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000) +#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) +#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) +#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) +#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) +#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) +#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) +#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) +#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200) +#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200) +#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300) +#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300) + +#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000) +#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000) + +#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000) +#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000) +#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000) +#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000) + +#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000) +#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000) +#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000) + +#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000) +#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000) + +#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000) +#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000) +#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000) +#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000) + +#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) + + +#define GPIO_MAX 32 + + +#endif diff --git a/include/asm-arm/arch-mv78xx0/system.h b/include/asm-arm/arch-mv78xx0/system.h new file mode 100644 index 00000000000..7eb47d376db --- /dev/null +++ b/include/asm-arm/arch-mv78xx0/system.h @@ -0,0 +1,37 @@ +/* + * include/asm-arm/arch-mv78xx0/system.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include +#include + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode) +{ + /* + * Enable soft reset to assert RSTOUTn. + */ + writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); + + /* + * Assert soft reset. + */ + writel(SOFT_RESET, SYSTEM_SOFT_RESET); + + while (1) + ; +} + + +#endif diff --git a/include/asm-arm/arch-mv78xx0/timex.h b/include/asm-arm/arch-mv78xx0/timex.h new file mode 100644 index 00000000000..a854b1ccbd0 --- /dev/null +++ b/include/asm-arm/arch-mv78xx0/timex.h @@ -0,0 +1,9 @@ +/* + * include/asm-arm/arch-mv78xx0/timex.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define CLOCK_TICK_RATE (100 * HZ) diff --git a/include/asm-arm/arch-mv78xx0/uncompress.h b/include/asm-arm/arch-mv78xx0/uncompress.h new file mode 100644 index 00000000000..3bfe0a293ef --- /dev/null +++ b/include/asm-arm/arch-mv78xx0/uncompress.h @@ -0,0 +1,47 @@ +/* + * include/asm-arm/arch-mv78xx0/uncompress.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include + +#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE) + +static void putc(const char c) +{ + unsigned char *base = SERIAL_BASE; + int i; + + for (i = 0; i < 0x1000; i++) { + if (base[UART_LSR << 2] & UART_LSR_THRE) + break; + barrier(); + } + + base[UART_TX << 2] = c; +} + +static void flush(void) +{ + unsigned char *base = SERIAL_BASE; + unsigned char mask; + int i; + + mask = UART_LSR_TEMT | UART_LSR_THRE; + + for (i = 0; i < 0x1000; i++) { + if ((base[UART_LSR << 2] & mask) == mask) + break; + barrier(); + } +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-mv78xx0/vmalloc.h b/include/asm-arm/arch-mv78xx0/vmalloc.h new file mode 100644 index 00000000000..f2c51219757 --- /dev/null +++ b/include/asm-arm/arch-mv78xx0/vmalloc.h @@ -0,0 +1,5 @@ +/* + * include/asm-arm/arch-mv78xx0/vmalloc.h + */ + +#define VMALLOC_END 0xfe000000 -- cgit v1.2.3 From 20d4fdc1a788e4ca0aaf2422772ba668e7e10839 Mon Sep 17 00:00:00 2001 From: Jan Engelhardt Date: Mon, 9 Jun 2008 16:40:36 -0700 Subject: [patch 2/4] fs: make struct file arg to d_path const Signed-off-by: Jan Engelhardt Cc: Al Viro Signed-off-by: Andrew Morton Signed-off-by: Al Viro --- include/linux/dcache.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/dcache.h b/include/linux/dcache.h index 2a6639407c8..d982eb89c77 100644 --- a/include/linux/dcache.h +++ b/include/linux/dcache.h @@ -300,7 +300,7 @@ extern int d_validate(struct dentry *, struct dentry *); extern char *dynamic_dname(struct dentry *, char *, int, const char *, ...); extern char *__d_path(const struct path *path, struct path *root, char *, int); -extern char *d_path(struct path *, char *, int); +extern char *d_path(const struct path *, char *, int); extern char *dentry_path(struct dentry *, char *, int); /* Allocation counts.. */ -- cgit v1.2.3 From f9f48ec72bfc9489a30bc6ddbfcf27d86a8bc651 Mon Sep 17 00:00:00 2001 From: "Denis V. Lunev" Date: Mon, 9 Jun 2008 16:40:38 -0700 Subject: [patch 4/4] flock: remove unused fields from file_lock_operations fl_insert and fl_remove are not used right now in the kernel. Remove them. Signed-off-by: Denis V. Lunev Cc: Matthew Wilcox Cc: Alexander Viro Cc: "J. Bruce Fields" Signed-off-by: Andrew Morton Signed-off-by: Al Viro --- include/linux/fs.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/linux/fs.h b/include/linux/fs.h index d490779f18d..7c108082683 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -894,8 +894,6 @@ static inline int file_check_writeable(struct file *filp) typedef struct files_struct *fl_owner_t; struct file_lock_operations { - void (*fl_insert)(struct file_lock *); /* lock insertion callback */ - void (*fl_remove)(struct file_lock *); /* lock removal callback */ void (*fl_copy_lock)(struct file_lock *, struct file_lock *); void (*fl_release_private)(struct file_lock *); }; -- cgit v1.2.3 From d8de72473effd674a3c1fe9621821f406f5587c9 Mon Sep 17 00:00:00 2001 From: Peng Haitao Date: Tue, 20 May 2008 09:13:02 +0800 Subject: [PATCH] remove useless argument type in audit_filter_user() The second argument "type" is not used in audit_filter_user(), so I think that type can be removed. If I'm wrong, please tell me. Signed-off-by: Peng Haitao Signed-off-by: Al Viro --- include/linux/audit.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/audit.h b/include/linux/audit.h index 63c3bb98558..8b82974bdc1 100644 --- a/include/linux/audit.h +++ b/include/linux/audit.h @@ -571,7 +571,7 @@ extern void audit_log_lost(const char *message); extern int audit_update_lsm_rules(void); /* Private API (for audit.c only) */ -extern int audit_filter_user(struct netlink_skb_parms *cb, int type); +extern int audit_filter_user(struct netlink_skb_parms *cb); extern int audit_filter_type(int type); extern int audit_receive_filter(int type, int pid, int uid, int seq, void *data, size_t datasz, uid_t loginuid, -- cgit v1.2.3 From 16d752397301b95abaa95cbaf9e785d221872311 Mon Sep 17 00:00:00 2001 From: Rene Herman Date: Tue, 24 Jun 2008 19:38:56 +0200 Subject: thermal: Create CONFIG_THERMAL_HWMON=n A bug in libsensors <= 2.10.6 is exposed when this new hwmon I/F is enabled. Create CONFIG_THERMAL_HWMON=n until some time after libsensors 2.10.7 ships so those users can run the latest kernel. libsensors 3.x is already fixed -- those users can use CONFIG_THERMAL_HWMON=y now. Signed-off-by: Rene Herman Acked-by: Mark M. Hoffman Signed-off-by: Len Brown --- include/linux/thermal.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/linux/thermal.h b/include/linux/thermal.h index 06d3e6eb9ca..917707e6151 100644 --- a/include/linux/thermal.h +++ b/include/linux/thermal.h @@ -66,8 +66,7 @@ struct thermal_cooling_device { ((long)t-2732+5)/10 : ((long)t-2732-5)/10) #define CELSIUS_TO_KELVIN(t) ((t)*10+2732) -#if defined(CONFIG_HWMON) || \ - (defined(CONFIG_HWMON_MODULE) && defined(CONFIG_THERMAL_MODULE)) +#if defined(CONFIG_THERMAL_HWMON) /* thermal zone devices with the same type share one hwmon device */ struct thermal_hwmon_device { char type[THERMAL_NAME_LENGTH]; @@ -94,8 +93,7 @@ struct thermal_zone_device { struct idr idr; struct mutex lock; /* protect cooling devices list */ struct list_head node; -#if defined(CONFIG_HWMON) || \ - (defined(CONFIG_HWMON_MODULE) && defined(CONFIG_THERMAL_MODULE)) +#if defined(CONFIG_THERMAL_HWMON) struct list_head hwmon_node; struct thermal_hwmon_device *hwmon; struct thermal_hwmon_attr temp_input; /* hwmon sys attr */ -- cgit v1.2.3 From 41aefdcc98fdba47459eab67630293d67e855fc3 Mon Sep 17 00:00:00 2001 From: Max Asbock Date: Wed, 25 Jun 2008 14:45:28 -0700 Subject: x86: shift bits the right way in native_read_tscp native_read_tscp shifts the bits in the high order value in the wrong direction, the attached patch fixes that. Signed-off-by: Max Asbock Acked-by: Glauber Costa Signed-off-by: Ingo Molnar --- include/asm-x86/msr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-x86/msr.h b/include/asm-x86/msr.h index 3707650a169..2b5f2c91db2 100644 --- a/include/asm-x86/msr.h +++ b/include/asm-x86/msr.h @@ -18,7 +18,7 @@ static inline unsigned long long native_read_tscp(unsigned int *aux) unsigned long low, high; asm volatile(".byte 0x0f,0x01,0xf9" : "=a" (low), "=d" (high), "=c" (*aux)); - return low | ((u64)high >> 32); + return low | ((u64)high << 32); } /* -- cgit v1.2.3 From 45270a1531a2aa90dd890666913c25a1e6f5e8eb Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Sat, 7 Jun 2008 11:18:17 -0300 Subject: V4L/DVB (8007): cx18/cx25840: the S-Video LUMA input can use all In1-In8 inputs The S-Video LUMA input was restricted to the In1-In4 inputs, but it turns out that it can use the full range of In1-In8. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- include/media/cx25840.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/media/cx25840.h b/include/media/cx25840.h index cd599ad29fb..db431d513f2 100644 --- a/include/media/cx25840.h +++ b/include/media/cx25840.h @@ -32,12 +32,16 @@ enum cx25840_video_input { CX25840_COMPOSITE7, CX25840_COMPOSITE8, - /* S-Video inputs consist of one luma input (In1-In4) ORed with one + /* S-Video inputs consist of one luma input (In1-In8) ORed with one chroma input (In5-In8) */ CX25840_SVIDEO_LUMA1 = 0x10, CX25840_SVIDEO_LUMA2 = 0x20, CX25840_SVIDEO_LUMA3 = 0x30, CX25840_SVIDEO_LUMA4 = 0x40, + CX25840_SVIDEO_LUMA5 = 0x50, + CX25840_SVIDEO_LUMA6 = 0x60, + CX25840_SVIDEO_LUMA7 = 0x70, + CX25840_SVIDEO_LUMA8 = 0x80, CX25840_SVIDEO_CHROMA4 = 0x400, CX25840_SVIDEO_CHROMA5 = 0x500, CX25840_SVIDEO_CHROMA6 = 0x600, -- cgit v1.2.3 From 6e501a3f4a7259b1c04aa6cbdfe64376afc9f59c Mon Sep 17 00:00:00 2001 From: Tim Farrington Date: Sun, 15 Jun 2008 13:33:42 -0300 Subject: V4L/DVB (8048): saa7134: Fix entries for Avermedia A16d and Avermedia E506 Also, adds IR table for Avermedia A16d Signed-off-by: Tim Farrington Signed-off-by: Mauro Carvalho Chehab --- include/media/ir-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/media/ir-common.h b/include/media/ir-common.h index bfee8be5d63..b8e8aa91905 100644 --- a/include/media/ir-common.h +++ b/include/media/ir-common.h @@ -146,6 +146,7 @@ extern IR_KEYTAB_TYPE ir_codes_behold_columbus[IR_KEYTAB_SIZE]; extern IR_KEYTAB_TYPE ir_codes_pinnacle_pctv_hd[IR_KEYTAB_SIZE]; extern IR_KEYTAB_TYPE ir_codes_genius_tvgo_a11mce[IR_KEYTAB_SIZE]; extern IR_KEYTAB_TYPE ir_codes_powercolor_real_angel[IR_KEYTAB_SIZE]; +extern IR_KEYTAB_TYPE ir_codes_avermedia_a16d[IR_KEYTAB_SIZE]; #endif -- cgit v1.2.3 From 7fa8e6fa1519194fc0c931f40d530fb55137bad9 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Sat, 21 Jun 2008 13:23:27 -0300 Subject: V4L/DVB (8092): videodev: simplify and fix standard enumeration VIDIOC_ENUMSTD did not return all the PAL/SECAM/NTSC variants: it just returned one single PAL/SECAM/NTSC standard without separate entries for the trickier standards like NTSC-JP. Changed the code so that it behaves better. Also simplified the if/switch statements into a common standards lookup table. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- include/media/v4l2-dev.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/media/v4l2-dev.h b/include/media/v4l2-dev.h index 33f01ae08f7..859f7a6f6f6 100644 --- a/include/media/v4l2-dev.h +++ b/include/media/v4l2-dev.h @@ -40,9 +40,9 @@ #define VFL_TYPE_VTX 3 /* Video standard functions */ -extern char *v4l2_norm_to_name(v4l2_std_id id); +extern const char *v4l2_norm_to_name(v4l2_std_id id); extern int v4l2_video_std_construct(struct v4l2_standard *vs, - int id, char *name); + int id, const char *name); /* Prints the ioctl in a human-readable format */ extern void v4l_printk_ioctl(unsigned int cmd); -- cgit v1.2.3 From b660398101cd0622325480a67ac88bb4d33d553a Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Fri, 27 Jun 2008 14:39:42 +0100 Subject: kbuild: fix a.out.h export to userspace with O= build. We need to check for existence of the a.out.h header in the source tree, not the object tree, if we want it to get the right answer with O=. Signed-off-by: David Woodhouse Signed-off-by: Sam Ravnborg --- include/asm-generic/Kbuild.asm | 2 +- include/asm-powerpc/Kbuild | 1 - include/linux/Kbuild | 2 +- 3 files changed, 2 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-generic/Kbuild.asm b/include/asm-generic/Kbuild.asm index 92a6d91d0c1..7cd25b8e7c9 100644 --- a/include/asm-generic/Kbuild.asm +++ b/include/asm-generic/Kbuild.asm @@ -1,6 +1,6 @@ header-y += kvm.h -ifeq ($(wildcard include/asm-$(SRCARCH)/a.out.h),include/asm-$(SRCARCH)/a.out.h) +ifneq ($(wildcard $(srctree)/include/asm-$(SRCARCH)/a.out.h),) unifdef-y += a.out.h endif unifdef-y += auxvec.h diff --git a/include/asm-powerpc/Kbuild b/include/asm-powerpc/Kbuild index 7381916dfcb..bca352e033c 100644 --- a/include/asm-powerpc/Kbuild +++ b/include/asm-powerpc/Kbuild @@ -1,6 +1,5 @@ include include/asm-generic/Kbuild.asm -header-y += a.out.h header-y += auxvec.h header-y += ioctls.h header-y += mman.h diff --git a/include/linux/Kbuild b/include/linux/Kbuild index b6fbb2573e8..71d70d1fbce 100644 --- a/include/linux/Kbuild +++ b/include/linux/Kbuild @@ -166,7 +166,7 @@ unifdef-y += acct.h unifdef-y += adb.h unifdef-y += adfs_fs.h unifdef-y += agpgart.h -ifeq ($(wildcard include/asm-$(SRCARCH)/a.out.h),include/asm-$(SRCARCH)/a.out.h) +ifneq ($(wildcard $(srctree)/include/asm-$(SRCARCH)/a.out.h),) unifdef-y += a.out.h endif unifdef-y += apm_bios.h -- cgit v1.2.3 From c88e6f51c2154c7606f7e281bcca2d1a2c89d7b2 Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Fri, 27 Jun 2008 19:54:54 -0700 Subject: include/linux/netdevice.h: don't export MAX_HEADER to userspace Due to the CONFIG_'s the value is anyway not correct in userspace. Signed-off-by: Adrian Bunk Signed-off-by: David S. Miller --- include/linux/netdevice.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index f27fd200933..25f87102ab6 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -88,6 +88,8 @@ struct wireless_dev; #define NETDEV_TX_BUSY 1 /* driver tx path was busy*/ #define NETDEV_TX_LOCKED -1 /* driver tx lock was already taken */ +#ifdef __KERNEL__ + /* * Compute the worst case header length according to the protocols * used. @@ -114,6 +116,8 @@ struct wireless_dev; #define MAX_HEADER (LL_MAX_HEADER + 48) #endif +#endif /* __KERNEL__ */ + struct net_device_subqueue { /* Give a control state for each queue. This struct may contain -- cgit v1.2.3 From 251a4b320f2352598f84e4452ab538aa8064af52 Mon Sep 17 00:00:00 2001 From: Eli Cohen Date: Fri, 27 Jun 2008 20:09:00 -0700 Subject: net/inet_lro: remove setting skb->ip_summed when not LRO-able When an SKB cannot be chained to a session, the current code attempts to "restore" its ip_summed field from lro_mgr->ip_summed. However, lro_mgr->ip_summed does not hold the original value; in fact, we'd better not touch skb->ip_summed since it is not modified by the code in the path leading to a failure to chain it. Also use a cleaer comment to the describe the ip_summed field of struct net_lro_mgr. Issue raised by Or Gerlitz Signed-off-by: Eli Cohen Signed-off-by: David S. Miller --- include/linux/inet_lro.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/inet_lro.h b/include/linux/inet_lro.h index 80335b7d77c..c4335faebb6 100644 --- a/include/linux/inet_lro.h +++ b/include/linux/inet_lro.h @@ -84,7 +84,11 @@ struct net_lro_mgr { from received packets and eth protocol is still ETH_P_8021Q */ - u32 ip_summed; /* Set in non generated SKBs in page mode */ + /* + * Set for generated SKBs that are not added to + * the frag list in fragmented mode + */ + u32 ip_summed; u32 ip_summed_aggr; /* Set in aggregated SKBs: CHECKSUM_UNNECESSARY * or CHECKSUM_NONE */ -- cgit v1.2.3 From 4bbff7e408a54cce88d26191191e8bcda2a60d55 Mon Sep 17 00:00:00 2001 From: Bastien Nocera Date: Thu, 26 Jun 2008 09:13:48 -0400 Subject: Input: add KEY_MEDIA_REPEAT definition This patch adds the Repeat key to the input layer. The usage in the HUT is 0xBC (listed under "15.7 Transport Controls"). Signed-off-by: Dmitry Torokhov --- include/linux/input.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/input.h b/include/linux/input.h index e075c4b762f..d150c57e5f0 100644 --- a/include/linux/input.h +++ b/include/linux/input.h @@ -534,8 +534,8 @@ struct input_absinfo { #define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ #define KEY_FRAMEFORWARD 0x1b5 - #define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ +#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ #define KEY_DEL_EOL 0x1c0 #define KEY_DEL_EOS 0x1c1 -- cgit v1.2.3 From 1338760329c586e0141831099e15f5c336dd9c1d Mon Sep 17 00:00:00 2001 From: Saeed Bishara Date: Mon, 23 Jun 2008 01:05:08 -1100 Subject: [ARM] Kirkwood: support L2 writeback mode This patch allows booting Kirkwood with the L2 in writeback mode, by reading the WT override bit from the L2 config register and passing that into the Feroceon L2 init routine, instead of assuming that the WT override bit will always be set Signed-off-by: Saeed Bishara Signed-off-by: Lennert Buytenhek --- include/asm-arm/arch-kirkwood/kirkwood.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-arm/arch-kirkwood/kirkwood.h b/include/asm-arm/arch-kirkwood/kirkwood.h index 520250dbd8a..bb31b315c35 100644 --- a/include/asm-arm/arch-kirkwood/kirkwood.h +++ b/include/asm-arm/arch-kirkwood/kirkwood.h @@ -49,7 +49,6 @@ #define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000) #define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) #define CPU_RESET 0x00000002 -//#define L2_WRITETHROUGH 0x00020000 #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) #define SOFT_RESET_OUT_EN 0x00000004 #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) @@ -65,6 +64,8 @@ #define IRQ_CAUSE_HIGH_OFF 0x0010 #define IRQ_MASK_HIGH_OFF 0x0014 #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) +#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128) +#define L2_WRITETHROUGH 0x00000010 /* * Register Map -- cgit v1.2.3 From 23976efedd5ecb420b87455787c537eb4aed1981 Mon Sep 17 00:00:00 2001 From: Emmanuel Grumbach Date: Sat, 28 Jun 2008 02:50:13 +0300 Subject: mac80211: don't accept WEP keys other than WEP40 and WEP104 This patch makes mac80211 refuse a WEP key whose length is not WEP40 nor WEP104. Signed-off-by: Emmanuel Grumbach Signed-off-by: Tomas Winkler Signed-off-by: John W. Linville --- include/net/mac80211.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/net/mac80211.h b/include/net/mac80211.h index dae3f9ec115..bcd1623245c 100644 --- a/include/net/mac80211.h +++ b/include/net/mac80211.h @@ -595,6 +595,15 @@ enum ieee80211_key_alg { ALG_CCMP, }; +/** + * enum ieee80211_key_len - key length + * @WEP40: WEP 5 byte long key + * @WEP104: WEP 13 byte long key + */ +enum ieee80211_key_len { + LEN_WEP40 = 5, + LEN_WEP104 = 13, +}; /** * enum ieee80211_key_flags - key flags -- cgit v1.2.3 From f4db56ffd43a810424866fac6de9a32486415316 Mon Sep 17 00:00:00 2001 From: Saeed Bishara Date: Sun, 4 May 2008 19:25:52 -1100 Subject: [MTD] orion_nand: add chip_delay parameter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some SoCs need a different chip_delay value. Signed-off-by: Saeed Bishara Acked-by: Jörn Engel Signed-off-by: Lennert Buytenhek Signed-off-by: Nicolas Pitre --- include/asm-arm/plat-orion/orion_nand.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/asm-arm/plat-orion/orion_nand.h b/include/asm-arm/plat-orion/orion_nand.h index ffd3852a0dd..ad4ce94c199 100644 --- a/include/asm-arm/plat-orion/orion_nand.h +++ b/include/asm-arm/plat-orion/orion_nand.h @@ -18,6 +18,7 @@ struct orion_nand_data { u8 ale; /* address line number connected to ALE */ u8 cle; /* address line number connected to CLE */ u8 width; /* buswidth */ + u8 chip_delay; }; -- cgit v1.2.3 From 18ce3751ccd488c78d3827e9f6bf54e6322676fb Mon Sep 17 00:00:00 2001 From: Jens Axboe Date: Tue, 1 Jul 2008 09:07:34 +0200 Subject: Properly notify block layer of sync writes fsync_buffers_list() and sync_dirty_buffer() both issue async writes and then immediately wait on them. Conceptually, that makes them sync writes and we should treat them as such so that the IO schedulers can handle them appropriately. This patch fixes a write starvation issue that Lin Ming reported, where xx is stuck for more than 2 minutes because of a large number of synchronous IO in the system: INFO: task kjournald:20558 blocked for more than 120 seconds. "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. kjournald D ffff810010820978 6712 20558 2 ffff81022ddb1d10 0000000000000046 ffff81022e7baa10 ffffffff803ba6f2 ffff81022ecd0000 ffff8101e6dc9160 ffff81022ecd0348 000000008048b6cb 0000000000000086 ffff81022c4e8d30 0000000000000000 ffffffff80247537 Call Trace: [] kobject_get+0x12/0x17 [] getnstimeofday+0x2f/0x83 [] sync_buffer+0x0/0x3f [] io_schedule+0x5d/0x9f [] sync_buffer+0x3b/0x3f [] __wait_on_bit+0x40/0x6f [] sync_buffer+0x0/0x3f [] out_of_line_wait_on_bit+0x6c/0x78 [] wake_bit_function+0x0/0x23 [] sync_dirty_buffer+0x98/0xcb [] journal_commit_transaction+0x97d/0xcb6 [] lock_timer_base+0x26/0x4b [] kjournald+0xc1/0x1fb [] autoremove_wake_function+0x0/0x2e [] kjournald+0x0/0x1fb [] kthread+0x47/0x74 [] schedule_tail+0x28/0x5d [] child_rip+0xa/0x12 [] kthread+0x0/0x74 [] child_rip+0x0/0x12 Lin Ming confirms that this patch fixes the issue. I've run tests with it for the past week and no ill effects have been observed, so I'm proposing it for inclusion into 2.6.26. Signed-off-by: Jens Axboe --- include/linux/fs.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/linux/fs.h b/include/linux/fs.h index 7c108082683..d8e2762ed14 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -83,6 +83,7 @@ extern int dir_notify_enable; #define READ_SYNC (READ | (1 << BIO_RW_SYNC)) #define READ_META (READ | (1 << BIO_RW_META)) #define WRITE_SYNC (WRITE | (1 << BIO_RW_SYNC)) +#define SWRITE_SYNC (SWRITE | (1 << BIO_RW_SYNC)) #define WRITE_BARRIER ((1 << BIO_RW) | (1 << BIO_RW_BARRIER)) #define SEL_IN 1 -- cgit v1.2.3 From 8e29da9ee8958cc17e27f4053420f1c982614793 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 1 Jul 2008 22:38:18 +0200 Subject: i2c: Fix bad hint about irqs in i2c.h i2c.h mentions -1 as a not-issued irq. This false hint was taken by of_i2c and caused crashes. Don't give any advice as 'no irq' is not consistent across all architectures yet and it is not needed internally by the i2c-core. Signed-off-by: Wolfram Sang Signed-off-by: Jean Delvare --- include/linux/i2c.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/i2c.h b/include/linux/i2c.h index fb9af6a0fe9..8dc73013219 100644 --- a/include/linux/i2c.h +++ b/include/linux/i2c.h @@ -171,7 +171,7 @@ struct i2c_client { struct i2c_adapter *adapter; /* the adapter we sit on */ struct i2c_driver *driver; /* and our access routines */ struct device dev; /* the device structure */ - int irq; /* irq issued by device (or -1) */ + int irq; /* irq issued by device */ struct list_head list; /* DEPRECATED */ struct completion released; }; -- cgit v1.2.3 From ff31ab56c0e900235f653e375fc3b01ba2d8d6a3 Mon Sep 17 00:00:00 2001 From: Patrick McHardy Date: Tue, 1 Jul 2008 19:52:38 -0700 Subject: net-sched: change tcf_destroy_chain() to clear start of filter list Pass double tcf_proto pointers to tcf_destroy_chain() to make it clear the start of the filter list for more consistency. Signed-off-by: Patrick McHardy Signed-off-by: David S. Miller --- include/net/sch_generic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/net/sch_generic.h b/include/net/sch_generic.h index ab502ec1c61..a87fc0312ed 100644 --- a/include/net/sch_generic.h +++ b/include/net/sch_generic.h @@ -178,7 +178,7 @@ extern struct Qdisc *qdisc_alloc(struct net_device *dev, struct Qdisc_ops *ops); extern struct Qdisc *qdisc_create_dflt(struct net_device *dev, struct Qdisc_ops *ops, u32 parentid); extern void tcf_destroy(struct tcf_proto *tp); -extern void tcf_destroy_chain(struct tcf_proto *fl); +extern void tcf_destroy_chain(struct tcf_proto **fl); static inline int __qdisc_enqueue_tail(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff_head *list) -- cgit v1.2.3 From 3fddd09e59cf49dc339e2de74d31a76c1f7f172f Mon Sep 17 00:00:00 2001 From: Richard Woodruff Date: Thu, 3 Jul 2008 12:24:30 +0300 Subject: ARM: OMAP: DMTimer: Optimize by adding load and start This patch optimizes the timer load and start sequence. By combining the load and start a needless posted wait can be removed from the system timer execution path. * Before patch register writes are taking up .078% @ 500MHz during idle. Address |total |min |max |avr |count|ratio% old\process\default_idle|7.369s |0.0us|999.902ms|14.477ms|509. |62.661% ld\Global\cpu_v7_do_idle|4.265s |0.0us|375.786ms|24.374ms|175. |36.270% (UNKNOWN)|17.503ms|0.us|531.080us|5.119us|3419. |0.148% r\omap_dm_timer_set_load|8.135ms|0.0us|79.887us|15.065us|540. |0.069% <-- \vmlinux-old\Global\_end|2.023ms|0.0us|4.000us|0.560us|3613. |0.017% -old\Global\__raw_readsw|1.962ms|0.0us|108.610us|9.167us|214. |0.016% old\smc91x\smc_interrupt|1.353ms|0.0us|10.212us|2.348us|576. |0.011% s/namei\__link_path_walk|1.161ms|0.0us|4.310us|0.762us| 1524. |0.009% \omap_dm_timer_write_reg|1.085ms|0.0us|126.150us|2.153us|504. |0.009% <-- * After patch timer functions do not show up in top listings for long captures. Signed-off-by: Richard Woodruff Signed-off-by: Tony Lindgren --- include/asm-arm/arch-omap/dmtimer.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/asm-arm/arch-omap/dmtimer.h b/include/asm-arm/arch-omap/dmtimer.h index fefb276ed40..02b29e8437a 100644 --- a/include/asm-arm/arch-omap/dmtimer.h +++ b/include/asm-arm/arch-omap/dmtimer.h @@ -66,6 +66,7 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer); void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source); void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value); +void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value); void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match); void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger); void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler); -- cgit v1.2.3 From 4a79acdc784c315d9c436ba2315d08f8f53b8adf Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 3 Jul 2008 12:24:31 +0300 Subject: ARM: OMAP: Add OMAP3430 base defines Add symbolic constants for OMAP3430 base addresses; include that file in hardware.h. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren --- include/asm-arm/arch-omap/hardware.h | 1 + include/asm-arm/arch-omap/omap34xx.h | 72 ++++++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+) create mode 100644 include/asm-arm/arch-omap/omap34xx.h (limited to 'include') diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h index 91d85b3417b..45fdfccbd5d 100644 --- a/include/asm-arm/arch-omap/hardware.h +++ b/include/asm-arm/arch-omap/hardware.h @@ -284,6 +284,7 @@ #include "omap1510.h" #include "omap24xx.h" #include "omap16xx.h" +#include "omap34xx.h" #ifndef __ASSEMBLER__ diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h new file mode 100644 index 00000000000..aa30c6d10ab --- /dev/null +++ b/include/asm-arm/arch-omap/omap34xx.h @@ -0,0 +1,72 @@ +/* + * include/asm-arm/arch-omap/omap34xx.h + * + * This file contains the processor specific definitions of the TI OMAP34XX. + * + * Copyright (C) 2007 Texas Instruments. + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP34XX_H +#define __ASM_ARCH_OMAP34XX_H + +/* + * Please place only base defines here and put the rest in device + * specific headers. + */ + +#define L4_34XX_BASE 0x48000000 +#define L4_WK_34XX_BASE 0x48300000 +#define L4_WK_OMAP_BASE L4_WK_34XX_BASE +#define L4_PER_34XX_BASE 0x49000000 +#define L4_PER_OMAP_BASE L4_PER_34XX_BASE +#define L4_EMU_34XX_BASE 0x54000000 +#define L4_EMU_BASE L4_EMU_34XX_BASE +#define L3_34XX_BASE 0x68000000 +#define L3_OMAP_BASE L3_34XX_BASE + +#define OMAP3430_32KSYNCT_BASE 0x48320000 +#define OMAP3430_CM_BASE 0x48004800 +#define OMAP3430_PRM_BASE 0x48306800 +#define OMAP343X_SMS_BASE 0x6C000000 +#define OMAP343X_SDRC_BASE 0x6D000000 +#define OMAP34XX_GPMC_BASE 0x6E000000 +#define OMAP343X_SCM_BASE 0x48002000 +#define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE + +#define OMAP34XX_IC_BASE 0x48200000 +#define OMAP34XX_IVA_INTC_BASE 0x40000000 +#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) +#define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000) +#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000) + + +#if defined(CONFIG_ARCH_OMAP3430) + +#define OMAP2_32KSYNCT_BASE OMAP3430_32KSYNCT_BASE +#define OMAP2_CM_BASE OMAP3430_CM_BASE +#define OMAP2_PRM_BASE OMAP3430_PRM_BASE +#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE) + +#endif + +#define OMAP34XX_DSP_BASE 0x58000000 +#define OMAP34XX_DSP_MEM_BASE (OMAP34XX_DSP_BASE + 0x0) +#define OMAP34XX_DSP_IPI_BASE (OMAP34XX_DSP_BASE + 0x1000000) +#define OMAP34XX_DSP_MMU_BASE (OMAP34XX_DSP_BASE + 0x2000000) +#endif /* __ASM_ARCH_OMAP34XX_H */ + -- cgit v1.2.3 From 4d96372e6daae89166fed7883ee092dc8db80b21 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Jul 2008 12:24:31 +0300 Subject: ARM: OMAP: DMA: Make channels dynamic for multi-boot Make DMA channels dynamic for multi-boot Signed-off-by: Tony Lindgren --- include/asm-arm/arch-omap/dma.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h index 24acf090030..46fe5a40a25 100644 --- a/include/asm-arm/arch-omap/dma.h +++ b/include/asm-arm/arch-omap/dma.h @@ -68,9 +68,10 @@ #define OMAP_DMA4_CAPS_3 (OMAP_DMA4_BASE + 0x70) #define OMAP_DMA4_CAPS_4 (OMAP_DMA4_BASE + 0x74) -#ifdef CONFIG_ARCH_OMAP1 +#define OMAP1_LOGICAL_DMA_CH_COUNT 17 +#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ -#define OMAP_LOGICAL_DMA_CH_COUNT 17 +#ifdef CONFIG_ARCH_OMAP1 /* Common channel specific registers for omap1 */ #define OMAP_DMA_CSDP_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00) @@ -89,8 +90,6 @@ #else -#define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ - /* Common channel specific registers for omap2 */ #define OMAP_DMA_CCR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80) #define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84) -- cgit v1.2.3 From 0499bdeb1dec30325aa282a83f9374fa849aa01c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Jul 2008 12:24:36 +0300 Subject: ARM: OMAP: DMA: Remove __REG access Remove __REG access in DMA code, use dma_read/write instead: - dynamically set the omap_dma_base based on the omap type - omap_read/write becomes dma_read/write - dma channel registers are read with dma_ch_read/write Cc: David Brownell Cc: linux-usb@vger.kernel.org Signed-off-by: Tony Lindgren --- include/asm-arm/arch-omap/dma.h | 210 +++++++++++++++++++++++----------------- 1 file changed, 120 insertions(+), 90 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h index 46fe5a40a25..d188100f8f4 100644 --- a/include/asm-arm/arch-omap/dma.h +++ b/include/asm-arm/arch-omap/dma.h @@ -22,107 +22,128 @@ #define __ASM_ARCH_DMA_H /* Hardware registers for omap1 */ -#define OMAP_DMA_BASE (0xfffed800) -#define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400) -#define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404) -#define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408) -#define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442) -#define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444) -#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446) -#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448) -#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a) -#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c) -#define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e) -#define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450) -#define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452) -#define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454) -#define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456) -#define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458) -#define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a) -#define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460) -#define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480) -#define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482) -#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0) - -/* Hardware registers for omap2 */ -#if defined(CONFIG_ARCH_OMAP3) -#define OMAP_DMA4_BASE (L4_34XX_BASE + 0x56000) -#else /* CONFIG_ARCH_OMAP2 */ -#define OMAP_DMA4_BASE (L4_24XX_BASE + 0x56000) -#endif - -#define OMAP_DMA4_REVISION (OMAP_DMA4_BASE + 0x00) -#define OMAP_DMA4_GCR_REG (OMAP_DMA4_BASE + 0x78) -#define OMAP_DMA4_IRQSTATUS_L0 (OMAP_DMA4_BASE + 0x08) -#define OMAP_DMA4_IRQSTATUS_L1 (OMAP_DMA4_BASE + 0x0c) -#define OMAP_DMA4_IRQSTATUS_L2 (OMAP_DMA4_BASE + 0x10) -#define OMAP_DMA4_IRQSTATUS_L3 (OMAP_DMA4_BASE + 0x14) -#define OMAP_DMA4_IRQENABLE_L0 (OMAP_DMA4_BASE + 0x18) -#define OMAP_DMA4_IRQENABLE_L1 (OMAP_DMA4_BASE + 0x1c) -#define OMAP_DMA4_IRQENABLE_L2 (OMAP_DMA4_BASE + 0x20) -#define OMAP_DMA4_IRQENABLE_L3 (OMAP_DMA4_BASE + 0x24) -#define OMAP_DMA4_SYSSTATUS (OMAP_DMA4_BASE + 0x28) -#define OMAP_DMA4_OCP_SYSCONFIG (OMAP_DMA4_BASE + 0x2c) -#define OMAP_DMA4_CAPS_0 (OMAP_DMA4_BASE + 0x64) -#define OMAP_DMA4_CAPS_2 (OMAP_DMA4_BASE + 0x6c) -#define OMAP_DMA4_CAPS_3 (OMAP_DMA4_BASE + 0x70) -#define OMAP_DMA4_CAPS_4 (OMAP_DMA4_BASE + 0x74) +#define OMAP1_DMA_BASE (0xfffed800) + +#define OMAP1_DMA_GCR 0x400 +#define OMAP1_DMA_GSCR 0x404 +#define OMAP1_DMA_GRST 0x408 +#define OMAP1_DMA_HW_ID 0x442 +#define OMAP1_DMA_PCH2_ID 0x444 +#define OMAP1_DMA_PCH0_ID 0x446 +#define OMAP1_DMA_PCH1_ID 0x448 +#define OMAP1_DMA_PCHG_ID 0x44a +#define OMAP1_DMA_PCHD_ID 0x44c +#define OMAP1_DMA_CAPS_0_U 0x44e +#define OMAP1_DMA_CAPS_0_L 0x450 +#define OMAP1_DMA_CAPS_1_U 0x452 +#define OMAP1_DMA_CAPS_1_L 0x454 +#define OMAP1_DMA_CAPS_2 0x456 +#define OMAP1_DMA_CAPS_3 0x458 +#define OMAP1_DMA_CAPS_4 0x45a +#define OMAP1_DMA_PCH2_SR 0x460 +#define OMAP1_DMA_PCH0_SR 0x480 +#define OMAP1_DMA_PCH1_SR 0x482 +#define OMAP1_DMA_PCHD_SR 0x4c0 + +/* Hardware registers for omap2 and omap3 */ +#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000) +#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000) + +#define OMAP_DMA4_REVISION 0x00 +#define OMAP_DMA4_GCR 0x78 +#define OMAP_DMA4_IRQSTATUS_L0 0x08 +#define OMAP_DMA4_IRQSTATUS_L1 0x0c +#define OMAP_DMA4_IRQSTATUS_L2 0x10 +#define OMAP_DMA4_IRQSTATUS_L3 0x14 +#define OMAP_DMA4_IRQENABLE_L0 0x18 +#define OMAP_DMA4_IRQENABLE_L1 0x1c +#define OMAP_DMA4_IRQENABLE_L2 0x20 +#define OMAP_DMA4_IRQENABLE_L3 0x24 +#define OMAP_DMA4_SYSSTATUS 0x28 +#define OMAP_DMA4_OCP_SYSCONFIG 0x2c +#define OMAP_DMA4_CAPS_0 0x64 +#define OMAP_DMA4_CAPS_2 0x6c +#define OMAP_DMA4_CAPS_3 0x70 +#define OMAP_DMA4_CAPS_4 0x74 #define OMAP1_LOGICAL_DMA_CH_COUNT 17 #define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ -#ifdef CONFIG_ARCH_OMAP1 - /* Common channel specific registers for omap1 */ -#define OMAP_DMA_CSDP_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00) -#define OMAP_DMA_CCR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02) -#define OMAP_DMA_CICR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04) -#define OMAP_DMA_CSR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06) -#define OMAP_DMA_CEN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10) -#define OMAP_DMA_CFN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12) -#define OMAP_DMA_CSFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14) -#define OMAP_DMA_CSEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16) -#define OMAP_DMA_CSAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18) -#define OMAP_DMA_CDAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a) -#define OMAP_DMA_CDEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c) -#define OMAP_DMA_CDFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e) -#define OMAP_DMA_CLNK_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28) - -#else +#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00) +#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00) +#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02) +#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04) +#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06) +#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10) +#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12) +#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14) +#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16) +#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */ +#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18) +#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a) +#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c) +#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e) +#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28) /* Common channel specific registers for omap2 */ -#define OMAP_DMA_CCR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80) -#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84) -#define OMAP_DMA_CICR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88) -#define OMAP_DMA_CSR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c) -#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90) -#define OMAP_DMA_CEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94) -#define OMAP_DMA_CFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98) -#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4) -#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8) -#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac) -#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0) -#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4) -#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8) - -#endif +#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80) +#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80) +#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84) +#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88) +#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c) +#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90) +#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94) +#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98) +#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4) +#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8) +#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac) +#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0) +#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4) +#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8) /* Channel specific registers only on omap1 */ -#define OMAP1_DMA_CSSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08) -#define OMAP1_DMA_CSSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a) -#define OMAP1_DMA_CDSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c) -#define OMAP1_DMA_CDSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e) -#define OMAP1_DMA_COLOR_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20) -#define OMAP1_DMA_CCR2_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24) -#define OMAP1_DMA_COLOR_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22) -#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a) +#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08) +#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a) +#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c) +#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e) +#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20) +#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22) +#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24) +#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */ +#define OMAP1_DMA_CCEN(n) 0 +#define OMAP1_DMA_CCFN(n) 0 /* Channel specific registers only on omap2 */ -#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c) -#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0) -#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc) -#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0) -#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4) +#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c) +#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0) +#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc) +#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0) +#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4) + +/* Dummy defines to keep multi-omap compiles happy */ +#define OMAP1_DMA_REVISION 0 +#define OMAP1_DMA_IRQSTATUS_L0 0 +#define OMAP1_DMA_IRQENABLE_L0 0 +#define OMAP1_DMA_OCP_SYSCONFIG 0 +#define OMAP_DMA4_HW_ID 0 +#define OMAP_DMA4_CAPS_0_L 0 +#define OMAP_DMA4_CAPS_0_U 0 +#define OMAP_DMA4_CAPS_1_L 0 +#define OMAP_DMA4_CAPS_1_U 0 +#define OMAP_DMA4_GSCR 0 +#define OMAP_DMA4_CPC(n) 0 + +#define OMAP_DMA4_LCH_CTRL(n) 0 +#define OMAP_DMA4_COLOR_L(n) 0 +#define OMAP_DMA4_COLOR_U(n) 0 +#define OMAP_DMA4_CCR2(n) 0 +#define OMAP1_DMA_CSSA(n) 0 +#define OMAP1_DMA_CDSA(n) 0 +#define OMAP_DMA4_CSSA_L(n) 0 +#define OMAP_DMA4_CSSA_U(n) 0 +#define OMAP_DMA4_CDSA_L(n) 0 +#define OMAP_DMA4_CDSA_U(n) 0 /*----------------------------------------------------------------------------*/ @@ -369,6 +390,13 @@ enum omap_dma_write_mode { OMAP_DMA_WRITE_LAST_NON_POSTED }; +enum omap_dma_channel_mode { + OMAP_DMA_LCH_2D = 0, + OMAP_DMA_LCH_G, + OMAP_DMA_LCH_P, + OMAP_DMA_LCH_PD +}; + struct omap_dma_channel_params { int data_type; /* data type 8,16,32 */ int elem_count; /* number of elements in a frame */ @@ -417,6 +445,7 @@ extern void omap_set_dma_transfer_params(int lch, int data_type, extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color); extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode); +extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode); extern void omap_set_dma_src_params(int lch, int src_port, int src_amode, unsigned long src_start, @@ -447,6 +476,7 @@ extern dma_addr_t omap_get_dma_src_pos(int lch); extern dma_addr_t omap_get_dma_dst_pos(int lch); extern int omap_get_dma_src_addr_counter(int lch); extern void omap_clear_dma(int lch); +extern int omap_get_dma_active_status(int lch); extern int omap_dma_running(void); extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams); -- cgit v1.2.3 From 97b7f715589fb997e430c6aa824abbd9fd5ed42d Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Jul 2008 12:24:37 +0300 Subject: ARM: OMAP: DMA: Clean-up code DMA clean-up, mostly checkpatch.pl fixes. Signed-off-by: Tony Lindgren --- include/asm-arm/arch-omap/dma.h | 161 +++++++++++++++++++++++++--------------- 1 file changed, 103 insertions(+), 58 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h index d188100f8f4..f4dcb958786 100644 --- a/include/asm-arm/arch-omap/dma.h +++ b/include/asm-arm/arch-omap/dma.h @@ -216,63 +216,98 @@ #define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ #define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */ #define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */ -#define OMAP24XX_DMA_VLYNQ_TX 7 /* S_DMA_6 */ +#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */ +#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */ #define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */ #define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */ #define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */ #define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */ #define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */ #define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */ -#define OMAP24XX_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */ -#define OMAP24XX_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */ -#define OMAP24XX_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */ -#define OMAP24XX_DMA_EAC_AC_RD 17 /* S_DMA_16 */ -#define OMAP24XX_DMA_EAC_AC_WR 18 /* S_DMA_17 */ -#define OMAP24XX_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */ -#define OMAP24XX_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */ -#define OMAP24XX_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */ -#define OMAP24XX_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */ -#define OMAP24XX_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */ -#define OMAP24XX_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */ -#define OMAP24XX_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */ -#define OMAP24XX_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */ +#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */ +#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */ +#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */ +#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */ +#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */ +#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */ +#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */ +#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */ +#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */ +#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */ +#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */ +#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */ +#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */ +#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */ +#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */ +#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */ +#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */ +#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */ +#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */ +#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */ +#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */ +#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */ +#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */ +#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */ +#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */ +#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */ +#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */ +#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */ +#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */ #define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */ #define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */ #define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */ #define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */ -#define OMAP24XX_DMA_MCBSP1_TX 31 /* SDMA_30 */ -#define OMAP24XX_DMA_MCBSP1_RX 32 /* SDMA_31 */ -#define OMAP24XX_DMA_MCBSP2_TX 33 /* SDMA_32 */ -#define OMAP24XX_DMA_MCBSP2_RX 34 /* SDMA_33 */ -#define OMAP24XX_DMA_SPI1_TX0 35 /* SDMA_34 */ -#define OMAP24XX_DMA_SPI1_RX0 36 /* SDMA_35 */ -#define OMAP24XX_DMA_SPI1_TX1 37 /* SDMA_36 */ -#define OMAP24XX_DMA_SPI1_RX1 38 /* SDMA_37 */ -#define OMAP24XX_DMA_SPI1_TX2 39 /* SDMA_38 */ -#define OMAP24XX_DMA_SPI1_RX2 40 /* SDMA_39 */ -#define OMAP24XX_DMA_SPI1_TX3 41 /* SDMA_40 */ -#define OMAP24XX_DMA_SPI1_RX3 42 /* SDMA_41 */ -#define OMAP24XX_DMA_SPI2_TX0 43 /* SDMA_42 */ -#define OMAP24XX_DMA_SPI2_RX0 44 /* SDMA_43 */ -#define OMAP24XX_DMA_SPI2_TX1 45 /* SDMA_44 */ -#define OMAP24XX_DMA_SPI2_RX1 46 /* SDMA_45 */ - -#define OMAP24XX_DMA_UART1_TX 49 /* SDMA_48 */ -#define OMAP24XX_DMA_UART1_RX 50 /* SDMA_49 */ -#define OMAP24XX_DMA_UART2_TX 51 /* SDMA_50 */ -#define OMAP24XX_DMA_UART2_RX 52 /* SDMA_51 */ -#define OMAP24XX_DMA_UART3_TX 53 /* SDMA_52 */ -#define OMAP24XX_DMA_UART3_RX 54 /* SDMA_53 */ -#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* SDMA_54 */ -#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* SDMA_55 */ -#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* SDMA_56 */ -#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* SDMA_57 */ -#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* SDMA_58 */ -#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* SDMA_59 */ -#define OMAP24XX_DMA_MMC1_TX 61 /* SDMA_60 */ -#define OMAP24XX_DMA_MMC1_RX 62 /* SDMA_61 */ -#define OMAP24XX_DMA_MS 63 /* SDMA_62 */ -#define OMAP24XX_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */ +#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */ +#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */ +#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */ +#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */ +#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */ +#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */ +#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */ +#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */ +#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */ +#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */ +#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */ +#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */ +#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */ +#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */ +#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */ +#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */ +#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */ +#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */ +#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */ +#define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */ +#define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */ +#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */ +#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */ +#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */ +#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */ +#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */ +#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */ +#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */ +#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */ +#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */ +#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */ +#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */ +#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */ +#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */ +#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */ +#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */ +#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */ +#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */ +#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */ +#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */ +#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */ +#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */ +#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */ +#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */ +#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */ +#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */ +#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */ +#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */ +#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */ +#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ +#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ /*----------------------------------------------------------------------------*/ @@ -378,6 +413,11 @@ enum omap_dma_burst_mode { OMAP_DMA_DATA_BURST_16, }; +enum end_type { + OMAP_DMA_LITTLE_ENDIAN = 0, + OMAP_DMA_BIG_ENDIAN +}; + enum omap_dma_color_mode { OMAP_DMA_COLOR_DIS = 0, OMAP_DMA_CONSTANT_FILL, @@ -403,18 +443,21 @@ struct omap_dma_channel_params { int frame_count; /* number of frames in a element */ int src_port; /* Only on OMAP1 REVISIT: Is this needed? */ - int src_amode; /* constant , post increment, indexed , double indexed */ + int src_amode; /* constant, post increment, indexed, + double indexed */ unsigned long src_start; /* source address : physical */ int src_ei; /* source element index */ int src_fi; /* source frame index */ int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */ - int dst_amode; /* constant , post increment, indexed , double indexed */ + int dst_amode; /* constant, post increment, indexed, + double indexed */ unsigned long dst_start; /* source address : physical */ int dst_ei; /* source element index */ int dst_fi; /* source frame index */ - int trigger; /* trigger attached if the channel is synchronized */ + int trigger; /* trigger attached if the channel is + synchronized */ int sync_mode; /* sycn on element, frame , block or packet */ int src_or_dst_synch; /* source synch(1) or destination synch(0) */ @@ -431,8 +474,8 @@ struct omap_dma_channel_params { extern void omap_set_dma_priority(int lch, int dst_port, int priority); extern int omap_request_dma(int dev_id, const char *dev_name, - void (* callback)(int lch, u16 ch_status, void *data), - void *data, int *dma_ch); + void (*callback)(int lch, u16 ch_status, void *data), + void *data, int *dma_ch); extern void omap_enable_dma_irq(int ch, u16 irq_bits); extern void omap_disable_dma_irq(int ch, u16 irq_bits); extern void omap_free_dma(int ch); @@ -464,17 +507,16 @@ extern void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode); extern void omap_set_dma_params(int lch, - struct omap_dma_channel_params * params); + struct omap_dma_channel_params *params); -extern void omap_dma_link_lch (int lch_head, int lch_queue); -extern void omap_dma_unlink_lch (int lch_head, int lch_queue); +extern void omap_dma_link_lch(int lch_head, int lch_queue); +extern void omap_dma_unlink_lch(int lch_head, int lch_queue); extern int omap_set_dma_callback(int lch, - void (* callback)(int lch, u16 ch_status, void *data), + void (*callback)(int lch, u16 ch_status, void *data), void *data); extern dma_addr_t omap_get_dma_src_pos(int lch); extern dma_addr_t omap_get_dma_dst_pos(int lch); -extern int omap_get_dma_src_addr_counter(int lch); extern void omap_clear_dma(int lch); extern int omap_get_dma_active_status(int lch); extern int omap_dma_running(void); @@ -482,6 +524,9 @@ extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams); extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio, unsigned char write_prio); +extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype); +extern void omap_set_dma_src_endian_type(int lch, enum end_type etype); +extern int omap_get_dma_index(int lch, int *ei, int *fi); /* Chaining APIs */ #ifndef CONFIG_ARCH_OMAP1 @@ -507,7 +552,7 @@ extern int omap_dma_chain_status(int chain_id); #endif /* LCD DMA functions */ -extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data), +extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data), void *data); extern void omap_free_lcd_dma(void); extern void omap_setup_lcd_dma(void); -- cgit v1.2.3 From c2d43e39c7c303db53facd0bea44b66f263e3f35 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Jul 2008 12:24:38 +0300 Subject: ARM: OMAP: SRAM: Split sram24xx.S into sram242x.S and sram243x.S Split sram24xx.S into sram242x.S and sram243x.S Signed-off-by: Tony Lindgren --- include/asm-arm/arch-omap/sram.h | 37 ++++++++++++++++++++++++++++--------- 1 file changed, 28 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h index bb9bb3fd532..be59f4a9828 100644 --- a/include/asm-arm/arch-omap/sram.h +++ b/include/asm-arm/arch-omap/sram.h @@ -11,6 +11,7 @@ #ifndef __ARCH_ARM_OMAP_SRAM_H #define __ARCH_ARM_OMAP_SRAM_H +extern int __init omap_sram_init(void); extern void * omap_sram_push(void * start, unsigned long size); extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); @@ -21,17 +22,35 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); /* Do not use these */ -extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl); -extern unsigned long sram_reprogram_clock_sz; +extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); +extern unsigned long omap1_sram_reprogram_clock_sz; -extern void sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, - u32 base_cs, u32 force_unlock); -extern unsigned long sram_ddr_init_sz; +extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl); +extern unsigned long omap24xx_sram_reprogram_clock_sz; -extern u32 sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); -extern unsigned long sram_set_prcm_sz; +extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, + u32 base_cs, u32 force_unlock); +extern unsigned long omap242x_sram_ddr_init_sz; -extern void sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type); -extern unsigned long sram_reprogram_sdrc_sz; +extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, + int bypass); +extern unsigned long omap242x_sram_set_prcm_sz; + +extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, + u32 mem_type); +extern unsigned long omap242x_sram_reprogram_sdrc_sz; + + +extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, + u32 base_cs, u32 force_unlock); +extern unsigned long omap243x_sram_ddr_init_sz; + +extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, + int bypass); +extern unsigned long omap243x_sram_set_prcm_sz; + +extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, + u32 mem_type); +extern unsigned long omap243x_sram_reprogram_sdrc_sz; #endif -- cgit v1.2.3 From bc5d0c89c88df67f92d5d5882c27437379e9e8af Mon Sep 17 00:00:00 2001 From: Eduardo Valentin Date: Thu, 3 Jul 2008 12:24:39 +0300 Subject: ARM: OMAP: McBSP: Prepare for splitting into omap1 and omap2 code This patch transform mcbsp code to use platform data from arch/arm/plat-omap/devices.c It also gets ride of ifdefs on mcbsp.c code. To do it, a platform data structure was defined. Signed-off-by: Eduardo Valentin Signed-off-by: Tony Lindgren --- include/asm-arm/arch-omap/mcbsp.h | 62 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 60 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-omap/mcbsp.h b/include/asm-arm/arch-omap/mcbsp.h index c7a0cc1c4e9..26c78f67dc8 100644 --- a/include/asm-arm/arch-omap/mcbsp.h +++ b/include/asm-arm/arch-omap/mcbsp.h @@ -24,7 +24,11 @@ #ifndef __ASM_ARCH_OMAP_MCBSP_H #define __ASM_ARCH_OMAP_MCBSP_H +#include +#include + #include +#include #define OMAP730_MCBSP1_BASE 0xfffb1000 #define OMAP730_MCBSP2_BASE 0xfffb1800 @@ -40,6 +44,9 @@ #define OMAP24XX_MCBSP1_BASE 0x48074000 #define OMAP24XX_MCBSP2_BASE 0x48076000 +#define OMAP34XX_MCBSP1_BASE 0x48074000 +#define OMAP34XX_MCBSP2_BASE 0x49022000 + #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) #define OMAP_MCBSP_REG_DRR2 0x00 @@ -74,7 +81,8 @@ #define OMAP_MCBSP_REG_XCERG 0x3A #define OMAP_MCBSP_REG_XCERH 0x3C -#define OMAP_MAX_MCBSP_COUNT 3 +#define OMAP_MAX_MCBSP_COUNT 3 +#define MAX_MCBSP_CLOCKS 3 #define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1) #define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1) @@ -117,7 +125,8 @@ #define OMAP_MCBSP_REG_XCERG 0x74 #define OMAP_MCBSP_REG_XCERH 0x78 -#define OMAP_MAX_MCBSP_COUNT 2 +#define OMAP_MAX_MCBSP_COUNT 2 +#define MAX_MCBSP_CLOCKS 2 #define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1) #define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1) @@ -298,6 +307,55 @@ struct omap_mcbsp_spi_cfg { omap_mcbsp_word_length word_length; }; +/* Platform specific configuration */ +struct omap_mcbsp_ops { + void (*request)(unsigned int); + void (*free)(unsigned int); + int (*check)(unsigned int); +}; + +struct omap_mcbsp_platform_data { + u32 virt_base; + u8 dma_rx_sync, dma_tx_sync; + u16 rx_irq, tx_irq; + struct omap_mcbsp_ops *ops; + char const *clk_name; +}; + +struct omap_mcbsp { + struct device *dev; + u32 io_base; + u8 id; + u8 free; + omap_mcbsp_word_length rx_word_length; + omap_mcbsp_word_length tx_word_length; + + omap_mcbsp_io_type_t io_type; /* IRQ or poll */ + /* IRQ based TX/RX */ + int rx_irq; + int tx_irq; + + /* DMA stuff */ + u8 dma_rx_sync; + short dma_rx_lch; + u8 dma_tx_sync; + short dma_tx_lch; + + /* Completion queues */ + struct completion tx_irq_completion; + struct completion rx_irq_completion; + struct completion tx_dma_completion; + struct completion rx_dma_completion; + + /* Protect the field .free, while checking if the mcbsp is in use */ + spinlock_t lock; + struct omap_mcbsp_platform_data *pdata; + struct clk *clk; +}; + +int omap_mcbsp_init(void); +void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, + int size); void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); int omap_mcbsp_request(unsigned int id); void omap_mcbsp_free(unsigned int id); -- cgit v1.2.3 From 44f78f43b349d19d378a996c4a2d9fcdff771b1e Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Jul 2008 12:24:41 +0300 Subject: ARM: OMAP: Clean up interrupt lines to fix warnings for multi-omap If boards with different NR_IRQS are compiled together, tons of compiler warnings are emitted about redefining NR_IRQS. This patch fixes the problem by adding up NR_IRQS in a common place. Patch also removes quite a bit of now unnecessary code. Signed-off-by: Tony Lindgren --- include/asm-arm/arch-omap/board-2430sdp.h | 5 --- include/asm-arm/arch-omap/board-h3.h | 6 ---- include/asm-arm/arch-omap/board-innovator.h | 3 -- include/asm-arm/arch-omap/board-perseus2.h | 6 ---- include/asm-arm/arch-omap/fpga.h | 49 ++++++++++++++--------------- include/asm-arm/arch-omap/irqs.h | 44 ++++++++++++++++++++------ 6 files changed, 59 insertions(+), 54 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-omap/board-2430sdp.h b/include/asm-arm/arch-omap/board-2430sdp.h index e9c65ce3cb1..c7db9004ec3 100644 --- a/include/asm-arm/arch-omap/board-2430sdp.h +++ b/include/asm-arm/arch-omap/board-2430sdp.h @@ -36,9 +36,4 @@ #define TWL4030_IRQNUM INT_24XX_SYS_NIRQ -/* TWL4030 Primary Interrupt Handler (PIH) interrupts */ -#define IH_TWL4030_BASE IH_BOARD_BASE -#define IH_TWL4030_END (IH_TWL4030_BASE+8) -#define NR_IRQS (IH_TWL4030_END) - #endif /* __ASM_ARCH_OMAP_2430SDP_H */ diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h index 0f6404435ea..c5d0f32a40a 100644 --- a/include/asm-arm/arch-omap/board-h3.h +++ b/include/asm-arm/arch-omap/board-h3.h @@ -30,12 +30,6 @@ /* In OMAP1710 H3 the Ethernet is directly connected to CS1 */ #define OMAP1710_ETHR_START 0x04000300 -#define MAXIRQNUM (IH_BOARD_BASE) -#define MAXFIQNUM MAXIRQNUM -#define MAXSWINUM MAXIRQNUM - -#define NR_IRQS (MAXIRQNUM + 1) - extern void h3_mmc_init(void); extern void h3_mmc_slot_cover_handler(void *arg, int state); diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h index 56d2c98e143..9ca03dec9d3 100644 --- a/include/asm-arm/arch-omap/board-innovator.h +++ b/include/asm-arm/arch-omap/board-innovator.h @@ -36,9 +36,6 @@ #define OMAP1510P1_EMIFS_PRI_VALUE 0x00 #define OMAP1510P1_EMIFF_PRI_VALUE 0x00 -#define NR_FPGA_IRQS 24 -#define NR_IRQS (IH_BOARD_BASE + NR_FPGA_IRQS) - #ifndef __ASSEMBLY__ void fpga_write(unsigned char val, int reg); unsigned char fpga_read(int reg); diff --git a/include/asm-arm/arch-omap/board-perseus2.h b/include/asm-arm/arch-omap/board-perseus2.h index eb74420cb43..d7429cb0f72 100644 --- a/include/asm-arm/arch-omap/board-perseus2.h +++ b/include/asm-arm/arch-omap/board-perseus2.h @@ -36,10 +36,4 @@ #define OMAP_SDRAM_DEVICE D256M_1X16_4B #endif -#define MAXIRQNUM IH_BOARD_BASE -#define MAXFIQNUM MAXIRQNUM -#define MAXSWINUM MAXIRQNUM - -#define NR_IRQS (MAXIRQNUM + 1) - #endif diff --git a/include/asm-arm/arch-omap/fpga.h b/include/asm-arm/arch-omap/fpga.h index 6a883e0bdbb..f420881d2a3 100644 --- a/include/asm-arm/arch-omap/fpga.h +++ b/include/asm-arm/arch-omap/fpga.h @@ -169,30 +169,29 @@ struct h2p2_dbg_fpga { #define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13) /* IRQ Numbers for interrupts muxed through the FPGA */ -#define OMAP1510_IH_FPGA_BASE IH_BOARD_BASE -#define OMAP1510_INT_FPGA_ATN (OMAP1510_IH_FPGA_BASE + 0) -#define OMAP1510_INT_FPGA_ACK (OMAP1510_IH_FPGA_BASE + 1) -#define OMAP1510_INT_FPGA2 (OMAP1510_IH_FPGA_BASE + 2) -#define OMAP1510_INT_FPGA3 (OMAP1510_IH_FPGA_BASE + 3) -#define OMAP1510_INT_FPGA4 (OMAP1510_IH_FPGA_BASE + 4) -#define OMAP1510_INT_FPGA5 (OMAP1510_IH_FPGA_BASE + 5) -#define OMAP1510_INT_FPGA6 (OMAP1510_IH_FPGA_BASE + 6) -#define OMAP1510_INT_FPGA7 (OMAP1510_IH_FPGA_BASE + 7) -#define OMAP1510_INT_FPGA8 (OMAP1510_IH_FPGA_BASE + 8) -#define OMAP1510_INT_FPGA9 (OMAP1510_IH_FPGA_BASE + 9) -#define OMAP1510_INT_FPGA10 (OMAP1510_IH_FPGA_BASE + 10) -#define OMAP1510_INT_FPGA11 (OMAP1510_IH_FPGA_BASE + 11) -#define OMAP1510_INT_FPGA12 (OMAP1510_IH_FPGA_BASE + 12) -#define OMAP1510_INT_ETHER (OMAP1510_IH_FPGA_BASE + 13) -#define OMAP1510_INT_FPGAUART1 (OMAP1510_IH_FPGA_BASE + 14) -#define OMAP1510_INT_FPGAUART2 (OMAP1510_IH_FPGA_BASE + 15) -#define OMAP1510_INT_FPGA_TS (OMAP1510_IH_FPGA_BASE + 16) -#define OMAP1510_INT_FPGA17 (OMAP1510_IH_FPGA_BASE + 17) -#define OMAP1510_INT_FPGA_CAM (OMAP1510_IH_FPGA_BASE + 18) -#define OMAP1510_INT_FPGA_RTC_A (OMAP1510_IH_FPGA_BASE + 19) -#define OMAP1510_INT_FPGA_RTC_B (OMAP1510_IH_FPGA_BASE + 20) -#define OMAP1510_INT_FPGA_CD (OMAP1510_IH_FPGA_BASE + 21) -#define OMAP1510_INT_FPGA22 (OMAP1510_IH_FPGA_BASE + 22) -#define OMAP1510_INT_FPGA23 (OMAP1510_IH_FPGA_BASE + 23) +#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0) +#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1) +#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2) +#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3) +#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4) +#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5) +#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6) +#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7) +#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8) +#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9) +#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10) +#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11) +#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12) +#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13) +#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14) +#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15) +#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16) +#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17) +#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18) +#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19) +#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20) +#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21) +#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22) +#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23) #endif diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h index 87973654e62..7464c694859 100644 --- a/include/asm-arm/arch-omap/irqs.h +++ b/include/asm-arm/arch-omap/irqs.h @@ -285,7 +285,41 @@ #define OMAP_MAX_GPIO_LINES 192 #define IH_GPIO_BASE (128 + IH2_BASE) #define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) -#define IH_BOARD_BASE (16 + IH_MPUIO_BASE) +#define OMAP_IRQ_END (IH_MPUIO_BASE + 16) + +/* External FPGA handles interrupts on Innovator boards */ +#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END) +#ifdef CONFIG_MACH_OMAP_INNOVATOR +#define OMAP_FPGA_NR_IRQS 24 +#else +#define OMAP_FPGA_NR_IRQS 0 +#endif +#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS) + +/* External TWL4030 can handle interrupts on 2430 and 34xx boards */ +#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END) +#ifdef CONFIG_TWL4030_CORE +#define TWL4030_BASE_NR_IRQS 8 +#define TWL4030_PWR_NR_IRQS 8 +#else +#define TWL4030_BASE_NR_IRQS 0 +#define TWL4030_PWR_NR_IRQS 0 +#endif +#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS) +#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END +#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS) + +/* External TWL4030 gpio interrupts are optional */ +#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END +#ifdef CONFIG_TWL4030_GPIO +#define TWL4030_GPIO_NR_IRQS 18 +#else +#define TWL4030_GPIO_NR_IRQS 0 +#endif +#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS) + +/* Total number of interrupts depends on the enabled blocks above */ +#define NR_IRQS TWL4030_GPIO_IRQ_END #define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) @@ -293,14 +327,6 @@ extern void omap_init_irq(void); #endif -/* - * The definition of NR_IRQS is in board-specific header file, which is - * included via hardware.h - */ #include -#ifndef NR_IRQS -#define NR_IRQS IH_BOARD_BASE -#endif - #endif -- cgit v1.2.3 From 137b3ee27ab1b27dba081542476054836978ca45 Mon Sep 17 00:00:00 2001 From: Hiroshi DOYU Date: Thu, 3 Jul 2008 12:24:41 +0300 Subject: ARM: OMAP: CLKFW: Initial debugfs support for omap clock framework debugfs can provide the infrastructure to trace the dependencies of clock tree hierarchy quite visibly. This patch enables to keep track of clock tree hierarchy and expose their attributes under each clock directry as below: omap:~# tree -d -L 2 /debug/clock/omap_32k_fck/ /debug/clock/omap_32k_fck/ |-- gpt10_fck |-- gpt11_fck |-- gpt1_fck |-- per_32k_alwon_fck | |-- gpio2_fck | |-- gpio3_fck | |-- gpio4_fck | |-- gpio5_fck | |-- gpio6_fck | `-- wdt3_fck |-- ts_fck `-- wkup_32k_fck |-- gpio1_fck `-- wdt2_fck 14 directories omap:~# tree /debug/clock/omap_32k_fck/gpt10_fck/ /debug/clock/omap_32k_fck/gpt10_fck/ |-- flags |-- rate `-- usecount 0 directories, 3 files Although, compared with David Brownell's small patch, this may look bit overkilling, I expect that this debugfs can deal with other PRCM complexities at the same time. For example, powerdomain dependencies can be expressed by using symbolic links of these clocks if powerdomain supports dubgfs as well. Signed-off-by: Hiroshi DOYU Signed-off-by: Tony Lindgren --- include/asm-arm/arch-omap/clock.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h index 12a5e4de951..8490fbba39d 100644 --- a/include/asm-arm/arch-omap/clock.h +++ b/include/asm-arm/arch-omap/clock.h @@ -71,6 +71,9 @@ struct clk { __u8 rate_offset; __u8 src_offset; #endif +#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) + struct dentry *dent; /* For visible tree hierarchy */ +#endif }; struct cpufreq_frequency_table; -- cgit v1.2.3 From 030b15457d8069a6255579a28db196e002cb9c86 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Jul 2008 12:24:41 +0300 Subject: ARM: OMAP: Change omap_cf.c and omap_nor.c to use omap_readw/writew instead of __REG Change omap_cf.c and omap_nor.c to use omap_readw/writew instead of __REG. This is needed for multi-omap in the future. Cc: David Brownell Cc: linux-pcmcia@lists.infradead.org Cc: linux-mtd@lists.infradead.org Signed-off-by: Tony Lindren --- include/asm-arm/arch-omap/tc.h | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-omap/tc.h b/include/asm-arm/arch-omap/tc.h index 8ded218cbea..65a9c82d3bf 100644 --- a/include/asm-arm/arch-omap/tc.h +++ b/include/asm-arm/arch-omap/tc.h @@ -75,16 +75,14 @@ #ifndef __ASSEMBLER__ /* EMIF Slow Interface Configuration Register */ -#define OMAP_EMIFS_CONFIG_REG __REG32(EMIFS_CONFIG) - #define OMAP_EMIFS_CONFIG_FR (1 << 4) #define OMAP_EMIFS_CONFIG_PDE (1 << 3) #define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2) #define OMAP_EMIFS_CONFIG_BM (1 << 1) #define OMAP_EMIFS_CONFIG_WP (1 << 0) -#define EMIFS_CCS(n) __REG32(EMIFS_CS0_CONFIG + (4 * (n))) -#define EMIFS_ACS(n) __REG32(EMIFS_ACS0 + (4 * (n))) +#define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n))) +#define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n))) /* Almost all documentation for chip and board memory maps assumes * BM is clear. Most devel boards have a switch to control booting @@ -93,13 +91,13 @@ */ static inline u32 omap_cs0_phys(void) { - return (OMAP_EMIFS_CONFIG_REG & OMAP_EMIFS_CONFIG_BM) + return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM) ? OMAP_CS3_PHYS : 0; } static inline u32 omap_cs3_phys(void) { - return (OMAP_EMIFS_CONFIG_REG & OMAP_EMIFS_CONFIG_BM) + return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM) ? 0 : OMAP_CS3_PHYS; } -- cgit v1.2.3 From f35ae6346850f6c192269b09088b20261760f0e0 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Jul 2008 12:24:43 +0300 Subject: ARM: OMAP: USB: Change omap USB code to use omap_read/write instead of __REG Change omap USB code to use omap_read/write instead of __REG for multi-omap Cc: David Brownell Cc: linux-usb@vger.kernel.org Cc: i2c@lm-sensors.org Signed-off-by: Tony Lindgren --- include/asm-arm/arch-omap/usb.h | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h index 2147d18aaea..ddf1861e6df 100644 --- a/include/asm-arm/arch-omap/usb.h +++ b/include/asm-arm/arch-omap/usb.h @@ -34,11 +34,8 @@ /* * OTG and transceiver registers, for OMAPs starting with ARM926 */ -#define OTG_REG32(offset) __REG32(OTG_BASE + (offset)) -#define OTG_REG16(offset) __REG16(OTG_BASE + (offset)) - -#define OTG_REV_REG OTG_REG32(0x00) -#define OTG_SYSCON_1_REG OTG_REG32(0x04) +#define OTG_REV (OTG_BASE + 0x00) +#define OTG_SYSCON_1 (OTG_BASE + 0x04) # define USB2_TRX_MODE(w) (((w)>>24)&0x07) # define USB1_TRX_MODE(w) (((w)>>20)&0x07) # define USB0_TRX_MODE(w) (((w)>>16)&0x07) @@ -47,7 +44,7 @@ # define DEV_IDLE_EN (1 << 13) # define OTG_RESET_DONE (1 << 2) # define OTG_SOFT_RESET (1 << 1) -#define OTG_SYSCON_2_REG OTG_REG32(0x08) +#define OTG_SYSCON_2 (OTG_BASE + 0x08) # define OTG_EN (1 << 31) # define USBX_SYNCHRO (1 << 30) # define OTG_MST16 (1 << 29) @@ -65,7 +62,7 @@ # define HMC_TLLSPEED (1 << 7) # define HMC_TLLATTACH (1 << 6) # define OTG_HMC(w) (((w)>>0)&0x3f) -#define OTG_CTRL_REG OTG_REG32(0x0c) +#define OTG_CTRL (OTG_BASE + 0x0c) # define OTG_USB2_EN (1 << 29) # define OTG_USB2_DP (1 << 28) # define OTG_USB2_DM (1 << 27) @@ -92,7 +89,7 @@ # define OTG_PD_VBUS (1 << 2) # define OTG_PU_VBUS (1 << 1) # define OTG_PU_ID (1 << 0) -#define OTG_IRQ_EN_REG OTG_REG16(0x10) +#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */ # define DRIVER_SWITCH (1 << 15) # define A_VBUS_ERR (1 << 13) # define A_REQ_TMROUT (1 << 12) @@ -102,9 +99,9 @@ # define B_SRP_DONE (1 << 8) # define B_SRP_STARTED (1 << 7) # define OPRT_CHG (1 << 0) -#define OTG_IRQ_SRC_REG OTG_REG16(0x14) +#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */ // same bits as in IRQ_EN -#define OTG_OUTCTRL_REG OTG_REG16(0x18) +#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */ # define OTGVPD (1 << 14) # define OTGVPU (1 << 13) # define OTGPUID (1 << 12) @@ -117,13 +114,13 @@ # define USB0VDR (1 << 2) # define USB0PDEN (1 << 1) # define USB0PUEN (1 << 0) -#define OTG_TEST_REG OTG_REG16(0x20) -#define OTG_VENDOR_CODE_REG OTG_REG32(0xfc) +#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */ +#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */ /*-------------------------------------------------------------------------*/ /* OMAP1 */ -#define USB_TRANSCEIVER_CTRL_REG __REG32(0xfffe1000 + 0x0064) +#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064) # define CONF_USB2_UNI_R (1 << 8) # define CONF_USB1_UNI_R (1 << 7) # define CONF_USB_PORT0_R(x) (((x)>>4)&0x7) -- cgit v1.2.3 From e1f80bfca86ab48b7bed731b32262fb1a2835de5 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Jul 2008 12:24:43 +0300 Subject: ARM: OMAP: Remove __REG access for multi-omap This does not play nicely with multi-omap as it cannot be replaced by a function in io.c for omaps with different IO bases. Signed-off-by: Tony Lindgren --- include/asm-arm/arch-omap/io.h | 23 ----------------------- 1 file changed, 23 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h index 160578e1f55..e1fb7ec7d47 100644 --- a/include/asm-arm/arch-omap/io.h +++ b/include/asm-arm/arch-omap/io.h @@ -183,35 +183,12 @@ #define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) #define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) -/* 16 bit uses LDRH/STRH, base +/- offset_8 */ -typedef struct { volatile u16 offset[256]; } __regbase16; -#define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \ - ->offset[((vaddr)&0xff)>>1] -#define __REG16(paddr) __REGV16(io_p2v(paddr)) - -/* 8/32 bit uses LDR/STR, base +/- offset_12 */ -typedef struct { volatile u8 offset[4096]; } __regbase8; -#define __REGV8(vaddr) ((__regbase8 *)((vaddr)&~4095)) \ - ->offset[((vaddr)&4095)>>0] -#define __REG8(paddr) __REGV8(io_p2v(paddr)) - -typedef struct { volatile u32 offset[4096]; } __regbase32; -#define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \ - ->offset[((vaddr)&4095)>>2] -#define __REG32(paddr) __REGV32(io_p2v(paddr)) - extern void omap1_map_common_io(void); extern void omap1_init_common_hw(void); extern void omap2_map_common_io(void); extern void omap2_init_common_hw(void); -#else - -#define __REG8(paddr) io_p2v(paddr) -#define __REG16(paddr) io_p2v(paddr) -#define __REG32(paddr) io_p2v(paddr) - #endif #endif -- cgit v1.2.3 From a58caad11301a5bdc2d7b76596ab5477221f7a9b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Jul 2008 12:24:44 +0300 Subject: ARM: OMAP: Introduce omap_globals and prcm access functions for multi-omap New struct omap_globals contains the omap processor specific module bases. Use omap_globals to set the various base addresses to make detecting omap chip type simpler. Also introduce OMAP1_IO_ADDRESS and OMAP2_IO_ADDRESS for future multi-omap patches. Signed-off-by: Tony Lindgren --- include/asm-arm/arch-omap/common.h | 15 +++++++++++++++ include/asm-arm/arch-omap/control.h | 4 +--- include/asm-arm/arch-omap/io.h | 3 +++ 3 files changed, 19 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h index 36a3b62d4d8..8ac03071f60 100644 --- a/include/asm-arm/arch-omap/common.h +++ b/include/asm-arm/arch-omap/common.h @@ -47,8 +47,23 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, } #endif +/* IO bases for various OMAP processors */ +struct omap_globals { + void __iomem *tap; /* Control module ID code */ + void __iomem *sdrc; /* SDRAM Controller */ + void __iomem *sms; /* SDRAM Memory Scheduler */ + void __iomem *ctrl; /* System Control Module */ + void __iomem *prm; /* Power and Reset Management */ + void __iomem *cm; /* Clock Management */ +}; + void omap2_set_globals_242x(void); void omap2_set_globals_243x(void); void omap2_set_globals_343x(void); +/* These get called from omap2_set_globals_xxxx(), do not call these */ +void omap2_set_globals_memory(struct omap_globals *); +void omap2_set_globals_control(struct omap_globals *); +void omap2_set_globals_prcm(struct omap_globals *); + #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h index 59c0686f8be..987553e3eeb 100644 --- a/include/asm-arm/arch-omap/control.h +++ b/include/asm-arm/arch-omap/control.h @@ -167,8 +167,7 @@ #ifndef __ASSEMBLY__ #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) -extern void omap_ctrl_base_set(u32 base); -extern u32 omap_ctrl_base_get(void); +extern void __iomem *omap_ctrl_base_get(void); extern u8 omap_ctrl_readb(u16 offset); extern u16 omap_ctrl_readw(u16 offset); extern u32 omap_ctrl_readl(u16 offset); @@ -176,7 +175,6 @@ extern void omap_ctrl_writeb(u8 val, u16 offset); extern void omap_ctrl_writew(u16 val, u16 offset); extern void omap_ctrl_writel(u32 val, u16 offset); #else -#define omap_ctrl_base_set(x) WARN_ON(1) #define omap_ctrl_base_get() 0 #define omap_ctrl_readb(x) 0 #define omap_ctrl_readw(x) 0 diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h index e1fb7ec7d47..0b13557fd30 100644 --- a/include/asm-arm/arch-omap/io.h +++ b/include/asm-arm/arch-omap/io.h @@ -60,6 +60,7 @@ #define IO_SIZE 0x40000 #define IO_VIRT (IO_PHYS - IO_OFFSET) #define IO_ADDRESS(pa) ((pa) - IO_OFFSET) +#define OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET) #define io_p2v(pa) ((pa) - IO_OFFSET) #define io_v2p(va) ((va) + IO_OFFSET) @@ -91,6 +92,7 @@ #define IO_OFFSET 0x90000000 #define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ +#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ #define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ #define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */ @@ -148,6 +150,7 @@ #define IO_OFFSET 0x90000000 #define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ +#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ #define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ #define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */ -- cgit v1.2.3 From 097c584cd48844d9ef8402bdc6ab49e7e2135f31 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 3 Jul 2008 12:24:45 +0300 Subject: ARM: OMAP: Add OMAP chip type structure; clean up mach-omap2/id.c Add a new OMAP chip identification interface, omap_chip_id. omap_chip_id is a structure which contains one bit for each OMAP2/3 CPU type, and on 3430, ES level. For example, the CHIP_IS_OMAP2420 bit is set in omap_chip at boot on an OMAP2420. On OMAP3430ES2, both CHIP_IS_OMAP3430 and CHIP_IS_OMAP3430ES2 bits are set. omap_chip is set in mach-omap2/id.c by _set_omap_chip(). Other code should use the omap_chip_is() function to test against omap_chip. Also, clean up id.c by splitting some code out of omap_check_revision() into its own function, _set_system_rev(); and converting some debug printk()s into pr_debug(). Second revision. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren --- include/asm-arm/arch-omap/cpu.h | 39 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h index e8a4cf52778..52db09f8328 100644 --- a/include/asm-arm/arch-omap/cpu.h +++ b/include/asm-arm/arch-omap/cpu.h @@ -3,7 +3,7 @@ * * OMAP cpu type detection * - * Copyright (C) 2004 Nokia Corporation + * Copyright (C) 2004, 2008 Nokia Corporation * * Written by Tony Lindgren * @@ -26,6 +26,12 @@ #ifndef __ASM_ARCH_OMAP_CPU_H #define __ASM_ARCH_OMAP_CPU_H +struct omap_chip_id { + u8 oc; +}; + +#define OMAP_CHIP_INIT(x) { .oc = x } + extern unsigned int system_rev; #define omap2_cpu_rev() ((system_rev >> 12) & 0x0f) @@ -345,6 +351,33 @@ IS_OMAP_TYPE(3430, 0x3430) #define OMAP2430_REV_ES1_0 0x24300000 #define OMAP3430_REV_ES1_0 0x34300000 #define OMAP3430_REV_ES2_0 0x34301000 +#define OMAP3430_REV_ES2_1 0x34302000 +#define OMAP3430_REV_ES2_2 0x34303000 + +/* + * omap_chip bits + * + * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is + * valid on all chips of that type. CHIP_IS_OMAP3430ES{1,2} indicates + * something that is only valid on that particular ES revision. + * + * These bits may be ORed together to indicate structures that are + * available on multiple chip types. + * + * To test whether a particular structure matches the current OMAP chip type, + * use omap_chip_is(). + * + */ +#define CHIP_IS_OMAP2420 (1 << 0) +#define CHIP_IS_OMAP2430 (1 << 1) +#define CHIP_IS_OMAP3430 (1 << 2) +#define CHIP_IS_OMAP3430ES1 (1 << 3) +#define CHIP_IS_OMAP3430ES2 (1 << 4) + +#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) + +int omap_chip_is(struct omap_chip_id oci); + /* * Macro to detect device type i.e. EMU/HS/TST/GP/BAD @@ -362,6 +395,8 @@ IS_OMAP_TYPE(3430, 0x3430) #define is_device_type_gp() (get_device_type() == DEVICE_TYPE_GP) #define is_device_type_bad() (get_device_type() == DEVICE_TYPE_BAD) -#endif +void omap2_check_revision(void); + +#endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */ #endif -- cgit v1.2.3 From 542313cc98e72d026d2df86f515699dfaface460 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 3 Jul 2008 12:24:45 +0300 Subject: ARM: OMAP2: Clock: Add OMAP3 DPLL autoidle functions This patch adds support for DPLL autoidle control to the OMAP3 clock framework. These functions will be used by the noncore DPLL enable and disable code - this is because, according to the CDP code, the DPLL autoidle status must be saved and restored across DPLL lock/bypass/off transitions. N.B.: the CORE DPLL (DPLL3) has three autoidle mode options, rather than just two. This code currently does not support the third option, low-power bypass autoidle. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren --- include/asm-arm/arch-omap/clock.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h index 8490fbba39d..22daa5d64d3 100644 --- a/include/asm-arm/arch-omap/clock.h +++ b/include/asm-arm/arch-omap/clock.h @@ -34,11 +34,16 @@ struct dpll_data { u32 mult_mask; u32 div1_mask; # if defined(CONFIG_ARCH_OMAP3) + u8 modes; void __iomem *control_reg; u32 enable_mask; u8 auto_recal_bit; u8 recal_en_bit; u8 recal_st_bit; + void __iomem *autoidle_reg; + u32 autoidle_mask; + void __iomem *idlest_reg; + u8 idlest_bit; # endif }; -- cgit v1.2.3 From 88b8ba90570067178d32c654ad95786041e86e86 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 3 Jul 2008 12:24:46 +0300 Subject: ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm This patch adds a new rate rounding algorithm for DPLL clocks on the OMAP2/3 architecture. For a desired DPLL target rate, there may be several multiplier/divider (M, N) values which will generate a sufficiently close rate. Lower N values result in greater power economy. However, lower N values can cause the difference between the rounded rate and the target rate ("rate error") to be larger than it would be with a higher N. This can cause downstream devices to run more slowly than they otherwise would. This DPLL rate rounding algorithm: - attempts to find the lowest possible N (DPLL divider) to reach the target_rate (since, according to Richard Woodruff , lower N values save more power than higher N values). - allows developers to set an upper bound on the error between the rounded rate and the desired target rate ("rate tolerance"), so an appropriate balance between rate fidelity and power savings can be set. This maximum rate error tolerance is set via omap2_set_dpll_rate_tolerance(). - never returns a rounded rate higher than the target rate. The rate rounding algorithm caches the last rounded M, N, and rate computation to avoid rounding the rate twice for each clk_set_rate() call. (This patch does not yet implement set_rate for DPLLs; that follows in a future patch.) The algorithm trades execution speed for rate accuracy. It will find the (M, N) set that results in the least rate error, within a specified rate tolerance. It does this by evaluating each divider setting - on OMAP3, this involves 128 steps. Another approach to DPLL rate rounding would be to bail out as soon as a valid rate is found within the rate tolerance, which would trade rate accuracy for execution speed. Alternate implementations welcome. This code is not yet used by the OMAP24XX DPLL clock, since it is currently defined as a composite clock, fusing the DPLL M,N and the M2 output divider. This patch also renames the existing OMAP24xx DPLL programming functions to highlight that they program both the DPLL and the DPLL's output multiplier. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren --- include/asm-arm/arch-omap/clock.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h index 22daa5d64d3..4c7b3514f71 100644 --- a/include/asm-arm/arch-omap/clock.h +++ b/include/asm-arm/arch-omap/clock.h @@ -33,6 +33,13 @@ struct dpll_data { void __iomem *mult_div1_reg; u32 mult_mask; u32 div1_mask; + u16 last_rounded_m; + u8 last_rounded_n; + unsigned long last_rounded_rate; + unsigned int rate_tolerance; + u16 max_multiplier; + u8 max_divider; + u32 max_tolerance; # if defined(CONFIG_ARCH_OMAP3) u8 modes; void __iomem *control_reg; @@ -71,7 +78,7 @@ struct clk { void __iomem *clksel_reg; u32 clksel_mask; const struct clksel *clksel; - const struct dpll_data *dpll_data; + struct dpll_data *dpll_data; #else __u8 rate_offset; __u8 src_offset; -- cgit v1.2.3 From 50bbb05d60e1897abad92d42bf185314be36bd74 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 19 Apr 2008 15:56:08 +0100 Subject: [ARM] rpc: deprecate __ioaddr() and __ioaddrc() helpers Now everything is converted to use MMIO accessors, these helpers are no longer required. Signed-off-by: Russell King --- include/asm-arm/arch-rpc/io.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-rpc/io.h b/include/asm-arm/arch-rpc/io.h index b4da08d7a33..6bd2295c0e0 100644 --- a/include/asm-arm/arch-rpc/io.h +++ b/include/asm-arm/arch-rpc/io.h @@ -126,7 +126,7 @@ static inline unsigned sz __in##fnsuffix (unsigned int port) \ return (unsigned sz)value; \ } -static inline void __iomem *__ioaddr(unsigned int port) +static inline void __iomem *__deprecated __ioaddr(unsigned int port) { void __iomem *ret; if (__PORT_PCIO(port)) @@ -232,8 +232,7 @@ DECLARE_IO(int,l,"") result; \ }) -#define __ioaddrc(port) \ - ((__PORT_PCIO(port) ? PCIO_BASE : IO_BASE) + ((port) << 2)) +#define __ioaddrc(port) __ioaddr(port) #define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p)) #define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p)) -- cgit v1.2.3 From 9ecba1f288d2cf87d1b6a9401d5ce17464eb776d Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 19 Apr 2008 16:01:38 +0100 Subject: [ARM] rpc: ecard: remove deprecated ecard_address() and relatives ecard_address() is obsolete, and has been marked deprecated since at least 2.6.12-rc2. All in-tree users have been updated to use the new approach, so it's time to remove this. Signed-off-by: Russell King --- include/asm-arm/ecard.h | 35 ----------------------------------- 1 file changed, 35 deletions(-) (limited to 'include') diff --git a/include/asm-arm/ecard.h b/include/asm-arm/ecard.h index 684fe064523..5e22881a630 100644 --- a/include/asm-arm/ecard.h +++ b/include/asm-arm/ecard.h @@ -85,19 +85,6 @@ #define MAX_ECARDS 9 -typedef enum { /* Cards address space */ - ECARD_IOC, - ECARD_MEMC, - ECARD_EASI -} card_type_t; - -typedef enum { /* Speed for ECARD_IOC space */ - ECARD_SLOW = 0, - ECARD_MEDIUM = 1, - ECARD_FAST = 2, - ECARD_SYNC = 3 -} card_speed_t; - struct ecard_id { /* Card ID structure */ unsigned short manufacturer; unsigned short product; @@ -189,16 +176,6 @@ struct in_chunk_dir { } d; }; -/* - * ecard_claim: claim an expansion card entry - */ -#define ecard_claim(ec) ((ec)->claimed = 1) - -/* - * ecard_release: release an expansion card entry - */ -#define ecard_release(ec) ((ec)->claimed = 0) - /* * Read a chunk from an expansion card * cd : where to put read data @@ -208,18 +185,6 @@ struct in_chunk_dir { */ extern int ecard_readchunk (struct in_chunk_dir *cd, struct expansion_card *ec, int id, int num); -/* - * Obtain the address of a card. This returns the "old style" address - * and should no longer be used. - */ -static inline unsigned int __deprecated -ecard_address(struct expansion_card *ec, card_type_t type, card_speed_t speed) -{ - extern unsigned int __ecard_address(struct expansion_card *, - card_type_t, card_speed_t); - return __ecard_address(ec, type, speed); -} - /* * Request and release ecard resources */ -- cgit v1.2.3 From 3c093f9f182eef6a8dc535f2c62b36a0320d0db1 Mon Sep 17 00:00:00 2001 From: Vegard Nossum Date: Mon, 9 Jun 2008 16:24:10 -0700 Subject: [ARM] fix header guards Acked-by: Dan Williams Signed-off-by: Vegard Nossum Signed-off-by: Andrew Morton Signed-off-by: Russell King --- include/asm-arm/arch-iop13xx/dma.h | 2 +- include/asm-arm/arch-msm/irqs.h | 1 + include/asm-arm/arch-msm/timex.h | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-arm/arch-iop13xx/dma.h b/include/asm-arm/arch-iop13xx/dma.h index 2e15da53ff7..d79846fbb39 100644 --- a/include/asm-arm/arch-iop13xx/dma.h +++ b/include/asm-arm/arch-iop13xx/dma.h @@ -1,3 +1,3 @@ #ifndef _IOP13XX_DMA_H -#define _IOP13XX_DMA_H_ +#define _IOP13XX_DMA_H #endif diff --git a/include/asm-arm/arch-msm/irqs.h b/include/asm-arm/arch-msm/irqs.h index 565430cfaa7..e62a108b185 100644 --- a/include/asm-arm/arch-msm/irqs.h +++ b/include/asm-arm/arch-msm/irqs.h @@ -15,6 +15,7 @@ */ #ifndef __ASM_ARCH_MSM_IRQS_H +#define __ASM_ARCH_MSM_IRQS_H /* MSM ARM11 Interrupt Numbers */ /* See 80-VE113-1 A, pp219-221 */ diff --git a/include/asm-arm/arch-msm/timex.h b/include/asm-arm/arch-msm/timex.h index 154b23fb359..8724487ab4c 100644 --- a/include/asm-arm/arch-msm/timex.h +++ b/include/asm-arm/arch-msm/timex.h @@ -14,6 +14,7 @@ */ #ifndef __ASM_ARCH_MSM_TIMEX_H +#define __ASM_ARCH_MSM_TIMEX_H #define CLOCK_TICK_RATE 1000000 -- cgit v1.2.3 From 826cbdaff29764bb6928c715c6a025e49469dda9 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Fri, 13 Jun 2008 10:28:36 +0100 Subject: [ARM] 5092/1: Fix the I-cache invalidation on ARMv6 and later CPUs This patch adds the I-cache invalidation in update_mmu_cache if the corresponding vma is marked as executable. It also invalidates the I-cache if a thread migrates to a CPU it never ran on. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- include/asm-arm/cacheflush.h | 7 +++++++ include/asm-arm/mmu_context.h | 5 +++++ 2 files changed, 12 insertions(+) (limited to 'include') diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index 759a97b56ee..559fb4af1f6 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -410,6 +410,13 @@ extern void flush_dcache_page(struct page *); extern void __flush_dcache_page(struct address_space *mapping, struct page *page); +static inline void __flush_icache_all(void) +{ + asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n" + : + : "r" (0)); +} + #define ARCH_HAS_FLUSH_ANON_PAGE static inline void flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr) diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h index 6913d02ca5d..91b9dfdfed5 100644 --- a/include/asm-arm/mmu_context.h +++ b/include/asm-arm/mmu_context.h @@ -97,6 +97,11 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, #ifdef CONFIG_MMU unsigned int cpu = smp_processor_id(); +#ifdef CONFIG_SMP + /* check for possible thread migration */ + if (!cpus_empty(next->cpu_vm_mask) && !cpu_isset(cpu, next->cpu_vm_mask)) + __flush_icache_all(); +#endif if (!cpu_test_and_set(cpu, next->cpu_vm_mask) || prev != next) { check_context(next); cpu_switch_mm(next->pgd, next); -- cgit v1.2.3 From f7def13ed0775ee506c62a8612a124dce1776ac2 Mon Sep 17 00:00:00 2001 From: Paulius Zaleckas Date: Wed, 25 Jun 2008 13:25:13 +0100 Subject: [ARM] 5122/1: imx_dma_request_by_prio simpilfication imx_dma_request_by_prio can return channel number by itself. No need to supply variable address through parameters. Also converted all drivers using this function. Signed-off-by: Paulius Zaleckas Acked-by: Sascha Hauer Signed-off-by: Russell King --- include/asm-arm/arch-imx/imx-dma.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-arm/arch-imx/imx-dma.h b/include/asm-arm/arch-imx/imx-dma.h index 5b1066da4e1..44d89c35539 100644 --- a/include/asm-arm/arch-imx/imx-dma.h +++ b/include/asm-arm/arch-imx/imx-dma.h @@ -88,7 +88,7 @@ int imx_dma_request(imx_dmach_t dma_ch, const char *name); void imx_dma_free(imx_dmach_t dma_ch); -int imx_dma_request_by_prio(imx_dmach_t *pdma_ch, const char *name, imx_dma_prio prio); +imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio); #endif /* _ASM_ARCH_IMX_DMA_H */ -- cgit v1.2.3 From f348a2a2817e9d24b1edd4befc9659ec83501ca5 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 3 Jul 2008 11:24:25 +0100 Subject: [ARM] S3C24XX: Add gpiolib support Add support for gpilib on all S3C24XX platforms. Signed-off-by: Ben Dooks --- include/asm-arm/arch-s3c2410/gpio.h | 74 ++++++------------------------------- 1 file changed, 12 insertions(+), 62 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-s3c2410/gpio.h b/include/asm-arm/arch-s3c2410/gpio.h index 7583895fd33..18e10d2c35e 100644 --- a/include/asm-arm/arch-s3c2410/gpio.h +++ b/include/asm-arm/arch-s3c2410/gpio.h @@ -1,68 +1,18 @@ -/* - * linux/include/asm-arm/arch-s3c2410/gpio.h +/* linux/include/asm-arm/arch-s3c2410/gpio.h * - * S3C2410 GPIO wrappers for arch-neutral GPIO calls + * Copyright (c) 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks * - * Written by Philipp Zabel + * S3C2410 - GPIO lib support * * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __ASM_ARCH_S3C2410_GPIO_H -#define __ASM_ARCH_S3C2410_GPIO_H - -#include -#include -#include - -static inline int gpio_request(unsigned gpio, const char *label) -{ - return 0; -} - -static inline void gpio_free(unsigned gpio) -{ - return; -} - -static inline int gpio_direction_input(unsigned gpio) -{ - s3c2410_gpio_cfgpin(gpio, S3C2410_GPIO_INPUT); - return 0; -} - -static inline int gpio_direction_output(unsigned gpio, int value) -{ - s3c2410_gpio_cfgpin(gpio, S3C2410_GPIO_OUTPUT); - /* REVISIT can we write the value first, to avoid glitching? */ - s3c2410_gpio_setpin(gpio, value); - return 0; -} - -#define gpio_get_value(gpio) s3c2410_gpio_getpin(gpio) -#define gpio_set_value(gpio,value) s3c2410_gpio_setpin(gpio, value) - -#include /* cansleep wrappers */ - -#ifdef CONFIG_CPU_S3C2400 -#define gpio_to_irq(gpio) s3c2400_gpio_getirq(gpio) -#else -#define gpio_to_irq(gpio) s3c2410_gpio_getirq(gpio) -#endif + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ -/* FIXME implement irq_to_gpio() */ +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep -#endif +#include -- cgit v1.2.3 From b4b68f8cfaf583945019e41674cfa858c83316c3 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 3 Jul 2008 11:24:26 +0100 Subject: [ARM] S3C24XX: Add PWM timer MUX defines Add timer defines for the MUX settings for each of the PWM timers to add to the per-timer defines already in the file. Signed-off-by: Ben Dooks --- include/asm-arm/plat-s3c/regs-timer.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/asm-arm/plat-s3c/regs-timer.h b/include/asm-arm/plat-s3c/regs-timer.h index 8b0d594397b..b5bc692f348 100644 --- a/include/asm-arm/plat-s3c/regs-timer.h +++ b/include/asm-arm/plat-s3c/regs-timer.h @@ -65,6 +65,15 @@ #define S3C2410_TCFG1_MUX0_TCLK0 (4<<0) #define S3C2410_TCFG1_MUX0_MASK (15<<0) +#define S3C2410_TCFG1_MUX_DIV2 (0<<0) +#define S3C2410_TCFG1_MUX_DIV4 (1<<0) +#define S3C2410_TCFG1_MUX_DIV8 (2<<0) +#define S3C2410_TCFG1_MUX_DIV16 (3<<0) +#define S3C2410_TCFG1_MUX_TCLK (4<<0) +#define S3C2410_TCFG1_MUX_MASK (15<<0) + +#define S3C2410_TCFG1_SHIFT(x) ((x) * 4) + /* for each timer, we have an count buffer, an compare buffer and * an observation buffer */ -- cgit v1.2.3 From d5c52922b618aa6ddd6b5ebebc8d0a5ec9a20f10 Mon Sep 17 00:00:00 2001 From: Matthieu Castet Date: Thu, 3 Jul 2008 11:24:45 +0100 Subject: [ARM] S3C2412: Correct parents for EREFCLK and UREFCLK For s3c2412, set parent for clk_erefclk and clk_urefclk. This allow for example to use xtal or extclk for i2s clock. Signed-off-by: Ben Dooks Signed-off-by: Matthieu Castet --- include/asm-arm/arch-s3c2410/regs-clock.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h index ecae9e7f5e4..37661358b42 100644 --- a/include/asm-arm/arch-s3c2410/regs-clock.h +++ b/include/asm-arm/arch-s3c2410/regs-clock.h @@ -189,6 +189,8 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk) #define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9) #define S3C2412_CLKSRC_USBCLK_HCLK (1<<10) #define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11) +#define S3C2412_CLKSRC_UREFCLK_EXTCLK (1<<12) +#define S3C2412_CLKSRC_EREFCLK_EXTCLK (1<<14) #endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */ -- cgit v1.2.3 From 6fc601e37bbb4045ee0afefc76b64284ea800c89 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 1 Jul 2008 13:17:24 +0100 Subject: [ARM] S3C24XX: PWM API support. Add support for PWM in the S3C24XX series of SoC via the PWM API. Signed-off-by: Ben Dooks --- include/asm-arm/plat-s3c24xx/devs.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/asm-arm/plat-s3c24xx/devs.h b/include/asm-arm/plat-s3c24xx/devs.h index f9d6f0317bc..badaac9d64a 100644 --- a/include/asm-arm/plat-s3c24xx/devs.h +++ b/include/asm-arm/plat-s3c24xx/devs.h @@ -21,6 +21,8 @@ extern struct s3c24xx_uart_resources s3c2410_uart_resources[]; extern struct platform_device *s3c24xx_uart_devs[]; extern struct platform_device *s3c24xx_uart_src[]; +extern struct platform_device s3c_device_timer[]; + extern struct platform_device s3c_device_usb; extern struct platform_device s3c_device_lcd; extern struct platform_device s3c_device_wdt; @@ -36,11 +38,6 @@ extern struct platform_device s3c_device_spi1; extern struct platform_device s3c_device_nand; -extern struct platform_device s3c_device_timer0; -extern struct platform_device s3c_device_timer1; -extern struct platform_device s3c_device_timer2; -extern struct platform_device s3c_device_timer3; - extern struct platform_device s3c_device_usbgadget; /* s3c2440 specific devices */ -- cgit v1.2.3 From 63f385cd1f649b3f4f2d59fc609e051981215fd7 Mon Sep 17 00:00:00 2001 From: Arnaud Patard Date: Tue, 8 Jul 2008 23:07:48 +0100 Subject: [ARM] 5160/1: IOP3XX: gpio/gpiolib support This patch brings support for gpio/gpiolib framework to Intel IOP3xx platforms. Signed-off-by: Arnaud Patard Acked-by: Dan Williams Signed-off-by: Russell King --- include/asm-arm/arch-iop32x/gpio.h | 6 +++ include/asm-arm/arch-iop33x/gpio.h | 6 +++ include/asm-arm/hardware/iop3xx-gpio.h | 73 ++++++++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+) create mode 100644 include/asm-arm/arch-iop32x/gpio.h create mode 100644 include/asm-arm/arch-iop33x/gpio.h create mode 100644 include/asm-arm/hardware/iop3xx-gpio.h (limited to 'include') diff --git a/include/asm-arm/arch-iop32x/gpio.h b/include/asm-arm/arch-iop32x/gpio.h new file mode 100644 index 00000000000..708f4ec9db1 --- /dev/null +++ b/include/asm-arm/arch-iop32x/gpio.h @@ -0,0 +1,6 @@ +#ifndef __ASM_ARCH_IOP32X_GPIO_H +#define __ASM_ARCH_IOP32X_GPIO_H + +#include + +#endif diff --git a/include/asm-arm/arch-iop33x/gpio.h b/include/asm-arm/arch-iop33x/gpio.h new file mode 100644 index 00000000000..ddd55bba9bb --- /dev/null +++ b/include/asm-arm/arch-iop33x/gpio.h @@ -0,0 +1,6 @@ +#ifndef __ASM_ARCH_IOP33X_GPIO_H +#define __ASM_ARCH_IOP33X_GPIO_H + +#include + +#endif diff --git a/include/asm-arm/hardware/iop3xx-gpio.h b/include/asm-arm/hardware/iop3xx-gpio.h new file mode 100644 index 00000000000..0c9331f9ac2 --- /dev/null +++ b/include/asm-arm/hardware/iop3xx-gpio.h @@ -0,0 +1,73 @@ +/* + * linux/include/asm-arm/hardware/iop3xx-gpio.h + * + * IOP3xx GPIO wrappers + * + * Copyright (c) 2008 Arnaud Patard + * Based on IXP4XX gpio.h file + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_HARDWARE_IOP3XX_GPIO_H +#define __ASM_ARM_HARDWARE_IOP3XX_GPIO_H + +#include +#include + +#define IOP3XX_N_GPIOS 8 + +static inline int gpio_get_value(unsigned gpio) +{ + if (gpio > IOP3XX_N_GPIOS) + return __gpio_get_value(gpio); + + return gpio_line_get(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + if (gpio > IOP3XX_N_GPIOS) { + __gpio_set_value(gpio, value); + return; + } + gpio_line_set(gpio, value); +} + +static inline int gpio_cansleep(unsigned gpio) +{ + if (gpio < IOP3XX_N_GPIOS) + return 0; + else + return __gpio_cansleep(gpio); +} + +/* + * The GPIOs are not generating any interrupt + * Note : manuals are not clear about this + */ +static inline int gpio_to_irq(int gpio) +{ + return -EINVAL; +} + +static inline int irq_to_gpio(int gpio) +{ + return -EINVAL; +} + +#endif + -- cgit v1.2.3 From 613526677a74c2b3d1b1696ea7334b2cf35155b3 Mon Sep 17 00:00:00 2001 From: sedji gaouaou Date: Thu, 10 Jul 2008 10:15:35 +0100 Subject: [ARM] 5130/4: Support for the at91sam9g20 Support for the at91sam9g20 : Atmel 400Mhz ARM 926ej-s SOC. AT91sam9g20 is an evolution of the at91sam9260 with a faster clock speed. We created a new board for this device but based the chip support directly on 9260 files with little updates. Here is the chip page on Atmel wabsite: http://atmel.com/dyn/products/product_card.asp?part_id=4337 Signed-off-by: Sedji Gaouaou Signed-off-by: Justin Waters Acked-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/arch-at91/at91sam9260.h | 11 +++++++++++ include/asm-arm/arch-at91/board.h | 2 +- include/asm-arm/arch-at91/cpu.h | 7 +++++++ include/asm-arm/arch-at91/hardware.h | 2 +- include/asm-arm/arch-at91/timex.h | 5 +++++ 5 files changed, 25 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h index c8934fe34dc..889872a3f2a 100644 --- a/include/asm-arm/arch-at91/at91sam9260.h +++ b/include/asm-arm/arch-at91/at91sam9260.h @@ -6,6 +6,8 @@ * Common definitions. * Based on AT91SAM9260 datasheet revision A (Preliminary). * + * Includes also definitions for AT91SAM9XE and AT91SAM9G families + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -123,5 +125,14 @@ #define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ #define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ +#define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */ +#define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ + +#define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ +#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */ +#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ +#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ + +#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */ #endif diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h index 1f247028686..94de788da76 100644 --- a/include/asm-arm/arch-at91/board.h +++ b/include/asm-arm/arch-at91/board.h @@ -77,7 +77,7 @@ struct at91_eth_data { }; extern void __init at91_add_device_eth(struct at91_eth_data *data); -#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9) +#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) #define eth_platform_data at91_eth_data #endif diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h index 7145166826a..52df794205c 100644 --- a/include/asm-arm/arch-at91/cpu.h +++ b/include/asm-arm/arch-at91/cpu.h @@ -21,6 +21,7 @@ #define ARCH_ID_AT91SAM9260 0x019803a0 #define ARCH_ID_AT91SAM9261 0x019703a0 #define ARCH_ID_AT91SAM9263 0x019607a0 +#define ARCH_ID_AT91SAM9G20 0x019905a0 #define ARCH_ID_AT91SAM9RL64 0x019b03a0 #define ARCH_ID_AT91CAP9 0x039A03A0 @@ -63,6 +64,12 @@ static inline unsigned long at91_arch_identify(void) #define cpu_is_at91sam9260() (0) #endif +#ifdef CONFIG_ARCH_AT91SAM9G20 +#define cpu_is_at91sam9g20() (at91_cpu_identify() == ARCH_ID_AT91SAM9G20) +#else +#define cpu_is_at91sam9g20() (0) +#endif + #ifdef CONFIG_ARCH_AT91SAM9261 #define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261) #else diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h index 2c826d8247a..016a3a3f663 100644 --- a/include/asm-arm/arch-at91/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h @@ -18,7 +18,7 @@ #if defined(CONFIG_ARCH_AT91RM9200) #include -#elif defined(CONFIG_ARCH_AT91SAM9260) +#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) #include #elif defined(CONFIG_ARCH_AT91SAM9261) #include diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h index 6e084eb839d..298d8313cda 100644 --- a/include/asm-arm/arch-at91/timex.h +++ b/include/asm-arm/arch-at91/timex.h @@ -57,6 +57,11 @@ #define AT91SAM9_MASTER_CLOCK 100000000 #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) +#elif defined(CONFIG_ARCH_AT91SAM9G20) + +#define AT91SAM9_MASTER_CLOCK 132096000 +#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) + #elif defined(CONFIG_ARCH_AT91CAP9) #define AT91CAP9_MASTER_CLOCK 100000000 -- cgit v1.2.3