From 0154724d487586241c1ad57cfd348ed2ff2274e2 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Sat, 23 May 2009 00:01:05 +0100 Subject: ASoC: Fix WM9081 PowerPC compiler issues Ensure that we always set a new sysclk when using the FLL in master mode and pick out the correct value for the sample rate in hw_params(). Signed-off-by: Mark Brown --- sound/soc/codecs/wm9081.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'sound/soc/codecs') diff --git a/sound/soc/codecs/wm9081.c b/sound/soc/codecs/wm9081.c index 83e3148c258..86fc57e25f9 100644 --- a/sound/soc/codecs/wm9081.c +++ b/sound/soc/codecs/wm9081.c @@ -702,9 +702,10 @@ static int configure_clock(struct snd_soc_codec *codec) * performance. */ for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) { target = wm9081->fs * clk_sys_rates[i].ratio; + new_sysclk = target; if (target >= wm9081->bclk && target > 3000000) - new_sysclk = target; + break; } } else if (wm9081->fs) { for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) { @@ -1102,7 +1103,8 @@ static int wm9081_hw_params(struct snd_pcm_substream *substream, } dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n", sample_rates[best].rate); - clk_ctrl2 |= (sample_rates[i].sample_rate << WM9081_SAMPLE_RATE_SHIFT); + clk_ctrl2 |= (sample_rates[best].sample_rate + << WM9081_SAMPLE_RATE_SHIFT); /* BCLK_DIV */ best = 0; -- cgit v1.2.3