aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/mach-omap2/sram34xx.S
blob: 8d524f305633301019d1c9dae0ec721213009919 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
/*
 * linux/arch/arm/mach-omap3/sram.S
 *
 * Omap3 specific functions that need to be run in internal SRAM
 *
 * (C) Copyright 2007
 * Texas Instruments Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
 * (C) Copyright 2004
 * Texas Instruments, <www.ti.com>
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <mach/hardware.h>

#include <mach/io.h>

#include "sdrc.h"
#include "cm.h"

	.text

/*
 * Change frequency of core dpll
 * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
 */
ENTRY(omap3_sram_configure_core_dpll)
	stmfd	sp!, {r1-r12, lr}	@ store regs to stack
	dsb				@ flush buffered writes to interconnect
	cmp	r3, #0x2
	blne	configure_sdrc
	cmp	r3, #0x2
	blne	lock_dll
	cmp	r3, #0x1
	blne	unlock_dll
	bl	sdram_in_selfrefresh	@ put the SDRAM in self refresh
	bl 	configure_core_dpll
	bl	enable_sdrc
	cmp	r3, #0x1
	blne	wait_dll_unlock
	cmp	r3, #0x2
	blne	wait_dll_lock
	cmp	r3, #0x1
	blne	configure_sdrc
	isb				@ prevent speculative exec past here
	mov 	r0, #0 			@ return value
	ldmfd	sp!, {r1-r12, pc}	@ restore regs and return
unlock_dll:
	ldr	r4, omap3_sdrc_dlla_ctrl
	ldr	r5, [r4]
	orr	r5, r5, #0x4
	str	r5, [r4]		@ (no OCP barrier needed)
	bx	lr
lock_dll:
	ldr	r4, omap3_sdrc_dlla_ctrl
	ldr	r5, [r4]
	bic	r5, r5, #0x4
	str	r5, [r4]		@ (no OCP barrier needed)
	bx	lr
sdram_in_selfrefresh:
	ldr	r4, omap3_sdrc_power	@ read the SDRC_POWER register
	ldr	r5, [r4]		@ read the contents of SDRC_POWER
	orr 	r5, r5, #0x40		@ enable self refresh on idle req
	str 	r5, [r4]		@ write back to SDRC_POWER register
	ldr	r5, [r4]		@ posted-write barrier for SDRC
	ldr	r4, omap3_cm_iclken1_core	@ read the CM_ICLKEN1_CORE reg
	ldr	r5, [r4]
	bic	r5, r5, #0x2		@ disable iclk bit for SDRC
	str 	r5, [r4]
wait_sdrc_idle:
	ldr 	r4, omap3_cm_idlest1_core
	ldr 	r5, [r4]
	and 	r5, r5, #0x2		@ check for SDRC idle
	cmp 	r5, #2
	bne 	wait_sdrc_idle
	bx 	lr
configure_core_dpll:
	ldr 	r4, omap3_cm_clksel1_pll
	ldr	r5, [r4]
	ldr	r6, core_m2_mask_val	@ modify m2 for core dpll
	and	r5, r5, r6
	orr	r5, r5, r3, lsl #0x1B	@ r3 contains the M2 val
	str	r5, [r4]
	ldr	r5, [r4]		@ posted-write barrier for CM
	mov 	r5, #0x800		@ wait for the clock to stabilise
	cmp	r3, #2
	bne	wait_clk_stable
	bx	lr
wait_clk_stable:
	subs 	r5, r5, #1
	bne	wait_clk_stable
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	bx	lr
enable_sdrc:
	ldr 	r4, omap3_cm_iclken1_core
	ldr	r5, [r4]
	orr 	r5, r5, #0x2		@ enable iclk bit for SDRC
	str 	r5, [r4]
wait_sdrc_idle1:
	ldr 	r4, omap3_cm_idlest1_core
	ldr	r5, [r4]
	and 	r5, r5, #0x2
	cmp	r5, #0
	bne	wait_sdrc_idle1
	ldr	r4, omap3_sdrc_power
	ldr	r5, [r4]
	bic 	r5, r5, #0x40
	str 	r5, [r4]
	bx	lr
wait_dll_lock:
	ldr	r4, omap3_sdrc_dlla_status
	ldr	r5, [r4]
	and 	r5, r5, #0x4
	cmp	r5, #0x4
	bne	wait_dll_lock
	bx	lr
wait_dll_unlock:
	ldr	r4, omap3_sdrc_dlla_status
	ldr	r5, [r4]
	and	r5, r5, #0x4
	cmp	r5, #0x0
	bne	wait_dll_unlock
	bx	lr
configure_sdrc:
	ldr	r4, omap3_sdrc_rfr_ctrl
	str	r0, [r4]
	ldr	r4, omap3_sdrc_actim_ctrla
	str	r1, [r4]
	ldr	r4, omap3_sdrc_actim_ctrlb
	str	r2, [r4]
	ldr	r2, [r4]		@ posted-write barrier for SDRC
	bx	lr

omap3_sdrc_power:
	.word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
omap3_cm_clksel1_pll:
	.word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
omap3_cm_idlest1_core:
	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
omap3_cm_iclken1_core:
	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
omap3_sdrc_rfr_ctrl:
	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
omap3_sdrc_actim_ctrla:
	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
omap3_sdrc_actim_ctrlb:
	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
omap3_sdrc_dlla_status:
	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
omap3_sdrc_dlla_ctrl:
	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
core_m2_mask_val:
	.word 0x07FFFFFF

ENTRY(omap3_sram_configure_core_dpll_sz)
	.word	. - omap3_sram_configure_core_dpll