aboutsummaryrefslogtreecommitdiff
path: root/shared-core/nouveau_fifo.c
diff options
context:
space:
mode:
authorBen Skeggs <skeggsb@gmail.com>2007-07-15 17:18:15 +1000
committerBen Skeggs <skeggsb@gmail.com>2007-07-17 13:51:14 +1000
commitec67c2def9af16bf9252d6742aec815b817f135a (patch)
tree90a1645b3fe9cd2b7c7ea36b79b609aaf2f2aa4c /shared-core/nouveau_fifo.c
parent70a8a60a3e81c18f9c6485102cb226c340c3cd73 (diff)
nouveau: G8x PCIEGART
Actually a NV04-NV50 ttm backend for both PCI and PCIEGART, but PCIGART support for G8X using the current mm has been hacked on top of it.
Diffstat (limited to 'shared-core/nouveau_fifo.c')
-rw-r--r--shared-core/nouveau_fifo.c31
1 files changed, 18 insertions, 13 deletions
diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c
index 56c25a6e..230c8298 100644
--- a/shared-core/nouveau_fifo.c
+++ b/shared-core/nouveau_fifo.c
@@ -211,24 +211,27 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel)
}
if (cb->flags & NOUVEAU_MEM_AGP) {
- DRM_DEBUG("Creating CB in AGP memory\n");
+ ret = nouveau_gpuobj_gart_dma_new(dev, channel,
+ cb->start, cb->size,
+ NV_DMA_ACCESS_RO,
+ &pushbuf,
+ &chan->pushbuf_base);
+ } else
+ if (cb->flags & NOUVEAU_MEM_PCI) {
ret = nouveau_gpuobj_dma_new(dev, channel,
- NV_CLASS_DMA_IN_MEMORY,
- cb->start, cb->size,
- NV_DMA_ACCESS_RO, NV_DMA_TARGET_AGP, &pushbuf);
- } else if ( cb->flags & NOUVEAU_MEM_PCI) {
- DRM_DEBUG("Creating CB in PCI memory\n");
- ret = nouveau_gpuobj_dma_new(dev, channel,
- NV_CLASS_DMA_IN_MEMORY,
- cb->start,
- cb->size,
- NV_DMA_ACCESS_RO, NV_DMA_TARGET_PCI_NONLINEAR, &pushbuf);
+ NV_CLASS_DMA_IN_MEMORY,
+ cb->start, cb->size,
+ NV_DMA_ACCESS_RO,
+ NV_DMA_TARGET_PCI_NONLINEAR,
+ &pushbuf);
+ chan->pushbuf_base = 0;
} else if (dev_priv->card_type != NV_04) {
ret = nouveau_gpuobj_dma_new
(dev, channel, NV_CLASS_DMA_IN_MEMORY,
cb->start,
cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_VIDMEM,
&pushbuf);
+ chan->pushbuf_base = 0;
} else {
/* NV04 cmdbuf hack, from original ddx.. not sure of it's
* exact reason for existing :) PCI access to cmdbuf in
@@ -239,6 +242,7 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel)
cb->start + drm_get_resource_start(dev, 1),
cb->size, NV_DMA_ACCESS_RO,
NV_DMA_TARGET_PCI, &pushbuf);
+ chan->pushbuf_base = 0;
}
if (ret) {
@@ -250,11 +254,12 @@ nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel)
if ((ret = nouveau_gpuobj_ref_add(dev, channel, 0, pushbuf,
&chan->pushbuf))) {
DRM_ERROR("Error referencing push buffer ctxdma: %d\n", ret);
+ if (pushbuf != dev_priv->gart_info.sg_ctxdma)
+ nouveau_gpuobj_del(dev, &pushbuf);
return ret;
}
- dev_priv->fifos[channel]->pushbuf_base = 0;
- dev_priv->fifos[channel]->pushbuf_mem = cb;
+ chan->pushbuf_mem = cb;
return 0;
}