diff options
author | Dave Airlie <airlied@linux.ie> | 2005-05-27 07:23:44 +0000 |
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committer | Dave Airlie <airlied@linux.ie> | 2005-05-27 07:23:44 +0000 |
commit | c9abd2fec509c271339d1ca3addd95df884df80a (patch) | |
tree | 03a7c21599c2934c06d2546320d4ea8a89f10a49 /shared-core/radeon_drv.h | |
parent | e1fd79b31e130e9e4bafcab914491973147b7f86 (diff) |
add radeon registers from VHA code these are the "unknown" registers
Diffstat (limited to 'shared-core/radeon_drv.h')
-rw-r--r-- | shared-core/radeon_drv.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index aaf77968..3c423542 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -831,6 +831,36 @@ extern void radeon_driver_free_filp_priv(drm_device_t * dev, #define R200_PP_TRI_PERF 0x2cf8 +/* MPEG settings from VHA code */ +#define RADEON_VHA_SETTO16_1 0x2694 +#define RADEON_VHA_SETTO16_2 0x2680 +#define RADEON_VHA_SETTO0_1 0x1840 +#define RADEON_VHA_FB_OFFSET 0x19e4 +#define RADEON_VHA_SETTO1AND70S 0x19d8 +#define RADEON_VHA_DST_PITCH 0x1408 + +// set as reference header +#define RADEON_VHA_BACKFRAME0_OFF_Y 0x1840 +#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y 0x1844 +#define RADEON_VHA_BACKFRAME0_OFF_U 0x1848 +#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U 0x184c +#define RADOEN_VHA_BACKFRAME0_OFF_V 0x1850 +#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V 0x1854 +#define RADEON_VHA_FORWFRAME0_OFF_Y 0x1858 +#define RADEON_VHA_FORWFRAME1_OFF_PITCH_Y 0x185c +#define RADEON_VHA_FORWFRAME0_OFF_U 0x1860 +#define RADEON_VHA_FORWFRAME1_OFF_PITCH_U 0x1864 +#define RADEON_VHA_FORWFRAME0_OFF_V 0x1868 +#define RADEON_VHA_FORWFRAME0_OFF_PITCH_V 0x1880 +#define RADEON_VHA_BACKFRAME0_OFF_Y_2 0x1884 +#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y_2 0x1888 +#define RADEON_VHA_BACKFRAME0_OFF_U_2 0x188c +#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U_2 0x1890 +#define RADEON_VHA_BACKFRAME0_OFF_V_2 0x1894 +#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V_2 0x1898 + + + /* Constants */ #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |