From c806bba4665bb369168ee0b453fa28e2e0bf2a5d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 5 Jul 2007 00:12:33 +1000 Subject: nouveau/nv50: Initial channel/object support Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80. --- shared-core/nv10_fifo.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'shared-core/nv10_fifo.c') diff --git a/shared-core/nv10_fifo.c b/shared-core/nv10_fifo.c index 07ec4635..2d8d5a0d 100644 --- a/shared-core/nv10_fifo.c +++ b/shared-core/nv10_fifo.c @@ -40,7 +40,7 @@ int nv10_fifo_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; int ret; if ((ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(channel), @@ -64,6 +64,8 @@ nv10_fifo_create_context(drm_device_t *dev, int channel) #endif 0); + /* enable the fifo dma operation */ + NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; + + NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<ramfc) nouveau_gpuobj_ref_del(dev, &chan->ramfc); @@ -81,7 +85,7 @@ int nv10_fifo_load_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp; NV_WRITE(NV03_PFIFO_CACHE1_PUSH1 , 0x00000100 | channel); @@ -123,7 +127,7 @@ int nv10_fifo_save_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp; RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); -- cgit v1.2.3