From 0b87f143c466f7e5bd730895ee29f1cd20a68f9b Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 16 Dec 2009 15:22:26 -0800 Subject: intel: Replace IS_G4X() across the driver with context structure usage. Saves ~2KB of code. --- src/mesa/drivers/dri/i965/brw_clip_state.c | 2 +- src/mesa/drivers/dri/i965/brw_clip_util.c | 7 +++--- src/mesa/drivers/dri/i965/brw_context.c | 32 ++++++++++++++++++++++++ src/mesa/drivers/dri/i965/brw_context.h | 11 +++++++- src/mesa/drivers/dri/i965/brw_defines.h | 9 ++----- src/mesa/drivers/dri/i965/brw_eu_emit.c | 2 +- src/mesa/drivers/dri/i965/brw_fallback.c | 4 +-- src/mesa/drivers/dri/i965/brw_misc_state.c | 10 ++++---- src/mesa/drivers/dri/i965/brw_urb.c | 9 ++++--- src/mesa/drivers/dri/i965/brw_vs_state.c | 14 ++--------- src/mesa/drivers/dri/i965/brw_wm_emit.c | 3 +-- src/mesa/drivers/dri/i965/brw_wm_state.c | 18 ++----------- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 ++-- 13 files changed, 69 insertions(+), 57 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c index 28ed634631..c8f24a94e4 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_state.c +++ b/src/mesa/drivers/dri/i965/brw_clip_state.c @@ -131,7 +131,7 @@ clip_unit_create_from_key(struct brw_context *brw, clip.clip5.api_mode = BRW_CLIP_API_OGL; clip.clip5.clip_mode = key->clip_mode; - if (BRW_IS_G4X(brw)) + if (intel->is_g4x) clip.clip5.negative_w_clip_test = 1; clip.clip6.clipper_viewport_state_ptr = 0; diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c b/src/mesa/drivers/dri/i965/brw_clip_util.c index 091ebfc34c..86fed59fa4 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_util.c +++ b/src/mesa/drivers/dri/i965/brw_clip_util.c @@ -135,6 +135,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c, GLboolean force_edgeflag) { struct brw_compile *p = &c->func; + struct intel_context *intel = &p->brw->intel; struct brw_reg tmp = get_tmp(c); GLuint i; @@ -142,7 +143,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c, */ /* * After CLIP stage, only first 256 bits of the VUE are read - * back on IGDNG, so needn't change it + * back on Ironlake, so needn't change it */ brw_copy_indirect_to_indirect(p, dest_ptr, v0_ptr, 1); @@ -151,7 +152,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c, for (i = 0; i < c->nr_attrs; i++) { GLuint delta = i*16 + 32; - if (BRW_IS_IGDNG(p->brw)) + if (intel->is_ironlake) delta = i * 16 + 32 * 3; if (delta == c->offset[VERT_RESULT_EDGE]) { @@ -185,7 +186,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c, if (i & 1) { GLuint delta = i*16 + 32; - if (BRW_IS_IGDNG(p->brw)) + if (intel->is_ironlake) delta = i * 16 + 32 * 3; brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(0)); diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 78bea82949..282566f8d5 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -158,6 +158,38 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis, MIN2(ctx->Const.FragmentProgram.MaxNativeParameters, ctx->Const.FragmentProgram.MaxEnvParams); + if (intel->is_ironlake || intel->is_g4x) { + brw->CMD_VF_STATISTICS = CMD_VF_STATISTICS_GM45; + brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_GM45; + brw->has_surface_tile_offset = GL_TRUE; + brw->has_compr4 = GL_TRUE; + } else { + brw->CMD_VF_STATISTICS = CMD_VF_STATISTICS_965; + brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_965; + brw->has_surface_tile_offset = GL_FALSE; + brw->has_compr4 = GL_FALSE; + } + + /* WM maximum threads is number of EUs times number of threads per EU. */ + if (intel->is_ironlake) { + brw->urb.size = 1024; + brw->vs_max_threads = 72; + brw->wm_max_threads = 12 * 6; + } else if (intel->is_g4x) { + brw->urb.size = 384; + brw->vs_max_threads = 32; + brw->wm_max_threads = 10 * 5; + } else { + brw->urb.size = 256; + brw->vs_max_threads = 16; + brw->wm_max_threads = 8 * 4; + } + + if (INTEL_DEBUG & DEBUG_SINGLE_THREAD) { + brw->vs_max_threads = 1; + brw->wm_max_threads = 1; + } + brw_init_state( brw ); brw->state.dirty.mesa = ~0; diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index e73e21433c..4ae48bba05 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -438,7 +438,9 @@ struct brw_context GLuint primitive; GLboolean emit_state_always; - + GLboolean has_surface_tile_offset; + GLboolean has_compr4; +; struct { struct brw_state_flags dirty; @@ -514,6 +516,12 @@ struct brw_context */ GLuint next_free_page; + /* hw-dependent 3DSTATE_VF_STATISTICS opcode */ + uint32_t CMD_VF_STATISTICS; + /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */ + uint32_t CMD_PIPELINE_SELECT; + int vs_max_threads; + int wm_max_threads; /* BRW_NEW_URB_ALLOCATIONS: */ @@ -541,6 +549,7 @@ struct brw_context GLuint clip_start; GLuint sf_start; GLuint cs_start; + GLuint size; /* Hardware URB size, in KB. */ } urb; diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index c19510bbd4..2ee331a200 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -832,12 +832,7 @@ #include "intel_chipset.h" -#define BRW_IS_G4X(brw) (IS_G4X((brw)->intel.intelScreen->deviceID)) -#define BRW_IS_IGDNG(brw) (IS_IGDNG((brw)->intel.intelScreen->deviceID)) -#define BRW_IS_965(brw) (!(BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))) -#define CMD_PIPELINE_SELECT(brw) ((BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw)) ? CMD_PIPELINE_SELECT_GM45 : CMD_PIPELINE_SELECT_965) -#define CMD_VF_STATISTICS(brw) ((BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw)) ? CMD_VF_STATISTICS_GM45 : CMD_VF_STATISTICS_965) -#define URB_SIZES(brw) (BRW_IS_IGDNG(brw) ? 1024 : \ - (BRW_IS_G4X(brw) ? 384 : 256)) /* 512 bit units */ +#define BRW_IS_965(brw) (!(brw)->intel.is_g4x && \ + !(brw)->intel.is_ironlake) #endif diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 67673e9911..3413c96928 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -452,7 +452,7 @@ static void brw_set_sampler_message(struct brw_context *brw, insn->bits3.sampler_igdng.end_of_thread = eot; insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_SAMPLER; insn->bits2.send_igdng.end_of_thread = eot; - } else if (BRW_IS_G4X(brw)) { + } else if (intel->is_g4x) { insn->bits3.sampler_g4x.binding_table_index = binding_table_index; insn->bits3.sampler_g4x.sampler = sampler; insn->bits3.sampler_g4x.msg_type = msg_type; diff --git a/src/mesa/drivers/dri/i965/brw_fallback.c b/src/mesa/drivers/dri/i965/brw_fallback.c index 562a17844b..fe5c1ae279 100644 --- a/src/mesa/drivers/dri/i965/brw_fallback.c +++ b/src/mesa/drivers/dri/i965/brw_fallback.c @@ -47,7 +47,6 @@ static GLboolean do_check_fallback(struct brw_context *brw) { - struct intel_context *intel = &brw->intel; GLcontext *ctx = &brw->intel.ctx; GLuint i; @@ -86,8 +85,7 @@ static GLboolean do_check_fallback(struct brw_context *brw) } /* _NEW_BUFFERS */ - if (IS_965(intel->intelScreen->deviceID) && - !IS_G4X(intel->intelScreen->deviceID)) { + if (!brw->has_surface_tile_offset) { for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i]; struct intel_renderbuffer *irb = intel_renderbuffer(rb); diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 6cb2da28e6..fd14eaa612 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -212,7 +212,7 @@ static void emit_depthbuffer(struct brw_context *brw) { struct intel_context *intel = &brw->intel; struct intel_region *region = brw->state.depth_region; - unsigned int len = (BRW_IS_G4X(brw) || intel->is_ironlake) ? 6 : 5; + unsigned int len = (intel->is_g4x || intel->is_ironlake) ? 6 : 5; if (region == NULL) { BEGIN_BATCH(len, IGNORE_CLIPRECTS); @@ -223,7 +223,7 @@ static void emit_depthbuffer(struct brw_context *brw) OUT_BATCH(0); OUT_BATCH(0); - if (BRW_IS_G4X(brw) || intel->is_ironlake) + if (intel->is_g4x || intel->is_ironlake) OUT_BATCH(0); ADVANCE_BATCH(); @@ -262,7 +262,7 @@ static void emit_depthbuffer(struct brw_context *brw) ((region->height - 1) << 19)); OUT_BATCH(0); - if (BRW_IS_G4X(brw) || intel->is_ironlake) + if (intel->is_g4x || intel->is_ironlake) OUT_BATCH(0); ADVANCE_BATCH(); @@ -444,7 +444,7 @@ static void upload_invarient_state( struct brw_context *brw ) struct brw_pipeline_select ps; memset(&ps, 0, sizeof(ps)); - ps.header.opcode = CMD_PIPELINE_SELECT(brw); + ps.header.opcode = brw->CMD_PIPELINE_SELECT; ps.header.pipeline_select = 0; BRW_BATCH_STRUCT(brw, &ps); } @@ -480,7 +480,7 @@ static void upload_invarient_state( struct brw_context *brw ) struct brw_vf_statistics vfs; memset(&vfs, 0, sizeof(vfs)); - vfs.opcode = CMD_VF_STATISTICS(brw); + vfs.opcode = brw->CMD_VF_STATISTICS; if (INTEL_DEBUG & DEBUG_STATS) vfs.statistics_enable = 1; diff --git a/src/mesa/drivers/dri/i965/brw_urb.c b/src/mesa/drivers/dri/i965/brw_urb.c index e1e8a90ca7..f2cdb203b8 100644 --- a/src/mesa/drivers/dri/i965/brw_urb.c +++ b/src/mesa/drivers/dri/i965/brw_urb.c @@ -105,7 +105,8 @@ static GLboolean check_urb_layout( struct brw_context *brw ) brw->urb.sf_start = brw->urb.clip_start + brw->urb.nr_clip_entries * brw->urb.vsize; brw->urb.cs_start = brw->urb.sf_start + brw->urb.nr_sf_entries * brw->urb.sfsize; - return brw->urb.cs_start + brw->urb.nr_cs_entries * brw->urb.csize <= URB_SIZES(brw); + return brw->urb.cs_start + brw->urb.nr_cs_entries * + brw->urb.csize <= brw->urb.size; } /* Most minimal update, forces re-emit of URB fence packet after GS @@ -157,7 +158,7 @@ static void recalculate_urb_fence( struct brw_context *brw ) brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries; brw->urb.nr_sf_entries = limits[SF].preferred_nr_entries; } - } else if (BRW_IS_G4X(brw)) { + } else if (intel->is_g4x) { brw->urb.nr_vs_entries = 64; if (check_urb_layout(brw)) { goto done; @@ -201,7 +202,7 @@ done: brw->urb.clip_start, brw->urb.sf_start, brw->urb.cs_start, - URB_SIZES(brw)); + brw->urb.size); brw->state.dirty.brw |= BRW_NEW_URB_FENCE; } @@ -245,7 +246,7 @@ void brw_upload_urb_fence(struct brw_context *brw) uf.bits0.gs_fence = brw->urb.clip_start; uf.bits0.clp_fence = brw->urb.sf_start; uf.bits1.sf_fence = brw->urb.cs_start; - uf.bits1.cs_fence = URB_SIZES(brw); + uf.bits1.cs_fence = brw->urb.size; BRW_BATCH_STRUCT(brw, &uf); } diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c index fdc55aa1b2..345ffa7ee1 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_state.c +++ b/src/mesa/drivers/dri/i965/brw_vs_state.c @@ -85,7 +85,6 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key) struct intel_context *intel = &brw->intel; struct brw_vs_unit_state vs; dri_bo *bo; - int chipset_max_threads; memset(&vs, 0, sizeof(vs)); @@ -136,7 +135,7 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key) case 32: break; case 64: - assert(BRW_IS_G4X(brw)); + assert(intel->is_g4x); break; default: assert(0); @@ -146,17 +145,8 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key) vs.thread4.urb_entry_allocation_size = key->urb_size - 1; - if (intel->is_ironlake) - chipset_max_threads = 72; - else if (BRW_IS_G4X(brw)) - chipset_max_threads = 32; - else - chipset_max_threads = 16; vs.thread4.max_threads = CLAMP(key->nr_urb_entries / 2, - 1, chipset_max_threads) - 1; - - if (INTEL_DEBUG & DEBUG_SINGLE_THREAD) - vs.thread4.max_threads = 0; + 1, brw->vs_max_threads) - 1; /* No samplers for ARB_vp programs: */ diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index bcaa793de1..7811689d6a 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -1162,7 +1162,6 @@ void emit_fb_write(struct brw_wm_compile *c, { struct brw_compile *p = &c->func; struct brw_context *brw = p->brw; - struct intel_context *intel = &brw->intel; GLuint nr = 2; GLuint channel; @@ -1177,7 +1176,7 @@ void emit_fb_write(struct brw_wm_compile *c, brw_push_insn_state(p); for (channel = 0; channel < 4; channel++) { - if (c->dispatch_width == 16 && (BRW_IS_G4X(brw) || intel->is_ironlake)) { + if (c->dispatch_width == 16 && brw->has_compr4) { /* By setting the high bit of the MRF register number, we indicate * that we want COMPR4 mode - instead of doing the usual destination * + 1 for the second half we get destination + 4. diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index fe795fadf8..d3373ea79e 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -49,8 +49,6 @@ struct brw_wm_unit_key { unsigned int curbe_offset; unsigned int urb_size; - unsigned int max_threads; - unsigned int nr_surfaces, sampler_count; GLboolean uses_depth, computes_depth, uses_kill, is_glsl; GLboolean polygon_stipple, stats_wm, line_stipple, offset_enable; @@ -67,18 +65,6 @@ wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key) memset(key, 0, sizeof(*key)); - if (INTEL_DEBUG & DEBUG_SINGLE_THREAD) - key->max_threads = 1; - else { - /* WM maximum threads is number of EUs times number of threads per EU. */ - if (intel->is_ironlake) - key->max_threads = 12 * 6; - else if (BRW_IS_G4X(brw)) - key->max_threads = 10 * 5; - else - key->max_threads = 8 * 4; - } - /* CACHE_NEW_WM_PROG */ key->total_grf = brw->wm.prog_data->total_grf; key->urb_entry_read_length = brw->wm.prog_data->urb_read_length; @@ -192,7 +178,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key, else wm.wm5.enable_16_pix = 1; - wm.wm5.max_threads = key->max_threads - 1; + wm.wm5.max_threads = brw->wm_max_threads - 1; wm.wm5.thread_dispatch_enable = 1; /* AKA: color_write */ wm.wm5.legacy_line_rast = 0; wm.wm5.legacy_global_depth_bias = 0; @@ -269,7 +255,7 @@ static void upload_wm_unit( struct brw_context *brw ) */ assert(key.total_scratch <= 12 * 1024); if (key.total_scratch) { - GLuint total = key.total_scratch * key.max_threads; + GLuint total = key.total_scratch * brw->wm_max_threads; if (brw->wm.scratch_bo && total > brw->wm.scratch_bo->size) { dri_bo_unreference(brw->wm.scratch_bo); diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 8335e5a650..8810f2a380 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -608,8 +608,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw, surf.ss1.base_addr = key.draw_offset - tile_offset; - assert(BRW_IS_G4X(brw) || tile_offset == 0); - if (BRW_IS_G4X(brw)) { + if (brw->has_surface_tile_offset) { if (key.tiling == I915_TILING_X) { /* Note that the low bits of these fields are missing, so * there's the possibility of getting in trouble. @@ -620,6 +619,8 @@ brw_update_renderbuffer_surface(struct brw_context *brw, surf.ss5.x_offset = (tile_offset % 128) / key.cpp / 4; surf.ss5.y_offset = tile_offset / 128 / 2; } + } else { + assert(tile_offset == 0); } } if (region_bo != NULL) -- cgit v1.2.3