diff options
| author | merge <null@invalid> | 2008-12-03 11:20:14 +0000 |
|---|---|---|
| committer | Andy Green <agreen@pads.home.warmcat.com> | 2008-12-03 11:20:14 +0000 |
| commit | 1e664d4740009ac49c2a2f85ffc994c12ee040bd (patch) | |
| tree | bb4f41fda406a637dacffdd74235250d05b689e9 | |
| parent | 6c19559f4c6d0697f9c9c7706970ce70bb3d64c6 (diff) | |
MERGE-via-pending-tracking-hist-MERGE-via-stable-tracking-MERGE-via-mokopatches-tracking-MERGE-via-master-1228302402-1228302766-1228303138
pending-tracking-hist top was MERGE-via-stable-tracking-MERGE-via-mokopatches-tracking-MERGE-via-master-1228302402-1228302766-1228303138 / 27d86638fe294ef1d1a8f527564ec37bb20e7ef2 ... parent commitmessage:
From: merge <null@invalid>
MERGE-via-stable-tracking-hist-MERGE-via-mokopatches-tracking-MERGE-via-master-1228302402-1228302766
stable-tracking-hist top was MERGE-via-mokopatches-tracking-MERGE-via-master-1228302402-1228302766 / 66e84c4be853030f1cea816a124cf76a741ecc08 ... parent commitmessage:
From: merge <null@invalid>
MERGE-via-mokopatches-tracking-hist-MERGE-via-master-1228302402
mokopatches-tracking-hist top was MERGE-via-master-1228302402 / de9177f7bd127e9b6fa6213018c7c731b8ca0d0c ... parent commitmessage:
From: merge <null@invalid>
MERGE-via-master-
master top was / 3838a80929f91d35c6d987e518bf9ea397f3e13c ... parent commitmessage:
From: Andy Green <andy@openmoko.com>
fix-wm8753-DBG.patch
Signed-off-by: Andy Green <andy@openmoko.com>
58 files changed, 2306 insertions, 894 deletions
diff --git a/Documentation/arm/Samsung-S3C24XX/Suspend.txt b/Documentation/arm/Samsung-S3C24XX/Suspend.txt index 0dab6e32c13..a30fe510572 100644 --- a/Documentation/arm/Samsung-S3C24XX/Suspend.txt +++ b/Documentation/arm/Samsung-S3C24XX/Suspend.txt @@ -40,13 +40,13 @@ Resuming Machine Support --------------- - The machine specific functions must call the s3c2410_pm_init() function + The machine specific functions must call the s3c_pm_init() function to say that its bootloader is capable of resuming. This can be as simple as adding the following to the machine's definition: - INITMACHINE(s3c2410_pm_init) + INITMACHINE(s3c_pm_init) - A board can do its own setup before calling s3c2410_pm_init, if it + A board can do its own setup before calling s3c_pm_init, if it needs to setup anything else for power management support. There is currently no support for over-riding the default method of @@ -74,7 +74,7 @@ statuc void __init machine_init(void) enable_irq_wake(IRQ_EINT0); - s3c2410_pm_init(); + s3c_pm_init(); } diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h new file mode 100644 index 00000000000..ce1ec69806a --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h @@ -0,0 +1,23 @@ +/* arch/arm/mach-s3c2410/include/mach/gpio-nrs.h + * + * Copyright (c) 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C2410 - GPIO bank numbering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) + +#define S3C2410_GPIO_BANKA (32*0) +#define S3C2410_GPIO_BANKB (32*1) +#define S3C2410_GPIO_BANKC (32*2) +#define S3C2410_GPIO_BANKD (32*3) +#define S3C2410_GPIO_BANKE (32*4) +#define S3C2410_GPIO_BANKF (32*5) +#define S3C2410_GPIO_BANKG (32*6) +#define S3C2410_GPIO_BANKH (32*7) diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h index 7232f8ca474..aa997ba798a 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio.h @@ -23,3 +23,6 @@ /* -- cut to here when generic irq makes it */ #include <asm-generic/gpio.h> +#include <mach/gpio-nrs.h> + +#define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32) diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h index ff43c229b99..4a82338c287 100644 --- a/arch/arm/mach-s3c2410/include/mach/irqs.h +++ b/arch/arm/mach-s3c2410/include/mach/irqs.h @@ -84,7 +84,7 @@ #define IRQ_EINT22 S3C2410_IRQ(50) #define IRQ_EINT23 S3C2410_IRQ(51) - +#define IRQ_EINT_BIT(x) ((x) - (IRQ_EINT4 + 4)) #define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) #define IRQ_LCD_FIFO S3C2410_IRQ(52) diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h index 32107761306..35a03df473f 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h @@ -14,16 +14,7 @@ #ifndef __ASM_ARCH_REGS_GPIO_H #define __ASM_ARCH_REGS_GPIO_H -#define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) - -#define S3C2410_GPIO_BANKA (32*0) -#define S3C2410_GPIO_BANKB (32*1) -#define S3C2410_GPIO_BANKC (32*2) -#define S3C2410_GPIO_BANKD (32*3) -#define S3C2410_GPIO_BANKE (32*4) -#define S3C2410_GPIO_BANKF (32*5) -#define S3C2410_GPIO_BANKG (32*6) -#define S3C2410_GPIO_BANKH (32*7) +#include <mach/gpio-nrs.h> #ifdef CONFIG_CPU_S3C2400 #define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x) diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index a38327ded86..e4ff37191b2 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -209,7 +209,7 @@ static void __init h1940_map_io(void) #ifdef CONFIG_PM_H1940 memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024); #endif - s3c2410_pm_init(); + s3c_pm_init(); } static void __init h1940_init_irq(void) diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c index 749dcd7a868..db0d8675f1d 100644 --- a/arch/arm/mach-s3c2410/mach-qt2410.c +++ b/arch/arm/mach-s3c2410/mach-qt2410.c @@ -373,7 +373,7 @@ static void __init qt2410_machine_init(void) s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT); platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices)); - s3c2410_pm_init(); + s3c_pm_init(); } MACHINE_START(QT2410, "QT2410") diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c index a6970f61319..24fb0a19001 100644 --- a/arch/arm/mach-s3c2410/pm.c +++ b/arch/arm/mach-s3c2410/pm.c @@ -48,7 +48,7 @@ static void s3c2410_pm_prepare(void) { /* ensure at least GSTATUS3 has the resume address */ - __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3); + __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3); DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c index e08a0f06224..1172708d015 100644 --- a/arch/arm/mach-s3c2412/mach-jive.c +++ b/arch/arm/mach-s3c2412/mach-jive.c @@ -493,7 +493,7 @@ static int jive_pm_suspend(struct sys_device *sd, pm_message_t state) * correct address to resume from. */ __raw_writel(0x2BED, S3C2412_INFORM0); - __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2412_INFORM1); + __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1); return 0; } @@ -629,7 +629,7 @@ static void __init jive_machine_init(void) /* initialise the power management now we've setup everything. */ - s3c2410_pm_init(); + s3c_pm_init(); s3c_device_nand.dev.platform_data = &jive_nand_info; diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c index 217e9e4ed45..c9cfe40e21f 100644 --- a/arch/arm/mach-s3c2412/pm.c +++ b/arch/arm/mach-s3c2412/pm.c @@ -85,7 +85,7 @@ static struct sleep_save s3c2412_sleep[] = { static int s3c2412_pm_suspend(struct sys_device *dev, pm_message_t state) { - s3c2410_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep)); + s3c_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep)); return 0; } @@ -98,7 +98,7 @@ static int s3c2412_pm_resume(struct sys_device *dev) tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE; __raw_writel(tmp, S3C2412_PWRCFG); - s3c2410_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep)); + s3c_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep)); return 0; } diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c index 12d378f84ad..bc8d8d1ebd1 100644 --- a/arch/arm/mach-s3c2440/mach-rx3715.c +++ b/arch/arm/mach-s3c2440/mach-rx3715.c @@ -203,7 +203,7 @@ static void __init rx3715_init_machine(void) #ifdef CONFIG_PM_H1940 memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024); #endif - s3c2410_pm_init(); + s3c_pm_init(); s3c24xx_fb_set_platdata(&rx3715_fb_info); platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices)); diff --git a/arch/arm/mach-s3c24a0/include/mach/irqs.h b/arch/arm/mach-s3c24a0/include/mach/irqs.h index ae8c0e35978..83ce2a7a9da 100644 --- a/arch/arm/mach-s3c24a0/include/mach/irqs.h +++ b/arch/arm/mach-s3c24a0/include/mach/irqs.h @@ -70,6 +70,8 @@ #define IRQ_EINT17 S3C2410_IRQ(49) #define IRQ_EINT18 S3C2410_IRQ(50) +#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT00) + /* SUB IRQS */ #define IRQ_S3CUART_RX0 S3C2410_IRQ(51) /* 67 */ #define IRQ_S3CUART_TX0 S3C2410_IRQ(52) diff --git a/arch/arm/mach-s3c6400/include/mach/regs-clock.h b/arch/arm/mach-s3c6400/include/mach/regs-clock.h new file mode 100644 index 00000000000..a6c7f4eb3a1 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/regs-clock.h @@ -0,0 +1,16 @@ +/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C64XX - clock register compatibility with s3c24xx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <plat/regs-clock.h> + diff --git a/arch/arm/mach-s3c6400/include/mach/system.h b/arch/arm/mach-s3c6400/include/mach/system.h index 652bbc403f0..3165f509780 100644 --- a/arch/arm/mach-s3c6400/include/mach/system.h +++ b/arch/arm/mach-s3c6400/include/mach/system.h @@ -11,9 +11,29 @@ #ifndef __ASM_ARCH_SYSTEM_H #define __ASM_ARCH_SYSTEM_H __FILE__ +#include <linux/io.h> +#include <mach/map.h> + +#include <plat/regs-sys.h> +#include <plat/regs-syscon-power.h> + static void arch_idle(void) { - /* nothing here yet */ + unsigned long flags; + u32 mode; + + /* ensure that if we execute the cpu idle sequence that we + * go into idle mode instead of powering off. */ + + local_irq_save(flags); + mode = __raw_readl(S3C64XX_PWR_CFG); + mode &= ~S3C64XX_PWRCFG_CFG_WFI_MASK; + mode |= S3C64XX_PWRCFG_CFG_WFI_IDLE; + __raw_writel(mode, S3C64XX_PWR_CFG); + + local_irq_restore(flags); + + cpu_do_idle(); } static void arch_reset(char mode) diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c index 3c4d47145c8..a3d3b3187de 100644 --- a/arch/arm/mach-s3c6410/mach-smdk6410.c +++ b/arch/arm/mach-s3c6410/mach-smdk6410.c @@ -39,8 +39,10 @@ #include <asm/mach-types.h> #include <plat/regs-serial.h> +#include <plat/regs-gpio.h> #include <plat/iic.h> #include <plat/fb.h> +#include <plat/pm.h> #include <plat/s3c6410.h> #include <plat/clock.h> @@ -158,10 +160,15 @@ static void __init smdk6410_map_io(void) s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs)); + + /* do not change gpio settings over sleep to xxxSLPCON */ + __raw_writel(S3C64XX_SLPEN_CFG_BYSLPEN, S3C64XX_SLPEN); } static void __init smdk6410_machine_init(void) { + s3c_pm_init(); + s3c_i2c0_set_platdata(NULL); s3c_i2c1_set_platdata(NULL); s3c_fb_set_platdata(&smdk6410_lcd_pdata); diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig index def0bb457ca..d47091d5c68 100644 --- a/arch/arm/plat-s3c/Kconfig +++ b/arch/arm/plat-s3c/Kconfig @@ -75,6 +75,15 @@ config S3C2410_PM_DEBUG Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> for more information. +config S3C_PM_DEBUG_LED_SMDK + bool "SMDK LED suspend/resume debugging" + depends on PM && (MACH_SMDK6410) + help + Say Y here to enable the use of the SMDK LEDs on the baseboard + for debugging of the state of the suspend and resume process. + + Note, this currently only works for S3C64XX based SMDK boards. + config S3C2410_PM_CHECK bool "S3C2410 PM Suspend Memory CRC" depends on PLAT_S3C && PM && CRC32 diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index 39195f972d5..c77fcae5529 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile @@ -18,6 +18,12 @@ obj-y += pwm-clock.o obj-y += gpio.o obj-y += gpio-config.o +# PM support + +obj-$(CONFIG_PM) += pm.o +obj-$(CONFIG_PM) += pm-gpio.o +obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o + # devices obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o diff --git a/arch/arm/plat-s3c/gpio.c b/arch/arm/plat-s3c/gpio.c index d71dd6d9ce5..260fdc6ad68 100644 --- a/arch/arm/plat-s3c/gpio.c +++ b/arch/arm/plat-s3c/gpio.c @@ -16,7 +16,7 @@ #include <linux/io.h> #include <linux/gpio.h> -#include <plat/gpio-core.h> +#include <mach/gpio-core.h> #ifdef CONFIG_S3C_GPIO_TRACK struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; @@ -140,6 +140,15 @@ __init void s3c_gpiolib_add(struct s3c_gpio_chip *chip) if (!gc->get) gc->get = s3c_gpiolib_get; +#ifdef CONFIG_PM + if (chip->pm != NULL) { + if (!chip->pm->save || !chip->pm->resume) + printk(KERN_ERR "gpio: %s has missing PM functions\n", + gc->label); + } else + printk(KERN_ERR "gpio: %s has no PM function\n", gc->label); +#endif + /* gpiochip_add() prints own failure message on error. */ ret = gpiochip_add(gc); if (ret >= 0) diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h index e62ae0fcfe5..be541cbba07 100644 --- a/arch/arm/plat-s3c/include/plat/cpu.h +++ b/arch/arm/plat-s3c/include/plat/cpu.h @@ -69,3 +69,6 @@ extern struct sysdev_class s3c2412_sysclass; extern struct sysdev_class s3c2440_sysclass; extern struct sysdev_class s3c2442_sysclass; extern struct sysdev_class s3c2443_sysclass; +extern struct sysdev_class s3c6410_sysclass; +extern struct sysdev_class s3c64xx_sysclass; + diff --git a/arch/arm/plat-s3c/include/plat/gpio-core.h b/arch/arm/plat-s3c/include/plat/gpio-core.h index 2fc60a580ac..32af612767a 100644 --- a/arch/arm/plat-s3c/include/plat/gpio-core.h +++ b/arch/arm/plat-s3c/include/plat/gpio-core.h @@ -20,6 +20,18 @@ * specific code. */ +struct s3c_gpio_chip; + +/** + * struct s3c_gpio_pm - power management (suspend/resume) information + * @save: Routine to save the state of the GPIO block + * @resume: Routine to resume the GPIO block. + */ +struct s3c_gpio_pm { + void (*save)(struct s3c_gpio_chip *chip); + void (*resume)(struct s3c_gpio_chip *chip); +}; + struct s3c_gpio_cfg; /** @@ -27,6 +39,7 @@ struct s3c_gpio_cfg; * @chip: The chip structure to be exported via gpiolib. * @base: The base pointer to the gpio configuration registers. * @config: special function and pull-resistor control information. + * @pm_save: Save information for suspend/resume support. * * This wrapper provides the necessary information for the Samsung * specific gpios being registered with gpiolib. @@ -34,7 +47,11 @@ struct s3c_gpio_cfg; struct s3c_gpio_chip { struct gpio_chip chip; struct s3c_gpio_cfg *config; + struct s3c_gpio_pm *pm; void __iomem *base; +#ifdef CONFIG_PM + u32 pm_save[4]; +#endif }; static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc) @@ -75,3 +92,16 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip) static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { } #endif + +#ifdef CONFIG_PM +extern struct s3c_gpio_pm s3c_gpio_pm_1bit; +extern struct s3c_gpio_pm s3c_gpio_pm_2bit; +extern struct s3c_gpio_pm s3c_gpio_pm_4bit; +#define __gpio_pm(x) x +#else +#define s3c_gpio_pm_1bit NULL +#define s3c_gpio_pm_2bit NULL +#define s3c_gpio_pm_4bit NULL +#define __gpio_pm(x) NULL + +#endif /* CONFIG_PM */ diff --git a/arch/arm/plat-s3c24xx/include/plat/pm.h b/arch/arm/plat-s3c/include/plat/pm.h index c384d02d4cf..c384d02d4cf 100644 --- a/arch/arm/plat-s3c24xx/include/plat/pm.h +++ b/arch/arm/plat-s3c/include/plat/pm.h diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h index 487d7d2a7e1..66af75a5cdd 100644 --- a/arch/arm/plat-s3c/include/plat/regs-serial.h +++ b/arch/arm/plat-s3c/include/plat/regs-serial.h @@ -189,6 +189,11 @@ #define S3C2443_DIVSLOT (0x2C) +/* S3C64XX interrupt registers. */ +#define S3C64XX_UINTP 0x30 +#define S3C64XX_UINTSP 0x34 +#define S3C64XX_UINTM 0x38 + #ifndef __ASSEMBLY__ /* struct s3c24xx_uart_clksrc diff --git a/arch/arm/plat-s3c/pm-check.c b/arch/arm/plat-s3c/pm-check.c new file mode 100644 index 00000000000..7f21bef09c3 --- /dev/null +++ b/arch/arm/plat-s3c/pm-check.c @@ -0,0 +1,222 @@ +/* linux/arch/arm/plat-s3c/pm-check.c + * originally in linux/arch/arm/plat-s3c24xx/pm.c + * + * Copyright (c) 2004,2006,2008 Simtec Electronics + * http://armlinux.simtec.co.uk + * Ben Dooks <ben@simtec.co.uk> + * + * S3C Power Mangament - suspend/resume memory corruptiuon check. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/suspend.h> +#include <linux/init.h> +#include <linux/crc32.h> +#include <linux/ioport.h> + +#include <plat/pm.h> + +#if CONFIG_S3C2410_PM_CHECK_CHUNKSIZE < 1 +#error CONFIG_S3C2410_PM_CHECK_CHUNKSIZE must be a positive non-zero value +#endif + +/* suspend checking code... + * + * this next area does a set of crc checks over all the installed + * memory, so the system can verify if the resume was ok. + * + * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC, + * increasing it will mean that the area corrupted will be less easy to spot, + * and reducing the size will cause the CRC save area to grow +*/ + +#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024) + +static u32 crc_size; /* size needed for the crc block */ +static u32 *crcs; /* allocated over suspend/resume */ + +typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg); + +/* s3c_pm_run_res + * + * go thorugh the given resource list, and look for system ram +*/ + +static void s3c_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg) +{ + while (ptr != NULL) { + if (ptr->child != NULL) + s3c_pm_run_res(ptr->child, fn, arg); + + if ((ptr->flags & IORESOURCE_MEM) && + strcmp(ptr->name, "System RAM") == 0) { + S3C_PMDBG("Found system RAM at %08lx..%08lx\n", + (unsigned long)ptr->start, + (unsigned long)ptr->end); + arg = (fn)(ptr, arg); + } + + ptr = ptr->sibling; + } +} + +static void s3c_pm_run_sysram(run_fn_t fn, u32 *arg) +{ + s3c_pm_run_res(&iomem_resource, fn, arg); +} + +static u32 *s3c_pm_countram(struct resource *res, u32 *val) +{ + u32 size = (u32)(res->end - res->start)+1; + + size += CHECK_CHUNKSIZE-1; + size /= CHECK_CHUNKSIZE; + + S3C_PMDBG("Area %08lx..%08lx, %d blocks\n", + (unsigned long)res->start, (unsigned long)res->end, size); + + *val += size * sizeof(u32); + return val; +} + +/* s3c_pm_prepare_check + * + * prepare the necessary information for creating the CRCs. This + * must be done before the final save, as it will require memory + * allocating, and thus touching bits of the kernel we do not + * know about. +*/ + +void s3c_pm_check_prepare(void) +{ + crc_size = 0; + + s3c_pm_run_sysram(s3c_pm_countram, &crc_size); + + S3C_PMDBG("s3c_pm_prepare_check: %u checks needed\n", crc_size); + + crcs = kmalloc(crc_size+4, GFP_KERNEL); + if (crcs == NULL) + printk(KERN_ERR "Cannot allocated CRC save area\n"); +} + +static u32 *s3c_pm_makecheck(struct resource *res, u32 *val) +{ + unsigned long addr, left; + + for (addr = res->start; addr < res->end; + addr += CHECK_CHUNKSIZE) { + left = res->end - addr; + + if (left > CHECK_CHUNKSIZE) + left = CHECK_CHUNKSIZE; + + *val = crc32_le(~0, phys_to_virt(addr), left); + val++; + } + + return val; +} + +/* s3c_pm_check_store + * + * compute the CRC values for the memory blocks before the final + * sleep. +*/ + +void s3c_pm_check_store(void) +{ + if (crcs != NULL) + s3c_pm_run_sysram(s3c_pm_makecheck, crcs); +} + +/* in_region + * + * return TRUE if the area defined by ptr..ptr+size contatins the + * what..what+whatsz +*/ + +static inline int in_region(void *ptr, int size, void *what, size_t whatsz) +{ + if ((what+whatsz) < ptr) + return 0; + + if (what > (ptr+size)) + return 0; + + return 1; +} + +/** + * s3c_pm_runcheck*() - helper to check a resource on restore. + * @res: The resource to check + * @vak: Pointer to list of CRC32 values to check. + * + * Called from the s3c_pm_check_restore() via s3c_pm_run_sysram(), this + * function runs the given memory resource checking it against the stored + * CRC to ensure that memory is restored. The function tries to skip as + * many of the areas used during the suspend process. + */ +static u32 *s3c_pm_runcheck(struct resource *res, u32 *val) +{ + void *save_at = phys_to_virt(s3c_sleep_save_phys); + unsigned long addr; + unsigned long left; + void *ptr; + u32 calc; + + for (addr = res->start; addr < res->end; + addr += CHECK_CHUNKSIZE) { + left = res->end - addr; + + if (left > CHECK_CHUNKSIZE) + left = CHECK_CHUNKSIZE; + + ptr = phys_to_virt(addr); + + if (in_region(ptr, left, crcs, crc_size)) { + S3C_PMDBG("skipping %08lx, has crc block in\n", addr); + goto skip_check; + } + + if (in_region(ptr, left, save_at, 32*4 )) { + S3C_PMDBG("skipping %08lx, has save block in\n", addr); + goto skip_check; + } + + /* calculate and check the checksum */ + + calc = crc32_le(~0, ptr, left); + if (calc != *val) { + printk(KERN_ERR "Restore CRC error at " + "%08lx (%08x vs %08x)\n", addr, calc, *val); + + S3C_PMDBG("Restore CRC error at %08lx (%08x vs %08x)\n", + addr, calc, *val); + } + + skip_check: + val++; + } + + return val; +} + +/** + * s3c_pm_check_restore() - memory check called on resume + * + * check the CRCs after the restore event and free the memory used + * to hold them +*/ +void s3c_pm_check_restore(void) +{ + if (crcs != NULL) { + s3c_pm_run_sysram(s3c_pm_runcheck, crcs); + kfree(crcs); + crcs = NULL; + } +} diff --git a/arch/arm/plat-s3c/pm-gpio.c b/arch/arm/plat-s3c/pm-gpio.c new file mode 100644 index 00000000000..6b5d6ec1dd7 --- /dev/null +++ b/arch/arm/plat-s3c/pm-gpio.c @@ -0,0 +1,378 @@ +/* linux/arch/arm/plat-s3c/pm-gpio.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C series GPIO PM code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/gpio.h> + +#include <mach/gpio-core.h> +#include <plat/pm.h> + +/* PM GPIO helpers */ + +#define OFFS_CON (0x00) +#define OFFS_DAT (0X04) +#define OFFS_UP (0X08) + +static void s3c_gpio_pm_1bit_save(struct s3c_gpio_chip *chip) +{ + chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); + chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); +} + +static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip) +{ + void __iomem *base = chip->base; + u32 old_gpcon = __raw_readl(base + OFFS_CON); + u32 old_gpdat = __raw_readl(base + OFFS_DAT); + u32 gps_gpcon = chip->pm_save[0]; + u32 gps_gpdat = chip->pm_save[1]; + u32 gpcon; + + /* GPACON only has one bit per control / data and no PULLUPs. + * GPACON[x] = 0 => Output, 1 => SFN */ + + /* first set all SFN bits to SFN */ + + gpcon = old_gpcon | gps_gpcon; + __raw_writel(gpcon, base + OFFS_CON); + + /* now set all the other bits */ + + __raw_writel(gps_gpdat, base + OFFS_DAT); + __raw_writel(gps_gpcon, base + OFFS_CON); + + S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n", + chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); +} + +struct s3c_gpio_pm s3c_gpio_pm_1bit = { + .save = s3c_gpio_pm_1bit_save, + .resume = s3c_gpio_pm_1bit_resume, +}; + +static void s3c_gpio_pm_2bit_save(struct s3c_gpio_chip *chip) +{ + chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); + chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); + chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP); +} + +/* Test whether the given masked+shifted bits of an GPIO configuration + * are one of the SFN (special function) modes. */ + +static inline int is_sfn(unsigned long con) +{ + return con >= 2; +} + +/* Test if the given masked+shifted GPIO configuration is an input */ + +static inline int is_in(unsigned long con) +{ + return con == 0; +} + +/* Test if the given masked+shifted GPIO configuration is an output */ + +static inline int is_out(unsigned long con) +{ + return con == 1; +} + +/** + * s3c_gpio_pm_2bit_resume() - restore the given GPIO bank + * @chip: The chip information to resume. + * + * Restore one of the GPIO banks that was saved during suspend. This is + * not as simple as once thought, due to the possibility of glitches + * from the order that the CON and DAT registers are set in. + * + * The three states the pin can be are {IN,OUT,SFN} which gives us 9 + * combinations of changes to check. Three of these, if the pin stays + * in the same configuration can be discounted. This leaves us with + * the following: + * + * { IN => OUT } Change DAT first + * { IN => SFN } Change CON first + * { OUT => SFN } Change CON first, so new data will not glitch + * { OUT => IN } Change CON first, so new data will not glitch + * { SFN => IN } Change CON first + * { SFN => OUT } Change DAT first, so new data will not glitch [1] + * + * We do not currently deal with the UP registers as these control + * weak resistors, so a small delay in change should not need to bring + * these into the calculations. + * + * [1] this assumes that writing to a pin DAT whilst in SFN will set the + * state for when it is next output. + */ +static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip) +{ + void __iomem *base = chip->base; + u32 old_gpcon = __raw_readl(base + OFFS_CON); + u32 old_gpdat = __raw_readl(base + OFFS_DAT); + u32 gps_gpcon = chip->pm_save[0]; + u32 gps_gpdat = chip->pm_save[1]; + u32 gpcon, old, new, mask; + u32 change_mask = 0x0; + int nr; + + /* restore GPIO pull-up settings */ + __raw_writel(chip->pm_save[2], base + OFFS_UP); + + /* Create a change_mask of all the items that need to have + * their CON value changed before their DAT value, so that + * we minimise the work between the two settings. + */ + + for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) { + old = (old_gpcon & mask) >> nr; + new = (gps_gpcon & mask) >> nr; + + /* If there is no change, then skip */ + + if (old == new) + continue; + + /* If both are special function, then skip */ + + if (is_sfn(old) && is_sfn(new)) + continue; + + /* Change is IN => OUT, do not change now */ + + if (is_in(old) && is_out(new)) + continue; + + /* Change is SFN => OUT, do not change now */ + + if (is_sfn(old) && is_out(new)) + continue; + + /* We should now be at the case of IN=>SFN, + * OUT=>SFN, OUT=>IN, SFN=>IN. */ + + change_mask |= mask; + } + + + /* Write the new CON settings */ + + gpcon = old_gpcon & ~change_mask; + gpcon |= gps_gpcon & change_mask; + + __raw_writel(gpcon, base + OFFS_CON); + + /* Now change any items that require DAT,CON */ + + __raw_writel(gps_gpdat, base + OFFS_DAT); + __raw_writel(gps_gpcon, base + OFFS_CON); + + S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n", + chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); +} + +struct s3c_gpio_pm s3c_gpio_pm_2bit = { + .save = s3c_gpio_pm_2bit_save, + .resume = s3c_gpio_pm_2bit_resume, +}; + +#ifdef CONFIG_ARCH_S3C64XX +static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip) +{ + chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); + chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT); + chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP); + + if (chip->chip.ngpio > 8) + chip->pm_save[0] = __raw_readl(chip->base - 4); +} + +static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon) +{ + u32 old, new, mask; + u32 change_mask = 0x0; + int nr; + + for (nr = 0, mask = 0x0f; nr < 16; nr += 4, mask <<= 4) { + old = (old_gpcon & mask) >> nr; + new = (gps_gpcon & mask) >> nr; + + /* If there is no change, then skip */ + + if (old == new) + continue; + + /* If both are special function, then skip */ + + if (is_sfn(old) && is_sfn(new)) + continue; + + /* Change is IN => OUT, do not change now */ + + if (is_in(old) && is_out(new)) + continue; + + /* Change is SFN => OUT, do not change now */ + + if (is_sfn(old) && is_out(new)) + continue; + + /* We should now be at the case of IN=>SFN, + * OUT=>SFN, OUT=>IN, SFN=>IN. */ + + change_mask |= mask; + } + + return change_mask; +} + +static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index) +{ + void __iomem *con = chip->base + (index * 4); + u32 old_gpcon = __raw_readl(con); + u32 gps_gpcon = chip->pm_save[index + 1]; + u32 gpcon, mask; + + mask = s3c_gpio_pm_4bit_mask(old_gpcon, gps_gpcon); + + gpcon = old_gpcon & ~mask; + gpcon |= gps_gpcon & mask; + + __raw_writel(gpcon, con); +} + +static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip) +{ + void __iomem *base = chip->base; + u32 old_gpcon[2]; + u32 old_gpdat = __raw_readl(base + OFFS_DAT); + u32 gps_gpdat = chip->pm_save[1]; + + /* First, modify the CON settings */ + + old_gpcon[0] = 0; + old_gpcon[1] = __raw_readl(base + OFFS_CON); + + s3c_gpio_pm_4bit_con(chip, 0); + if (chip->chip.ngpio > 8) { + old_gpcon[0] = __raw_readl(base - 4); + s3c_gpio_pm_4bit_con(chip, -1); + } + + /* Now change the configurations that require DAT,CON */ + + __raw_writel(chip->pm_save[2], base + OFFS_DAT); + __raw_writel(chip->pm_save[1], base + OFFS_CON); + if (chip->chip.ngpio > 8) + __raw_writel(chip->pm_save[0], base - 4); + + __raw_writel(chip->pm_save[2], base + OFFS_DAT); + __raw_writel(chip->pm_save[3], base + OFFS_UP); + + if (chip->chip.ngpio > 8) { + S3C_PMDBG("%s: CON4 %08x => %08x, DAT %08x => %08x\n", + chip->chip.label, old_gpcon[0], old_gpcon[1], + __raw_readl(base - 4), + __raw_readl(base + OFFS_CON), + old_gpdat, gps_gpdat); + } else + S3C_PMDBG("%s: CON4 %08x => %08x, DAT %08x => %08x\n", + chip->chip.label, old_gpcon[1], + __raw_readl(base + OFFS_CON), + old_gpdat, gps_gpdat); +} + +struct s3c_gpio_pm s3c_gpio_pm_4bit = { + .save = s3c_gpio_pm_4bit_save, + .resume = s3c_gpio_pm_4bit_resume, +}; +#endif /* CONFIG_ARCH_S3C64XX */ + +/** + * s3c_pm_save_gpio() - save gpio chip data for suspend + * @ourchip: The chip for suspend. + */ +static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip) +{ + struct s3c_gpio_pm *pm = ourchip->pm; + + if (pm == NULL || pm->save == NULL) + S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label); + else + pm->save(ourchip); +} + +/** + * s3c_pm_save_gpios() - Save the state of the GPIO banks. + * + * For all the GPIO banks, save the state of each one ready for going + * into a suspend mode. + */ +void s3c_pm_save_gpios(void) +{ + struct s3c_gpio_chip *ourchip; + unsigned int gpio_nr; + + for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) { + ourchip = s3c_gpiolib_getchip(gpio_nr); + if (!ourchip) + continue; + + s3c_pm_save_gpio(ourchip); + + S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n", + ourchip->chip.label, + ourchip->pm_save[0], + ourchip->pm_save[1], + ourchip->pm_save[2], + ourchip->pm_save[3]); + + gpio_nr += ourchip->chip.ngpio; + gpio_nr += CONFIG_S3C_GPIO_SPACE; + } +} + +/** + * s3c_pm_resume_gpio() - restore gpio chip data after suspend + * @ourchip: The suspended chip. + */ +static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip) +{ + struct s3c_gpio_pm *pm = ourchip->pm; + + if (pm == NULL || pm->resume == NULL) + S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label); + else + pm->resume(ourchip); +} + +void s3c_pm_restore_gpios(void) +{ + struct s3c_gpio_chip *ourchip; + unsigned int gpio_nr; + + for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) { + ourchip = s3c_gpiolib_getchip(gpio_nr); + if (!ourchip) + continue; + + s3c_pm_resume_gpio(ourchip); + + gpio_nr += ourchip->chip.ngpio; + gpio_nr += CONFIG_S3C_GPIO_SPACE; + } +} diff --git a/arch/arm/plat-s3c/pm.c b/arch/arm/plat-s3c/pm.c new file mode 100644 index 00000000000..ea03e5e75da --- /dev/null +++ b/arch/arm/plat-s3c/pm.c @@ -0,0 +1,375 @@ +/* linux/arch/arm/plat-s3c/pm.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2004,2006,2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C common power management (suspend to ram) support. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/init.h> +#include <linux/suspend.h> +#include <linux/errno.h> +#include <linux/delay.h> +#include <linux/serial_core.h> +#include <linux/io.h> + +#include <asm/cacheflush.h> +#include <mach/hardware.h> +#include <mach/map.h> + +#include <plat/regs-serial.h> +#include <mach/regs-clock.h> +#include <mach/regs-irq.h> +#include <asm/irq.h> + +#include <plat/pm.h> +#include <plat/pm-core.h> + +/* for external use */ + +unsigned long s3c_pm_flags; + +/* Debug code: + * + * This code supports debug output to the low level UARTs for use on + * resume before the console layer is available. +*/ + +#ifdef CONFIG_S3C2410_PM_DEBUG +extern void printascii(const char *); + +void s3c_pm_dbg(const char *fmt, ...) +{ + va_list va; + char buff[256]; + + va_start(va, fmt); + vsprintf(buff, fmt, va); + va_end(va); + + printascii(buff); +} + +static inline void s3c_pm_debug_init(void) +{ + /* restart uart clocks so we can use them to output */ + s3c_pm_debug_init_uart(); +} + +#else +#define s3c_pm_debug_init() do { } while(0) + +#endif /* CONFIG_S3C2410_PM_DEBUG */ + +/* Save the UART configurations if we are configured for debug. */ + +unsigned char pm_uart_udivslot; + +#ifdef CONFIG_S3C2410_PM_DEBUG + +struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS]; + +static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save) +{ + void __iomem *regs = S3C_VA_UARTx(uart); + + save->ulcon = __raw_readl(regs + S3C2410_ULCON); + save->ucon = __raw_readl(regs + S3C2410_UCON); + save->ufcon = __raw_readl(regs + S3C2410_UFCON); + save->umcon = __raw_readl(regs + S3C2410_UMCON); + save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); + + if (pm_uart_udivslot) + save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT); + + S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n", + uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv); +} + +static void s3c_pm_save_uarts(void) +{ + struct pm_uart_save *save = uart_save; + unsigned int uart; + + for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++) + s3c_pm_save_uart(uart, save); +} + +static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save) +{ + void __iomem *regs = S3C_VA_UARTx(uart); + + s3c_pm_arch_update_uart(regs, save); + + __raw_writel(save->ulcon, regs + S3C2410_ULCON); + __raw_writel(save->ucon, regs + S3C2410_UCON); + __raw_writel(save->ufcon, regs + S3C2410_UFCON); + __raw_writel(save->umcon, regs + S3C2410_UMCON); + __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV); + + if (pm_uart_udivslot) + __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT); +} + +static void s3c_pm_restore_uarts(void) +{ + struct pm_uart_save *save = uart_save; + unsigned int uart; + + for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++) + s3c_pm_restore_uart(uart, save); +} +#else +static void s3c_pm_save_uarts(void) { } +static void s3c_pm_restore_uarts(void) { } +#endif + +/* The IRQ ext-int code goes here, it is too small to currently bother + * with its own file. */ + +unsigned long s3c_irqwake_intmask = 0xffffffffL; +unsigned long s3c_irqwake_eintmask = 0xffffffffL; + +int s3c_irqext_wake(unsigned int irqno, unsigned int state) +{ + unsigned long bit = 1L << IRQ_EINT_BIT(irqno); + + if (!(s3c_irqwake_eintallow & bit)) + return -ENOENT; + + printk(KERN_INFO "wake %s for irq %d\n", + state ? "enabled" : "disabled", irqno); + + if (!state) + s3c_irqwake_eintmask |= bit; + else + s3c_irqwake_eintmask &= ~bit; + + return 0; +} + +/* helper functions to save and restore register state */ + +/** + * s3c_pm_do_save() - save a set of registers for restoration on resume. + * @ptr: Pointer to an array of registers. + * @count: Size of the ptr array. + * + * Run through the list of registers given, saving their contents in the + * array for later restoration when we wakeup. + */ +void s3c_pm_do_save(struct sleep_save *ptr, int count) +{ + for (; count > 0; count--, ptr++) { + ptr->val = __raw_readl(ptr->reg); + S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val); + } +} + +/** + * s3c_pm_do_restore() - restore register values from the save list. + * @ptr: Pointer to an array of registers. + * @count: Size of the ptr array. + * + * Restore the register values saved from s3c_pm_do_save(). + * + * Note, we do not use S3C_PMDBG() in here, as the system may not have + * restore the UARTs state yet +*/ + +void s3c_pm_do_restore(struct sleep_save *ptr, int count) +{ + for (; count > 0; count--, ptr++) { + printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n", + ptr->reg, ptr->val, __raw_readl(ptr->reg)); + + __raw_writel(ptr->val, ptr->reg); + } +} + +/** + * s3c_pm_do_restore_core() - early restore register values from save list. + * + * This is simialr to s3c_pm_do_restore() except we try and minimise the + * side effects of the function in case registers that hardware might need + * to work has been restored. + * + * WARNING: Do not put any debug in here that may effect memory or use + * peripherals, as things may be changing! +*/ + +void s3c_pm_do_restore_core(struct sleep_save *ptr, int count) +{ + for (; count > 0; count--, ptr++) + __raw_writel(ptr->val, ptr->reg); +} + +/* s3c2410_pm_show_resume_irqs + * + * print any IRQs asserted at resume time (ie, we woke from) +*/ +static void s3c_pm_show_resume_irqs(int start, unsigned long which, + unsigned long mask) +{ + int i; + + which &= ~mask; + + for (i = 0; i <= 31; i++) { + if (which & (1L<<i)) { + S3C_PMDBG("IRQ %d asserted at resume\n", start+i); + } + } +} + + +void (*pm_cpu_prep)(void); +void (*pm_cpu_sleep)(void); + +#define any_allowed(mask, allow) (((mask) & (allow)) != (allow)) + +/* s3c_pm_enter + * + * central control for sleep/resume process +*/ + +static int s3c_pm_enter(suspend_state_t state) +{ + unsigned long regs_save[16]; + + /* ensure the debug is initialised (if enabled) */ + + s3c_pm_debug_init(); + + S3C_PMDBG("%s(%d)\n", __func__, state); + + if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) { + printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__); + return -EINVAL; + } + + /* check if we have anything to wake-up with... bad things seem + * to happen if you suspend with no wakeup (system will often + * require a full power-cycle) + */ + + if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) && + !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) { + printk(KERN_ERR "%s: No wake-up sources!\n", __func__); + printk(KERN_ERR "%s: Aborting sleep\n", __func__); + return -EINVAL; + } + + /* prepare check area if configured */ + + s3c_pm_check_prepare(); + + /* store the physical address of the register recovery block */ + + s3c_sleep_save_phys = virt_to_phys(regs_save); + + S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys); + + /* save all necessary core registers not covered by the drivers */ + + s3c_pm_save_gpios(); + s3c_pm_save_uarts(); + s3c_pm_save_core(); + + /* set the irq configuration for wake */ + + s3c_pm_configure_extint(); + + S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n", + s3c_irqwake_intmask, s3c_irqwake_eintmask); + + s3c_pm_arch_prepare_irqs(); + + /* call cpu specific preparation */ + + pm_cpu_prep(); + + /* flush cache back to ram */ + + flush_cache_all(); + + s3c_pm_check_store(); + + /* send the cpu to sleep... */ + + s3c_pm_arch_stop_clocks(); + + /* s3c2410_cpu_save will also act as our return point from when + * we resume as it saves its own register state, so use the return + * code to differentiate return from save and return from sleep */ + + if (s3c_cpu_save(regs_save) == 0) { + flush_cache_all(); + pm_cpu_sleep(); + } + + /* restore the cpu state using the kernel's cpu init code. */ + + cpu_init(); + + /* restore the system state */ + + s3c_pm_restore_core(); + s3c_pm_restore_uarts(); + s3c_pm_restore_gpios(); + + s3c_pm_debug_init(); + + /* check what irq (if any) restored the system */ + + s3c_pm_arch_show_resume_irqs(); + + S3C_PMDBG("%s: post sleep, preparing to return\n", __func__); + + /* LEDs should now be 1110 */ + s3c_pm_debug_smdkled(1 << 1, 0); + + s3c_pm_check_restore(); + + /* ok, let's return from sleep */ + + S3C_PMDBG("S3C PM Resume (post-restore)\n"); + return 0; +} + +static int s3c_pm_begin(suspend_state_t state) +{ + int ret = 0; + +#ifdef CONFIG_REGULATOR + ret = regulator_suspend_prepare(state); +#endif + return ret; +} + +static struct platform_suspend_ops s3c_pm_ops = { + .enter = s3c_pm_enter, + .valid = suspend_valid_only_mem, + .begin = s3c_pm_begin, +}; + +/* s3c_pm_init + * + * Attach the power management functions. This should be called + * from the board specific initialisation if the board supports + * it. +*/ + +int __init s3c_pm_init(void) +{ + printk("S3C Power Management, Copyright 2004 Simtec Electronics\n"); + + suspend_set_ops(&s3c_pm_ops); + return 0; +} diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index 2fe793c9235..72bc07dec70 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o obj-$(CONFIG_CPU_S3C244X) += s3c244x-clock.o obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o obj-$(CONFIG_PM) += pm.o +obj-$(CONFIG_PM) += irq-pm.o obj-$(CONFIG_PM) += sleep.o obj-$(CONFIG_HAVE_PWM) += pwm.o obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c index 3d4837021ac..1a8347cec20 100644 --- a/arch/arm/plat-s3c24xx/common-smdk.c +++ b/arch/arm/plat-s3c24xx/common-smdk.c @@ -201,5 +201,5 @@ void __init smdk_machine_init(void) platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs)); - s3c2410_pm_init(); + s3c_pm_init(); } diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c index f95c6c9d9f1..a9cf22d32b9 100644 --- a/arch/arm/plat-s3c24xx/gpiolib.c +++ b/arch/arm/plat-s3c24xx/gpiolib.c @@ -22,6 +22,7 @@ #include <plat/gpio-core.h> #include <mach/hardware.h> #include <asm/irq.h> +#include <plat/pm.h> #include <mach/regs-gpio.h> @@ -62,6 +63,7 @@ static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip, struct s3c_gpio_chip s3c24xx_gpios[] = { [0] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPA0), + .pm = __gpio_pm(&s3c_gpio_pm_1bit), .chip = { .base = S3C2410_GPA0, .owner = THIS_MODULE, @@ -73,6 +75,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = { }, [1] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPB0), + .pm = __gpio_pm(&s3c_gpio_pm_2bit), .chip = { .base = S3C2410_GPB0, .owner = THIS_MODULE, @@ -82,6 +85,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = { }, [2] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPC0), + .pm = __gpio_pm(&s3c_gpio_pm_2bit), .chip = { .base = S3C2410_GPC0, .owner = THIS_MODULE, @@ -91,6 +95,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = { }, [3] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPD0), + .pm = __gpio_pm(&s3c_gpio_pm_2bit), .chip = { .base = S3C2410_GPD0, .owner = THIS_MODULE, @@ -100,6 +105,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = { }, [4] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPE0), + .pm = __gpio_pm(&s3c_gpio_pm_2bit), .chip = { .base = S3C2410_GPE0, .label = "GPIOE", @@ -109,6 +115,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = { }, [5] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPF0), + .pm = __gpio_pm(&s3c_gpio_pm_2bit), .chip = { .base = S3C2410_GPF0, .owner = THIS_MODULE, @@ -118,6 +125,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = { }, [6] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPG0), + .pm = __gpio_pm(&s3c_gpio_pm_2bit), .chip = { .base = S3C2410_GPG0, .owner = THIS_MODULE, diff --git a/arch/arm/plat-s3c24xx/include/plat/irq.h b/arch/arm/plat-s3c24xx/include/plat/irq.h index bf15e1c5d90..48fb56456b5 100644 --- a/arch/arm/plat-s3c24xx/include/plat/irq.h +++ b/arch/arm/plat-s3c24xx/include/plat/irq.h @@ -10,6 +10,12 @@ * published by the Free Software Foundation. */ +#include <linux/io.h> + +#include <mach/hardware.h> +#include <mach/regs-irq.h> +#include <mach/regs-gpio.h> + #define irqdbf(x...) #define irqdbf2(x...) diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h index fef8ea8b8e1..eed8f78e759 100644 --- a/arch/arm/plat-s3c24xx/include/plat/map.h +++ b/arch/arm/plat-s3c24xx/include/plat/map.h @@ -31,6 +31,8 @@ #define S3C24XX_SZ_UART SZ_1M #define S3C_UART_OFFSET (0x4000) +#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET))) + /* Timers */ #define S3C24XX_VA_TIMER S3C_VA_TIMER #define S3C2410_PA_TIMER (0x51000000) diff --git a/arch/arm/plat-s3c24xx/include/plat/pm-core.h b/arch/arm/plat-s3c24xx/include/plat/pm-core.h new file mode 100644 index 00000000000..fb45dd9adca --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/pm-core.h @@ -0,0 +1,64 @@ +/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C24xx - PM core support for arch/arm/plat-s3c/pm.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +static inline void s3c_pm_debug_init_uart(void) +{ + unsigned long tmp = __raw_readl(S3C2410_CLKCON); + + /* re-start uart clocks */ + tmp |= S3C2410_CLKCON_UART0; + tmp |= S3C2410_CLKCON_UART1; + tmp |= S3C2410_CLKCON_UART2; + + __raw_writel(tmp, S3C2410_CLKCON); + udelay(10); +} + +static inline void s3c_pm_arch_prepare_irqs(void) +{ + __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK); + __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK); + + /* ack any outstanding external interrupts before we go to sleep */ + + __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); + __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); + __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); + +} + +static inline void s3c_pm_arch_stop_clocks(void) +{ + __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */ +} + +static void s3c_pm_show_resume_irqs(int start, unsigned long which, + unsigned long mask); + +static inline void s3c_pm_arch_show_resume_irqs(void) +{ + S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n", + __raw_readl(S3C2410_SRCPND), + __raw_readl(S3C2410_EINTPEND)); + + s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND), + s3c_irqwake_intmask); + + s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND), + s3c_irqwake_eintmask); +} + +static inline void s3c_pm_arch_update_uart(void __iomem *regs, + struct pm_uart_save *save) +{ +} diff --git a/arch/arm/plat-s3c24xx/irq-pm.c b/arch/arm/plat-s3c24xx/irq-pm.c new file mode 100644 index 00000000000..b7acf1a8ecd --- /dev/null +++ b/arch/arm/plat-s3c24xx/irq-pm.c @@ -0,0 +1,95 @@ +/* linux/arch/arm/plat-s3c24xx/irq-om.c + * + * Copyright (c) 2003,2004 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C24XX - IRQ PM code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/sysdev.h> + +#include <plat/cpu.h> +#include <plat/pm.h> +#include <plat/irq.h> + +/* state for IRQs over sleep */ + +/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources + * + * set bit to 1 in allow bitfield to enable the wakeup settings on it +*/ + +unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL; +unsigned long s3c_irqwake_eintallow = 0x0000fff0L; + +int s3c_irq_wake(unsigned int irqno, unsigned int state) +{ + unsigned long irqbit = 1 << (irqno - IRQ_EINT0); + + if (!(s3c_irqwake_intallow & irqbit)) + return -ENOENT; + + printk(KERN_INFO "wake %s for irq %d\n", + state ? "enabled" : "disabled", irqno); + + if (!state) + s3c_irqwake_intmask |= irqbit; + else + s3c_irqwake_intmask &= ~irqbit; + + return 0; +} + +static struct sleep_save irq_save[] = { + SAVE_ITEM(S3C2410_INTMSK), + SAVE_ITEM(S3C2410_INTSUBMSK), +}; + +/* the extint values move between the s3c2410/s3c2440 and the s3c2412 + * so we use an array to hold them, and to calculate the address of + * the register at run-time +*/ + +static unsigned long save_extint[3]; +static unsigned long save_eintflt[4]; +static unsigned long save_eintmask; + +int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(save_extint); i++) + save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4)); + + for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) + save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4)); + + s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); + save_eintmask = __raw_readl(S3C24XX_EINTMASK); + + return 0; +} + +int s3c24xx_irq_resume(struct sys_device *dev) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(save_extint); i++) + __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4)); + + for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) + __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4)); + + s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); + __raw_writel(save_eintmask, S3C24XX_EINTMASK); + + return 0; +} diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c index f31770cf71a..d696bbd1c9e 100644 --- a/arch/arm/plat-s3c24xx/irq.c +++ b/arch/arm/plat-s3c24xx/irq.c @@ -1,6 +1,6 @@ /* linux/arch/arm/plat-s3c24xx/irq.c * - * Copyright (c) 2003,2004 Simtec Electronics + * Copyright (c) 2003,2004 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> * * This program is free software; you can redistribute it and/or modify @@ -16,38 +16,6 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * Changelog: - * - * 22-Jul-2004 Ben Dooks <ben@simtec.co.uk> - * Fixed compile warnings - * - * 22-Jul-2004 Roc Wu <cooloney@yahoo.com.cn> - * Fixed s3c_extirq_type - * - * 21-Jul-2004 Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org> - * Addition of ADC/TC demux - * - * 04-Oct-2004 Klaus Fetscher <k.fetscher@fetron.de> - * Fix for set_irq_type() on low EINT numbers - * - * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk> - * Tidy up KF's patch and sort out new release - * - * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk> - * Add support for power management controls - * - * 04-Nov-2004 Ben Dooks - * Fix standard IRQ wake for EINT0..4 and RTC - * - * 22-Feb-2005 Ben Dooks - * Fixed edge-triggering on ADC IRQ - * - * 28-Jun-2005 Ben Dooks - * Mark IRQ_LCD valid - * - * 25-Jul-2005 Ben Dooks - * Split the S3C2440 IRQ code to separate file */ #include <linux/init.h> @@ -55,81 +23,16 @@ #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/sysdev.h> -#include <linux/io.h> -#include <mach/hardware.h> #include <asm/irq.h> - #include <asm/mach/irq.h> #include <plat/regs-irqtype.h> -#include <mach/regs-irq.h> -#include <mach/regs-gpio.h> #include <plat/cpu.h> #include <plat/pm.h> #include <plat/irq.h> -/* wakeup irq control */ - -#ifdef CONFIG_PM - -/* state for IRQs over sleep */ - -/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources - * - * set bit to 1 in allow bitfield to enable the wakeup settings on it -*/ - -unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL; -unsigned long s3c_irqwake_intmask = 0xffffffffL; -unsigned long s3c_irqwake_eintallow = 0x0000fff0L; -unsigned long s3c_irqwake_eintmask = 0xffffffffL; - -int -s3c_irq_wake(unsigned int irqno, unsigned int state) -{ - unsigned long irqbit = 1 << (irqno - IRQ_EINT0); - - if (!(s3c_irqwake_intallow & irqbit)) - return -ENOENT; - - printk(KERN_INFO "wake %s for irq %d\n", - state ? "enabled" : "disabled", irqno); - - if (!state) - s3c_irqwake_intmask |= irqbit; - else - s3c_irqwake_intmask &= ~irqbit; - - return 0; -} - -static int -s3c_irqext_wake(unsigned int irqno, unsigned int state) -{ - unsigned long bit = 1L << (irqno - EXTINT_OFF); - - if (!(s3c_irqwake_eintallow & bit)) - return -ENOENT; - - printk(KERN_INFO "wake %s for irq %d\n", - state ? "enabled" : "disabled", irqno); - - if (!state) - s3c_irqwake_eintmask |= bit; - else - s3c_irqwake_eintmask &= ~bit; - - return 0; -} - -#else -#define s3c_irqext_wake NULL -#define s3c_irq_wake NULL -#endif - - static void s3c_irq_mask(unsigned int irqno) { @@ -618,59 +521,6 @@ s3c_irq_demux_extint4t7(unsigned int irq, } } -#ifdef CONFIG_PM - -static struct sleep_save irq_save[] = { - SAVE_ITEM(S3C2410_INTMSK), - SAVE_ITEM(S3C2410_INTSUBMSK), -}; - -/* the extint values move between the s3c2410/s3c2440 and the s3c2412 - * so we use an array to hold them, and to calculate the address of - * the register at run-time -*/ - -static unsigned long save_extint[3]; -static unsigned long save_eintflt[4]; -static unsigned long save_eintmask; - -int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(save_extint); i++) - save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4)); - - for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) - save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4)); - - s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); - save_eintmask = __raw_readl(S3C24XX_EINTMASK); - - return 0; -} - -int s3c24xx_irq_resume(struct sys_device *dev) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(save_extint); i++) - __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4)); - - for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) - __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4)); - - s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); - __raw_writel(save_eintmask, S3C24XX_EINTMASK); - - return 0; -} - -#else -#define s3c24xx_irq_suspend NULL -#define s3c24xx_irq_resume NULL -#endif - /* s3c24xx_init_irq * * Initialise S3C2410 IRQ system diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/plat-s3c24xx/pm-simtec.c index 21dfa74773d..da0d3217d3e 100644 --- a/arch/arm/plat-s3c24xx/pm-simtec.c +++ b/arch/arm/plat-s3c24xx/pm-simtec.c @@ -61,7 +61,7 @@ static __init int pm_simtec_init(void) __raw_writel(gstatus4, S3C2410_GSTATUS4); - return s3c2410_pm_init(); + return s3c_pm_init(); } arch_initcall(pm_simtec_init); diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c index 325631e2aed..57062bc4247 100644 --- a/arch/arm/plat-s3c24xx/pm.c +++ b/arch/arm/plat-s3c24xx/pm.c @@ -31,16 +31,10 @@ #include <linux/errno.h> #include <linux/time.h> #include <linux/interrupt.h> -#include <linux/crc32.h> -#include <linux/ioport.h> -#include <linux/delay.h> #include <linux/serial_core.h> #include <linux/io.h> #include <linux/regulator/machine.h> -#include <asm/cacheflush.h> -#include <mach/hardware.h> - #include <plat/regs-serial.h> #include <mach/regs-clock.h> #include <mach/regs-gpio.h> @@ -51,10 +45,6 @@ #include <plat/pm.h> -/* for external use */ - -unsigned long s3c_pm_flags; - #define PFX "s3c24xx-pm: " static struct sleep_save core_save[] = { @@ -86,364 +76,17 @@ static struct sleep_save core_save[] = { SAVE_ITEM(S3C2410_CLKSLOW), }; -static struct gpio_sleep { - void __iomem *base; - unsigned int gpcon; - unsigned int gpdat; - unsigned int gpup; -} gpio_save[] = { - [0] = { - .base = S3C2410_GPACON, - }, - [1] = { - .base = S3C2410_GPBCON, - }, - [2] = { - .base = S3C2410_GPCCON, - }, - [3] = { - .base = S3C2410_GPDCON, - }, - [4] = { - .base = S3C2410_GPECON, - }, - [5] = { - .base = S3C2410_GPFCON, - }, - [6] = { - .base = S3C2410_GPGCON, - }, - [7] = { - .base = S3C2410_GPHCON, - }, -}; - static struct sleep_save misc_save[] = { SAVE_ITEM(S3C2410_DCLKCON), }; -#ifdef CONFIG_S3C2410_PM_DEBUG - -#define SAVE_UART(va) \ - SAVE_ITEM((va) + S3C2410_ULCON), \ - SAVE_ITEM((va) + S3C2410_UCON), \ - SAVE_ITEM((va) + S3C2410_UFCON), \ - SAVE_ITEM((va) + S3C2410_UMCON), \ - SAVE_ITEM((va) + S3C2410_UBRDIV) - -static struct sleep_save uart_save[] = { - SAVE_UART(S3C24XX_VA_UART0), - SAVE_UART(S3C24XX_VA_UART1), -#ifndef CONFIG_CPU_S3C2400 - SAVE_UART(S3C24XX_VA_UART2), -#endif -}; - -/* debug - * - * we send the debug to printascii() to allow it to be seen if the - * system never wakes up from the sleep -*/ - -extern void printascii(const char *); - -void pm_dbg(const char *fmt, ...) -{ - va_list va; - char buff[256]; - - va_start(va, fmt); - vsprintf(buff, fmt, va); - va_end(va); - - printascii(buff); -} - -static void s3c2410_pm_debug_init(void) -{ - unsigned long tmp = __raw_readl(S3C2410_CLKCON); - - /* re-start uart clocks */ - tmp |= S3C2410_CLKCON_UART0; - tmp |= S3C2410_CLKCON_UART1; - tmp |= S3C2410_CLKCON_UART2; - - __raw_writel(tmp, S3C2410_CLKCON); - udelay(10); -} - -#define DBG(fmt...) pm_dbg(fmt) -#else -#define DBG(fmt...) printk(KERN_DEBUG fmt) - -#define s3c2410_pm_debug_init() do { } while(0) - -static struct sleep_save uart_save[] = {}; -#endif - -#if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0 - -/* suspend checking code... - * - * this next area does a set of crc checks over all the installed - * memory, so the system can verify if the resume was ok. - * - * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC, - * increasing it will mean that the area corrupted will be less easy to spot, - * and reducing the size will cause the CRC save area to grow -*/ - -#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024) - -static u32 crc_size; /* size needed for the crc block */ -static u32 *crcs; /* allocated over suspend/resume */ - -typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg); - -/* s3c2410_pm_run_res - * - * go thorugh the given resource list, and look for system ram -*/ - -static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg) -{ - while (ptr != NULL) { - if (ptr->child != NULL) - s3c2410_pm_run_res(ptr->child, fn, arg); - - if ((ptr->flags & IORESOURCE_MEM) && - strcmp(ptr->name, "System RAM") == 0) { - DBG("Found system RAM at %08lx..%08lx\n", - ptr->start, ptr->end); - arg = (fn)(ptr, arg); - } - - ptr = ptr->sibling; - } -} - -static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg) -{ - s3c2410_pm_run_res(&iomem_resource, fn, arg); -} - -static u32 *s3c2410_pm_countram(struct resource *res, u32 *val) -{ - u32 size = (u32)(res->end - res->start)+1; - - size += CHECK_CHUNKSIZE-1; - size /= CHECK_CHUNKSIZE; - - DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size); - - *val += size * sizeof(u32); - return val; -} - -/* s3c2410_pm_prepare_check - * - * prepare the necessary information for creating the CRCs. This - * must be done before the final save, as it will require memory - * allocating, and thus touching bits of the kernel we do not - * know about. -*/ - -static void s3c2410_pm_check_prepare(void) -{ - crc_size = 0; - - s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size); - - DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size); - - crcs = kmalloc(crc_size+4, GFP_KERNEL); - if (crcs == NULL) - printk(KERN_ERR "Cannot allocated CRC save area\n"); -} - -static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val) -{ - unsigned long addr, left; - - for (addr = res->start; addr < res->end; - addr += CHECK_CHUNKSIZE) { - left = res->end - addr; - - if (left > CHECK_CHUNKSIZE) - left = CHECK_CHUNKSIZE; - - *val = crc32_le(~0, phys_to_virt(addr), left); - val++; - } - - return val; -} - -/* s3c2410_pm_check_store - * - * compute the CRC values for the memory blocks before the final - * sleep. -*/ - -static void s3c2410_pm_check_store(void) -{ - if (crcs != NULL) - s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs); -} - -/* in_region - * - * return TRUE if the area defined by ptr..ptr+size contatins the - * what..what+whatsz -*/ - -static inline int in_region(void *ptr, int size, void *what, size_t whatsz) -{ - if ((what+whatsz) < ptr) - return 0; - - if (what > (ptr+size)) - return 0; - - return 1; -} - -static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val) -{ - void *save_at = phys_to_virt(s3c2410_sleep_save_phys); - unsigned long addr; - unsigned long left; - void *ptr; - u32 calc; - - for (addr = res->start; addr < res->end; - addr += CHECK_CHUNKSIZE) { - left = res->end - addr; - - if (left > CHECK_CHUNKSIZE) - left = CHECK_CHUNKSIZE; - - ptr = phys_to_virt(addr); - - if (in_region(ptr, left, crcs, crc_size)) { - DBG("skipping %08lx, has crc block in\n", addr); - goto skip_check; - } - - if (in_region(ptr, left, save_at, 32*4 )) { - DBG("skipping %08lx, has save block in\n", addr); - goto skip_check; - } - - /* calculate and check the checksum */ - - calc = crc32_le(~0, ptr, left); - if (calc != *val) { - printk(KERN_ERR PFX "Restore CRC error at " - "%08lx (%08x vs %08x)\n", addr, calc, *val); - - DBG("Restore CRC error at %08lx (%08x vs %08x)\n", - addr, calc, *val); - } - - skip_check: - val++; - } - - return val; -} - -/* s3c2410_pm_check_restore - * - * check the CRCs after the restore event and free the memory used - * to hold them -*/ - -static void s3c2410_pm_check_restore(void) -{ - if (crcs != NULL) { - s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs); - kfree(crcs); - crcs = NULL; - } -} - -#else - -#define s3c2410_pm_check_prepare() do { } while(0) -#define s3c2410_pm_check_restore() do { } while(0) -#define s3c2410_pm_check_store() do { } while(0) -#endif - -/* helper functions to save and restore register state */ - -void s3c2410_pm_do_save(struct sleep_save *ptr, int count) -{ - for (; count > 0; count--, ptr++) { - ptr->val = __raw_readl(ptr->reg); - DBG("saved %p value %08lx\n", ptr->reg, ptr->val); - } -} - -/* s3c2410_pm_do_restore - * - * restore the system from the given list of saved registers - * - * Note, we do not use DBG() in here, as the system may not have - * restore the UARTs state yet -*/ - -void s3c2410_pm_do_restore(struct sleep_save *ptr, int count) -{ - for (; count > 0; count--, ptr++) { - printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n", - ptr->reg, ptr->val, __raw_readl(ptr->reg)); - - __raw_writel(ptr->val, ptr->reg); - } -} - -/* s3c2410_pm_do_restore_core - * - * similar to s3c2410_pm_do_restore_core - * - * WARNING: Do not put any debug in here that may effect memory or use - * peripherals, as things may be changing! -*/ - -static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count) -{ - for (; count > 0; count--, ptr++) { - __raw_writel(ptr->val, ptr->reg); - } -} - -/* s3c2410_pm_show_resume_irqs - * - * print any IRQs asserted at resume time (ie, we woke from) -*/ - -static void s3c2410_pm_show_resume_irqs(int start, unsigned long which, - unsigned long mask) -{ - int i; - - which &= ~mask; - - for (i = 0; i <= 31; i++) { - if ((which) & (1L<<i)) { - DBG("IRQ %d asserted at resume\n", start+i); - } - } -} - -/* s3c2410_pm_check_resume_pin +/* s3c_pm_check_resume_pin * * check to see if the pin is configured correctly for sleep mode, and * make any necessary adjustments if it is not */ -static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) +static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) { unsigned long irqstate; unsigned long pinstate; @@ -458,21 +101,21 @@ static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) if (!irqstate) { if (pinstate == S3C2410_GPIO_IRQ) - DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin); + S3C_PMDBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin); } else { if (pinstate == S3C2410_GPIO_IRQ) { - DBG("Disabling IRQ %d (pin %d)\n", irq, pin); + S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin); s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT); } } } -/* s3c2410_pm_configure_extint +/* s3c_pm_configure_extint * * configure all external interrupt pins */ -static void s3c2410_pm_configure_extint(void) +void s3c_pm_configure_extint(void) { int pin; @@ -482,320 +125,28 @@ static void s3c2410_pm_configure_extint(void) */ for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) { - s3c2410_pm_check_resume_pin(pin, pin - S3C2410_GPF0); + s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF0); } for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) { - s3c2410_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8); + s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8); } } -/* offsets for CON/DAT/UP registers */ - -#define OFFS_CON (S3C2410_GPACON - S3C2410_GPACON) -#define OFFS_DAT (S3C2410_GPADAT - S3C2410_GPACON) -#define OFFS_UP (S3C2410_GPBUP - S3C2410_GPBCON) - -/* s3c2410_pm_save_gpios() - * - * Save the state of the GPIOs - */ - -static void s3c2410_pm_save_gpios(void) -{ - struct gpio_sleep *gps = gpio_save; - unsigned int gpio; - - for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) { - void __iomem *base = gps->base; - - gps->gpcon = __raw_readl(base + OFFS_CON); - gps->gpdat = __raw_readl(base + OFFS_DAT); - - if (gpio > 0) - gps->gpup = __raw_readl(base + OFFS_UP); - - } -} - -/* Test whether the given masked+shifted bits of an GPIO configuration - * are one of the SFN (special function) modes. */ - -static inline int is_sfn(unsigned long con) -{ - return (con == 2 || con == 3); -} - -/* Test if the given masked+shifted GPIO configuration is an input */ - -static inline int is_in(unsigned long con) -{ - return con == 0; -} - -/* Test if the given masked+shifted GPIO configuration is an output */ - -static inline int is_out(unsigned long con) +void s3c_pm_restore_core(void) { - return con == 1; + s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); + s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save)); } -/* s3c2410_pm_restore_gpio() - * - * Restore one of the GPIO banks that was saved during suspend. This is - * not as simple as once thought, due to the possibility of glitches - * from the order that the CON and DAT registers are set in. - * - * The three states the pin can be are {IN,OUT,SFN} which gives us 9 - * combinations of changes to check. Three of these, if the pin stays - * in the same configuration can be discounted. This leaves us with - * the following: - * - * { IN => OUT } Change DAT first - * { IN => SFN } Change CON first - * { OUT => SFN } Change CON first, so new data will not glitch - * { OUT => IN } Change CON first, so new data will not glitch - * { SFN => IN } Change CON first - * { SFN => OUT } Change DAT first, so new data will not glitch [1] - * - * We do not currently deal with the UP registers as these control - * weak resistors, so a small delay in change should not need to bring - * these into the calculations. - * - * [1] this assumes that writing to a pin DAT whilst in SFN will set the - * state for when it is next output. - */ - -static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps) +void s3c_pm_save_core(void) { - void __iomem *base = gps->base; - unsigned long gps_gpcon = gps->gpcon; - unsigned long gps_gpdat = gps->gpdat; - unsigned long old_gpcon; - unsigned long old_gpdat; - unsigned long old_gpup = 0x0; - unsigned long gpcon; - int nr; - - old_gpcon = __raw_readl(base + OFFS_CON); - old_gpdat = __raw_readl(base + OFFS_DAT); - - if (base == S3C2410_GPACON) { - /* GPACON only has one bit per control / data and no PULLUPs. - * GPACON[x] = 0 => Output, 1 => SFN */ - - /* first set all SFN bits to SFN */ - - gpcon = old_gpcon | gps->gpcon; - __raw_writel(gpcon, base + OFFS_CON); - - /* now set all the other bits */ - - __raw_writel(gps_gpdat, base + OFFS_DAT); - __raw_writel(gps_gpcon, base + OFFS_CON); - } else { - unsigned long old, new, mask; - unsigned long change_mask = 0x0; - - old_gpup = __raw_readl(base + OFFS_UP); - - /* Create a change_mask of all the items that need to have - * their CON value changed before their DAT value, so that - * we minimise the work between the two settings. - */ - - for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) { - old = (old_gpcon & mask) >> nr; - new = (gps_gpcon & mask) >> nr; - - /* If there is no change, then skip */ - - if (old == new) - continue; - - /* If both are special function, then skip */ - - if (is_sfn(old) && is_sfn(new)) - continue; - - /* Change is IN => OUT, do not change now */ - - if (is_in(old) && is_out(new)) - continue; - - /* Change is SFN => OUT, do not change now */ - - if (is_sfn(old) && is_out(new)) - continue; - - /* We should now be at the case of IN=>SFN, - * OUT=>SFN, OUT=>IN, SFN=>IN. */ - - change_mask |= mask; - } - - /* Write the new CON settings */ - - gpcon = old_gpcon & ~change_mask; - gpcon |= gps_gpcon & change_mask; - - __raw_writel(gpcon, base + OFFS_CON); - - /* Now change any items that require DAT,CON */ - - __raw_writel(gps_gpdat, base + OFFS_DAT); - __raw_writel(gps_gpcon, base + OFFS_CON); - __raw_writel(gps->gpup, base + OFFS_UP); - } - - DBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n", - index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); -} - - -/** s3c2410_pm_restore_gpios() - * - * Restore the state of the GPIOs - */ - -static void s3c2410_pm_restore_gpios(void) -{ - struct gpio_sleep *gps = gpio_save; - int gpio; - - for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) { - s3c2410_pm_restore_gpio(gpio, gps); - } -} - -void (*pm_cpu_prep)(void); -void (*pm_cpu_sleep)(void); - -#define any_allowed(mask, allow) (((mask) & (allow)) != (allow)) - -/* s3c2410_pm_enter - * - * central control for sleep/resume process -*/ - -static int s3c2410_pm_enter(suspend_state_t state) -{ - unsigned long regs_save[16]; - - /* ensure the debug is initialised (if enabled) */ - - s3c2410_pm_debug_init(); - - DBG("s3c2410_pm_enter(%d)\n", state); - - if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) { - printk(KERN_ERR PFX "error: no cpu sleep functions set\n"); - return -EINVAL; - } - - /* check if we have anything to wake-up with... bad things seem - * to happen if you suspend with no wakeup (system will often - * require a full power-cycle) - */ - - if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) && - !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) { - printk(KERN_ERR PFX "No sources enabled for wake-up!\n"); - printk(KERN_ERR PFX "Aborting sleep\n"); - return -EINVAL; - } - - /* prepare check area if configured */ - - s3c2410_pm_check_prepare(); - - /* store the physical address of the register recovery block */ - - s3c2410_sleep_save_phys = virt_to_phys(regs_save); - - DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys); - - /* save all necessary core registers not covered by the drivers */ - - s3c2410_pm_save_gpios(); - s3c2410_pm_do_save(misc_save, ARRAY_SIZE(misc_save)); - s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save)); - s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save)); - - /* set the irq configuration for wake */ - - s3c2410_pm_configure_extint(); - - DBG("sleep: irq wakeup masks: %08lx,%08lx\n", - s3c_irqwake_intmask, s3c_irqwake_eintmask); - - __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK); - __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK); - - /* ack any outstanding external interrupts before we go to sleep */ - - __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); - __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); - __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); - - /* call cpu specific preparation */ - - pm_cpu_prep(); - - /* flush cache back to ram */ - - flush_cache_all(); - - s3c2410_pm_check_store(); - - /* send the cpu to sleep... */ - - __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */ - - /* s3c2410_cpu_save will also act as our return point from when - * we resume as it saves its own register state, so use the return - * code to differentiate return from save and return from sleep */ - - if (s3c2410_cpu_save(regs_save) == 0) { - flush_cache_all(); - pm_cpu_sleep(); - } - - /* restore the cpu state */ - - cpu_init(); - - /* restore the system state */ - - s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); - s3c2410_pm_do_restore(misc_save, ARRAY_SIZE(misc_save)); - s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save)); - s3c2410_pm_restore_gpios(); - - s3c2410_pm_debug_init(); - - /* check what irq (if any) restored the system */ - - DBG("post sleep: IRQs 0x%08x, 0x%08x\n", - __raw_readl(S3C2410_SRCPND), - __raw_readl(S3C2410_EINTPEND)); - - s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND), - s3c_irqwake_intmask); - - s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND), - s3c_irqwake_eintmask); - - DBG("post sleep, preparing to return\n"); - - s3c2410_pm_check_restore(); - - /* ok, let's return from sleep */ - - DBG("S3C2410 PM Resume (post-restore)\n"); - return 0; + s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save)); + s3c_pm_do_save(core_save, ARRAY_SIZE(core_save)); } +<<<<<<< current +======= static int s3c2410_pm_begin(suspend_state_t state) { int ret = 0; @@ -826,3 +177,4 @@ int __init s3c2410_pm_init(void) suspend_set_ops(&s3c2410_pm_ops); return 0; } +>>>>>>> patched diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c index df78a15a80b..0731b239132 100644 --- a/arch/arm/plat-s3c24xx/s3c244x.c +++ b/arch/arm/plat-s3c24xx/s3c244x.c @@ -148,13 +148,13 @@ static struct sleep_save s3c244x_sleep[] = { static int s3c244x_suspend(struct sys_device *dev, pm_message_t state) { - s3c2410_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); + s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); return 0; } static int s3c244x_resume(struct sys_device *dev) { - s3c2410_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); + s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); return 0; } diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S index 76594b21280..ecb830be67d 100644 --- a/arch/arm/plat-s3c24xx/sleep.S +++ b/arch/arm/plat-s3c24xx/sleep.S @@ -41,7 +41,7 @@ .text - /* s3c2410_cpu_save + /* s3c_cpu_save * * save enough of the CPU state to allow us to re-start * pm.c code. as we store items like the sp/lr, we will @@ -59,7 +59,7 @@ * 1 => resumed from sleep */ -ENTRY(s3c2410_cpu_save) +ENTRY(s3c_cpu_save) stmfd sp!, { r4 - r12, lr } @@ store co-processor registers @@ -84,7 +84,7 @@ resume_with_mmu: .ltorg @@ the next bits sit in the .data segment, even though they - @@ happen to be code... the s3c2410_sleep_save_phys needs to be + @@ happen to be code... the s3c_sleep_save_phys needs to be @@ accessed by the resume code before it can restore the MMU. @@ This means that the variable has to be close enough for the @@ code to read it... since the .text segment needs to be RO, @@ -92,19 +92,19 @@ resume_with_mmu: .data - .global s3c2410_sleep_save_phys -s3c2410_sleep_save_phys: + .global s3c_sleep_save_phys +s3c_sleep_save_phys: .word 0 /* sleep magic, to allow the bootloader to check for an valid * image to resume to. Must be the first word before the - * s3c2410_cpu_resume entry. + * s3c_cpu_resume entry. */ .word 0x2bedf00d - /* s3c2410_cpu_resume + /* s3c_cpu_resume * * resume code entry for bootloader to call * @@ -113,7 +113,7 @@ s3c2410_sleep_save_phys: * must not write to the code segment (code is read-only) */ -ENTRY(s3c2410_cpu_resume) +ENTRY(s3c_cpu_resume) mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE msr cpsr_c, r0 @@ -145,7 +145,7 @@ ENTRY(s3c2410_cpu_resume) mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches - ldr r0, s3c2410_sleep_save_phys @ address of restore block + ldr r0, s3c_sleep_save_phys @ address of restore block ldmia r0, { r4 - r13 } mcr p15, 0, r4, c13, c0, 0 @ PID diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile index 2e6d79bf8f3..12ac7a50ab7 100644 --- a/arch/arm/plat-s3c64xx/Makefile +++ b/arch/arm/plat-s3c64xx/Makefile @@ -24,6 +24,12 @@ obj-y += gpiolib.o obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o +# PM support + +obj-$(CONFIG_PM) += pm.o +obj-$(CONFIG_PM) += sleep.o +obj-$(CONFIG_PM) += irq-pm.o + # Device setup obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c index 36182fcfaeb..278a04d5c57 100644 --- a/arch/arm/plat-s3c64xx/cpu.c +++ b/arch/arm/plat-s3c64xx/cpu.c @@ -16,6 +16,7 @@ #include <linux/module.h> #include <linux/interrupt.h> #include <linux/ioport.h> +#include <linux/sysdev.h> #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/delay.h> @@ -100,6 +101,16 @@ static struct map_desc s3c_iodesc[] __initdata = { }, }; + +struct sysdev_class s3c64xx_sysclass = { + .name = "s3c64xx-core", +}; + +static struct sys_device s3c64xx_sysdev = { + .cls = &s3c64xx_sysclass, +}; + + /* read cpu identification code */ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) @@ -113,3 +124,11 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) idcode = __raw_readl(S3C_VA_SYS + 0x118); s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); } + +static __init int s3c64xx_sysdev_init(void) +{ + sysdev_class_register(&s3c64xx_sysclass); + return sysdev_register(&s3c64xx_sysdev); +} + +core_initcall(s3c64xx_sysdev_init); diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c index cc62941d7b5..09bd681ae73 100644 --- a/arch/arm/plat-s3c64xx/gpiolib.c +++ b/arch/arm/plat-s3c64xx/gpiolib.c @@ -385,12 +385,19 @@ static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip) { chip->chip.direction_input = s3c64xx_gpiolib_4bit_input; chip->chip.direction_output = s3c64xx_gpiolib_4bit_output; + chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); } static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip) { chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input; chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output; + chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); +} + +static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip) +{ + chip->pm = __gpio_pm(&s3c_gpio_pm_2bit); } static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips, @@ -412,7 +419,8 @@ static __init int s3c64xx_gpiolib_init(void) s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2), s3c64xx_gpiolib_add_4bit2); - s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), NULL); + s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), + s3c64xx_gpiolib_add_2bit); return 0; } diff --git a/arch/arm/plat-s3c64xx/include/plat/irqs.h b/arch/arm/plat-s3c64xx/include/plat/irqs.h index 02e8dd4c97d..b85085295f0 100644 --- a/arch/arm/plat-s3c64xx/include/plat/irqs.h +++ b/arch/arm/plat-s3c64xx/include/plat/irqs.h @@ -157,6 +157,7 @@ #define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) #define IRQ_EINT(x) S3C_EINT(x) +#define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0)) /* Next the external interrupt groups. These are similar to the IRQ_EINT(x) * that they are sourced from the GPIO pins but with a different scheme for diff --git a/arch/arm/plat-s3c64xx/include/plat/pm-core.h b/arch/arm/plat-s3c64xx/include/plat/pm-core.h new file mode 100644 index 00000000000..8906c9fd443 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/pm-core.h @@ -0,0 +1,108 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/pm-core.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <plat/regs-gpio.h> + +static inline void s3c_pm_debug_init_uart(void) +{ + u32 tmp = __raw_readl(S3C_PCLK_GATE); + + /* As a note, since the S3C64XX UARTs generally have multiple + * clock sources, we simply enable PCLK at the momemnt and hope + * that the resume settings for the UART are suitable for the + * use with PCLK. + */ + + tmp |= S3C_CLKCON_PCLK_UART0; + tmp |= S3C_CLKCON_PCLK_UART1; + tmp |= S3C_CLKCON_PCLK_UART2; + tmp |= S3C_CLKCON_PCLK_UART3; + + __raw_writel(tmp, S3C_PCLK_GATE); + udelay(10); +} + +static inline void s3c_pm_arch_clear_vic(void __iomem *base) +{ + __raw_writel(~0, base + VIC_INT_ENABLE_CLEAR); + __raw_writel(~0, base + VIC_INT_SOFT_CLEAR); +} + +static inline void s3c_pm_arch_prepare_irqs(void) +{ + /* shutdown the VICs */ + s3c_pm_arch_clear_vic(S3C_VA_VIC0); + s3c_pm_arch_clear_vic(S3C_VA_VIC1); + + /* clear any pending EINT0 interrupts */ + __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND); +} + +static inline void s3c_pm_arch_stop_clocks(void) +{ +} + +static inline void s3c_pm_arch_show_resume_irqs(void) +{ +} + +/* make these defines, we currently do not have any need to change + * the IRQ wake controls depending on the CPU we are running on */ + +#define s3c_irqwake_eintallow ((1 << 28) - 1) +#define s3c_irqwake_intallow (0) + +static inline void s3c_pm_arch_update_uart(void __iomem *regs, + struct pm_uart_save *save) +{ + u32 ucon = __raw_readl(regs + S3C2410_UCON); + u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK; + u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK; + u32 new_ucon; + + /* S3C64XX UART blocks only support level interrupts, so ensure that + * when we restore unused UART blocks we force the level interrupt + * settigs. */ + save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL; + + /* We have a constraint on changing the clock type of the UART + * between UCLKx and PCLK, so ensure that when we restore UCON + * that the CLK field is correctly modified if the bootloader + * has changed anything. + */ + if (ucon_clk != save_clk) { + new_ucon = save->ucon; + new_ucon &= ~S3C6400_UCON_CLKMASK; + + /* check for illegal change of UCLK, and fixup */ + + if (ucon_clk == S3C6400_UCON_UCLK0 && + save_clk == S3C6400_UCON_PCLK2) + new_ucon |= S3C6400_UCON_PCLK; + + if (ucon_clk == S3C6400_UCON_UCLK1 && + save_clk == S3C6400_UCON_PCLK) + new_ucon |= S3C6400_UCON_PCLK2; + + if (ucon_clk == S3C6400_UCON_PCLK && + save_clk == S3C6400_UCON_PCLK2) + new_ucon |= S3C6400_UCON_PCLK; + + if (ucon_clk == S3C6400_UCON_PCLK2 && + save_clk == S3C6400_UCON_PCLK) + new_ucon |= S3C6400_UCON_PCLK2; + + save->ucon = new_ucon; + } +} diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h index b1082c16324..52836d41e33 100644 --- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h +++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h @@ -32,6 +32,7 @@ #define S3C_HCLK_GATE S3C_CLKREG(0x30) #define S3C_PCLK_GATE S3C_CLKREG(0x34) #define S3C_SCLK_GATE S3C_CLKREG(0x38) +#define S3C_MEM0_GATE S3C_CLKREG(0x3C) /* CLKDIV0 */ #define S3C6400_CLKDIV0_MFC_MASK (0xf << 28) diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h index 75b873d8280..17944803a32 100644 --- a/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h +++ b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h @@ -13,23 +13,90 @@ /* Base addresses for each of the banks */ -#define S3C64XX_GPA_BASE (S3C64XX_VA_GPIO + 0x0000) -#define S3C64XX_GPB_BASE (S3C64XX_VA_GPIO + 0x0020) -#define S3C64XX_GPC_BASE (S3C64XX_VA_GPIO + 0x0040) -#define S3C64XX_GPD_BASE (S3C64XX_VA_GPIO + 0x0060) -#define S3C64XX_GPE_BASE (S3C64XX_VA_GPIO + 0x0080) -#define S3C64XX_GPF_BASE (S3C64XX_VA_GPIO + 0x00A0) -#define S3C64XX_GPG_BASE (S3C64XX_VA_GPIO + 0x00C0) -#define S3C64XX_GPH_BASE (S3C64XX_VA_GPIO + 0x00E0) -#define S3C64XX_GPI_BASE (S3C64XX_VA_GPIO + 0x0100) -#define S3C64XX_GPJ_BASE (S3C64XX_VA_GPIO + 0x0120) -#define S3C64XX_GPK_BASE (S3C64XX_VA_GPIO + 0x0800) -#define S3C64XX_GPL_BASE (S3C64XX_VA_GPIO + 0x0810) -#define S3C64XX_GPM_BASE (S3C64XX_VA_GPIO + 0x0820) -#define S3C64XX_GPN_BASE (S3C64XX_VA_GPIO + 0x0830) -#define S3C64XX_GPO_BASE (S3C64XX_VA_GPIO + 0x0140) -#define S3C64XX_GPP_BASE (S3C64XX_VA_GPIO + 0x0160) -#define S3C64XX_GPQ_BASE (S3C64XX_VA_GPIO + 0x0180) +#define S3C64XX_GPIOREG(reg) (S3C64XX_VA_GPIO + (reg)) + +#define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000) +#define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020) +#define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040) +#define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060) +#define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080) +#define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0) +#define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0) +#define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0) +#define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100) +#define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120) +#define S3C64XX_GPK_BASE S3C64XX_GPIOREG(0x0800) +#define S3C64XX_GPL_BASE S3C64XX_GPIOREG(0x0810) +#define S3C64XX_GPM_BASE S3C64XX_GPIOREG(0x0820) +#define S3C64XX_GPN_BASE S3C64XX_GPIOREG(0x0830) +#define S3C64XX_GPO_BASE S3C64XX_GPIOREG(0x0140) +#define S3C64XX_GPP_BASE S3C64XX_GPIOREG(0x0160) +#define S3C64XX_GPQ_BASE S3C64XX_GPIOREG(0x0180) + +/* External interrupt registers */ + +#define S3C64XX_EINT12CON S3C64XX_GPIOREG(0x200) +#define S3C64XX_EINT34CON S3C64XX_GPIOREG(0x204) +#define S3C64XX_EINT56CON S3C64XX_GPIOREG(0x208) +#define S3C64XX_EINT78CON S3C64XX_GPIOREG(0x20C) +#define S3C64XX_EINT9CON S3C64XX_GPIOREG(0x210) + +#define S3C64XX_EINT12FLTCON S3C64XX_GPIOREG(0x220) +#define S3C64XX_EINT34FLTCON S3C64XX_GPIOREG(0x224) +#define S3C64XX_EINT56FLTCON S3C64XX_GPIOREG(0x228) +#define S3C64XX_EINT78FLTCON S3C64XX_GPIOREG(0x22C) +#define S3C64XX_EINT9FLTCON S3C64XX_GPIOREG(0x230) + +#define S3C64XX_EINT12MASK S3C64XX_GPIOREG(0x240) +#define S3C64XX_EINT34MASK S3C64XX_GPIOREG(0x244) +#define S3C64XX_EINT56MASK S3C64XX_GPIOREG(0x248) +#define S3C64XX_EINT78MASK S3C64XX_GPIOREG(0x24C) +#define S3C64XX_EINT9MASK S3C64XX_GPIOREG(0x250) + +#define S3C64XX_EINT12PEND S3C64XX_GPIOREG(0x260) +#define S3C64XX_EINT34PEND S3C64XX_GPIOREG(0x264) +#define S3C64XX_EINT56PEND S3C64XX_GPIOREG(0x268) +#define S3C64XX_EINT78PEND S3C64XX_GPIOREG(0x26C) +#define S3C64XX_EINT9PEND S3C64XX_GPIOREG(0x270) + +#define S3C64XX_PRIORITY S3C64XX_GPIOREG(0x280) +#define S3C64XX_PRIORITY_ARB(x) (1 << (x)) + +#define S3C64XX_SERVICE S3C64XX_GPIOREG(0x284) +#define S3C64XX_SERVICEPEND S3C64XX_GPIOREG(0x288) + +#define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900) +#define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904) +#define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910) +#define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914) +#define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918) +#define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C) + +#define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920) +#define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924) + +/* GPIO sleep configuration */ + +#define S3C64XX_SPCONSLP S3C64XX_GPIOREG(0x880) + +#define S3C64XX_SPCONSLP_TDO_PULLDOWN (1 << 14) +#define S3C64XX_SPCONSLP_CKE1INIT (1 << 5) + +#define S3C64XX_SPCONSLP_RSTOUT_MASK (0x3 << 12) +#define S3C64XX_SPCONSLP_RSTOUT_OUT0 (0x0 << 12) +#define S3C64XX_SPCONSLP_RSTOUT_OUT1 (0x1 << 12) +#define S3C64XX_SPCONSLP_RSTOUT_HIZ (0x2 << 12) + +#define S3C64XX_SPCONSLP_KPCOL_MASK (0x3 << 0) +#define S3C64XX_SPCONSLP_KPCOL_OUT0 (0x0 << 0) +#define S3C64XX_SPCONSLP_KPCOL_OUT1 (0x1 << 0) +#define S3C64XX_SPCONSLP_KPCOL_INP (0x2 << 0) + + +#define S3C64XX_SLPEN S3C64XX_GPIOREG(0x930) + +#define S3C64XX_SLPEN_USE_xSLP (1 << 0) +#define S3C64XX_SLPEN_CFG_BYSLPEN (1 << 1) #endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */ diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-sys.h b/arch/arm/plat-s3c64xx/include/plat/regs-sys.h index d8ed8291709..69b78d9f83b 100644 --- a/arch/arm/plat-s3c64xx/include/plat/regs-sys.h +++ b/arch/arm/plat-s3c64xx/include/plat/regs-sys.h @@ -17,6 +17,10 @@ #define S3C_SYSREG(x) (S3C_VA_SYS + (x)) +#define S3C64XX_AHB_CON0 S3C_SYSREG(0x100) +#define S3C64XX_AHB_CON1 S3C_SYSREG(0x104) +#define S3C64XX_AHB_CON2 S3C_SYSREG(0x108) + #define S3C64XX_OTHERS S3C_SYSREG(0x900) #define S3C64XX_OTHERS_USBMASK (1 << 16) diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h b/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h new file mode 100644 index 00000000000..1b155fcb03b --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h @@ -0,0 +1,113 @@ +/* arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C64XX - syscon power and sleep control registers + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_S3C64XX_REGS_SYSCON_POWER_H +#define __PLAT_S3C64XX_REGS_SYSCON_POWER_H __FILE__ + +#define S3C64XX_PWR_CFG S3C_SYSREG(0x804) + +#define S3C64XX_PWRCFG_OSC_OTG_DISABLE (1 << 17) +#define S3C64XX_PWRCFG_MMC2_DISABLE (1 << 16) +#define S3C64XX_PWRCFG_MMC1_DISABLE (1 << 15) +#define S3C64XX_PWRCFG_MMC0_DISABLE (1 << 14) +#define S3C64XX_PWRCFG_HSI_DISABLE (1 << 13) +#define S3C64XX_PWRCFG_TS_DISABLE (1 << 12) +#define S3C64XX_PWRCFG_RTC_TICK_DISABLE (1 << 11) +#define S3C64XX_PWRCFG_RTC_ALARM_DISABLE (1 << 10) +#define S3C64XX_PWRCFG_MSM_DISABLE (1 << 9) +#define S3C64XX_PWRCFG_KEY_DISABLE (1 << 8) +#define S3C64XX_PWRCFG_BATF_DISABLE (1 << 7) + +#define S3C64XX_PWRCFG_CFG_WFI_MASK (0x3 << 5) +#define S3C64XX_PWRCFG_CFG_WFI_SHIFT (5) +#define S3C64XX_PWRCFG_CFG_WFI_IGNORE (0x0 << 5) +#define S3C64XX_PWRCFG_CFG_WFI_IDLE (0x1 << 5) +#define S3C64XX_PWRCFG_CFG_WFI_STOP (0x2 << 5) +#define S3C64XX_PWRCFG_CFG_WFI_SLEEP (0x3 << 5) + +#define S3C64XX_PWRCFG_CFG_BATFLT_MASK (0x3 << 3) +#define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT (3) +#define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE (0x0 << 3) +#define S3C64XX_PWRCFG_CFG_BATFLT_IRQ (0x1 << 3) +#define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP (0x3 << 3) + +#define S3C64XX_PWRCFG_CFG_BAT_WAKE (1 << 2) +#define S3C64XX_PWRCFG_OSC27_EN (1 << 0) + +#define S3C64XX_EINT_MASK S3C_SYSREG(0x808) + +#define S3C64XX_NORMAL_CFG S3C_SYSREG(0x810) + +#define S3C64XX_NORMALCFG_IROM_ON (1 << 30) +#define S3C64XX_NORMALCFG_DOMAIN_ETM_ON (1 << 16) +#define S3C64XX_NORMALCFG_DOMAIN_S_ON (1 << 15) +#define S3C64XX_NORMALCFG_DOMAIN_F_ON (1 << 14) +#define S3C64XX_NORMALCFG_DOMAIN_P_ON (1 << 13) +#define S3C64XX_NORMALCFG_DOMAIN_I_ON (1 << 12) +#define S3C64XX_NORMALCFG_DOMAIN_G_ON (1 << 10) +#define S3C64XX_NORMALCFG_DOMAIN_V_ON (1 << 9) + +#define S3C64XX_STOP_CFG S3C_SYSREG(0x814) + +#define S3C64XX_STOPCFG_MEMORY_ARM_ON (1 << 29) +#define S3C64XX_STOPCFG_TOP_MEMORY_ON (1 << 20) +#define S3C64XX_STOPCFG_ARM_LOGIC_ON (1 << 17) +#define S3C64XX_STOPCFG_TOP_LOGIC_ON (1 << 8) +#define S3C64XX_STOPCFG_OSC_EN (1 << 0) + +#define S3C64XX_SLEEP_CFG S3C_SYSREG(0x818) + +#define S3C64XX_SLEEPCFG_OSC_EN (1 << 0) + +#define S3C64XX_STOP_MEM_CFG S3C_SYSREG(0x81c) + +#define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN (1 << 6) +#define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN (1 << 5) +#define S3C64XX_STOPMEMCFG_OTG_RETAIN (1 << 4) +#define S3C64XX_STOPMEMCFG_HSMCC_RETAIN (1 << 3) +#define S3C64XX_STOPMEMCFG_IROM_RETAIN (1 << 2) +#define S3C64XX_STOPMEMCFG_IRDA_RETAIN (1 << 1) +#define S3C64XX_STOPMEMCFG_NFCON_RETAIN (1 << 0) + +#define S3C64XX_WAKEUP_STAT S3C_SYSREG(0x908) + +#define S3C64XX_WAKEUPSTAT_MMC2 (1 << 11) +#define S3C64XX_WAKEUPSTAT_MMC1 (1 << 10) +#define S3C64XX_WAKEUPSTAT_MMC0 (1 << 9) +#define S3C64XX_WAKEUPSTAT_HSI (1 << 8) +#define S3C64XX_WAKEUPSTAT_BATFLT (1 << 6) +#define S3C64XX_WAKEUPSTAT_MSM (1 << 5) +#define S3C64XX_WAKEUPSTAT_KEY (1 << 4) +#define S3C64XX_WAKEUPSTAT_TS (1 << 3) +#define S3C64XX_WAKEUPSTAT_RTC_TICK (1 << 2) +#define S3C64XX_WAKEUPSTAT_RTC_ALARM (1 << 1) +#define S3C64XX_WAKEUPSTAT_EINT (1 << 0) + +#define S3C64XX_BLK_PWR_STAT S3C_SYSREG(0x90c) + +#define S3C64XX_BLKPWRSTAT_G (1 << 7) +#define S3C64XX_BLKPWRSTAT_ETM (1 << 6) +#define S3C64XX_BLKPWRSTAT_S (1 << 5) +#define S3C64XX_BLKPWRSTAT_F (1 << 4) +#define S3C64XX_BLKPWRSTAT_P (1 << 3) +#define S3C64XX_BLKPWRSTAT_I (1 << 2) +#define S3C64XX_BLKPWRSTAT_V (1 << 1) +#define S3C64XX_BLKPWRSTAT_TOP (1 << 0) + +#define S3C64XX_INFORM0 S3C_SYSREG(0xA00) +#define S3C64XX_INFORM1 S3C_SYSREG(0xA04) +#define S3C64XX_INFORM2 S3C_SYSREG(0xA08) +#define S3C64XX_INFORM3 S3C_SYSREG(0xA0C) + +#endif /* __PLAT_S3C64XX_REGS_SYSCON_POWER_H */ diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c index a57636137a6..90654adbb48 100644 --- a/arch/arm/plat-s3c64xx/irq-eint.c +++ b/arch/arm/plat-s3c64xx/irq-eint.c @@ -20,23 +20,11 @@ #include <asm/hardware/vic.h> #include <plat/regs-irqtype.h> +#include <plat/regs-gpio.h> #include <mach/map.h> #include <plat/cpu.h> - -/* GPIO is 0x7F008xxx, */ -#define S3C64XX_GPIOREG(x) (S3C64XX_VA_GPIO + (x)) - -#define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900) -#define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904) -#define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910) -#define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914) -#define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918) -#define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C) - -#define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920) -#define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924) - +#include <plat/pm.h> #define eint_offset(irq) ((irq) - IRQ_EINT(0)) #define eint_irq_to_bit(irq) (1 << eint_offset(irq)) @@ -46,7 +34,7 @@ static inline void s3c_irq_eint_mask(unsigned int irq) u32 mask; mask = __raw_readl(S3C64XX_EINT0MASK); - mask |= eint_irq_to_bit(irq); + mask &= ~eint_irq_to_bit(irq); __raw_writel(mask, S3C64XX_EINT0MASK); } @@ -145,6 +133,7 @@ static struct irq_chip s3c_irq_eint = { .mask_ack = s3c_irq_eint_maskack, .ack = s3c_irq_eint_ack, .set_type = s3c_irq_eint_set_type, + .set_wake = s3c_irqext_wake, }; /* s3c_irq_demux_eint diff --git a/arch/arm/plat-s3c64xx/irq-pm.c b/arch/arm/plat-s3c64xx/irq-pm.c new file mode 100644 index 00000000000..fd705faf335 --- /dev/null +++ b/arch/arm/plat-s3c64xx/irq-pm.c @@ -0,0 +1,160 @@ +/* arch/arm/plat-s3c64xx/irq-pm.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX - Interrupt handling Power Managment + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/sysdev.h> +#include <linux/interrupt.h> +#include <linux/serial_core.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <asm/hardware/vic.h> + +#include <mach/map.h> + +#include <plat/regs-serial.h> +#include <plat/regs-timer.h> +#include <plat/regs-gpio.h> +#include <plat/cpu.h> +#include <plat/pm.h> + +/* We handled all the IRQ types in this code, to save having to make several + * small files to handle each different type seperately. Having the EINT_GRP + * code here shouldn't be as much bloat as the IRQ table space needed when + * they are enabled. The added benefit is we ensure that these registers are + * in the same state as we suspsended. + */ + +static struct sleep_save irq_save[] = { + SAVE_ITEM(S3C64XX_PRIORITY), + SAVE_ITEM(S3C64XX_EINT0CON0), + SAVE_ITEM(S3C64XX_EINT0CON1), + SAVE_ITEM(S3C64XX_EINT0FLTCON0), + SAVE_ITEM(S3C64XX_EINT0FLTCON1), + SAVE_ITEM(S3C64XX_EINT0FLTCON2), + SAVE_ITEM(S3C64XX_EINT0FLTCON3), + SAVE_ITEM(S3C64XX_EINT0MASK), + SAVE_ITEM(S3C64XX_TINT_CSTAT), +}; + +static struct irq_grp_save { + u32 fltcon; + u32 con; + u32 mask; +} eint_grp_save[5]; + +struct irq_vic_save { + u32 int_select; + u32 int_enable; + u32 protect; + u32 vect_addr[32]; + u32 vect_cntl[32]; +}; + +static struct irq_vic_save irq_pm_vic0_save; +static struct irq_vic_save irq_pm_vic1_save; + +static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS]; + +static void s3c64xx_vic_save(void __iomem *base, struct irq_vic_save *save) +{ + int v; + + save->int_select = readl(base + VIC_INT_SELECT); + save->int_enable = readl(base + VIC_INT_ENABLE); + save->protect = readl(base + VIC_PROTECT); + + for (v = 0; v < ARRAY_SIZE(save->vect_addr); v++) { + save->vect_addr[v] = readl(base + VIC_VECT_ADDR0 + (v * 4)); + save->vect_cntl[v] = readl(base + VIC_VECT_CNTL0 + (v * 4)); + } +} + +static void s3c64xx_vic_restore(void __iomem *base, struct irq_vic_save *save) +{ + int v; + + writel(save->int_select, base + VIC_INT_SELECT); + writel(save->protect, base + VIC_PROTECT); + + /* set the enabled ints and then clear the non-enabled */ + writel(save->int_enable, base + VIC_INT_ENABLE); + writel(~save->int_enable, base + VIC_INT_ENABLE_CLEAR); + + for (v = 0; v < ARRAY_SIZE(save->vect_addr); v++) { + writel(save->vect_addr[v], base + VIC_VECT_ADDR0 + (v * 4)); + writel(save->vect_cntl[v], base + VIC_VECT_CNTL0 + (v * 4)); + } +} + +static int s3c64xx_irq_pm_suspend(struct sys_device *dev, pm_message_t state) +{ + struct irq_grp_save *grp = eint_grp_save; + int i; + + S3C_PMDBG("%s: suspending IRQs\n"); + + s3c64xx_vic_save(S3C_VA_VIC0, &irq_pm_vic0_save); + s3c64xx_vic_save(S3C_VA_VIC1, &irq_pm_vic1_save); + + s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); + + for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) + irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM); + + for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) { + grp->con = __raw_readl(S3C64XX_EINT12CON + (i * 4)); + grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4)); + grp->fltcon = __raw_readl(S3C64XX_EINT12FLTCON + (i * 4)); + } + + return 0; +} + +static int s3c64xx_irq_pm_resume(struct sys_device *dev) +{ + struct irq_grp_save *grp = eint_grp_save; + int i; + + S3C_PMDBG("%s: resuming IRQs\n"); + + s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); + + s3c64xx_vic_restore(S3C_VA_VIC0, &irq_pm_vic0_save); + s3c64xx_vic_restore(S3C_VA_VIC1, &irq_pm_vic1_save); + + for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) + __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM); + + for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) { + __raw_writel(grp->con, S3C64XX_EINT12CON + (i * 4)); + __raw_writel(grp->mask, S3C64XX_EINT12MASK + (i * 4)); + __raw_writel(grp->fltcon, S3C64XX_EINT12FLTCON + (i * 4)); + } + + return 0; +} + +static struct sysdev_driver s3c64xx_irq_driver = { + .suspend = s3c64xx_irq_pm_suspend, + .resume = s3c64xx_irq_pm_resume, +}; + +static int __init s3c64xx_irq_pm_init(void) +{ + return sysdev_driver_register(&s3c64xx_sysclass, &s3c64xx_irq_driver); +} + +arch_initcall(s3c64xx_irq_pm_init); + diff --git a/arch/arm/plat-s3c64xx/irq.c b/arch/arm/plat-s3c64xx/irq.c index a94f1d5e819..12e9d689b15 100644 --- a/arch/arm/plat-s3c64xx/irq.c +++ b/arch/arm/plat-s3c64xx/irq.c @@ -14,12 +14,14 @@ #include <linux/kernel.h> #include <linux/interrupt.h> +#include <linux/serial_core.h> #include <linux/irq.h> #include <linux/io.h> #include <asm/hardware/vic.h> #include <mach/map.h> +#include <plat/regs-serial.h> #include <plat/regs-timer.h> #include <plat/cpu.h> @@ -135,9 +137,6 @@ static inline unsigned int s3c_irq_uart_bit(unsigned int irq) } /* UART interrupt registers, not worth adding to seperate include header */ -#define S3C64XX_UINTP 0x30 -#define S3C64XX_UINTSP 0x34 -#define S3C64XX_UINTM 0x38 static void s3c_irq_uart_mask(unsigned int irq) { @@ -252,6 +251,8 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) s3c64xx_uart_irq(&uart_irqs[uart]); + } + diff --git a/arch/arm/plat-s3c64xx/pm.c b/arch/arm/plat-s3c64xx/pm.c new file mode 100644 index 00000000000..539a93b1b88 --- /dev/null +++ b/arch/arm/plat-s3c64xx/pm.c @@ -0,0 +1,157 @@ +/* linux/arch/arm/plat-s3c64xx/pm.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX CPU PM support. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/init.h> +#include <linux/suspend.h> +#include <linux/serial_core.h> +#include <linux/io.h> + +#include <mach/map.h> + +#include <plat/pm.h> +#include <plat/regs-sys.h> +#include <plat/regs-gpio.h> +#include <plat/regs-clock.h> +#include <plat/regs-syscon-power.h> + +#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK +#include <plat/gpio-bank-n.h> + +void s3c_pm_debug_smdkled(u32 set, u32 clear) +{ + unsigned long flags; + u32 reg; + + local_irq_save(flags); + reg = __raw_readl(S3C64XX_GPNCON); + reg &= ~(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | + S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15)); + reg |= S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | + S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15); + __raw_writel(reg, S3C64XX_GPNCON); + + reg = __raw_readl(S3C64XX_GPNDAT); + reg &= ~(clear << 12); + reg |= set << 12; + __raw_writel(reg, S3C64XX_GPNDAT); + + local_irq_restore(flags); +} +#endif + +static struct sleep_save core_save[] = { + SAVE_ITEM(S3C_APLL_LOCK), + SAVE_ITEM(S3C_MPLL_LOCK), + SAVE_ITEM(S3C_EPLL_LOCK), + SAVE_ITEM(S3C_CLK_SRC), + SAVE_ITEM(S3C_CLK_DIV0), + SAVE_ITEM(S3C_CLK_DIV1), + SAVE_ITEM(S3C_CLK_DIV2), + SAVE_ITEM(S3C_CLK_OUT), + SAVE_ITEM(S3C_HCLK_GATE), + SAVE_ITEM(S3C_PCLK_GATE), + SAVE_ITEM(S3C_SCLK_GATE), + SAVE_ITEM(S3C_MEM0_GATE), + + SAVE_ITEM(S3C_EPLL_CON1), + SAVE_ITEM(S3C_EPLL_CON0), + +#ifndef CONFIG_CPU_FREQ + SAVE_ITEM(S3C_APLL_CON), + SAVE_ITEM(S3C_MPLL_CON), +#endif +}; + +static struct sleep_save misc_save[] = { + SAVE_ITEM(S3C64XX_AHB_CON0), + SAVE_ITEM(S3C64XX_AHB_CON1), + SAVE_ITEM(S3C64XX_AHB_CON2), +}; + +void s3c_pm_configure_extint(void) +{ + __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK); + __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK); +} + +void s3c_pm_restore_core(void) +{ + __raw_writel(0, S3C64XX_EINT_MASK); + + s3c_pm_debug_smdkled(1 << 2, 0); + + s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); + s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save)); +} + +void s3c_pm_save_core(void) +{ + s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save)); + s3c_pm_do_save(core_save, ARRAY_SIZE(core_save)); +} + +/* since both s3c6400 and s3c6410 share the same sleep pm calls, we + * put the per-cpu code in here until any new cpu comes along and changes + * this. + */ + +static void s3c64xx_cpu_suspend(void) +{ + unsigned long tmp; + + /* set our standby method to sleep */ + + tmp = __raw_readl(S3C64XX_PWR_CFG); + tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK; + tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP; + __raw_writel(tmp, S3C64XX_PWR_CFG); + + /* set the LED state to 0110 over sleep */ + s3c_pm_debug_smdkled(3 << 1, 0xf); + + /* issue the standby signal into the pm unit. Note, we + * issue a write-buffer drain just in case */ + + tmp = 0; + + asm("b 1f\n\t" + ".align 5\n\t" + "1:\n\t" + "mcr p15, 0, %0, c7, c10, 5\n\t" + "mcr p15, 0, %0, c7, c10, 4\n\t" + "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp)); + + /* we should never get past here */ + + panic("sleep resumed to originator?"); +} + +static void s3c64xx_pm_prepare(void) +{ + /* store address of resume. */ + __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0); + + /* ensure previous wakeup state is cleared before sleeping */ + __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT); +} + +static int s3c64xx_pm_init(void) +{ + pm_cpu_prep = s3c64xx_pm_prepare; + pm_cpu_sleep = s3c64xx_cpu_suspend; + pm_uart_udivslot = 1; + return 0; +} + +arch_initcall(s3c64xx_pm_init); diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c index 8d9a0cada66..a6f6b91b732 100644 --- a/arch/arm/plat-s3c64xx/s3c6400-clock.c +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c @@ -650,6 +650,5 @@ void __init s3c6400_register_clocks(void) } } - clk_mpll.parent = &clk_mout_mpll.clk; clk_epll.parent = &clk_mout_epll.clk; } diff --git a/arch/arm/plat-s3c64xx/sleep.S b/arch/arm/plat-s3c64xx/sleep.S new file mode 100644 index 00000000000..8b96f2f0e06 --- /dev/null +++ b/arch/arm/plat-s3c64xx/sleep.S @@ -0,0 +1,135 @@ +/* linux/0arch/arm/plat-s3c64xx/sleep.S + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX CPU sleep code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <mach/map.h> + +#undef S3C64XX_VA_GPIO +#define S3C64XX_VA_GPIO (0x0) + +#include <plat/regs-gpio.h> +#include <plat/gpio-bank-n.h> + +#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT)) + + .text + + /* s3c_cpu_save + * + * Save enough processor state to allow the restart of the pm.c + * code after resume. + * + * entry: + * r0 = pointer to the save block + * exit: + * r0 = exit code: 1 => stored data + * 0 => resumed from sleep + */ + +ENTRY(s3c_cpu_save) + stmfd sp!, { r4 - r12, lr } + + mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID + mrc p15, 0, r5, c3, c0, 0 @ Domain ID + mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 + mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 + mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control + mrc p15, 0, r9, c1, c0, 0 @ Control register + + stmia r0, { r4 - r13 } @ Save CP registers and SP + mov r0, #0 + ldmfd sp, { r4 - r12, pc } @ return, not disturbing SP + + @@ return to the caller, after the MMU is turned on. + @@ restore the last bits of the stack and return. +resume_with_mmu: + mov r0, #1 + ldmfd sp!, { r4 - r12, pc } @ return, from sp from s3c_cpu_save + + .data + + /* the next bit is code, but it requires easy access to the + * s3c_sleep_save_phys data before the MMU is switched on, so + * we store the code that needs this variable in the .data where + * the value can be written to (the .text segment is RO). + */ + + .global s3c_sleep_save_phys +s3c_sleep_save_phys: + .word 0 + + /* Sleep magic, the word before the resume entry point so that the + * bootloader can check for a resumeable image. */ + + .word 0x2bedf00d + + /* s3c_cpu_reusme + * + * This is the entry point, stored by whatever method the bootloader + * requires to get the kernel runnign again. This code expects to be + * entered with no caches live and the MMU disabled. It will then + * restore the MMU and other basic CP registers saved and restart + * the kernel C code to finish the resume code. + */ + +ENTRY(s3c_cpu_resume) + msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE + ldr r2, =LL_UART /* for debug */ + +#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK + /* Initialise the GPIO state if we are debugging via the SMDK LEDs, + * as the uboot version supplied resets these to inputs during the + * resume checks. + */ + + ldr r3, =S3C64XX_PA_GPIO + ldr r0, [ r3, #S3C64XX_GPNCON ] + bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \ + S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15)) + orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \ + S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15)) + str r0, [ r3, #S3C64XX_GPNCON ] + + ldr r0, [ r3, #S3C64XX_GPNDAT ] + bic r0, r0, #0xf << 12 @ GPN12..15 + orr r0, r0, #1 << 15 @ GPN15 + str r0, [ r3, #S3C64XX_GPNDAT ] +#endif + + /* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches + * are thorougly cleaned just in case the bootloader didn't do it + * for us. */ + mov r0, #0 + mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache + mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache + mcr p15, 0, r0, c7, c10, 4 @ drain write buffer + mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs + + ldr r0, s3c_sleep_save_phys + ldmia r0, { r4 - r13 } + + mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID + mcr p15, 0, r5, c3, c0, 0 @ Domain ID + mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 + mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 + mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control + + ldr r2, =resume_with_mmu + mcr p15, 0, r9, c1, c0, 0 /* turn mmu back on */ + nop + mov pc, r2 /* jump back */ + + .end diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 94b8fea5fb8..77efd7a7aab 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_KGDB_TESTS) += kgdbts.o obj-$(CONFIG_SGI_XP) += sgi-xp/ obj-$(CONFIG_SGI_GRU) += sgi-gru/ obj-$(CONFIG_HP_ILO) += hpilo.o +obj-$(CONFIG_MACH_SMDK6410) += smdk6410-sleeptest.o obj-$(CONFIG_LOW_MEMORY_KILLER) += lowmemorykiller.o obj-$(CONFIG_MACH_NEO1973) += neo1973_version.o \ neo1973_pm_host.o \ diff --git a/drivers/misc/smdk6410-sleeptest.c b/drivers/misc/smdk6410-sleeptest.c new file mode 100644 index 00000000000..3bf668024fb --- /dev/null +++ b/drivers/misc/smdk6410-sleeptest.c @@ -0,0 +1,65 @@ +/* linux/drivers/misc/smdk6410-sleeptest.c + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/gpio.h> +#include <linux/err.h> +#include <linux/interrupt.h> + +#include <plat/gpio-cfg.h> + +static irqreturn_t sleep_action(int irq, void *pw) +{ + printk(KERN_INFO "%s: irq %d\n", __func__, irq); + return IRQ_HANDLED; +} + +static void sleep_setup(unsigned int irq, unsigned int gpio) +{ + int ret; + + WARN_ON(s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)) < 0); + WARN_ON(s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP) < 0); + + ret = request_irq(irq, sleep_action, IRQF_TRIGGER_FALLING, + "sleep", NULL); + if (ret < 0) + printk(KERN_ERR "%s: request_irq() failed\n", __func__); + + ret = set_irq_wake(irq, 1); + if (ret < 0) + printk(KERN_ERR "%s: set_irq_wake() failed\n", __func__); +} + +static void sleep_led(unsigned int gpio) +{ + gpio_request(gpio, "sleep led"); + gpio_direction_output(gpio, 0); +} + +static __init int smdk6410_sleeptest_init(void) +{ + sleep_setup(IRQ_EINT(10), S3C64XX_GPN(10)); + sleep_led(S3C64XX_GPN(15)); + sleep_led(S3C64XX_GPN(14)); + sleep_led(S3C64XX_GPN(13)); + sleep_led(S3C64XX_GPN(12)); + + return 0; +} + +module_init(smdk6410_sleeptest_init); + +MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/serial/s3c6400.c b/drivers/serial/s3c6400.c index 06936d13393..3e378523368 100644 --- a/drivers/serial/s3c6400.c +++ b/drivers/serial/s3c6400.c @@ -102,6 +102,7 @@ static struct s3c24xx_uart_info s3c6400_uart_inf = { .name = "Samsung S3C6400 UART", .type = PORT_S3C6400, .fifosize = 64, + .has_divslot = 1, .rx_fifomask = S3C2440_UFSTAT_RXMASK, .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, .rx_fifofull = S3C2440_UFSTAT_RXFULL, diff --git a/drivers/serial/samsung.c b/drivers/serial/samsung.c index c262eb1ae20..eca6cab0e20 100644 --- a/drivers/serial/samsung.c +++ b/drivers/serial/samsung.c @@ -512,6 +512,7 @@ s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c) struct baud_calc { struct s3c24xx_uart_clksrc *clksrc; unsigned int calc; + unsigned int divslot; unsigned int quot; struct clk *src; }; @@ -521,6 +522,7 @@ static int s3c24xx_serial_calcbaud(struct baud_calc *calc, struct s3c24xx_uart_clksrc *clksrc, unsigned int baud) { + struct s3c24xx_uart_port *ourport = to_ourport(port); unsigned long rate; calc->src = clk_get(port->dev, clksrc->name); @@ -531,8 +533,24 @@ static int s3c24xx_serial_calcbaud(struct baud_calc *calc, rate /= clksrc->divisor; calc->clksrc = clksrc; - calc->quot = (rate + (8 * baud)) / (16 * baud); - calc->calc = (rate / (calc->quot * 16)); + + if (ourport->info->has_divslot) { + unsigned long div = rate / baud; + + /* The UDIVSLOT register on the newer UARTs allows us to + * get a divisor adjustment of 1/16th on the baud clock. + * + * We don't keep the UDIVSLOT value (the 16ths we calculated + * by not multiplying the baud by 16) as it is easy enough + * to recalculate. + */ + + calc->quot = div / 16; + calc->calc = rate / div; + } else { + calc->quot = (rate + (8 * baud)) / (16 * baud); + calc->calc = (rate / (calc->quot * 16)); + } calc->quot--; return 1; @@ -615,6 +633,30 @@ static unsigned int s3c24xx_serial_getclk(struct uart_port *port, return best->quot; } +/* udivslot_table[] + * + * This table takes the fractional value of the baud divisor and gives + * the recommended setting for the UDIVSLOT register. + */ +static u16 udivslot_table[16] = { + [0] = 0x0000, + [1] = 0x0080, + [2] = 0x0808, + [3] = 0x0888, + [4] = 0x2222, + [5] = 0x4924, + [6] = 0x4A52, + [7] = 0x54AA, + [8] = 0x5555, + [9] = 0xD555, + [10] = 0xD5D5, + [11] = 0xDDD5, + [12] = 0xDDDD, + [13] = 0xDFDD, + [14] = 0xDFDF, + [15] = 0xFFDF, +}; + static void s3c24xx_serial_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old) @@ -627,6 +669,7 @@ static void s3c24xx_serial_set_termios(struct uart_port *port, unsigned int baud, quot; unsigned int ulcon; unsigned int umcon; + unsigned int udivslot = 0; /* * We don't support modem control lines. @@ -648,6 +691,7 @@ static void s3c24xx_serial_set_termios(struct uart_port *port, /* check to see if we need to change clock source */ if (ourport->clksrc != clksrc || ourport->baudclk != clk) { + dbg("selecting clock %p\n", clk); s3c24xx_serial_setsource(port, clksrc); if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) { @@ -655,6 +699,7 @@ static void s3c24xx_serial_set_termios(struct uart_port *port, ourport->baudclk = NULL; } + //dbg("calling clk_enable() for new baud clock\n"); clk_enable(clk); ourport->clksrc = clksrc; @@ -662,6 +707,13 @@ static void s3c24xx_serial_set_termios(struct uart_port *port, ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0; } + if (ourport->info->has_divslot) { + unsigned int div = ourport->baudclk_rate / baud; + + udivslot = udivslot_table[div & 15]; + dbg("udivslot = %04x (div %d)\n", udivslot, div & 15); + } + switch (termios->c_cflag & CSIZE) { case CS5: dbg("config: 5bits/char\n"); @@ -701,12 +753,16 @@ static void s3c24xx_serial_set_termios(struct uart_port *port, spin_lock_irqsave(&port->lock, flags); - dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot); + dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n", + ulcon, quot, udivslot); wr_regl(port, S3C2410_ULCON, ulcon); wr_regl(port, S3C2410_UBRDIV, quot); wr_regl(port, S3C2410_UMCON, umcon); + if (ourport->info->has_divslot) + wr_regl(port, S3C2443_DIVSLOT, udivslot); + dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n", rd_regl(port, S3C2410_ULCON), rd_regl(port, S3C2410_UCON), diff --git a/drivers/serial/samsung.h b/drivers/serial/samsung.h index 9675b2fa267..f259211279f 100644 --- a/drivers/serial/samsung.h +++ b/drivers/serial/samsung.h @@ -23,6 +23,10 @@ struct s3c24xx_uart_info { unsigned long tx_fifoshift; unsigned long tx_fifofull; + /* uart port features */ + + unsigned int has_divslot:1; + /* clock source control */ int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk); diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c index 9ffb6b68a8e..09ebbc69b0c 100644 --- a/drivers/video/s3c-fb.c +++ b/drivers/video/s3c-fb.c @@ -962,8 +962,48 @@ static int __devexit s3c_fb_remove(struct platform_device *pdev) return 0; } +#ifdef CONFIG_PM +static int s3c_fb_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct s3c_fb *sfb = platform_get_drvdata(pdev); + struct s3c_fb_win *win; + int win_no; + + for (win_no = S3C_FB_MAX_WIN; win_no >= 0; win_no--) { + win = sfb->windows[win_no]; + if (!win) + continue; + + /* use the blank function to push into power-down */ + s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo); + } + + clk_disable(sfb->bus_clk); + return 0; +} + +static int s3c_fb_resume(struct platform_device *pdev) +{ + struct s3c_fb *sfb = platform_get_drvdata(pdev); + struct s3c_fb_win *win; + int win_no; + + clk_enable(sfb->bus_clk); + + for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) { + win = sfb->windows[win_no]; + if (!win) + continue; + + s3c_fb_set_par(win->fbinfo); + } + + return 0; +} +#else #define s3c_fb_suspend NULL #define s3c_fb_resume NULL +#endif static struct platform_driver s3c_fb_driver = { .probe = s3c_fb_probe, |