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authorMikael Pettersson <mikpe@it.uu.se>2007-09-11 22:28:37 +0200
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2007-09-11 22:28:37 +0200
commit56fe23d5a702a39ee3bb29a04b55db292479d07a (patch)
tree71631f145fe8969f0c4d347a37fb5435e733bef8
parent58e47bb1767aa89bfa9cf7ecf4bc051886ae22b3 (diff)
pdc202xx_new: PLL detection fix
Fix a bitmask typo in the pdc202xx_new PLL frequency detection code which causes it to truncate an intermediate difference to 26 bits instead of the correct 30 bits (the PLL's bitwidth). Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
-rw-r--r--drivers/ide/pci/pdc202xx_new.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ide/pci/pdc202xx_new.c b/drivers/ide/pci/pdc202xx_new.c
index f74a02aba58..7b0e479c355 100644
--- a/drivers/ide/pci/pdc202xx_new.c
+++ b/drivers/ide/pci/pdc202xx_new.c
@@ -341,7 +341,7 @@ static long __devinit detect_pll_input_clock(unsigned long dma_base)
*/
usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
(end_time.tv_usec - start_time.tv_usec);
- pll_input = ((start_count - end_count) & 0x3ffffff) / 10 *
+ pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
(10000000 / usec_elapsed);
DBG("start[%ld] end[%ld]\n", start_count, end_count);