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authorCatalin Marinas <catalin.marinas@arm.com>2006-03-07 14:42:27 +0000
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-03-07 14:42:27 +0000
commit6a0e243069b09a323255f6e847c87d531961cd96 (patch)
tree575a7194c86b2b3e1b9db30e283a2f5705e89e99
parentd11d9b2dd2c43dd99a491df8a83ae28401db0044 (diff)
[ARM] 3352/1: DSB required for the completion of a TLB maintenance operation
Patch from Catalin Marinas Chapter B2.7.3 in the latest ARM ARM (with v6 information) states that the completion of a TLB maintenance operation is only guaranteed by the execution of a DSB (Data Syncronization Barrier, formerly Data Write Barrier or Drain Write Buffer). Note that a DSB is only needed in the flush_tlb_kernel_* functions since the completion is guaranteed by a mode change (i.e. switching back to user mode) for the flush_tlb_user_* functions. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/mm/tlb-v6.S1
-rw-r--r--include/asm-arm/tlbflush.h6
3 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 15dc1a0dffb..9f80fa502f8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -78,7 +78,7 @@ menu "System Type"
choice
prompt "ARM system type"
- default ARCH_RPC
+ default ARCH_VERSATILE
config ARCH_CLPS7500
bool "Cirrus-CL-PS7500FE"
diff --git a/arch/arm/mm/tlb-v6.S b/arch/arm/mm/tlb-v6.S
index 6f76b89ef46..fd6adde3909 100644
--- a/arch/arm/mm/tlb-v6.S
+++ b/arch/arm/mm/tlb-v6.S
@@ -80,6 +80,7 @@ ENTRY(v6wbi_flush_kern_tlb_range)
add r0, r0, #PAGE_SZ
cmp r0, r1
blo 1b
+ mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier
mov pc, lr
.section ".text.init", #alloc, #execinstr
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index 9387a5e1ffe..0c2acc944a0 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -340,6 +340,12 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr));
if (tlb_flag(TLB_V6_I_PAGE))
asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr));
+
+ /* The ARM ARM states that the completion of a TLB maintenance
+ * operation is only guaranteed by a DSB instruction
+ */
+ if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE))
+ asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
}
/*