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authorLennert Buytenhek <buytenh@wantstofly.org>2005-06-26 22:24:13 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-06-26 22:24:13 +0100
commit91f6a589fb6bb4ce6b6b196e910d3b907e1d0a40 (patch)
treef4c9c06ad5f8d9e9d49d36db783893e1e96084b5
parent09b8b5f843afc21daf710cc610e5ca890ee94696 (diff)
[PATCH] ARM: 2753/1: move ixdp* cpld mappings
Patch from Lennert Buytenhek All ixdp platforms currently have a cpld mapped in at 0xfafff000. Since this address is not 1M-aligned, a regular page mapping will be used instead of a section mapping, which opens up the possibility of triggering ixp2400 erratum #66 as we only do the XCB=101 workaround thing for section mappings. There is still a lot of space higher up in the virtual memory map for 1M mappings, so move the cpld mapping to 0xfe000000 and make it 1M big so that a section mapping will be used for it. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Deepak Saxena Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--include/asm-arm/arch-ixp2000/ixdp2x00.h4
-rw-r--r--include/asm-arm/arch-ixp2000/ixdp2x01.h4
2 files changed, 4 insertions, 4 deletions
diff --git a/include/asm-arm/arch-ixp2000/ixdp2x00.h b/include/asm-arm/arch-ixp2000/ixdp2x00.h
index 3a398dfbf12..229381c6428 100644
--- a/include/asm-arm/arch-ixp2000/ixdp2x00.h
+++ b/include/asm-arm/arch-ixp2000/ixdp2x00.h
@@ -21,8 +21,8 @@
* On board CPLD memory map
*/
#define IXDP2X00_PHYS_CPLD_BASE 0xc7000000
-#define IXDP2X00_VIRT_CPLD_BASE 0xfafff000
-#define IXDP2X00_CPLD_SIZE 0x00001000
+#define IXDP2X00_VIRT_CPLD_BASE 0xfe000000
+#define IXDP2X00_CPLD_SIZE 0x00100000
#define IXDP2X00_CPLD_REG(x) \
diff --git a/include/asm-arm/arch-ixp2000/ixdp2x01.h b/include/asm-arm/arch-ixp2000/ixdp2x01.h
index b3a1bcda8d0..b768009c3a5 100644
--- a/include/asm-arm/arch-ixp2000/ixdp2x01.h
+++ b/include/asm-arm/arch-ixp2000/ixdp2x01.h
@@ -18,8 +18,8 @@
#define __IXDP2X01_H__
#define IXDP2X01_PHYS_CPLD_BASE 0xc6024000
-#define IXDP2X01_VIRT_CPLD_BASE 0xfafff000
-#define IXDP2X01_CPLD_REGION_SIZE 0x00001000
+#define IXDP2X01_VIRT_CPLD_BASE 0xfe000000
+#define IXDP2X01_CPLD_REGION_SIZE 0x00100000
#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
#define IXDP2X01_CPLD_PHYS_REG(reg) (volatile u32*)(IXDP2X01_PHYS_CPLD_BASE | reg)