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authorDave Airlie <airlied@starflyer.(none)>2005-09-11 19:55:53 +1000
committerDave Airlie <airlied@linux.ie>2005-09-11 19:55:53 +1000
commit9d17601c4e132eee9fe450191f6866fb9fb5a762 (patch)
treef4bdfbc95a28370ad0bf9f0d0f42a821f5a8ec9d
parent70dfcfea4b728ab26af1a3e0f331cc63a7e3554b (diff)
drm: update radeon driver to 1.18
Add support for GL_ATI_fragment_shader, new packets R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) From: Roland Scheidegger, David Airlie Signed-off-by: David Airlie <airlied@linux.ie>
-rw-r--r--drivers/char/drm/radeon_drm.h11
-rw-r--r--drivers/char/drm/radeon_drv.h11
-rw-r--r--drivers/char/drm/radeon_state.c18
3 files changed, 37 insertions, 3 deletions
diff --git a/drivers/char/drm/radeon_drm.h b/drivers/char/drm/radeon_drm.h
index 3792798270a..67a8bf04970 100644
--- a/drivers/char/drm/radeon_drm.h
+++ b/drivers/char/drm/radeon_drm.h
@@ -153,7 +153,16 @@
#define RADEON_EMIT_PP_CUBIC_FACES_2 82
#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
#define R200_EMIT_PP_TRI_PERF_CNTL 84
-#define RADEON_MAX_STATE_PACKETS 85
+#define R200_EMIT_PP_AFS_0 85
+#define R200_EMIT_PP_AFS_1 86
+#define R200_EMIT_ATF_TFACTOR 87
+#define R200_EMIT_PP_TXCTLALL_0 88
+#define R200_EMIT_PP_TXCTLALL_1 89
+#define R200_EMIT_PP_TXCTLALL_2 90
+#define R200_EMIT_PP_TXCTLALL_3 91
+#define R200_EMIT_PP_TXCTLALL_4 92
+#define R200_EMIT_PP_TXCTLALL_5 93
+#define RADEON_MAX_STATE_PACKETS 94
/* Commands understood by cmd_buffer ioctl. More can be added but
* obviously these can't be removed or changed:
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index f12a963ede1..430598e1fa6 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -38,7 +38,7 @@
#define DRIVER_NAME "radeon"
#define DRIVER_DESC "ATI Radeon"
-#define DRIVER_DATE "20050311"
+#define DRIVER_DATE "20050720"
/* Interface history:
*
@@ -83,9 +83,13 @@
* 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
* texture filtering on r200
* 1.17- Add initial support for R300 (3D).
+ * 1.18- Add support for GL_ATI_fragment_shader, new packets
+ * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
+ * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
+ * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
*/
#define DRIVER_MAJOR 1
-#define DRIVER_MINOR 17
+#define DRIVER_MINOR 18
#define DRIVER_PATCHLEVEL 0
#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 )
@@ -857,6 +861,9 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp,
#define R200_PP_TRI_PERF 0x2cf8
+#define R200_PP_AFS_0 0x2f80
+#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
+
/* Constants */
#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c
index 64a3e3a406e..c4325f1e229 100644
--- a/drivers/char/drm/radeon_state.c
+++ b/drivers/char/drm/radeon_state.c
@@ -207,6 +207,15 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
case RADEON_EMIT_PP_CUBIC_FACES_1:
case RADEON_EMIT_PP_CUBIC_FACES_2:
case R200_EMIT_PP_TRI_PERF_CNTL:
+ case R200_EMIT_PP_AFS_0:
+ case R200_EMIT_PP_AFS_1:
+ case R200_EMIT_ATF_TFACTOR:
+ case R200_EMIT_PP_TXCTLALL_0:
+ case R200_EMIT_PP_TXCTLALL_1:
+ case R200_EMIT_PP_TXCTLALL_2:
+ case R200_EMIT_PP_TXCTLALL_3:
+ case R200_EMIT_PP_TXCTLALL_4:
+ case R200_EMIT_PP_TXCTLALL_5:
/* These packets don't contain memory offsets */
break;
@@ -568,6 +577,15 @@ static struct {
{ RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
{ RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
{ R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
+ { R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, /* 85 */
+ { R200_PP_AFS_1, 32, "R200_PP_AFS_1"},
+ { R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
+ { R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
+ { R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
+ { R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
+ { R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
+ { R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
+ { R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
};