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authorMatt Porter <mporter@kernel.crashing.org>2005-08-18 11:24:26 -0700
committerLinus Torvalds <torvalds@g5.osdl.org>2005-08-18 12:53:58 -0700
commitc6a3ea22af7a2ed36afa4672a86b3a86d604db33 (patch)
treeb61bf02bb31ad01a0fe734dc697dd0c9583e0441
parent28cd1d17801774561c81a5be53bfb2d632aee2a2 (diff)
[PATCH] ppc32: Fix PPC440SP SRAM controller DCRs
Fixes the incorrect DCR base value for the 440SP SRAM controller. Signed-off-by: Matt Porter <mporter@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
-rw-r--r--include/asm-ppc/ibm44x.h4
1 files changed, 0 insertions, 4 deletions
diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h
index 21e41c9b726..e5374be86ae 100644
--- a/include/asm-ppc/ibm44x.h
+++ b/include/asm-ppc/ibm44x.h
@@ -423,11 +423,7 @@
#define MQ0_CONFIG_SIZE_2G 0x0000c000
/* Internal SRAM Controller 440GX/440SP */
-#ifdef CONFIG_440SP
-#define DCRN_SRAM0_BASE 0x100
-#else /* 440GX */
#define DCRN_SRAM0_BASE 0x000
-#endif
#define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020)
#define DCRN_SRAM0_SB1CR (DCRN_SRAM0_BASE + 0x021)