Merge with /shiny/git/linux-2.6/.git

1115 files changed, 88971 insertions, 12248 deletions

diff --git a/CREDITS b/CREDITS
index 3b7a1548aaf..50121d432b6 100644
--- a/CREDITS
+++ b/CREDITS
@@ -1624,10 +1624,10 @@ E: ajoshi@shell.unixbox.com
 D: fbdev hacking
 
 N: Jesper Juhl
-E: juhl-lkml@dif.dk
-D: Various small janitor fixes, cleanups etc.
+E: jesper.juhl@gmail.com
+D: Various fixes, cleanups and minor features.
 S: Lemnosvej 1, 3.tv
-S: 2300 Copenhagen S
+S: 2300 Copenhagen S.
 S: Denmark
 
 N: Jozsef Kadlecsik
@@ -2380,8 +2380,8 @@ E: tmolina@cablespeed.com
 D: bug fixes, documentation, minor hackery
 
 N: James Morris
-E: jmorris@redhat.com
-W: http://www.intercode.com.au/jmorris/
+E: jmorris@namei.org
+W: http://namei.org/
 D: Netfilter, Linux Security Modules (LSM), SELinux, IPSec,
 D: Crypto API, general networking, miscellaneous.
 S: PO Box 707
diff --git a/Documentation/Changes b/Documentation/Changes
index dfec7569d45..5eaab0441d7 100644
--- a/Documentation/Changes
+++ b/Documentation/Changes
@@ -65,6 +65,7 @@ o  isdn4k-utils           3.1pre1                 # isdnctrl 2>&1|grep version
 o  nfs-utils              1.0.5                   # showmount --version
 o  procps                 3.2.0                   # ps --version
 o  oprofile               0.9                     # oprofiled --version
+o  udev                   058                     # udevinfo -V
 
 Kernel compilation
 ==================
diff --git a/Documentation/SubmittingPatches b/Documentation/SubmittingPatches
index 6761a7b241a..7f43b040311 100644
--- a/Documentation/SubmittingPatches
+++ b/Documentation/SubmittingPatches
@@ -149,6 +149,11 @@ USB, framebuffer devices, the VFS, the SCSI subsystem, etc.  See the
 MAINTAINERS file for a mailing list that relates specifically to
 your change.
 
+If changes affect userland-kernel interfaces, please send
+the MAN-PAGES maintainer (as listed in the MAINTAINERS file)
+a man-pages patch, or at least a notification of the change,
+so that some information makes its way into the manual pages.
+
 Even if the maintainer did not respond in step #4, make sure to ALWAYS
 copy the maintainer when you change their code.
 
diff --git a/Documentation/dontdiff b/Documentation/dontdiff
index b974cf595d0..96bea278bbf 100644
--- a/Documentation/dontdiff
+++ b/Documentation/dontdiff
@@ -104,6 +104,7 @@ logo_*.c
 logo_*_clut224.c
 logo_*_mono.c
 lxdialog
+mach-types
 mach-types.h
 make_times_h
 map
diff --git a/Documentation/fb/vesafb.txt b/Documentation/fb/vesafb.txt
index 814e2f56a6a..62db6758d1c 100644
--- a/Documentation/fb/vesafb.txt
+++ b/Documentation/fb/vesafb.txt
@@ -144,7 +144,21 @@ vgapal	Use the standard vga registers for palette changes.
 	This is the default.
 pmipal	Use the protected mode interface for palette changes.
 
-mtrr	setup memory type range registers for the vesafb framebuffer.
+mtrr:n	setup memory type range registers for the vesafb framebuffer
+	where n:
+	      0 - disabled (equivalent to nomtrr)
+	      1 - uncachable
+	      2 - write-back
+	      3 - write-combining (default)
+	      4 - write-through
+
+	If you see the following in dmesg, choose the type that matches the
+	old one. In this example, use "mtrr:2".
+...
+mtrr: type mismatch for e0000000,8000000 old: write-back new: write-combining
+...
+
+nomtrr  disable mtrr
 
 vremap:n
         remap 'n' MiB of video RAM. If 0 or not specified, remap memory
diff --git a/Documentation/infiniband/core_locking.txt b/Documentation/infiniband/core_locking.txt
new file mode 100644
index 00000000000..e1678542279
--- /dev/null
+++ b/Documentation/infiniband/core_locking.txt
@@ -0,0 +1,114 @@
+INFINIBAND MIDLAYER LOCKING
+
+  This guide is an attempt to make explicit the locking assumptions
+  made by the InfiniBand midlayer.  It describes the requirements on
+  both low-level drivers that sit below the midlayer and upper level
+  protocols that use the midlayer.
+
+Sleeping and interrupt context
+
+  With the following exceptions, a low-level driver implementation of
+  all of the methods in struct ib_device may sleep.  The exceptions
+  are any methods from the list:
+
+    create_ah
+    modify_ah
+    query_ah
+    destroy_ah
+    bind_mw
+    post_send
+    post_recv
+    poll_cq
+    req_notify_cq
+    map_phys_fmr
+
+  which may not sleep and must be callable from any context.
+
+  The corresponding functions exported to upper level protocol
+  consumers:
+
+    ib_create_ah
+    ib_modify_ah
+    ib_query_ah
+    ib_destroy_ah
+    ib_bind_mw
+    ib_post_send
+    ib_post_recv
+    ib_req_notify_cq
+    ib_map_phys_fmr
+
+  are therefore safe to call from any context.
+
+  In addition, the function
+
+    ib_dispatch_event
+
+  used by low-level drivers to dispatch asynchronous events through
+  the midlayer is also safe to call from any context.
+
+Reentrancy
+
+  All of the methods in struct ib_device exported by a low-level
+  driver must be fully reentrant.  The low-level driver is required to
+  perform all synchronization necessary to maintain consistency, even
+  if multiple function calls using the same object are run
+  simultaneously.
+
+  The IB midlayer does not perform any serialization of function calls.
+
+  Because low-level drivers are reentrant, upper level protocol
+  consumers are not required to perform any serialization.  However,
+  some serialization may be required to get sensible results.  For
+  example, a consumer may safely call ib_poll_cq() on multiple CPUs
+  simultaneously.  However, the ordering of the work completion
+  information between different calls of ib_poll_cq() is not defined.
+
+Callbacks
+
+  A low-level driver must not perform a callback directly from the
+  same callchain as an ib_device method call.  For example, it is not
+  allowed for a low-level driver to call a consumer's completion event
+  handler directly from its post_send method.  Instead, the low-level
+  driver should defer this callback by, for example, scheduling a
+  tasklet to perform the callback.
+
+  The low-level driver is responsible for ensuring that multiple
+  completion event handlers for the same CQ are not called
+  simultaneously.  The driver must guarantee that only one CQ event
+  handler for a given CQ is running at a time.  In other words, the
+  following situation is not allowed:
+
+        CPU1                                    CPU2
+
+  low-level driver ->
+    consumer CQ event callback:
+      /* ... */
+      ib_req_notify_cq(cq, ...);
+                                        low-level driver ->
+      /* ... */                           consumer CQ event callback:
+                                            /* ... */
+      return from CQ event handler
+
+  The context in which completion event and asynchronous event
+  callbacks run is not defined.  Depending on the low-level driver, it
+  may be process context, softirq context, or interrupt context.
+  Upper level protocol consumers may not sleep in a callback.
+
+Hot-plug
+
+  A low-level driver announces that a device is ready for use by
+  consumers when it calls ib_register_device(), all initialization
+  must be complete before this call.  The device must remain usable
+  until the driver's call to ib_unregister_device() has returned.
+
+  A low-level driver must call ib_register_device() and
+  ib_unregister_device() from process context.  It must not hold any
+  semaphores that could cause deadlock if a consumer calls back into
+  the driver across these calls.
+
+  An upper level protocol consumer may begin using an IB device as
+  soon as the add method of its struct ib_client is called for that
+  device.  A consumer must finish all cleanup and free all resources
+  relating to a device before returning from the remove method.
+
+  A consumer is permitted to sleep in its add and remove methods.
diff --git a/Documentation/infiniband/user_mad.txt b/Documentation/infiniband/user_mad.txt
index cae0c83f1ee..750fe5e80eb 100644
--- a/Documentation/infiniband/user_mad.txt
+++ b/Documentation/infiniband/user_mad.txt
@@ -28,13 +28,37 @@ Creating MAD agents
 
 Receiving MADs
 
-  MADs are received using read().  The buffer passed to read() must be
-  large enough to hold at least one struct ib_user_mad.  For example:
-
-	struct ib_user_mad mad;
-	ret = read(fd, &mad, sizeof mad);
-	if (ret != sizeof mad)
+  MADs are received using read().  The receive side now supports
+  RMPP. The buffer passed to read() must be at least one
+  struct ib_user_mad + 256 bytes. For example:
+
+  If the buffer passed is not large enough to hold the received
+  MAD (RMPP), the errno is set to ENOSPC and the length of the
+  buffer needed is set in mad.length.
+
+  Example for normal MAD (non RMPP) reads:
+	struct ib_user_mad *mad;
+	mad = malloc(sizeof *mad + 256);
+	ret = read(fd, mad, sizeof *mad + 256);
+	if (ret != sizeof mad + 256) {
+		perror("read");
+		free(mad);
+	}
+
+  Example for RMPP reads:
+	struct ib_user_mad *mad;
+	mad = malloc(sizeof *mad + 256);
+	ret = read(fd, mad, sizeof *mad + 256);
+	if (ret == -ENOSPC)) {
+		length = mad.length;
+		free(mad);
+		mad = malloc(sizeof *mad + length);
+		ret = read(fd, mad, sizeof *mad + length);
+	}
+	if (ret < 0) {
 		perror("read");
+		free(mad);
+	}
 
   In addition to the actual MAD contents, the other struct ib_user_mad
   fields will be filled in with information on the received MAD.  For
@@ -50,18 +74,21 @@ Sending MADs
 
   MADs are sent using write().  The agent ID for sending should be
   filled into the id field of the MAD, the destination LID should be
-  filled into the lid field, and so on.  For example:
+  filled into the lid field, and so on.  The send side does support
+  RMPP so arbitrary length MAD can be sent. For example:
+
+	struct ib_user_mad *mad;
 
-	struct ib_user_mad mad;
+	mad = malloc(sizeof *mad + mad_length);
 
-	/* fill in mad.data */
+	/* fill in mad->data */
 
-	mad.id  = my_agent;	/* req.id from agent registration */
-	mad.lid = my_dest;	/* in network byte order... */
+	mad->hdr.id  = my_agent;	/* req.id from agent registration */
+	mad->hdr.lid = my_dest;		/* in network byte order... */
 	/* etc. */
 
-	ret = write(fd, &mad, sizeof mad);
-	if (ret != sizeof mad)
+	ret = write(fd, &mad, sizeof *mad + mad_length);
+	if (ret != sizeof *mad + mad_length)
 		perror("write");
 
 Setting IsSM Capability Bit
diff --git a/Documentation/kprobes.txt b/Documentation/kprobes.txt
new file mode 100644
index 00000000000..0541fe1de70
--- /dev/null
+++ b/Documentation/kprobes.txt
@@ -0,0 +1,588 @@
+Title	: Kernel Probes (Kprobes)
+Authors	: Jim Keniston <jkenisto@us.ibm.com>
+	: Prasanna S Panchamukhi <prasanna@in.ibm.com>
+
+CONTENTS
+
+1. Concepts: Kprobes, Jprobes, Return Probes
+2. Architectures Supported
+3. Configuring Kprobes
+4. API Reference
+5. Kprobes Features and Limitations
+6. Probe Overhead
+7. TODO
+8. Kprobes Example
+9. Jprobes Example
+10. Kretprobes Example
+
+1. Concepts: Kprobes, Jprobes, Return Probes
+
+Kprobes enables you to dynamically break into any kernel routine and
+collect debugging and performance information non-disruptively. You
+can trap at almost any kernel code address, specifying a handler
+routine to be invoked when the breakpoint is hit.
+
+There are currently three types of probes: kprobes, jprobes, and
+kretprobes (also called return probes).  A kprobe can be inserted
+on virtually any instruction in the kernel.  A jprobe is inserted at
+the entry to a kernel function, and provides convenient access to the
+function's arguments.  A return probe fires when a specified function
+returns.
+
+In the typical case, Kprobes-based instrumentation is packaged as
+a kernel module.  The module's init function installs ("registers")
+one or more probes, and the exit function unregisters them.  A
+registration function such as register_kprobe() specifies where
+the probe is to be inserted and what handler is to be called when
+the probe is hit.
+
+The next three subsections explain how the different types of
+probes work.  They explain certain things that you'll need to
+know in order to make the best use of Kprobes -- e.g., the
+difference between a pre_handler and a post_handler, and how
+to use the maxactive and nmissed fields of a kretprobe.  But
+if you're in a hurry to start using Kprobes, you can skip ahead
+to section 2.
+
+1.1 How Does a Kprobe Work?
+
+When a kprobe is registered, Kprobes makes a copy of the probed
+instruction and replaces the first byte(s) of the probed instruction
+with a breakpoint instruction (e.g., int3 on i386 and x86_64).
+
+When a CPU hits the breakpoint instruction, a trap occurs, the CPU's
+registers are saved, and control passes to Kprobes via the
+notifier_call_chain mechanism.  Kprobes executes the "pre_handler"
+associated with the kprobe, passing the handler the addresses of the
+kprobe struct and the saved registers.
+
+Next, Kprobes single-steps its copy of the probed instruction.
+(It would be simpler to single-step the actual instruction in place,
+but then Kprobes would have to temporarily remove the breakpoint
+instruction.  This would open a small time window when another CPU
+could sail right past the probepoint.)
+
+After the instruction is single-stepped, Kprobes executes the
+"post_handler," if any, that is associated with the kprobe.
+Execution then continues with the instruction following the probepoint.
+
+1.2 How Does a Jprobe Work?
+
+A jprobe is implemented using a kprobe that is placed on a function's
+entry point.  It employs a simple mirroring principle to allow
+seamless access to the probed function's arguments.  The jprobe
+handler routine should have the same signature (arg list and return
+type) as the function being probed, and must always end by calling
+the Kprobes function jprobe_return().
+
+Here's how it works.  When the probe is hit, Kprobes makes a copy of
+the saved registers and a generous portion of the stack (see below).
+Kprobes then points the saved instruction pointer at the jprobe's
+handler routine, and returns from the trap.  As a result, control
+passes to the handler, which is presented with the same register and
+stack contents as the probed function.  When it is done, the handler
+calls jprobe_return(), which traps again to restore the original stack
+contents and processor state and switch to the probed function.
+
+By convention, the callee owns its arguments, so gcc may produce code
+that unexpectedly modifies that portion of the stack.  This is why
+Kprobes saves a copy of the stack and restores it after the jprobe
+handler has run.  Up to MAX_STACK_SIZE bytes are copied -- e.g.,
+64 bytes on i386.
+
+Note that the probed function's args may be passed on the stack
+or in registers (e.g., for x86_64 or for an i386 fastcall function).
+The jprobe will work in either case, so long as the handler's
+prototype matches that of the probed function.
+
+1.3 How Does a Return Probe Work?
+
+When you call register_kretprobe(), Kprobes establishes a kprobe at
+the entry to the function.  When the probed function is called and this
+probe is hit, Kprobes saves a copy of the return address, and replaces
+the return address with the address of a "trampoline."  The trampoline
+is an arbitrary piece of code -- typically just a nop instruction.
+At boot time, Kprobes registers a kprobe at the trampoline.
+
+When the probed function executes its return instruction, control
+passes to the trampoline and that probe is hit.  Kprobes' trampoline
+handler calls the user-specified handler associated with the kretprobe,
+then sets the saved instruction pointer to the saved return address,
+and that's where execution resumes upon return from the trap.
+
+While the probed function is executing, its return address is
+stored in an object of type kretprobe_instance.  Before calling
+register_kretprobe(), the user sets the maxactive field of the
+kretprobe struct to specify how many instances of the specified
+function can be probed simultaneously.  register_kretprobe()
+pre-allocates the indicated number of kretprobe_instance objects.
+
+For example, if the function is non-recursive and is called with a
+spinlock held, maxactive = 1 should be enough.  If the function is
+non-recursive and can never relinquish the CPU (e.g., via a semaphore
+or preemption), NR_CPUS should be enough.  If maxactive <= 0, it is
+set to a default value.  If CONFIG_PREEMPT is enabled, the default
+is max(10, 2*NR_CPUS).  Otherwise, the default is NR_CPUS.
+
+It's not a disaster if you set maxactive too low; you'll just miss
+some probes.  In the kretprobe struct, the nmissed field is set to
+zero when the return probe is registered, and is incremented every
+time the probed function is entered but there is no kretprobe_instance
+object available for establishing the return probe.
+
+2. Architectures Supported
+
+Kprobes, jprobes, and return probes are implemented on the following
+architectures:
+
+- i386
+- x86_64 (AMD-64, E64MT)
+- ppc64
+- ia64 (Support for probes on certain instruction types is still in progress.)
+- sparc64 (Return probes not yet implemented.)
+
+3. Configuring Kprobes
+
+When configuring the kernel using make menuconfig/xconfig/oldconfig,
+ensure that CONFIG_KPROBES is set to "y".  Under "Kernel hacking",
+look for "Kprobes".  You may have to enable "Kernel debugging"
+(CONFIG_DEBUG_KERNEL) before you can enable Kprobes.
+
+You may also want to ensure that CONFIG_KALLSYMS and perhaps even
+CONFIG_KALLSYMS_ALL are set to "y", since kallsyms_lookup_name()
+is a handy, version-independent way to find a function's address.
+
+If you need to insert a probe in the middle of a function, you may find
+it useful to "Compile the kernel with debug info" (CONFIG_DEBUG_INFO),
+so you can use "objdump -d -l vmlinux" to see the source-to-object
+code mapping.
+
+4. API Reference
+
+The Kprobes API includes a "register" function and an "unregister"
+function for each type of probe.  Here are terse, mini-man-page
+specifications for these functions and the associated probe handlers
+that you'll write.  See the latter half of this document for examples.
+
+4.1 register_kprobe
+
+#include <linux/kprobes.h>
+int register_kprobe(struct kprobe *kp);
+
+Sets a breakpoint at the address kp->addr.  When the breakpoint is
+hit, Kprobes calls kp->pre_handler.  After the probed instruction
+is single-stepped, Kprobe calls kp->post_handler.  If a fault
+occurs during execution of kp->pre_handler or kp->post_handler,
+or during single-stepping of the probed instruction, Kprobes calls
+kp->fault_handler.  Any or all handlers can be NULL.
+
+register_kprobe() returns 0 on success, or a negative errno otherwise.
+
+User's pre-handler (kp->pre_handler):
+#include <linux/kprobes.h>
+#include <linux/ptrace.h>
+int pre_handler(struct kprobe *p, struct pt_regs *regs);
+
+Called with p pointing to the kprobe associated with the breakpoint,
+and regs pointing to the struct containing the registers saved when
+the breakpoint was hit.  Return 0 here unless you're a Kprobes geek.
+
+User's post-handler (kp->post_handler):
+#include <linux/kprobes.h>
+#include <linux/ptrace.h>
+void post_handler(struct kprobe *p, struct pt_regs *regs,
+	unsigned long flags);
+
+p and regs are as described for the pre_handler.  flags always seems
+to be zero.
+
+User's fault-handler (kp->fault_handler):
+#include <linux/kprobes.h>
+#include <linux/ptrace.h>
+int fault_handler(struct kprobe *p, struct pt_regs *regs, int trapnr);
+
+p and regs are as described for the pre_handler.  trapnr is the
+architecture-specific trap number associated with the fault (e.g.,
+on i386, 13 for a general protection fault or 14 for a page fault).
+Returns 1 if it successfully handled the exception.
+
+4.2 register_jprobe
+
+#include <linux/kprobes.h>
+int register_jprobe(struct jprobe *jp)
+
+Sets a breakpoint at the address jp->kp.addr, which must be the address
+of the first instruction of a function.  When the breakpoint is hit,
+Kprobes runs the handler whose address is jp->entry.
+
+The handler should have the same arg list and return type as the probed
+function; and just before it returns, it must call jprobe_return().
+(The handler never actually returns, since jprobe_return() returns
+control to Kprobes.)  If the probed function is declared asmlinkage,
+fastcall, or anything else that affects how args are passed, the
+handler's declaration must match.
+
+register_jprobe() returns 0 on success, or a negative errno otherwise.
+
+4.3 register_kretprobe
+
+#include <linux/kprobes.h>
+int register_kretprobe(struct kretprobe *rp);
+
+Establishes a return probe for the function whose address is
+rp->kp.addr.  When that function returns, Kprobes calls rp->handler.
+You must set rp->maxactive appropriately before you call
+register_kretprobe(); see "How Does a Return Probe Work?" for details.
+
+register_kretprobe() returns 0 on success, or a negative errno
+otherwise.
+
+User's return-probe handler (rp->handler):
+#include <linux/kprobes.h>
+#include <linux/ptrace.h>
+int kretprobe_handler(struct kretprobe_instance *ri, struct pt_regs *regs);
+
+regs is as described for kprobe.pre_handler.  ri points to the
+kretprobe_instance object, of which the following fields may be
+of interest:
+- ret_addr: the return address
+- rp: points to the corresponding kretprobe object
+- task: points to the corresponding task struct
+The handler's return value is currently ignored.
+
+4.4 unregister_*probe
+
+#include <linux/kprobes.h>
+void unregister_kprobe(struct kprobe *kp);
+void unregister_jprobe(struct jprobe *jp);
+void unregister_kretprobe(struct kretprobe *rp);
+
+Removes the specified probe.  The unregister function can be called
+at any time after the probe has been registered.
+
+5. Kprobes Features and Limitations
+
+As of Linux v2.6.12, Kprobes allows multiple probes at the same
+address.  Currently, however, there cannot be multiple jprobes on
+the same function at the same time.
+
+In general, you can install a probe anywhere in the kernel.
+In particular, you can probe interrupt handlers.  Known exceptions
+are discussed in this section.
+
+For obvious reasons, it's a bad idea to install a probe in
+the code that implements Kprobes (mostly kernel/kprobes.c and
+arch/*/kernel/kprobes.c).  A patch in the v2.6.13 timeframe instructs
+Kprobes to reject such requests.
+
+If you install a probe in an inline-able function, Kprobes makes
+no attempt to chase down all inline instances of the function and
+install probes there.  gcc may inline a function without being asked,
+so keep this in mind if you're not seeing the probe hits you expect.
+
+A probe handler can modify the environment of the probed function
+-- e.g., by modifying kernel data structures, or by modifying the
+contents of the pt_regs struct (which are restored to the registers
+upon return from the breakpoint).  So Kprobes can be used, for example,
+to install a bug fix or to inject faults for testing.  Kprobes, of
+course, has no way to distinguish the deliberately injected faults
+from the accidental ones.  Don't drink and probe.
+
+Kprobes makes no attempt to prevent probe handlers from stepping on
+each other -- e.g., probing printk() and then calling printk() from a
+probe handler.  As of Linux v2.6.12, if a probe handler hits a probe,
+that second probe's handlers won't be run in that instance.
+
+In Linux v2.6.12 and previous versions, Kprobes' data structures are
+protected by a single lock that is held during probe registration and
+unregistration and while handlers are run.  Thus, no two handlers
+can run simultaneously.  To improve scalability on SMP systems,
+this restriction will probably be removed soon, in which case
+multiple handlers (or multiple instances of the same handler) may
+run concurrently on different CPUs.  Code your handlers accordingly.
+
+Kprobes does not use semaphores or allocate memory except during
+registration and unregistration.
+
+Probe handlers are run with preemption disabled.  Depending on the
+architecture, handlers may also run with interrupts disabled.  In any
+case, your handler should not yield the CPU (e.g., by attempting to
+acquire a semaphore).
+
+Since a return probe is implemented by replacing the return
+address with the trampoline's address, stack backtraces and calls
+to __builtin_return_address() will typically yield the trampoline's
+address instead of the real return address for kretprobed functions.
+(As far as we can tell, __builtin_return_address() is used only
+for instrumentation and error reporting.)
+
+If the number of times a function is called does not match the
+number of times it returns, registering a return probe on that
+function may produce undesirable results.  We have the do_exit()
+and do_execve() cases covered.  do_fork() is not an issue.  We're
+unaware of other specific cases where this could be a problem.
+
+6. Probe Overhead
+
+On a typical CPU in use in 2005, a kprobe hit takes 0.5 to 1.0
+microseconds to process.  Specifically, a benchmark that hits the same
+probepoint repeatedly, firing a simple handler each time, reports 1-2
+million hits per second, depending on the architecture.  A jprobe or
+return-probe hit typically takes 50-75% longer than a kprobe hit.
+When you have a return probe set on a function, adding a kprobe at
+the entry to that function adds essentially no overhead.
+
+Here are sample overhead figures (in usec) for different architectures.
+k = kprobe; j = jprobe; r = return probe; kr = kprobe + return probe
+on same function; jr = jprobe + return probe on same function
+
+i386: Intel Pentium M, 1495 MHz, 2957.31 bogomips
+k = 0.57 usec; j = 1.00; r = 0.92; kr = 0.99; jr = 1.40
+
+x86_64: AMD Opteron 246, 1994 MHz, 3971.48 bogomips
+k = 0.49 usec; j = 0.76; r = 0.80; kr = 0.82; jr = 1.07
+
+ppc64: POWER5 (gr), 1656 MHz (SMT disabled, 1 virtual CPU per physical CPU)
+k = 0.77 usec; j = 1.31; r = 1.26; kr = 1.45; jr = 1.99
+
+7. TODO
+
+a. SystemTap (http://sourceware.org/systemtap): Work in progress
+to provide a simplified programming interface for probe-based
+instrumentation.
+b. Improved SMP scalability: Currently, work is in progress to handle
+multiple kprobes in parallel.
+c. Kernel return probes for sparc64.
+d. Support for other architectures.
+e. User-space probes.
+
+8. Kprobes Example
+
+Here's a sample kernel module showing the use of kprobes to dump a
+stack trace and selected i386 registers when do_fork() is called.
+----- cut here -----
+/*kprobe_example.c*/
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/kprobes.h>
+#include <linux/kallsyms.h>
+#include <linux/sched.h>
+
+/*For each probe you need to allocate a kprobe structure*/
+static struct kprobe kp;
+
+/*kprobe pre_handler: called just before the probed instruction is executed*/
+int handler_pre(struct kprobe *p, struct pt_regs *regs)
+{
+	printk("pre_handler: p->addr=0x%p, eip=%lx, eflags=0x%lx\n",
+		p->addr, regs->eip, regs->eflags);
+	dump_stack();
+	return 0;
+}
+
+/*kprobe post_handler: called after the probed instruction is executed*/
+void handler_post(struct kprobe *p, struct pt_regs *regs, unsigned long flags)
+{
+	printk("post_handler: p->addr=0x%p, eflags=0x%lx\n",
+		p->addr, regs->eflags);
+}
+
+/* fault_handler: this is called if an exception is generated for any
+ * instruction within the pre- or post-handler, or when Kprobes
+ * single-steps the probed instruction.
+ */
+int handler_fault(struct kprobe *p, struct pt_regs *regs, int trapnr)
+{
+	printk("fault_handler: p->addr=0x%p, trap #%dn",
+		p->addr, trapnr);
+	/* Return 0 because we don't handle the fault. */
+	return 0;
+}
+
+int init_module(void)
+{
+	int ret;
+	kp.pre_handler = handler_pre;
+	kp.post_handler = handler_post;
+	kp.fault_handler = handler_fault;
+	kp.addr = (kprobe_opcode_t*) kallsyms_lookup_name("do_fork");
+	/* register the kprobe now */
+	if (!kp.addr) {
+		printk("Couldn't find %s to plant kprobe\n", "do_fork");
+		return -1;
+	}
+	if ((ret = register_kprobe(&kp) < 0)) {
+		printk("register_kprobe failed, returned %d\n", ret);
+		return -1;
+	}
+	printk("kprobe registered\n");
+	return 0;
+}
+
+void cleanup_module(void)
+{
+	unregister_kprobe(&kp);
+	printk("kprobe unregistered\n");
+}
+
+MODULE_LICENSE("GPL");
+----- cut here -----
+
+You can build the kernel module, kprobe-example.ko, using the following
+Makefile:
+----- cut here -----
+obj-m := kprobe-example.o
+KDIR := /lib/modules/$(shell uname -r)/build
+PWD := $(shell pwd)
+default:
+	$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules
+clean:
+	rm -f *.mod.c *.ko *.o
+----- cut here -----
+
+$ make
+$ su -
+...
+# insmod kprobe-example.ko
+
+You will see the trace data in /var/log/messages and on the console
+whenever do_fork() is invoked to create a new process.
+
+9. Jprobes Example
+
+Here's a sample kernel module showing the use of jprobes to dump
+the arguments of do_fork().
+----- cut here -----
+/*jprobe-example.c */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/uio.h>
+#include <linux/kprobes.h>
+#include <linux/kallsyms.h>
+
+/*
+ * Jumper probe for do_fork.
+ * Mirror principle enables access to arguments of the probed routine
+ * from the probe handler.
+ */
+
+/* Proxy routine having the same arguments as actual do_fork() routine */
+long jdo_fork(unsigned long clone_flags, unsigned long stack_start,
+	      struct pt_regs *regs, unsigned long stack_size,
+	      int __user * parent_tidptr, int __user * child_tidptr)
+{
+	printk("jprobe: clone_flags=0x%lx, stack_size=0x%lx, regs=0x%p\n",
+	       clone_flags, stack_size, regs);
+	/* Always end with a call to jprobe_return(). */
+	jprobe_return();
+	/*NOTREACHED*/
+	return 0;
+}
+
+static struct jprobe my_jprobe = {
+	.entry = (kprobe_opcode_t *) jdo_fork
+};
+
+int init_module(void)
+{
+	int ret;
+	my_jprobe.kp.addr = (kprobe_opcode_t *) kallsyms_lookup_name("do_fork");
+	if (!my_jprobe.kp.addr) {
+		printk("Couldn't find %s to plant jprobe\n", "do_fork");
+		return -1;
+	}
+
+	if ((ret = register_jprobe(&my_jprobe)) <0) {
+		printk("register_jprobe failed, returned %d\n", ret);
+		return -1;
+	}
+	printk("Planted jprobe at %p, handler addr %p\n",
+	       my_jprobe.kp.addr, my_jprobe.entry);
+	return 0;
+}
+
+void cleanup_module(void)
+{
+	unregister_jprobe(&my_jprobe);
+	printk("jprobe unregistered\n");
+}
+
+MODULE_LICENSE("GPL");
+----- cut here -----
+
+Build and insert the kernel module as shown in the above kprobe
+example.  You will see the trace data in /var/log/messages and on
+the console whenever do_fork() is invoked to create a new process.
+(Some messages may be suppressed if syslogd is configured to
+eliminate duplicate messages.)
+
+10. Kretprobes Example
+
+Here's a sample kernel module showing the use of return probes to
+report failed calls to sys_open().
+----- cut here -----
+/*kretprobe-example.c*/
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/kprobes.h>
+#include <linux/kallsyms.h>
+
+static const char *probed_func = "sys_open";
+
+/* Return-probe handler: If the probed function fails, log the return value. */
+static int ret_handler(struct kretprobe_instance *ri, struct pt_regs *regs)
+{
+	// Substitute the appropriate register name for your architecture --
+	// e.g., regs->rax for x86_64, regs->gpr[3] for ppc64.
+	int retval = (int) regs->eax;
+	if (retval < 0) {
+		printk("%s returns %d\n", probed_func, retval);
+	}
+	return 0;
+}
+
+static struct kretprobe my_kretprobe = {
+	.handler = ret_handler,
+	/* Probe up to 20 instances concurrently. */
+	.maxactive = 20
+};
+
+int init_module(void)
+{
+	int ret;
+	my_kretprobe.kp.addr =
+		(kprobe_opcode_t *) kallsyms_lookup_name(probed_func);
+	if (!my_kretprobe.kp.addr) {
+		printk("Couldn't find %s to plant return probe\n", probed_func);
+		return -1;
+	}
+	if ((ret = register_kretprobe(&my_kretprobe)) < 0) {
+		printk("register_kretprobe failed, returned %d\n", ret);
+		return -1;
+	}
+	printk("Planted return probe at %p\n", my_kretprobe.kp.addr);
+	return 0;
+}
+
+void cleanup_module(void)
+{
+	unregister_kretprobe(&my_kretprobe);
+	printk("kretprobe unregistered\n");
+	/* nmissed > 0 suggests that maxactive was set too low. */
+	printk("Missed probing %d instances of %s\n",
+		my_kretprobe.nmissed, probed_func);
+}
+
+MODULE_LICENSE("GPL");
+----- cut here -----
+
+Build and insert the kernel module as shown in the above kprobe
+example.  You will see the trace data in /var/log/messages and on the
+console whenever sys_open() returns a negative value.  (Some messages
+may be suppressed if syslogd is configured to eliminate duplicate
+messages.)
+
+For additional information on Kprobes, refer to the following URLs:
+http://www-106.ibm.com/developerworks/library/l-kprobes.html?ca=dgr-lnxw42Kprobe
+http://www.redhat.com/magazine/005mar05/features/kprobes/
diff --git a/Documentation/networking/bonding.txt b/Documentation/networking/bonding.txt
index 0bc2ed136a3..24d029455ba 100644
--- a/Documentation/networking/bonding.txt
+++ b/Documentation/networking/bonding.txt
@@ -1,5 +1,7 @@
 
-                   Linux Ethernet Bonding Driver HOWTO
+		Linux Ethernet Bonding Driver HOWTO
+
+		Latest update: 21 June 2005
 
 Initial release : Thomas Davis <tadavis at lbl.gov>
 Corrections, HA extensions : 2000/10/03-15 :
@@ -11,15 +13,22 @@ Corrections, HA extensions : 2000/10/03-15 :
 
 Reorganized and updated Feb 2005 by Jay Vosburgh
 
-Note :
-------
+Introduction
+============
+
+	The Linux bonding driver provides a method for aggregating
+multiple network interfaces into a single logical "bonded" interface.
+The behavior of the bonded interfaces depends upon the mode; generally
+speaking, modes provide either hot standby or load balancing services.
+Additionally, link integrity monitoring may be performed.
 	
-The bonding driver originally came from Donald Becker's beowulf patches for
-kernel 2.0. It has changed quite a bit since, and the original tools from
-extreme-linux and beowulf sites will not work with this version of the driver.
+	The bonding driver originally came from Donald Becker's
+beowulf patches for kernel 2.0. It has changed quite a bit since, and
+the original tools from extreme-linux and beowulf sites will not work
+with this version of the driver.
 
-For new versions of the driver, patches for older kernels and the updated
-userspace tools, please follow the links at the end of this file.
+	For new versions of the driver, updated userspace tools, and
+who to ask for help, please follow the links at the end of this file.
 
 Table of Contents
 =================
@@ -30,9 +39,13 @@ Table of Contents
 
 3. Configuring Bonding Devices
 3.1	Configuration with sysconfig support
+3.1.1		Using DHCP with sysconfig
+3.1.2		Configuring Multiple Bonds with sysconfig
 3.2	Configuration with initscripts support
+3.2.1		Using DHCP with initscripts
+3.2.2		Configuring Multiple Bonds with initscripts
 3.3	Configuring Bonding Manually
-3.4	Configuring Multiple Bonds
+3.3.1		Configuring Multiple Bonds Manually
 
 5. Querying Bonding Configuration
 5.1	Bonding Configuration
@@ -56,21 +69,30 @@ Table of Contents
 
 11. Promiscuous mode
 
-12. High Availability Information
+12. Configuring Bonding for High Availability
 12.1	High Availability in a Single Switch Topology
-12.1.1		Bonding Mode Selection for Single Switch Topology
-12.1.2		Link Monitoring for Single Switch Topology
 12.2	High Availability in a Multiple Switch Topology
-12.2.1		Bonding Mode Selection for Multiple Switch Topology
-12.2.2		Link Monitoring for Multiple Switch Topology
-12.3	Switch Behavior Issues for High Availability
+12.2.1		HA Bonding Mode Selection for Multiple Switch Topology
+12.2.2		HA Link Monitoring for Multiple Switch Topology
+
+13. Configuring Bonding for Maximum Throughput
+13.1	Maximum Throughput in a Single Switch Topology
+13.1.1		MT Bonding Mode Selection for Single Switch Topology
+13.1.2		MT Link Monitoring for Single Switch Topology
+13.2	Maximum Throughput in a Multiple Switch Topology
+13.2.1		MT Bonding Mode Selection for Multiple Switch Topology
+13.2.2		MT Link Monitoring for Multiple Switch Topology
 
-13. Hardware Specific Considerations
-13.1	IBM BladeCenter
+14. Switch Behavior Issues
+14.1	Link Establishment and Failover Delays
+14.2	Duplicated Incoming Packets
 
-14. Frequently Asked Questions
+15. Hardware Specific Considerations
+15.1	IBM BladeCenter
 
-15. Resources and Links
+16. Frequently Asked Questions
+
+17. Resources and Links
 
 
 1. Bonding Driver Installation
@@ -86,16 +108,10 @@ the following steps:
 1.1 Configure and build the kernel with bonding
 -----------------------------------------------
 
-	The latest version of the bonding driver is available in the
+	The current version of the bonding driver is available in the
 drivers/net/bonding subdirectory of the most recent kernel source
-(which is available on http://kernel.org).
-
-	Prior to the 2.4.11 kernel, the bonding driver was maintained
-largely outside the kernel tree; patches for some earlier kernels are
-available on the bonding sourceforge site, although those patches are
-still several years out of date.  Most users will want to use either
-the most recent kernel from kernel.org or whatever kernel came with
-their distro.
+(which is available on http://kernel.org).  Most users "rolling their
+own" will want to use the most recent kernel from kernel.org.
 
 	Configure kernel with "make menuconfig" (or "make xconfig" or
 "make config"), then select "Bonding driver support" in the "Network
@@ -103,8 +119,8 @@ device support" section.  It is recommended that you configure the
 driver as module since it is currently the only way to pass parameters
 to the driver or configure more than one bonding device.
 
-	Build and install the new kernel and modules, then proceed to
-step 2.
+	Build and install the new kernel and modules, then continue
+below to install ifenslave.
 
 1.2 Install ifenslave Control Utility
 -------------------------------------
@@ -147,9 +163,9 @@ default kernel source include directory.
 	Options for the bonding driver are supplied as parameters to
 the bonding module at load time.  They may be given as command line
 arguments to the insmod or modprobe command, but are usually specified
-in either the /etc/modprobe.conf configuration file, or in a
-distro-specific configuration file (some of which are detailed in the
-next section).
+in either the /etc/modules.conf or /etc/modprobe.conf configuration
+file, or in a distro-specific configuration file (some of which are
+detailed in the next section).
 
 	The available bonding driver parameters are listed below. If a
 parameter is not specified the default value is used.  When initially
@@ -162,34 +178,34 @@ degradation will occur during link failures.  Very few devices do not
 support at least miimon, so there is really no reason not to use it.
 
 	Options with textual values will accept either the text name
-	or, for backwards compatibility, the option value.  E.g.,
-	"mode=802.3ad" and "mode=4" set the same mode.
+or, for backwards compatibility, the option value.  E.g.,
+"mode=802.3ad" and "mode=4" set the same mode.
 
 	The parameters are as follows:
 
 arp_interval
 
-	Specifies the ARP monitoring frequency in milli-seconds. If
-	ARP monitoring is used in a load-balancing mode (mode 0 or 2),
-	the switch should be configured in a mode that evenly
-	distributes packets across all links - such as round-robin. If
-	the switch is configured to distribute the packets in an XOR
+	Specifies the ARP link monitoring frequency in milliseconds.
+	If ARP monitoring is used in an etherchannel compatible mode
+	(modes 0 and 2), the switch should be configured in a mode
+	that evenly distributes packets across all links. If the
+	switch is configured to distribute the packets in an XOR
 	fashion, all replies from the ARP targets will be received on
 	the same link which could cause the other team members to
-	fail. ARP monitoring should not be used in conjunction with
-	miimon. A value of 0 disables ARP monitoring. The default
+	fail.  ARP monitoring should not be used in conjunction with
+	miimon.  A value of 0 disables ARP monitoring.  The default
 	value is 0.
 
 arp_ip_target
 
-	Specifies the ip addresses to use when arp_interval is > 0.
-	These are the targets of the ARP request sent to determine the
-	health of the link to the targets.  Specify these values in
-	ddd.ddd.ddd.ddd format.  Multiple ip adresses must be
-	seperated by a comma.  At least one IP address must be given
-	for ARP monitoring to function.  The maximum number of targets
-	that can be specified is 16.  The default value is no IP
-	addresses.
+	Specifies the IP addresses to use as ARP monitoring peers when
+	arp_interval is > 0.  These are the targets of the ARP request
+	sent to determine the health of the link to the targets.
+	Specify these values in ddd.ddd.ddd.ddd format.  Multiple IP
+	addresses must be separated by a comma.  At least one IP
+	address must be given for ARP monitoring to function.  The
+	maximum number of targets that can be specified is 16.  The
+	default value is no IP addresses.
 
 downdelay
 
@@ -207,11 +223,13 @@ lacp_rate
 	are:
 
 	slow or 0
-		Request partner to transmit LACPDUs every 30 seconds (default)
+		Request partner to transmit LACPDUs every 30 seconds
 
 	fast or 1
 		Request partner to transmit LACPDUs every 1 second
 
+	The default is slow.
+
 max_bonds
 
 	Specifies the number of bonding devices to create for this
@@ -221,10 +239,11 @@ max_bonds
 
 miimon
 
-	Specifies the frequency in milli-seconds that MII link
-	monitoring will occur.  A value of zero disables MII link
-	monitoring.  A value of 100 is a good starting point.  The
-	use_carrier option, below, affects how the link state is
+	Specifies the MII link monitoring frequency in milliseconds.
+	This determines how often the link state of each slave is
+	inspected for link failures.  A value of zero disables MII
+	link monitoring.  A value of 100 is a good starting point.
+	The use_carrier option, below, affects how the link state is
 	determined.  See the High Availability section for additional
 	information.  The default value is 0.
 
@@ -246,17 +265,31 @@ mode
 		active.  A different slave becomes active if, and only
 		if, the active slave fails.  The bond's MAC address is
 		externally visible on only one port (network adapter)
-		to avoid confusing the switch.  This mode provides
-		fault tolerance.  The primary option affects the
-		behavior of this mode.
+		to avoid confusing the switch.
+
+		In bonding version 2.6.2 or later, when a failover
+		occurs in active-backup mode, bonding will issue one
+		or more gratuitous ARPs on the newly active slave.
+		One gratutious ARP is issued for the bonding master
+		interface and each VLAN interfaces configured above
+		it, provided that the interface has at least one IP
+		address configured.  Gratuitous ARPs issued for VLAN
+		interfaces are tagged with the appropriate VLAN id.
+
+		This mode provides fault tolerance.  The primary
+		option, documented below, affects the behavior of this
+		mode.
 
 	balance-xor or 2
 
-		XOR policy: Transmit based on [(source MAC address
-		XOR'd with destination MAC address) modulo slave
-		count].  This selects the same slave for each
-		destination MAC address.  This mode provides load
-		balancing and fault tolerance.
+		XOR policy: Transmit based on the selected transmit
+		hash policy.  The default policy is a simple [(source
+		MAC address XOR'd with destination MAC address) modulo
+		slave count].  Alternate transmit policies may be
+		selected via the xmit_hash_policy option, described
+		below.
+
+		This mode provides load balancing and fault tolerance.
 
 	broadcast or 3
 
@@ -270,7 +303,17 @@ mode
 		duplex settings.  Utilizes all slaves in the active
 		aggregator according to the 802.3ad specification.
 
-		Pre-requisites:
+		Slave selection for outgoing traffic is done according
+		to the transmit hash policy, which may be changed from
+		the default simple XOR policy via the xmit_hash_policy
+		option, documented below.  Note that not all transmit
+		policies may be 802.3ad compliant, particularly in
+		regards to the packet mis-ordering requirements of
+		section 43.2.4 of the 802.3ad standard.  Differing
+		peer implementations will have varying tolerances for
+		noncompliance.
+
+		Prerequisites:
 
 		1. Ethtool support in the base drivers for retrieving
 		the speed and duplex of each slave.
@@ -333,7 +376,7 @@ mode
 
 		When a link is reconnected or a new slave joins the
 		bond the receive traffic is redistributed among all
-		active slaves in the bond by intiating ARP Replies
+		active slaves in the bond by initiating ARP Replies
 		with the selected mac address to each of the
 		clients. The updelay parameter (detailed below) must
 		be set to a value equal or greater than the switch's
@@ -396,6 +439,60 @@ use_carrier
 	0 will use the deprecated MII / ETHTOOL ioctls.  The default
 	value is 1.
 
+xmit_hash_policy
+
+	Selects the transmit hash policy to use for slave selection in
+	balance-xor and 802.3ad modes.  Possible values are:
+
+	layer2
+
+		Uses XOR of hardware MAC addresses to generate the
+		hash.  The formula is
+
+		(source MAC XOR destination MAC) modulo slave count
+
+		This algorithm will place all traffic to a particular
+		network peer on the same slave.
+
+		This algorithm is 802.3ad compliant.
+
+	layer3+4
+
+		This policy uses upper layer protocol information,
+		when available, to generate the hash.  This allows for
+		traffic to a particular network peer to span multiple
+		slaves, although a single connection will not span
+		multiple slaves.
+
+		The formula for unfragmented TCP and UDP packets is
+
+		((source port XOR dest port) XOR
+			 ((source IP XOR dest IP) AND 0xffff)
+				modulo slave count
+
+		For fragmented TCP or UDP packets and all other IP
+		protocol traffic, the source and destination port
+		information is omitted.  For non-IP traffic, the
+		formula is the same as for the layer2 transmit hash
+		policy.
+
+		This policy is intended to mimic the behavior of
+		certain switches, notably Cisco switches with PFC2 as
+		well as some Foundry and IBM products.
+
+		This algorithm is not fully 802.3ad compliant.  A
+		single TCP or UDP conversation containing both
+		fragmented and unfragmented packets will see packets
+		striped across two interfaces.  This may result in out
+		of order delivery.  Most traffic types will not meet
+		this criteria, as TCP rarely fragments traffic, and
+		most UDP traffic is not involved in extended
+		conversations.  Other implementations of 802.3ad may
+		or may not tolerate this noncompliance.
+
+	The default value is layer2.  This option was added in bonding
+version 2.6.3.  In earlier versions of bonding, this parameter does
+not exist, and the layer2 policy is the only policy.
 
 
 3. Configuring Bonding Devices
@@ -448,8 +545,9 @@ Bonding devices can be managed by hand, however, as follows.
 slave devices.  On SLES 9, this is most easily done by running the
 yast2 sysconfig configuration utility.  The goal is for to create an
 ifcfg-id file for each slave device.  The simplest way to accomplish
-this is to configure the devices for DHCP.  The name of the
-configuration file for each device will be of the form:
+this is to configure the devices for DHCP (this is only to get the
+file ifcfg-id file created; see below for some issues with DHCP).  The
+name of the configuration file for each device will be of the form:
 
 ifcfg-id-xx:xx:xx:xx:xx:xx
 
@@ -459,7 +557,7 @@ the device's permanent MAC address.
 	Once the set of ifcfg-id-xx:xx:xx:xx:xx:xx files has been
 created, it is necessary to edit the configuration files for the slave
 devices (the MAC addresses correspond to those of the slave devices).
-Before editing, the file will contain muliple lines, and will look
+Before editing, the file will contain multiple lines, and will look
 something like this:
 
 BOOTPROTO='dhcp'
@@ -496,16 +594,11 @@ STARTMODE="onboot"
 BONDING_MASTER="yes"
 BONDING_MODULE_OPTS="mode=active-backup miimon=100"
 BONDING_SLAVE0="eth0"
-BONDING_SLAVE1="eth1"
+BONDING_SLAVE1="bus-pci-0000:06:08.1"
 
 	Replace the sample BROADCAST, IPADDR, NETMASK and NETWORK
 values with the appropriate values for your network.
 
-	Note that configuring the bonding device with BOOTPROTO='dhcp'
-does not work; the scripts attempt to obtain the device address from
-DHCP prior to adding any of the slave devices.  Without active slaves,
-the DHCP requests are not sent to the network.
-
 	The STARTMODE specifies when the device is brought online.
 The possible values are:
 
@@ -531,9 +624,17 @@ for the bonding mode, link monitoring, and so on here.  Do not include
 the max_bonds bonding parameter; this will confuse the configuration
 system if you have multiple bonding devices.
 
-	Finally, supply one BONDING_SLAVEn="ethX" for each slave,
-where "n" is an increasing value, one for each slave, and "ethX" is
-the name of the slave device (eth0, eth1, etc).
+	Finally, supply one BONDING_SLAVEn="slave device" for each
+slave.  where "n" is an increasing value, one for each slave.  The
+"slave device" is either an interface name, e.g., "eth0", or a device
+specifier for the network device.  The interface name is easier to
+find, but the ethN names are subject to change at boot time if, e.g.,
+a device early in the sequence has failed.  The device specifiers
+(bus-pci-0000:06:08.1 in the example above) specify the physical
+network device, and will not change unless the device's bus location
+changes (for example, it is moved from one PCI slot to another).  The
+example above uses one of each type for demonstration purposes; most
+configurations will choose one or the other for all slave devices.
 
 	When all configuration files have been modified or created,
 networking must be restarted for the configuration changes to take
@@ -544,7 +645,7 @@ effect.  This can be accomplished via the following:
 	Note that the network control script (/sbin/ifdown) will
 remove the bonding module as part of the network shutdown processing,
 so it is not necessary to remove the module by hand if, e.g., the
-module paramters have changed.
+module parameters have changed.
 
 	Also, at this writing, YaST/YaST2 will not manage bonding
 devices (they do not show bonding interfaces on its list of network
@@ -559,12 +660,37 @@ format can be found in an example ifcfg template file:
 	Note that the template does not document the various BONDING_
 settings described above, but does describe many of the other options.
 
+3.1.1 Using DHCP with sysconfig
+-------------------------------
+
+	Under sysconfig, configuring a device with BOOTPROTO='dhcp'
+will cause it to query DHCP for its IP address information.  At this
+writing, this does not function for bonding devices; the scripts
+attempt to obtain the device address from DHCP prior to adding any of
+the slave devices.  Without active slaves, the DHCP requests are not
+sent to the network.
+
+3.1.2 Configuring Multiple Bonds with sysconfig
+-----------------------------------------------
+
+	The sysconfig network initialization system is capable of
+handling multiple bonding devices.  All that is necessary is for each
+bonding instance to have an appropriately configured ifcfg-bondX file
+(as described above).  Do not specify the "max_bonds" parameter to any
+instance of bonding, as this will confuse sysconfig.  If you require
+multiple bonding devices with identical parameters, create multiple
+ifcfg-bondX files.
+
+	Because the sysconfig scripts supply the bonding module
+options in the ifcfg-bondX file, it is not necessary to add them to
+the system /etc/modules.conf or /etc/modprobe.conf configuration file.
+
 3.2 Configuration with initscripts support
 ------------------------------------------
 
 	This section applies to distros using a version of initscripts
 with bonding support, for example, Red Hat Linux 9 or Red Hat
-Enterprise Linux version 3.  On these systems, the network
+Enterprise Linux version 3 or 4.  On these systems, the network
 initialization scripts have some knowledge of bonding, and can be
 configured to control bonding devices.
 
@@ -614,10 +740,11 @@ USERCTL=no
 	Be sure to change the networking specific lines (IPADDR,
 NETMASK, NETWORK and BROADCAST) to match your network configuration.
 
-	Finally, it is necessary to edit /etc/modules.conf to load the
-bonding module when the bond0 interface is brought up.  The following
-sample lines in /etc/modules.conf will load the bonding module, and
-select its options:
+	Finally, it is necessary to edit /etc/modules.conf (or
+/etc/modprobe.conf, depending upon your distro) to load the bonding
+module with your desired options when the bond0 interface is brought
+up.  The following lines in /etc/modules.conf (or modprobe.conf) will
+load the bonding module, and select its options:
 
 alias bond0 bonding
 options bond0 mode=balance-alb miimon=100
@@ -629,6 +756,33 @@ options for your configuration.
 will restart the networking subsystem and your bond link should be now
 up and running.
 
+3.2.1 Using DHCP with initscripts
+---------------------------------
+
+	Recent versions of initscripts (the version supplied with
+Fedora Core 3 and Red Hat Enterprise Linux 4 is reported to work) do
+have support for assigning IP information to bonding devices via DHCP.
+
+	To configure bonding for DHCP, configure it as described
+above, except replace the line "BOOTPROTO=none" with "BOOTPROTO=dhcp"
+and add a line consisting of "TYPE=Bonding".  Note that the TYPE value
+is case sensitive.
+
+3.2.2 Configuring Multiple Bonds with initscripts
+-------------------------------------------------
+
+	At this writing, the initscripts package does not directly
+support loading the bonding driver multiple times, so the process for
+doing so is the same as described in the "Configuring Multiple Bonds
+Manually" section, below.
+
+	NOTE: It has been observed that some Red Hat supplied kernels
+are apparently unable to rename modules at load time (the "-obonding1"
+part).  Attempts to pass that option to modprobe will produce an
+"Operation not permitted" error.  This has been reported on some
+Fedora Core kernels, and has been seen on RHEL 4 as well.  On kernels
+exhibiting this problem, it will be impossible to configure multiple
+bonds with differing parameters.
 
 3.3 Configuring Bonding Manually
 --------------------------------
@@ -638,10 +792,11 @@ scripts (the sysconfig or initscripts package) do not have specific
 knowledge of bonding.  One such distro is SuSE Linux Enterprise Server
 version 8.
 
-	The general methodology for these systems is to place the
-bonding module parameters into /etc/modprobe.conf, then add modprobe
-and/or ifenslave commands to the system's global init script.  The
-name of the global init script differs; for sysconfig, it is
+	The general method for these systems is to place the bonding
+module parameters into /etc/modules.conf or /etc/modprobe.conf (as
+appropriate for the installed distro), then add modprobe and/or
+ifenslave commands to the system's global init script.  The name of
+the global init script differs; for sysconfig, it is
 /etc/init.d/boot.local and for initscripts it is /etc/rc.d/rc.local.
 
 	For example, if you wanted to make a simple bond of two e100
@@ -649,7 +804,7 @@ devices (presumed to be eth0 and eth1), and have it persist across
 reboots, edit the appropriate file (/etc/init.d/boot.local or
 /etc/rc.d/rc.local), and add the following:
 
-modprobe bonding -obond0 mode=balance-alb miimon=100
+modprobe bonding mode=balance-alb miimon=100
 modprobe e100
 ifconfig bond0 192.168.1.1 netmask 255.255.255.0 up
 ifenslave bond0 eth0
@@ -657,11 +812,7 @@ ifenslave bond0 eth1
 
 	Replace the example bonding module parameters and bond0
 network configuration (IP address, netmask, etc) with the appropriate
-values for your configuration.  The above example loads the bonding
-module with the name "bond0," this simplifies the naming if multiple
-bonding modules are loaded (each successive instance of the module is
-given a different name, and the module instance names match the
-bonding interface names).
+values for your configuration.
 
 	Unfortunately, this method will not provide support for the
 ifup and ifdown scripts on the bond devices.  To reload the bonding
@@ -684,20 +835,23 @@ appropriate device driver modules.  For our example above, you can do
 the following:
 
 # ifconfig bond0 down
-# rmmod bond0
+# rmmod bonding
 # rmmod e100
 
 	Again, for convenience, it may be desirable to create a script
 with these commands.
 
 
-3.4 Configuring Multiple Bonds
-------------------------------
+3.3.1 Configuring Multiple Bonds Manually
+-----------------------------------------
 
 	This section contains information on configuring multiple
-bonding devices with differing options.  If you require multiple
-bonding devices, but all with the same options, see the "max_bonds"
-module paramter, documented above.
+bonding devices with differing options for those systems whose network
+initialization scripts lack support for configuring multiple bonds.
+
+	If you require multiple bonding devices, but all with the same
+options, you may wish to use the "max_bonds" module parameter,
+documented above.
 
 	To create multiple bonding devices with differing options, it
 is necessary to load the bonding driver multiple times.  Note that
@@ -724,11 +878,16 @@ named "bond0" and creates the bond0 device in balance-rr mode with an
 miimon of 100.  The second instance is named "bond1" and creates the
 bond1 device in balance-alb mode with an miimon of 50.
 
+	In some circumstances (typically with older distributions),
+the above does not work, and the second bonding instance never sees
+its options.  In that case, the second options line can be substituted
+as follows:
+
+install bonding1 /sbin/modprobe bonding -obond1 mode=balance-alb miimon=50
+
 	This may be repeated any number of times, specifying a new and
-unique name in place of bond0 or bond1 for each instance.
+unique name in place of bond1 for each subsequent instance.
 
-	When the appropriate module paramters are in place, then
-configure bonding according to the instructions for your distro.
 
 5. Querying Bonding Configuration 
 =================================
@@ -846,8 +1005,8 @@ tagged internally by bonding itself.  As a result, bonding must
 self generated packets.
 
 	For reasons of simplicity, and to support the use of adapters
-that can do VLAN hardware acceleration offloding, the bonding
-interface declares itself as fully hardware offloaing capable, it gets
+that can do VLAN hardware acceleration offloading, the bonding
+interface declares itself as fully hardware offloading capable, it gets
 the add_vid/kill_vid notifications to gather the necessary
 information, and it propagates those actions to the slaves.  In case
 of mixed adapter types, hardware accelerated tagged packets that
@@ -880,7 +1039,7 @@ bond interface:
 matches the hardware address of the VLAN interfaces.
 
 	Note that changing a VLAN interface's HW address would set the
-underlying device -- i.e. the bonding interface -- to promiscouos
+underlying device -- i.e. the bonding interface -- to promiscuous
 mode, which might not be what you want.
 
 
@@ -923,7 +1082,7 @@ down or have a problem making it unresponsive to ARP requests.  Having
 an additional target (or several) increases the reliability of the ARP
 monitoring.
 
-	Multiple ARP targets must be seperated by commas as follows:
+	Multiple ARP targets must be separated by commas as follows:
 
 # example options for ARP monitoring with three targets
 alias bond0 bonding
@@ -1045,7 +1204,7 @@ install bonding /sbin/modprobe tg3; /sbin/modprobe e1000;
 	This will, when loading the bonding module, rather than
 performing the normal action, instead execute the provided command.
 This command loads the device drivers in the order needed, then calls
-modprobe with --ingore-install to cause the normal action to then take
+modprobe with --ignore-install to cause the normal action to then take
 place.  Full documentation on this can be found in the modprobe.conf
 and modprobe manual pages.
 
@@ -1130,14 +1289,14 @@ association.
 common to enable promiscuous mode on the device, so that all traffic
 is seen (instead of seeing only traffic destined for the local host).
 The bonding driver handles promiscuous mode changes to the bonding
-master device (e.g., bond0), and propogates the setting to the slave
+master device (e.g., bond0), and propagates the setting to the slave
 devices.
 
 	For the balance-rr, balance-xor, broadcast, and 802.3ad modes,
-the promiscuous mode setting is propogated to all slaves.
+the promiscuous mode setting is propagated to all slaves.
 
 	For the active-backup, balance-tlb and balance-alb modes, the
-promiscuous mode setting is propogated only to the active slave.
+promiscuous mode setting is propagated only to the active slave.
 
 	For balance-tlb mode, the active slave is the slave currently
 receiving inbound traffic.
@@ -1148,46 +1307,182 @@ sending to peers that are unassigned or if the load is unbalanced.
 
 	For the active-backup, balance-tlb and balance-alb modes, when
 the active slave changes (e.g., due to a link failure), the
-promiscuous setting will be propogated to the new active slave.
+promiscuous setting will be propagated to the new active slave.
 
-12. High Availability Information
-=================================
+12. Configuring Bonding for High Availability
+=============================================
 
 	High Availability refers to configurations that provide
 maximum network availability by having redundant or backup devices,
-links and switches between the host and the rest of the world.
-
-	There are currently two basic methods for configuring to
-maximize availability. They are dependent on the network topology and
-the primary goal of the configuration, but in general, a configuration
-can be optimized for maximum available bandwidth, or for maximum
-network availability.
+links or switches between the host and the rest of the world.  The
+goal is to provide the maximum availability of network connectivity
+(i.e., the network always works), even though other configurations
+could provide higher throughput.
 
 12.1 High Availability in a Single Switch Topology
 --------------------------------------------------
 
-	If two hosts (or a host and a switch) are directly connected
-via multiple physical links, then there is no network availability
-penalty for optimizing for maximum bandwidth: there is only one switch
-(or peer), so if it fails, you have no alternative access to fail over
-to.
+	If two hosts (or a host and a single switch) are directly
+connected via multiple physical links, then there is no availability
+penalty to optimizing for maximum bandwidth.  In this case, there is
+only one switch (or peer), so if it fails, there is no alternative
+access to fail over to.  Additionally, the bonding load balance modes
+support link monitoring of their members, so if individual links fail,
+the load will be rebalanced across the remaining devices.
+
+	See Section 13, "Configuring Bonding for Maximum Throughput"
+for information on configuring bonding with one peer device.
+
+12.2 High Availability in a Multiple Switch Topology
+----------------------------------------------------
+
+	With multiple switches, the configuration of bonding and the
+network changes dramatically.  In multiple switch topologies, there is
+a trade off between network availability and usable bandwidth.
+
+	Below is a sample network, configured to maximize the
+availability of the network:
 
-Example 1 : host to switch (or other host)
+                |                                     |
+                |port3                           port3|
+          +-----+----+                          +-----+----+
+          |          |port2       ISL      port2|          |
+          | switch A +--------------------------+ switch B |
+          |          |                          |          |
+          +-----+----+                          +-----++---+
+                |port1                           port1|
+                |             +-------+               |
+                +-------------+ host1 +---------------+
+                         eth0 +-------+ eth1
 
-          +----------+                          +----------+
-          |          |eth0                  eth0|  switch  |
-          | Host A   +--------------------------+    or    |
-          |          +--------------------------+  other   |
-          |          |eth1                  eth1|  host    |
-          +----------+                          +----------+
+	In this configuration, there is a link between the two
+switches (ISL, or inter switch link), and multiple ports connecting to
+the outside world ("port3" on each switch).  There is no technical
+reason that this could not be extended to a third switch.
 
+12.2.1 HA Bonding Mode Selection for Multiple Switch Topology
+-------------------------------------------------------------
 
-12.1.1 Bonding Mode Selection for single switch topology
---------------------------------------------------------
+	In a topology such as the example above, the active-backup and
+broadcast modes are the only useful bonding modes when optimizing for
+availability; the other modes require all links to terminate on the
+same peer for them to behave rationally.
+
+active-backup: This is generally the preferred mode, particularly if
+	the switches have an ISL and play together well.  If the
+	network configuration is such that one switch is specifically
+	a backup switch (e.g., has lower capacity, higher cost, etc),
+	then the primary option can be used to insure that the
+	preferred link is always used when it is available.
+
+broadcast: This mode is really a special purpose mode, and is suitable
+	only for very specific needs.  For example, if the two
+	switches are not connected (no ISL), and the networks beyond
+	them are totally independent.  In this case, if it is
+	necessary for some specific one-way traffic to reach both
+	independent networks, then the broadcast mode may be suitable.
+
+12.2.2 HA Link Monitoring Selection for Multiple Switch Topology
+----------------------------------------------------------------
+
+	The choice of link monitoring ultimately depends upon your
+switch.  If the switch can reliably fail ports in response to other
+failures, then either the MII or ARP monitors should work.  For
+example, in the above example, if the "port3" link fails at the remote
+end, the MII monitor has no direct means to detect this.  The ARP
+monitor could be configured with a target at the remote end of port3,
+thus detecting that failure without switch support.
+
+	In general, however, in a multiple switch topology, the ARP
+monitor can provide a higher level of reliability in detecting end to
+end connectivity failures (which may be caused by the failure of any
+individual component to pass traffic for any reason).  Additionally,
+the ARP monitor should be configured with multiple targets (at least
+one for each switch in the network).  This will insure that,
+regardless of which switch is active, the ARP monitor has a suitable
+target to query.
+
+
+13. Configuring Bonding for Maximum Throughput
+==============================================
+
+13.1 Maximizing Throughput in a Single Switch Topology
+------------------------------------------------------
+
+	In a single switch configuration, the best method to maximize
+throughput depends upon the application and network environment.  The
+various load balancing modes each have strengths and weaknesses in
+different environments, as detailed below.
+
+	For this discussion, we will break down the topologies into
+two categories.  Depending upon the destination of most traffic, we
+categorize them into either "gatewayed" or "local" configurations.
+
+	In a gatewayed configuration, the "switch" is acting primarily
+as a router, and the majority of traffic passes through this router to
+other networks.  An example would be the following:
+
+
+     +----------+                     +----------+
+     |          |eth0            port1|          | to other networks
+     | Host A   +---------------------+ router   +------------------->
+     |          +---------------------+          | Hosts B and C are out
+     |          |eth1            port2|          | here somewhere
+     +----------+                     +----------+
+
+	The router may be a dedicated router device, or another host
+acting as a gateway.  For our discussion, the important point is that
+the majority of traffic from Host A will pass through the router to
+some other network before reaching its final destination.
+
+	In a gatewayed network configuration, although Host A may
+communicate with many other systems, all of its traffic will be sent
+and received via one other peer on the local network, the router.
+
+	Note that the case of two systems connected directly via
+multiple physical links is, for purposes of configuring bonding, the
+same as a gatewayed configuration.  In that case, it happens that all
+traffic is destined for the "gateway" itself, not some other network
+beyond the gateway.
+
+	In a local configuration, the "switch" is acting primarily as
+a switch, and the majority of traffic passes through this switch to
+reach other stations on the same network.  An example would be the
+following:
+
+    +----------+            +----------+       +--------+
+    |          |eth0   port1|          +-------+ Host B |
+    |  Host A  +------------+  switch  |port3  +--------+
+    |          +------------+          |                  +--------+
+    |          |eth1   port2|          +------------------+ Host C |
+    +----------+            +----------+port4             +--------+
+
+
+	Again, the switch may be a dedicated switch device, or another
+host acting as a gateway.  For our discussion, the important point is
+that the majority of traffic from Host A is destined for other hosts
+on the same local network (Hosts B and C in the above example).
+
+	In summary, in a gatewayed configuration, traffic to and from
+the bonded device will be to the same MAC level peer on the network
+(the gateway itself, i.e., the router), regardless of its final
+destination.  In a local configuration, traffic flows directly to and
+from the final destinations, thus, each destination (Host B, Host C)
+will be addressed directly by their individual MAC addresses.
+
+	This distinction between a gatewayed and a local network
+configuration is important because many of the load balancing modes
+available use the MAC addresses of the local network source and
+destination to make load balancing decisions.  The behavior of each
+mode is described below.
+
+
+13.1.1 MT Bonding Mode Selection for Single Switch Topology
+-----------------------------------------------------------
 
 	This configuration is the easiest to set up and to understand,
 although you will have to decide which bonding mode best suits your
-needs.  The tradeoffs for each mode are detailed below:
+needs.  The trade offs for each mode are detailed below:
 
 balance-rr: This mode is the only mode that will permit a single
 	TCP/IP connection to stripe traffic across multiple
@@ -1206,6 +1501,23 @@ balance-rr: This mode is the only mode that will permit a single
 	interface's worth of throughput, even after adjusting
 	tcp_reordering.
 
+	Note that this out of order delivery occurs when both the
+	sending and receiving systems are utilizing a multiple
+	interface bond.  Consider a configuration in which a
+	balance-rr bond feeds into a single higher capacity network
+	channel (e.g., multiple 100Mb/sec ethernets feeding a single
+	gigabit ethernet via an etherchannel capable switch).  In this
+	configuration, traffic sent from the multiple 100Mb devices to
+	a destination connected to the gigabit device will not see
+	packets out of order.  However, traffic sent from the gigabit
+	device to the multiple 100Mb devices may or may not see
+	traffic out of order, depending upon the balance policy of the
+	switch.  Many switches do not support any modes that stripe
+	traffic (instead choosing a port based upon IP or MAC level
+	addresses); for those devices, traffic flowing from the
+	gigabit device to the many 100Mb devices will only utilize one
+	interface.
+
 	If you are utilizing protocols other than TCP/IP, UDP for
 	example, and your application can tolerate out of order
 	delivery, then this mode can allow for single stream datagram
@@ -1220,16 +1532,21 @@ active-backup: There is not much advantage in this network topology to
 	connected to the same peer as the primary.  In this case, a
 	load balancing mode (with link monitoring) will provide the
 	same level of network availability, but with increased
-	available bandwidth.  On the plus side, it does not require
-	any configuration of the switch.
+	available bandwidth.  On the plus side, active-backup mode
+	does not require any configuration of the switch, so it may
+	have value if the hardware available does not support any of
+	the load balance modes.
 
 balance-xor: This mode will limit traffic such that packets destined
 	for specific peers will always be sent over the same
 	interface.  Since the destination is determined by the MAC
-	addresses involved, this may be desirable if you have a large
-	network with many hosts.  It is likely to be suboptimal if all
-	your traffic is passed through a single router, however.  As
-	with balance-rr, the switch ports need to be configured for
+	addresses involved, this mode works best in a "local" network
+	configuration (as described above), with destinations all on
+	the same local network.  This mode is likely to be suboptimal
+	if all your traffic is passed through a single router (i.e., a
+	"gatewayed" network configuration, as described above).
+
+	As with balance-rr, the switch ports need to be configured for
 	"etherchannel" or "trunking."
 
 broadcast: Like active-backup, there is not much advantage to this
@@ -1241,122 +1558,131 @@ broadcast: Like active-backup, there is not much advantage to this
 	protocol includes automatic configuration of the aggregates,
 	so minimal manual configuration of the switch is needed
 	(typically only to designate that some set of devices is
-	usable for 802.3ad).  The 802.3ad standard also mandates that
-	frames be delivered in order (within certain limits), so in
-	general single connections will not see misordering of
+	available for 802.3ad).  The 802.3ad standard also mandates
+	that frames be delivered in order (within certain limits), so
+	in general single connections will not see misordering of
 	packets.  The 802.3ad mode does have some drawbacks: the
 	standard mandates that all devices in the aggregate operate at
 	the same speed and duplex.  Also, as with all bonding load
 	balance modes other than balance-rr, no single connection will
 	be able to utilize more than a single interface's worth of
-	bandwidth.  Additionally, the linux bonding 802.3ad
-	implementation distributes traffic by peer (using an XOR of
-	MAC addresses), so in general all traffic to a particular
-	destination will use the same interface.  Finally, the 802.3ad
-	mode mandates the use of the MII monitor, therefore, the ARP
-	monitor is not available in this mode.
-
-balance-tlb: This mode is also a good choice for this type of
-	topology.  It has no special switch configuration
-	requirements, and balances outgoing traffic by peer, in a
-	vaguely intelligent manner (not a simple XOR as in balance-xor
-	or 802.3ad mode), so that unlucky MAC addresses will not all
-	"bunch up" on a single interface.  Interfaces may be of
-	differing speeds.  On the down side, in this mode all incoming
-	traffic arrives over a single interface, this mode requires
-	certain ethtool support in the network device driver of the
-	slave interfaces, and the ARP monitor is not available.
-
-balance-alb: This mode is everything that balance-tlb is, and more. It
-	has all of the features (and restrictions) of balance-tlb, and
-	will also balance incoming traffic from peers (as described in
-	the Bonding Module Options section, above).  The only extra
-	down side to this mode is that the network device driver must
-	support changing the hardware address while the device is
-	open.
-
-12.1.2 Link Monitoring for Single Switch Topology
--------------------------------------------------
+	bandwidth.  
+
+	Additionally, the linux bonding 802.3ad implementation
+	distributes traffic by peer (using an XOR of MAC addresses),
+	so in a "gatewayed" configuration, all outgoing traffic will
+	generally use the same device.  Incoming traffic may also end
+	up on a single device, but that is dependent upon the
+	balancing policy of the peer's 8023.ad implementation.  In a
+	"local" configuration, traffic will be distributed across the
+	devices in the bond.
+
+	Finally, the 802.3ad mode mandates the use of the MII monitor,
+	therefore, the ARP monitor is not available in this mode.
+
+balance-tlb: The balance-tlb mode balances outgoing traffic by peer.
+	Since the balancing is done according to MAC address, in a
+	"gatewayed" configuration (as described above), this mode will
+	send all traffic across a single device.  However, in a
+	"local" network configuration, this mode balances multiple
+	local network peers across devices in a vaguely intelligent
+	manner (not a simple XOR as in balance-xor or 802.3ad mode),
+	so that mathematically unlucky MAC addresses (i.e., ones that
+	XOR to the same value) will not all "bunch up" on a single
+	interface.
+
+	Unlike 802.3ad, interfaces may be of differing speeds, and no
+	special switch configuration is required.  On the down side,
+	in this mode all incoming traffic arrives over a single
+	interface, this mode requires certain ethtool support in the
+	network device driver of the slave interfaces, and the ARP
+	monitor is not available.
+
+balance-alb: This mode is everything that balance-tlb is, and more.
+	It has all of the features (and restrictions) of balance-tlb,
+	and will also balance incoming traffic from local network
+	peers (as described in the Bonding Module Options section,
+	above).
+
+	The only additional down side to this mode is that the network
+	device driver must support changing the hardware address while
+	the device is open.
+
+13.1.2 MT Link Monitoring for Single Switch Topology
+----------------------------------------------------
 
 	The choice of link monitoring may largely depend upon which
 mode you choose to use.  The more advanced load balancing modes do not
 support the use of the ARP monitor, and are thus restricted to using
-the MII monitor (which does not provide as high a level of assurance
-as the ARP monitor).
-
-
-12.2 High Availability in a Multiple Switch Topology
-----------------------------------------------------
-
-	With multiple switches, the configuration of bonding and the
-network changes dramatically.  In multiple switch topologies, there is
-a tradeoff between network availability and usable bandwidth.
-
-	Below is a sample network, configured to maximize the
-availability of the network:
-
-                |                                     |
-                |port3                           port3|
-          +-----+----+                          +-----+----+
-          |          |port2       ISL      port2|          |
-          | switch A +--------------------------+ switch B |
-          |          |                          |          |
-          +-----+----+                          +-----++---+
-                |port1                           port1|
-                |             +-------+               |
-                +-------------+ host1 +---------------+
-                         eth0 +-------+ eth1
-
-	In this configuration, there is a link between the two
-switches (ISL, or inter switch link), and multiple ports connecting to
-the outside world ("port3" on each switch).  There is no technical
-reason that this could not be extended to a third switch.
-
-12.2.1 Bonding Mode Selection for Multiple Switch Topology
-----------------------------------------------------------
-
-	In a topology such as this, the active-backup and broadcast
-modes are the only useful bonding modes; the other modes require all
-links to terminate on the same peer for them to behave rationally.
-
-active-backup: This is generally the preferred mode, particularly if
-	the switches have an ISL and play together well.  If the
-	network configuration is such that one switch is specifically
-	a backup switch (e.g., has lower capacity, higher cost, etc),
-	then the primary option can be used to insure that the
-	preferred link is always used when it is available.
-
-broadcast: This mode is really a special purpose mode, and is suitable
-	only for very specific needs.  For example, if the two
-	switches are not connected (no ISL), and the networks beyond
-	them are totally independant.  In this case, if it is
-	necessary for some specific one-way traffic to reach both
-	independent networks, then the broadcast mode may be suitable.
-
-12.2.2 Link Monitoring Selection for Multiple Switch Topology
+the MII monitor (which does not provide as high a level of end to end
+assurance as the ARP monitor).
+
+13.2 Maximum Throughput in a Multiple Switch Topology
+-----------------------------------------------------
+
+	Multiple switches may be utilized to optimize for throughput
+when they are configured in parallel as part of an isolated network
+between two or more systems, for example:
+
+                       +-----------+
+                       |  Host A   | 
+                       +-+---+---+-+
+                         |   |   |
+                +--------+   |   +---------+
+                |            |             |
+         +------+---+  +-----+----+  +-----+----+
+         | Switch A |  | Switch B |  | Switch C |
+         +------+---+  +-----+----+  +-----+----+
+                |            |             |
+                +--------+   |   +---------+
+                         |   |   |
+                       +-+---+---+-+
+                       |  Host B   | 
+                       +-----------+
+
+	In this configuration, the switches are isolated from one
+another.  One reason to employ a topology such as this is for an
+isolated network with many hosts (a cluster configured for high
+performance, for example), using multiple smaller switches can be more
+cost effective than a single larger switch, e.g., on a network with 24
+hosts, three 24 port switches can be significantly less expensive than
+a single 72 port switch.
+
+	If access beyond the network is required, an individual host
+can be equipped with an additional network device connected to an
+external network; this host then additionally acts as a gateway.
+
+13.2.1 MT Bonding Mode Selection for Multiple Switch Topology
 -------------------------------------------------------------
 
-	The choice of link monitoring ultimately depends upon your
-switch.  If the switch can reliably fail ports in response to other
-failures, then either the MII or ARP monitors should work.  For
-example, in the above example, if the "port3" link fails at the remote
-end, the MII monitor has no direct means to detect this.  The ARP
-monitor could be configured with a target at the remote end of port3,
-thus detecting that failure without switch support.
+	In actual practice, the bonding mode typically employed in
+configurations of this type is balance-rr.  Historically, in this
+network configuration, the usual caveats about out of order packet
+delivery are mitigated by the use of network adapters that do not do
+any kind of packet coalescing (via the use of NAPI, or because the
+device itself does not generate interrupts until some number of
+packets has arrived).  When employed in this fashion, the balance-rr
+mode allows individual connections between two hosts to effectively
+utilize greater than one interface's bandwidth.
 
-	In general, however, in a multiple switch topology, the ARP
-monitor can provide a higher level of reliability in detecting link
-failures.  Additionally, it should be configured with multiple targets
-(at least one for each switch in the network).  This will insure that,
-regardless of which switch is active, the ARP monitor has a suitable
-target to query.
+13.2.2 MT Link Monitoring for Multiple Switch Topology
+------------------------------------------------------
 
+	Again, in actual practice, the MII monitor is most often used
+in this configuration, as performance is given preference over
+availability.  The ARP monitor will function in this topology, but its
+advantages over the MII monitor are mitigated by the volume of probes
+needed as the number of systems involved grows (remember that each
+host in the network is configured with bonding).
 
-12.3 Switch Behavior Issues for High Availability
--------------------------------------------------
+14. Switch Behavior Issues
+==========================
 
-	You may encounter issues with the timing of link up and down
-reporting by the switch.
+14.1 Link Establishment and Failover Delays
+-------------------------------------------
+
+	Some switches exhibit undesirable behavior with regard to the
+timing of link up and down reporting by the switch.
 
 	First, when a link comes up, some switches may indicate that
 the link is up (carrier available), but not pass traffic over the
@@ -1370,30 +1696,70 @@ relevant interface(s).
 	Second, some switches may "bounce" the link state one or more
 times while a link is changing state.  This occurs most commonly while
 the switch is initializing.  Again, an appropriate updelay value may
-help, but note that if all links are down, then updelay is ignored
-when any link becomes active (the slave closest to completing its
-updelay is chosen).
+help.
 
 	Note that when a bonding interface has no active links, the
-driver will immediately reuse the first link that goes up, even if
-updelay parameter was specified.  If there are slave interfaces
-waiting for the updelay timeout to expire, the interface that first
-went into that state will be immediately reused.  This reduces down
-time of the network if the value of updelay has been overestimated.
+driver will immediately reuse the first link that goes up, even if the
+updelay parameter has been specified (the updelay is ignored in this
+case).  If there are slave interfaces waiting for the updelay timeout
+to expire, the interface that first went into that state will be
+immediately reused.  This reduces down time of the network if the
+value of updelay has been overestimated, and since this occurs only in
+cases with no connectivity, there is no additional penalty for
+ignoring the updelay.
 
 	In addition to the concerns about switch timings, if your
 switches take a long time to go into backup mode, it may be desirable
 to not activate a backup interface immediately after a link goes down.
 Failover may be delayed via the downdelay bonding module option.
 
-13. Hardware Specific Considerations
+14.2 Duplicated Incoming Packets
+--------------------------------
+
+	It is not uncommon to observe a short burst of duplicated
+traffic when the bonding device is first used, or after it has been
+idle for some period of time.  This is most easily observed by issuing
+a "ping" to some other host on the network, and noticing that the
+output from ping flags duplicates (typically one per slave).
+
+	For example, on a bond in active-backup mode with five slaves
+all connected to one switch, the output may appear as follows:
+
+# ping -n 10.0.4.2
+PING 10.0.4.2 (10.0.4.2) from 10.0.3.10 : 56(84) bytes of data.
+64 bytes from 10.0.4.2: icmp_seq=1 ttl=64 time=13.7 ms
+64 bytes from 10.0.4.2: icmp_seq=1 ttl=64 time=13.8 ms (DUP!)
+64 bytes from 10.0.4.2: icmp_seq=1 ttl=64 time=13.8 ms (DUP!)
+64 bytes from 10.0.4.2: icmp_seq=1 ttl=64 time=13.8 ms (DUP!)
+64 bytes from 10.0.4.2: icmp_seq=1 ttl=64 time=13.8 ms (DUP!)
+64 bytes from 10.0.4.2: icmp_seq=2 ttl=64 time=0.216 ms
+64 bytes from 10.0.4.2: icmp_seq=3 ttl=64 time=0.267 ms
+64 bytes from 10.0.4.2: icmp_seq=4 ttl=64 time=0.222 ms
+
+	This is not due to an error in the bonding driver, rather, it
+is a side effect of how many switches update their MAC forwarding
+tables.  Initially, the switch does not associate the MAC address in
+the packet with a particular switch port, and so it may send the
+traffic to all ports until its MAC forwarding table is updated.  Since
+the interfaces attached to the bond may occupy multiple ports on a
+single switch, when the switch (temporarily) floods the traffic to all
+ports, the bond device receives multiple copies of the same packet
+(one per slave device).
+
+	The duplicated packet behavior is switch dependent, some
+switches exhibit this, and some do not.  On switches that display this
+behavior, it can be induced by clearing the MAC forwarding table (on
+most Cisco switches, the privileged command "clear mac address-table
+dynamic" will accomplish this).
+
+15. Hardware Specific Considerations
 ====================================
 
 	This section contains additional information for configuring
 bonding on specific hardware platforms, or for interfacing bonding
 with particular switches or other devices.
 
-13.1 IBM BladeCenter
+15.1 IBM BladeCenter
 --------------------
 
 	This applies to the JS20 and similar systems.
@@ -1407,12 +1773,12 @@ JS20 network adapter information
 --------------------------------
 
 	All JS20s come with two Broadcom Gigabit Ethernet ports
-integrated on the planar.  In the BladeCenter chassis, the eth0 port
-of all JS20 blades is hard wired to I/O Module #1; similarly, all eth1
-ports are wired to I/O Module #2.  An add-on Broadcom daughter card
-can be installed on a JS20 to provide two more Gigabit Ethernet ports.
-These ports, eth2 and eth3, are wired to I/O Modules 3 and 4,
-respectively.
+integrated on the planar (that's "motherboard" in IBM-speak).  In the
+BladeCenter chassis, the eth0 port of all JS20 blades is hard wired to
+I/O Module #1; similarly, all eth1 ports are wired to I/O Module #2.
+An add-on Broadcom daughter card can be installed on a JS20 to provide
+two more Gigabit Ethernet ports.  These ports, eth2 and eth3, are
+wired to I/O Modules 3 and 4, respectively.
 
 	Each I/O Module may contain either a switch or a passthrough
 module (which allows ports to be directly connected to an external
@@ -1432,29 +1798,30 @@ BladeCenter networking configuration
 of ways, this discussion will be confined to describing basic
 configurations.
 
-	Normally, Ethernet Switch Modules (ESM) are used in I/O
+	Normally, Ethernet Switch Modules (ESMs) are used in I/O
 modules 1 and 2.  In this configuration, the eth0 and eth1 ports of a
 JS20 will be connected to different internal switches (in the
 respective I/O modules).
 
-	An optical passthru module (OPM) connects the I/O module
-directly to an external switch.  By using OPMs in I/O module #1 and
-#2, the eth0 and eth1 interfaces of a JS20 can be redirected to the
-outside world and connected to a common external switch.
-
-	Depending upon the mix of ESM and OPM modules, the network
-will appear to bonding as either a single switch topology (all OPM
-modules) or as a multiple switch topology (one or more ESM modules,
-zero or more OPM modules).  It is also possible to connect ESM modules
-together, resulting in a configuration much like the example in "High
-Availability in a multiple switch topology."
-
-Requirements for specifc modes
-------------------------------
-
-	The balance-rr mode requires the use of OPM modules for
-devices in the bond, all connected to an common external switch.  That
-switch must be configured for "etherchannel" or "trunking" on the
+	A passthrough module (OPM or CPM, optical or copper,
+passthrough module) connects the I/O module directly to an external
+switch.  By using PMs in I/O module #1 and #2, the eth0 and eth1
+interfaces of a JS20 can be redirected to the outside world and
+connected to a common external switch.
+
+	Depending upon the mix of ESMs and PMs, the network will
+appear to bonding as either a single switch topology (all PMs) or as a
+multiple switch topology (one or more ESMs, zero or more PMs).  It is
+also possible to connect ESMs together, resulting in a configuration
+much like the example in "High Availability in a Multiple Switch
+Topology," above.
+
+Requirements for specific modes
+-------------------------------
+
+	The balance-rr mode requires the use of passthrough modules
+for devices in the bond, all connected to an common external switch.
+That switch must be configured for "etherchannel" or "trunking" on the
 appropriate ports, as is usual for balance-rr.
 
 	The balance-alb and balance-tlb modes will function with
@@ -1484,17 +1851,18 @@ connected to the JS20 system.
 Other concerns
 --------------
 
-	The Serial Over LAN link is established over the primary
+	The Serial Over LAN (SoL) link is established over the primary
 ethernet (eth0) only, therefore, any loss of link to eth0 will result
 in losing your SoL connection.  It will not fail over with other
-network traffic.
+network traffic, as the SoL system is beyond the control of the
+bonding driver.
 
 	It may be desirable to disable spanning tree on the switch
 (either the internal Ethernet Switch Module, or an external switch) to
-avoid fail-over delays issues when using bonding.
+avoid fail-over delay issues when using bonding.
 
 	
-14. Frequently Asked Questions
+16. Frequently Asked Questions
 ==============================
 
 1.  Is it SMP safe?
@@ -1505,8 +1873,8 @@ The new driver was designed to be SMP safe from the start.
 2.  What type of cards will work with it?
 
 	Any Ethernet type cards (you can even mix cards - a Intel
-EtherExpress PRO/100 and a 3com 3c905b, for example).  They need not
-be of the same speed.
+EtherExpress PRO/100 and a 3com 3c905b, for example).  For most modes,
+devices need not be of the same speed.
 
 3.  How many bonding devices can I have?
 
@@ -1524,11 +1892,12 @@ system.
 disabled.  The active-backup mode will fail over to a backup link, and
 other modes will ignore the failed link.  The link will continue to be
 monitored, and should it recover, it will rejoin the bond (in whatever
-manner is appropriate for the mode). See the section on High
-Availability for additional information.
+manner is appropriate for the mode). See the sections on High
+Availability and the documentation for each mode for additional
+information.
 	
 	Link monitoring can be enabled via either the miimon or
-arp_interval paramters (described in the module paramters section,
+arp_interval parameters (described in the module parameters section,
 above).  In general, miimon monitors the carrier state as sensed by
 the underlying network device, and the arp monitor (arp_interval)
 monitors connectivity to another host on the local network.
@@ -1536,7 +1905,7 @@ monitors connectivity to another host on the local network.
 	If no link monitoring is configured, the bonding driver will
 be unable to detect link failures, and will assume that all links are
 always available.  This will likely result in lost packets, and a
-resulting degredation of performance.  The precise performance loss
+resulting degradation of performance.  The precise performance loss
 depends upon the bonding mode and network configuration.
 
 6.  Can bonding be used for High Availability?
@@ -1550,12 +1919,12 @@ depends upon the bonding mode and network configuration.
 	In the basic balance modes (balance-rr and balance-xor), it
 works with any system that supports etherchannel (also called
 trunking).  Most managed switches currently available have such
-support, and many unmananged switches as well.
+support, and many unmanaged switches as well.
 
 	The advanced balance modes (balance-tlb and balance-alb) do
 not have special switch requirements, but do need device drivers that
 support specific features (described in the appropriate section under
-module paramters, above).
+module parameters, above).
 
 	In 802.3ad mode, it works with with systems that support IEEE
 802.3ad Dynamic Link Aggregation.  Most managed and many unmanaged
@@ -1565,17 +1934,19 @@ switches currently available support 802.3ad.
 
 8.  Where does a bonding device get its MAC address from?
 
-	If not explicitly configured with ifconfig, the MAC address of
-the bonding device is taken from its first slave device. This MAC
-address is then passed to all following slaves and remains persistent
-(even if the the first slave is removed) until the bonding device is
-brought down or reconfigured.
+	If not explicitly configured (with ifconfig or ip link), the
+MAC address of the bonding device is taken from its first slave
+device.  This MAC address is then passed to all following slaves and
+remains persistent (even if the the first slave is removed) until the
+bonding device is brought down or reconfigured.
 
 	If you wish to change the MAC address, you can set it with
-ifconfig:
+ifconfig or ip link:
 
 # ifconfig bond0 hw ether 00:11:22:33:44:55
 
+# ip link set bond0 address 66:77:88:99:aa:bb
+
 	The MAC address can be also changed by bringing down/up the
 device and then changing its slaves (or their order):
 
@@ -1591,23 +1962,28 @@ from the bond (`ifenslave -d bond0 eth0'). The bonding driver will
 then restore the MAC addresses that the slaves had before they were
 enslaved.
 
-15. Resources and Links
+16. Resources and Links
 =======================
 
 The latest version of the bonding driver can be found in the latest
 version of the linux kernel, found on http://kernel.org
 
+The latest version of this document can be found in either the latest
+kernel source (named Documentation/networking/bonding.txt), or on the
+bonding sourceforge site:
+
+http://www.sourceforge.net/projects/bonding
+
 Discussions regarding the bonding driver take place primarily on the
 bonding-devel mailing list, hosted at sourceforge.net.  If you have
-questions or problems, post them to the list.
+questions or problems, post them to the list.  The list address is:
 
 bonding-devel@lists.sourceforge.net
 
-https://lists.sourceforge.net/lists/listinfo/bonding-devel
-
-There is also a project site on sourceforge.
+	The administrative interface (to subscribe or unsubscribe) can
+be found at:
 
-http://www.sourceforge.net/projects/bonding
+https://lists.sourceforge.net/lists/listinfo/bonding-devel
 
 Donald Becker's Ethernet Drivers and diag programs may be found at :
  - http://www.scyld.com/network/
diff --git a/Documentation/pcmcia/driver-changes.txt b/Documentation/pcmcia/driver-changes.txt
index 59ccc63838c..403e7b4dcdd 100644
--- a/Documentation/pcmcia/driver-changes.txt
+++ b/Documentation/pcmcia/driver-changes.txt
@@ -56,3 +56,12 @@ This file details changes in 2.6 which affect PCMCIA card driver authors:
    memory regions in-use. The name argument should be a pointer to
    your driver name. Eg, for pcnet_cs, name should point to the
    string "pcnet_cs".
+
+* CardServices is gone
+  CardServices() in 2.4 is just a big switch statement to call various
+  services.  In 2.6, all of those entry points are exported and called
+  directly (except for pcmcia_report_error(), just use cs_error() instead).
+
+* struct pcmcia_driver
+  You need to use struct pcmcia_driver and pcmcia_{un,}register_driver
+  instead of {un,}register_pccard_driver
diff --git a/Documentation/sound/alsa/ALSA-Configuration.txt b/Documentation/sound/alsa/ALSA-Configuration.txt
index 104a994b828..a18ecb92b35 100644
--- a/Documentation/sound/alsa/ALSA-Configuration.txt
+++ b/Documentation/sound/alsa/ALSA-Configuration.txt
@@ -636,11 +636,16 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed.
 	  3stack-digout	3-jack in back, a HP out and a SPDIF out
 	  5stack	5-jack in back, 2-jack in front
 	  5stack-digout	5-jack in back, 2-jack in front, a SPDIF out
+	  6stack	6-jack in back, 2-jack in front
+	  6stack-digout	6-jack with a SPDIF out
 	  w810		3-jack
 	  z71v		3-jack (HP shared SPDIF)
 	  asus		3-jack
 	  uniwill	3-jack
 	  F1734		2-jack
+	  test		for testing/debugging purpose, almost all controls can be
+			adjusted.  Appearing only when compiled with
+			$CONFIG_SND_DEBUG=y
 
 	CMI9880
 	  minimal	3-jack in back
@@ -1054,6 +1059,13 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed.
 
     The power-management is supported.
 
+  Module snd-pxa2xx-ac97 (on arm only)
+  ------------------------------------
+
+    Module for AC97 driver for the Intel PXA2xx chip
+
+    For ARM architecture only.
+
   Module snd-rme32
   ----------------
 
@@ -1173,6 +1185,13 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed.
 
     Module supports up to 8 cards.
 
+  Module snd-sun-dbri (on sparc only)
+  -----------------------------------
+
+    Module for DBRI sound chips found on Sparcs.
+
+    Module supports up to 8 cards.
+
   Module snd-wavefront
   --------------------
 
@@ -1371,7 +1390,7 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed.
   Module snd-vxpocket
   -------------------
 
-    Module for Digigram VX-Pocket VX2 PCMCIA card.
+    Module for Digigram VX-Pocket VX2 and 440 PCMCIA cards.
 
     ibl      - Capture IBL size. (default = 0, minimum size)
 
@@ -1391,29 +1410,6 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed.
 
     Note: the driver is build only when CONFIG_ISA is set.
     
-  Module snd-vxp440
-  -----------------
-
-    Module for Digigram VX-Pocket 440 PCMCIA card.
-
-    ibl      - Capture IBL size. (default = 0, minimum size)
-
-    Module supports up to 8 cards.  The module is compiled only when
-    PCMCIA is supported on kernel.
-
-    To activate the driver via the card manager, you'll need to set
-    up /etc/pcmcia/vxp440.conf.  See the sound/pcmcia/vx/vxp440.c.
-
-    When the driver is compiled as a module and the hotplug firmware
-    is supported, the firmware data is loaded via hotplug automatically.
-    Install the necessary firmware files in alsa-firmware package.
-    When no hotplug fw loader is available, you need to load the
-    firmware via vxloader utility in alsa-tools package.
-
-    About capture IBL, see the description of snd-vx222 module.
-
-    Note: the driver is build only when CONFIG_ISA is set.
-    
   Module snd-ymfpci
   -----------------
 
diff --git a/Documentation/stable_api_nonsense.txt b/Documentation/stable_api_nonsense.txt
index 3cea1387527..f39c9d714db 100644
--- a/Documentation/stable_api_nonsense.txt
+++ b/Documentation/stable_api_nonsense.txt
@@ -132,7 +132,7 @@ to extra work for the USB developers.  Since all Linux USB developers do
 their work on their own time, asking programmers to do extra work for no
 gain, for free, is not a possibility.
 
-Security issues are also a very important for Linux.  When a
+Security issues are also very important for Linux.  When a
 security issue is found, it is fixed in a very short amount of time.  A
 number of times this has caused internal kernel interfaces to be
 reworked to prevent the security problem from occurring.  When this
diff --git a/Documentation/stable_kernel_rules.txt b/Documentation/stable_kernel_rules.txt
new file mode 100644
index 00000000000..2c81305090d
--- /dev/null
+++ b/Documentation/stable_kernel_rules.txt
@@ -0,0 +1,58 @@
+Everything you ever wanted to know about Linux 2.6 -stable releases.
+
+Rules on what kind of patches are accepted, and what ones are not, into
+the "-stable" tree:
+
+ - It must be obviously correct and tested.
+ - It can not bigger than 100 lines, with context.
+ - It must fix only one thing.
+ - It must fix a real bug that bothers people (not a, "This could be a
+   problem..." type thing.)
+ - It must fix a problem that causes a build error (but not for things
+   marked CONFIG_BROKEN), an oops, a hang, data corruption, a real
+   security issue, or some "oh, that's not good" issue.  In short,
+   something critical.
+ - No "theoretical race condition" issues, unless an explanation of how
+   the race can be exploited.
+ - It can not contain any "trivial" fixes in it (spelling changes,
+   whitespace cleanups, etc.)
+ - It must be accepted by the relevant subsystem maintainer.
+ - It must follow Documentation/SubmittingPatches rules.
+
+
+Procedure for submitting patches to the -stable tree:
+
+ - Send the patch, after verifying that it follows the above rules, to
+   stable@kernel.org.
+ - The sender will receive an ack when the patch has been accepted into
+   the queue, or a nak if the patch is rejected.  This response might
+   take a few days, according to the developer's schedules.
+ - If accepted, the patch will be added to the -stable queue, for review
+   by other developers.
+ - Security patches should not be sent to this alias, but instead to the
+   documented security@kernel.org.
+
+
+Review cycle:
+
+ - When the -stable maintainers decide for a review cycle, the patches
+   will be sent to the review committee, and the maintainer of the
+   affected area of the patch (unless the submitter is the maintainer of
+   the area) and CC: to the linux-kernel mailing list.
+ - The review committee has 48 hours in which to ack or nak the patch.
+ - If the patch is rejected by a member of the committee, or linux-kernel
+   members object to the patch, bringing up issues that the maintainers
+   and members did not realize, the patch will be dropped from the
+   queue.
+ - At the end of the review cycle, the acked patches will be added to
+   the latest -stable release, and a new -stable release will happen.
+ - Security patches will be accepted into the -stable tree directly from
+   the security kernel team, and not go through the normal review cycle.
+   Contact the kernel security team for more details on this procedure.
+
+
+Review committe:
+
+ - This will be made up of a number of kernel developers who have
+   volunteered for this task, and a few that haven't.
+
diff --git a/Documentation/usb/usbmon.txt b/Documentation/usb/usbmon.txt
index f1896ee3bb2..63cb7edd177 100644
--- a/Documentation/usb/usbmon.txt
+++ b/Documentation/usb/usbmon.txt
@@ -102,7 +102,7 @@ Here is the list of words, from left to right:
 - URB Status. This field makes no sense for submissions, but is present
   to help scripts with parsing. In error case, it contains the error code.
   In case of a setup packet, it contains a Setup Tag. If scripts read a number
-  in this field, the proceed to read Data Length. Otherwise, they read
+  in this field, they proceed to read Data Length. Otherwise, they read
   the setup packet before reading the Data Length.
 - Setup packet, if present, consists of 5 words: one of each for bmRequestType,
   bRequest, wValue, wIndex, wLength, as specified by the USB Specification 2.0.
diff --git a/Documentation/video4linux/CARDLIST.cx88 b/Documentation/video4linux/CARDLIST.cx88
index 6d44958289d..03deb0726aa 100644
--- a/Documentation/video4linux/CARDLIST.cx88
+++ b/Documentation/video4linux/CARDLIST.cx88
@@ -29,3 +29,4 @@ card=27 - PixelView PlayTV Ultra Pro (Stereo)
 card=28 - DViCO FusionHDTV 3 Gold-T
 card=29 - ADS Tech Instant TV DVB-T PCI
 card=30 - TerraTec Cinergy 1400 DVB-T
+card=31 - DViCO FusionHDTV 5 Gold
diff --git a/Documentation/video4linux/CARDLIST.tuner b/Documentation/video4linux/CARDLIST.tuner
index d1b9d21ffd8..f3302e1b1b9 100644
--- a/Documentation/video4linux/CARDLIST.tuner
+++ b/Documentation/video4linux/CARDLIST.tuner
@@ -62,3 +62,5 @@ tuner=60 - Thomson DDT 7611 (ATSC/NTSC)
 tuner=61 - Tena TNF9533-D/IF/TNF9533-B/DF
 tuner=62 - Philips TEA5767HN FM Radio
 tuner=63 - Philips FMD1216ME MK3 Hybrid Tuner
+tuner=64 - LG TDVS-H062F/TUA6034
+tuner=65 - Ymec TVF66T5-B/DFF
diff --git a/Documentation/video4linux/bttv/Insmod-options b/Documentation/video4linux/bttv/Insmod-options
index 7bb5a50b077..fc94ff235ff 100644
--- a/Documentation/video4linux/bttv/Insmod-options
+++ b/Documentation/video4linux/bttv/Insmod-options
@@ -44,6 +44,9 @@ bttv.o
 				push used by bttv.  bttv will disable overlay
 				by default on this hardware to avoid crashes.
 				With this insmod option you can override this.
+		no_overlay=1	Disable overlay. It should be used by broken
+				hardware that doesn't support PCI2PCI direct
+				transfers.
 		automute=0/1	Automatically mutes the sound if there is
 				no TV signal, on by default.  You might try
 				to disable this if you have bad input signal
diff --git a/Documentation/x86_64/boot-options.txt b/Documentation/x86_64/boot-options.txt
index b9e6be00cad..678e8f192db 100644
--- a/Documentation/x86_64/boot-options.txt
+++ b/Documentation/x86_64/boot-options.txt
@@ -6,6 +6,11 @@ only the AMD64 specific ones are listed here.
 Machine check
 
    mce=off disable machine check
+   mce=bootlog Enable logging of machine checks left over from booting.
+               Disabled by default because some BIOS leave bogus ones.
+               If your BIOS doesn't do that it's a good idea to enable though
+               to make sure you log even machine check events that result
+               in a reboot.
 
    nomce (for compatibility with i386): same as mce=off
 
@@ -47,7 +52,7 @@ Timing
   notsc
   Don't use the CPU time stamp counter to read the wall time.
   This can be used to work around timing problems on multiprocessor systems
-  with not properly synchronized CPUs. Only useful with a SMP kernel
+  with not properly synchronized CPUs.
 
   report_lost_ticks
   Report when timer interrupts are lost because some code turned off
@@ -74,6 +79,9 @@ Idle loop
   event. This will make the CPUs eat a lot more power, but may be useful
   to get slightly better performance in multiprocessor benchmarks. It also
   makes some profiling using performance counters more accurate.
+  Please note that on systems with MONITOR/MWAIT support (like Intel EM64T
+  CPUs) this option has no performance advantage over the normal idle loop.
+  It may also interact badly with hyperthreading.
 
 Rebooting
 
@@ -178,6 +186,5 @@ Debugging
 Misc
 
   noreplacement  Don't replace instructions with more appropiate ones
-  				 for the CPU. This may be useful on asymmetric MP systems
-				 where some CPU have less capabilities than the others.
-
+		 for the CPU. This may be useful on asymmetric MP systems
+		 where some CPU have less capabilities than the others.
diff --git a/MAINTAINERS b/MAINTAINERS
index 6d187fb934f..ac594d26d69 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1524,6 +1524,12 @@ P:	Zach Brown
 M:	zab@zabbo.net
 S:	Odd Fixes
 
+MAN-PAGES: MANUAL PAGES FOR LINUX -- Sections 2, 3, 4, 5, and 7
+P: Michael Kerrisk
+M: mtk-manpages@gmx.net
+W: ftp://ftp.kernel.org/pub/linux/docs/manpages
+S: Maintained
+
 MARVELL MV64340 ETHERNET DRIVER
 P:	Manish Lachwani
 M:	Manish_Lachwani@pmc-sierra.com
@@ -1655,7 +1661,7 @@ M:	kuznet@ms2.inr.ac.ru
 P:	Pekka Savola (ipv6)
 M:	pekkas@netcore.fi
 P:	James Morris
-M:	jmorris@redhat.com
+M:	jmorris@namei.org
 P:	Hideaki YOSHIFUJI
 M:	yoshfuji@linux-ipv6.org
 P:	Patrick McHardy
@@ -2044,7 +2050,7 @@ SELINUX SECURITY MODULE
 P:	Stephen Smalley
 M:	sds@epoch.ncsc.mil
 P:	James Morris
-M:	jmorris@redhat.com
+M:	jmorris@namei.org
 L:	linux-kernel@vger.kernel.org (kernel issues)
 L: 	selinux@tycho.nsa.gov (general discussion)
 W:	http://www.nsa.gov/selinux
diff --git a/Makefile b/Makefile
index cf34a6b5c6e..2c1486159d8 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 6
 SUBLEVEL = 13
-EXTRAVERSION =-rc3
+EXTRAVERSION =-rc6
 NAME=Woozy Numbat
 
 # *DOCUMENTATION*
diff --git a/README b/README
index 0df20f07227..76dd780d88e 100644
--- a/README
+++ b/README
@@ -87,6 +87,16 @@ INSTALLING the kernel:
    kernel source.  Patches are applied from the current directory, but
    an alternative directory can be specified as the second argument.
 
+ - If you are upgrading between releases using the stable series patches
+   (for example, patch-2.6.xx.y), note that these "dot-releases" are
+   not incremental and must be applied to the 2.6.xx base tree. For
+   example, if your base kernel is 2.6.12 and you want to apply the
+   2.6.12.3 patch, you do not and indeed must not first apply the
+   2.6.12.1 and 2.6.12.2 patches. Similarly, if you are running kernel
+   version 2.6.12.2 and want to jump to 2.6.12.3, you must first
+   reverse the 2.6.12.2 patch (that is, patch -R) _before_ applying
+   the 2.6.12.3 patch.
+
  - Make sure you have no stale .o files and dependencies lying around:
 
 		cd linux
diff --git a/REPORTING-BUGS b/REPORTING-BUGS
index 2045eaea2d9..224c34741d3 100644
--- a/REPORTING-BUGS
+++ b/REPORTING-BUGS
@@ -41,18 +41,19 @@ summary from [1.]>" for easy identification by the developers
 [2.] Full description of the problem/report:
 [3.] Keywords (i.e., modules, networking, kernel):
 [4.] Kernel version (from /proc/version):
-[5.] Output of Oops.. message (if applicable) with symbolic information 
+[5.] Most recent kernel version which did not have the bug:
+[6.] Output of Oops.. message (if applicable) with symbolic information
      resolved (see Documentation/oops-tracing.txt)
-[6.] A small shell script or example program which triggers the
+[7.] A small shell script or example program which triggers the
      problem (if possible)
-[7.] Environment
-[7.1.] Software (add the output of the ver_linux script here)
-[7.2.] Processor information (from /proc/cpuinfo):
-[7.3.] Module information (from /proc/modules):
-[7.4.] Loaded driver and hardware information (/proc/ioports, /proc/iomem)
-[7.5.] PCI information ('lspci -vvv' as root)
-[7.6.] SCSI information (from /proc/scsi/scsi)
-[7.7.] Other information that might be relevant to the problem
+[8.] Environment
+[8.1.] Software (add the output of the ver_linux script here)
+[8.2.] Processor information (from /proc/cpuinfo):
+[8.3.] Module information (from /proc/modules):
+[8.4.] Loaded driver and hardware information (/proc/ioports, /proc/iomem)
+[8.5.] PCI information ('lspci -vvv' as root)
+[8.6.] SCSI information (from /proc/scsi/scsi)
+[8.7.] Other information that might be relevant to the problem
        (please look in /proc and include all information that you
        think to be relevant):
 [X.] Other notes, patches, fixes, workarounds:
diff --git a/arch/alpha/kernel/pci.c b/arch/alpha/kernel/pci.c
index 1f36bbd0ed5..2a8b364c822 100644
--- a/arch/alpha/kernel/pci.c
+++ b/arch/alpha/kernel/pci.c
@@ -350,8 +350,24 @@ pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 	region->end = res->end - offset;
 }
 
+void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+			     struct pci_bus_region *region)
+{
+	struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
+	unsigned long offset = 0;
+
+	if (res->flags & IORESOURCE_IO)
+		offset = hose->io_space->start;
+	else if (res->flags & IORESOURCE_MEM)
+		offset = hose->mem_space->start;
+
+	res->start = region->start + offset;
+	res->end = region->end + offset;
+}
+
 #ifdef CONFIG_HOTPLUG
 EXPORT_SYMBOL(pcibios_resource_to_bus);
+EXPORT_SYMBOL(pcibios_bus_to_resource);
 #endif
 
 int
diff --git a/arch/alpha/kernel/systbls.S b/arch/alpha/kernel/systbls.S
index 05212088287..4342cea1a92 100644
--- a/arch/alpha/kernel/systbls.S
+++ b/arch/alpha/kernel/systbls.S
@@ -461,6 +461,11 @@ sys_call_table:
 	.quad sys_add_key
 	.quad sys_request_key			/* 440 */
 	.quad sys_keyctl
+	.quad sys_ioprio_set
+	.quad sys_ioprio_get
+	.quad sys_inotify_init
+	.quad sys_inotify_add_watch		/* 445 */
+	.quad sys_inotify_rm_watch
 
 	.size sys_call_table, . - sys_call_table
 	.type sys_call_table, @object
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index ad26e98f1e6..c4923fac8df 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -447,9 +447,26 @@ pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 	region->end   = res->end - offset;
 }
 
+void __devinit
+pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+			struct pci_bus_region *region)
+{
+	struct pci_sys_data *root = dev->sysdata;
+	unsigned long offset = 0;
+
+	if (res->flags & IORESOURCE_IO)
+		offset = root->io_offset;
+	if (res->flags & IORESOURCE_MEM)
+		offset = root->mem_offset;
+
+	res->start = region->start + offset;
+	res->end   = region->end + offset;
+}
+
 #ifdef CONFIG_HOTPLUG
 EXPORT_SYMBOL(pcibios_fixup_bus);
 EXPORT_SYMBOL(pcibios_resource_to_bus);
+EXPORT_SYMBOL(pcibios_bus_to_resource);
 #endif
 
 /*
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 295e0a8379c..b2085735a2b 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -176,6 +176,7 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
 	cpu_set(cpu, mm->cpu_vm_mask);
 	cpu_switch_mm(mm->pgd, mm);
 	enter_lazy_tlb(mm, current);
+	local_flush_tlb_all();
 
 	cpu_init();
 
diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h
index 6976e60e47c..2036ff15bda 100644
--- a/arch/arm/lib/bitops.h
+++ b/arch/arm/lib/bitops.h
@@ -7,7 +7,7 @@
 1:	ldrexb	r2, [r1]
 	\instr	r2, r2, r3
 	strexb	r0, r2, [r1]
-	cmpne	r0, #0
+	cmp	r0, #0
 	bne	1b
 	mov	pc, lr
 	.endm
@@ -19,9 +19,9 @@
 	mov	r3, r2, lsl r3		@ create mask
 1:	ldrexb	r2, [r1]
 	ands	r0, r2, r3		@ save old value of bit
-	\instr	ip, r2, r3			@ toggle bit
-	strexb	r2, ip, [r1]
-	cmp	r2, #0
+	\instr	r2, r2, r3			@ toggle bit
+	strexb	ip, r2, [r1]
+	cmp	ip, #0
 	bne	1b
 	cmp	r0, #0
 	movne	r0, #1
diff --git a/arch/arm/mach-integrator/platsmp.c b/arch/arm/mach-integrator/platsmp.c
index aecf47ba033..ea10bd8c972 100644
--- a/arch/arm/mach-integrator/platsmp.c
+++ b/arch/arm/mach-integrator/platsmp.c
@@ -15,6 +15,7 @@
 #include <linux/mm.h>
 
 #include <asm/atomic.h>
+#include <asm/cacheflush.h>
 #include <asm/delay.h>
 #include <asm/mmu_context.h>
 #include <asm/procinfo.h>
@@ -80,6 +81,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 	 * "cpu" is Linux's internal ID.
 	 */
 	pen_release = cpu;
+	flush_cache_all();
 
 	/*
 	 * XXX
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c
index 4ff4393ef0e..7f58afb27e7 100644
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -61,7 +61,7 @@ static struct plat_serial8250_port coyote_uart_data[] = {
 		.mapbase	= IXP4XX_UART2_BASE_PHYS,
 		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
 		.irq		= IRQ_IXP4XX_UART2,
-		.flags		= UPF_BOOT_AUTOCONF,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
 		.uartclk	= IXP4XX_UART_XTAL,
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
index 8ba1cd9406e..65e356bd10d 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -83,7 +83,7 @@ static struct plat_serial8250_port gtwx5715_uart_platform_data[] = {
 	.mapbase	= IXP4XX_UART2_BASE_PHYS,
 	.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
 	.irq		= IRQ_IXP4XX_UART2,
-	.flags		= UPF_BOOT_AUTOCONF,
+	.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 	.iotype		= UPIO_MEM,
 	.regshift	= 2,
 	.uartclk	= IXP4XX_UART_XTAL,
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index c2ba759e994..4633470a6a3 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -82,7 +82,7 @@ static struct plat_serial8250_port ixdp425_uart_data[] = {
 		.mapbase	= IXP4XX_UART1_BASE_PHYS,
 		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
 		.irq		= IRQ_IXP4XX_UART1,
-		.flags		= UPF_BOOT_AUTOCONF,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
 		.uartclk	= IXP4XX_UART_XTAL,
@@ -91,7 +91,7 @@ static struct plat_serial8250_port ixdp425_uart_data[] = {
 		.mapbase	= IXP4XX_UART2_BASE_PHYS,
 		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
 		.irq		= IRQ_IXP4XX_UART1,
-		.flags		= UPF_BOOT_AUTOCONF,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
 		.uartclk	= IXP4XX_UART_XTAL,
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 1e7f343822d..e9182242da9 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -30,6 +30,7 @@
  *     28-Jun-2005 BJD  Moved pm functionality out to common code
  *     17-Jul-2005 BJD  Changed to platform device for SuperIO 16550s
  *     25-Jul-2005 BJD  Removed ASIX static mappings
+ *     27-Jul-2005 BJD  Ensure maximum frequency of i2c bus
 */
 
 #include <linux/kernel.h>
@@ -60,6 +61,7 @@
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
 #include <asm/arch/nand.h>
+#include <asm/arch/iic.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
@@ -304,7 +306,7 @@ static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
 }
 
 static struct s3c2410_platform_nand bast_nand_info = {
-	.tacls		= 80,
+	.tacls		= 40,
 	.twrph0		= 80,
 	.twrph1		= 80,
 	.nr_sets	= ARRAY_SIZE(bast_nand_sets),
@@ -385,6 +387,17 @@ static struct platform_device bast_sio = {
 	},
 };
 
+/* we have devices on the bus which cannot work much over the
+ * standard 100KHz i2c bus frequency
+*/
+
+static struct s3c2410_platform_i2c bast_i2c_info = {
+	.flags		= 0,
+	.slave_addr	= 0x10,
+	.bus_freq	= 100*1000,
+	.max_freq	= 130*1000,
+};
+
 /* Standard BAST devices */
 
 static struct platform_device *bast_devices[] __initdata = {
@@ -431,6 +444,7 @@ void __init bast_map_io(void)
 	s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 
 	s3c_device_nand.dev.platform_data = &bast_nand_info;
+	s3c_device_i2c.dev.platform_data = &bast_i2c_info;
 
 	s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
 	s3c24xx_init_clocks(0);
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c
index eee3cbc5ec4..2f497112c96 100644
--- a/arch/arm/mach-sa1100/jornada720.c
+++ b/arch/arm/mach-sa1100/jornada720.c
@@ -97,6 +97,7 @@ static void __init jornada720_map_io(void)
 }
 
 MACHINE_START(JORNADA720, "HP Jornada 720")
+	/* Maintainer: Michael Gernoth <michael@gernoth.net> */
 	.phys_ram	= 0xc0000000,
 	.phys_io	= 0x80000000,
 	.io_pg_offst	= ((0xf8000000) >> 18) & 0xfffc,
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 65bfe84b6d6..0b6c4db44e0 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -238,9 +238,9 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 	up_read(&mm->mmap_sem);
 
 	/*
-	 * Handle the "normal" case first
+	 * Handle the "normal" case first - VM_FAULT_MAJOR / VM_FAULT_MINOR
 	 */
-	if (fault > 0)
+	if (fault >= VM_FAULT_MINOR)
 		return 0;
 
 	/*
@@ -261,7 +261,7 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 		do_exit(SIGKILL);
 		return 0;
 
-	case 0:
+	case VM_FAULT_SIGBUS:
 		/*
 		 * We had some memory, but were unable to
 		 * successfully fix up this page fault.
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 2d977b4eeea..b88de270014 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -370,142 +370,6 @@ ENTRY(cpu_xscale_dcache_clean_area)
 	bhi	1b
 	mov	pc, lr
 
-/* ================================ CACHE LOCKING============================
- *
- * The XScale MicroArchitecture implements support for locking entries into
- * the data and instruction cache.  The following functions implement the core
- * low level instructions needed to accomplish the locking.  The developer's
- * manual states that the code that performs the locking must be in non-cached
- * memory.  To accomplish this, the code in xscale-cache-lock.c copies the
- * following functions from the cache into a non-cached memory region that
- * is allocated through consistent_alloc().
- *
- */
-	.align	5
-/*
- * xscale_icache_lock
- *
- * r0: starting address to lock
- * r1: end address to lock
- */
-ENTRY(xscale_icache_lock)
-
-iLockLoop:
-	bic	r0, r0, #CACHELINESIZE - 1
-	mcr	p15, 0, r0, c9, c1, 0	@ lock into cache
-	cmp	r0, r1			@ are we done?
-	add	r0, r0, #CACHELINESIZE	@ advance to next cache line
-	bls	iLockLoop
-	mov	pc, lr
-
-/*
- * xscale_icache_unlock
- */
-ENTRY(xscale_icache_unlock)
-	mcr	p15, 0, r0, c9, c1, 1	@ Unlock icache
-	mov	pc, lr
-
-/*
- * xscale_dcache_lock
- *
- * r0: starting address to lock
- * r1: end address to lock
- */
-ENTRY(xscale_dcache_lock)
-	mcr	p15, 0, ip, c7, c10, 4		@ Drain Write (& Fill) Buffer
-	mov	r2, #1
-	mcr	p15, 0, r2, c9, c2, 0	@ Put dcache in lock mode
-	cpwait	ip			@ Wait for completion
-
-	mrs	r2, cpsr
-	orr	r3, r2, #PSR_F_BIT | PSR_I_BIT
-dLockLoop:
-	msr	cpsr_c, r3
-	mcr	p15, 0, r0, c7, c10, 1	@ Write back line if it is dirty
-	mcr	p15, 0, r0, c7, c6, 1	@ Flush/invalidate line
-	msr	cpsr_c, r2
-	ldr	ip, [r0], #CACHELINESIZE @ Preload 32 bytes into cache from
-					@ location [r0]. Post-increment
-					@ r3 to next cache line
-	cmp	r0, r1			@ Are we done?
-	bls	dLockLoop
-
-	mcr	p15, 0, ip, c7, c10, 4		@ Drain Write (& Fill) Buffer
-	mov	r2, #0
-	mcr	p15, 0, r2, c9, c2, 0	@ Get out of lock mode
-	cpwait_ret lr, ip
-
-/*
- * xscale_dcache_unlock
- */
-ENTRY(xscale_dcache_unlock)
-	mcr	p15, 0, ip, c7, c10, 4		@ Drain Write (& Fill) Buffer
-	mcr	p15, 0, ip, c9, c2, 1	@ Unlock cache
-	mov	pc, lr
-
-/*
- * Needed to determine the length of the code that needs to be copied.
- */
-	.align	5
-ENTRY(xscale_cache_dummy)
-	mov	pc, lr
-
-/* ================================ TLB LOCKING==============================
- *
- * The XScale MicroArchitecture implements support for locking entries into
- * the Instruction and Data TLBs.  The following functions provide the
- * low level support for supporting these under Linux.  xscale-lock.c
- * implements some higher level management code.  Most of the following
- * is taken straight out of the Developer's Manual.
- */
-
-/*
- * Lock I-TLB entry
- *
- * r0: Virtual address to translate and lock
- */
-	.align	5
-ENTRY(xscale_itlb_lock)
-	mrs	r2, cpsr
-	orr	r3, r2, #PSR_F_BIT | PSR_I_BIT
-	msr	cpsr_c, r3			@ Disable interrupts
-	mcr	p15, 0, r0, c8, c5, 1		@ Invalidate I-TLB entry
-	mcr	p15, 0, r0, c10, c4, 0		@ Translate and lock
-	msr	cpsr_c, r2			@ Restore interrupts
-	cpwait_ret lr, ip
-
-/*
- * Lock D-TLB entry
- *
- * r0: Virtual address to translate and lock
- */
-	.align	5
-ENTRY(xscale_dtlb_lock)
-	mrs	r2, cpsr
-	orr	r3, r2, #PSR_F_BIT | PSR_I_BIT
-	msr	cpsr_c, r3			@ Disable interrupts
-	mcr	p15, 0, r0, c8, c6, 1		@ Invalidate D-TLB entry
-	mcr	p15, 0, r0, c10, c8, 0		@ Translate and lock
-	msr	cpsr_c, r2			@ Restore interrupts
-	cpwait_ret lr, ip
-
-/*
- * Unlock all I-TLB entries
- */
-	.align	5
-ENTRY(xscale_itlb_unlock)
-	mcr	p15, 0, ip, c10, c4, 1		@ Unlock I-TLB
-	mcr	p15, 0, ip, c8, c5, 0		@ Invalidate I-TLB
-	cpwait_ret lr, ip
-
-/*
- * Unlock all D-TLB entries
- */
-ENTRY(xscale_dtlb_unlock)
-	mcr	p15, 0, ip, c10, c8, 1		@ Unlock D-TBL
-	mcr	p15, 0, ip, c8, c6, 0		@ Invalidate D-TLB
-	cpwait_ret lr, ip
-
 /* =============================== PageTable ============================== */
 
 #define PTE_CACHE_WRITE_ALLOCATE 0
diff --git a/arch/arm/nwfpe/double_cpdo.c b/arch/arm/nwfpe/double_cpdo.c
index 7ffd8cb9bc9..c51d1386a97 100644
--- a/arch/arm/nwfpe/double_cpdo.c
+++ b/arch/arm/nwfpe/double_cpdo.c
@@ -40,17 +40,17 @@ float64 float64_arccos(float64 rFm);
 float64 float64_pow(float64 rFn, float64 rFm);
 float64 float64_pol(float64 rFn, float64 rFm);
 
-static float64 float64_rsf(float64 rFn, float64 rFm)
+static float64 float64_rsf(struct roundingData *roundData, float64 rFn, float64 rFm)
 {
-	return float64_sub(rFm, rFn);
+	return float64_sub(roundData, rFm, rFn);
 }
 
-static float64 float64_rdv(float64 rFn, float64 rFm)
+static float64 float64_rdv(struct roundingData *roundData, float64 rFn, float64 rFm)
 {
-	return float64_div(rFm, rFn);
+	return float64_div(roundData, rFm, rFn);
 }
 
-static float64 (*const dyadic_double[16])(float64 rFn, float64 rFm) = {
+static float64 (*const dyadic_double[16])(struct roundingData*, float64 rFn, float64 rFm) = {
 	[ADF_CODE >> 20] = float64_add,
 	[MUF_CODE >> 20] = float64_mul,
 	[SUF_CODE >> 20] = float64_sub,
@@ -65,12 +65,12 @@ static float64 (*const dyadic_double[16])(float64 rFn, float64 rFm) = {
 	[FRD_CODE >> 20] = float64_rdv,
 };
 
-static float64 float64_mvf(float64 rFm)
+static float64 float64_mvf(struct roundingData *roundData,float64 rFm)
 {
 	return rFm;
 }
 
-static float64 float64_mnf(float64 rFm)
+static float64 float64_mnf(struct roundingData *roundData,float64 rFm)
 {
 	union float64_components u;
 
@@ -84,7 +84,7 @@ static float64 float64_mnf(float64 rFm)
 	return u.f64;
 }
 
-static float64 float64_abs(float64 rFm)
+static float64 float64_abs(struct roundingData *roundData,float64 rFm)
 {
 	union float64_components u;
 
@@ -98,7 +98,7 @@ static float64 float64_abs(float64 rFm)
 	return u.f64;
 }
 
-static float64 (*const monadic_double[16])(float64 rFm) = {
+static float64 (*const monadic_double[16])(struct roundingData *, float64 rFm) = {
 	[MVF_CODE >> 20] = float64_mvf,
 	[MNF_CODE >> 20] = float64_mnf,
 	[ABS_CODE >> 20] = float64_abs,
@@ -108,7 +108,7 @@ static float64 (*const monadic_double[16])(float64 rFm) = {
 	[NRM_CODE >> 20] = float64_mvf,
 };
 
-unsigned int DoubleCPDO(const unsigned int opcode, FPREG * rFd)
+unsigned int DoubleCPDO(struct roundingData *roundData, const unsigned int opcode, FPREG * rFd)
 {
 	FPA11 *fpa11 = GET_FPA11();
 	float64 rFm;
@@ -151,13 +151,13 @@ unsigned int DoubleCPDO(const unsigned int opcode, FPREG * rFd)
 		}
 
 		if (dyadic_double[opc_mask_shift]) {
-			rFd->fDouble = dyadic_double[opc_mask_shift](rFn, rFm);
+			rFd->fDouble = dyadic_double[opc_mask_shift](roundData, rFn, rFm);
 		} else {
 			return 0;
 		}
 	} else {
 		if (monadic_double[opc_mask_shift]) {
-			rFd->fDouble = monadic_double[opc_mask_shift](rFm);
+			rFd->fDouble = monadic_double[opc_mask_shift](roundData, rFm);
 		} else {
 			return 0;
 		}
diff --git a/arch/arm/nwfpe/extended_cpdo.c b/arch/arm/nwfpe/extended_cpdo.c
index c39f68a3449..65a279ba927 100644
--- a/arch/arm/nwfpe/extended_cpdo.c
+++ b/arch/arm/nwfpe/extended_cpdo.c
@@ -35,17 +35,17 @@ floatx80 floatx80_arccos(floatx80 rFm);
 floatx80 floatx80_pow(floatx80 rFn, floatx80 rFm);
 floatx80 floatx80_pol(floatx80 rFn, floatx80 rFm);
 
-static floatx80 floatx80_rsf(floatx80 rFn, floatx80 rFm)
+static floatx80 floatx80_rsf(struct roundingData *roundData, floatx80 rFn, floatx80 rFm)
 {
-	return floatx80_sub(rFm, rFn);
+	return floatx80_sub(roundData, rFm, rFn);
 }
 
-static floatx80 floatx80_rdv(floatx80 rFn, floatx80 rFm)
+static floatx80 floatx80_rdv(struct roundingData *roundData, floatx80 rFn, floatx80 rFm)
 {
-	return floatx80_div(rFm, rFn);
+	return floatx80_div(roundData, rFm, rFn);
 }
 
-static floatx80 (*const dyadic_extended[16])(floatx80 rFn, floatx80 rFm) = {
+static floatx80 (*const dyadic_extended[16])(struct roundingData*, floatx80 rFn, floatx80 rFm) = {
 	[ADF_CODE >> 20] = floatx80_add,
 	[MUF_CODE >> 20] = floatx80_mul,
 	[SUF_CODE >> 20] = floatx80_sub,
@@ -60,24 +60,24 @@ static floatx80 (*const dyadic_extended[16])(floatx80 rFn, floatx80 rFm) = {
 	[FRD_CODE >> 20] = floatx80_rdv,
 };
 
-static floatx80 floatx80_mvf(floatx80 rFm)
+static floatx80 floatx80_mvf(struct roundingData *roundData, floatx80 rFm)
 {
 	return rFm;
 }
 
-static floatx80 floatx80_mnf(floatx80 rFm)
+static floatx80 floatx80_mnf(struct roundingData *roundData, floatx80 rFm)
 {
 	rFm.high ^= 0x8000;
 	return rFm;
 }
 
-static floatx80 floatx80_abs(floatx80 rFm)
+static floatx80 floatx80_abs(struct roundingData *roundData, floatx80 rFm)
 {
 	rFm.high &= 0x7fff;
 	return rFm;
 }
 
-static floatx80 (*const monadic_extended[16])(floatx80 rFm) = {
+static floatx80 (*const monadic_extended[16])(struct roundingData*, floatx80 rFm) = {
 	[MVF_CODE >> 20] = floatx80_mvf,
 	[MNF_CODE >> 20] = floatx80_mnf,
 	[ABS_CODE >> 20] = floatx80_abs,
@@ -87,7 +87,7 @@ static floatx80 (*const monadic_extended[16])(floatx80 rFm) = {
 	[NRM_CODE >> 20] = floatx80_mvf,
 };
 
-unsigned int ExtendedCPDO(const unsigned int opcode, FPREG * rFd)
+unsigned int ExtendedCPDO(struct roundingData *roundData, const unsigned int opcode, FPREG * rFd)
 {
 	FPA11 *fpa11 = GET_FPA11();
 	floatx80 rFm;
@@ -138,13 +138,13 @@ unsigned int ExtendedCPDO(const unsigned int opcode, FPREG * rFd)
 		}
 
 		if (dyadic_extended[opc_mask_shift]) {
-			rFd->fExtended = dyadic_extended[opc_mask_shift](rFn, rFm);
+			rFd->fExtended = dyadic_extended[opc_mask_shift](roundData, rFn, rFm);
 		} else {
 			return 0;
 		}
 	} else {
 		if (monadic_extended[opc_mask_shift]) {
-			rFd->fExtended = monadic_extended[opc_mask_shift](rFm);
+			rFd->fExtended = monadic_extended[opc_mask_shift](roundData, rFm);
 		} else {
 			return 0;
 		}
diff --git a/arch/arm/nwfpe/fpa11.c b/arch/arm/nwfpe/fpa11.c
index bf61696865e..7690f731ee8 100644
--- a/arch/arm/nwfpe/fpa11.c
+++ b/arch/arm/nwfpe/fpa11.c
@@ -51,48 +51,42 @@ static void resetFPA11(void)
 	fpa11->fpsr = FP_EMULATOR | BIT_AC;
 }
 
-void SetRoundingMode(const unsigned int opcode)
+int8 SetRoundingMode(const unsigned int opcode)
 {
 	switch (opcode & MASK_ROUNDING_MODE) {
 	default:
 	case ROUND_TO_NEAREST:
-		float_rounding_mode = float_round_nearest_even;
-		break;
+		return float_round_nearest_even;
 
 	case ROUND_TO_PLUS_INFINITY:
-		float_rounding_mode = float_round_up;
-		break;
+		return float_round_up;
 
 	case ROUND_TO_MINUS_INFINITY:
-		float_rounding_mode = float_round_down;
-		break;
+		return float_round_down;
 
 	case ROUND_TO_ZERO:
-		float_rounding_mode = float_round_to_zero;
-		break;
+		return float_round_to_zero;
 	}
 }
 
-void SetRoundingPrecision(const unsigned int opcode)
+int8 SetRoundingPrecision(const unsigned int opcode)
 {
 #ifdef CONFIG_FPE_NWFPE_XP
 	switch (opcode & MASK_ROUNDING_PRECISION) {
 	case ROUND_SINGLE:
-		floatx80_rounding_precision = 32;
-		break;
+		return 32;
 
 	case ROUND_DOUBLE:
-		floatx80_rounding_precision = 64;
-		break;
+		return 64;
 
 	case ROUND_EXTENDED:
-		floatx80_rounding_precision = 80;
-		break;
+		return 80;
 
 	default:
-		floatx80_rounding_precision = 80;
+		return 80;
 	}
 #endif
+	return 80;
 }
 
 void nwfpe_init_fpa(union fp_state *fp)
@@ -103,8 +97,6 @@ void nwfpe_init_fpa(union fp_state *fp)
 #endif
  	memset(fpa11, 0, sizeof(FPA11));
 	resetFPA11();
-	SetRoundingMode(ROUND_TO_NEAREST);
-	SetRoundingPrecision(ROUND_EXTENDED);
 	fpa11->initflag = 1;
 }
 
diff --git a/arch/arm/nwfpe/fpa11.h b/arch/arm/nwfpe/fpa11.h
index e4a61aea534..93523ae4b7a 100644
--- a/arch/arm/nwfpe/fpa11.h
+++ b/arch/arm/nwfpe/fpa11.h
@@ -37,6 +37,13 @@
 /* includes */
 #include "fpsr.h"		/* FP control and status register definitions */
 #include "milieu.h"
+
+struct roundingData {
+    int8 mode;
+    int8 precision;
+    signed char exception;
+};
+
 #include "softfloat.h"
 
 #define		typeNone		0x00
@@ -84,8 +91,8 @@ typedef struct tagFPA11 {
 				   initialised. */
 } FPA11;
 
-extern void SetRoundingMode(const unsigned int);
-extern void SetRoundingPrecision(const unsigned int);
+extern int8 SetRoundingMode(const unsigned int);
+extern int8 SetRoundingPrecision(const unsigned int);
 extern void nwfpe_init_fpa(union fp_state *fp);
 
 #endif
diff --git a/arch/arm/nwfpe/fpa11_cpdo.c b/arch/arm/nwfpe/fpa11_cpdo.c
index 1bea67437b6..4a31dfd9406 100644
--- a/arch/arm/nwfpe/fpa11_cpdo.c
+++ b/arch/arm/nwfpe/fpa11_cpdo.c
@@ -24,15 +24,16 @@
 #include "fpa11.h"
 #include "fpopcode.h"
 
-unsigned int SingleCPDO(const unsigned int opcode, FPREG * rFd);
-unsigned int DoubleCPDO(const unsigned int opcode, FPREG * rFd);
-unsigned int ExtendedCPDO(const unsigned int opcode, FPREG * rFd);
+unsigned int SingleCPDO(struct roundingData *roundData, const unsigned int opcode, FPREG * rFd);
+unsigned int DoubleCPDO(struct roundingData *roundData, const unsigned int opcode, FPREG * rFd);
+unsigned int ExtendedCPDO(struct roundingData *roundData, const unsigned int opcode, FPREG * rFd);
 
 unsigned int EmulateCPDO(const unsigned int opcode)
 {
 	FPA11 *fpa11 = GET_FPA11();
 	FPREG *rFd;
 	unsigned int nType, nDest, nRc;
+	struct roundingData roundData;
 
 	/* Get the destination size.  If not valid let Linux perform
 	   an invalid instruction trap. */
@@ -40,7 +41,9 @@ unsigned int EmulateCPDO(const unsigned int opcode)
 	if (typeNone == nDest)
 		return 0;
 
-	SetRoundingMode(opcode);
+	roundData.mode = SetRoundingMode(opcode);
+	roundData.precision = SetRoundingPrecision(opcode);
+	roundData.exception = 0;
 
 	/* Compare the size of the operands in Fn and Fm.
 	   Choose the largest size and perform operations in that size,
@@ -63,14 +66,14 @@ unsigned int EmulateCPDO(const unsigned int opcode)
 
 	switch (nType) {
 	case typeSingle:
-		nRc = SingleCPDO(opcode, rFd);
+		nRc = SingleCPDO(&roundData, opcode, rFd);
 		break;
 	case typeDouble:
-		nRc = DoubleCPDO(opcode, rFd);
+		nRc = DoubleCPDO(&roundData, opcode, rFd);
 		break;
 #ifdef CONFIG_FPE_NWFPE_XP
 	case typeExtended:
-		nRc = ExtendedCPDO(opcode, rFd);
+		nRc = ExtendedCPDO(&roundData, opcode, rFd);
 		break;
 #endif
 	default:
@@ -93,9 +96,9 @@ unsigned int EmulateCPDO(const unsigned int opcode)
 			case typeSingle:
 				{
 					if (typeDouble == nType)
-						rFd->fSingle = float64_to_float32(rFd->fDouble);
+						rFd->fSingle = float64_to_float32(&roundData, rFd->fDouble);
 					else
-						rFd->fSingle = floatx80_to_float32(rFd->fExtended);
+						rFd->fSingle = floatx80_to_float32(&roundData, rFd->fExtended);
 				}
 				break;
 
@@ -104,7 +107,7 @@ unsigned int EmulateCPDO(const unsigned int opcode)
 					if (typeSingle == nType)
 						rFd->fDouble = float32_to_float64(rFd->fSingle);
 					else
-						rFd->fDouble = floatx80_to_float64(rFd->fExtended);
+						rFd->fDouble = floatx80_to_float64(&roundData, rFd->fExtended);
 				}
 				break;
 
@@ -121,12 +124,15 @@ unsigned int EmulateCPDO(const unsigned int opcode)
 #else
 		if (nDest != nType) {
 			if (nDest == typeSingle)
-				rFd->fSingle = float64_to_float32(rFd->fDouble);
+				rFd->fSingle = float64_to_float32(&roundData, rFd->fDouble);
 			else
 				rFd->fDouble = float32_to_float64(rFd->fSingle);
 		}
 #endif
 	}
 
+	if (roundData.exception)
+		float_raise(roundData.exception);
+
 	return nRc;
 }
diff --git a/arch/arm/nwfpe/fpa11_cpdt.c b/arch/arm/nwfpe/fpa11_cpdt.c
index 95fb63fa9d1..b0db5cbcc3b 100644
--- a/arch/arm/nwfpe/fpa11_cpdt.c
+++ b/arch/arm/nwfpe/fpa11_cpdt.c
@@ -96,7 +96,7 @@ static inline void loadMultiple(const unsigned int Fn, const unsigned int __user
 	}
 }
 
-static inline void storeSingle(const unsigned int Fn, unsigned int __user *pMem)
+static inline void storeSingle(struct roundingData *roundData, const unsigned int Fn, unsigned int __user *pMem)
 {
 	FPA11 *fpa11 = GET_FPA11();
 	union {
@@ -106,12 +106,12 @@ static inline void storeSingle(const unsigned int Fn, unsigned int __user *pMem)
 
 	switch (fpa11->fType[Fn]) {
 	case typeDouble:
-		val.f = float64_to_float32(fpa11->fpreg[Fn].fDouble);
+		val.f = float64_to_float32(roundData, fpa11->fpreg[Fn].fDouble);
 		break;
 
 #ifdef CONFIG_FPE_NWFPE_XP
 	case typeExtended:
-		val.f = floatx80_to_float32(fpa11->fpreg[Fn].fExtended);
+		val.f = floatx80_to_float32(roundData, fpa11->fpreg[Fn].fExtended);
 		break;
 #endif
 
@@ -122,7 +122,7 @@ static inline void storeSingle(const unsigned int Fn, unsigned int __user *pMem)
 	put_user(val.i[0], pMem);
 }
 
-static inline void storeDouble(const unsigned int Fn, unsigned int __user *pMem)
+static inline void storeDouble(struct roundingData *roundData, const unsigned int Fn, unsigned int __user *pMem)
 {
 	FPA11 *fpa11 = GET_FPA11();
 	union {
@@ -137,7 +137,7 @@ static inline void storeDouble(const unsigned int Fn, unsigned int __user *pMem)
 
 #ifdef CONFIG_FPE_NWFPE_XP
 	case typeExtended:
-		val.f = floatx80_to_float64(fpa11->fpreg[Fn].fExtended);
+		val.f = floatx80_to_float64(roundData, fpa11->fpreg[Fn].fExtended);
 		break;
 #endif
 
@@ -259,8 +259,11 @@ unsigned int PerformSTF(const unsigned int opcode)
 {
 	unsigned int __user *pBase, *pAddress, *pFinal;
 	unsigned int nRc = 1, write_back = WRITE_BACK(opcode);
+	struct roundingData roundData;
 
-	SetRoundingMode(ROUND_TO_NEAREST);
+	roundData.mode = SetRoundingMode(opcode);
+	roundData.precision = SetRoundingPrecision(opcode);
+	roundData.exception = 0;
 
 	pBase = (unsigned int __user *) readRegister(getRn(opcode));
 	if (REG_PC == getRn(opcode)) {
@@ -281,10 +284,10 @@ unsigned int PerformSTF(const unsigned int opcode)
 
 	switch (opcode & MASK_TRANSFER_LENGTH) {
 	case TRANSFER_SINGLE:
-		storeSingle(getFd(opcode), pAddress);
+		storeSingle(&roundData, getFd(opcode), pAddress);
 		break;
 	case TRANSFER_DOUBLE:
-		storeDouble(getFd(opcode), pAddress);
+		storeDouble(&roundData, getFd(opcode), pAddress);
 		break;
 #ifdef CONFIG_FPE_NWFPE_XP
 	case TRANSFER_EXTENDED:
@@ -295,6 +298,9 @@ unsigned int PerformSTF(const unsigned int opcode)
 		nRc = 0;
 	}
 
+	if (roundData.exception)
+		float_raise(roundData.exception);
+
 	if (write_back)
 		writeRegister(getRn(opcode), (unsigned long) pFinal);
 	return nRc;
diff --git a/arch/arm/nwfpe/fpa11_cprt.c b/arch/arm/nwfpe/fpa11_cprt.c
index db01fbc9721..adf8d300054 100644
--- a/arch/arm/nwfpe/fpa11_cprt.c
+++ b/arch/arm/nwfpe/fpa11_cprt.c
@@ -33,8 +33,6 @@ extern flag floatx80_is_nan(floatx80);
 extern flag float64_is_nan(float64);
 extern flag float32_is_nan(float32);
 
-void SetRoundingMode(const unsigned int opcode);
-
 unsigned int PerformFLT(const unsigned int opcode);
 unsigned int PerformFIX(const unsigned int opcode);
 
@@ -77,14 +75,17 @@ unsigned int EmulateCPRT(const unsigned int opcode)
 unsigned int PerformFLT(const unsigned int opcode)
 {
 	FPA11 *fpa11 = GET_FPA11();
-	SetRoundingMode(opcode);
-	SetRoundingPrecision(opcode);
+	struct roundingData roundData;
+
+	roundData.mode = SetRoundingMode(opcode);
+	roundData.precision = SetRoundingPrecision(opcode);
+	roundData.exception = 0;
 
 	switch (opcode & MASK_ROUNDING_PRECISION) {
 	case ROUND_SINGLE:
 		{
 			fpa11->fType[getFn(opcode)] = typeSingle;
-			fpa11->fpreg[getFn(opcode)].fSingle = int32_to_float32(readRegister(getRd(opcode)));
+			fpa11->fpreg[getFn(opcode)].fSingle = int32_to_float32(&roundData, readRegister(getRd(opcode)));
 		}
 		break;
 
@@ -108,6 +109,9 @@ unsigned int PerformFLT(const unsigned int opcode)
 		return 0;
 	}
 
+	if (roundData.exception)
+		float_raise(roundData.exception);
+
 	return 1;
 }
 
@@ -115,26 +119,29 @@ unsigned int PerformFIX(const unsigned int opcode)
 {
 	FPA11 *fpa11 = GET_FPA11();
 	unsigned int Fn = getFm(opcode);
+	struct roundingData roundData;
 
-	SetRoundingMode(opcode);
+	roundData.mode = SetRoundingMode(opcode);
+	roundData.precision = SetRoundingPrecision(opcode);
+	roundData.exception = 0;
 
 	switch (fpa11->fType[Fn]) {
 	case typeSingle:
 		{
-			writeRegister(getRd(opcode), float32_to_int32(fpa11->fpreg[Fn].fSingle));
+			writeRegister(getRd(opcode), float32_to_int32(&roundData, fpa11->fpreg[Fn].fSingle));
 		}
 		break;
 
 	case typeDouble:
 		{
-			writeRegister(getRd(opcode), float64_to_int32(fpa11->fpreg[Fn].fDouble));
+			writeRegister(getRd(opcode), float64_to_int32(&roundData, fpa11->fpreg[Fn].fDouble));
 		}
 		break;
 
 #ifdef CONFIG_FPE_NWFPE_XP
 	case typeExtended:
 		{
-			writeRegister(getRd(opcode), floatx80_to_int32(fpa11->fpreg[Fn].fExtended));
+			writeRegister(getRd(opcode), floatx80_to_int32(&roundData, fpa11->fpreg[Fn].fExtended));
 		}
 		break;
 #endif
@@ -143,6 +150,9 @@ unsigned int PerformFIX(const unsigned int opcode)
 		return 0;
 	}
 
+	if (roundData.exception)
+		float_raise(roundData.exception);
+
 	return 1;
 }
 
diff --git a/arch/arm/nwfpe/fpmodule.c b/arch/arm/nwfpe/fpmodule.c
index 12885f31d34..2dfe1ac42ee 100644
--- a/arch/arm/nwfpe/fpmodule.c
+++ b/arch/arm/nwfpe/fpmodule.c
@@ -116,8 +116,6 @@ fpmodule.c to integrate with the NetBSD kernel (I hope!).
 code to access data in user space in some other source files at the 
 moment (grep for get_user / put_user calls).  --philb]
 
-float_exception_flags is a global variable in SoftFloat.
-
 This function is called by the SoftFloat routines to raise a floating
 point exception.  We check the trap enable byte in the FPSR, and raise
 a SIGFPE exception if necessary.  If not the relevant bits in the 
@@ -129,15 +127,14 @@ void float_raise(signed char flags)
 	register unsigned int fpsr, cumulativeTraps;
 
 #ifdef CONFIG_DEBUG_USER
-	printk(KERN_DEBUG
-	       "NWFPE: %s[%d] takes exception %08x at %p from %08lx\n",
-	       current->comm, current->pid, flags,
-	       __builtin_return_address(0), GET_USERREG()->ARM_pc);
+ 	/* Ignore inexact errors as there are far too many of them to log */
+ 	if (flags & ~BIT_IXC)
+ 		printk(KERN_DEBUG
+		       "NWFPE: %s[%d] takes exception %08x at %p from %08lx\n",
+		       current->comm, current->pid, flags,
+		       __builtin_return_address(0), GET_USERREG()->ARM_pc);
 #endif
 
-	/* Keep SoftFloat exception flags up to date.  */
-	float_exception_flags |= flags;
-
 	/* Read fpsr and initialize the cumulativeTraps.  */
 	fpsr = readFPSR();
 	cumulativeTraps = 0;
diff --git a/arch/arm/nwfpe/single_cpdo.c b/arch/arm/nwfpe/single_cpdo.c
index 705808e88d9..c66981d682c 100644
--- a/arch/arm/nwfpe/single_cpdo.c
+++ b/arch/arm/nwfpe/single_cpdo.c
@@ -36,17 +36,17 @@ float32 float32_arccos(float32 rFm);
 float32 float32_pow(float32 rFn, float32 rFm);
 float32 float32_pol(float32 rFn, float32 rFm);
 
-static float32 float32_rsf(float32 rFn, float32 rFm)
+static float32 float32_rsf(struct roundingData *roundData, float32 rFn, float32 rFm)
 {
-	return float32_sub(rFm, rFn);
+	return float32_sub(roundData, rFm, rFn);
 }
 
-static float32 float32_rdv(float32 rFn, float32 rFm)
+static float32 float32_rdv(struct roundingData *roundData, float32 rFn, float32 rFm)
 {
-	return float32_div(rFm, rFn);
+	return float32_div(roundData, rFm, rFn);
 }
 
-static float32 (*const dyadic_single[16])(float32 rFn, float32 rFm) = {
+static float32 (*const dyadic_single[16])(struct roundingData *, float32 rFn, float32 rFm) = {
 	[ADF_CODE >> 20] = float32_add,
 	[MUF_CODE >> 20] = float32_mul,
 	[SUF_CODE >> 20] = float32_sub,
@@ -60,22 +60,22 @@ static float32 (*const dyadic_single[16])(float32 rFn, float32 rFm) = {
 	[FRD_CODE >> 20] = float32_rdv,
 };
 
-static float32 float32_mvf(float32 rFm)
+static float32 float32_mvf(struct roundingData *roundData, float32 rFm)
 {
 	return rFm;
 }
 
-static float32 float32_mnf(float32 rFm)
+static float32 float32_mnf(struct roundingData *roundData, float32 rFm)
 {
 	return rFm ^ 0x80000000;
 }
 
-static float32 float32_abs(float32 rFm)
+static float32 float32_abs(struct roundingData *roundData, float32 rFm)
 {
 	return rFm & 0x7fffffff;
 }
 
-static float32 (*const monadic_single[16])(float32 rFm) = {
+static float32 (*const monadic_single[16])(struct roundingData*, float32 rFm) = {
 	[MVF_CODE >> 20] = float32_mvf,
 	[MNF_CODE >> 20] = float32_mnf,
 	[ABS_CODE >> 20] = float32_abs,
@@ -85,7 +85,7 @@ static float32 (*const monadic_single[16])(float32 rFm) = {
 	[NRM_CODE >> 20] = float32_mvf,
 };
 
-unsigned int SingleCPDO(const unsigned int opcode, FPREG * rFd)
+unsigned int SingleCPDO(struct roundingData *roundData, const unsigned int opcode, FPREG * rFd)
 {
 	FPA11 *fpa11 = GET_FPA11();
 	float32 rFm;
@@ -108,13 +108,13 @@ unsigned int SingleCPDO(const unsigned int opcode, FPREG * rFd)
 		if (fpa11->fType[Fn] == typeSingle &&
 		    dyadic_single[opc_mask_shift]) {
 			rFn = fpa11->fpreg[Fn].fSingle;
-			rFd->fSingle = dyadic_single[opc_mask_shift](rFn, rFm);
+			rFd->fSingle = dyadic_single[opc_mask_shift](roundData, rFn, rFm);
 		} else {
 			return 0;
 		}
 	} else {
 		if (monadic_single[opc_mask_shift]) {
-			rFd->fSingle = monadic_single[opc_mask_shift](rFm);
+			rFd->fSingle = monadic_single[opc_mask_shift](roundData, rFm);
 		} else {
 			return 0;
 		}
diff --git a/arch/arm/nwfpe/softfloat.c b/arch/arm/nwfpe/softfloat.c
index e038dd3be9b..8b75a6e7cb3 100644
--- a/arch/arm/nwfpe/softfloat.c
+++ b/arch/arm/nwfpe/softfloat.c
@@ -36,16 +36,6 @@ this code that are retained.
 
 /*
 -------------------------------------------------------------------------------
-Floating-point rounding mode, extended double-precision rounding precision,
-and exception flags.
--------------------------------------------------------------------------------
-*/
-int8 float_rounding_mode = float_round_nearest_even;
-int8 floatx80_rounding_precision = 80;
-int8 float_exception_flags;
-
-/*
--------------------------------------------------------------------------------
 Primitive arithmetic functions, including multi-word arithmetic, and
 division and square root approximations.  (Can be specialized to target if
 desired.)
@@ -77,14 +67,14 @@ input is too large, however, the invalid exception is raised and the largest
 positive or negative integer is returned.
 -------------------------------------------------------------------------------
 */
-static int32 roundAndPackInt32( flag zSign, bits64 absZ )
+static int32 roundAndPackInt32( struct roundingData *roundData, flag zSign, bits64 absZ )
 {
     int8 roundingMode;
     flag roundNearestEven;
     int8 roundIncrement, roundBits;
     int32 z;
 
-    roundingMode = float_rounding_mode;
+    roundingMode = roundData->mode;
     roundNearestEven = ( roundingMode == float_round_nearest_even );
     roundIncrement = 0x40;
     if ( ! roundNearestEven ) {
@@ -107,10 +97,10 @@ static int32 roundAndPackInt32( flag zSign, bits64 absZ )
     z = absZ;
     if ( zSign ) z = - z;
     if ( ( absZ>>32 ) || ( z && ( ( z < 0 ) ^ zSign ) ) ) {
-        float_exception_flags |= float_flag_invalid;
+        roundData->exception |= float_flag_invalid;
         return zSign ? 0x80000000 : 0x7FFFFFFF;
     }
-    if ( roundBits ) float_exception_flags |= float_flag_inexact;
+    if ( roundBits ) roundData->exception |= float_flag_inexact;
     return z;
 
 }
@@ -224,14 +214,14 @@ The handling of underflow and overflow follows the IEC/IEEE Standard for
 Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-static float32 roundAndPackFloat32( flag zSign, int16 zExp, bits32 zSig )
+static float32 roundAndPackFloat32( struct roundingData *roundData, flag zSign, int16 zExp, bits32 zSig )
 {
     int8 roundingMode;
     flag roundNearestEven;
     int8 roundIncrement, roundBits;
     flag isTiny;
 
-    roundingMode = float_rounding_mode;
+    roundingMode = roundData->mode;
     roundNearestEven = ( roundingMode == float_round_nearest_even );
     roundIncrement = 0x40;
     if ( ! roundNearestEven ) {
@@ -254,7 +244,7 @@ static float32 roundAndPackFloat32( flag zSign, int16 zExp, bits32 zSig )
              || (    ( zExp == 0xFD )
                   && ( (sbits32) ( zSig + roundIncrement ) < 0 ) )
            ) {
-            float_raise( float_flag_overflow | float_flag_inexact );
+            roundData->exception |= float_flag_overflow | float_flag_inexact;
             return packFloat32( zSign, 0xFF, 0 ) - ( roundIncrement == 0 );
         }
         if ( zExp < 0 ) {
@@ -265,10 +255,10 @@ static float32 roundAndPackFloat32( flag zSign, int16 zExp, bits32 zSig )
             shift32RightJamming( zSig, - zExp, &zSig );
             zExp = 0;
             roundBits = zSig & 0x7F;
-            if ( isTiny && roundBits ) float_raise( float_flag_underflow );
+            if ( isTiny && roundBits ) roundData->exception |= float_flag_underflow;
         }
     }
-    if ( roundBits ) float_exception_flags |= float_flag_inexact;
+    if ( roundBits ) roundData->exception |= float_flag_inexact;
     zSig = ( zSig + roundIncrement )>>7;
     zSig &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven );
     if ( zSig == 0 ) zExp = 0;
@@ -287,12 +277,12 @@ point exponent.
 -------------------------------------------------------------------------------
 */
 static float32
- normalizeRoundAndPackFloat32( flag zSign, int16 zExp, bits32 zSig )
+ normalizeRoundAndPackFloat32( struct roundingData *roundData, flag zSign, int16 zExp, bits32 zSig )
 {
     int8 shiftCount;
 
     shiftCount = countLeadingZeros32( zSig ) - 1;
-    return roundAndPackFloat32( zSign, zExp - shiftCount, zSig<<shiftCount );
+    return roundAndPackFloat32( roundData, zSign, zExp - shiftCount, zSig<<shiftCount );
 
 }
 
@@ -395,14 +385,14 @@ The handling of underflow and overflow follows the IEC/IEEE Standard for
 Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-static float64 roundAndPackFloat64( flag zSign, int16 zExp, bits64 zSig )
+static float64 roundAndPackFloat64( struct roundingData *roundData, flag zSign, int16 zExp, bits64 zSig )
 {
     int8 roundingMode;
     flag roundNearestEven;
     int16 roundIncrement, roundBits;
     flag isTiny;
 
-    roundingMode = float_rounding_mode;
+    roundingMode = roundData->mode;
     roundNearestEven = ( roundingMode == float_round_nearest_even );
     roundIncrement = 0x200;
     if ( ! roundNearestEven ) {
@@ -427,7 +417,7 @@ static float64 roundAndPackFloat64( flag zSign, int16 zExp, bits64 zSig )
            ) {
             //register int lr = __builtin_return_address(0);
             //printk("roundAndPackFloat64 called from 0x%08x\n",lr);
-            float_raise( float_flag_overflow | float_flag_inexact );
+            roundData->exception |= float_flag_overflow | float_flag_inexact;
             return packFloat64( zSign, 0x7FF, 0 ) - ( roundIncrement == 0 );
         }
         if ( zExp < 0 ) {
@@ -438,10 +428,10 @@ static float64 roundAndPackFloat64( flag zSign, int16 zExp, bits64 zSig )
             shift64RightJamming( zSig, - zExp, &zSig );
             zExp = 0;
             roundBits = zSig & 0x3FF;
-            if ( isTiny && roundBits ) float_raise( float_flag_underflow );
+            if ( isTiny && roundBits ) roundData->exception |= float_flag_underflow;
         }
     }
-    if ( roundBits ) float_exception_flags |= float_flag_inexact;
+    if ( roundBits ) roundData->exception |= float_flag_inexact;
     zSig = ( zSig + roundIncrement )>>10;
     zSig &= ~ ( ( ( roundBits ^ 0x200 ) == 0 ) & roundNearestEven );
     if ( zSig == 0 ) zExp = 0;
@@ -460,12 +450,12 @@ point exponent.
 -------------------------------------------------------------------------------
 */
 static float64
- normalizeRoundAndPackFloat64( flag zSign, int16 zExp, bits64 zSig )
+ normalizeRoundAndPackFloat64( struct roundingData *roundData, flag zSign, int16 zExp, bits64 zSig )
 {
     int8 shiftCount;
 
     shiftCount = countLeadingZeros64( zSig ) - 1;
-    return roundAndPackFloat64( zSign, zExp - shiftCount, zSig<<shiftCount );
+    return roundAndPackFloat64( roundData, zSign, zExp - shiftCount, zSig<<shiftCount );
 
 }
 
@@ -572,14 +562,15 @@ Floating-point Arithmetic.
 */
 static floatx80
  roundAndPackFloatx80(
-     int8 roundingPrecision, flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1
+     struct roundingData *roundData, flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1
  )
 {
-    int8 roundingMode;
+    int8 roundingMode, roundingPrecision;
     flag roundNearestEven, increment, isTiny;
     int64 roundIncrement, roundMask, roundBits;
 
-    roundingMode = float_rounding_mode;
+    roundingMode = roundData->mode;
+    roundingPrecision = roundData->precision;
     roundNearestEven = ( roundingMode == float_round_nearest_even );
     if ( roundingPrecision == 80 ) goto precision80;
     if ( roundingPrecision == 64 ) {
@@ -623,8 +614,8 @@ static floatx80
             shift64RightJamming( zSig0, 1 - zExp, &zSig0 );
             zExp = 0;
             roundBits = zSig0 & roundMask;
-            if ( isTiny && roundBits ) float_raise( float_flag_underflow );
-            if ( roundBits ) float_exception_flags |= float_flag_inexact;
+            if ( isTiny && roundBits ) roundData->exception |= float_flag_underflow;
+            if ( roundBits ) roundData->exception |= float_flag_inexact;
             zSig0 += roundIncrement;
             if ( (sbits64) zSig0 < 0 ) zExp = 1;
             roundIncrement = roundMask + 1;
@@ -635,7 +626,7 @@ static floatx80
             return packFloatx80( zSign, zExp, zSig0 );
         }
     }
-    if ( roundBits ) float_exception_flags |= float_flag_inexact;
+    if ( roundBits ) roundData->exception |= float_flag_inexact;
     zSig0 += roundIncrement;
     if ( zSig0 < roundIncrement ) {
         ++zExp;
@@ -672,7 +663,7 @@ static floatx80
            ) {
             roundMask = 0;
  overflow:
-            float_raise( float_flag_overflow | float_flag_inexact );
+            roundData->exception |= float_flag_overflow | float_flag_inexact;
             if (    ( roundingMode == float_round_to_zero )
                  || ( zSign && ( roundingMode == float_round_up ) )
                  || ( ! zSign && ( roundingMode == float_round_down ) )
@@ -689,8 +680,8 @@ static floatx80
                 || ( zSig0 < LIT64( 0xFFFFFFFFFFFFFFFF ) );
             shift64ExtraRightJamming( zSig0, zSig1, 1 - zExp, &zSig0, &zSig1 );
             zExp = 0;
-            if ( isTiny && zSig1 ) float_raise( float_flag_underflow );
-            if ( zSig1 ) float_exception_flags |= float_flag_inexact;
+            if ( isTiny && zSig1 ) roundData->exception |= float_flag_underflow;
+            if ( zSig1 ) roundData->exception |= float_flag_inexact;
             if ( roundNearestEven ) {
                 increment = ( (sbits64) zSig1 < 0 );
             }
@@ -710,7 +701,7 @@ static floatx80
             return packFloatx80( zSign, zExp, zSig0 );
         }
     }
-    if ( zSig1 ) float_exception_flags |= float_flag_inexact;
+    if ( zSig1 ) roundData->exception |= float_flag_inexact;
     if ( increment ) {
         ++zSig0;
         if ( zSig0 == 0 ) {
@@ -740,7 +731,7 @@ normalized.
 */
 static floatx80
  normalizeRoundAndPackFloatx80(
-     int8 roundingPrecision, flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1
+     struct roundingData *roundData, flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1
  )
 {
     int8 shiftCount;
@@ -754,7 +745,7 @@ static floatx80
     shortShift128Left( zSig0, zSig1, shiftCount, &zSig0, &zSig1 );
     zExp -= shiftCount;
     return
-        roundAndPackFloatx80( roundingPrecision, zSign, zExp, zSig0, zSig1 );
+        roundAndPackFloatx80( roundData, zSign, zExp, zSig0, zSig1 );
 
 }
 
@@ -767,14 +758,14 @@ the single-precision floating-point format.  The conversion is performed
 according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-float32 int32_to_float32( int32 a )
+float32 int32_to_float32(struct roundingData *roundData, int32 a)
 {
     flag zSign;
 
     if ( a == 0 ) return 0;
     if ( a == 0x80000000 ) return packFloat32( 1, 0x9E, 0 );
     zSign = ( a < 0 );
-    return normalizeRoundAndPackFloat32( zSign, 0x9C, zSign ? - a : a );
+    return normalizeRoundAndPackFloat32( roundData, zSign, 0x9C, zSign ? - a : a );
 
 }
 
@@ -840,7 +831,7 @@ positive integer is returned.  Otherwise, if the conversion overflows, the
 largest integer with the same sign as `a' is returned.
 -------------------------------------------------------------------------------
 */
-int32 float32_to_int32( float32 a )
+int32 float32_to_int32( struct roundingData *roundData, float32 a )
 {
     flag aSign;
     int16 aExp, shiftCount;
@@ -856,7 +847,7 @@ int32 float32_to_int32( float32 a )
     zSig = aSig;
     zSig <<= 32;
     if ( 0 < shiftCount ) shift64RightJamming( zSig, shiftCount, &zSig );
-    return roundAndPackInt32( aSign, zSig );
+    return roundAndPackInt32( roundData, aSign, zSig );
 
 }
 
@@ -889,13 +880,13 @@ int32 float32_to_int32_round_to_zero( float32 a )
         return 0x80000000;
     }
     else if ( aExp <= 0x7E ) {
-        if ( aExp | aSig ) float_exception_flags |= float_flag_inexact;
+        if ( aExp | aSig ) float_raise( float_flag_inexact );
         return 0;
     }
     aSig = ( aSig | 0x00800000 )<<8;
     z = aSig>>( - shiftCount );
     if ( (bits32) ( aSig<<( shiftCount & 31 ) ) ) {
-        float_exception_flags |= float_flag_inexact;
+        float_raise( float_flag_inexact );
     }
     return aSign ? - z : z;
 
@@ -973,7 +964,7 @@ operation is performed according to the IEC/IEEE Standard for Binary
 Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-float32 float32_round_to_int( float32 a )
+float32 float32_round_to_int( struct roundingData *roundData, float32 a )
 {
     flag aSign;
     int16 aExp;
@@ -988,11 +979,12 @@ float32 float32_round_to_int( float32 a )
         }
         return a;
     }
+    roundingMode = roundData->mode;
     if ( aExp <= 0x7E ) {
         if ( (bits32) ( a<<1 ) == 0 ) return a;
-        float_exception_flags |= float_flag_inexact;
+        roundData->exception |= float_flag_inexact;
         aSign = extractFloat32Sign( a );
-        switch ( float_rounding_mode ) {
+        switch ( roundingMode ) {
          case float_round_nearest_even:
             if ( ( aExp == 0x7E ) && extractFloat32Frac( a ) ) {
                 return packFloat32( aSign, 0x7F, 0 );
@@ -1009,7 +1001,6 @@ float32 float32_round_to_int( float32 a )
     lastBitMask <<= 0x96 - aExp;
     roundBitsMask = lastBitMask - 1;
     z = a;
-    roundingMode = float_rounding_mode;
     if ( roundingMode == float_round_nearest_even ) {
         z += lastBitMask>>1;
         if ( ( z & roundBitsMask ) == 0 ) z &= ~ lastBitMask;
@@ -1020,7 +1011,7 @@ float32 float32_round_to_int( float32 a )
         }
     }
     z &= ~ roundBitsMask;
-    if ( z != a ) float_exception_flags |= float_flag_inexact;
+    if ( z != a ) roundData->exception |= float_flag_inexact;
     return z;
 
 }
@@ -1034,7 +1025,7 @@ addition is performed according to the IEC/IEEE Standard for Binary
 Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-static float32 addFloat32Sigs( float32 a, float32 b, flag zSign )
+static float32 addFloat32Sigs( struct roundingData *roundData, float32 a, float32 b, flag zSign )
 {
     int16 aExp, bExp, zExp;
     bits32 aSig, bSig, zSig;
@@ -1093,7 +1084,7 @@ static float32 addFloat32Sigs( float32 a, float32 b, flag zSign )
         ++zExp;
     }
  roundAndPack:
-    return roundAndPackFloat32( zSign, zExp, zSig );
+    return roundAndPackFloat32( roundData, zSign, zExp, zSig );
 
 }
 
@@ -1106,7 +1097,7 @@ result is a NaN.  The subtraction is performed according to the IEC/IEEE
 Standard for Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-static float32 subFloat32Sigs( float32 a, float32 b, flag zSign )
+static float32 subFloat32Sigs( struct roundingData *roundData, float32 a, float32 b, flag zSign )
 {
     int16 aExp, bExp, zExp;
     bits32 aSig, bSig, zSig;
@@ -1123,7 +1114,7 @@ static float32 subFloat32Sigs( float32 a, float32 b, flag zSign )
     if ( expDiff < 0 ) goto bExpBigger;
     if ( aExp == 0xFF ) {
         if ( aSig | bSig ) return propagateFloat32NaN( a, b );
-        float_raise( float_flag_invalid );
+        roundData->exception |= float_flag_invalid;
         return float32_default_nan;
     }
     if ( aExp == 0 ) {
@@ -1132,7 +1123,7 @@ static float32 subFloat32Sigs( float32 a, float32 b, flag zSign )
     }
     if ( bSig < aSig ) goto aBigger;
     if ( aSig < bSig ) goto bBigger;
-    return packFloat32( float_rounding_mode == float_round_down, 0, 0 );
+    return packFloat32( roundData->mode == float_round_down, 0, 0 );
  bExpBigger:
     if ( bExp == 0xFF ) {
         if ( bSig ) return propagateFloat32NaN( a, b );
@@ -1169,7 +1160,7 @@ static float32 subFloat32Sigs( float32 a, float32 b, flag zSign )
     zExp = aExp;
  normalizeRoundAndPack:
     --zExp;
-    return normalizeRoundAndPackFloat32( zSign, zExp, zSig );
+    return normalizeRoundAndPackFloat32( roundData, zSign, zExp, zSig );
 
 }
 
@@ -1180,17 +1171,17 @@ and `b'.  The operation is performed according to the IEC/IEEE Standard for
 Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-float32 float32_add( float32 a, float32 b )
+float32 float32_add( struct roundingData *roundData, float32 a, float32 b )
 {
     flag aSign, bSign;
 
     aSign = extractFloat32Sign( a );
     bSign = extractFloat32Sign( b );
     if ( aSign == bSign ) {
-        return addFloat32Sigs( a, b, aSign );
+        return addFloat32Sigs( roundData, a, b, aSign );
     }
     else {
-        return subFloat32Sigs( a, b, aSign );
+        return subFloat32Sigs( roundData, a, b, aSign );
     }
 
 }
@@ -1202,17 +1193,17 @@ Returns the result of subtracting the single-precision floating-point values
 for Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-float32 float32_sub( float32 a, float32 b )
+float32 float32_sub( struct roundingData *roundData, float32 a, float32 b )
 {
     flag aSign, bSign;
 
     aSign = extractFloat32Sign( a );
     bSign = extractFloat32Sign( b );
     if ( aSign == bSign ) {
-        return subFloat32Sigs( a, b, aSign );
+        return subFloat32Sigs( roundData, a, b, aSign );
     }
     else {
-        return addFloat32Sigs( a, b, aSign );
+        return addFloat32Sigs( roundData, a, b, aSign );
     }
 
 }
@@ -1224,7 +1215,7 @@ Returns the result of multiplying the single-precision floating-point values
 for Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-float32 float32_mul( float32 a, float32 b )
+float32 float32_mul( struct roundingData *roundData, float32 a, float32 b )
 {
     flag aSign, bSign, zSign;
     int16 aExp, bExp, zExp;
@@ -1244,7 +1235,7 @@ float32 float32_mul( float32 a, float32 b )
             return propagateFloat32NaN( a, b );
         }
         if ( ( bExp | bSig ) == 0 ) {
-            float_raise( float_flag_invalid );
+            roundData->exception |= float_flag_invalid;
             return float32_default_nan;
         }
         return packFloat32( zSign, 0xFF, 0 );
@@ -1252,7 +1243,7 @@ float32 float32_mul( float32 a, float32 b )
     if ( bExp == 0xFF ) {
         if ( bSig ) return propagateFloat32NaN( a, b );
         if ( ( aExp | aSig ) == 0 ) {
-            float_raise( float_flag_invalid );
+            roundData->exception |= float_flag_invalid;
             return float32_default_nan;
         }
         return packFloat32( zSign, 0xFF, 0 );
@@ -1274,7 +1265,7 @@ float32 float32_mul( float32 a, float32 b )
         zSig <<= 1;
         --zExp;
     }
-    return roundAndPackFloat32( zSign, zExp, zSig );
+    return roundAndPackFloat32( roundData, zSign, zExp, zSig );
 
 }
 
@@ -1285,7 +1276,7 @@ by the corresponding value `b'.  The operation is performed according to the
 IEC/IEEE Standard for Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-float32 float32_div( float32 a, float32 b )
+float32 float32_div( struct roundingData *roundData, float32 a, float32 b )
 {
     flag aSign, bSign, zSign;
     int16 aExp, bExp, zExp;
@@ -1302,7 +1293,7 @@ float32 float32_div( float32 a, float32 b )
         if ( aSig ) return propagateFloat32NaN( a, b );
         if ( bExp == 0xFF ) {
             if ( bSig ) return propagateFloat32NaN( a, b );
-            float_raise( float_flag_invalid );
+            roundData->exception |= float_flag_invalid;
             return float32_default_nan;
         }
         return packFloat32( zSign, 0xFF, 0 );
@@ -1314,10 +1305,10 @@ float32 float32_div( float32 a, float32 b )
     if ( bExp == 0 ) {
         if ( bSig == 0 ) {
             if ( ( aExp | aSig ) == 0 ) {
-                float_raise( float_flag_invalid );
+                roundData->exception |= float_flag_invalid;
                 return float32_default_nan;
             }
-            float_raise( float_flag_divbyzero );
+            roundData->exception |= float_flag_divbyzero;
             return packFloat32( zSign, 0xFF, 0 );
         }
         normalizeFloat32Subnormal( bSig, &bExp, &bSig );
@@ -1341,7 +1332,7 @@ float32 float32_div( float32 a, float32 b )
     if ( ( zSig & 0x3F ) == 0 ) {
         zSig |= ( ( (bits64) bSig ) * zSig != ( (bits64) aSig )<<32 );
     }
-    return roundAndPackFloat32( zSign, zExp, zSig );
+    return roundAndPackFloat32( roundData, zSign, zExp, zSig );
 
 }
 
@@ -1352,7 +1343,7 @@ with respect to the corresponding value `b'.  The operation is performed
 according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-float32 float32_rem( float32 a, float32 b )
+float32 float32_rem( struct roundingData *roundData, float32 a, float32 b )
 {
     flag aSign, bSign, zSign;
     int16 aExp, bExp, expDiff;
@@ -1372,7 +1363,7 @@ float32 float32_rem( float32 a, float32 b )
         if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) {
             return propagateFloat32NaN( a, b );
         }
-        float_raise( float_flag_invalid );
+        roundData->exception |= float_flag_invalid;
         return float32_default_nan;
     }
     if ( bExp == 0xFF ) {
@@ -1381,7 +1372,7 @@ float32 float32_rem( float32 a, float32 b )
     }
     if ( bExp == 0 ) {
         if ( bSig == 0 ) {
-            float_raise( float_flag_invalid );
+            roundData->exception |= float_flag_invalid;
             return float32_default_nan;
         }
         normalizeFloat32Subnormal( bSig, &bExp, &bSig );
@@ -1444,7 +1435,7 @@ float32 float32_rem( float32 a, float32 b )
     }
     zSign = ( (sbits32) aSig < 0 );
     if ( zSign ) aSig = - aSig;
-    return normalizeRoundAndPackFloat32( aSign ^ zSign, bExp, aSig );
+    return normalizeRoundAndPackFloat32( roundData, aSign ^ zSign, bExp, aSig );
 
 }
 
@@ -1455,7 +1446,7 @@ The operation is performed according to the IEC/IEEE Standard for Binary
 Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-float32 float32_sqrt( float32 a )
+float32 float32_sqrt( struct roundingData *roundData, float32 a )
 {
     flag aSign;
     int16 aExp, zExp;
@@ -1468,12 +1459,12 @@ float32 float32_sqrt( float32 a )
     if ( aExp == 0xFF ) {
         if ( aSig ) return propagateFloat32NaN( a, 0 );
         if ( ! aSign ) return a;
-        float_raise( float_flag_invalid );
+        roundData->exception |= float_flag_invalid;
         return float32_default_nan;
     }
     if ( aSign ) {
         if ( ( aExp | aSig ) == 0 ) return a;
-        float_raise( float_flag_invalid );
+        roundData->exception |= float_flag_invalid;
         return float32_default_nan;
     }
     if ( aExp == 0 ) {
@@ -1499,7 +1490,7 @@ float32 float32_sqrt( float32 a )
         }
     }
     shift32RightJamming( zSig, 1, &zSig );
-    return roundAndPackFloat32( 0, zExp, zSig );
+    return roundAndPackFloat32( roundData, 0, zExp, zSig );
 
 }
 
@@ -1661,7 +1652,7 @@ positive integer is returned.  Otherwise, if the conversion overflows, the
 largest integer with the same sign as `a' is returned.
 -------------------------------------------------------------------------------
 */
-int32 float64_to_int32( float64 a )
+int32 float64_to_int32( struct roundingData *roundData, float64 a )
 {
     flag aSign;
     int16 aExp, shiftCount;
@@ -1674,7 +1665,7 @@ int32 float64_to_int32( float64 a )
     if ( aExp ) aSig |= LIT64( 0x0010000000000000 );
     shiftCount = 0x42C - aExp;
     if ( 0 < shiftCount ) shift64RightJamming( aSig, shiftCount, &aSig );
-    return roundAndPackInt32( aSign, aSig );
+    return roundAndPackInt32( roundData, aSign, aSig );
 
 }
 
@@ -1705,7 +1696,7 @@ int32 float64_to_int32_round_to_zero( float64 a )
         goto invalid;
     }
     else if ( 52 < shiftCount ) {
-        if ( aExp || aSig ) float_exception_flags |= float_flag_inexact;
+        if ( aExp || aSig ) float_raise( float_flag_inexact );
         return 0;
     }
     aSig |= LIT64( 0x0010000000000000 );
@@ -1715,11 +1706,11 @@ int32 float64_to_int32_round_to_zero( float64 a )
     if ( aSign ) z = - z;
     if ( ( z < 0 ) ^ aSign ) {
  invalid:
-        float_exception_flags |= float_flag_invalid;
+        float_raise( float_flag_invalid );
         return aSign ? 0x80000000 : 0x7FFFFFFF;
     }
     if ( ( aSig<<shiftCount ) != savedASig ) {
-        float_exception_flags |= float_flag_inexact;
+        float_raise( float_flag_inexact );
     }
     return z;
 
@@ -1736,7 +1727,7 @@ positive integer is returned.  Otherwise, if the conversion overflows, the
 largest positive integer is returned.
 -------------------------------------------------------------------------------
 */
-int32 float64_to_uint32( float64 a )
+int32 float64_to_uint32( struct roundingData *roundData, float64 a )
 {
     flag aSign;
     int16 aExp, shiftCount;
@@ -1749,7 +1740,7 @@ int32 float64_to_uint32( float64 a )
     if ( aExp ) aSig |= LIT64( 0x0010000000000000 );
     shiftCount = 0x42C - aExp;
     if ( 0 < shiftCount ) shift64RightJamming( aSig, shiftCount, &aSig );
-    return roundAndPackInt32( aSign, aSig );
+    return roundAndPackInt32( roundData, aSign, aSig );
 }
 
 /*
@@ -1778,7 +1769,7 @@ int32 float64_to_uint32_round_to_zero( float64 a )
         goto invalid;
     }
     else if ( 52 < shiftCount ) {
-        if ( aExp || aSig ) float_exception_flags |= float_flag_inexact;
+        if ( aExp || aSig ) float_raise( float_flag_inexact );
         return 0;
     }
     aSig |= LIT64( 0x0010000000000000 );
@@ -1788,11 +1779,11 @@ int32 float64_to_uint32_round_to_zero( float64 a )
     if ( aSign ) z = - z;
     if ( ( z < 0 ) ^ aSign ) {
  invalid:
-        float_exception_flags |= float_flag_invalid;
+        float_raise( float_flag_invalid );
         return aSign ? 0x80000000 : 0x7FFFFFFF;
     }
     if ( ( aSig<<shiftCount ) != savedASig ) {
-        float_exception_flags |= float_flag_inexact;
+        float_raise( float_flag_inexact );
     }
     return z;
 }
@@ -1805,7 +1796,7 @@ performed according to the IEC/IEEE Standard for Binary Floating-point
 Arithmetic.
 -------------------------------------------------------------------------------
 */
-float32 float64_to_float32( float64 a )
+float32 float64_to_float32( struct roundingData *roundData, float64 a )
 {
     flag aSign;
     int16 aExp;
@@ -1825,7 +1816,7 @@ float32 float64_to_float32( float64 a )
         zSig |= 0x40000000;
         aExp -= 0x381;
     }
-    return roundAndPackFloat32( aSign, aExp, zSig );
+    return roundAndPackFloat32( roundData, aSign, aExp, zSig );
 
 }
 
@@ -1872,7 +1863,7 @@ operation is performed according to the IEC/IEEE Standard for Binary
 Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-float64 float64_round_to_int( float64 a )
+float64 float64_round_to_int( struct roundingData *roundData, float64 a )
 {
     flag aSign;
     int16 aExp;
@@ -1889,9 +1880,9 @@ float64 float64_round_to_int( float64 a )
     }
     if ( aExp <= 0x3FE ) {
         if ( (bits64) ( a<<1 ) == 0 ) return a;
-        float_exception_flags |= float_flag_inexact;
+        roundData->exception |= float_flag_inexact;
         aSign = extractFloat64Sign( a );
-        switch ( float_rounding_mode ) {
+        switch ( roundData->mode ) {
          case float_round_nearest_even:
             if ( ( aExp == 0x3FE ) && extractFloat64Frac( a ) ) {
                 return packFloat64( aSign, 0x3FF, 0 );
@@ -1909,7 +1900,7 @@ float64 float64_round_to_int( float64 a )
     lastBitMask <<= 0x433 - aExp;
     roundBitsMask = lastBitMask - 1;
     z = a;
-    roundingMode = float_rounding_mode;
+    roundingMode = roundData->mode;
     if ( roundingMode == float_round_nearest_even ) {
         z += lastBitMask>>1;
         if ( ( z & roundBitsMask ) == 0 ) z &= ~ lastBitMask;
@@ -1920,7 +1911,7 @@ float64 float64_round_to_int( float64 a )
         }
     }
     z &= ~ roundBitsMask;
-    if ( z != a ) float_exception_flags |= float_flag_inexact;
+    if ( z != a ) roundData->exception |= float_flag_inexact;
     return z;
 
 }
@@ -1934,7 +1925,7 @@ addition is performed according to the IEC/IEEE Standard for Binary
 Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-static float64 addFloat64Sigs( float64 a, float64 b, flag zSign )
+static float64 addFloat64Sigs( struct roundingData *roundData, float64 a, float64 b, flag zSign )
 {
     int16 aExp, bExp, zExp;
     bits64 aSig, bSig, zSig;
@@ -1993,7 +1984,7 @@ static float64 addFloat64Sigs( float64 a, float64 b, flag zSign )
         ++zExp;
     }
  roundAndPack:
-    return roundAndPackFloat64( zSign, zExp, zSig );
+    return roundAndPackFloat64( roundData, zSign, zExp, zSig );
 
 }
 
@@ -2006,7 +1997,7 @@ result is a NaN.  The subtraction is performed according to the IEC/IEEE
 Standard for Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-static float64 subFloat64Sigs( float64 a, float64 b, flag zSign )
+static float64 subFloat64Sigs( struct roundingData *roundData, float64 a, float64 b, flag zSign )
 {
     int16 aExp, bExp, zExp;
     bits64 aSig, bSig, zSig;
@@ -2023,7 +2014,7 @@ static float64 subFloat64Sigs( float64 a, float64 b, flag zSign )
     if ( expDiff < 0 ) goto bExpBigger;
     if ( aExp == 0x7FF ) {
         if ( aSig | bSig ) return propagateFloat64NaN( a, b );
-        float_raise( float_flag_invalid );
+        roundData->exception |= float_flag_invalid;
         return float64_default_nan;
     }
     if ( aExp == 0 ) {
@@ -2032,7 +2023,7 @@ static float64 subFloat64Sigs( float64 a, float64 b, flag zSign )
     }
     if ( bSig < aSig ) goto aBigger;
     if ( aSig < bSig ) goto bBigger;
-    return packFloat64( float_rounding_mode == float_round_down, 0, 0 );
+    return packFloat64( roundData->mode == float_round_down, 0, 0 );
  bExpBigger:
     if ( bExp == 0x7FF ) {
         if ( bSig ) return propagateFloat64NaN( a, b );
@@ -2069,7 +2060,7 @@ static float64 subFloat64Sigs( float64 a, float64 b, flag zSign )
     zExp = aExp;
  normalizeRoundAndPack:
     --zExp;
-    return normalizeRoundAndPackFloat64( zSign, zExp, zSig );
+    return normalizeRoundAndPackFloat64( roundData, zSign, zExp, zSig );
 
 }
 
@@ -2080,17 +2071,17 @@ and `b'.  The operation is performed according to the IEC/IEEE Standard for
 Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-float64 float64_add( float64 a, float64 b )
+float64 float64_add( struct roundingData *roundData, float64 a, float64 b )
 {
     flag aSign, bSign;
 
     aSign = extractFloat64Sign( a );
     bSign = extractFloat64Sign( b );
     if ( aSign == bSign ) {
-        return addFloat64Sigs( a, b, aSign );
+        return addFloat64Sigs( roundData, a, b, aSign );
     }
     else {
-        return subFloat64Sigs( a, b, aSign );
+        return subFloat64Sigs( roundData, a, b, aSign );
     }
 
 }
@@ -2102,17 +2093,17 @@ Returns the result of subtracting the double-precision floating-point values
 for Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-float64 float64_sub( float64 a, float64 b )
+float64 float64_sub( struct roundingData *roundData, float64 a, float64 b )
 {
     flag aSign, bSign;
 
     aSign = extractFloat64Sign( a );
     bSign = extractFloat64Sign( b );
     if ( aSign == bSign ) {
-        return subFloat64Sigs( a, b, aSign );
+        return subFloat64Sigs( roundData, a, b, aSign );
     }
     else {
-        return addFloat64Sigs( a, b, aSign );
+        return addFloat64Sigs( roundData, a, b, aSign );
     }
 
 }
@@ -2124,7 +2115,7 @@ Returns the result of multiplying the double-precision floating-point values
 for Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-float64 float64_mul( float64 a, float64 b )
+float64 float64_mul( struct roundingData *roundData, float64 a, float64 b )
 {
     flag aSign, bSign, zSign;
     int16 aExp, bExp, zExp;
@@ -2142,7 +2133,7 @@ float64 float64_mul( float64 a, float64 b )
             return propagateFloat64NaN( a, b );
         }
         if ( ( bExp | bSig ) == 0 ) {
-            float_raise( float_flag_invalid );
+            roundData->exception |= float_flag_invalid;
             return float64_default_nan;
         }
         return packFloat64( zSign, 0x7FF, 0 );
@@ -2150,7 +2141,7 @@ float64 float64_mul( float64 a, float64 b )
     if ( bExp == 0x7FF ) {
         if ( bSig ) return propagateFloat64NaN( a, b );
         if ( ( aExp | aSig ) == 0 ) {
-            float_raise( float_flag_invalid );
+            roundData->exception |= float_flag_invalid;
             return float64_default_nan;
         }
         return packFloat64( zSign, 0x7FF, 0 );
@@ -2172,7 +2163,7 @@ float64 float64_mul( float64 a, float64 b )
         zSig0 <<= 1;
         --zExp;
     }
-    return roundAndPackFloat64( zSign, zExp, zSig0 );
+    return roundAndPackFloat64( roundData, zSign, zExp, zSig0 );
 
 }
 
@@ -2183,7 +2174,7 @@ by the corresponding value `b'.  The operation is performed according to
 the IEC/IEEE Standard for Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-float64 float64_div( float64 a, float64 b )
+float64 float64_div( struct roundingData *roundData, float64 a, float64 b )
 {
     flag aSign, bSign, zSign;
     int16 aExp, bExp, zExp;
@@ -2202,7 +2193,7 @@ float64 float64_div( float64 a, float64 b )
         if ( aSig ) return propagateFloat64NaN( a, b );
         if ( bExp == 0x7FF ) {
             if ( bSig ) return propagateFloat64NaN( a, b );
-            float_raise( float_flag_invalid );
+            roundData->exception |= float_flag_invalid;
             return float64_default_nan;
         }
         return packFloat64( zSign, 0x7FF, 0 );
@@ -2214,10 +2205,10 @@ float64 float64_div( float64 a, float64 b )
     if ( bExp == 0 ) {
         if ( bSig == 0 ) {
             if ( ( aExp | aSig ) == 0 ) {
-                float_raise( float_flag_invalid );
+                roundData->exception |= float_flag_invalid;
                 return float64_default_nan;
             }
-            float_raise( float_flag_divbyzero );
+            roundData->exception |= float_flag_divbyzero;
             return packFloat64( zSign, 0x7FF, 0 );
         }
         normalizeFloat64Subnormal( bSig, &bExp, &bSig );
@@ -2243,7 +2234,7 @@ float64 float64_div( float64 a, float64 b )
         }
         zSig |= ( rem1 != 0 );
     }
-    return roundAndPackFloat64( zSign, zExp, zSig );
+    return roundAndPackFloat64( roundData, zSign, zExp, zSig );
 
 }
 
@@ -2254,7 +2245,7 @@ with respect to the corresponding value `b'.  The operation is performed
 according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-float64 float64_rem( float64 a, float64 b )
+float64 float64_rem( struct roundingData *roundData, float64 a, float64 b )
 {
     flag aSign, bSign, zSign;
     int16 aExp, bExp, expDiff;
@@ -2272,7 +2263,7 @@ float64 float64_rem( float64 a, float64 b )
         if ( aSig || ( ( bExp == 0x7FF ) && bSig ) ) {
             return propagateFloat64NaN( a, b );
         }
-        float_raise( float_flag_invalid );
+        roundData->exception |= float_flag_invalid;
         return float64_default_nan;
     }
     if ( bExp == 0x7FF ) {
@@ -2281,7 +2272,7 @@ float64 float64_rem( float64 a, float64 b )
     }
     if ( bExp == 0 ) {
         if ( bSig == 0 ) {
-            float_raise( float_flag_invalid );
+            roundData->exception |= float_flag_invalid;
             return float64_default_nan;
         }
         normalizeFloat64Subnormal( bSig, &bExp, &bSig );
@@ -2329,7 +2320,7 @@ float64 float64_rem( float64 a, float64 b )
     }
     zSign = ( (sbits64) aSig < 0 );
     if ( zSign ) aSig = - aSig;
-    return normalizeRoundAndPackFloat64( aSign ^ zSign, bExp, aSig );
+    return normalizeRoundAndPackFloat64( roundData, aSign ^ zSign, bExp, aSig );
 
 }
 
@@ -2340,7 +2331,7 @@ The operation is performed according to the IEC/IEEE Standard for Binary
 Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-float64 float64_sqrt( float64 a )
+float64 float64_sqrt( struct roundingData *roundData, float64 a )
 {
     flag aSign;
     int16 aExp, zExp;
@@ -2354,12 +2345,12 @@ float64 float64_sqrt( float64 a )
     if ( aExp == 0x7FF ) {
         if ( aSig ) return propagateFloat64NaN( a, a );
         if ( ! aSign ) return a;
-        float_raise( float_flag_invalid );
+        roundData->exception |= float_flag_invalid;
         return float64_default_nan;
     }
     if ( aSign ) {
         if ( ( aExp | aSig ) == 0 ) return a;
-        float_raise( float_flag_invalid );
+        roundData->exception |= float_flag_invalid;
         return float64_default_nan;
     }
     if ( aExp == 0 ) {
@@ -2390,7 +2381,7 @@ float64 float64_sqrt( float64 a )
         }
     }
     shift64RightJamming( zSig, 1, &zSig );
-    return roundAndPackFloat64( 0, zExp, zSig );
+    return roundAndPackFloat64( roundData, 0, zExp, zSig );
 
 }
 
@@ -2554,7 +2545,7 @@ largest positive integer is returned.  Otherwise, if the conversion
 overflows, the largest integer with the same sign as `a' is returned.
 -------------------------------------------------------------------------------
 */
-int32 floatx80_to_int32( floatx80 a )
+int32 floatx80_to_int32( struct roundingData *roundData, floatx80 a )
 {
     flag aSign;
     int32 aExp, shiftCount;
@@ -2567,7 +2558,7 @@ int32 floatx80_to_int32( floatx80 a )
     shiftCount = 0x4037 - aExp;
     if ( shiftCount <= 0 ) shiftCount = 1;
     shift64RightJamming( aSig, shiftCount, &aSig );
-    return roundAndPackInt32( aSign, aSig );
+    return roundAndPackInt32( roundData, aSign, aSig );
 
 }
 
@@ -2598,7 +2589,7 @@ int32 floatx80_to_int32_round_to_zero( floatx80 a )
         goto invalid;
     }
     else if ( 63 < shiftCount ) {
-        if ( aExp || aSig ) float_exception_flags |= float_flag_inexact;
+        if ( aExp || aSig ) float_raise( float_flag_inexact );
         return 0;
     }
     savedASig = aSig;
@@ -2607,11 +2598,11 @@ int32 floatx80_to_int32_round_to_zero( floatx80 a )
     if ( aSign ) z = - z;
     if ( ( z < 0 ) ^ aSign ) {
  invalid:
-        float_exception_flags |= float_flag_invalid;
+        float_raise( float_flag_invalid );
         return aSign ? 0x80000000 : 0x7FFFFFFF;
     }
     if ( ( aSig<<shiftCount ) != savedASig ) {
-        float_exception_flags |= float_flag_inexact;
+        float_raise( float_flag_inexact );
     }
     return z;
 
@@ -2625,7 +2616,7 @@ conversion is performed according to the IEC/IEEE Standard for Binary
 Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-float32 floatx80_to_float32( floatx80 a )
+float32 floatx80_to_float32( struct roundingData *roundData, floatx80 a )
 {
     flag aSign;
     int32 aExp;
@@ -2642,7 +2633,7 @@ float32 floatx80_to_float32( floatx80 a )
     }
     shift64RightJamming( aSig, 33, &aSig );
     if ( aExp || aSig ) aExp -= 0x3F81;
-    return roundAndPackFloat32( aSign, aExp, aSig );
+    return roundAndPackFloat32( roundData, aSign, aExp, aSig );
 
 }
 
@@ -2654,7 +2645,7 @@ conversion is performed according to the IEC/IEEE Standard for Binary
 Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-float64 floatx80_to_float64( floatx80 a )
+float64 floatx80_to_float64( struct roundingData *roundData, floatx80 a )
 {
     flag aSign;
     int32 aExp;
@@ -2671,7 +2662,7 @@ float64 floatx80_to_float64( floatx80 a )
     }
     shift64RightJamming( aSig, 1, &zSig );
     if ( aExp || aSig ) aExp -= 0x3C01;
-    return roundAndPackFloat64( aSign, aExp, zSig );
+    return roundAndPackFloat64( roundData, aSign, aExp, zSig );
 
 }
 
@@ -2683,7 +2674,7 @@ value.  The operation is performed according to the IEC/IEEE Standard for
 Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-floatx80 floatx80_round_to_int( floatx80 a )
+floatx80 floatx80_round_to_int( struct roundingData *roundData, floatx80 a )
 {
     flag aSign;
     int32 aExp;
@@ -2703,9 +2694,9 @@ floatx80 floatx80_round_to_int( floatx80 a )
              && ( (bits64) ( extractFloatx80Frac( a )<<1 ) == 0 ) ) {
             return a;
         }
-        float_exception_flags |= float_flag_inexact;
+        roundData->exception |= float_flag_inexact;
         aSign = extractFloatx80Sign( a );
-        switch ( float_rounding_mode ) {
+        switch ( roundData->mode ) {
          case float_round_nearest_even:
             if ( ( aExp == 0x3FFE ) && (bits64) ( extractFloatx80Frac( a )<<1 )
                ) {
@@ -2729,7 +2720,7 @@ floatx80 floatx80_round_to_int( floatx80 a )
     lastBitMask <<= 0x403E - aExp;
     roundBitsMask = lastBitMask - 1;
     z = a;
-    roundingMode = float_rounding_mode;
+    roundingMode = roundData->mode;
     if ( roundingMode == float_round_nearest_even ) {
         z.low += lastBitMask>>1;
         if ( ( z.low & roundBitsMask ) == 0 ) z.low &= ~ lastBitMask;
@@ -2744,7 +2735,7 @@ floatx80 floatx80_round_to_int( floatx80 a )
         ++z.high;
         z.low = LIT64( 0x8000000000000000 );
     }
-    if ( z.low != a.low ) float_exception_flags |= float_flag_inexact;
+    if ( z.low != a.low ) roundData->exception |= float_flag_inexact;
     return z;
 
 }
@@ -2758,7 +2749,7 @@ The addition is performed according to the IEC/IEEE Standard for Binary
 Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-static floatx80 addFloatx80Sigs( floatx80 a, floatx80 b, flag zSign )
+static floatx80 addFloatx80Sigs( struct roundingData *roundData, floatx80 a, floatx80 b, flag zSign )
 {
     int32 aExp, bExp, zExp;
     bits64 aSig, bSig, zSig0, zSig1;
@@ -2814,7 +2805,7 @@ static floatx80 addFloatx80Sigs( floatx80 a, floatx80 b, flag zSign )
  roundAndPack:
     return
         roundAndPackFloatx80(
-            floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );
+            roundData, zSign, zExp, zSig0, zSig1 );
 
 }
 
@@ -2827,7 +2818,7 @@ result is a NaN.  The subtraction is performed according to the IEC/IEEE
 Standard for Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-static floatx80 subFloatx80Sigs( floatx80 a, floatx80 b, flag zSign )
+static floatx80 subFloatx80Sigs( struct roundingData *roundData, floatx80 a, floatx80 b, flag zSign )
 {
     int32 aExp, bExp, zExp;
     bits64 aSig, bSig, zSig0, zSig1;
@@ -2845,7 +2836,7 @@ static floatx80 subFloatx80Sigs( floatx80 a, floatx80 b, flag zSign )
         if ( (bits64) ( ( aSig | bSig )<<1 ) ) {
             return propagateFloatx80NaN( a, b );
         }
-        float_raise( float_flag_invalid );
+        roundData->exception |= float_flag_invalid;
         z.low = floatx80_default_nan_low;
         z.high = floatx80_default_nan_high;
         return z;
@@ -2857,7 +2848,7 @@ static floatx80 subFloatx80Sigs( floatx80 a, floatx80 b, flag zSign )
     zSig1 = 0;
     if ( bSig < aSig ) goto aBigger;
     if ( aSig < bSig ) goto bBigger;
-    return packFloatx80( float_rounding_mode == float_round_down, 0, 0 );
+    return packFloatx80( roundData->mode == float_round_down, 0, 0 );
  bExpBigger:
     if ( bExp == 0x7FFF ) {
         if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );
@@ -2883,7 +2874,7 @@ static floatx80 subFloatx80Sigs( floatx80 a, floatx80 b, flag zSign )
  normalizeRoundAndPack:
     return
         normalizeRoundAndPackFloatx80(
-            floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );
+            roundData, zSign, zExp, zSig0, zSig1 );
 
 }
 
@@ -2894,17 +2885,17 @@ values `a' and `b'.  The operation is performed according to the IEC/IEEE
 Standard for Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-floatx80 floatx80_add( floatx80 a, floatx80 b )
+floatx80 floatx80_add( struct roundingData *roundData, floatx80 a, floatx80 b )
 {
     flag aSign, bSign;
     
     aSign = extractFloatx80Sign( a );
     bSign = extractFloatx80Sign( b );
     if ( aSign == bSign ) {
-        return addFloatx80Sigs( a, b, aSign );
+        return addFloatx80Sigs( roundData, a, b, aSign );
     }
     else {
-        return subFloatx80Sigs( a, b, aSign );
+        return subFloatx80Sigs( roundData, a, b, aSign );
     }
     
 }
@@ -2916,17 +2907,17 @@ point values `a' and `b'.  The operation is performed according to the
 IEC/IEEE Standard for Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-floatx80 floatx80_sub( floatx80 a, floatx80 b )
+floatx80 floatx80_sub( struct roundingData *roundData, floatx80 a, floatx80 b )
 {
     flag aSign, bSign;
 
     aSign = extractFloatx80Sign( a );
     bSign = extractFloatx80Sign( b );
     if ( aSign == bSign ) {
-        return subFloatx80Sigs( a, b, aSign );
+        return subFloatx80Sigs( roundData, a, b, aSign );
     }
     else {
-        return addFloatx80Sigs( a, b, aSign );
+        return addFloatx80Sigs( roundData, a, b, aSign );
     }
 
 }
@@ -2938,7 +2929,7 @@ point values `a' and `b'.  The operation is performed according to the
 IEC/IEEE Standard for Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-floatx80 floatx80_mul( floatx80 a, floatx80 b )
+floatx80 floatx80_mul( struct roundingData *roundData, floatx80 a, floatx80 b )
 {
     flag aSign, bSign, zSign;
     int32 aExp, bExp, zExp;
@@ -2964,7 +2955,7 @@ floatx80 floatx80_mul( floatx80 a, floatx80 b )
         if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );
         if ( ( aExp | aSig ) == 0 ) {
  invalid:
-            float_raise( float_flag_invalid );
+            roundData->exception |= float_flag_invalid;
             z.low = floatx80_default_nan_low;
             z.high = floatx80_default_nan_high;
             return z;
@@ -2987,7 +2978,7 @@ floatx80 floatx80_mul( floatx80 a, floatx80 b )
     }
     return
         roundAndPackFloatx80(
-            floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );
+            roundData, zSign, zExp, zSig0, zSig1 );
 
 }
 
@@ -2998,7 +2989,7 @@ value `a' by the corresponding value `b'.  The operation is performed
 according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-floatx80 floatx80_div( floatx80 a, floatx80 b )
+floatx80 floatx80_div( struct roundingData *roundData, floatx80 a, floatx80 b )
 {
     flag aSign, bSign, zSign;
     int32 aExp, bExp, zExp;
@@ -3029,12 +3020,12 @@ floatx80 floatx80_div( floatx80 a, floatx80 b )
         if ( bSig == 0 ) {
             if ( ( aExp | aSig ) == 0 ) {
  invalid:
-                float_raise( float_flag_invalid );
+                roundData->exception |= float_flag_invalid;
                 z.low = floatx80_default_nan_low;
                 z.high = floatx80_default_nan_high;
                 return z;
             }
-            float_raise( float_flag_divbyzero );
+            roundData->exception |= float_flag_divbyzero;
             return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
         }
         normalizeFloatx80Subnormal( bSig, &bExp, &bSig );
@@ -3068,7 +3059,7 @@ floatx80 floatx80_div( floatx80 a, floatx80 b )
     }
     return
         roundAndPackFloatx80(
-            floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );
+            roundData, zSign, zExp, zSig0, zSig1 );
 
 }
 
@@ -3079,7 +3070,7 @@ Returns the remainder of the extended double-precision floating-point value
 according to the IEC/IEEE Standard for Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-floatx80 floatx80_rem( floatx80 a, floatx80 b )
+floatx80 floatx80_rem( struct roundingData *roundData, floatx80 a, floatx80 b )
 {
     flag aSign, bSign, zSign;
     int32 aExp, bExp, expDiff;
@@ -3107,7 +3098,7 @@ floatx80 floatx80_rem( floatx80 a, floatx80 b )
     if ( bExp == 0 ) {
         if ( bSig == 0 ) {
  invalid:
-            float_raise( float_flag_invalid );
+            roundData->exception |= float_flag_invalid;
             z.low = floatx80_default_nan_low;
             z.high = floatx80_default_nan_high;
             return z;
@@ -3164,9 +3155,10 @@ floatx80 floatx80_rem( floatx80 a, floatx80 b )
         aSig1 = alternateASig1;
         zSign = ! zSign;
     }
+
     return
         normalizeRoundAndPackFloatx80(
-            80, zSign, bExp + expDiff, aSig0, aSig1 );
+            roundData, zSign, bExp + expDiff, aSig0, aSig1 );
 
 }
 
@@ -3177,7 +3169,7 @@ value `a'.  The operation is performed according to the IEC/IEEE Standard
 for Binary Floating-point Arithmetic.
 -------------------------------------------------------------------------------
 */
-floatx80 floatx80_sqrt( floatx80 a )
+floatx80 floatx80_sqrt( struct roundingData *roundData, floatx80 a )
 {
     flag aSign;
     int32 aExp, zExp;
@@ -3197,7 +3189,7 @@ floatx80 floatx80_sqrt( floatx80 a )
     if ( aSign ) {
         if ( ( aExp | aSig0 ) == 0 ) return a;
  invalid:
-        float_raise( float_flag_invalid );
+        roundData->exception |= float_flag_invalid;
         z.low = floatx80_default_nan_low;
         z.high = floatx80_default_nan_high;
         return z;
@@ -3242,7 +3234,7 @@ floatx80 floatx80_sqrt( floatx80 a )
     }
     return
         roundAndPackFloatx80(
-            floatx80_rounding_precision, 0, zExp, zSig0, zSig1 );
+            roundData, 0, zExp, zSig0, zSig1 );
 
 }
 
@@ -3264,7 +3256,7 @@ flag floatx80_eq( floatx80 a, floatx80 b )
        ) {
         if (    floatx80_is_signaling_nan( a )
              || floatx80_is_signaling_nan( b ) ) {
-            float_raise( float_flag_invalid );
+            roundData->exception |= float_flag_invalid;
         }
         return 0;
     }
@@ -3294,7 +3286,7 @@ flag floatx80_le( floatx80 a, floatx80 b )
          || (    ( extractFloatx80Exp( b ) == 0x7FFF )
               && (bits64) ( extractFloatx80Frac( b )<<1 ) )
        ) {
-        float_raise( float_flag_invalid );
+        roundData->exception |= float_flag_invalid;
         return 0;
     }
     aSign = extractFloatx80Sign( a );
@@ -3328,7 +3320,7 @@ flag floatx80_lt( floatx80 a, floatx80 b )
          || (    ( extractFloatx80Exp( b ) == 0x7FFF )
               && (bits64) ( extractFloatx80Frac( b )<<1 ) )
        ) {
-        float_raise( float_flag_invalid );
+        roundData->exception |= float_flag_invalid;
         return 0;
     }
     aSign = extractFloatx80Sign( a );
@@ -3361,7 +3353,7 @@ flag floatx80_eq_signaling( floatx80 a, floatx80 b )
          || (    ( extractFloatx80Exp( b ) == 0x7FFF )
               && (bits64) ( extractFloatx80Frac( b )<<1 ) )
        ) {
-        float_raise( float_flag_invalid );
+        roundData->exception |= float_flag_invalid;
         return 0;
     }
     return
@@ -3392,7 +3384,7 @@ flag floatx80_le_quiet( floatx80 a, floatx80 b )
        ) {
         if (    floatx80_is_signaling_nan( a )
              || floatx80_is_signaling_nan( b ) ) {
-            float_raise( float_flag_invalid );
+            roundData->exception |= float_flag_invalid;
         }
         return 0;
     }
@@ -3429,7 +3421,7 @@ flag floatx80_lt_quiet( floatx80 a, floatx80 b )
        ) {
         if (    floatx80_is_signaling_nan( a )
              || floatx80_is_signaling_nan( b ) ) {
-            float_raise( float_flag_invalid );
+            roundData->exception |= float_flag_invalid;
         }
         return 0;
     }
diff --git a/arch/arm/nwfpe/softfloat.h b/arch/arm/nwfpe/softfloat.h
index 1e174317389..1c8799b9ee4 100644
--- a/arch/arm/nwfpe/softfloat.h
+++ b/arch/arm/nwfpe/softfloat.h
@@ -74,7 +74,7 @@ enum {
 Software IEC/IEEE floating-point rounding mode.
 -------------------------------------------------------------------------------
 */
-extern signed char float_rounding_mode;
+//extern int8 float_rounding_mode;
 enum {
     float_round_nearest_even = 0,
     float_round_to_zero      = 1,
@@ -86,7 +86,6 @@ enum {
 -------------------------------------------------------------------------------
 Software IEC/IEEE floating-point exception flags.
 -------------------------------------------------------------------------------
-extern signed char float_exception_flags;
 enum {
     float_flag_inexact   =  1,
     float_flag_underflow =  2,
@@ -99,7 +98,6 @@ ScottB: November 4, 1998
 Changed the enumeration to match the bit order in the FPA11.
 */
 
-extern signed char float_exception_flags;
 enum {
     float_flag_invalid   =  1,
     float_flag_divbyzero =  2,
@@ -121,7 +119,7 @@ void float_raise( signed char );
 Software IEC/IEEE integer-to-floating-point conversion routines.
 -------------------------------------------------------------------------------
 */
-float32 int32_to_float32( signed int );
+float32 int32_to_float32( struct roundingData *, signed int );
 float64 int32_to_float64( signed int );
 #ifdef FLOATX80
 floatx80 int32_to_floatx80( signed int );
@@ -132,7 +130,7 @@ floatx80 int32_to_floatx80( signed int );
 Software IEC/IEEE single-precision conversion routines.
 -------------------------------------------------------------------------------
 */
-signed int float32_to_int32( float32 );
+signed int float32_to_int32( struct roundingData *, float32 );
 signed int float32_to_int32_round_to_zero( float32 );
 float64 float32_to_float64( float32 );
 #ifdef FLOATX80
@@ -144,13 +142,13 @@ floatx80 float32_to_floatx80( float32 );
 Software IEC/IEEE single-precision operations.
 -------------------------------------------------------------------------------
 */
-float32 float32_round_to_int( float32 );
-float32 float32_add( float32, float32 );
-float32 float32_sub( float32, float32 );
-float32 float32_mul( float32, float32 );
-float32 float32_div( float32, float32 );
-float32 float32_rem( float32, float32 );
-float32 float32_sqrt( float32 );
+float32 float32_round_to_int( struct roundingData*, float32 );
+float32 float32_add( struct roundingData *, float32, float32 );
+float32 float32_sub( struct roundingData *, float32, float32 );
+float32 float32_mul( struct roundingData *, float32, float32 );
+float32 float32_div( struct roundingData *, float32, float32 );
+float32 float32_rem( struct roundingData *, float32, float32 );
+float32 float32_sqrt( struct roundingData*, float32 );
 char float32_eq( float32, float32 );
 char float32_le( float32, float32 );
 char float32_lt( float32, float32 );
@@ -164,9 +162,9 @@ char float32_is_signaling_nan( float32 );
 Software IEC/IEEE double-precision conversion routines.
 -------------------------------------------------------------------------------
 */
-signed int float64_to_int32( float64 );
+signed int float64_to_int32( struct roundingData *, float64 );
 signed int float64_to_int32_round_to_zero( float64 );
-float32 float64_to_float32( float64 );
+float32 float64_to_float32( struct roundingData *, float64 );
 #ifdef FLOATX80
 floatx80 float64_to_floatx80( float64 );
 #endif
@@ -176,13 +174,13 @@ floatx80 float64_to_floatx80( float64 );
 Software IEC/IEEE double-precision operations.
 -------------------------------------------------------------------------------
 */
-float64 float64_round_to_int( float64 );
-float64 float64_add( float64, float64 );
-float64 float64_sub( float64, float64 );
-float64 float64_mul( float64, float64 );
-float64 float64_div( float64, float64 );
-float64 float64_rem( float64, float64 );
-float64 float64_sqrt( float64 );
+float64 float64_round_to_int( struct roundingData *, float64 );
+float64 float64_add( struct roundingData *, float64, float64 );
+float64 float64_sub( struct roundingData *, float64, float64 );
+float64 float64_mul( struct roundingData *, float64, float64 );
+float64 float64_div( struct roundingData *, float64, float64 );
+float64 float64_rem( struct roundingData *, float64, float64 );
+float64 float64_sqrt( struct roundingData *, float64 );
 char float64_eq( float64, float64 );
 char float64_le( float64, float64 );
 char float64_lt( float64, float64 );
@@ -198,31 +196,23 @@ char float64_is_signaling_nan( float64 );
 Software IEC/IEEE extended double-precision conversion routines.
 -------------------------------------------------------------------------------
 */
-signed int floatx80_to_int32( floatx80 );
+signed int floatx80_to_int32( struct roundingData *, floatx80 );
 signed int floatx80_to_int32_round_to_zero( floatx80 );
-float32 floatx80_to_float32( floatx80 );
-float64 floatx80_to_float64( floatx80 );
-
-/*
--------------------------------------------------------------------------------
-Software IEC/IEEE extended double-precision rounding precision.  Valid
-values are 32, 64, and 80.
--------------------------------------------------------------------------------
-*/
-extern signed char floatx80_rounding_precision;
+float32 floatx80_to_float32( struct roundingData *, floatx80 );
+float64 floatx80_to_float64( struct roundingData *, floatx80 );
 
 /*
 -------------------------------------------------------------------------------
 Software IEC/IEEE extended double-precision operations.
 -------------------------------------------------------------------------------
 */
-floatx80 floatx80_round_to_int( floatx80 );
-floatx80 floatx80_add( floatx80, floatx80 );
-floatx80 floatx80_sub( floatx80, floatx80 );
-floatx80 floatx80_mul( floatx80, floatx80 );
-floatx80 floatx80_div( floatx80, floatx80 );
-floatx80 floatx80_rem( floatx80, floatx80 );
-floatx80 floatx80_sqrt( floatx80 );
+floatx80 floatx80_round_to_int( struct roundingData *, floatx80 );
+floatx80 floatx80_add( struct roundingData *, floatx80, floatx80 );
+floatx80 floatx80_sub( struct roundingData *, floatx80, floatx80 );
+floatx80 floatx80_mul( struct roundingData *, floatx80, floatx80 );
+floatx80 floatx80_div( struct roundingData *, floatx80, floatx80 );
+floatx80 floatx80_rem( struct roundingData *, floatx80, floatx80 );
+floatx80 floatx80_sqrt( struct roundingData *, floatx80 );
 char floatx80_eq( floatx80, floatx80 );
 char floatx80_le( floatx80, floatx80 );
 char floatx80_lt( floatx80, floatx80 );
diff --git a/arch/arm/oprofile/backtrace.c b/arch/arm/oprofile/backtrace.c
index ec58d3e2eb8..df35c452a8b 100644
--- a/arch/arm/oprofile/backtrace.c
+++ b/arch/arm/oprofile/backtrace.c
@@ -115,7 +115,7 @@ static int valid_kernel_stack(struct frame_tail *tail, struct pt_regs *regs)
 	return (tailaddr > stack) && (tailaddr < stack_base);
 }
 
-void arm_backtrace(struct pt_regs const *regs, unsigned int depth)
+void arm_backtrace(struct pt_regs * const regs, unsigned int depth)
 {
 	struct frame_tail *tail;
 	unsigned long last_address = 0;
diff --git a/arch/arm/vfp/vfpdouble.c b/arch/arm/vfp/vfpdouble.c
index b801cd66b6e..9b367a65cb4 100644
--- a/arch/arm/vfp/vfpdouble.c
+++ b/arch/arm/vfp/vfpdouble.c
@@ -770,6 +770,9 @@ vfp_double_add(struct vfp_double *vdd, struct vfp_double *vdn,
 		if ((s64)m_sig < 0) {
 			vdd->sign = vfp_sign_negate(vdd->sign);
 			m_sig = -m_sig;
+		} else if (m_sig == 0) {
+			vdd->sign = (fpscr & FPSCR_RMODE_MASK) ==
+				      FPSCR_ROUND_MINUSINF ? 0x8000 : 0;
 		}
 	} else {
 		m_sig += vdn->significand;
diff --git a/arch/arm26/mm/fault.c b/arch/arm26/mm/fault.c
index dacca8bb774..bd6f2db608b 100644
--- a/arch/arm26/mm/fault.c
+++ b/arch/arm26/mm/fault.c
@@ -176,12 +176,12 @@ survive:
 	 * Handle the "normal" cases first - successful and sigbus
 	 */
 	switch (fault) {
-	case 2:
+	case VM_FAULT_MAJOR:
 		tsk->maj_flt++;
 		return fault;
-	case 1:
+	case VM_FAULT_MINOR:
 		tsk->min_flt++;
-	case 0:
+	case VM_FAULT_SIGBUS:
 		return fault;
 	}
 
@@ -226,14 +226,11 @@ int do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 	/*
 	 * Handle the "normal" case first
 	 */
-	if (fault > 0)
+	switch (fault) {
+	case VM_FAULT_MINOR:
+	case VM_FAULT_MAJOR:
 		return 0;
-
-	/*
-	 * We had some memory, but were unable to
-	 * successfully fix up this page fault.
-	 */
-	if (fault == 0){
+	case VM_FAULT_SIGBUS:
 		goto do_sigbus;
 	}
 
diff --git a/arch/cris/Kconfig.debug b/arch/cris/Kconfig.debug
index f42918bf22a..cd72324935c 100644
--- a/arch/cris/Kconfig.debug
+++ b/arch/cris/Kconfig.debug
@@ -38,4 +38,9 @@ config FRAME_POINTER
           If you don't debug the kernel, you can say N, but we may not be able
           to solve problems without frame pointers.
 
+config DEBUG_NMI_OOPS
+       bool "NMI causes oops printout"
+       help
+         If the system locks up without any debug information you can say Y
+         here to make it possible to dump an OOPS with an external NMI.
 endmenu
diff --git a/arch/cris/Makefile b/arch/cris/Makefile
index 9d28fa8563c..90ca8730b12 100644
--- a/arch/cris/Makefile
+++ b/arch/cris/Makefile
@@ -1,4 +1,4 @@
-# $Id: Makefile,v 1.23 2004/10/19 13:07:34 starvik Exp $
+# $Id: Makefile,v 1.28 2005/03/17 10:44:37 larsv Exp $
 # cris/Makefile
 #
 # This file is included by the global makefile so that you can add your own
@@ -15,6 +15,7 @@
 
 arch-y := v10
 arch-$(CONFIG_ETRAX_ARCH_V10) := v10
+arch-$(CONFIG_ETRAX_ARCH_V32) := v32
 
 # No config avaiable for make clean etc
 ifneq ($(arch-y),)
@@ -46,6 +47,21 @@ core-y		+= arch/$(ARCH)/$(SARCH)/kernel/ arch/$(ARCH)/$(SARCH)/mm/
 drivers-y	+= arch/$(ARCH)/$(SARCH)/drivers/
 libs-y		+= arch/$(ARCH)/$(SARCH)/lib/ $(LIBGCC)
 
+# cris source path
+SRC_ARCH              = $(srctree)/arch/$(ARCH)
+# cris object files path
+OBJ_ARCH              = $(objtree)/arch/$(ARCH)
+
+target_boot_arch_dir  = $(OBJ_ARCH)/$(SARCH)/boot
+target_boot_dir       = $(OBJ_ARCH)/boot
+src_boot_dir          = $(SRC_ARCH)/boot
+target_compressed_dir = $(OBJ_ARCH)/boot/compressed
+src_compressed_dir    = $(SRC_ARCH)/boot/compressed
+target_rescue_dir     = $(OBJ_ARCH)/boot/rescue
+src_rescue_dir        = $(SRC_ARCH)/boot/rescue
+
+export target_boot_arch_dir target_boot_dir src_boot_dir target_compressed_dir src_compressed_dir target_rescue_dir src_rescue_dir
+
 vmlinux.bin: vmlinux
 	$(OBJCOPY) $(OBJCOPYFLAGS) vmlinux vmlinux.bin
 
@@ -65,44 +81,52 @@ cramfs:
 
 clinux: vmlinux.bin decompress.bin rescue.bin
 
-decompress.bin: FORCE
-	@make -C arch/$(ARCH)/boot/compressed decompress.bin
+decompress.bin: $(target_boot_dir)
+	@$(MAKE) -f $(src_compressed_dir)/Makefile $(target_compressed_dir)/decompress.bin
 
-rescue.bin: FORCE
-	@make -C arch/$(ARCH)/boot/rescue rescue.bin
+$(target_rescue_dir)/rescue.bin: $(target_boot_dir)
+	@$(MAKE) -f $(src_rescue_dir)/Makefile $(target_rescue_dir)/rescue.bin
 
-zImage: vmlinux.bin rescue.bin
+zImage: $(target_boot_dir) vmlinux.bin $(target_rescue_dir)/rescue.bin
 ## zImage     - Compressed kernel (gzip)
-	@make -C arch/$(ARCH)/boot/ zImage
+	@$(MAKE) -f $(src_boot_dir)/Makefile zImage
+
+$(target_boot_dir): $(target_boot_arch_dir)
+	ln -sfn $< $@
+
+$(target_boot_arch_dir):
+	mkdir -p $@
 
 compressed: zImage
 
 archmrproper:
 archclean:
-	$(Q)$(MAKE) $(clean)=arch/$(ARCH)/boot
+	@if [ -d arch/$(ARCH)/boot ]; then \
+		$(MAKE) $(clean)=arch/$(ARCH)/boot ; \
+	fi
 	rm -f timage vmlinux.bin decompress.bin rescue.bin cramfs.img
 	rm -rf $(LD_SCRIPT).tmp
 
-prepare: arch/$(ARCH)/.links include/asm-$(ARCH)/.arch \
+prepare: $(SRC_ARCH)/.links $(srctree)/include/asm-$(ARCH)/.arch \
 	 include/asm-$(ARCH)/$(SARCH)/offset.h
 
 # Create some links to make all tools happy
-arch/$(ARCH)/.links:
-	@rm -rf arch/$(ARCH)/drivers
-	@ln -sfn $(SARCH)/drivers arch/$(ARCH)/drivers
-	@rm -rf arch/$(ARCH)/boot
-	@ln -sfn $(SARCH)/boot arch/$(ARCH)/boot
-	@rm -rf arch/$(ARCH)/lib
-	@ln -sfn $(SARCH)/lib arch/$(ARCH)/lib
-	@ln -sfn $(SARCH) arch/$(ARCH)/arch
-	@ln -sfn ../$(SARCH)/vmlinux.lds.S arch/$(ARCH)/kernel/vmlinux.lds.S
+$(SRC_ARCH)/.links:
+	@rm -rf $(SRC_ARCH)/drivers
+	@ln -sfn $(SRC_ARCH)/$(SARCH)/drivers $(SRC_ARCH)/drivers
+	@rm -rf $(SRC_ARCH)/boot
+	@ln -sfn $(SRC_ARCH)/$(SARCH)/boot $(SRC_ARCH)/boot
+	@rm -rf $(SRC_ARCH)/lib
+	@ln -sfn $(SRC_ARCH)/$(SARCH)/lib $(SRC_ARCH)/lib
+	@ln -sfn $(SRC_ARCH)/$(SARCH) $(SRC_ARCH)/arch
+	@ln -sfn $(SRC_ARCH)/$(SARCH)/vmlinux.lds.S $(SRC_ARCH)/kernel/vmlinux.lds.S
 	@touch $@
 
 # Create link to sub arch includes
-include/asm-$(ARCH)/.arch: $(wildcard include/config/arch/*.h)
-	@echo '  Making asm-$(ARCH)/arch -> asm-$(ARCH)/$(SARCH) symlink'
+$(srctree)/include/asm-$(ARCH)/.arch: $(wildcard include/config/arch/*.h)
+	@echo '  Making $(srctree)/include/asm-$(ARCH)/arch -> $(srctree)/include/asm-$(ARCH)/$(SARCH) symlink'
 	@rm -f include/asm-$(ARCH)/arch
-	@ln -sf $(SARCH) include/asm-$(ARCH)/arch
+	@ln -sf $(srctree)/include/asm-$(ARCH)/$(SARCH) $(srctree)/include/asm-$(ARCH)/arch
 	@touch $@
 
 arch/$(ARCH)/$(SARCH)/kernel/asm-offsets.s: include/asm include/linux/version.h \
diff --git a/arch/cris/arch-v10/Kconfig b/arch/cris/arch-v10/Kconfig
index 2ca64cc40c6..44eb1b9accb 100644
--- a/arch/cris/arch-v10/Kconfig
+++ b/arch/cris/arch-v10/Kconfig
@@ -260,6 +260,37 @@ config ETRAX_DEBUG_PORT_NULL
 endchoice
 
 choice
+	prompt "Kernel GDB port"
+	depends on ETRAX_KGDB
+	default ETRAX_KGDB_PORT0
+	help
+	  Choose a serial port for kernel debugging.  NOTE: This port should
+	  not be enabled under Drivers for built-in interfaces (as it has its
+	  own initialization code) and should not be the same as the debug port.
+
+config ETRAX_KGDB_PORT0
+	bool "Serial-0"
+	help
+	  Use serial port 0 for kernel debugging.
+
+config ETRAX_KGDB_PORT1
+	bool "Serial-1"
+	help
+	  Use serial port 1 for kernel debugging.
+
+config ETRAX_KGDB_PORT2
+	bool "Serial-2"
+	help
+	  Use serial port 2 for kernel debugging.
+
+config ETRAX_KGDB_PORT3
+	bool "Serial-3"
+	help
+	  Use serial port 3 for kernel debugging.
+
+endchoice
+
+choice
 	prompt "Product rescue-port"
 	depends on ETRAX_ARCH_V10
 	default ETRAX_RESCUE_SER0
diff --git a/arch/cris/arch-v10/boot/Makefile b/arch/cris/arch-v10/boot/Makefile
index fe6650368e6..e5b10585110 100644
--- a/arch/cris/arch-v10/boot/Makefile
+++ b/arch/cris/arch-v10/boot/Makefile
@@ -1,12 +1,13 @@
 #
 # arch/cris/boot/Makefile
 #
+target = $(target_boot_dir)
+src    = $(src_boot_dir)
 
 zImage: compressed/vmlinuz
 
-compressed/vmlinuz: $(TOPDIR)/vmlinux
-	@$(MAKE) -C compressed vmlinuz
+compressed/vmlinuz:
+	@$(MAKE) -f $(src)/compressed/Makefile $(target_compressed_dir)/vmlinuz
 
 clean:
-	rm -f zImage tools/build compressed/vmlinux.out
-	@$(MAKE) -C compressed clean
+	@$(MAKE) -f $(src)/compressed/Makefile clean
diff --git a/arch/cris/arch-v10/boot/compressed/Makefile b/arch/cris/arch-v10/boot/compressed/Makefile
index 5f71c2c819e..6584a44820f 100644
--- a/arch/cris/arch-v10/boot/compressed/Makefile
+++ b/arch/cris/arch-v10/boot/compressed/Makefile
@@ -1,40 +1,45 @@
 #
-# linux/arch/etrax100/boot/compressed/Makefile
-#
-# create a compressed vmlinux image from the original vmlinux files and romfs
+# create a compressed vmlinuz image from the binary vmlinux.bin file
 #
+target = $(target_compressed_dir)
+src    = $(src_compressed_dir)
 
-CC = gcc-cris -melf -I $(TOPDIR)/include
+CC = gcc-cris -melf $(LINUXINCLUDE)
 CFLAGS = -O2
 LD = ld-cris
 OBJCOPY = objcopy-cris
 OBJCOPYFLAGS = -O binary --remove-section=.bss
-OBJECTS = head.o misc.o
+OBJECTS = $(target)/head.o $(target)/misc.o
 
 # files to compress
-SYSTEM = $(TOPDIR)/vmlinux.bin
+SYSTEM = $(objtree)/vmlinux.bin
 
-all: vmlinuz
+all: $(target_compressed_dir)/vmlinuz
 
-decompress.bin: $(OBJECTS)
-	$(LD) -T decompress.ld -o decompress.o $(OBJECTS)
-	$(OBJCOPY) $(OBJCOPYFLAGS) decompress.o decompress.bin
-# save it for mkprod in the topdir.
-	cp decompress.bin $(TOPDIR)
+$(target)/decompress.bin: $(OBJECTS)
+	$(LD) -T $(src)/decompress.ld -o $(target)/decompress.o $(OBJECTS)
+	$(OBJCOPY) $(OBJCOPYFLAGS) $(target)/decompress.o $(target)/decompress.bin
 
+# Create vmlinuz image in top-level build directory
+$(target_compressed_dir)/vmlinuz: $(target) piggy.img $(target)/decompress.bin
+	@echo "  COMPR   vmlinux.bin --> vmlinuz"
+	@cat $(target)/decompress.bin piggy.img > $(target_compressed_dir)/vmlinuz
+	@rm -f piggy.img
 
-vmlinuz: piggy.img decompress.bin
-	cat decompress.bin piggy.img > vmlinuz
-	rm -f piggy.img
+$(target)/head.o: $(src)/head.S
+	$(CC) -D__ASSEMBLY__ -traditional -c $< -o $@
 
-head.o: head.S
-	$(CC) -D__ASSEMBLY__ -traditional -c head.S -o head.o
+$(target)/misc.o: $(src)/misc.c
+	$(CC) -D__KERNEL__ -c $< -o $@
 
 # gzip the kernel image
 
 piggy.img: $(SYSTEM)
-	cat $(SYSTEM) | gzip -f -9 > piggy.img
+	@cat $(SYSTEM) | gzip -f -9 > piggy.img
+
+$(target):
+	mkdir -p $(target)
 
 clean:
-	rm -f piggy.img vmlinuz vmlinuz.o
+	rm -f piggy.img $(objtree)/vmlinuz
 
diff --git a/arch/cris/arch-v10/boot/compressed/head.S b/arch/cris/arch-v10/boot/compressed/head.S
index 4cbdd4b1d9d..e73f44c998d 100644
--- a/arch/cris/arch-v10/boot/compressed/head.S
+++ b/arch/cris/arch-v10/boot/compressed/head.S
@@ -13,7 +13,8 @@
 #include <asm/arch/sv_addr_ag.h>
 
 #define RAM_INIT_MAGIC 0x56902387
-	
+#define COMMAND_LINE_MAGIC 0x87109563
+
 	;; Exported symbols
 	
 	.globl	_input_data
@@ -88,6 +89,12 @@ basse:	move.d	pc, r5
 	cmp.d	r2, r1
 	bcs	1b
 	nop
+
+	;;  Save command line magic and address.
+	move.d	_cmd_line_magic, $r12
+	move.d  $r10, [$r12]
+	move.d	_cmd_line_addr, $r12
+	move.d  $r11, [$r12]
 	
 	;; Do the decompression and save compressed size in _inptr
 
@@ -98,7 +105,13 @@ basse:	move.d	pc, r5
 
 	move.d	[_input_data], r9	; flash address of compressed kernel
 	add.d	[_inptr], r9		; size of compressed kernel
-	 
+
+	;; Restore command line magic and address.
+	move.d  _cmd_line_magic, $r10
+	move.d  [$r10], $r10
+	move.d  _cmd_line_addr, $r11
+	move.d  [$r11], $r11
+
 	;; Enter the decompressed kernel
 	move.d	RAM_INIT_MAGIC, r8	; Tell kernel that DRAM is initialized
 	jump	0x40004000	; kernel is linked to this address
@@ -107,5 +120,8 @@ basse:	move.d	pc, r5
 
 _input_data:
 	.dword	0		; used by the decompressor
-
+_cmd_line_magic:
+	.dword 0
+_cmd_line_addr:
+	.dword 0
 #include "../../lib/hw_settings.S"
diff --git a/arch/cris/arch-v10/boot/rescue/Makefile b/arch/cris/arch-v10/boot/rescue/Makefile
index e9f2ba2ad02..8be9b313031 100644
--- a/arch/cris/arch-v10/boot/rescue/Makefile
+++ b/arch/cris/arch-v10/boot/rescue/Makefile
@@ -1,52 +1,53 @@
 #
 # Makefile for rescue code
 #
-ifndef TOPDIR
-TOPDIR = ../../../..
-endif
-CC = gcc-cris -mlinux -I $(TOPDIR)/include
+target = $(target_rescue_dir)
+src    = $(src_rescue_dir)
+
+CC = gcc-cris -mlinux $(LINUXINCLUDE)
 CFLAGS = -O2
 LD = gcc-cris -mlinux -nostdlib
 OBJCOPY = objcopy-cris
 OBJCOPYFLAGS = -O binary --remove-section=.bss
 
-all: rescue.bin testrescue.bin kimagerescue.bin
-
-rescue: rescue.bin
-	# do nothing
+all: $(target)/rescue.bin $(target)/testrescue.bin $(target)/kimagerescue.bin
 
-rescue.bin: head.o
-	$(LD) -T rescue.ld -o rescue.o head.o
-	$(OBJCOPY) $(OBJCOPYFLAGS) rescue.o rescue.bin
-	cp rescue.bin $(TOPDIR)
+$(target)/rescue.bin: $(target) $(target)/head.o
+	$(LD) -T $(src)/rescue.ld -o $(target)/rescue.o $(target)/head.o
+	$(OBJCOPY) $(OBJCOPYFLAGS) $(target)/rescue.o $(target)/rescue.bin
+# Place a copy in top-level build directory
+	cp -p $(target)/rescue.bin $(objtree)
 
-testrescue.bin: testrescue.o
-	$(OBJCOPY) $(OBJCOPYFLAGS) testrescue.o tr.bin
+$(target)/testrescue.bin: $(target) $(target)/testrescue.o
+	$(OBJCOPY) $(OBJCOPYFLAGS) $(target)/testrescue.o tr.bin
 # Pad it to 784 bytes
 	dd if=/dev/zero of=tmp2423 bs=1 count=784
 	cat tr.bin tmp2423 >testrescue_tmp.bin
-	dd if=testrescue_tmp.bin of=testrescue.bin bs=1 count=784
+	dd if=testrescue_tmp.bin of=$(target)/testrescue.bin bs=1 count=784
 	rm tr.bin tmp2423 testrescue_tmp.bin
 
-kimagerescue.bin: kimagerescue.o
-	$(OBJCOPY) $(OBJCOPYFLAGS) kimagerescue.o ktr.bin
+$(target)/kimagerescue.bin: $(target) $(target)/kimagerescue.o
+	$(OBJCOPY) $(OBJCOPYFLAGS) $(target)/kimagerescue.o ktr.bin
 # Pad it to 784 bytes, that's what the rescue loader expects
 	dd if=/dev/zero of=tmp2423 bs=1 count=784
 	cat ktr.bin tmp2423 >kimagerescue_tmp.bin
-	dd if=kimagerescue_tmp.bin of=kimagerescue.bin bs=1 count=784
+	dd if=kimagerescue_tmp.bin of=$(target)/kimagerescue.bin bs=1 count=784
 	rm ktr.bin tmp2423 kimagerescue_tmp.bin
 
-head.o: head.S
+$(target):
+	mkdir -p $(target)
+
+$(target)/head.o: $(src)/head.S
 	$(CC) -D__ASSEMBLY__ -traditional -c $< -o $*.o
 
-testrescue.o: testrescue.S
+$(target)/testrescue.o: $(src)/testrescue.S
 	$(CC) -D__ASSEMBLY__ -traditional -c $< -o $*.o
 
-kimagerescue.o: kimagerescue.S
+$(target)/kimagerescue.o: $(src)/kimagerescue.S
 	$(CC) -D__ASSEMBLY__ -traditional -c $< -o $*.o
 
 clean:
-	rm -f *.o *.bin
+	rm -f $(target)/*.o $(target)/*.bin
 
 fastdep:
 
diff --git a/arch/cris/arch-v10/boot/rescue/head.S b/arch/cris/arch-v10/boot/rescue/head.S
index 8689ea972c4..addb2194de0 100644
--- a/arch/cris/arch-v10/boot/rescue/head.S
+++ b/arch/cris/arch-v10/boot/rescue/head.S
@@ -1,4 +1,4 @@
-/* $Id: head.S,v 1.6 2003/04/09 08:12:43 pkj Exp $
+/* $Id: head.S,v 1.7 2005/03/07 12:11:06 starvik Exp $
  * 
  * Rescue code, made to reside at the beginning of the
  * flash-memory. when it starts, it checks a partition
@@ -121,12 +121,13 @@
 	;; 0x80000000 if loaded in flash (as it should be)
 	;; since etrax actually starts at address 2 when booting from flash, we
 	;; put a nop (2 bytes) here first so we dont accidentally skip the di
-	
+
 	nop	
 	di
 
 	jump	in_cache	; enter cached area instead
-in_cache:	
+in_cache:
+
 
 	;; first put a jump test to give a possibility of upgrading the rescue code
 	;; without erasing/reflashing the sector. we put a longword of -1 here and if
@@ -325,9 +326,29 @@ flash_ok:
 	;; result will be in r0
 checksum:
 	moveq	0, $r0
-1:	addu.b	[$r1+], $r0
-	subq	1, $r2
-	bne	1b
+	moveq   CONFIG_ETRAX_FLASH1_SIZE, $r6
+
+	;; If the first physical flash memory is exceeded wrap to the second one.
+	btstq	26, $r1		; Are we addressing first flash?
+	bpl	1f
+	nop
+	clear.d	$r6
+
+1:	test.d  $r6		; 0 = no wrapping
+	beq	2f
+	nop
+	lslq	20, $r6		; Convert MB to bytes
+	sub.d	$r1, $r6
+
+2:	addu.b	[$r1+], $r0
+	subq	1, $r6		; Flash memory left
+	beq	3f
+	subq	1, $r2		; Length left
+	bne	2b
 	nop
 	ret
 	nop
+
+3:	move.d	MEM_CSE1_START, $r1 ; wrap to second flash
+	ba	2b
+	nop
diff --git a/arch/cris/arch-v10/drivers/Kconfig b/arch/cris/arch-v10/drivers/Kconfig
index 748374f25b8..8b50e840295 100644
--- a/arch/cris/arch-v10/drivers/Kconfig
+++ b/arch/cris/arch-v10/drivers/Kconfig
@@ -1,17 +1,11 @@
 config ETRAX_ETHERNET
 	bool "Ethernet support"
 	depends on ETRAX_ARCH_V10
+	select NET_ETHERNET
 	help
 	  This option enables the ETRAX 100LX built-in 10/100Mbit Ethernet
 	  controller.
 
-# this is just so that the user does not have to go into the
-# normal ethernet driver section just to enable ethernetworking
-config NET_ETHERNET
-	bool
-	depends on ETRAX_ETHERNET
-	default y
-
 choice
 	prompt "Network LED behavior"
 	depends on ETRAX_ETHERNET
@@ -20,26 +14,26 @@ choice
 config ETRAX_NETWORK_LED_ON_WHEN_LINK
 	bool "LED_on_when_link"
 	help
-	  Selecting LED_on_when_link will light the LED when there is a 
-	  connection and will flash off when there is activity. 
+	  Selecting LED_on_when_link will light the LED when there is a
+	  connection and will flash off when there is activity.
 
-	  Selecting LED_on_when_activity will light the LED only when 
+	  Selecting LED_on_when_activity will light the LED only when
 	  there is activity.
 
-	  This setting will also affect the behaviour of other activity LEDs 
-	  e.g. Bluetooth. 
+	  This setting will also affect the behaviour of other activity LEDs
+	  e.g. Bluetooth.
 
 config ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
 	bool "LED_on_when_activity"
 	help
-	  Selecting LED_on_when_link will light the LED when there is a 
-	  connection and will flash off when there is activity. 
+	  Selecting LED_on_when_link will light the LED when there is a
+	  connection and will flash off when there is activity.
 
-	  Selecting LED_on_when_activity will light the LED only when 
+	  Selecting LED_on_when_activity will light the LED only when
 	  there is activity.
 
-	  This setting will also affect the behaviour of other activity LEDs 
-	  e.g. Bluetooth. 
+	  This setting will also affect the behaviour of other activity LEDs
+	  e.g. Bluetooth.
 
 endchoice
 
@@ -91,11 +85,11 @@ choice
 	depends on ETRAX_SERIAL_PORT0
 	default ETRAX_SERIAL_PORT0_DMA6_OUT
 
-config CONFIG_ETRAX_SERIAL_PORT0_NO_DMA_OUT
-       bool "No DMA out"
+config ETRAX_SERIAL_PORT0_NO_DMA_OUT
+	bool "No DMA out"
 
-config CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT
-       bool "DMA 6"
+config ETRAX_SERIAL_PORT0_DMA6_OUT
+	bool "DMA 6"
 
 endchoice
 
@@ -104,11 +98,11 @@ choice
 	depends on ETRAX_SERIAL_PORT0
 	default ETRAX_SERIAL_PORT0_DMA7_IN
 
-config CONFIG_ETRAX_SERIAL_PORT0_NO_DMA_IN
-       bool "No DMA in"
+config ETRAX_SERIAL_PORT0_NO_DMA_IN
+	bool "No DMA in"
 
-config CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN
-       bool "DMA 7"
+config ETRAX_SERIAL_PORT0_DMA7_IN
+	bool "DMA 7"
 
 endchoice
 
@@ -205,11 +199,11 @@ choice
 	depends on ETRAX_SERIAL_PORT1
 	default ETRAX_SERIAL_PORT1_DMA8_OUT
 
-config CONFIG_ETRAX_SERIAL_PORT1_NO_DMA_OUT
-       bool "No DMA out"
+config ETRAX_SERIAL_PORT1_NO_DMA_OUT
+	bool "No DMA out"
 
-config CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT
-       bool "DMA 8"
+config ETRAX_SERIAL_PORT1_DMA8_OUT
+	bool "DMA 8"
 
 endchoice
 
@@ -218,11 +212,11 @@ choice
 	depends on ETRAX_SERIAL_PORT1
 	default ETRAX_SERIAL_PORT1_DMA9_IN
 
-config CONFIG_ETRAX_SERIAL_PORT1_NO_DMA_IN
-       bool "No DMA in"
+config ETRAX_SERIAL_PORT1_NO_DMA_IN
+	bool "No DMA in"
 
-config CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN
-       bool "DMA 9"
+config ETRAX_SERIAL_PORT1_DMA9_IN
+	bool "DMA 9"
 
 endchoice
 
@@ -308,7 +302,7 @@ config ETRAX_SER1_CD_ON_PB_BIT
 	  Specify the pin of the PB port to carry the CD signal for serial
 	  port 1.
 
-comment "Make sure you dont have the same PB bits more than once!"
+comment "Make sure you do not have the same PB bits more than once!"
 	depends on ETRAX_SERIAL && ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && ETRAX_SER1_DTR_RI_DSR_CD_ON_PB
 
 config ETRAX_SERIAL_PORT2
@@ -322,11 +316,11 @@ choice
 	depends on ETRAX_SERIAL_PORT2
 	default ETRAX_SERIAL_PORT2_DMA2_OUT
 
-config CONFIG_ETRAX_SERIAL_PORT2_NO_DMA_OUT
-       bool "No DMA out"
+config ETRAX_SERIAL_PORT2_NO_DMA_OUT
+	bool "No DMA out"
 
-config CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT
-       bool "DMA 2"
+config ETRAX_SERIAL_PORT2_DMA2_OUT
+	bool "DMA 2"
 
 endchoice
 
@@ -335,11 +329,11 @@ choice
 	depends on ETRAX_SERIAL_PORT2
 	default ETRAX_SERIAL_PORT2_DMA3_IN
 
-config CONFIG_ETRAX_SERIAL_PORT2_NO_DMA_IN
-       bool "No DMA in"
+config ETRAX_SERIAL_PORT2_NO_DMA_IN
+	bool "No DMA in"
 
-config CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN
-       bool "DMA 3"
+config ETRAX_SERIAL_PORT2_DMA3_IN
+	bool "DMA 3"
 
 endchoice
 
@@ -436,11 +430,11 @@ choice
 	depends on ETRAX_SERIAL_PORT3
 	default ETRAX_SERIAL_PORT3_DMA4_OUT
 
-config CONFIG_ETRAX_SERIAL_PORT3_NO_DMA_OUT
-       bool "No DMA out"
+config ETRAX_SERIAL_PORT3_NO_DMA_OUT
+	bool "No DMA out"
 
-config CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT
-       bool "DMA 4"
+config ETRAX_SERIAL_PORT3_DMA4_OUT
+	bool "DMA 4"
 
 endchoice
 
@@ -449,11 +443,11 @@ choice
 	depends on ETRAX_SERIAL_PORT3
 	default ETRAX_SERIAL_PORT3_DMA5_IN
 
-config CONFIG_ETRAX_SERIAL_PORT3_NO_DMA_IN
-       bool "No DMA in"
+config ETRAX_SERIAL_PORT3_NO_DMA_IN
+	bool "No DMA in"
 
-config CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN
-       bool "DMA 5"
+config ETRAX_SERIAL_PORT3_DMA5_IN
+	bool "DMA 5"
 
 endchoice
 
@@ -554,7 +548,6 @@ config ETRAX_IDE
 	select BLK_DEV_IDEDISK
 	select BLK_DEV_IDECD
 	select BLK_DEV_IDEDMA
-	select DMA_NONPCI
 	help
 	  Enable this to get support for ATA/IDE.
 	  You can't use paralell ports or SCSI ports
@@ -579,7 +572,7 @@ config ETRAX_IDE_PB7_RESET
 	  IDE reset on pin 7 on port B
 
 config ETRAX_IDE_G27_RESET
-        bool "Port_G_Bit_27"
+	bool "Port_G_Bit_27"
 	help
 	  IDE reset on pin 27 on port G
 
@@ -588,30 +581,36 @@ endchoice
 
 config ETRAX_USB_HOST
 	bool "USB host"
+	select USB
 	help
 	   This option enables the host functionality of the ETRAX 100LX
 	   built-in USB controller. In host mode the controller is designed
 	   for CTRL and BULK traffic only, INTR traffic may work as well
 	   however (depending on the requirements of timeliness).
 
-config USB
-       tristate
-       depends on ETRAX_USB_HOST
-       default y
-
 config ETRAX_USB_HOST_PORT1
-       bool "  USB port 1 enabled"
-       depends on ETRAX_USB_HOST
-       default n
+	bool "USB port 1 enabled"
+	depends on ETRAX_USB_HOST
+	default n
 
 config ETRAX_USB_HOST_PORT2
-       bool "  USB port 2 enabled"
-       depends on ETRAX_USB_HOST
-       default n
+	bool "USB port 2 enabled"
+	depends on ETRAX_USB_HOST
+	default n
 
 config ETRAX_AXISFLASHMAP
 	bool "Axis flash-map support"
 	depends on ETRAX_ARCH_V10
+	select MTD
+	select MTD_CFI
+	select MTD_CFI_AMDSTD
+	select MTD_OBSOLETE_CHIPS
+	select MTD_AMDSTD
+	select MTD_CHAR
+	select MTD_BLOCK
+	select MTD_PARTITIONS
+	select MTD_CONCAT
+	select MTD_COMPLEX_MAPPINGS
 	help
 	  This option enables MTD mapping of flash devices.  Needed to use
 	  flash memories.  If unsure, say Y.
@@ -627,119 +626,6 @@ config ETRAX_PTABLE_SECTOR
 	  for changing this is when the flash block size is bigger
 	  than 64kB (e.g. when using two parallel 16 bit flashes).
 
-# here we define the CONFIG_'s necessary to enable MTD support
-# for the flash
-config MTD
-	tristate
-	depends on ETRAX_AXISFLASHMAP
-	default y
-	help
-	  Memory Technology Devices are flash, RAM and similar chips, often
-	  used for solid state file systems on embedded devices. This option
-	  will provide the generic support for MTD drivers to register
-	  themselves with the kernel and for potential users of MTD devices
-	  to enumerate the devices which are present and obtain a handle on
-	  them. It will also allow you to select individual drivers for 
-	  particular hardware and users of MTD devices. If unsure, say N.
-
-config MTD_CFI
-	tristate
-	depends on ETRAX_AXISFLASHMAP
-	default y
-	help
-	  The Common Flash Interface specification was developed by Intel,
-	  AMD and other flash manufactures that provides a universal method
-	  for probing the capabilities of flash devices. If you wish to
-	  support any device that is CFI-compliant, you need to enable this
-	  option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
-	  for more information on CFI.
-
-config MTD_CFI_AMDSTD
-	tristate
-	depends on ETRAX_AXISFLASHMAP
-	default y
-	help
-	  The Common Flash Interface defines a number of different command
-	  sets which a CFI-compliant chip may claim to implement. This code
-	  provides support for one of those command sets, used on chips 
-	  chips including the AMD Am29LV320.
-
-config MTD_OBSOLETE_CHIPS
-	bool
-	depends on ETRAX_AXISFLASHMAP
-	default y
-	help
-	  This option does not enable any code directly, but will allow you to
-	  select some other chip drivers which are now considered obsolete,
-	  because the generic CONFIG_JEDEC_PROBE code above should now detect
-	  the chips which are supported by these drivers, and allow the generic
-	  CFI-compatible drivers to drive the chips. Say 'N' here unless you have
-	  already tried the CONFIG_JEDEC_PROBE method and reported its failure
-	  to the MTD mailing list at <linux-mtd@lists.infradead.org>
-
-config MTD_AMDSTD
-	tristate
-	depends on ETRAX_AXISFLASHMAP
-	default y
-	help
-	  This option enables support for flash chips using AMD-compatible
-	  commands, including some which are not CFI-compatible and hence 
-	  cannot be used with the CONFIG_MTD_CFI_AMDSTD option.
-
-	  It also works on AMD compatible chips that do conform to CFI.
-
-config MTD_CHAR
-	tristate
-	depends on ETRAX_AXISFLASHMAP
-	default y
-	help
-	  This provides a character device for each MTD device present in
-	  the system, allowing the user to read and write directly to the
-	  memory chips, and also use ioctl() to obtain information about
-	  the device, or to erase parts of it.
-
-config MTD_BLOCK
-	tristate
-	depends on ETRAX_AXISFLASHMAP
-	default y
-	---help---
-	  Although most flash chips have an erase size too large to be useful
-	  as block devices, it is possible to use MTD devices which are based
-	  on RAM chips in this manner. This block device is a user of MTD
-	  devices performing that function.
-
-	  At the moment, it is also required for the Journalling Flash File
-	  System(s) to obtain a handle on the MTD device when it's mounted
-	  (although JFFS and JFFS2 don't actually use any of the functionality
-	  of the mtdblock device).
-
-	  Later, it may be extended to perform read/erase/modify/write cycles
-	  on flash chips to emulate a smaller block size. Needless to say,
-	  this is very unsafe, but could be useful for file systems which are
-	  almost never written to.
-
-	  You do not need this option for use with the DiskOnChip devices. For
-	  those, enable NFTL support (CONFIG_NFTL) instead.
-
-config MTD_PARTITIONS
-	tristate
-	depends on ETRAX_AXISFLASHMAP
-	default y
-	help
-	  If you have a device which needs to divide its flash chip(s) up
-	  into multiple 'partitions', each of which appears to the user as
-	  a separate MTD device, you require this option to be enabled. If
-	  unsure, say 'Y'.
-
-	  Note, however, that you don't need this option for the DiskOnChip
-	  devices. Partitioning on NFTL 'devices' is a different - that's the
-	  'normal' form of partitioning used on a block device.
-
-config MTD_CONCAT
-	tristate
-	depends on ETRAX_AXISFLASHMAP
-	default y
-
 config ETRAX_I2C
 	bool "I2C support"
 	depends on ETRAX_ARCH_V10
@@ -752,7 +638,7 @@ config ETRAX_I2C
 	  val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg);
 
 # this is true for most products since PB-I2C seems to be somewhat
-# flawed.. 
+# flawed..
 config ETRAX_I2C_USES_PB_NOT_PB_I2C
 	bool "I2C uses PB not PB-I2C"
 	depends on ETRAX_I2C
@@ -886,7 +772,7 @@ config ETRAX_RTC
 	bool "Real Time Clock support"
 	depends on ETRAX_ARCH_V10
 	help
-	  Enables drivers for the Real-Time Clock battery-backed chips on 
+	  Enables drivers for the Real-Time Clock battery-backed chips on
 	  some products. The kernel reads the time when booting, and
 	  the date can be set using ioctl(fd, RTC_SET_TIME, &rt) with rt a
 	  rtc_time struct (see <file:include/asm-cris/rtc.h>) on the /dev/rtc
@@ -903,13 +789,13 @@ config ETRAX_DS1302
 	bool "DS1302"
 	help
 	  Enables the driver for the DS1302 Real-Time Clock battery-backed
-	  chip on some products. 
+	  chip on some products.
 
 config ETRAX_PCF8563
 	bool "PCF8563"
 	help
 	  Enables the driver for the PCF8563 Real-Time Clock battery-backed
-	  chip on some products.  
+	  chip on some products.
 
 endchoice
 
@@ -954,10 +840,8 @@ config ETRAX_DS1302_TRICKLE_CHARGE
 	help
 	  This controls the initial value of the trickle charge register.
 	  0 = disabled (use this if you are unsure or have a non rechargable battery)
-	  Otherwise the following values can be OR:ed together to control the 
+	  Otherwise the following values can be OR:ed together to control the
 	  charge current:
 	  1 = 2kohm, 2 = 4kohm, 3 = 4kohm
 	  4 = 1 diode, 8 = 2 diodes
 	  Allowed values are (increasing current): 0, 11, 10, 9, 7, 6, 5
-
-
diff --git a/arch/cris/arch-v10/drivers/axisflashmap.c b/arch/cris/arch-v10/drivers/axisflashmap.c
index fb7d4855ea6..11ab3836aac 100644
--- a/arch/cris/arch-v10/drivers/axisflashmap.c
+++ b/arch/cris/arch-v10/drivers/axisflashmap.c
@@ -11,6 +11,9 @@
  * partition split defined below.
  *
  * $Log: axisflashmap.c,v $
+ * Revision 1.11  2004/11/15 10:27:14  starvik
+ * Corrected typo (Thanks to Milton Miller <miltonm@bga.com>).
+ *
  * Revision 1.10  2004/08/16 12:37:22  starvik
  * Merge of Linux 2.6.8
  *
@@ -161,7 +164,7 @@
 #elif CONFIG_ETRAX_FLASH_BUSWIDTH==2
 #define flash_data __u16
 #elif CONFIG_ETRAX_FLASH_BUSWIDTH==4
-#define flash_data __u16
+#define flash_data __u32
 #endif
 
 /* From head.S */
diff --git a/arch/cris/arch-v10/drivers/ds1302.c b/arch/cris/arch-v10/drivers/ds1302.c
index fba530fcfae..10795f67f68 100644
--- a/arch/cris/arch-v10/drivers/ds1302.c
+++ b/arch/cris/arch-v10/drivers/ds1302.c
@@ -7,6 +7,15 @@
 *! Functions exported: ds1302_readreg, ds1302_writereg, ds1302_init
 *!
 *! $Log: ds1302.c,v $
+*! Revision 1.18  2005/01/24 09:11:26  mikaelam
+*! Minor changes to get DS1302 RTC chip driver to work
+*!
+*! Revision 1.17  2005/01/05 06:11:22  starvik
+*! No need to do local_irq_disable after local_irq_save.
+*!
+*! Revision 1.16  2004/12/13 12:21:52  starvik
+*! Added I/O and DMA allocators from Linux 2.4
+*!
 *! Revision 1.14  2004/08/24 06:48:43  starvik
 *! Whitespace cleanup
 *!
@@ -124,9 +133,9 @@
 *!
 *! ---------------------------------------------------------------------------
 *!
-*! (C) Copyright 1999, 2000, 2001  Axis Communications AB, LUND, SWEDEN
+*! (C) Copyright 1999, 2000, 2001, 2002, 2003, 2004  Axis Communications AB, LUND, SWEDEN
 *!
-*! $Id: ds1302.c,v 1.14 2004/08/24 06:48:43 starvik Exp $
+*! $Id: ds1302.c,v 1.18 2005/01/24 09:11:26 mikaelam Exp $
 *!
 *!***************************************************************************/
 
@@ -145,6 +154,7 @@
 #include <asm/arch/svinto.h>
 #include <asm/io.h>
 #include <asm/rtc.h>
+#include <asm/arch/io_interface_mux.h>
 
 #define RTC_MAJOR_NR 121 /* local major, change later */
 
@@ -320,7 +330,6 @@ get_rtc_time(struct rtc_time *rtc_tm)
 	unsigned long flags;
 
 	local_irq_save(flags);
-	local_irq_disable();
 
 	rtc_tm->tm_sec = CMOS_READ(RTC_SECONDS);
 	rtc_tm->tm_min = CMOS_READ(RTC_MINUTES);
@@ -358,7 +367,7 @@ static int
 rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
 	  unsigned long arg) 
 {
-        unsigned long flags;
+	unsigned long flags;
 
 	switch(cmd) {
 		case RTC_RD_TIME:	/* read the time/date from RTC	*/
@@ -382,7 +391,7 @@ rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
 				return -EPERM;
 
 			if (copy_from_user(&rtc_tm, (struct rtc_time*)arg, sizeof(struct rtc_time)))
-				return -EFAULT;    	
+				return -EFAULT;
 
 			yrs = rtc_tm.tm_year + 1900;
 			mon = rtc_tm.tm_mon + 1;   /* tm_mon starts at zero */
@@ -419,7 +428,6 @@ rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
 			BIN_TO_BCD(yrs);
 
 			local_irq_save(flags);
-			local_irq_disable();
 			CMOS_WRITE(yrs, RTC_YEAR);
 			CMOS_WRITE(mon, RTC_MONTH);
 			CMOS_WRITE(day, RTC_DAY_OF_MONTH);
@@ -438,7 +446,7 @@ rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
 
 		case RTC_SET_CHARGE: /* set the RTC TRICKLE CHARGE register */
 		{
-			int tcs_val;                        
+			int tcs_val;
 
 			if (!capable(CAP_SYS_TIME))
 				return -EPERM;
@@ -492,8 +500,8 @@ print_rtc_status(void)
 /* The various file operations we support. */
 
 static struct file_operations rtc_fops = {
-        .owner          = THIS_MODULE,
-        .ioctl          = rtc_ioctl,	
+	.owner =	THIS_MODULE,
+	.ioctl =	rtc_ioctl,
 }; 
 
 /* Probe for the chip by writing something to its RAM and try reading it back. */
@@ -532,7 +540,7 @@ ds1302_probe(void)
 		       "PB",
 #endif
 		       CONFIG_ETRAX_DS1302_RSTBIT);
-                print_rtc_status();
+		       print_rtc_status();
 		retval = 1;
 	} else {
 		stop();
@@ -548,7 +556,9 @@ ds1302_probe(void)
 int __init
 ds1302_init(void) 
 {
+#ifdef CONFIG_ETRAX_I2C
 	i2c_init();
+#endif
 
 	if (!ds1302_probe()) {
 #ifdef CONFIG_ETRAX_DS1302_RST_ON_GENERIC_PORT
@@ -558,25 +568,42 @@ ds1302_init(void)
 		 *
 		 * Make sure that R_GEN_CONFIG is setup correct.
 		 */
-    		genconfig_shadow = ((genconfig_shadow &
-				     ~IO_MASK(R_GEN_CONFIG, ata)) | 
-				   (IO_STATE(R_GEN_CONFIG, ata, select)));    
-    		*R_GEN_CONFIG = genconfig_shadow;
+		/* Allocating the ATA interface will grab almost all
+		 * pins in I/O groups a, b, c and d.  A consequence of
+		 * allocating the ATA interface is that the fixed
+		 * interfaces shared RAM, parallel port 0, parallel
+		 * port 1, parallel port W, SCSI-8 port 0, SCSI-8 port
+		 * 1, SCSI-W, serial port 2, serial port 3,
+		 * synchronous serial port 3 and USB port 2 and almost
+		 * all GPIO pins on port g cannot be used.
+		 */
+		if (cris_request_io_interface(if_ata, "ds1302/ATA")) {
+			printk(KERN_WARNING "ds1302: Failed to get IO interface\n");
+			return -1;
+		}
+
 #elif CONFIG_ETRAX_DS1302_RSTBIT == 0
-		
-		/* Set the direction of this bit to out. */		
-    		genconfig_shadow = ((genconfig_shadow &
-				     ~IO_MASK(R_GEN_CONFIG, g0dir)) | 
-				   (IO_STATE(R_GEN_CONFIG, g0dir, out)));    
-    		*R_GEN_CONFIG = genconfig_shadow;
+		if (cris_io_interface_allocate_pins(if_gpio_grp_a,
+						    'g',
+						    CONFIG_ETRAX_DS1302_RSTBIT,
+						    CONFIG_ETRAX_DS1302_RSTBIT)) {
+			printk(KERN_WARNING "ds1302: Failed to get IO interface\n");
+			return -1;
+		}
+
+		/* Set the direction of this bit to out. */
+		genconfig_shadow = ((genconfig_shadow &
+ 				     ~IO_MASK(R_GEN_CONFIG, g0dir)) |
+ 				   (IO_STATE(R_GEN_CONFIG, g0dir, out)));
+		*R_GEN_CONFIG = genconfig_shadow;
 #endif
 		if (!ds1302_probe()) {
 			printk(KERN_WARNING "%s: RTC not found.\n", ds1302_name);
-      			return -1;
+			return -1;
 		}
 #else
 		printk(KERN_WARNING "%s: RTC not found.\n", ds1302_name);
-    		return -1;
+		return -1;
 #endif
   	}
 	/* Initialise trickle charger */
diff --git a/arch/cris/arch-v10/drivers/eeprom.c b/arch/cris/arch-v10/drivers/eeprom.c
index 316ca15d680..512f16dec06 100644
--- a/arch/cris/arch-v10/drivers/eeprom.c
+++ b/arch/cris/arch-v10/drivers/eeprom.c
@@ -20,6 +20,12 @@
 *!                                  in the spin-lock.
 *!
 *!  $Log: eeprom.c,v $
+*!  Revision 1.12  2005/06/19 17:06:46  starvik
+*!  Merge of Linux 2.6.12.
+*!
+*!  Revision 1.11  2005/01/26 07:14:46  starvik
+*!  Applied diff from kernel janitors (Nish Aravamudan).
+*!
 *!  Revision 1.10  2003/09/11 07:29:48  starvik
 *!  Merge of Linux 2.6.0-test5
 *!
@@ -94,6 +100,7 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
+#include <linux/wait.h>
 #include <asm/uaccess.h>
 #include "i2c.h"
 
@@ -526,15 +533,10 @@ static ssize_t eeprom_read(struct file * file, char * buf, size_t count, loff_t
     return -EFAULT;
   }
   
-  while(eeprom.busy)
-  {
-    interruptible_sleep_on(&eeprom.wait_q);
+  wait_event_interruptible(eeprom.wait_q, !eeprom.busy);
+  if (signal_pending(current))
+    return -EINTR;
 
-    /* bail out if we get interrupted */
-    if (signal_pending(current))
-      return -EINTR;
-    
-  }
   eeprom.busy++;
 
   page = (unsigned char) (p >> 8);
@@ -604,13 +606,10 @@ static ssize_t eeprom_write(struct file * file, const char * buf, size_t count,
     return -EFAULT;
   }
 
-  while(eeprom.busy)
-  {
-    interruptible_sleep_on(&eeprom.wait_q);
-    /* bail out if we get interrupted */
-    if (signal_pending(current))
-      return -EINTR;
-  }
+  wait_event_interruptible(eeprom.wait_q, !eeprom.busy);
+  /* bail out if we get interrupted */
+  if (signal_pending(current))
+    return -EINTR;
   eeprom.busy++;
   for(i = 0; (i < EEPROM_RETRIES) && (restart > 0); i++)
   {
diff --git a/arch/cris/arch-v10/drivers/gpio.c b/arch/cris/arch-v10/drivers/gpio.c
index c095de82a0d..09963fe299a 100644
--- a/arch/cris/arch-v10/drivers/gpio.c
+++ b/arch/cris/arch-v10/drivers/gpio.c
@@ -1,4 +1,4 @@
-/* $Id: gpio.c,v 1.12 2004/08/24 07:19:59 starvik Exp $
+/* $Id: gpio.c,v 1.17 2005/06/19 17:06:46 starvik Exp $
  *
  * Etrax general port I/O device
  *
@@ -9,6 +9,18 @@
  *             Johan Adolfsson  (read/set directions, write, port G)
  *
  * $Log: gpio.c,v $
+ * Revision 1.17  2005/06/19 17:06:46  starvik
+ * Merge of Linux 2.6.12.
+ *
+ * Revision 1.16  2005/03/07 13:02:29  starvik
+ * Protect driver global states with spinlock
+ *
+ * Revision 1.15  2005/01/05 06:08:55  starvik
+ * No need to do local_irq_disable after local_irq_save.
+ *
+ * Revision 1.14  2004/12/13 12:21:52  starvik
+ * Added I/O and DMA allocators from Linux 2.4
+ *
  * Revision 1.12  2004/08/24 07:19:59  starvik
  * Whitespace cleanup
  *
@@ -142,6 +154,7 @@
 #include <asm/io.h>
 #include <asm/system.h>
 #include <asm/irq.h>
+#include <asm/arch/io_interface_mux.h>
 
 #define GPIO_MAJOR 120  /* experimental MAJOR number */
 
@@ -194,6 +207,8 @@ static struct gpio_private *alarmlist = 0;
 static int gpio_some_alarms = 0; /* Set if someone uses alarm */
 static unsigned long gpio_pa_irq_enabled_mask = 0;
 
+static DEFINE_SPINLOCK(gpio_lock); /* Protect directions etc */
+
 /* Port A and B use 8 bit access, but Port G is 32 bit */
 #define NUM_PORTS (GPIO_MINOR_B+1)
 
@@ -241,6 +256,9 @@ static volatile unsigned char *dir_shadow[NUM_PORTS] = {
 	&port_pb_dir_shadow 
 };
 
+/* All bits in port g that can change dir. */
+static const unsigned long int changeable_dir_g_mask = 0x01FFFF01;
+
 /* Port G is 32 bit, handle it special, some bits are both inputs 
    and outputs at the same time, only some of the bits can change direction
    and some of them in groups of 8 bit. */
@@ -260,6 +278,7 @@ gpio_poll(struct file *file,
 	unsigned int mask = 0;
 	struct gpio_private *priv = (struct gpio_private *)file->private_data;
 	unsigned long data;
+	spin_lock(&gpio_lock);
 	poll_wait(file, &priv->alarm_wq, wait);
 	if (priv->minor == GPIO_MINOR_A) {
 		unsigned long flags;
@@ -270,10 +289,10 @@ gpio_poll(struct file *file,
 		 */
 		tmp = ~data & priv->highalarm & 0xFF;
 		tmp = (tmp << R_IRQ_MASK1_SET__pa0__BITNR);
-		save_flags(flags); cli();
+		local_irq_save(flags);
 		gpio_pa_irq_enabled_mask |= tmp;
 		*R_IRQ_MASK1_SET = tmp;
-		restore_flags(flags);
+		local_irq_restore(flags);
 
 	} else if (priv->minor == GPIO_MINOR_B)
 		data = *R_PORT_PB_DATA;
@@ -286,8 +305,11 @@ gpio_poll(struct file *file,
 	    (~data & priv->lowalarm)) {
 		mask = POLLIN|POLLRDNORM;
 	}
+
+	spin_unlock(&gpio_lock);
 	
 	DP(printk("gpio_poll ready: mask 0x%08X\n", mask));
+
 	return mask;
 }
 
@@ -296,6 +318,7 @@ int etrax_gpio_wake_up_check(void)
 	struct gpio_private *priv = alarmlist;
 	unsigned long data = 0;
         int ret = 0;
+	spin_lock(&gpio_lock);
 	while (priv) {
 		if (USE_PORTS(priv)) {
 			data = *priv->port;
@@ -310,6 +333,7 @@ int etrax_gpio_wake_up_check(void)
 		}
 		priv = priv->next;
 	}
+	spin_unlock(&gpio_lock);
         return ret;
 }
 
@@ -327,6 +351,7 @@ static irqreturn_t
 gpio_pa_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 {
 	unsigned long tmp;
+	spin_lock(&gpio_lock);
 	/* Find what PA interrupts are active */
 	tmp = (*R_IRQ_READ1);
 
@@ -337,6 +362,8 @@ gpio_pa_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 	*R_IRQ_MASK1_CLR = tmp;
 	gpio_pa_irq_enabled_mask &= ~tmp;
 
+	spin_unlock(&gpio_lock);
+
 	if (gpio_some_alarms) {
 		return IRQ_RETVAL(etrax_gpio_wake_up_check());
 	}
@@ -350,6 +377,9 @@ static ssize_t gpio_write(struct file * file, const char * buf, size_t count,
 	struct gpio_private *priv = (struct gpio_private *)file->private_data;
 	unsigned char data, clk_mask, data_mask, write_msb;
 	unsigned long flags;
+
+	spin_lock(&gpio_lock);
+
 	ssize_t retval = count;
 	if (priv->minor !=GPIO_MINOR_A && priv->minor != GPIO_MINOR_B) {
 		return -EFAULT;
@@ -372,7 +402,7 @@ static ssize_t gpio_write(struct file * file, const char * buf, size_t count,
 		data = *buf++;
 		if (priv->write_msb) {
 			for (i = 7; i >= 0;i--) {
-				local_irq_save(flags); local_irq_disable();
+				local_irq_save(flags);
 				*priv->port = *priv->shadow &= ~clk_mask;
 				if (data & 1<<i)
 					*priv->port = *priv->shadow |= data_mask;
@@ -384,7 +414,7 @@ static ssize_t gpio_write(struct file * file, const char * buf, size_t count,
 			}
 		} else {
 			for (i = 0; i <= 7;i++) {
-				local_irq_save(flags); local_irq_disable();
+				local_irq_save(flags);
 				*priv->port = *priv->shadow &= ~clk_mask;
 				if (data & 1<<i)
 					*priv->port = *priv->shadow |= data_mask;
@@ -396,6 +426,7 @@ static ssize_t gpio_write(struct file * file, const char * buf, size_t count,
 			}
 		}
 	}
+	spin_unlock(&gpio_lock);
 	return retval;
 }
 
@@ -452,9 +483,14 @@ gpio_open(struct inode *inode, struct file *filp)
 static int
 gpio_release(struct inode *inode, struct file *filp)
 {
-	struct gpio_private *p = alarmlist;
-	struct gpio_private *todel = (struct gpio_private *)filp->private_data;
-	
+	struct gpio_private *p;
+	struct gpio_private *todel;
+
+	spin_lock(&gpio_lock);
+
+        p = alarmlist;
+        todel = (struct gpio_private *)filp->private_data;
+
 	/* unlink from alarmlist and free the private structure */
 
 	if (p == todel) {
@@ -476,7 +512,7 @@ gpio_release(struct inode *inode, struct file *filp)
 		p = p->next;
 	}
 	gpio_some_alarms = 0;
-		
+	spin_unlock(&gpio_lock);
 	return 0;
 }
 
@@ -491,14 +527,14 @@ unsigned long inline setget_input(struct gpio_private *priv, unsigned long arg)
 	 */
 	unsigned long flags;
 	if (USE_PORTS(priv)) {
-		local_irq_save(flags); local_irq_disable();
+		local_irq_save(flags);
 		*priv->dir = *priv->dir_shadow &= 
 		~((unsigned char)arg & priv->changeable_dir);
 		local_irq_restore(flags);
 		return ~(*priv->dir_shadow) & 0xFF; /* Only 8 bits */
 	} else if (priv->minor == GPIO_MINOR_G) {
 		/* We must fiddle with R_GEN_CONFIG to change dir */
-		save_flags(flags); cli();
+		local_irq_save(flags);
 		if (((arg & dir_g_in_bits) != arg) && 
 		    (arg & changeable_dir_g)) {
 			arg &= changeable_dir_g;
@@ -533,7 +569,7 @@ unsigned long inline setget_input(struct gpio_private *priv, unsigned long arg)
 			/* Must be a >120 ns delay before writing this again */
 				
 		}
-		restore_flags(flags);
+		local_irq_restore(flags);
 		return dir_g_in_bits;
 	}
 	return 0;
@@ -543,14 +579,14 @@ unsigned long inline setget_output(struct gpio_private *priv, unsigned long arg)
 {
 	unsigned long flags;
 	if (USE_PORTS(priv)) {
-		local_irq_save(flags); local_irq_disable();
+		local_irq_save(flags);
 		*priv->dir = *priv->dir_shadow |= 
 		  ((unsigned char)arg & priv->changeable_dir);
 		local_irq_restore(flags);
 		return *priv->dir_shadow;
 	} else if (priv->minor == GPIO_MINOR_G) {
 		/* We must fiddle with R_GEN_CONFIG to change dir */			
-		save_flags(flags); cli();
+		local_irq_save(flags);
 		if (((arg & dir_g_out_bits) != arg) &&
 		    (arg & changeable_dir_g)) {
 			/* Set bits in genconfig to set to output */
@@ -583,7 +619,7 @@ unsigned long inline setget_output(struct gpio_private *priv, unsigned long arg)
 			*R_GEN_CONFIG = genconfig_shadow;
 			/* Must be a >120 ns delay before writing this again */
 		}
-		restore_flags(flags);
+		local_irq_restore(flags);
 		return dir_g_out_bits & 0x7FFFFFFF;
 	}
 	return 0;
@@ -598,22 +634,26 @@ gpio_ioctl(struct inode *inode, struct file *file,
 {
 	unsigned long flags;
 	unsigned long val;
+        int ret = 0;
+
 	struct gpio_private *priv = (struct gpio_private *)file->private_data;
 	if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE) {
 		return -EINVAL;
 	}
 
+	spin_lock(&gpio_lock);
+
 	switch (_IOC_NR(cmd)) {
 	case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
 		// read the port
 		if (USE_PORTS(priv)) {
-			return *priv->port;
+			ret =  *priv->port;
 		} else if (priv->minor == GPIO_MINOR_G) {
-			return (*R_PORT_G_DATA) & 0x7FFFFFFF;
+			ret =  (*R_PORT_G_DATA) & 0x7FFFFFFF;
 		}
 		break;
 	case IO_SETBITS:
-		local_irq_save(flags); local_irq_disable();
+		local_irq_save(flags);
 		// set changeable bits with a 1 in arg
 		if (USE_PORTS(priv)) {
 			*priv->port = *priv->shadow |= 
@@ -624,7 +664,7 @@ gpio_ioctl(struct inode *inode, struct file *file,
 		local_irq_restore(flags);
 		break;
 	case IO_CLRBITS:
-		local_irq_save(flags); local_irq_disable();
+		local_irq_save(flags);
 		// clear changeable bits with a 1 in arg
 		if (USE_PORTS(priv)) {
 			*priv->port = *priv->shadow &= 
@@ -666,33 +706,34 @@ gpio_ioctl(struct inode *inode, struct file *file,
 	case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
 		/* Read direction 0=input 1=output */
 		if (USE_PORTS(priv)) {
-			return *priv->dir_shadow;
+			ret = *priv->dir_shadow;
 		} else if (priv->minor == GPIO_MINOR_G) {
 			/* Note: Some bits are both in and out,
 			 * Those that are dual is set here as well.
 			 */
-			return (dir_g_shadow | dir_g_out_bits) & 0x7FFFFFFF;
+			ret = (dir_g_shadow | dir_g_out_bits) & 0x7FFFFFFF;
 		}
+		break;
 	case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
 		/* Set direction 0=unchanged 1=input, 
 		 * return mask with 1=input 
 		 */
-		return setget_input(priv, arg) & 0x7FFFFFFF;
+		ret = setget_input(priv, arg) & 0x7FFFFFFF;
 		break;
 	case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
 		/* Set direction 0=unchanged 1=output, 
 		 * return mask with 1=output 
 		 */
-		return setget_output(priv, arg) & 0x7FFFFFFF;
-
+		ret =  setget_output(priv, arg) & 0x7FFFFFFF;
+		break;
 	case IO_SHUTDOWN:
 		SOFT_SHUTDOWN();
 		break;
 	case IO_GET_PWR_BT:
 #if defined (CONFIG_ETRAX_SOFT_SHUTDOWN)
-		return (*R_PORT_G_DATA & ( 1 << CONFIG_ETRAX_POWERBUTTON_BIT));
+		ret = (*R_PORT_G_DATA & ( 1 << CONFIG_ETRAX_POWERBUTTON_BIT));
 #else
-		return 0;
+		ret = 0;
 #endif
 		break;
 	case IO_CFG_WRITE_MODE:
@@ -709,7 +750,7 @@ gpio_ioctl(struct inode *inode, struct file *file,
 		{
 			priv->clk_mask = 0;
 			priv->data_mask = 0;
-			return -EPERM;
+			ret = -EPERM;
 		}
 		break;
 	case IO_READ_INBITS: 
@@ -720,8 +761,7 @@ gpio_ioctl(struct inode *inode, struct file *file,
 			val = *R_PORT_G_DATA;
 		}
 		if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
-			return -EFAULT;
-		return 0;
+			ret = -EFAULT;
 		break;
 	case IO_READ_OUTBITS:
 		 /* *arg is result of reading the output shadow */
@@ -731,36 +771,43 @@ gpio_ioctl(struct inode *inode, struct file *file,
 			val = port_g_data_shadow;
 		}
 		if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
-			return -EFAULT;
+			ret = -EFAULT;
 		break;
 	case IO_SETGET_INPUT: 
 		/* bits set in *arg is set to input,
 		 * *arg updated with current input pins.
 		 */
 		if (copy_from_user(&val, (unsigned long*)arg, sizeof(val)))
-			return -EFAULT;
+		{
+			ret = -EFAULT;
+			break;
+		}
 		val = setget_input(priv, val);
 		if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
-			return -EFAULT;
+			ret = -EFAULT;
 		break;
 	case IO_SETGET_OUTPUT:
 		/* bits set in *arg is set to output,
 		 * *arg updated with current output pins.
 		 */
 		if (copy_from_user(&val, (unsigned long*)arg, sizeof(val)))
-			return -EFAULT;
+		{
+			ret = -EFAULT;
+			break;
+		}
 		val = setget_output(priv, val);
 		if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
-			return -EFAULT;
+			ret = -EFAULT;
 		break;
 	default:
 		if (priv->minor == GPIO_MINOR_LEDS)
-			return gpio_leds_ioctl(cmd, arg);
+			ret = gpio_leds_ioctl(cmd, arg);
 		else
-			return -EINVAL;
+			ret = -EINVAL;
 	} /* switch */
-	
-	return 0;
+
+	spin_unlock(&gpio_lock);
+	return ret;
 }
 
 static int
@@ -802,60 +849,20 @@ struct file_operations gpio_fops = {
 };
 
 
-static void __init gpio_init_port_g(void)
+void ioif_watcher(const unsigned int gpio_in_available,
+		  const unsigned int gpio_out_available,
+		  const unsigned char pa_available,
+		  const unsigned char pb_available)
 {
-#define GROUPA (0x0000FF3F)
-#define GROUPB (1<<6 | 1<<7)
-#define GROUPC (1<<30 | 1<<31)
-#define GROUPD (0x3FFF0000)
-#define GROUPD_LOW (0x00FF0000)
-	unsigned long used_in_bits = 0;
-	unsigned long used_out_bits = 0;
-	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, scsi0, select)){
-		used_in_bits  |= GROUPA | GROUPB | 0 | 0;
-		used_out_bits |= GROUPA | GROUPB | 0 | 0;
-	}
-	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, ata, select)) {
-		used_in_bits  |= GROUPA | GROUPB | GROUPC | (GROUPD & ~(1<<25|1<<26));
-		used_out_bits |= GROUPA | GROUPB | GROUPC | GROUPD;
-	}
+	unsigned long int flags;
+	D(printk("gpio.c: ioif_watcher called\n"));
+	D(printk("gpio.c: G in: 0x%08x G out: 0x%08x PA: 0x%02x PB: 0x%02x\n",
+		 gpio_in_available, gpio_out_available, pa_available, pb_available));
 
-	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, par0, select)) {
-		used_in_bits  |= (GROUPA & ~(1<<0)) | 0 | 0 | 0;
-		used_out_bits |= (GROUPA & ~(1<<0)) | 0 | 0 | 0;
-	}
-	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, ser2, select)) {
-		used_in_bits  |= 0 | GROUPB | 0 | 0;
-		used_out_bits |= 0 | GROUPB | 0 | 0;
-	}
-	/* mio same as shared RAM ? */
-	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, mio, select)) {
-		used_in_bits  |= (GROUPA & ~(1<<0)) | 0 |0 |GROUPD_LOW;
-		used_out_bits |= (GROUPA & ~(1<<0|1<<1|1<<2)) | 0 |0 |GROUPD_LOW;
-	}
-	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, scsi1, select)) {
-		used_in_bits  |= 0 | 0 | GROUPC | GROUPD;
-		used_out_bits |= 0 | 0 | GROUPC | GROUPD;
-	}
-	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, scsi0w, select)) {
-		used_in_bits  |= GROUPA | GROUPB | 0 | (GROUPD_LOW | 1<<24);
-		used_out_bits |= GROUPA | GROUPB | 0 | (GROUPD_LOW | 1<<24 | 1<<25|1<<26);
-	}
+	spin_lock_irqsave(&gpio_lock, flags);
 
-	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, par1, select)) {
-		used_in_bits  |= 0 | 0 | 0 | (GROUPD & ~(1<<24));
-		used_out_bits |= 0 | 0 | 0 | (GROUPD & ~(1<<24));
-	}
-	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, ser3, select)) {
-		used_in_bits  |= 0 | 0 | GROUPC | 0;
-		used_out_bits |= 0 | 0 | GROUPC | 0;
-	}
-	/* mio same as shared RAM-W? */
-	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, mio_w, select)) {
-		used_in_bits  |= (GROUPA & ~(1<<0)) | 0 | 0 |GROUPD_LOW;
-		used_out_bits |= (GROUPA & ~(1<<0|1<<1|1<<2)) | 0 | 0 |GROUPD_LOW;
-	}
-	/* TODO: USB p2, parw, sync ser3? */
+	dir_g_in_bits = gpio_in_available;
+	dir_g_out_bits = gpio_out_available;
 
 	/* Initialise the dir_g_shadow etc. depending on genconfig */
 	/* 0=input 1=output */
@@ -868,10 +875,7 @@ static void __init gpio_init_port_g(void)
 	if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g24dir, out))
 		dir_g_shadow |= (1 << 24);
 
-	dir_g_in_bits = ~used_in_bits;
-	dir_g_out_bits = ~used_out_bits;
-
-	changeable_dir_g = 0x01FFFF01; /* all that can change dir */
+	changeable_dir_g = changeable_dir_g_mask;
 	changeable_dir_g &= dir_g_out_bits;
 	changeable_dir_g &= dir_g_in_bits;
 	/* Correct the bits that can change direction */ 
@@ -880,6 +884,7 @@ static void __init gpio_init_port_g(void)
 	dir_g_in_bits &= ~changeable_dir_g;
 	dir_g_in_bits |= (~dir_g_shadow & changeable_dir_g);
 
+	spin_unlock_irqrestore(&gpio_lock, flags);
 
 	printk(KERN_INFO "GPIO port G: in_bits: 0x%08lX out_bits: 0x%08lX val: %08lX\n",
 	       dir_g_in_bits, dir_g_out_bits, (unsigned long)*R_PORT_G_DATA);
@@ -896,6 +901,7 @@ gpio_init(void)
 #if defined (CONFIG_ETRAX_CSP0_LEDS)
 	int i;
 #endif
+        printk("gpio init\n");
 
 	/* do the formalities */
 
@@ -919,8 +925,13 @@ gpio_init(void)
 #endif
 
 #endif
-	gpio_init_port_g();
-	printk(KERN_INFO "ETRAX 100LX GPIO driver v2.5, (c) 2001, 2002 Axis Communications AB\n");
+	/* The I/O interface allocation watcher will be called when
+	 * registering it. */
+	if (cris_io_interface_register_watcher(ioif_watcher)){
+		printk(KERN_WARNING "gpio_init: Failed to install IO if allocator watcher\n");
+	}
+
+	printk(KERN_INFO "ETRAX 100LX GPIO driver v2.5, (c) 2001, 2002, 2003, 2004 Axis Communications AB\n");
 	/* We call etrax_gpio_wake_up_check() from timer interrupt and
 	 * from cpu_idle() in kernel/process.c
 	 * The check in cpu_idle() reduces latency from ~15 ms to ~6 ms
diff --git a/arch/cris/arch-v10/drivers/i2c.c b/arch/cris/arch-v10/drivers/i2c.c
index 8bbe233ba7b..b38267d60d3 100644
--- a/arch/cris/arch-v10/drivers/i2c.c
+++ b/arch/cris/arch-v10/drivers/i2c.c
@@ -12,6 +12,15 @@
 *!                                 don't use PB_I2C if DS1302 uses same bits,
 *!                                 use PB.
 *! $Log: i2c.c,v $
+*! Revision 1.13  2005/03/07 13:13:07  starvik
+*! Added spinlocks to protect states etc
+*!
+*! Revision 1.12  2005/01/05 06:11:22  starvik
+*! No need to do local_irq_disable after local_irq_save.
+*!
+*! Revision 1.11  2004/12/13 12:21:52  starvik
+*! Added I/O and DMA allocators from Linux 2.4
+*!
 *! Revision 1.9  2004/08/24 06:49:14  starvik
 *! Whitespace cleanup
 *!
@@ -75,7 +84,7 @@
 *! (C) Copyright 1999-2002 Axis Communications AB, LUND, SWEDEN
 *!
 *!***************************************************************************/
-/* $Id: i2c.c,v 1.9 2004/08/24 06:49:14 starvik Exp $ */
+/* $Id: i2c.c,v 1.13 2005/03/07 13:13:07 starvik Exp $ */
 
 /****************** INCLUDE FILES SECTION ***********************************/
 
@@ -95,6 +104,7 @@
 #include <asm/arch/svinto.h>
 #include <asm/io.h>
 #include <asm/delay.h>
+#include <asm/arch/io_interface_mux.h>
 
 #include "i2c.h"
 
@@ -184,6 +194,7 @@ static const char i2c_name[] = "i2c";
 
 #define i2c_delay(usecs) udelay(usecs)
 
+static DEFINE_SPINLOCK(i2c_lock); /* Protect directions etc */
 
 /****************** FUNCTION DEFINITION SECTION *************************/
 
@@ -488,13 +499,14 @@ i2c_writereg(unsigned char theSlave, unsigned char theReg,
 	int error, cntr = 3;
 	unsigned long flags;
 
+	spin_lock(&i2c_lock);
+
 	do {
 		error = 0;
 		/*
 		 * we don't like to be interrupted
 		 */
 		local_irq_save(flags);
-		local_irq_disable();
 
 		i2c_start();
 		/*
@@ -538,6 +550,8 @@ i2c_writereg(unsigned char theSlave, unsigned char theReg,
 
 	i2c_delay(CLOCK_LOW_TIME);
 
+	spin_unlock(&i2c_lock);
+
 	return -error;
 }
 
@@ -555,13 +569,14 @@ i2c_readreg(unsigned char theSlave, unsigned char theReg)
 	int error, cntr = 3;
 	unsigned long flags;
 
+	spin_lock(&i2c_lock);
+
 	do {
 		error = 0;
 		/*
 		 * we don't like to be interrupted
 		 */
 		local_irq_save(flags);
-		local_irq_disable();
 		/*
 		 * generate start condition
 		 */
@@ -620,6 +635,8 @@ i2c_readreg(unsigned char theSlave, unsigned char theReg)
 		
 	} while(error && cntr--);
 
+	spin_unlock(&i2c_lock);
+
 	return b;
 }
 
@@ -686,15 +703,26 @@ static struct file_operations i2c_fops = {
 int __init
 i2c_init(void)
 {
+	static int res = 0;
+	static int first = 1;
+
+	if (!first) {
+		return res;
+	}
+
 	/* Setup and enable the Port B I2C interface */
 
 #ifndef CONFIG_ETRAX_I2C_USES_PB_NOT_PB_I2C
+	if ((res = cris_request_io_interface(if_i2c, "I2C"))) {
+		printk(KERN_CRIT "i2c_init: Failed to get IO interface\n");
+		return res;
+	}
+
 	*R_PORT_PB_I2C = port_pb_i2c_shadow |= 
 		IO_STATE(R_PORT_PB_I2C, i2c_en,  on) |
 		IO_FIELD(R_PORT_PB_I2C, i2c_d,   1)  |
 		IO_FIELD(R_PORT_PB_I2C, i2c_clk, 1)  |
 		IO_STATE(R_PORT_PB_I2C, i2c_oe_, enable);
-#endif
 
 	port_pb_dir_shadow &= ~IO_MASK(R_PORT_PB_DIR, dir0);
 	port_pb_dir_shadow &= ~IO_MASK(R_PORT_PB_DIR, dir1);
@@ -702,8 +730,26 @@ i2c_init(void)
 	*R_PORT_PB_DIR = (port_pb_dir_shadow |=
 			  IO_STATE(R_PORT_PB_DIR, dir0, input)  |
 			  IO_STATE(R_PORT_PB_DIR, dir1, output));
+#else
+        if ((res = cris_io_interface_allocate_pins(if_i2c,
+						   'b',
+                                                   CONFIG_ETRAX_I2C_DATA_PORT,
+						   CONFIG_ETRAX_I2C_DATA_PORT))) {
+		printk(KERN_WARNING "i2c_init: Failed to get IO pin for I2C data port\n");
+		return res;
+	} else if ((res = cris_io_interface_allocate_pins(if_i2c,
+							  'b',
+							  CONFIG_ETRAX_I2C_CLK_PORT,
+							  CONFIG_ETRAX_I2C_CLK_PORT))) {
+		cris_io_interface_free_pins(if_i2c,
+					    'b',
+					    CONFIG_ETRAX_I2C_DATA_PORT,
+					    CONFIG_ETRAX_I2C_DATA_PORT);
+		printk(KERN_WARNING "i2c_init: Failed to get IO pin for I2C clk port\n");
+	}
+#endif
 
-	return 0;
+	return res;
 }
 
 static int __init
@@ -711,14 +757,16 @@ i2c_register(void)
 {
 	int res;
 
-	i2c_init();
+	res = i2c_init();
+	if (res < 0)
+		return res;
   	res = register_chrdev(I2C_MAJOR, i2c_name, &i2c_fops);
 	if(res < 0) {
 		printk(KERN_ERR "i2c: couldn't get a major number.\n");
 		return res;
 	}
 
-	printk(KERN_INFO "I2C driver v2.2, (c) 1999-2001 Axis Communications AB\n");
+	printk(KERN_INFO "I2C driver v2.2, (c) 1999-2004 Axis Communications AB\n");
 	
 	return 0;
 }
diff --git a/arch/cris/arch-v10/drivers/pcf8563.c b/arch/cris/arch-v10/drivers/pcf8563.c
index b3dfdf7b8fc..201f4c90d96 100644
--- a/arch/cris/arch-v10/drivers/pcf8563.c
+++ b/arch/cris/arch-v10/drivers/pcf8563.c
@@ -15,7 +15,7 @@
  *
  * Author: Tobias Anderberg <tobiasa@axis.com>.
  *
- * $Id: pcf8563.c,v 1.8 2004/08/24 06:42:51 starvik Exp $
+ * $Id: pcf8563.c,v 1.11 2005/03/07 13:13:07 starvik Exp $
  */
 
 #include <linux/config.h>
@@ -40,7 +40,7 @@
 #define PCF8563_MAJOR 121		/* Local major number. */
 #define DEVICE_NAME "rtc"		/* Name which is registered in /proc/devices. */
 #define PCF8563_NAME "PCF8563"
-#define DRIVER_VERSION "$Revision: 1.8 $"
+#define DRIVER_VERSION "$Revision: 1.11 $"
 
 /* I2C bus slave registers. */
 #define RTC_I2C_READ		0xa3
@@ -49,6 +49,8 @@
 /* Two simple wrapper macros, saves a few keystrokes. */
 #define rtc_read(x) i2c_readreg(RTC_I2C_READ, x)
 #define rtc_write(x,y) i2c_writereg(RTC_I2C_WRITE, x, y)
+
+static DEFINE_SPINLOCK(rtc_lock); /* Protect state etc */
 	
 static const unsigned char days_in_month[] =
 	{ 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
@@ -125,9 +127,12 @@ get_rtc_time(struct rtc_time *tm)
 int __init
 pcf8563_init(void)
 {
-	unsigned char ret;
+	int ret;
 
-	i2c_init();
+	if ((ret = i2c_init())) {
+		printk(KERN_CRIT "pcf8563_init: failed to init i2c\n");
+		return ret;
+	}
 
 	/*
 	 * First of all we need to reset the chip. This is done by
@@ -200,12 +205,15 @@ pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned
 			{
 				struct rtc_time tm;
 
+				spin_lock(&rtc_lock);
 				get_rtc_time(&tm);
 
 				if (copy_to_user((struct rtc_time *) arg, &tm, sizeof(struct rtc_time))) {
+					spin_unlock(&rtc_lock);
 					return -EFAULT;
 				}
 
+				spin_unlock(&rtc_lock);
 				return 0;
 			}
 			break;
@@ -250,6 +258,8 @@ pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned
 				BIN_TO_BCD(tm.tm_min);
 				BIN_TO_BCD(tm.tm_sec);
 				tm.tm_mon |= century;
+
+				spin_lock(&rtc_lock);
 				
 				rtc_write(RTC_YEAR, tm.tm_year);
 				rtc_write(RTC_MONTH, tm.tm_mon);
@@ -258,6 +268,8 @@ pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned
 				rtc_write(RTC_MINUTES, tm.tm_min);
 				rtc_write(RTC_SECONDS, tm.tm_sec);
 
+				spin_unlock(&rtc_lock);
+
 				return 0;
 #endif /* !CONFIG_ETRAX_RTC_READONLY */
 			}
diff --git a/arch/cris/arch-v10/kernel/Makefile b/arch/cris/arch-v10/kernel/Makefile
index 52761603b6a..dcfec41d353 100644
--- a/arch/cris/arch-v10/kernel/Makefile
+++ b/arch/cris/arch-v10/kernel/Makefile
@@ -1,4 +1,4 @@
-# $Id: Makefile,v 1.5 2004/06/02 08:24:38 starvik Exp $
+# $Id: Makefile,v 1.6 2004/12/13 12:21:51 starvik Exp $
 #
 # Makefile for the linux kernel.
 #
@@ -7,7 +7,8 @@ extra-y	:= head.o
 
 
 obj-y   := entry.o traps.o shadows.o debugport.o irq.o \
-	   process.o setup.o signal.o traps.o time.o ptrace.o
+	   process.o setup.o signal.o traps.o time.o ptrace.o \
+	   dma.o io_interface_mux.o
 
 obj-$(CONFIG_ETRAX_KGDB) += kgdb.o
 obj-$(CONFIG_ETRAX_FAST_TIMER) += fasttimer.o
diff --git a/arch/cris/arch-v10/kernel/debugport.c b/arch/cris/arch-v10/kernel/debugport.c
index 6cf069e5e7b..f3a85b77c17 100644
--- a/arch/cris/arch-v10/kernel/debugport.c
+++ b/arch/cris/arch-v10/kernel/debugport.c
@@ -12,6 +12,31 @@
  *    init_etrax_debug()
  *
  * $Log: debugport.c,v $
+ * Revision 1.27  2005/06/10 10:34:14  starvik
+ * Real console support
+ *
+ * Revision 1.26  2005/06/07 07:06:07  starvik
+ * Added LF->CR translation to make ETRAX customers happy.
+ *
+ * Revision 1.25  2005/03/08 08:56:47  mikaelam
+ * Do only set index as port->index if port is defined, otherwise use the index from the command line
+ *
+ * Revision 1.24  2005/01/19 10:26:33  mikaelam
+ * Return the cris serial driver in console device driver callback function
+ *
+ * Revision 1.23  2005/01/14 10:12:17  starvik
+ * KGDB on separate port.
+ * Console fixes from 2.4.
+ *
+ * Revision 1.22  2005/01/11 16:06:13  starvik
+ * typo
+ *
+ * Revision 1.21  2005/01/11 13:49:14  starvik
+ * Added raw_printk to be used where we don't trust the console.
+ *
+ * Revision 1.20  2004/12/27 11:18:32  starvik
+ * Merge of Linux 2.6.10 (not functional yet).
+ *
  * Revision 1.19  2004/10/21 07:26:16  starvik
  * Made it possible to specify console settings on kernel command line.
  *
@@ -114,7 +139,11 @@ struct dbg_port ports[]=
     R_SERIAL0_BAUD,
     R_SERIAL0_TR_CTRL,
     R_SERIAL0_REC_CTRL,
-    IO_STATE(R_IRQ_MASK1_SET, ser0_data, set)
+    IO_STATE(R_IRQ_MASK1_SET, ser0_data, set),
+    0,
+    115200,
+    'N',
+    8
   },
   {
     1,
@@ -124,7 +153,11 @@ struct dbg_port ports[]=
     R_SERIAL1_BAUD,
     R_SERIAL1_TR_CTRL,
     R_SERIAL1_REC_CTRL,
-    IO_STATE(R_IRQ_MASK1_SET, ser1_data, set)
+    IO_STATE(R_IRQ_MASK1_SET, ser1_data, set),
+    0,
+    115200,
+    'N',
+    8
   },
   {
     2,
@@ -134,7 +167,11 @@ struct dbg_port ports[]=
     R_SERIAL2_BAUD,
     R_SERIAL2_TR_CTRL,
     R_SERIAL2_REC_CTRL,
-    IO_STATE(R_IRQ_MASK1_SET, ser2_data, set)
+    IO_STATE(R_IRQ_MASK1_SET, ser2_data, set),
+    0,
+    115200,
+    'N',
+    8
   },
   {
     3,
@@ -144,11 +181,15 @@ struct dbg_port ports[]=
     R_SERIAL3_BAUD,
     R_SERIAL3_TR_CTRL,
     R_SERIAL3_REC_CTRL,
-    IO_STATE(R_IRQ_MASK1_SET, ser3_data, set)
+    IO_STATE(R_IRQ_MASK1_SET, ser3_data, set),
+    0,
+    115200,
+    'N',
+    8
   }
 };
 
-static struct tty_driver *serial_driver;
+extern struct tty_driver *serial_driver;
 
 struct dbg_port* port =
 #if defined(CONFIG_ETRAX_DEBUG_PORT0)
@@ -162,37 +203,44 @@ struct dbg_port* port =
 #else
   NULL;
 #endif
-/* Used by serial.c to register a debug_write_function so that the normal
- * serial driver is used for kernel debug output
- */
-typedef int (*debugport_write_function)(int i, const char *buf, unsigned int len);
 
-debugport_write_function debug_write_function = NULL;
+static struct dbg_port* kgdb_port =
+#if defined(CONFIG_ETRAX_KGDB_PORT0)
+  &ports[0];
+#elif defined(CONFIG_ETRAX_KGDB_PORT1)
+  &ports[1];
+#elif defined(CONFIG_ETRAX_KGDB_PORT2)
+  &ports[2];
+#elif defined(CONFIG_ETRAX_KGDB_PORT3)
+  &ports[3];
+#else
+  NULL;
+#endif
 
 static void
-start_port(void)
+start_port(struct dbg_port* p)
 {
 	unsigned long rec_ctrl = 0;
 	unsigned long tr_ctrl = 0;
 
-	if (!port)
+	if (!p)
 		return;
 
-	if (port->started)
+	if (p->started)
 		return;
-	port->started = 1;
+	p->started = 1;
 
-	if (port->index == 0)
+	if (p->index == 0)
 	{
 		genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
 		genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused);
 	}
-	else if (port->index == 1)
+	else if (p->index == 1)
 	{
 		genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
 		genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb);
 	}
-	else if (port->index == 2)
+	else if (p->index == 2)
 	{
 		genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
 		genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0);
@@ -211,69 +259,69 @@ start_port(void)
 
 	*R_GEN_CONFIG = genconfig_shadow;
 
-	*port->xoff =
+	*p->xoff =
 		IO_STATE(R_SERIAL0_XOFF, tx_stop, enable) |
 		IO_STATE(R_SERIAL0_XOFF, auto_xoff, disable) |
 		IO_FIELD(R_SERIAL0_XOFF, xoff_char, 0);
 
-	switch (port->baudrate)
+	switch (p->baudrate)
 	{
 	case 0:
 	case 115200:
-		*port->baud =
+		*p->baud =
 		  IO_STATE(R_SERIAL0_BAUD, tr_baud, c115k2Hz) |
 		  IO_STATE(R_SERIAL0_BAUD, rec_baud, c115k2Hz);
 		break;
 	case 1200:
-		*port->baud =
+		*p->baud =
 		  IO_STATE(R_SERIAL0_BAUD, tr_baud, c1200Hz) |
 		  IO_STATE(R_SERIAL0_BAUD, rec_baud, c1200Hz);
 		break;
 	case 2400:
-		*port->baud =
+		*p->baud =
 		  IO_STATE(R_SERIAL0_BAUD, tr_baud, c2400Hz) |
 		  IO_STATE(R_SERIAL0_BAUD, rec_baud, c2400Hz);
 		break;
 	case 4800:
-		*port->baud =
+		*p->baud =
 		  IO_STATE(R_SERIAL0_BAUD, tr_baud, c4800Hz) |
 		  IO_STATE(R_SERIAL0_BAUD, rec_baud, c4800Hz);
 		break;
 	case 9600:
-		*port->baud =
+		*p->baud =
 		  IO_STATE(R_SERIAL0_BAUD, tr_baud, c9600Hz) |
 		  IO_STATE(R_SERIAL0_BAUD, rec_baud, c9600Hz);
 		  break;
 	case 19200:
-		*port->baud =
+		*p->baud =
 		  IO_STATE(R_SERIAL0_BAUD, tr_baud, c19k2Hz) |
 		  IO_STATE(R_SERIAL0_BAUD, rec_baud, c19k2Hz);
 		 break;
 	case 38400:
-		*port->baud =
+		*p->baud =
 		  IO_STATE(R_SERIAL0_BAUD, tr_baud, c38k4Hz) |
 		  IO_STATE(R_SERIAL0_BAUD, rec_baud, c38k4Hz);
 		break;
 	case 57600:
-		*port->baud =
+		*p->baud =
 		  IO_STATE(R_SERIAL0_BAUD, tr_baud, c57k6Hz) |
 		  IO_STATE(R_SERIAL0_BAUD, rec_baud, c57k6Hz);
 		break;
 	default:
-		*port->baud =
+		*p->baud =
 		  IO_STATE(R_SERIAL0_BAUD, tr_baud, c115k2Hz) |
 		  IO_STATE(R_SERIAL0_BAUD, rec_baud, c115k2Hz);
 		  break;
         }
 
-	if (port->parity == 'E') {
+	if (p->parity == 'E') {
 		rec_ctrl =
 		  IO_STATE(R_SERIAL0_REC_CTRL, rec_par, even) |
 		  IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
 		tr_ctrl =
 		  IO_STATE(R_SERIAL0_TR_CTRL, tr_par, even) |
 		  IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable);
-	} else if (port->parity == 'O') {
+	} else if (p->parity == 'O') {
 		rec_ctrl =
 		  IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd) |
 		  IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
@@ -288,8 +336,7 @@ start_port(void)
 		  IO_STATE(R_SERIAL0_TR_CTRL, tr_par, even) |
 		  IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, disable);
 	}
-
-	if (port->bits == 7)
+	if (p->bits == 7)
 	{
 		rec_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit);
 		tr_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit);
@@ -300,7 +347,7 @@ start_port(void)
 		tr_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_8bit);
 	}
 
-	*port->rec_ctrl =
+	*p->rec_ctrl =
 		IO_STATE(R_SERIAL0_REC_CTRL, dma_err, stop) |
 		IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable) |
 		IO_STATE(R_SERIAL0_REC_CTRL, rts_, active) |
@@ -308,7 +355,7 @@ start_port(void)
 		IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, normal) |
 		rec_ctrl;
 
-	*port->tr_ctrl =
+	*p->tr_ctrl =
 		IO_FIELD(R_SERIAL0_TR_CTRL, txd, 0) |
 		IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable) |
 		IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, disabled) |
@@ -323,8 +370,18 @@ console_write_direct(struct console *co, const char *buf, unsigned int len)
 	int i;
 	unsigned long flags;
 	local_irq_save(flags);
+
+        if (!port)
+		return;
+
 	/* Send data */
 	for (i = 0; i < len; i++) {
+		/* LF -> CRLF */
+		if (buf[i] == '\n') {
+			while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready)))
+			;
+			*port->write = '\r';
+		}
 		/* Wait until transmitter is ready and send.*/
 		while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready)))
 			;
@@ -333,6 +390,25 @@ console_write_direct(struct console *co, const char *buf, unsigned int len)
 	local_irq_restore(flags);
 }
 
+int raw_printk(const char *fmt, ...)
+{
+	static char buf[1024];
+	int printed_len;
+	static int first = 1;
+	if (first) {
+		/* Force reinitialization of the port to get manual mode. */
+		port->started = 0;
+		start_port(port);
+		first = 0;
+	}
+	va_list args;
+	va_start(args, fmt);
+	printed_len = vsnprintf(buf, sizeof(buf), fmt, args);
+	va_end(args);
+	console_write_direct(NULL, buf, strlen(buf));
+	return printed_len;
+}
+
 static void
 console_write(struct console *co, const char *buf, unsigned int len)
 {
@@ -345,18 +421,7 @@ console_write(struct console *co, const char *buf, unsigned int len)
 	return;
 #endif
 
-	start_port();
-
-#ifdef CONFIG_ETRAX_KGDB
-	/* kgdb needs to output debug info using the gdb protocol */
-	putDebugString(buf, len);
-	return;
-#endif
-
-	if (debug_write_function)
-		debug_write_function(co->index, buf, len);
-	else
-		console_write_direct(co, buf, len);
+        console_write_direct(co, buf, len);
 }
 
 /* legacy function */
@@ -374,8 +439,11 @@ getDebugChar(void)
 {
 	unsigned long readval;
 
+	if (!kgdb_port)
+		return 0;
+
 	do {
-		readval = *port->read;
+		readval = *kgdb_port->read;
 	} while (!(readval & IO_MASK(R_SERIAL0_READ, data_avail)));
 
 	return (readval & IO_MASK(R_SERIAL0_READ, data_in));
@@ -386,9 +454,12 @@ getDebugChar(void)
 void
 putDebugChar(int val)
 {
-	while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready)))
+	if (!kgdb_port)
+		return;
+
+	while (!(*kgdb_port->read & IO_MASK(R_SERIAL0_READ, tr_ready)))
 		;
-	*port->write = val;
+	*kgdb_port->write = val;
 }
 
 /* Enable irq for receiving chars on the debug port, used by kgdb */
@@ -396,19 +467,16 @@ putDebugChar(int val)
 void
 enableDebugIRQ(void)
 {
-	*R_IRQ_MASK1_SET = port->irq;
+	if (!kgdb_port)
+		return;
+
+	*R_IRQ_MASK1_SET = kgdb_port->irq;
 	/* use R_VECT_MASK directly, since we really bypass Linux normal
 	 * IRQ handling in kgdb anyway, we don't need to use enable_irq
 	 */
 	*R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set);
 
-	*port->rec_ctrl = IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable);
-}
-
-static struct tty_driver*
-etrax_console_device(struct console* co, int *index)
-{
-	return serial_driver;
+	*kgdb_port->rec_ctrl = IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable);
 }
 
 static int __init
@@ -428,11 +496,69 @@ console_setup(struct console *co, char *options)
 		if (*s) port->parity = *s++;
 		if (*s) port->bits   = *s++ - '0';
 		port->started = 0;
-		start_port();
+		start_port(0);
 	}
 	return 0;
 }
 
+/* This is a dummy serial device that throws away anything written to it.
+ * This is used when no debug output is wanted.
+ */
+static struct tty_driver dummy_driver;
+
+static int dummy_open(struct tty_struct *tty, struct file * filp)
+{
+	return 0;
+}
+
+static void dummy_close(struct tty_struct *tty, struct file * filp)
+{
+}
+
+static int dummy_write(struct tty_struct * tty,
+                       const unsigned char *buf, int count)
+{
+	return count;
+}
+
+static int
+dummy_write_room(struct tty_struct *tty)
+{
+	return 8192;
+}
+
+void __init
+init_dummy_console(void)
+{
+	memset(&dummy_driver, 0, sizeof(struct tty_driver));
+	dummy_driver.driver_name = "serial";
+	dummy_driver.name = "ttyS";
+	dummy_driver.major = TTY_MAJOR;
+	dummy_driver.minor_start = 68;
+	dummy_driver.num = 1;       /* etrax100 has 4 serial ports */
+	dummy_driver.type = TTY_DRIVER_TYPE_SERIAL;
+	dummy_driver.subtype = SERIAL_TYPE_NORMAL;
+	dummy_driver.init_termios = tty_std_termios;
+	dummy_driver.init_termios.c_cflag =
+		B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */
+	dummy_driver.flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_NO_DEVFS;
+
+	dummy_driver.open = dummy_open;
+	dummy_driver.close = dummy_close;
+	dummy_driver.write = dummy_write;
+	dummy_driver.write_room = dummy_write_room;
+	if (tty_register_driver(&dummy_driver))
+		panic("Couldn't register dummy serial driver\n");
+}
+
+static struct tty_driver*
+etrax_console_device(struct console* co, int *index)
+{
+	if (port)
+		*index = port->index;
+        return port ? serial_driver : &dummy_driver;
+}
+
 static struct console sercons = {
 	name : "ttyS",
 	write: console_write,
@@ -504,28 +630,21 @@ init_etrax_debug(void)
 	static int first = 1;
 
 	if (!first) {
-		if (!port) {
-			register_console(&sercons0);
-			register_console(&sercons1);
-			register_console(&sercons2);
-			register_console(&sercons3);
-			unregister_console(&sercons);
-		}
+		unregister_console(&sercons);
+		register_console(&sercons0);
+		register_console(&sercons1);
+		register_console(&sercons2);
+		register_console(&sercons3);
+                init_dummy_console();
 		return 0;
 	}
-	first = 0;
-	if (port)
-		register_console(&sercons);
-	return 0;
-}
 
-int __init
-init_console(void)
-{
-	serial_driver = alloc_tty_driver(1);
-	if (!serial_driver)
-		return -ENOMEM;
+	first = 0;
+	register_console(&sercons);
+	start_port(port);
+#ifdef CONFIG_ETRAX_KGDB
+	start_port(kgdb_port);
+#endif
 	return 0;
 }
-
 __initcall(init_etrax_debug);
diff --git a/arch/cris/arch-v10/kernel/dma.c b/arch/cris/arch-v10/kernel/dma.c
new file mode 100644
index 00000000000..e9a0311b141
--- /dev/null
+++ b/arch/cris/arch-v10/kernel/dma.c
@@ -0,0 +1,287 @@
+/* Wrapper for DMA channel allocator that updates DMA client muxing.
+ * Copyright 2004, Axis Communications AB
+ * $Id: dma.c,v 1.1 2004/12/13 12:21:51 starvik Exp $
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+
+#include <asm/dma.h>
+#include <asm/arch/svinto.h>
+
+/* Macro to access ETRAX 100 registers */
+#define SETS(var, reg, field, val) var = (var & ~IO_MASK_(reg##_, field##_)) | \
+					  IO_STATE_(reg##_, field##_, _##val)
+
+
+static char used_dma_channels[MAX_DMA_CHANNELS];
+static const char * used_dma_channels_users[MAX_DMA_CHANNELS];
+
+int cris_request_dma(unsigned int dmanr, const char * device_id,
+		     unsigned options, enum dma_owner owner)
+{
+	unsigned long flags;
+	unsigned long int gens;
+	int fail = -EINVAL;
+
+	if ((dmanr < 0) || (dmanr >= MAX_DMA_CHANNELS)) {
+		printk(KERN_CRIT "cris_request_dma: invalid DMA channel %u\n", dmanr);
+		return -EINVAL;
+	}
+
+	local_irq_save(flags);
+	if (used_dma_channels[dmanr]) {
+		local_irq_restore(flags);
+		if (options & DMA_VERBOSE_ON_ERROR) {
+			printk(KERN_CRIT "Failed to request DMA %i for %s, already allocated by %s\n", dmanr, device_id, used_dma_channels_users[dmanr]);
+		}
+		if (options & DMA_PANIC_ON_ERROR) {
+			panic("request_dma error!");
+		}
+		return -EBUSY;
+	}
+
+	gens = genconfig_shadow;
+
+	switch(owner)
+	{
+	case dma_eth:
+		if ((dmanr != NETWORK_TX_DMA_NBR) &&
+		    (dmanr != NETWORK_RX_DMA_NBR)) {
+			printk(KERN_CRIT "Invalid DMA channel for eth\n");
+			goto bail;
+		}
+		break;
+	case dma_ser0:
+		if (dmanr == SER0_TX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma6, serial0);
+		} else if (dmanr == SER0_RX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma7, serial0);
+		} else {
+			printk(KERN_CRIT "Invalid DMA channel for ser0\n");
+			goto bail;
+		}
+		break;
+	case dma_ser1:
+		if (dmanr == SER1_TX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma8, serial1);
+		} else if (dmanr == SER1_RX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma9, serial1);
+		} else {
+			printk(KERN_CRIT "Invalid DMA channel for ser1\n");
+			goto bail;
+		}
+		break;
+	case dma_ser2:
+		if (dmanr == SER2_TX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma2, serial2);
+		} else if (dmanr == SER2_RX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma3, serial2);
+		} else {
+			printk(KERN_CRIT "Invalid DMA channel for ser2\n");
+			goto bail;
+		}
+		break;
+	case dma_ser3:
+		if (dmanr == SER3_TX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma4, serial3);
+		} else if (dmanr == SER3_RX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma5, serial3);
+		} else {
+			printk(KERN_CRIT "Invalid DMA channel for ser3\n");
+			goto bail;
+		}
+		break;
+	case dma_ata:
+		if (dmanr == ATA_TX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma2, ata);
+		} else if (dmanr == ATA_RX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma3, ata);
+		} else {
+			printk(KERN_CRIT "Invalid DMA channel for ata\n");
+			goto bail;
+		}
+		break;
+	case dma_ext0:
+		if (dmanr == EXTDMA0_TX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma4, extdma0);
+		} else if (dmanr == EXTDMA0_RX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma5, extdma0);
+		} else {
+			printk(KERN_CRIT "Invalid DMA channel for ext0\n");
+			goto bail;
+		}
+		break;
+	case dma_ext1:
+		if (dmanr == EXTDMA1_TX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma6, extdma1);
+		} else if (dmanr == EXTDMA1_RX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma7, extdma1);
+		} else {
+			printk(KERN_CRIT "Invalid DMA channel for ext1\n");
+			goto bail;
+		}
+		break;
+	case dma_int6:
+		if (dmanr == MEM2MEM_RX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma7, intdma6);
+		} else {
+			printk(KERN_CRIT "Invalid DMA channel for int6\n");
+			goto bail;
+		}
+		break;
+	case dma_int7:
+		if (dmanr == MEM2MEM_TX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma6, intdma7);
+		} else {
+			printk(KERN_CRIT "Invalid DMA channel for int7\n");
+			goto bail;
+		}
+		break;
+	case dma_usb:
+		if (dmanr == USB_TX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma8, usb);
+		} else if (dmanr == USB_RX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma9, usb);
+		} else {
+			printk(KERN_CRIT "Invalid DMA channel for usb\n");
+			goto bail;
+		}
+		break;
+	case dma_scsi0:
+		if (dmanr == SCSI0_TX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma2, scsi0);
+		} else if (dmanr == SCSI0_RX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma3, scsi0);
+		} else {
+			printk(KERN_CRIT "Invalid DMA channel for scsi0\n");
+			goto bail;
+		}
+		break;
+	case dma_scsi1:
+		if (dmanr == SCSI1_TX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma4, scsi1);
+		} else if (dmanr == SCSI1_RX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma5, scsi1);
+		} else {
+			printk(KERN_CRIT "Invalid DMA channel for scsi1\n");
+			goto bail;
+		}
+		break;
+	case dma_par0:
+		if (dmanr == PAR0_TX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma2, par0);
+		} else if (dmanr == PAR0_RX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma3, par0);
+		} else {
+			printk(KERN_CRIT "Invalid DMA channel for par0\n");
+			goto bail;
+		}
+		break;
+	case dma_par1:
+		if (dmanr == PAR1_TX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma4, par1);
+		} else if (dmanr == PAR1_RX_DMA_NBR) {
+			SETS(gens, R_GEN_CONFIG, dma5, par1);
+		} else {
+			printk(KERN_CRIT "Invalid DMA channel for par1\n");
+			goto bail;
+		}
+		break;
+	default:
+		printk(KERN_CRIT "Invalid DMA owner.\n");
+		goto bail;
+	}
+
+	used_dma_channels[dmanr] = 1;
+	used_dma_channels_users[dmanr] = device_id;
+
+	{
+		volatile int i;
+		genconfig_shadow = gens;
+		*R_GEN_CONFIG = genconfig_shadow;
+		/* Wait 12 cycles before doing any DMA command */
+		for(i = 6; i > 0; i--)
+			nop();
+	}
+	fail = 0;
+ bail:
+	local_irq_restore(flags);
+	return fail;
+}
+
+void cris_free_dma(unsigned int dmanr, const char * device_id)
+{
+	unsigned long flags;
+	if ((dmanr < 0) || (dmanr >= MAX_DMA_CHANNELS)) {
+		printk(KERN_CRIT "cris_free_dma: invalid DMA channel %u\n", dmanr);
+		return;
+	}
+
+	local_irq_save(flags);
+	if (!used_dma_channels[dmanr]) {
+		printk(KERN_CRIT "cris_free_dma: DMA channel %u not allocated\n", dmanr);
+	} else if (device_id != used_dma_channels_users[dmanr]) {
+		printk(KERN_CRIT "cris_free_dma: DMA channel %u not allocated by device\n", dmanr);
+	} else {
+		switch(dmanr)
+		{
+		case 0:
+			*R_DMA_CH0_CMD = IO_STATE(R_DMA_CH0_CMD, cmd, reset);
+			while (IO_EXTRACT(R_DMA_CH0_CMD, cmd, *R_DMA_CH0_CMD) ==
+			       IO_STATE_VALUE(R_DMA_CH0_CMD, cmd, reset));
+			break;
+		case 1:
+			*R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, reset);
+			while (IO_EXTRACT(R_DMA_CH1_CMD, cmd, *R_DMA_CH1_CMD) ==
+			       IO_STATE_VALUE(R_DMA_CH1_CMD, cmd, reset));
+			break;
+		case 2:
+			*R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, reset);
+			while (IO_EXTRACT(R_DMA_CH2_CMD, cmd, *R_DMA_CH2_CMD) ==
+			       IO_STATE_VALUE(R_DMA_CH2_CMD, cmd, reset));
+			break;
+		case 3:
+			*R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, reset);
+			while (IO_EXTRACT(R_DMA_CH3_CMD, cmd, *R_DMA_CH3_CMD) ==
+			       IO_STATE_VALUE(R_DMA_CH3_CMD, cmd, reset));
+			break;
+		case 4:
+			*R_DMA_CH4_CMD = IO_STATE(R_DMA_CH4_CMD, cmd, reset);
+			while (IO_EXTRACT(R_DMA_CH4_CMD, cmd, *R_DMA_CH4_CMD) ==
+			       IO_STATE_VALUE(R_DMA_CH4_CMD, cmd, reset));
+			break;
+		case 5:
+			*R_DMA_CH5_CMD = IO_STATE(R_DMA_CH5_CMD, cmd, reset);
+			while (IO_EXTRACT(R_DMA_CH5_CMD, cmd, *R_DMA_CH5_CMD) ==
+			       IO_STATE_VALUE(R_DMA_CH5_CMD, cmd, reset));
+			break;
+		case 6:
+			*R_DMA_CH6_CMD = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
+			while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *R_DMA_CH6_CMD) ==
+			       IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
+			break;
+		case 7:
+			*R_DMA_CH7_CMD = IO_STATE(R_DMA_CH7_CMD, cmd, reset);
+			while (IO_EXTRACT(R_DMA_CH7_CMD, cmd, *R_DMA_CH7_CMD) ==
+			       IO_STATE_VALUE(R_DMA_CH7_CMD, cmd, reset));
+			break;
+		case 8:
+			*R_DMA_CH8_CMD = IO_STATE(R_DMA_CH8_CMD, cmd, reset);
+			while (IO_EXTRACT(R_DMA_CH8_CMD, cmd, *R_DMA_CH8_CMD) ==
+			       IO_STATE_VALUE(R_DMA_CH8_CMD, cmd, reset));
+			break;
+		case 9:
+			*R_DMA_CH9_CMD = IO_STATE(R_DMA_CH9_CMD, cmd, reset);
+			while (IO_EXTRACT(R_DMA_CH9_CMD, cmd, *R_DMA_CH9_CMD) ==
+			       IO_STATE_VALUE(R_DMA_CH9_CMD, cmd, reset));
+			break;
+		}
+		used_dma_channels[dmanr] = 0;
+	}
+	local_irq_restore(flags);
+}
+
+EXPORT_SYMBOL(cris_request_dma);
+EXPORT_SYMBOL(cris_free_dma);
diff --git a/arch/cris/arch-v10/kernel/entry.S b/arch/cris/arch-v10/kernel/entry.S
index 1bc44f481c3..c0163bf94a5 100644
--- a/arch/cris/arch-v10/kernel/entry.S
+++ b/arch/cris/arch-v10/kernel/entry.S
@@ -1,4 +1,4 @@
-/* $Id: entry.S,v 1.23 2004/10/19 13:07:37 starvik Exp $
+/* $Id: entry.S,v 1.28 2005/06/20 05:06:30 starvik Exp $
  *
  *  linux/arch/cris/entry.S
  *
@@ -7,6 +7,22 @@
  *  Authors:	Bjorn Wesen (bjornw@axis.com)
  *
  *  $Log: entry.S,v $
+ *  Revision 1.28  2005/06/20 05:06:30  starvik
+ *  Remove unnecessary diff to kernel.org tree
+ *
+ *  Revision 1.27  2005/03/04 08:16:16  starvik
+ *  Merge of Linux 2.6.11.
+ *
+ *  Revision 1.26  2005/01/11 13:49:47  starvik
+ *  Added NMI handler.
+ *
+ *  Revision 1.25  2004/12/27 11:18:32  starvik
+ *  Merge of Linux 2.6.10 (not functional yet).
+ *
+ *  Revision 1.24  2004/12/22 10:41:23  starvik
+ *  Updates to make v10 compile with the latest SMP aware generic code (even
+ *  though v10 will never have SMP).
+ *
  *  Revision 1.23  2004/10/19 13:07:37  starvik
  *  Merge of Linux 2.6.9
  *
@@ -279,6 +295,7 @@
 #ifdef CONFIG_PREEMPT	
 	; Check if preemptive kernel scheduling should be done
 _resume_kernel:
+	di
 	; Load current task struct
 	movs.w	-8192, $r0	;  THREAD_SIZE = 8192
 	and.d	$sp, $r0
@@ -291,12 +308,7 @@ _need_resched:
 	bpl	_Rexit
 	nop
 	; Ok, lets's do some preemptive kernel scheduling
-	move.d	PREEMPT_ACTIVE, $r10
-	move.d	$r10, [$r0+TI_preempt_count] ; Mark as active
-	ei
-	jsr	schedule
-	clear.d	[$r0+TI_preempt_count] ;  Mark as inactive
-	di
+	jsr	preempt_schedule_irq
 	; Load new task struct
 	movs.w	-8192, $r0	;  THREAD_SIZE = 8192
 	and.d	$sp, $r0
@@ -590,15 +602,15 @@ mmu_bus_fault:
 	move.d	$r0, [$sp+16]
 1:	btstq	12, $r1		   ; Refill?
 	bpl	2f
-	lsrq	PMD_SHIFT, $r1     ; Get PMD index into PGD (bit 24-31)
-	move.d  [current_pgd], $r0 ; PGD for the current process
+	lsrq	24, $r1     ; Get PGD index (bit 24-31)
+	move.d  [per_cpu__current_pgd], $r0 ; PGD for the current process
 	move.d	[$r0+$r1.d], $r0   ; Get PMD
 	beq	2f
 	nop
 	and.w	PAGE_MASK, $r0	   ; Remove PMD flags
 	move.d  [R_MMU_CAUSE], $r1
 	lsrq	PAGE_SHIFT, $r1
-	and.d	0x7ff, $r1         ; Get PTE index into PMD (bit 13-24)
+	and.d	0x7ff, $r1         ; Get PTE index into PGD (bit 13-23)
 	move.d	[$r0+$r1.d], $r1   ; Get PTE
 	beq	2f
 	nop
@@ -656,11 +668,6 @@ hwbreakpoint:
 	nop
 	
 IRQ1_interrupt:
-
-#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
-;; If we receive a watchdog interrupt while it is not expected, then set
-;; up a canonical frame and dump register contents before dying.
-
 	;; this prologue MUST match the one in irq.h and the struct in ptregs.h!!!
 	move	$brp,[$sp=$sp-16]; instruction pointer and room for a fake SBFS frame
 	push	$srp
@@ -672,9 +679,16 @@ IRQ1_interrupt:
 	push	$r10		; push orig_r10
 	clear.d [$sp=$sp-4]	; frametype == 0, normal frame
 
-;; We don't check that we actually were bit by the watchdog as opposed to
-;; an external NMI, since there is currently no handler for external NMI.
-
+	move.d	[R_IRQ_MASK0_RD], $r1 ; External NMI or watchdog?
+	and.d   0x80000000, $r1
+	beq	wdog
+	move.d  $sp, $r10
+	jsr	handle_nmi
+	setf m			; Enable NMI again
+	retb			; Return from NMI
+	nop
+wdog:
+#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 ;; Check if we're waiting for reset to happen, as signalled by
 ;; hard_reset_now setting cause_of_death to a magic value.  If so, just
 ;; get stuck until reset happens.
@@ -1118,6 +1132,10 @@ sys_call_table:
 	.long sys_mq_getsetattr
 	.long sys_ni_syscall		/* reserved for kexec */
 	.long sys_waitid
+	.long sys_ni_syscall		/* 285 */ /* available */
+	.long sys_add_key
+	.long sys_request_key
+	.long sys_keyctl
 
         /*
          * NOTE!! This doesn't have to be exact - we just have
diff --git a/arch/cris/arch-v10/kernel/fasttimer.c b/arch/cris/arch-v10/kernel/fasttimer.c
index 4717f7ae8e5..094ff45ae85 100644
--- a/arch/cris/arch-v10/kernel/fasttimer.c
+++ b/arch/cris/arch-v10/kernel/fasttimer.c
@@ -1,10 +1,20 @@
-/* $Id: fasttimer.c,v 1.6 2004/05/14 10:18:39 starvik Exp $
+/* $Id: fasttimer.c,v 1.9 2005/03/04 08:16:16 starvik Exp $
  * linux/arch/cris/kernel/fasttimer.c
  *
  * Fast timers for ETRAX100/ETRAX100LX
  * This may be useful in other OS than Linux so use 2 space indentation...
  *
  * $Log: fasttimer.c,v $
+ * Revision 1.9  2005/03/04 08:16:16  starvik
+ * Merge of Linux 2.6.11.
+ *
+ * Revision 1.8  2005/01/05 06:09:29  starvik
+ * cli()/sti() will be obsolete in 2.6.11.
+ *
+ * Revision 1.7  2005/01/03 13:35:46  starvik
+ * Removed obsolete stuff.
+ * Mark fast timer IRQ as not shared.
+ *
  * Revision 1.6  2004/05/14 10:18:39  starvik
  * Export fast_timer_list
  *
@@ -148,8 +158,7 @@ static int debug_log_cnt_wrapped = 0;
 #define DEBUG_LOG(string, value) \
 { \
   unsigned long log_flags; \
-  save_flags(log_flags); \
-  cli(); \
+  local_irq_save(log_flags); \
   debug_log_string[debug_log_cnt] = (string); \
   debug_log_value[debug_log_cnt] = (unsigned long)(value); \
   if (++debug_log_cnt >= DEBUG_LOG_MAX) \
@@ -157,7 +166,7 @@ static int debug_log_cnt_wrapped = 0;
     debug_log_cnt = debug_log_cnt % DEBUG_LOG_MAX; \
     debug_log_cnt_wrapped = 1; \
   } \
-  restore_flags(log_flags); \
+  local_irq_restore(log_flags); \
 }
 #else
 #define DEBUG_LOG(string, value)
@@ -320,8 +329,7 @@ void start_one_shot_timer(struct fast_timer *t,
 
   D1(printk("sft %s %d us\n", name, delay_us));
 
-  save_flags(flags);
-  cli();
+  local_irq_save(flags);
 
   do_gettimeofday_fast(&t->tv_set);
   tmp = fast_timer_list;
@@ -395,7 +403,7 @@ void start_one_shot_timer(struct fast_timer *t,
 
   D2(printk("start_one_shot_timer: %d us done\n", delay_us));
 
-  restore_flags(flags);
+  local_irq_restore(flags);
 } /* start_one_shot_timer */
 
 static inline int fast_timer_pending (const struct fast_timer * t)
@@ -425,11 +433,10 @@ int del_fast_timer(struct fast_timer * t)
   unsigned long flags;
   int ret;
   
-  save_flags(flags);
-  cli();
+  local_irq_save(flags);
   ret = detach_fast_timer(t);
   t->next = t->prev = NULL;
-  restore_flags(flags);
+  local_irq_restore(flags);
   return ret;
 } /* del_fast_timer */
 
@@ -444,8 +451,7 @@ timer1_handler(int irq, void *dev_id, struct pt_regs *regs)
   struct fast_timer *t;
   unsigned long flags;
 
-  save_flags(flags);
-  cli();
+  local_irq_save(flags);
 
   /* Clear timer1 irq */
   *R_IRQ_MASK0_CLR = IO_STATE(R_IRQ_MASK0_CLR, timer1, clr);
@@ -462,7 +468,7 @@ timer1_handler(int irq, void *dev_id, struct pt_regs *regs)
   fast_timer_running = 0;
   fast_timer_ints++;
 
-  restore_flags(flags);
+  local_irq_restore(flags);
 
   t = fast_timer_list;
   while (t)
@@ -482,8 +488,7 @@ timer1_handler(int irq, void *dev_id, struct pt_regs *regs)
       fast_timers_expired++;
 
       /* Remove this timer before call, since it may reuse the timer */
-      save_flags(flags);
-      cli();
+      local_irq_save(flags);
       if (t->prev)
       {
         t->prev->next = t->next;
@@ -498,7 +503,7 @@ timer1_handler(int irq, void *dev_id, struct pt_regs *regs)
       }
       t->prev = NULL;
       t->next = NULL;
-      restore_flags(flags);
+      local_irq_restore(flags);
 
       if (t->function != NULL)
       {
@@ -515,8 +520,7 @@ timer1_handler(int irq, void *dev_id, struct pt_regs *regs)
       D1(printk(".\n"));
     }
 
-    save_flags(flags);
-    cli();
+    local_irq_save(flags);
     if ((t = fast_timer_list) != NULL)
     {
       /* Start next timer.. */
@@ -535,7 +539,7 @@ timer1_handler(int irq, void *dev_id, struct pt_regs *regs)
 #endif
           start_timer1(us);
         }
-        restore_flags(flags);
+        local_irq_restore(flags);
         break;
       }
       else
@@ -546,7 +550,7 @@ timer1_handler(int irq, void *dev_id, struct pt_regs *regs)
         D1(printk("e! %d\n", us));
       }
     }
-    restore_flags(flags);
+    local_irq_restore(flags);
   }
 
   if (!t)
@@ -748,13 +752,12 @@ static int proc_fasttimer_read(char *buf, char **start, off_t offset, int len
 #endif
 
     used += sprintf(bigbuf + used, "Active timers:\n");
-    save_flags(flags);
-    cli();
+    local_irq_save(flags);
     t = fast_timer_list;
     while (t != NULL && (used+100 < BIG_BUF_SIZE))
     {
       nextt = t->next;
-      restore_flags(flags);
+      local_irq_restore(flags);
       used += sprintf(bigbuf + used, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
                       "d: %6li us data: 0x%08lX"
 /*                      " func: 0x%08lX" */
@@ -768,14 +771,14 @@ static int proc_fasttimer_read(char *buf, char **start, off_t offset, int len
                       t->data
 /*                      , t->function */
                       );
-      cli();
+      local_irq_disable();
       if (t->next != nextt)
       {
         printk(KERN_WARNING "timer removed!\n");
       }
       t = nextt;
     }
-    restore_flags(flags);
+    local_irq_restore(flags);
   }
 
   if (used - offset < len)
@@ -963,7 +966,7 @@ void fast_timer_init(void)
    if ((fasttimer_proc_entry = create_proc_entry( "fasttimer", 0, 0 )))
      fasttimer_proc_entry->read_proc = proc_fasttimer_read;
 #endif /* PROC_FS */
-    if(request_irq(TIMER1_IRQ_NBR, timer1_handler, SA_SHIRQ,
+    if(request_irq(TIMER1_IRQ_NBR, timer1_handler, 0,
                    "fast timer int", NULL))
     {
       printk("err: timer1 irq\n");
diff --git a/arch/cris/arch-v10/kernel/head.S b/arch/cris/arch-v10/kernel/head.S
index 2c1dd1184a8..f00c145b43f 100644
--- a/arch/cris/arch-v10/kernel/head.S
+++ b/arch/cris/arch-v10/kernel/head.S
@@ -1,4 +1,4 @@
-/* $Id: head.S,v 1.7 2004/05/14 07:58:01 starvik Exp $
+/* $Id: head.S,v 1.10 2005/06/20 05:12:54 starvik Exp $
  * 
  * Head of the kernel - alter with care
  *
@@ -7,6 +7,16 @@
  * Authors:	Bjorn Wesen (bjornw@axis.com)
  * 
  * $Log: head.S,v $
+ * Revision 1.10  2005/06/20 05:12:54  starvik
+ * Remove unnecessary diff to kernel.org tree
+ *
+ * Revision 1.9  2004/12/13 12:21:51  starvik
+ * Added I/O and DMA allocators from Linux 2.4
+ *
+ * Revision 1.8  2004/11/22 11:41:14  starvik
+ * Kernel command line may be supplied to kernel. Not used by Axis but may
+ * be used by customers.
+ *
  * Revision 1.7  2004/05/14 07:58:01  starvik
  * Merge of changes from 2.4
  *
@@ -181,6 +191,7 @@
 
 #define CRAMFS_MAGIC 0x28cd3d45
 #define RAM_INIT_MAGIC 0x56902387
+#define COMMAND_LINE_MAGIC 0x87109563
 
 #define START_ETHERNET_CLOCK IO_STATE(R_NETWORK_GEN_CONFIG, enable, on) |\
                              IO_STATE(R_NETWORK_GEN_CONFIG, phy, mii_clk)
@@ -490,6 +501,23 @@ _no_romfs_in_flash:
 	
 _start_it:
 
+	;; Check if kernel command line is supplied
+	cmp.d	COMMAND_LINE_MAGIC, $r10
+	bne	no_command_line
+	nop
+
+	move.d	256, $r13
+	move.d  cris_command_line, $r10
+	or.d	0x80000000, $r11 ; Make it virtual
+1:
+	move.b  [$r11+], $r12
+	move.b  $r12, [$r10+]
+	subq	1, $r13
+	bne	1b
+	nop
+
+no_command_line:
+
 	;; the kernel stack is overlayed with the task structure for each
 	;; task. thus the initial kernel stack is in the same page as the
 	;; init_task (but starts in the top of the page, size 8192)
@@ -567,76 +595,32 @@ _start_it:
 	;; Etrax product HW genconfig setup
 
 	moveq	0,$r0
-#if (!defined(CONFIG_ETRAX_KGDB) || !defined(CONFIG_ETRAX_DEBUG_PORT0)) \
-	&& !defined(CONFIG_DMA_MEMCPY)
-	; DMA channels 6 and 7 to ser0, kgdb doesnt want DMA
-	or.d	  IO_STATE (R_GEN_CONFIG, dma7, serial0)	\
-		| IO_STATE (R_GEN_CONFIG, dma6, serial0),$r0
-#endif
-#if !defined(CONFIG_ETRAX_KGDB) || !defined(CONFIG_ETRAX_DEBUG_PORT1)
-	; DMA channels 8 and 9 to ser1, kgdb doesnt want DMA
-	or.d	  IO_STATE (R_GEN_CONFIG, dma9, serial1)	\
-		| IO_STATE (R_GEN_CONFIG, dma8, serial1),$r0
-#endif	
-#ifdef CONFIG_DMA_MEMCPY
-	; 6/7 memory-memory DMA
-	or.d	  IO_STATE (R_GEN_CONFIG, dma7, intdma6)	\
-		| IO_STATE (R_GEN_CONFIG, dma6, intdma7),$r0
-#endif
-#ifdef CONFIG_ETRAX_SERIAL_PORT2
-	; Enable serial port 2
-	or.w	IO_STATE (R_GEN_CONFIG, ser2, select),$r0
-#if !defined(CONFIG_ETRAX_KGDB) || !defined(CONFIG_ETRAX_DEBUG_PORT2)
-	; DMA channels 2 and 3 to ser2, kgdb doesnt want DMA
-	or.d	  IO_STATE (R_GEN_CONFIG, dma3, serial2)	\
-		| IO_STATE (R_GEN_CONFIG, dma2, serial2),$r0
-#endif
-#endif
-#if defined(CONFIG_ETRAX_SERIAL_PORT3) || defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
-	; Enable serial port 3
-	or.w	IO_STATE (R_GEN_CONFIG, ser3, select),$r0
-#if !defined(CONFIG_ETRAX_KGDB) || !defined(CONFIG_ETRAX_DEBUG_PORT3)
-	; DMA channels 4 and 5 to ser3, kgdb doesnt want DMA
-	or.d	  IO_STATE (R_GEN_CONFIG, dma5, serial3)	\
-		| IO_STATE (R_GEN_CONFIG, dma4, serial3),$r0
-#endif
-#endif
-#if defined(CONFIG_ETRAX_PARALLEL_PORT0) || defined(CONFIG_ETRAX_ETHERNET_LPSLAVE)
-	; parport 0 enabled using DMA 2/3
-	or.w	IO_STATE (R_GEN_CONFIG, par0, select),$r0
-#endif
-#if defined(CONFIG_ETRAX_PARALLEL_PORT1) || defined(CONFIG_ETRAX_ETHERNET_LPSLAVE)
-	; parport 1 enabled using DMA 4/5
-	or.w	IO_STATE (R_GEN_CONFIG, par1, select),$r0
-#endif
-#ifdef CONFIG_ETRAX_IDE
-	; DMA channels 2 and 3 to ATA, ATA enabled
-	or.d	  IO_STATE (R_GEN_CONFIG, dma3, ata)	\
-		| IO_STATE (R_GEN_CONFIG, dma2, ata)	\
-		| IO_STATE (R_GEN_CONFIG, ata, select),$r0
-#endif
-	
-#ifdef CONFIG_ETRAX_USB_HOST_PORT1
-	; Set the USB port 1 enable bit
-	or.d	IO_STATE (R_GEN_CONFIG, usb1, select),$r0
-#endif
-#ifdef CONFIG_ETRAX_USB_HOST_PORT2
-	; Set the USB port 2 enable bit
-	or.d	IO_STATE (R_GEN_CONFIG, usb2, select),$r0
-#endif
-#ifdef CONFIG_ETRAX_USB_HOST
-	; Connect DMA channels 8 and 9 to USB
-	and.d	(~(IO_MASK (R_GEN_CONFIG, dma9)		\
-		   | IO_MASK (R_GEN_CONFIG, dma8)))	\
-		| IO_STATE (R_GEN_CONFIG, dma9, usb)	\
-		| IO_STATE (R_GEN_CONFIG, dma8, usb),$r0
-#endif
-	
-#ifdef CONFIG_JULIETTE
-	; DMA channels 4 and 5 to EXTDMA0, for Juliette
-	or.d	  IO_STATE (R_GEN_CONFIG, dma5, extdma0)	\
-		| IO_STATE (R_GEN_CONFIG, dma4, extdma0),$r0
-#endif
+
+	;; Init interfaces (disable them).
+	or.d	  IO_STATE (R_GEN_CONFIG, scsi0, disable) \
+		| IO_STATE (R_GEN_CONFIG, ata, disable) \
+		| IO_STATE (R_GEN_CONFIG, par0, disable) \
+		| IO_STATE (R_GEN_CONFIG, ser2, disable) \
+		| IO_STATE (R_GEN_CONFIG, mio, disable) \
+		| IO_STATE (R_GEN_CONFIG, scsi1, disable) \
+		| IO_STATE (R_GEN_CONFIG, scsi0w, disable) \
+		| IO_STATE (R_GEN_CONFIG, par1, disable) \
+		| IO_STATE (R_GEN_CONFIG, ser3, disable) \
+		| IO_STATE (R_GEN_CONFIG, mio_w, disable) \
+		| IO_STATE (R_GEN_CONFIG, usb1, disable) \
+		| IO_STATE (R_GEN_CONFIG, usb2, disable) \
+		| IO_STATE (R_GEN_CONFIG, par_w, disable),$r0
+
+	;; Init DMA channel muxing (set to unused clients).
+	or.d	  IO_STATE (R_GEN_CONFIG, dma2, ata)	\
+		| IO_STATE (R_GEN_CONFIG, dma3, ata) \
+		| IO_STATE (R_GEN_CONFIG, dma4, scsi1) \
+		| IO_STATE (R_GEN_CONFIG, dma5, scsi1) \
+		| IO_STATE (R_GEN_CONFIG, dma6, unused) \
+		| IO_STATE (R_GEN_CONFIG, dma7, unused) \
+		| IO_STATE (R_GEN_CONFIG, dma8, usb) \
+		| IO_STATE (R_GEN_CONFIG, dma9, usb),$r0
+
 
 #if defined(CONFIG_ETRAX_DEF_R_PORT_G0_DIR_OUT)
         or.d      IO_STATE (R_GEN_CONFIG, g0dir, out),$r0
diff --git a/arch/cris/arch-v10/kernel/io_interface_mux.c b/arch/cris/arch-v10/kernel/io_interface_mux.c
new file mode 100644
index 00000000000..29d48ad00df
--- /dev/null
+++ b/arch/cris/arch-v10/kernel/io_interface_mux.c
@@ -0,0 +1,879 @@
+/* IO interface mux allocator for ETRAX100LX.
+ * Copyright 2004, Axis Communications AB
+ * $Id: io_interface_mux.c,v 1.2 2004/12/21 12:08:38 starvik Exp $
+ */
+
+
+/* C.f. ETRAX100LX Designer's Reference 20.9 */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <asm/arch/svinto.h>
+#include <asm/io.h>
+#include <asm/arch/io_interface_mux.h>
+
+
+#define DBG(s)
+
+/* Macro to access ETRAX 100 registers */
+#define SETS(var, reg, field, val) var = (var & ~IO_MASK_(reg##_, field##_)) | \
+					  IO_STATE_(reg##_, field##_, _##val)
+
+enum io_if_group {
+	group_a = (1<<0),
+	group_b = (1<<1),
+	group_c = (1<<2),
+	group_d = (1<<3),
+	group_e = (1<<4),
+	group_f = (1<<5)
+};
+
+struct watcher
+{
+	void (*notify)(const unsigned int gpio_in_available,
+		       const unsigned int gpio_out_available,
+		       const unsigned char pa_available,
+		       const unsigned char pb_available);
+	struct watcher *next;
+};
+
+
+struct if_group
+{
+	enum io_if_group        group;
+	unsigned char           used;
+	enum cris_io_interface  owner;
+};
+
+
+struct interface
+{
+	enum cris_io_interface   ioif;
+	unsigned char            groups;
+	unsigned char            used;
+	char                    *owner;
+	unsigned int             gpio_g_in;
+	unsigned int             gpio_g_out;
+	unsigned char            gpio_b;
+};
+
+static struct if_group if_groups[6] = {
+	{
+		.group = group_a,
+		.used = 0,
+	},
+	{
+		.group = group_b,
+		.used = 0,
+	},
+	{
+		.group = group_c,
+		.used = 0,
+	},
+	{
+		.group = group_d,
+		.used = 0,
+	},
+	{
+		.group = group_e,
+		.used = 0,
+	},
+	{
+		.group = group_f,
+		.used = 0,
+	}
+};
+
+/* The order in the array must match the order of enum
+ * cris_io_interface in io_interface_mux.h */
+static struct interface interfaces[] = {
+	/* Begin Non-multiplexed interfaces */
+	{
+		.ioif = if_eth,
+		.groups = 0,
+		.gpio_g_in = 0,
+		.gpio_g_out = 0,
+		.gpio_b = 0
+	},
+	{
+		.ioif = if_serial_0,
+		.groups = 0,
+		.gpio_g_in = 0,
+		.gpio_g_out = 0,
+		.gpio_b = 0
+	},
+	/* End Non-multiplexed interfaces */
+	{
+		.ioif = if_serial_1,
+		.groups = group_e,
+		.gpio_g_in =  0x00000000,
+		.gpio_g_out = 0x00000000,
+		.gpio_b = 0x00
+	},
+	{
+		.ioif = if_serial_2,
+		.groups = group_b,
+		.gpio_g_in =  0x000000c0,
+		.gpio_g_out = 0x000000c0,
+		.gpio_b = 0x00
+	},
+	{
+		.ioif = if_serial_3,
+		.groups = group_c,
+		.gpio_g_in =  0xc0000000,
+		.gpio_g_out = 0xc0000000,
+		.gpio_b = 0x00
+	},
+	{
+		.ioif = if_sync_serial_1,
+		.groups = group_e | group_f, /* if_sync_serial_1 and if_sync_serial_3
+					       can be used simultaneously */
+		.gpio_g_in =  0x00000000,
+		.gpio_g_out = 0x00000000,
+		.gpio_b = 0x10
+	},
+	{
+		.ioif = if_sync_serial_3,
+		.groups = group_c | group_f,
+		.gpio_g_in =  0xc0000000,
+		.gpio_g_out = 0xc0000000,
+		.gpio_b = 0x80
+	},
+	{
+		.ioif = if_shared_ram,
+		.groups = group_a,
+		.gpio_g_in =  0x0000ff3e,
+		.gpio_g_out = 0x0000ff38,
+		.gpio_b = 0x00
+	},
+	{
+		.ioif = if_shared_ram_w,
+		.groups = group_a | group_d,
+		.gpio_g_in =  0x00ffff3e,
+		.gpio_g_out = 0x00ffff38,
+		.gpio_b = 0x00
+	},
+	{
+		.ioif = if_par_0,
+		.groups = group_a,
+		.gpio_g_in =  0x0000ff3e,
+		.gpio_g_out = 0x0000ff3e,
+		.gpio_b = 0x00
+	},
+	{
+		.ioif = if_par_1,
+		.groups = group_d,
+		.gpio_g_in =  0x3eff0000,
+		.gpio_g_out = 0x3eff0000,
+		.gpio_b = 0x00
+	},
+	{
+		.ioif = if_par_w,
+		.groups = group_a | group_d,
+		.gpio_g_in =  0x00ffff3e,
+		.gpio_g_out = 0x00ffff3e,
+		.gpio_b = 0x00
+	},
+	{
+		.ioif = if_scsi8_0,
+		.groups = group_a | group_b | group_f, /* if_scsi8_0 and if_scsi8_1
+							  can be used simultaneously */
+		.gpio_g_in =  0x0000ffff,
+		.gpio_g_out = 0x0000ffff,
+		.gpio_b = 0x10
+	},
+	{
+		.ioif = if_scsi8_1,
+		.groups = group_c | group_d | group_f, /* if_scsi8_0 and if_scsi8_1
+							  can be used simultaneously */
+		.gpio_g_in =  0xffff0000,
+		.gpio_g_out = 0xffff0000,
+		.gpio_b = 0x80
+	},
+	{
+		.ioif = if_scsi_w,
+		.groups = group_a | group_b | group_d | group_f,
+		.gpio_g_in =  0x01ffffff,
+		.gpio_g_out = 0x07ffffff,
+		.gpio_b = 0x80
+	},
+	{
+		.ioif = if_ata,
+		.groups = group_a | group_b | group_c | group_d,
+		.gpio_g_in =  0xf9ffffff,
+		.gpio_g_out = 0xffffffff,
+		.gpio_b = 0x80
+	},
+	{
+		.ioif = if_csp,
+		.groups = group_f, /* if_csp and if_i2c can be used simultaneously */
+		.gpio_g_in =  0x00000000,
+		.gpio_g_out = 0x00000000,
+		.gpio_b = 0xfc
+	},
+	{
+		.ioif = if_i2c,
+		.groups = group_f, /* if_csp and if_i2c can be used simultaneously */
+		.gpio_g_in =  0x00000000,
+		.gpio_g_out = 0x00000000,
+		.gpio_b = 0x03
+	},
+	{
+		.ioif = if_usb_1,
+		.groups = group_e | group_f,
+		.gpio_g_in =  0x00000000,
+		.gpio_g_out = 0x00000000,
+		.gpio_b = 0x2c
+	},
+	{
+		.ioif = if_usb_2,
+		.groups = group_d,
+		.gpio_g_in =  0x0e000000,
+		.gpio_g_out = 0x3c000000,
+		.gpio_b = 0x00
+	},
+	/* GPIO pins */
+	{
+		.ioif = if_gpio_grp_a,
+		.groups = group_a,
+		.gpio_g_in =  0x0000ff3f,
+		.gpio_g_out = 0x0000ff3f,
+		.gpio_b = 0x00
+	},
+	{
+		.ioif = if_gpio_grp_b,
+		.groups = group_b,
+		.gpio_g_in =  0x000000c0,
+		.gpio_g_out = 0x000000c0,
+		.gpio_b = 0x00
+	},
+	{
+		.ioif = if_gpio_grp_c,
+		.groups = group_c,
+		.gpio_g_in =  0xc0000000,
+		.gpio_g_out = 0xc0000000,
+		.gpio_b = 0x00
+	},
+	{
+		.ioif = if_gpio_grp_d,
+		.groups = group_d,
+		.gpio_g_in =  0x3fff0000,
+		.gpio_g_out = 0x3fff0000,
+		.gpio_b = 0x00
+	},
+	{
+		.ioif = if_gpio_grp_e,
+		.groups = group_e,
+		.gpio_g_in =  0x00000000,
+		.gpio_g_out = 0x00000000,
+		.gpio_b = 0x00
+	},
+	{
+		.ioif = if_gpio_grp_f,
+		.groups = group_f,
+		.gpio_g_in =  0x00000000,
+		.gpio_g_out = 0x00000000,
+		.gpio_b = 0xff
+	}
+	/* Array end */
+};
+
+static struct watcher *watchers = NULL;
+
+static unsigned int gpio_in_pins =  0xffffffff;
+static unsigned int gpio_out_pins = 0xffffffff;
+static unsigned char gpio_pb_pins = 0xff;
+static unsigned char gpio_pa_pins = 0xff;
+
+static enum cris_io_interface gpio_pa_owners[8];
+static enum cris_io_interface gpio_pb_owners[8];
+static enum cris_io_interface gpio_pg_owners[32];
+
+static int cris_io_interface_init(void);
+
+static unsigned char clear_group_from_set(const unsigned char groups, struct if_group *group)
+{
+	return (groups & ~group->group);
+}
+
+
+static struct if_group *get_group(const unsigned char groups)
+{
+	int i;
+	for (i = 0; i < sizeof(if_groups)/sizeof(struct if_group); i++) {
+		if (groups & if_groups[i].group) {
+			return &if_groups[i];
+		}
+	}
+	return NULL;
+}
+
+
+static void notify_watchers(void)
+{
+	struct watcher *w = watchers;
+
+	DBG(printk("io_interface_mux: notifying watchers\n"));
+
+	while (NULL != w) {
+		w->notify((const unsigned int)gpio_in_pins,
+			  (const unsigned int)gpio_out_pins,
+			  (const unsigned char)gpio_pa_pins,
+			  (const unsigned char)gpio_pb_pins);
+		w = w->next;
+	}
+}
+
+
+int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id)
+{
+	int set_gen_config = 0;
+	int set_gen_config_ii = 0;
+	unsigned long int gens;
+	unsigned long int gens_ii;
+	struct if_group *grp;
+	unsigned char group_set;
+	unsigned long flags;
+
+	(void)cris_io_interface_init();
+
+	DBG(printk("cris_request_io_interface(%d, \"%s\")\n", ioif, device_id));
+
+	if ((ioif >= if_max_interfaces) || (ioif < 0)) {
+		printk(KERN_CRIT "cris_request_io_interface: Bad interface %u submitted for %s\n",
+		       ioif,
+		       device_id);
+		return -EINVAL;
+	}
+
+	local_irq_save(flags);
+
+	if (interfaces[ioif].used) {
+		local_irq_restore(flags);
+		printk(KERN_CRIT "cris_io_interface: Cannot allocate interface for %s, in use by %s\n",
+		       device_id,
+		       interfaces[ioif].owner);
+		return -EBUSY;
+	}
+
+	/* Check that all required groups are free before allocating, */
+	group_set = interfaces[ioif].groups;
+	while (NULL != (grp = get_group(group_set))) {
+		if (grp->used) {
+			if (grp->group == group_f) {
+				if ((if_sync_serial_1 ==  ioif) ||
+				    (if_sync_serial_3 ==  ioif)) {
+					if ((grp->owner != if_sync_serial_1) &&
+					    (grp->owner != if_sync_serial_3)) {
+						local_irq_restore(flags);
+						return -EBUSY;
+					}
+				} else if ((if_scsi8_0 == ioif) ||
+					   (if_scsi8_1 == ioif)) {
+					if ((grp->owner != if_scsi8_0) &&
+					    (grp->owner != if_scsi8_1)) {
+						local_irq_restore(flags);
+						return -EBUSY;
+					}
+				}
+			} else {
+				local_irq_restore(flags);
+				return -EBUSY;
+			}
+		}
+		group_set = clear_group_from_set(group_set, grp);
+	}
+
+	/* Are the required GPIO pins available too? */
+	if (((interfaces[ioif].gpio_g_in & gpio_in_pins) != interfaces[ioif].gpio_g_in) ||
+	    ((interfaces[ioif].gpio_g_out & gpio_out_pins) != interfaces[ioif].gpio_g_out) ||
+	    ((interfaces[ioif].gpio_b & gpio_pb_pins) != interfaces[ioif].gpio_b)) {
+		printk(KERN_CRIT "cris_request_io_interface: Could not get required pins for interface %u\n",
+		       ioif);
+		return -EBUSY;
+	}
+
+	/* All needed I/O pins and pin groups are free, allocate. */
+	group_set = interfaces[ioif].groups;
+	while (NULL != (grp = get_group(group_set))) {
+		grp->used = 1;
+		grp->owner = ioif;
+		group_set = clear_group_from_set(group_set, grp);
+	}
+
+	gens = genconfig_shadow;
+	gens_ii = gen_config_ii_shadow;
+
+	set_gen_config = 1;
+	switch (ioif)
+	{
+	/* Begin Non-multiplexed interfaces */
+	case if_eth:
+		/* fall through */
+	case if_serial_0:
+		set_gen_config = 0;
+		break;
+	/* End Non-multiplexed interfaces */
+	case if_serial_1:
+		set_gen_config_ii = 1;
+		SETS(gens_ii, R_GEN_CONFIG_II, sermode1, async);
+		break;
+	case if_serial_2:
+		SETS(gens, R_GEN_CONFIG, ser2, select);
+		break;
+	case if_serial_3:
+		SETS(gens, R_GEN_CONFIG, ser3, select);
+		set_gen_config_ii = 1;
+		SETS(gens_ii, R_GEN_CONFIG_II, sermode3, async);
+		break;
+	case if_sync_serial_1:
+		set_gen_config_ii = 1;
+		SETS(gens_ii, R_GEN_CONFIG_II, sermode1, sync);
+		break;
+	case if_sync_serial_3:
+		SETS(gens, R_GEN_CONFIG, ser3, select);
+		set_gen_config_ii = 1;
+		SETS(gens_ii, R_GEN_CONFIG_II, sermode3, sync);
+		break;
+	case if_shared_ram:
+		SETS(gens, R_GEN_CONFIG, mio, select);
+		break;
+	case if_shared_ram_w:
+		SETS(gens, R_GEN_CONFIG, mio_w, select);
+		break;
+	case if_par_0:
+		SETS(gens, R_GEN_CONFIG, par0, select);
+		break;
+	case if_par_1:
+		SETS(gens, R_GEN_CONFIG, par1, select);
+		break;
+	case if_par_w:
+		SETS(gens, R_GEN_CONFIG, par0, select);
+		SETS(gens, R_GEN_CONFIG, par_w, select);
+		break;
+	case if_scsi8_0:
+		SETS(gens, R_GEN_CONFIG, scsi0, select);
+		break;
+	case if_scsi8_1:
+		SETS(gens, R_GEN_CONFIG, scsi1, select);
+		break;
+	case if_scsi_w:
+		SETS(gens, R_GEN_CONFIG, scsi0, select);
+		SETS(gens, R_GEN_CONFIG, scsi0w, select);
+		break;
+	case if_ata:
+		SETS(gens, R_GEN_CONFIG, ata, select);
+		break;
+	case if_csp:
+		/* fall through */
+	case if_i2c:
+		set_gen_config = 0;
+		break;
+	case if_usb_1:
+		SETS(gens, R_GEN_CONFIG, usb1, select);
+		break;
+	case if_usb_2:
+		SETS(gens, R_GEN_CONFIG, usb2, select);
+		break;
+	case if_gpio_grp_a:
+		/* GPIO groups are only accounted, don't do configuration changes. */
+		/* fall through */
+	case if_gpio_grp_b:
+		/* fall through */
+	case if_gpio_grp_c:
+		/* fall through */
+	case if_gpio_grp_d:
+		/* fall through */
+	case if_gpio_grp_e:
+		/* fall through */
+	case if_gpio_grp_f:
+		set_gen_config = 0;
+		break;
+	default:
+		panic("cris_request_io_interface: Bad interface %u submitted for %s\n",
+		      ioif,
+		      device_id);
+	}
+
+	interfaces[ioif].used = 1;
+	interfaces[ioif].owner = (char*)device_id;
+
+	if (set_gen_config) {
+		volatile int i;
+		genconfig_shadow = gens;
+		*R_GEN_CONFIG = genconfig_shadow;
+		/* Wait 12 cycles before doing any DMA command */
+		for(i = 6; i > 0; i--)
+			nop();
+	}
+	if (set_gen_config_ii) {
+		gen_config_ii_shadow = gens_ii;
+		*R_GEN_CONFIG_II = gen_config_ii_shadow;
+	}
+
+	DBG(printk("GPIO pins: available before: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
+		   gpio_in_pins, gpio_out_pins, gpio_pb_pins));
+	DBG(printk("grabbing pins: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
+		   interfaces[ioif].gpio_g_in,
+		   interfaces[ioif].gpio_g_out,
+		   interfaces[ioif].gpio_b));
+
+	gpio_in_pins &= ~interfaces[ioif].gpio_g_in;
+	gpio_out_pins &= ~interfaces[ioif].gpio_g_out;
+	gpio_pb_pins &= ~interfaces[ioif].gpio_b;
+
+	DBG(printk("GPIO pins: available after: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
+		   gpio_in_pins, gpio_out_pins, gpio_pb_pins));
+
+	local_irq_restore(flags);
+
+	notify_watchers();
+
+	return 0;
+}
+
+
+void cris_free_io_interface(enum cris_io_interface ioif)
+{
+	struct if_group *grp;
+	unsigned char group_set;
+	unsigned long flags;
+
+	(void)cris_io_interface_init();
+
+	if ((ioif >= if_max_interfaces) || (ioif < 0)) {
+		printk(KERN_CRIT "cris_free_io_interface: Bad interface %u\n",
+		       ioif);
+		return;
+	}
+	local_irq_save(flags);
+	if (!interfaces[ioif].used) {
+		printk(KERN_CRIT "cris_free_io_interface: Freeing free interface %u\n",
+		       ioif);
+		local_irq_restore(flags);
+		return;
+	}
+	group_set = interfaces[ioif].groups;
+	while (NULL != (grp = get_group(group_set))) {
+		if (grp->group == group_f) {
+			switch (ioif)
+			{
+			case if_sync_serial_1:
+				if ((grp->owner == if_sync_serial_1) &&
+				    interfaces[if_sync_serial_3].used) {
+					grp->owner = if_sync_serial_3;
+				} else
+					grp->used = 0;
+				break;
+			case if_sync_serial_3:
+				if ((grp->owner == if_sync_serial_3) &&
+				    interfaces[if_sync_serial_1].used) {
+					grp->owner = if_sync_serial_1;
+				} else
+					grp->used = 0;
+				break;
+			case if_scsi8_0:
+				if ((grp->owner == if_scsi8_0) &&
+				    interfaces[if_scsi8_1].used) {
+					grp->owner = if_scsi8_1;
+				} else
+					grp->used = 0;
+				break;
+			case if_scsi8_1:
+				if ((grp->owner == if_scsi8_1) &&
+				    interfaces[if_scsi8_0].used) {
+					grp->owner = if_scsi8_0;
+				} else
+					grp->used = 0;
+				break;
+			default:
+				grp->used = 0;
+			}
+		} else {
+			grp->used = 0;
+		}
+		group_set = clear_group_from_set(group_set, grp);
+	}
+	interfaces[ioif].used = 0;
+	interfaces[ioif].owner = NULL;
+
+	DBG(printk("GPIO pins: available before: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
+		   gpio_in_pins, gpio_out_pins, gpio_pb_pins));
+	DBG(printk("freeing pins: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
+		   interfaces[ioif].gpio_g_in,
+		   interfaces[ioif].gpio_g_out,
+		   interfaces[ioif].gpio_b));
+
+	gpio_in_pins |= interfaces[ioif].gpio_g_in;
+	gpio_out_pins |= interfaces[ioif].gpio_g_out;
+	gpio_pb_pins |= interfaces[ioif].gpio_b;
+
+	DBG(printk("GPIO pins: available after: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
+		   gpio_in_pins, gpio_out_pins, gpio_pb_pins));
+
+	local_irq_restore(flags);
+
+	notify_watchers();
+}
+
+/* Create a bitmask from bit 0 (inclusive) to bit stop_bit
+   (non-inclusive).  stop_bit == 0 returns 0x0 */
+static inline unsigned int create_mask(const unsigned stop_bit)
+{
+	/* Avoid overflow */
+	if (stop_bit >= 32) {
+		return 0xffffffff;
+	}
+	return (1<<stop_bit)-1;
+}
+
+
+/* port can be 'a', 'b' or 'g' */
+int cris_io_interface_allocate_pins(const enum cris_io_interface ioif,
+				    const char port,
+				    const unsigned start_bit,
+				    const unsigned stop_bit)
+{
+	unsigned int i;
+	unsigned int mask = 0;
+	unsigned int tmp_mask;
+	unsigned long int flags;
+	enum cris_io_interface *owners;
+
+	(void)cris_io_interface_init();
+
+	DBG(printk("cris_io_interface_allocate_pins: if=%d port=%c start=%u stop=%u\n",
+		   ioif, port, start_bit, stop_bit));
+
+	if (!((start_bit <= stop_bit) &&
+	      ((((port == 'a') || (port == 'b')) && (stop_bit < 8)) ||
+	       ((port == 'g') && (stop_bit < 32))))) {
+		return -EINVAL;
+	}
+
+	mask = create_mask(stop_bit + 1);
+	tmp_mask = create_mask(start_bit);
+	mask &= ~tmp_mask;
+
+	DBG(printk("cris_io_interface_allocate_pins: port=%c start=%u stop=%u mask=0x%08x\n",
+		   port, start_bit, stop_bit, mask));
+
+	local_irq_save(flags);
+
+	switch (port) {
+	case 'a':
+		if ((gpio_pa_pins & mask) != mask) {
+			local_irq_restore(flags);
+			return -EBUSY;
+		}
+		owners = gpio_pa_owners;
+		gpio_pa_pins &= ~mask;
+		break;
+	case 'b':
+		if ((gpio_pb_pins & mask) != mask) {
+			local_irq_restore(flags);
+			return -EBUSY;
+		}
+		owners = gpio_pb_owners;
+		gpio_pb_pins &= ~mask;
+		break;
+	case 'g':
+		if (((gpio_in_pins & mask) != mask) ||
+		    ((gpio_out_pins & mask) != mask)) {
+			local_irq_restore(flags);
+			return -EBUSY;
+		}
+		owners = gpio_pg_owners;
+		gpio_in_pins &= ~mask;
+		gpio_out_pins &= ~mask;
+		break;
+	default:
+		local_irq_restore(flags);
+		return -EINVAL;
+	}
+
+	for (i = start_bit; i <= stop_bit; i++) {
+		owners[i] = ioif;
+	}
+	local_irq_restore(flags);
+
+	notify_watchers();
+	return 0;
+}
+
+
+/* port can be 'a', 'b' or 'g' */
+int cris_io_interface_free_pins(const enum cris_io_interface ioif,
+                                const char port,
+                                const unsigned start_bit,
+                                const unsigned stop_bit)
+{
+	unsigned int i;
+	unsigned int mask = 0;
+	unsigned int tmp_mask;
+	unsigned long int flags;
+	enum cris_io_interface *owners;
+
+	(void)cris_io_interface_init();
+
+	if (!((start_bit <= stop_bit) &&
+	      ((((port == 'a') || (port == 'b')) && (stop_bit < 8)) ||
+	       ((port == 'g') && (stop_bit < 32))))) {
+		return -EINVAL;
+	}
+
+	mask = create_mask(stop_bit + 1);
+	tmp_mask = create_mask(start_bit);
+	mask &= ~tmp_mask;
+
+	DBG(printk("cris_io_interface_free_pins: port=%c start=%u stop=%u mask=0x%08x\n",
+		   port, start_bit, stop_bit, mask));
+
+	local_irq_save(flags);
+
+	switch (port) {
+	case 'a':
+		if ((~gpio_pa_pins & mask) != mask) {
+			local_irq_restore(flags);
+			printk(KERN_CRIT "cris_io_interface_free_pins: Freeing free pins");
+		}
+		owners = gpio_pa_owners;
+		break;
+	case 'b':
+		if ((~gpio_pb_pins & mask) != mask) {
+			local_irq_restore(flags);
+			printk(KERN_CRIT "cris_io_interface_free_pins: Freeing free pins");
+		}
+		owners = gpio_pb_owners;
+		break;
+	case 'g':
+		if (((~gpio_in_pins & mask) != mask) ||
+		    ((~gpio_out_pins & mask) != mask)) {
+			local_irq_restore(flags);
+			printk(KERN_CRIT "cris_io_interface_free_pins: Freeing free pins");
+		}
+		owners = gpio_pg_owners;
+		break;
+	default:
+		owners = NULL; /* Cannot happen. Shut up, gcc! */
+	}
+
+	for (i = start_bit; i <= stop_bit; i++) {
+		if (owners[i] != ioif) {
+			printk(KERN_CRIT "cris_io_interface_free_pins: Freeing unowned pins");
+		}
+	}
+
+	/* All was ok, change data. */
+	switch (port) {
+	case 'a':
+		gpio_pa_pins |= mask;
+		break;
+	case 'b':
+		gpio_pb_pins |= mask;
+		break;
+	case 'g':
+		gpio_in_pins |= mask;
+		gpio_out_pins |= mask;
+		break;
+	}
+
+	for (i = start_bit; i <= stop_bit; i++) {
+		owners[i] = if_unclaimed;
+	}
+	local_irq_restore(flags);
+	notify_watchers();
+
+        return 0;
+}
+
+
+int cris_io_interface_register_watcher(void (*notify)(const unsigned int gpio_in_available,
+                                                      const unsigned int gpio_out_available,
+                                                      const unsigned char pa_available,
+                                                      const unsigned char pb_available))
+{
+	struct watcher *w;
+
+	(void)cris_io_interface_init();
+
+	if (NULL == notify) {
+		return -EINVAL;
+	}
+	w = kmalloc(sizeof(*w), GFP_KERNEL);
+	if (!w) {
+		return -ENOMEM;
+	}
+	w->notify = notify;
+	w->next = watchers;
+	watchers = w;
+
+	w->notify((const unsigned int)gpio_in_pins,
+		  (const unsigned int)gpio_out_pins,
+		  (const unsigned char)gpio_pa_pins,
+		  (const unsigned char)gpio_pb_pins);
+
+	return 0;
+}
+
+void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available,
+						     const unsigned int gpio_out_available,
+                                                     const unsigned char pa_available,
+						     const unsigned char pb_available))
+{
+	struct watcher *w = watchers, *prev = NULL;
+
+	(void)cris_io_interface_init();
+
+	while ((NULL != w) && (w->notify != notify)){
+		prev = w;
+		w = w->next;
+	}
+	if (NULL != w) {
+		if (NULL != prev) {
+			prev->next = w->next;
+		} else {
+			watchers = w->next;
+		}
+		kfree(w);
+		return;
+	}
+	printk(KERN_WARNING "cris_io_interface_delete_watcher: Deleting unknown watcher 0x%p\n", notify);
+}
+
+
+static int cris_io_interface_init(void)
+{
+	static int first = 1;
+	int i;
+
+	if (!first) {
+		return 0;
+	}
+	first = 0;
+
+	for (i = 0; i<8; i++) {
+		gpio_pa_owners[i] = if_unclaimed;
+		gpio_pb_owners[i] = if_unclaimed;
+		gpio_pg_owners[i] = if_unclaimed;
+	}
+	for (; i<32; i++) {
+		gpio_pg_owners[i] = if_unclaimed;
+	}
+	return 0;
+}
+
+
+module_init(cris_io_interface_init);
+
+
+EXPORT_SYMBOL(cris_request_io_interface);
+EXPORT_SYMBOL(cris_free_io_interface);
+EXPORT_SYMBOL(cris_io_interface_allocate_pins);
+EXPORT_SYMBOL(cris_io_interface_free_pins);
+EXPORT_SYMBOL(cris_io_interface_register_watcher);
+EXPORT_SYMBOL(cris_io_interface_delete_watcher);
diff --git a/arch/cris/arch-v10/kernel/irq.c b/arch/cris/arch-v10/kernel/irq.c
index b2f16d6fc87..4b368a12201 100644
--- a/arch/cris/arch-v10/kernel/irq.c
+++ b/arch/cris/arch-v10/kernel/irq.c
@@ -1,4 +1,4 @@
-/* $Id: irq.c,v 1.2 2004/06/09 05:30:27 starvik Exp $
+/* $Id: irq.c,v 1.4 2005/01/04 12:22:28 starvik Exp $
  *
  *	linux/arch/cris/kernel/irq.c
  *
@@ -12,11 +12,13 @@
  */
 
 #include <asm/irq.h>
+#include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/config.h>
 
-irqvectptr irq_shortcuts[NR_IRQS]; /* vector of shortcut jumps after the irq prologue */
+#define mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr));
+#define unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr));
 
 /* don't use set_int_vector, it bypasses the linux interrupt handlers. it is
  * global just so that the kernel gdb can use it.
@@ -102,41 +104,52 @@ static void (*interrupt[NR_IRQS])(void) = {
 	IRQ31_interrupt
 };
 
-static void (*bad_interrupt[NR_IRQS])(void) = {
-        NULL, NULL,
-	NULL, bad_IRQ3_interrupt,
-	bad_IRQ4_interrupt, bad_IRQ5_interrupt,
-	bad_IRQ6_interrupt, bad_IRQ7_interrupt,
-	bad_IRQ8_interrupt, bad_IRQ9_interrupt,
-	bad_IRQ10_interrupt, bad_IRQ11_interrupt,
-	bad_IRQ12_interrupt, bad_IRQ13_interrupt,
-	NULL, NULL,
-	bad_IRQ16_interrupt, bad_IRQ17_interrupt,
-	bad_IRQ18_interrupt, bad_IRQ19_interrupt,
-	bad_IRQ20_interrupt, bad_IRQ21_interrupt,
-	bad_IRQ22_interrupt, bad_IRQ23_interrupt,
-	bad_IRQ24_interrupt, bad_IRQ25_interrupt,
-	NULL, NULL, NULL, NULL, NULL,
-	bad_IRQ31_interrupt
-};
+static void enable_crisv10_irq(unsigned int irq);
+
+static unsigned int startup_crisv10_irq(unsigned int irq)
+{
+	enable_crisv10_irq(irq);
+	return 0;
+}
+
+#define shutdown_crisv10_irq	disable_crisv10_irq
 
-void arch_setup_irq(int irq)
+static void enable_crisv10_irq(unsigned int irq)
 {
-  set_int_vector(irq, interrupt[irq]);
+	unmask_irq(irq);
 }
 
-void arch_free_irq(int irq)
+static void disable_crisv10_irq(unsigned int irq)
 {
-  set_int_vector(irq, bad_interrupt[irq]);
+	mask_irq(irq);
 }
 
+static void ack_crisv10_irq(unsigned int irq)
+{
+}
+
+static void end_crisv10_irq(unsigned int irq)
+{
+}
+
+static struct hw_interrupt_type crisv10_irq_type = {
+	.typename =    "CRISv10",
+	.startup =     startup_crisv10_irq,
+	.shutdown =    shutdown_crisv10_irq,
+	.enable =      enable_crisv10_irq,
+	.disable =     disable_crisv10_irq,
+	.ack =         ack_crisv10_irq,
+	.end =         end_crisv10_irq,
+	.set_affinity = NULL
+};
+
 void weird_irq(void);
 void system_call(void);  /* from entry.S */
 void do_sigtrap(void); /* from entry.S */
 void gdb_handle_breakpoint(void); /* from entry.S */
 
 /* init_IRQ() is called by start_kernel and is responsible for fixing IRQ masks and
-   setting the irq vector table to point to bad_interrupt ptrs.
+   setting the irq vector table.
 */
 
 void __init
@@ -154,14 +167,15 @@ init_IRQ(void)
 
 	*R_VECT_MASK_CLR = 0xffffffff;
 
-	/* clear the shortcut entry points */
-
-	for(i = 0; i < NR_IRQS; i++)
-		irq_shortcuts[i] = NULL;
-        
         for (i = 0; i < 256; i++)
                etrax_irv->v[i] = weird_irq;
 
+	/* Initialize IRQ handler descriptiors. */
+	for(i = 2; i < NR_IRQS; i++) {
+		irq_desc[i].handler = &crisv10_irq_type;
+		set_int_vector(i, interrupt[i]);
+	}
+
         /* the entries in the break vector contain actual code to be
            executed by the associated break handler, rather than just a jump
            address. therefore we need to setup a default breakpoint handler
@@ -170,10 +184,6 @@ init_IRQ(void)
 	for (i = 0; i < 16; i++)
                 set_break_vector(i, do_sigtrap);
         
-	/* set all etrax irq's to the bad handlers */
-	for (i = 2; i < NR_IRQS; i++)
-		set_int_vector(i, bad_interrupt[i]);
-        
 	/* except IRQ 15 which is the multiple-IRQ handler on Etrax100 */
 
 	set_int_vector(15, multiple_interrupt);
diff --git a/arch/cris/arch-v10/kernel/kgdb.c b/arch/cris/arch-v10/kernel/kgdb.c
index 7d368c877ee..b72e6a91a63 100644
--- a/arch/cris/arch-v10/kernel/kgdb.c
+++ b/arch/cris/arch-v10/kernel/kgdb.c
@@ -18,6 +18,10 @@
 *! Jul 21 1999  Bjorn Wesen     eLinux port
 *!
 *! $Log: kgdb.c,v $
+*! Revision 1.6  2005/01/14 10:12:17  starvik
+*! KGDB on separate port.
+*! Console fixes from 2.4.
+*!
 *! Revision 1.5  2004/10/07 13:59:08  starvik
 *! Corrected call to set_int_vector
 *!
@@ -71,7 +75,7 @@
 *!
 *!---------------------------------------------------------------------------
 *!
-*! $Id: kgdb.c,v 1.5 2004/10/07 13:59:08 starvik Exp $
+*! $Id: kgdb.c,v 1.6 2005/01/14 10:12:17 starvik Exp $
 *!
 *! (C) Copyright 1999, Axis Communications AB, LUND, SWEDEN
 *!
@@ -225,6 +229,7 @@
 #include <linux/kernel.h>
 #include <linux/delay.h>
 #include <linux/linkage.h>
+#include <linux/reboot.h>
 
 #include <asm/setup.h>
 #include <asm/ptrace.h>
@@ -1344,12 +1349,11 @@ handle_exception (int sigval)
 	}
 }
 
-/* The jump is to the address 0x00000002. Performs a complete re-start
-   from scratch. */
+/* Performs a complete re-start from scratch. */
 static void
 kill_restart ()
 {
-	__asm__ volatile ("jump 2");
+	machine_restart("");
 }
 
 /********************************** Breakpoint *******************************/
@@ -1506,6 +1510,11 @@ kgdb_handle_serial:
   bne goback
   nop
 
+  move.d  [reg+0x5E], $r10		; Get DCCR
+  btstq	   8, $r10			; Test the U-flag.
+  bmi	   goback
+  nop
+
 ;;
 ;; Handle the communication
 ;;
diff --git a/arch/cris/arch-v10/kernel/process.c b/arch/cris/arch-v10/kernel/process.c
index 87ff3779082..69e28b4057e 100644
--- a/arch/cris/arch-v10/kernel/process.c
+++ b/arch/cris/arch-v10/kernel/process.c
@@ -1,4 +1,4 @@
-/* $Id: process.c,v 1.9 2004/10/19 13:07:37 starvik Exp $
+/* $Id: process.c,v 1.12 2004/12/27 11:18:32 starvik Exp $
  * 
  *  linux/arch/cris/kernel/process.c
  *
@@ -101,6 +101,7 @@ int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
 	regs.r11 = (unsigned long)fn;
 	regs.r12 = (unsigned long)arg;
 	regs.irp = (unsigned long)kernel_thread_helper;
+	regs.dccr = 1 << I_DCCR_BITNR;
 
 	/* Ok, create the new process.. */
         return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
diff --git a/arch/cris/arch-v10/kernel/ptrace.c b/arch/cris/arch-v10/kernel/ptrace.c
index 581ecabaae5..130dd214e41 100644
--- a/arch/cris/arch-v10/kernel/ptrace.c
+++ b/arch/cris/arch-v10/kernel/ptrace.c
@@ -11,6 +11,7 @@
 #include <linux/ptrace.h>
 #include <linux/user.h>
 #include <linux/signal.h>
+#include <linux/security.h>
 
 #include <asm/uaccess.h>
 #include <asm/page.h>
@@ -86,9 +87,13 @@ sys_ptrace(long request, long pid, long addr, long data)
 	ret = -EPERM;
 	
 	if (request == PTRACE_TRACEME) {
+		/* are we already being traced? */
 		if (current->ptrace & PT_PTRACED)
 			goto out;
-
+		ret = security_ptrace(current->parent, current);
+		if (ret)
+			goto out;
+		/* set the ptrace bit in the process flags. */
 		current->ptrace |= PT_PTRACED;
 		ret = 0;
 		goto out;
@@ -207,7 +212,7 @@ sys_ptrace(long request, long pid, long addr, long data)
 		case PTRACE_KILL:
 			ret = 0;
 			
-			if (child->state == TASK_ZOMBIE)
+			if (child->exit_state == EXIT_ZOMBIE)
 				break;
 			
 			child->exit_code = SIGKILL;
diff --git a/arch/cris/arch-v10/kernel/shadows.c b/arch/cris/arch-v10/kernel/shadows.c
index 561a890a8e4..38fd44dfbc5 100644
--- a/arch/cris/arch-v10/kernel/shadows.c
+++ b/arch/cris/arch-v10/kernel/shadows.c
@@ -1,4 +1,4 @@
-/* $Id: shadows.c,v 1.1 2001/12/17 13:59:27 bjornw Exp $
+/* $Id: shadows.c,v 1.2 2004/12/13 12:21:51 starvik Exp $
  * 
  * Various shadow registers. Defines for these are in include/asm-etrax100/io.h
  */
@@ -6,6 +6,7 @@
 /* Shadows for internal Etrax-registers */
 
 unsigned long genconfig_shadow;
+unsigned long gen_config_ii_shadow;
 unsigned long port_g_data_shadow;
 unsigned char port_pa_dir_shadow;
 unsigned char port_pa_data_shadow;
diff --git a/arch/cris/arch-v10/kernel/traps.c b/arch/cris/arch-v10/kernel/traps.c
index da491f438a6..34a27ea2052 100644
--- a/arch/cris/arch-v10/kernel/traps.c
+++ b/arch/cris/arch-v10/kernel/traps.c
@@ -1,4 +1,4 @@
-/* $Id: traps.c,v 1.2 2003/07/04 08:27:41 starvik Exp $
+/* $Id: traps.c,v 1.4 2005/04/24 18:47:55 starvik Exp $
  *
  *  linux/arch/cris/arch-v10/traps.c
  *
@@ -16,6 +16,8 @@
 #include <asm/uaccess.h>
 #include <asm/arch/sv_addr_ag.h>
 
+extern int raw_printk(const char *fmt, ...);
+
 void 
 show_registers(struct pt_regs * regs)
 {
@@ -26,18 +28,18 @@ show_registers(struct pt_regs * regs)
 	   register.  */
 	unsigned long usp = rdusp();
 
-	printk("IRP: %08lx SRP: %08lx DCCR: %08lx USP: %08lx MOF: %08lx\n",
+	raw_printk("IRP: %08lx SRP: %08lx DCCR: %08lx USP: %08lx MOF: %08lx\n",
 	       regs->irp, regs->srp, regs->dccr, usp, regs->mof );
-	printk(" r0: %08lx  r1: %08lx   r2: %08lx  r3: %08lx\n",
+	raw_printk(" r0: %08lx  r1: %08lx   r2: %08lx  r3: %08lx\n",
 	       regs->r0, regs->r1, regs->r2, regs->r3);
-	printk(" r4: %08lx  r5: %08lx   r6: %08lx  r7: %08lx\n",
+	raw_printk(" r4: %08lx  r5: %08lx   r6: %08lx  r7: %08lx\n",
 	       regs->r4, regs->r5, regs->r6, regs->r7);
-	printk(" r8: %08lx  r9: %08lx  r10: %08lx r11: %08lx\n",
+	raw_printk(" r8: %08lx  r9: %08lx  r10: %08lx r11: %08lx\n",
 	       regs->r8, regs->r9, regs->r10, regs->r11);
-	printk("r12: %08lx r13: %08lx oR10: %08lx\n",
-	       regs->r12, regs->r13, regs->orig_r10);
-	printk("R_MMU_CAUSE: %08lx\n", (unsigned long)*R_MMU_CAUSE);
-	printk("Process %s (pid: %d, stackpage=%08lx)\n",
+	raw_printk("r12: %08lx r13: %08lx oR10: %08lx  sp: %08lx\n",
+	       regs->r12, regs->r13, regs->orig_r10, regs);
+	raw_printk("R_MMU_CAUSE: %08lx\n", (unsigned long)*R_MMU_CAUSE);
+	raw_printk("Process %s (pid: %d, stackpage=%08lx)\n",
 	       current->comm, current->pid, (unsigned long)current);
 
 	/*
@@ -53,7 +55,7 @@ show_registers(struct pt_regs * regs)
 		if (usp != 0)
 			show_stack (NULL, NULL);
 
-                printk("\nCode: ");
+                raw_printk("\nCode: ");
                 if(regs->irp < PAGE_OFFSET)
                         goto bad;
 
@@ -70,16 +72,16 @@ show_registers(struct pt_regs * regs)
                         unsigned char c;
                         if(__get_user(c, &((unsigned char*)regs->irp)[i])) {
 bad:
-                                printk(" Bad IP value.");
+                                raw_printk(" Bad IP value.");
                                 break;
                         }
 
 			if (i == 0)
-			  printk("(%02x) ", c);
+			  raw_printk("(%02x) ", c);
 			else
-			  printk("%02x ", c);
+			  raw_printk("%02x ", c);
                 }
-		printk("\n");
+		raw_printk("\n");
         }
 }
 
@@ -121,7 +123,7 @@ die_if_kernel(const char * str, struct pt_regs * regs, long err)
 	stop_watchdog();
 #endif
 
-	printk("%s: %04lx\n", str, err & 0xffff);
+	raw_printk("%s: %04lx\n", str, err & 0xffff);
 
 	show_registers(regs);
 
@@ -130,3 +132,8 @@ die_if_kernel(const char * str, struct pt_regs * regs, long err)
 #endif
 	do_exit(SIGSEGV);
 }
+
+void arch_enable_nmi(void)
+{
+  asm volatile("setf m");
+}
diff --git a/arch/cris/arch-v10/mm/fault.c b/arch/cris/arch-v10/mm/fault.c
index 6805cdb25a5..fe2615022b9 100644
--- a/arch/cris/arch-v10/mm/fault.c
+++ b/arch/cris/arch-v10/mm/fault.c
@@ -14,6 +14,7 @@
 #include <asm/uaccess.h>
 #include <asm/pgtable.h>
 #include <asm/arch/svinto.h>
+#include <asm/mmu_context.h>
 
 /* debug of low-level TLB reload */
 #undef DEBUG
@@ -24,8 +25,6 @@
 #define D(x)
 #endif
 
-extern volatile pgd_t *current_pgd;
-
 extern const struct exception_table_entry
 	*search_exception_tables(unsigned long addr);
 
@@ -46,7 +45,7 @@ handle_mmu_bus_fault(struct pt_regs *regs)
 	int page_id;
 	int acc, inv;
 #endif
-	pgd_t* pgd = (pgd_t*)current_pgd;
+	pgd_t* pgd = (pgd_t*)per_cpu(current_pgd, smp_processor_id());
 	pmd_t *pmd;
 	pte_t pte;
 	int miss, we, writeac;
@@ -94,24 +93,3 @@ handle_mmu_bus_fault(struct pt_regs *regs)
 	*R_TLB_LO = pte_val(pte);
 	local_irq_restore(flags);
 }
-
-/* Called from arch/cris/mm/fault.c to find fixup code. */
-int
-find_fixup_code(struct pt_regs *regs)
-{
-	const struct exception_table_entry *fixup;
-
-	if ((fixup = search_exception_tables(regs->irp)) != 0) {
-		/* Adjust the instruction pointer in the stackframe. */
-		regs->irp = fixup->fixup;
-		
-		/* 
-		 * Don't return by restoring the CPU state, so switch
-		 * frame-type. 
-		 */
-		regs->frametype = CRIS_FRAME_NORMAL;
-		return 1;
-	}
-
-	return 0;
-}
diff --git a/arch/cris/arch-v10/mm/init.c b/arch/cris/arch-v10/mm/init.c
index a9f975a9cfb..ff3481e76dd 100644
--- a/arch/cris/arch-v10/mm/init.c
+++ b/arch/cris/arch-v10/mm/init.c
@@ -42,7 +42,7 @@ paging_init(void)
 	 *  switch_mm)
 	 */
 
-	current_pgd = init_mm.pgd;
+	per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd;
 
 	/* initialise the TLB (tlb.c) */
 
diff --git a/arch/cris/arch-v10/mm/tlb.c b/arch/cris/arch-v10/mm/tlb.c
index 9d06125ff5a..70a5523eff7 100644
--- a/arch/cris/arch-v10/mm/tlb.c
+++ b/arch/cris/arch-v10/mm/tlb.c
@@ -139,53 +139,6 @@ flush_tlb_page(struct vm_area_struct *vma,
 	local_irq_restore(flags);
 }
 
-/* invalidate a page range */
-
-void
-flush_tlb_range(struct vm_area_struct *vma, 
-		unsigned long start,
-		unsigned long end)
-{
-	struct mm_struct *mm = vma->vm_mm;
-	int page_id = mm->context.page_id;
-	int i;
-	unsigned long flags;
-
-	D(printk("tlb: flush range %p<->%p in context %d (%p)\n",
-		 start, end, page_id, mm));
-
-	if(page_id == NO_CONTEXT)
-		return;
-
-	start &= PAGE_MASK;  /* probably not necessary */
-	end &= PAGE_MASK;    /* dito */
-
-	/* invalidate those TLB entries that match both the mm context
-	 * and the virtual address range
-	 */
-
-	local_save_flags(flags);
-	local_irq_disable();
-	for(i = 0; i < NUM_TLB_ENTRIES; i++) {
-		unsigned long tlb_hi, vpn;
-		*R_TLB_SELECT = IO_FIELD(R_TLB_SELECT, index, i);
-		tlb_hi = *R_TLB_HI;
-		vpn = tlb_hi & PAGE_MASK;
-		if (IO_EXTRACT(R_TLB_HI, page_id, tlb_hi) == page_id &&
-		    vpn >= start && vpn < end) {
-			*R_TLB_HI = ( IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) |
-				      IO_FIELD(R_TLB_HI, vpn,     i & 0xf ) );
-			
-			*R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no  ) |
-				      IO_STATE(R_TLB_LO, valid, no  ) |
-				      IO_STATE(R_TLB_LO, kernel,no  ) |
-				      IO_STATE(R_TLB_LO, we,    no  ) |
-				      IO_FIELD(R_TLB_LO, pfn,   0   ) );
-		}
-	}
-	local_irq_restore(flags);
-}
-
 /* dump the entire TLB for debug purposes */
 
 #if 0
@@ -237,7 +190,7 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
 	 * the pgd.
 	 */
 
-	current_pgd = next->pgd;
+	per_cpu(current_pgd, smp_processor_id()) = next->pgd;
 
 	/* switch context in the MMU */
 	
diff --git a/arch/cris/arch-v32/Kconfig b/arch/cris/arch-v32/Kconfig
new file mode 100644
index 00000000000..22f0ddc04c5
--- /dev/null
+++ b/arch/cris/arch-v32/Kconfig
@@ -0,0 +1,296 @@
+config ETRAX_DRAM_VIRTUAL_BASE
+	hex
+	depends on ETRAX_ARCH_V32
+	default "c0000000"
+
+config ETRAX_LED1G
+	string "First green LED bit"
+	depends on ETRAX_ARCH_V32
+	default "PA3"
+	help
+	  Bit to use for the first green LED (network LED).
+	  Most Axis products use bit A3 here.
+
+config ETRAX_LED1R
+	string "First red LED bit"
+	depends on ETRAX_ARCH_V32
+	default "PA4"
+	help
+	  Bit to use for the first red LED (network LED).
+	  Most Axis products use bit A4 here.
+
+config ETRAX_LED2G
+	string "Second green LED bit"
+	depends on ETRAX_ARCH_V32
+	default "PA5"
+	help
+	  Bit to use for the first green LED (status LED).
+	  Most Axis products use bit A5 here.
+
+config ETRAX_LED2R
+	string "Second red LED bit"
+	depends on ETRAX_ARCH_V32
+	default "PA6"
+	help
+	  Bit to use for the first red LED (network LED).
+	  Most Axis products use bit A6 here.
+
+config ETRAX_LED3G
+	string "Third green LED bit"
+	depends on ETRAX_ARCH_V32
+	default "PA7"
+	help
+	  Bit to use for the first green LED (drive/power LED).
+	  Most Axis products use bit A7 here.
+
+config ETRAX_LED3R
+	string "Third red LED bit"
+	depends on ETRAX_ARCH_V32
+	default "PA7"
+	help
+	  Bit to use for the first red LED (drive/power LED).
+	  Most Axis products use bit A7 here.
+
+choice
+	prompt "Product debug-port"
+	depends on ETRAX_ARCH_V32
+	default ETRAX_DEBUG_PORT0
+
+config ETRAX_DEBUG_PORT0
+	bool "Serial-0"
+	help
+	  Choose a serial port for the ETRAX debug console.  Default to
+	  port 0.
+
+config ETRAX_DEBUG_PORT1
+	bool "Serial-1"
+	help
+	  Use serial port 1 for the console.
+
+config ETRAX_DEBUG_PORT2
+	bool "Serial-2"
+	help
+	  Use serial port 2 for the console.
+
+config ETRAX_DEBUG_PORT3
+	bool "Serial-3"
+	help
+	  Use serial port 3 for the console.
+
+config ETRAX_DEBUG_PORT_NULL
+	bool "disabled"
+	help
+	  Disable serial-port debugging.
+
+endchoice
+
+choice
+	prompt "Kernel GDB port"
+	depends on ETRAX_KGDB
+	default ETRAX_KGDB_PORT0
+	help
+	  Choose a serial port for kernel debugging.  NOTE: This port should
+	  not be enabled under Drivers for built-in interfaces (as it has its
+	  own initialization code) and should not be the same as the debug port.
+
+config ETRAX_KGDB_PORT0
+	bool "Serial-0"
+	help
+	  Use serial port 0 for kernel debugging.
+
+config ETRAX_KGDB_PORT1
+	bool "Serial-1"
+	help
+	  Use serial port 1 for kernel debugging.
+
+config ETRAX_KGDB_PORT2
+	bool "Serial-2"
+	help
+	  Use serial port 2 for kernel debugging.
+
+config ETRAX_KGDB_PORT3
+	bool "Serial-3"
+	help
+	  Use serial port 3 for kernel debugging.
+
+endchoice
+
+config ETRAX_MEM_GRP1_CONFIG
+	hex "MEM_GRP1_CONFIG"
+	depends on ETRAX_ARCH_V32
+	default "4044a"
+	help
+	  Waitstates for flash. The default value is suitable for the
+	  standard flashes used in axis products (120 ns).
+
+config ETRAX_MEM_GRP2_CONFIG
+	hex "MEM_GRP2_CONFIG"
+	depends on ETRAX_ARCH_V32
+	default "0"
+	help
+	  Waitstates for SRAM. 0 is a good choice for most Axis products.
+
+config ETRAX_MEM_GRP3_CONFIG
+	hex "MEM_GRP3_CONFIG"
+	depends on ETRAX_ARCH_V32
+	default "0"
+	help
+	  Waitstates for CSP0-3. 0 is a good choice for most Axis products.
+	  It may need to be changed if external devices such as extra
+	  register-mapped LEDs are used.
+
+config ETRAX_MEM_GRP4_CONFIG
+	hex "MEM_GRP4_CONFIG"
+	depends on ETRAX_ARCH_V32
+	default "0"
+	help
+	  Waitstates for CSP4-6. 0 is a good choice for most Axis products.
+
+config ETRAX_SDRAM_GRP0_CONFIG
+	hex "SDRAM_GRP0_CONFIG"
+	depends on ETRAX_ARCH_V32
+	default "336"
+	help
+	  SDRAM configuration for group 0. The value depends on the
+	  hardware configuration. The default value is suitable
+	  for 32 MB organized as two 16 bits chips (e.g. Axis
+	  part number 18550) connected as one 32 bit device (i.e. in
+	  the same group).
+
+config ETRAX_SDRAM_GRP1_CONFIG
+	hex "SDRAM_GRP1_CONFIG"
+	depends on ETRAX_ARCH_V32
+	default "0"
+	help
+	  SDRAM configuration for group 1. The defult value is 0
+	  because group 1 is not used in the default configuration,
+	  described in the help for SDRAM_GRP0_CONFIG.
+
+config ETRAX_SDRAM_TIMING
+	hex "SDRAM_TIMING"
+	depends on ETRAX_ARCH_V32
+	default "104a"
+	help
+	  SDRAM timing parameters. The default value is ok for
+	  most hardwares but large SDRAMs may require a faster
+	  refresh (a.k.a 8K refresh). The default value implies
+	  100MHz clock and SDR mode.
+
+config ETRAX_SDRAM_COMMAND
+	hex "SDRAM_COMMAND"
+	depends on ETRAX_ARCH_V32
+	default "0"
+	help
+	  SDRAM command. Should be 0 unless you really know what
+	  you are doing (may be != 0 for unusual address line
+	  mappings such as in a MCM)..
+
+config ETRAX_DEF_GIO_PA_OE
+	hex "GIO_PA_OE"
+	depends on ETRAX_ARCH_V32
+	default "1c"
+	help
+	  Configures the direction of general port A bits.  1 is out, 0 is in.
+	  This is often totally different depending on the product used.
+	  There are some guidelines though - if you know that only LED's are
+	  connected to port PA, then they are usually connected to bits 2-4
+	  and you can therefore use 1c.  On other boards which don't have the
+	  LED's at the general ports, these bits are used for all kinds of
+	  stuff.  If you don't know what to use, it is always safe to put all
+	  as inputs, although floating inputs isn't good.
+
+config ETRAX_DEF_GIO_PA_OUT
+	hex "GIO_PA_OUT"
+	depends on ETRAX_ARCH_V32
+	default "00"
+	help
+	  Configures the initial data for the general port A bits.  Most
+	  products should use 00 here.
+
+config ETRAX_DEF_GIO_PB_OE
+	hex "GIO_PB_OE"
+	depends on ETRAX_ARCH_V32
+	default "00000"
+	help
+	  Configures the direction of general port B bits.  1 is out, 0 is in.
+	  This is often totally different depending on the product used.
+	  There are some guidelines though - if you know that only LED's are
+	  connected to port PA, then they are usually connected to bits 2-4
+	  and you can therefore use 1c.  On other boards which don't have the
+	  LED's at the general ports, these bits are used for all kinds of
+	  stuff.  If you don't know what to use, it is always safe to put all
+	  as inputs, although floating inputs isn't good.
+
+config ETRAX_DEF_GIO_PB_OUT
+	hex "GIO_PB_OUT"
+	depends on ETRAX_ARCH_V32
+	default "00000"
+	help
+	  Configures the initial data for the general port B bits.  Most
+	  products should use 00000 here.
+
+config ETRAX_DEF_GIO_PC_OE
+	hex "GIO_PC_OE"
+	depends on ETRAX_ARCH_V32
+	default "00000"
+	help
+	  Configures the direction of general port C bits.  1 is out, 0 is in.
+	  This is often totally different depending on the product used.
+	  There are some guidelines though - if you know that only LED's are
+	  connected to port PA, then they are usually connected to bits 2-4
+	  and you can therefore use 1c.  On other boards which don't have the
+	  LED's at the general ports, these bits are used for all kinds of
+	  stuff.  If you don't know what to use, it is always safe to put all
+	  as inputs, although floating inputs isn't good.
+
+config ETRAX_DEF_GIO_PC_OUT
+	hex "GIO_PC_OUT"
+	depends on ETRAX_ARCH_V32
+	default "00000"
+	help
+	  Configures the initial data for the general port C bits.  Most
+	  products should use 00000 here.
+
+config ETRAX_DEF_GIO_PD_OE
+	hex "GIO_PD_OE"
+	depends on ETRAX_ARCH_V32
+	default "00000"
+	help
+	  Configures the direction of general port D bits.  1 is out, 0 is in.
+	  This is often totally different depending on the product used.
+	  There are some guidelines though - if you know that only LED's are
+	  connected to port PA, then they are usually connected to bits 2-4
+	  and you can therefore use 1c.  On other boards which don't have the
+	  LED's at the general ports, these bits are used for all kinds of
+	  stuff.  If you don't know what to use, it is always safe to put all
+	  as inputs, although floating inputs isn't good.
+
+config ETRAX_DEF_GIO_PD_OUT
+	hex "GIO_PD_OUT"
+	depends on ETRAX_ARCH_V32
+	default "00000"
+	help
+	  Configures the initial data for the general port D bits.  Most
+	  products should use 00000 here.
+
+config ETRAX_DEF_GIO_PE_OE
+	hex "GIO_PE_OE"
+	depends on ETRAX_ARCH_V32
+	default "00000"
+	help
+	  Configures the direction of general port E bits.  1 is out, 0 is in.
+	  This is often totally different depending on the product used.
+	  There are some guidelines though - if you know that only LED's are
+	  connected to port PA, then they are usually connected to bits 2-4
+	  and you can therefore use 1c.  On other boards which don't have the
+	  LED's at the general ports, these bits are used for all kinds of
+	  stuff.  If you don't know what to use, it is always safe to put all
+	  as inputs, although floating inputs isn't good.
+
+config ETRAX_DEF_GIO_PE_OUT
+	hex "GIO_PE_OUT"
+	depends on ETRAX_ARCH_V32
+	default "00000"
+	help
+	  Configures the initial data for the general port E bits.  Most
+	  products should use 00000 here.
diff --git a/arch/cris/arch-v32/boot/Makefile b/arch/cris/arch-v32/boot/Makefile
new file mode 100644
index 00000000000..26f293ab961
--- /dev/null
+++ b/arch/cris/arch-v32/boot/Makefile
@@ -0,0 +1,14 @@
+#
+# arch/cris/arch-v32/boot/Makefile
+#
+target = $(target_boot_dir)
+src    = $(src_boot_dir)
+
+zImage: compressed/vmlinuz
+
+compressed/vmlinuz: $(objtree)/vmlinux
+	@$(MAKE) -f $(src)/compressed/Makefile $(objtree)/vmlinuz
+
+clean:
+	rm -f zImage tools/build compressed/vmlinux.out
+	@$(MAKE) -f $(src)/compressed/Makefile clean
diff --git a/arch/cris/arch-v32/boot/compressed/Makefile b/arch/cris/arch-v32/boot/compressed/Makefile
new file mode 100644
index 00000000000..9f77eda914b
--- /dev/null
+++ b/arch/cris/arch-v32/boot/compressed/Makefile
@@ -0,0 +1,41 @@
+#
+# lx25/arch/cris/arch-v32/boot/compressed/Makefile
+#
+# create a compressed vmlinux image from the original vmlinux files and romfs
+#
+
+target = $(target_compressed_dir)
+src    = $(src_compressed_dir)
+
+CC = gcc-cris -mlinux -march=v32 -I $(TOPDIR)/include
+CFLAGS = -O2
+LD = gcc-cris -mlinux -march=v32 -nostdlib
+OBJCOPY = objcopy-cris
+OBJCOPYFLAGS = -O binary --remove-section=.bss
+OBJECTS = $(target)/head.o $(target)/misc.o
+
+# files to compress
+SYSTEM = $(objtree)/vmlinux.bin
+
+all: vmlinuz
+
+$(target)/decompress.bin: $(OBJECTS)
+	$(LD) -T $(src)/decompress.ld -o $(target)/decompress.o $(OBJECTS)
+	$(OBJCOPY) $(OBJCOPYFLAGS) $(target)/decompress.o $(target)/decompress.bin
+
+$(objtree)/vmlinuz: $(target) piggy.img $(target)/decompress.bin
+	cat $(target)/decompress.bin piggy.img > $(objtree)/vmlinuz
+	rm -f piggy.img
+	cp $(objtree)/vmlinuz $(src)
+
+$(target)/head.o: $(src)/head.S
+	$(CC) -D__ASSEMBLY__ -c $< -o $@
+
+# gzip the kernel image
+
+piggy.img: $(SYSTEM)
+	cat $(SYSTEM) | gzip -f -9 > piggy.img
+
+clean:
+	rm -f piggy.img $(objtree)/vmlinuz vmlinuz.o decompress.o decompress.bin $(OBJECTS)
+
diff --git a/arch/cris/arch-v32/boot/compressed/README b/arch/cris/arch-v32/boot/compressed/README
new file mode 100644
index 00000000000..e33691d15c5
--- /dev/null
+++ b/arch/cris/arch-v32/boot/compressed/README
@@ -0,0 +1,25 @@
+Creation of the self-extracting compressed kernel image (vmlinuz)
+-----------------------------------------------------------------
+$Id: README,v 1.1 2003/08/21 09:37:03 johana Exp $
+
+This can be slightly confusing because it's a process with many steps.
+
+The kernel object built by the arch/etrax100/Makefile, vmlinux, is split
+by that makefile into text and data binary files, vmlinux.text and
+vmlinux.data.
+
+Those files together with a ROM filesystem can be catted together and
+burned into a flash or executed directly at the DRAM origin.
+
+They can also be catted together and compressed with gzip, which is what
+happens in this makefile. Together they make up piggy.img.
+
+The decompressor is built into the file decompress.o. It is turned into
+the binary file decompress.bin, which is catted together with piggy.img
+into the file vmlinuz. It can be executed in an arbitrary place in flash.
+
+Be careful - it assumes some things about free locations in DRAM. It
+assumes the DRAM starts at 0x40000000 and that it is at least 8 MB,
+so it puts its code at 0x40700000, and initial stack at 0x40800000.
+
+-Bjorn
diff --git a/arch/cris/arch-v32/boot/compressed/decompress.ld b/arch/cris/arch-v32/boot/compressed/decompress.ld
new file mode 100644
index 00000000000..3c837feca3a
--- /dev/null
+++ b/arch/cris/arch-v32/boot/compressed/decompress.ld
@@ -0,0 +1,30 @@
+/*#OUTPUT_FORMAT(elf32-us-cris) */
+OUTPUT_ARCH (crisv32)
+
+MEMORY
+	{
+	dram : ORIGIN = 0x40700000,
+	       LENGTH = 0x00100000
+	}
+
+SECTIONS
+{
+	.text :
+	{
+		_stext = . ;
+		*(.text)
+		*(.rodata)
+		*(.rodata.*)
+		_etext = . ;
+	} > dram
+	.data :
+	{
+		*(.data)
+		_edata = . ;
+	} > dram
+	.bss :
+	{
+		*(.bss)
+		_end = ALIGN( 0x10 ) ;
+	} > dram
+}
diff --git a/arch/cris/arch-v32/boot/compressed/head.S b/arch/cris/arch-v32/boot/compressed/head.S
new file mode 100644
index 00000000000..0c55b83b828
--- /dev/null
+++ b/arch/cris/arch-v32/boot/compressed/head.S
@@ -0,0 +1,193 @@
+/*
+ *  Code that sets up the DRAM registers, calls the
+ *  decompressor to unpack the piggybacked kernel, and jumps.
+ *
+ *  Copyright (C) 1999 - 2003, Axis Communications AB
+ */
+
+#include <linux/config.h>
+#define ASSEMBLER_MACROS_ONLY
+#include <asm/arch/hwregs/asm/reg_map_asm.h>
+#include <asm/arch/hwregs/asm/gio_defs_asm.h>
+#include <asm/arch/hwregs/asm/config_defs_asm.h>
+
+#define RAM_INIT_MAGIC 0x56902387
+#define COMMAND_LINE_MAGIC 0x87109563
+
+	;; Exported symbols
+
+	.globl	input_data
+
+	.text
+start:
+	di
+
+	;; Start clocks for used blocks.
+	move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1
+	move.d [$r1], $r0
+	or.d   REG_STATE(config, rw_clk_ctrl, cpu, yes) | \
+	       REG_STATE(config, rw_clk_ctrl, bif, yes) | \
+	       REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0
+	move.d $r0, [$r1]
+
+	;; If booting from NAND flash we first have to copy some
+	;; data from NAND flash to internal RAM to get the code
+	;; that initializes the SDRAM. Lets copy 20 KB. This
+	;; code executes at 0x38010000 if booting from NAND and
+	;; we are guaranted that at least 0x200 bytes are good so
+	;; lets start from there. The first 8192 bytes in the nand
+	;; flash is spliced with zeroes and is thus 16384 bytes.
+	move.d 0x38010200, $r10
+	move.d 0x14200, $r11	; Start offset in NAND flash 0x10200 + 16384
+	move.d 0x5000, $r12	; Length of copy
+
+	;; Before this code the tools add a partitiontable so the PC
+	;; has an offset from the linked address.
+offset1:
+	lapcq  ., $r13		; get PC
+	add.d	first_copy_complete-offset1, $r13
+
+#include "../../lib/nand_init.S"
+
+first_copy_complete:
+	;; Initialze the DRAM registers.
+	cmp.d	RAM_INIT_MAGIC, $r8	; Already initialized?
+	beq	dram_init_finished
+	nop
+
+#include "../../lib/dram_init.S"
+
+dram_init_finished:
+	lapcq  ., $r13		; get PC
+	add.d	second_copy_complete-dram_init_finished, $r13
+
+	move.d REG_ADDR(config, regi_config, r_bootsel), $r0
+	move.d [$r0], $r0
+	and.d  REG_MASK(config, r_bootsel, boot_mode), $r0
+	cmp.d  REG_STATE(config, r_bootsel, boot_mode, nand), $r0
+	bne second_copy_complete ; No NAND boot
+	nop
+
+	;; Copy 2MB from NAND flash to SDRAM (at 2-4MB into the SDRAM)
+	move.d 0x40204000, $r10
+	move.d 0x8000, $r11
+	move.d 0x200000, $r12
+	ba copy_nand_to_ram
+	nop
+second_copy_complete:
+
+	;; Initiate the PA port.
+	move.d	CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0
+	move.d	REG_ADDR(gio, regi_gio, rw_pa_dout), $r1
+	move.d	$r0, [$r1]
+
+	move.d	CONFIG_ETRAX_DEF_GIO_PA_OE, $r0
+	move.d	REG_ADDR(gio, regi_gio, rw_pa_oe), $r1
+	move.d	$r0, [$r1]
+
+	;; Setup the stack to a suitably high address.
+	;; We assume 8 MB is the minimum DRAM and put
+	;; the SP at the top for now.
+
+	move.d	0x40800000, $sp
+
+	;; Figure out where the compressed piggyback image is
+	;; in the flash (since we wont try to copy it to DRAM
+	;; before unpacking). It is at _edata, but in flash.
+	;; Use (_edata - herami) as offset to the current PC.
+
+	move.d REG_ADDR(config, regi_config, r_bootsel), $r0
+	move.d [$r0], $r0
+	and.d  REG_MASK(config, r_bootsel, boot_mode), $r0
+	cmp.d  REG_STATE(config, r_bootsel, boot_mode, nand), $r0
+	beq hereami2
+	nop
+hereami:
+	lapcq	., $r5		; get PC
+	and.d	0x7fffffff, $r5	; strip any non-cache bit
+	move.d	$r5, $r0	; save for later - flash address of 'herami'
+	add.d	_edata, $r5
+	sub.d	hereami, $r5	; r5 = flash address of '_edata'
+	move.d	hereami, $r1	; destination
+	ba 2f
+	nop
+hereami2:
+	lapcq	., $r5		; get PC
+	and.d	0x00ffffff, $r5	; strip any non-cache bit
+	move.d  $r5, $r6
+	or.d    0x40200000, $r6
+	move.d	$r6, $r0	; save for later - flash address of 'herami'
+	add.d	_edata, $r5
+	sub.d	hereami2, $r5	; r5 = flash address of '_edata'
+	add.d   0x40200000, $r5
+	move.d	hereami2, $r1	; destination
+2:
+	;; Copy text+data to DRAM
+
+	move.d	_edata, $r2	; end destination
+1:	move.w	[$r0+], $r3
+	move.w	$r3, [$r1+]
+	cmp.d	$r2, $r1
+	bcs	1b
+	nop
+
+	move.d	input_data, $r0 ; for the decompressor
+	move.d	$r5, [$r0]	; for the decompressor
+
+	;; Clear the decompressors BSS (between _edata and _end)
+
+	moveq	0, $r0
+	move.d	_edata, $r1
+	move.d	_end, $r2
+1:	move.w	$r0, [$r1+]
+	cmp.d	$r2, $r1
+	bcs	1b
+	nop
+
+	;;  Save command line magic and address.
+	move.d	_cmd_line_magic, $r12
+	move.d  $r10, [$r12]
+	move.d	_cmd_line_addr, $r12
+	move.d  $r11, [$r12]
+
+	;; Do the decompression and save compressed size in _inptr
+
+	jsr	decompress_kernel
+	nop
+
+	;; Restore command line magic and address.
+	move.d  _cmd_line_magic, $r10
+	move.d  [$r10], $r10
+	move.d  _cmd_line_addr, $r11
+	move.d  [$r11], $r11
+
+	;; Put start address of root partition in r9 so the kernel can use it
+	;; when mounting from flash
+	move.d  input_data, $r0
+	move.d	[$r0], $r9		; flash address of compressed kernel
+	move.d  inptr, $r0
+	add.d	[$r0], $r9		; size of compressed kernel
+	cmp.d   0x40200000, $r9
+	blo	enter_kernel
+	nop
+	sub.d   0x40200000, $r9
+	add.d   0x4000, $r9
+
+enter_kernel:
+	;; Enter the decompressed kernel
+	move.d	RAM_INIT_MAGIC, $r8	; Tell kernel that DRAM is initialized
+	jump	0x40004000	; kernel is linked to this address
+	nop
+
+	.data
+
+input_data:
+	.dword	0		; used by the decompressor
+_cmd_line_magic:
+	.dword 0
+_cmd_line_addr:
+	.dword 0
+is_nand_boot:
+	.dword  0
+
+#include "../../lib/hw_settings.S"
diff --git a/arch/cris/arch-v32/boot/compressed/misc.c b/arch/cris/arch-v32/boot/compressed/misc.c
new file mode 100644
index 00000000000..54644238ed5
--- /dev/null
+++ b/arch/cris/arch-v32/boot/compressed/misc.c
@@ -0,0 +1,318 @@
+/*
+ * misc.c
+ *
+ * $Id: misc.c,v 1.8 2005/04/24 18:34:29 starvik Exp $
+ *
+ * This is a collection of several routines from gzip-1.0.3
+ * adapted for Linux.
+ *
+ * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994
+ * puts by Nick Holloway 1993, better puts by Martin Mares 1995
+ * adoptation for Linux/CRIS Axis Communications AB, 1999
+ *
+ */
+
+/* where the piggybacked kernel image expects itself to live.
+ * it is the same address we use when we network load an uncompressed
+ * image into DRAM, and it is the address the kernel is linked to live
+ * at by vmlinux.lds.S
+ */
+
+#define KERNEL_LOAD_ADR 0x40004000
+
+#include <linux/config.h>
+
+#include <linux/types.h>
+#include <asm/arch/hwregs/reg_rdwr.h>
+#include <asm/arch/hwregs/reg_map.h>
+#include <asm/arch/hwregs/ser_defs.h>
+
+/*
+ * gzip declarations
+ */
+
+#define OF(args)  args
+#define STATIC static
+
+void* memset(void* s, int c, size_t n);
+void* memcpy(void* __dest, __const void* __src,
+	     size_t __n);
+
+#define memzero(s, n)     memset ((s), 0, (n))
+
+
+typedef unsigned char  uch;
+typedef unsigned short ush;
+typedef unsigned long  ulg;
+
+#define WSIZE 0x8000		/* Window size must be at least 32k, */
+				/* and a power of two */
+
+static uch *inbuf;	     /* input buffer */
+static uch window[WSIZE];    /* Sliding window buffer */
+
+unsigned inptr = 0;	/* index of next byte to be processed in inbuf
+			 * After decompression it will contain the
+			 * compressed size, and head.S will read it.
+			 */
+
+static unsigned outcnt = 0;  /* bytes in output buffer */
+
+/* gzip flag byte */
+#define ASCII_FLAG   0x01 /* bit 0 set: file probably ascii text */
+#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */
+#define EXTRA_FIELD  0x04 /* bit 2 set: extra field present */
+#define ORIG_NAME    0x08 /* bit 3 set: original file name present */
+#define COMMENT      0x10 /* bit 4 set: file comment present */
+#define ENCRYPTED    0x20 /* bit 5 set: file is encrypted */
+#define RESERVED     0xC0 /* bit 6,7:   reserved */
+
+#define get_byte() inbuf[inptr++]
+
+/* Diagnostic functions */
+#ifdef DEBUG
+#  define Assert(cond,msg) {if(!(cond)) error(msg);}
+#  define Trace(x) fprintf x
+#  define Tracev(x) {if (verbose) fprintf x ;}
+#  define Tracevv(x) {if (verbose>1) fprintf x ;}
+#  define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
+#  define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
+#else
+#  define Assert(cond,msg)
+#  define Trace(x)
+#  define Tracev(x)
+#  define Tracevv(x)
+#  define Tracec(c,x)
+#  define Tracecv(c,x)
+#endif
+
+static int  fill_inbuf(void);
+static void flush_window(void);
+static void error(char *m);
+static void gzip_mark(void **);
+static void gzip_release(void **);
+
+extern char *input_data;  /* lives in head.S */
+
+static long bytes_out = 0;
+static uch *output_data;
+static unsigned long output_ptr = 0;
+
+static void *malloc(int size);
+static void free(void *where);
+static void error(char *m);
+static void gzip_mark(void **);
+static void gzip_release(void **);
+
+static void puts(const char *);
+
+/* the "heap" is put directly after the BSS ends, at end */
+
+extern int _end;
+static long free_mem_ptr = (long)&_end;
+
+#include "../../../../../lib/inflate.c"
+
+static void *malloc(int size)
+{
+	void *p;
+
+	if (size <0) error("Malloc error");
+
+	free_mem_ptr = (free_mem_ptr + 3) & ~3;	/* Align */
+
+	p = (void *)free_mem_ptr;
+	free_mem_ptr += size;
+
+	return p;
+}
+
+static void free(void *where)
+{	/* Don't care */
+}
+
+static void gzip_mark(void **ptr)
+{
+	*ptr = (void *) free_mem_ptr;
+}
+
+static void gzip_release(void **ptr)
+{
+	free_mem_ptr = (long) *ptr;
+}
+
+/* decompressor info and error messages to serial console */
+
+static inline void
+serout(const char *s, reg_scope_instances regi_ser)
+{
+	reg_ser_rs_stat_din rs;
+	reg_ser_rw_dout dout = {.data = *s};
+
+	do {
+		rs = REG_RD(ser, regi_ser, rs_stat_din);
+	}
+	while (!rs.tr_rdy);/* Wait for tranceiver. */
+
+	REG_WR(ser, regi_ser, rw_dout, dout);
+}
+
+static void
+puts(const char *s)
+{
+#ifndef CONFIG_ETRAX_DEBUG_PORT_NULL
+	while (*s) {
+#ifdef CONFIG_ETRAX_DEBUG_PORT0
+		serout(s, regi_ser0);
+#endif
+#ifdef CONFIG_ETRAX_DEBUG_PORT1
+		serout(s, regi_ser1);
+#endif
+#ifdef CONFIG_ETRAX_DEBUG_PORT2
+		serout(s, regi_ser2);
+#endif
+#ifdef CONFIG_ETRAX_DEBUG_PORT3
+		serout(s, regi_ser3);
+#endif
+		*s++;
+	}
+/* CONFIG_ETRAX_DEBUG_PORT_NULL */
+#endif
+}
+
+void*
+memset(void* s, int c, size_t n)
+{
+	int i;
+	char *ss = (char*)s;
+
+	for (i=0;i<n;i++) ss[i] = c;
+}
+
+void*
+memcpy(void* __dest, __const void* __src,
+			    size_t __n)
+{
+	int i;
+	char *d = (char *)__dest, *s = (char *)__src;
+
+	for (i=0;i<__n;i++) d[i] = s[i];
+}
+
+/* ===========================================================================
+ * Write the output window window[0..outcnt-1] and update crc and bytes_out.
+ * (Used for the decompressed data only.)
+ */
+
+static void
+flush_window()
+{
+    ulg c = crc;         /* temporary variable */
+    unsigned n;
+    uch *in, *out, ch;
+
+    in = window;
+    out = &output_data[output_ptr];
+    for (n = 0; n < outcnt; n++) {
+	    ch = *out++ = *in++;
+	    c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8);
+    }
+    crc = c;
+    bytes_out += (ulg)outcnt;
+    output_ptr += (ulg)outcnt;
+    outcnt = 0;
+}
+
+static void
+error(char *x)
+{
+	puts("\n\n");
+	puts(x);
+	puts("\n\n -- System halted\n");
+
+	while(1);	/* Halt */
+}
+
+void
+setup_normal_output_buffer()
+{
+	output_data = (char *)KERNEL_LOAD_ADR;
+}
+
+static inline void
+serial_setup(reg_scope_instances regi_ser)
+{
+	reg_ser_rw_xoff xoff;
+	reg_ser_rw_tr_ctrl tr_ctrl;
+	reg_ser_rw_rec_ctrl rec_ctrl;
+	reg_ser_rw_tr_baud_div tr_baud;
+	reg_ser_rw_rec_baud_div rec_baud;
+
+	/* Turn off XOFF. */
+	xoff = REG_RD(ser, regi_ser, rw_xoff);
+
+	xoff.chr = 0;
+	xoff.automatic = regk_ser_no;
+
+	REG_WR(ser, regi_ser, rw_xoff, xoff);
+
+	/* Set baudrate and stopbits. */
+	tr_ctrl = REG_RD(ser, regi_ser, rw_tr_ctrl);
+	rec_ctrl = REG_RD(ser, regi_ser, rw_rec_ctrl);
+	tr_baud = REG_RD(ser, regi_ser, rw_tr_baud_div);
+	rec_baud = REG_RD(ser, regi_ser, rw_rec_baud_div);
+
+	tr_ctrl.stop_bits = 1;	/* 2 stop bits. */
+
+	/*
+	 * The baudrate setup is a bit fishy, but in the end the tranceiver is
+	 * set to 4800 and the receiver to 115200. The magic value is
+	 * 29.493 MHz.
+	 */
+	tr_ctrl.base_freq = regk_ser_f29_493;
+	rec_ctrl.base_freq = regk_ser_f29_493;
+	tr_baud.div = (29493000 / 8) / 4800;
+	rec_baud.div = (29493000 / 8) / 115200;
+
+	REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl);
+	REG_WR(ser, regi_ser, rw_tr_baud_div, tr_baud);
+	REG_WR(ser, regi_ser, rw_rec_ctrl, rec_ctrl);
+	REG_WR(ser, regi_ser, rw_rec_baud_div, rec_baud);
+}
+
+void
+decompress_kernel()
+{
+	char revision;
+
+	/* input_data is set in head.S */
+	inbuf = input_data;
+
+#ifdef CONFIG_ETRAX_DEBUG_PORT0
+	serial_setup(regi_ser0);
+#endif
+#ifdef CONFIG_ETRAX_DEBUG_PORT1
+	serial_setup(regi_ser1);
+#endif
+#ifdef CONFIG_ETRAX_DEBUG_PORT2
+	serial_setup(regi_ser2);
+#endif
+#ifdef CONFIG_ETRAX_DEBUG_PORT3
+	serial_setup(regi_ser3);
+#endif
+
+	setup_normal_output_buffer();
+
+	makecrc();
+
+	__asm__ volatile ("move $vr,%0" : "=rm" (revision));
+	if (revision < 32)
+	{
+		puts("You need an ETRAX FS to run Linux 2.6/crisv32.\n");
+		while(1);
+	}
+
+	puts("Uncompressing Linux...\n");
+	gunzip();
+	puts("Done. Now booting the kernel.\n");
+}
diff --git a/arch/cris/arch-v32/boot/rescue/Makefile b/arch/cris/arch-v32/boot/rescue/Makefile
new file mode 100644
index 00000000000..f668a819872
--- /dev/null
+++ b/arch/cris/arch-v32/boot/rescue/Makefile
@@ -0,0 +1,36 @@
+#
+# Makefile for rescue code
+#
+target = $(target_rescue_dir)
+src    = $(src_rescue_dir)
+
+CC = gcc-cris -mlinux -march=v32 $(LINUXINCLUDE)
+CFLAGS = -O2
+LD = gcc-cris -mlinux -march=v32 -nostdlib
+OBJCOPY = objcopy-cris
+OBJCOPYFLAGS = -O binary --remove-section=.bss
+
+all: $(target)/rescue.bin
+
+rescue: rescue.bin
+	# do nothing
+
+$(target)/rescue.bin: $(target) $(target)/head.o
+	$(LD) -T $(src)/rescue.ld -o $(target)/rescue.o $(target)/head.o
+	$(OBJCOPY) $(OBJCOPYFLAGS) $(target)/rescue.o $(target)/rescue.bin
+	cp -p $(target)/rescue.bin $(objtree)
+
+$(target):
+	mkdir -p $(target)
+
+$(target)/head.o: $(src)/head.S
+	$(CC) -D__ASSEMBLY__ -c $< -o $*.o
+
+clean:
+	rm -f $(target)/*.o $(target)/*.bin
+
+fastdep:
+
+modules:
+
+modules-install:
diff --git a/arch/cris/arch-v32/boot/rescue/head.S b/arch/cris/arch-v32/boot/rescue/head.S
new file mode 100644
index 00000000000..61ede5f30f9
--- /dev/null
+++ b/arch/cris/arch-v32/boot/rescue/head.S
@@ -0,0 +1,39 @@
+/* $Id: head.S,v 1.4 2004/11/01 16:10:28 starvik Exp $
+ *
+ * This used to be the rescue code but now that is handled by the
+ * RedBoot based RFL instead. Nothing to see here, move along.
+ */
+
+#include <linux/config.h>
+#include <asm/arch/hwregs/reg_map_asm.h>
+#include <asm/arch/hwregs/config_defs_asm.h>
+
+	.text
+
+	;; Start clocks for used blocks.
+	move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1
+	move.d [$r1], $r0
+	or.d   REG_STATE(config, rw_clk_ctrl, cpu, yes) | \
+	       REG_STATE(config, rw_clk_ctrl, bif, yes) | \
+	       REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0
+	move.d $r0, [$r1]
+
+	;; Copy 68KB NAND flash to Internal RAM (if NAND boot)
+	move.d 0x38004000, $r10
+	move.d 0x8000, $r11
+	move.d 0x11000, $r12
+	move.d copy_complete, $r13
+	and.d  0x000fffff, $r13
+	or.d   0x38000000, $r13
+
+#include "../../lib/nand_init.S"
+
+	;; No NAND found
+	move.d	CONFIG_ETRAX_PTABLE_SECTOR, $r10
+	jump	$r10 ; Jump to decompresser
+	nop
+
+copy_complete:
+	move.d	0x38000000 + CONFIG_ETRAX_PTABLE_SECTOR, $r10
+	jump	$r10 ; Jump to decompresser
+	nop
diff --git a/arch/cris/arch-v32/boot/rescue/rescue.ld b/arch/cris/arch-v32/boot/rescue/rescue.ld
new file mode 100644
index 00000000000..42b11aa122b
--- /dev/null
+++ b/arch/cris/arch-v32/boot/rescue/rescue.ld
@@ -0,0 +1,20 @@
+MEMORY
+	{
+	flash : ORIGIN = 0x00000000,
+	        LENGTH = 0x00100000
+	}
+
+SECTIONS
+{
+	.text :
+	{
+		stext = . ;
+		*(.text)
+		etext = . ;
+	} > flash
+	.data :
+	{
+		*(.data)
+		edata = . ;
+	} > flash
+}
diff --git a/arch/cris/arch-v32/drivers/Kconfig b/arch/cris/arch-v32/drivers/Kconfig
new file mode 100644
index 00000000000..a33097f9536
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/Kconfig
@@ -0,0 +1,625 @@
+config ETRAX_ETHERNET
+	bool "Ethernet support"
+	depends on ETRAX_ARCH_V32
+	select NET_ETHERNET
+	help
+	  This option enables the ETRAX FS built-in 10/100Mbit Ethernet
+	  controller.
+
+config ETRAX_ETHERNET_HW_CSUM
+	bool "Hardware accelerated ethernet checksum and scatter/gather"
+	depends on ETRAX_ETHERNET
+	depends on ETRAX_STREAMCOPROC
+	default y
+	help
+	  Hardware acceleration of checksumming and scatter/gather
+
+config ETRAX_ETHERNET_IFACE0
+	depends on ETRAX_ETHERNET
+	bool "Enable network interface 0"
+
+config ETRAX_ETHERNET_IFACE1
+	depends on ETRAX_ETHERNET
+	bool "Enable network interface 1 (uses DMA6 and DMA7)"
+
+choice
+	prompt "Network LED behavior"
+	depends on ETRAX_ETHERNET
+	default ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
+
+config ETRAX_NETWORK_LED_ON_WHEN_LINK
+	bool "LED_on_when_link"
+	help
+	  Selecting LED_on_when_link will light the LED when there is a
+	  connection and will flash off when there is activity.
+
+	  Selecting LED_on_when_activity will light the LED only when
+	  there is activity.
+
+	  This setting will also affect the behaviour of other activity LEDs
+	  e.g. Bluetooth.
+
+config ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
+	bool "LED_on_when_activity"
+	help
+	  Selecting LED_on_when_link will light the LED when there is a
+	  connection and will flash off when there is activity.
+
+	  Selecting LED_on_when_activity will light the LED only when
+	  there is activity.
+
+	  This setting will also affect the behaviour of other activity LEDs
+	  e.g. Bluetooth.
+
+endchoice
+
+config ETRAXFS_SERIAL
+	bool "Serial-port support"
+	depends on ETRAX_ARCH_V32
+	help
+	  Enables the ETRAX FS serial driver for ser0 (ttyS0)
+	  You probably want this enabled.
+
+config ETRAX_SERIAL_PORT0
+	bool "Serial port 0 enabled"
+	depends on ETRAXFS_SERIAL
+	help
+	  Enables the ETRAX FS serial driver for ser0 (ttyS0)
+	  Normally you want this on. You can control what DMA channels to use
+	  if you do not need DMA to something else.
+	  ser0 can use dma4 or dma6 for output and dma5 or dma7 for input.
+
+choice
+	prompt "Ser0 DMA in channel "
+	depends on ETRAX_SERIAL_PORT0
+	default ETRAX_SERIAL_PORT0_NO_DMA_IN
+	help
+	  What DMA channel to use for ser0.
+
+
+config ETRAX_SERIAL_PORT0_NO_DMA_IN
+	bool "Ser0 uses no DMA for input"
+	help
+	  Do not use DMA for ser0 input.
+
+config ETRAX_SERIAL_PORT0_DMA7_IN
+	bool "Ser0 uses DMA7 for input"
+	depends on ETRAX_SERIAL_PORT0
+	help
+	  Enables the DMA7 input channel for ser0 (ttyS0).
+	  If you do not enable DMA, an interrupt for each character will be
+	  used when receiveing data.
+	  Normally you want to use DMA, unless you use the DMA channel for
+	  something else.
+
+endchoice
+
+choice
+	prompt "Ser0 DMA out channel"
+	depends on ETRAX_SERIAL_PORT0
+	default ETRAX_SERIAL_PORT0_NO_DMA_OUT
+
+config ETRAX_SERIAL_PORT0_NO_DMA_OUT
+	bool "Ser0 uses no DMA for output"
+	help
+	  Do not use DMA for ser0 output.
+
+config ETRAX_SERIAL_PORT0_DMA6_OUT
+	bool "Ser0 uses DMA6 for output"
+	depends on ETRAX_SERIAL_PORT0
+	help
+	  Enables the DMA6 output channel for ser0 (ttyS0).
+	  If you do not enable DMA, an interrupt for each character will be
+	  used when transmitting data.
+	  Normally you want to use DMA, unless you use the DMA channel for
+	  something else.
+
+endchoice
+
+config ETRAX_SER0_DTR_BIT
+	string "Ser 0 DTR bit (empty = not used)"
+	depends on ETRAX_SERIAL_PORT0
+
+config ETRAX_SER0_RI_BIT
+	string "Ser 0 RI bit (empty = not used)"
+	depends on ETRAX_SERIAL_PORT0
+
+config ETRAX_SER0_DSR_BIT
+	string "Ser 0 DSR bit (empty = not used)"
+	depends on ETRAX_SERIAL_PORT0
+
+config ETRAX_SER0_CD_BIT
+	string "Ser 0 CD bit (empty = not used)"
+	depends on ETRAX_SERIAL_PORT0
+
+config ETRAX_SERIAL_PORT1
+	bool "Serial port 1 enabled"
+	depends on ETRAXFS_SERIAL
+	help
+	  Enables the ETRAX FS serial driver for ser1 (ttyS1).
+
+choice
+	prompt "Ser1 DMA in channel "
+	depends on ETRAX_SERIAL_PORT1
+	default ETRAX_SERIAL_PORT1_NO_DMA_IN
+	help
+	  What DMA channel to use for ser1.
+
+
+config ETRAX_SERIAL_PORT1_NO_DMA_IN
+	bool "Ser1 uses no DMA for input"
+	help
+	  Do not use DMA for ser1 input.
+
+config ETRAX_SERIAL_PORT1_DMA5_IN
+	bool "Ser1 uses DMA5 for input"
+	depends on ETRAX_SERIAL_PORT1
+	help
+	  Enables the DMA5 input channel for ser1 (ttyS1).
+	  If you do not enable DMA, an interrupt for each character will be
+	  used when receiveing data.
+	  Normally you want this on, unless you use the DMA channel for
+	  something else.
+
+endchoice
+
+choice
+	prompt "Ser1 DMA out channel "
+	depends on ETRAX_SERIAL_PORT1
+	default ETRAX_SERIAL_PORT1_NO_DMA_OUT
+	help
+	  What DMA channel to use for ser1.
+
+config ETRAX_SERIAL_PORT1_NO_DMA_OUT
+	bool "Ser1 uses no DMA for output"
+	help
+	  Do not use DMA for ser1 output.
+
+config ETRAX_SERIAL_PORT1_DMA4_OUT
+	bool "Ser1 uses DMA4 for output"
+	depends on ETRAX_SERIAL_PORT1
+	help
+	  Enables the DMA4 output channel for ser1 (ttyS1).
+	  If you do not enable DMA, an interrupt for each character will be
+	  used when transmitting data.
+	  Normally you want this on, unless you use the DMA channel for
+	  something else.
+
+endchoice
+
+config ETRAX_SER1_DTR_BIT
+	string "Ser 1 DTR bit (empty = not used)"
+	depends on ETRAX_SERIAL_PORT1
+
+config ETRAX_SER1_RI_BIT
+	string "Ser 1 RI bit (empty = not used)"
+	depends on ETRAX_SERIAL_PORT1
+
+config ETRAX_SER1_DSR_BIT
+	string "Ser 1 DSR bit (empty = not used)"
+	depends on ETRAX_SERIAL_PORT1
+
+config ETRAX_SER1_CD_BIT
+	string "Ser 1 CD bit (empty = not used)"
+	depends on ETRAX_SERIAL_PORT1
+
+config ETRAX_SERIAL_PORT2
+	bool "Serial port 2 enabled"
+	depends on ETRAXFS_SERIAL
+	help
+	  Enables the ETRAX FS serial driver for ser2 (ttyS2).
+
+choice
+	prompt "Ser2 DMA in channel "
+	depends on ETRAX_SERIAL_PORT2
+	default ETRAX_SERIAL_PORT2_NO_DMA_IN
+	help
+	  What DMA channel to use for ser2.
+
+
+config ETRAX_SERIAL_PORT2_NO_DMA_IN
+	bool "Ser2 uses no DMA for input"
+	help
+	  Do not use DMA for ser2 input.
+
+config ETRAX_SERIAL_PORT2_DMA3_IN
+	bool "Ser2 uses DMA3 for input"
+	depends on ETRAX_SERIAL_PORT2
+	help
+	  Enables the DMA3 input channel for ser2 (ttyS2).
+	  If you do not enable DMA, an interrupt for each character will be
+	  used when receiveing data.
+	  Normally you want to use DMA, unless you use the DMA channel for
+	  something else.
+
+endchoice
+
+choice
+	prompt "Ser2 DMA out channel"
+	depends on ETRAX_SERIAL_PORT2
+	default ETRAX_SERIAL_PORT2_NO_DMA_OUT
+
+config ETRAX_SERIAL_PORT2_NO_DMA_OUT
+	bool "Ser2 uses no DMA for output"
+	help
+	  Do not use DMA for ser2 output.
+
+config ETRAX_SERIAL_PORT2_DMA2_OUT
+	bool "Ser2 uses DMA2 for output"
+	depends on ETRAX_SERIAL_PORT2
+	help
+	  Enables the DMA2 output channel for ser2 (ttyS2).
+	  If you do not enable DMA, an interrupt for each character will be
+	  used when transmitting data.
+	  Normally you want to use DMA, unless you use the DMA channel for
+	  something else.
+
+endchoice
+
+config ETRAX_SER2_DTR_BIT
+	string "Ser 2 DTR bit (empty = not used)"
+	depends on ETRAX_SERIAL_PORT2
+
+config ETRAX_SER2_RI_BIT
+	string "Ser 2 RI bit (empty = not used)"
+	depends on ETRAX_SERIAL_PORT2
+
+config ETRAX_SER2_DSR_BIT
+	string "Ser 2 DSR bit (empty = not used)"
+	depends on ETRAX_SERIAL_PORT2
+
+config ETRAX_SER2_CD_BIT
+	string "Ser 2 CD bit (empty = not used)"
+	depends on ETRAX_SERIAL_PORT2
+
+config ETRAX_SERIAL_PORT3
+	bool "Serial port 3 enabled"
+	depends on ETRAXFS_SERIAL
+	help
+	  Enables the ETRAX FS serial driver for ser3 (ttyS3).
+
+choice
+	prompt "Ser3 DMA in channel "
+	depends on ETRAX_SERIAL_PORT3
+	default ETRAX_SERIAL_PORT3_NO_DMA_IN
+	help
+	  What DMA channel to use for ser3.
+
+
+config ETRAX_SERIAL_PORT3_NO_DMA_IN
+	bool "Ser3 uses no DMA for input"
+	help
+	  Do not use DMA for ser3 input.
+
+config ETRAX_SERIAL_PORT3_DMA9_IN
+	bool "Ser3 uses DMA9 for input"
+	depends on ETRAX_SERIAL_PORT3
+	help
+	  Enables the DMA9 input channel for ser3 (ttyS3).
+	  If you do not enable DMA, an interrupt for each character will be
+	  used when receiveing data.
+	  Normally you want to use DMA, unless you use the DMA channel for
+	  something else.
+
+endchoice
+
+choice
+	prompt "Ser3 DMA out channel"
+	depends on ETRAX_SERIAL_PORT3
+	default ETRAX_SERIAL_PORT3_NO_DMA_OUT
+
+config ETRAX_SERIAL_PORT3_NO_DMA_OUT
+	bool "Ser3 uses no DMA for output"
+	help
+	  Do not use DMA for ser3 output.
+
+config ETRAX_SERIAL_PORT3_DMA8_OUT
+	bool "Ser3 uses DMA8 for output"
+	depends on ETRAX_SERIAL_PORT3
+	help
+	  Enables the DMA8 output channel for ser3 (ttyS3).
+	  If you do not enable DMA, an interrupt for each character will be
+	  used when transmitting data.
+	  Normally you want to use DMA, unless you use the DMA channel for
+	  something else.
+
+endchoice
+
+config ETRAX_SER3_DTR_BIT
+	string "Ser 3 DTR bit (empty = not used)"
+	depends on ETRAX_SERIAL_PORT3
+
+config ETRAX_SER3_RI_BIT
+	string "Ser 3 RI bit (empty = not used)"
+	depends on ETRAX_SERIAL_PORT3
+
+config ETRAX_SER3_DSR_BIT
+	string "Ser 3 DSR bit (empty = not used)"
+	depends on ETRAX_SERIAL_PORT3
+
+config ETRAX_SER3_CD_BIT
+	string "Ser 3 CD bit (empty = not used)"
+	depends on ETRAX_SERIAL_PORT3
+
+config ETRAX_RS485
+	bool "RS-485 support"
+	depends on ETRAX_SERIAL
+	help
+	  Enables support for RS-485 serial communication.  For a primer on
+	  RS-485, see <http://www.hw.cz/english/docs/rs485/rs485.html>.
+
+config ETRAX_RS485_DISABLE_RECEIVER
+	bool "Disable serial receiver"
+	depends on ETRAX_RS485
+	help
+	  It is necessary to disable the serial receiver to avoid serial
+	  loopback.  Not all products are able to do this in software only.
+	  Axis 2400/2401 must disable receiver.
+
+config ETRAX_AXISFLASHMAP
+	bool "Axis flash-map support"
+	depends on ETRAX_ARCH_V32
+	select MTD
+	select MTD_CFI
+	select MTD_CFI_AMDSTD
+	select MTD_OBSOLETE_CHIPS
+	select MTD_AMDSTD
+	select MTD_CHAR
+	select MTD_BLOCK
+	select MTD_PARTITIONS
+	select MTD_CONCAT
+	select MTD_COMPLEX_MAPPINGS
+	help
+	  This option enables MTD mapping of flash devices.  Needed to use
+	  flash memories.  If unsure, say Y.
+
+config ETRAX_SYNCHRONOUS_SERIAL
+	bool "Synchronous serial-port support"
+	depends on ETRAX_ARCH_V32
+	help
+	  Enables the ETRAX FS synchronous serial driver.
+
+config ETRAX_SYNCHRONOUS_SERIAL_PORT0
+         bool "Synchronous serial port 0 enabled"
+         depends on ETRAX_SYNCHRONOUS_SERIAL
+         help
+           Enabled synchronous serial port 0.
+
+config ETRAX_SYNCHRONOUS_SERIAL0_DMA
+         bool "Enable DMA on synchronous serial port 0."
+         depends on ETRAX_SYNCHRONOUS_SERIAL_PORT0
+         help
+           A synchronous serial port can run in manual or DMA mode.
+           Selecting this option will make it run in DMA mode.
+
+config ETRAX_SYNCHRONOUS_SERIAL_PORT1
+         bool "Synchronous serial port 1 enabled"
+         depends on ETRAX_SYNCHRONOUS_SERIAL
+         help
+           Enabled synchronous serial port 1.
+
+config ETRAX_SYNCHRONOUS_SERIAL1_DMA
+         bool "Enable DMA on synchronous serial port 1."
+         depends on ETRAX_SYNCHRONOUS_SERIAL_PORT1
+         help
+           A synchronous serial port can run in manual or DMA mode.
+           Selecting this option will make it run in DMA mode.
+
+config ETRAX_PTABLE_SECTOR
+	int "Byte-offset of partition table sector"
+	depends on ETRAX_AXISFLASHMAP
+	default "65536"
+	help
+	  Byte-offset of the partition table in the first flash chip.
+	  The default value is 64kB and should not be changed unless
+	  you know exactly what you are doing. The only valid reason
+	  for changing this is when the flash block size is bigger
+	  than 64kB (e.g. when using two parallel 16 bit flashes).
+
+config ETRAX_NANDFLASH
+	bool "NAND flash support"
+	depends on ETRAX_ARCH_V32
+	select MTD_NAND
+	select MTD_NAND_IDS
+	help
+	  This option enables MTD mapping of NAND flash devices.  Needed to use
+	  NAND flash memories.  If unsure, say Y.
+
+config ETRAX_I2C
+	bool "I2C driver"
+	depends on ETRAX_ARCH_V32
+	help
+	  This option enabled the I2C driver used by e.g. the RTC driver.
+
+config ETRAX_I2C_DATA_PORT
+	string "I2C data pin"
+	depends on ETRAX_I2C
+	help
+	  The pin to use for I2C data.
+
+config ETRAX_I2C_CLK_PORT
+	string "I2C clock pin"
+	depends on ETRAX_I2C
+	help
+	  The pin to use for I2C clock.
+
+config ETRAX_RTC
+	bool "Real Time Clock support"
+	depends on ETRAX_ARCH_V32
+	help
+	  Enabled RTC support.
+
+choice
+	prompt "RTC chip"
+	depends on ETRAX_RTC
+	default ETRAX_PCF8563
+
+config ETRAX_PCF8563
+	bool "PCF8563"
+	help
+	  Philips PCF8563 RTC
+
+endchoice
+
+config ETRAX_GPIO
+	bool "GPIO support"
+	depends on ETRAX_ARCH_V32
+	---help---
+	  Enables the ETRAX general port device (major 120, minors 0-4).
+	  You can use this driver to access the general port bits. It supports
+	  these ioctl's:
+	  #include <linux/etraxgpio.h>
+	  fd = open("/dev/gpioa", O_RDWR); // or /dev/gpiob
+	  ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_SETBITS), bits_to_set);
+	  ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_CLRBITS), bits_to_clear);
+	  err = ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_READ_INBITS), &val);
+	  Remember that you need to setup the port directions appropriately in
+	  the General configuration.
+
+config ETRAX_PA_BUTTON_BITMASK
+	hex "PA-buttons bitmask"
+	depends on ETRAX_GPIO
+	default "0x02"
+	help
+	  This is a bitmask (8 bits) with information about what bits on PA
+	  that are used for buttons.
+	  Most products has a so called TEST button on PA1, if that is true
+	  use 0x02 here.
+	  Use 00 if there are no buttons on PA.
+	  If the bitmask is <> 00 a button driver will be included in the gpio
+	  driver. ETRAX general I/O support must be enabled.
+
+config ETRAX_PA_CHANGEABLE_DIR
+	hex "PA user changeable dir mask"
+	depends on ETRAX_GPIO
+	default "0x00"
+	help
+	  This is a bitmask (8 bits) with information of what bits in PA that a
+	  user can change direction on using ioctl's.
+	  Bit set = changeable.
+	  You probably want 0x00 here, but it depends on your hardware.
+
+config ETRAX_PA_CHANGEABLE_BITS
+	hex "PA user changeable bits mask"
+	depends on ETRAX_GPIO
+	default "0x00"
+	help
+	  This is a bitmask (8 bits) with information of what bits in PA
+	  that a user can change the value on using ioctl's.
+	  Bit set = changeable.
+
+config ETRAX_PB_CHANGEABLE_DIR
+	hex "PB user changeable dir mask"
+	depends on ETRAX_GPIO
+	default "0x00000"
+	help
+	  This is a bitmask (18 bits) with information of what bits in PB
+	  that a user can change direction on using ioctl's.
+	  Bit set = changeable.
+	  You probably want 0x00000 here, but it depends on your hardware.
+
+config ETRAX_PB_CHANGEABLE_BITS
+	hex "PB user changeable bits mask"
+	depends on ETRAX_GPIO
+	default "0x00000"
+	help
+	  This is a bitmask (18 bits) with information of what bits in PB
+	  that a user can change the value on using ioctl's.
+	  Bit set = changeable.
+
+config ETRAX_PC_CHANGEABLE_DIR
+	hex "PC user changeable dir mask"
+	depends on ETRAX_GPIO
+	default "0x00000"
+	help
+	  This is a bitmask (18 bits) with information of what bits in PC
+	  that a user can change direction on using ioctl's.
+	  Bit set = changeable.
+	  You probably want 0x00000 here, but it depends on your hardware.
+
+config ETRAX_PC_CHANGEABLE_BITS
+	hex "PC user changeable bits mask"
+	depends on ETRAX_GPIO
+	default "0x00000"
+	help
+	  This is a bitmask (18 bits) with information of what bits in PC
+	  that a user can change the value on using ioctl's.
+	  Bit set = changeable.
+
+config ETRAX_PD_CHANGEABLE_DIR
+	hex "PD user changeable dir mask"
+	depends on ETRAX_GPIO
+	default "0x00000"
+	help
+	  This is a bitmask (18 bits) with information of what bits in PD
+	  that a user can change direction on using ioctl's.
+	  Bit set = changeable.
+	  You probably want 0x00000 here, but it depends on your hardware.
+
+config ETRAX_PD_CHANGEABLE_BITS
+	hex "PD user changeable bits mask"
+	depends on ETRAX_GPIO
+	default "0x00000"
+	help
+	  This is a bitmask (18 bits) with information of what bits in PD
+	  that a user can change the value on using ioctl's.
+	  Bit set = changeable.
+
+config ETRAX_PE_CHANGEABLE_DIR
+	hex "PE user changeable dir mask"
+	depends on ETRAX_GPIO
+	default "0x00000"
+	help
+	  This is a bitmask (18 bits) with information of what bits in PE
+	  that a user can change direction on using ioctl's.
+	  Bit set = changeable.
+	  You probably want 0x00000 here, but it depends on your hardware.
+
+config ETRAX_PE_CHANGEABLE_BITS
+	hex "PE user changeable bits mask"
+	depends on ETRAX_GPIO
+	default "0x00000"
+	help
+	  This is a bitmask (18 bits) with information of what bits in PE
+	  that a user can change the value on using ioctl's.
+	  Bit set = changeable.
+
+config ETRAX_IDE
+	bool "ATA/IDE support"
+	depends on ETRAX_ARCH_V32
+	select IDE
+	select BLK_DEV_IDE
+	select BLK_DEV_IDEDISK
+	select BLK_DEV_IDECD
+	select BLK_DEV_IDEDMA
+	help
+	  Enables the ETRAX IDE driver.
+
+config ETRAX_CARDBUS
+        bool "Cardbus support"
+        depends on ETRAX_ARCH_V32
+        select PCCARD
+        select CARDBUS
+        select HOTPLUG
+        select PCCARD_NONSTATIC
+        help
+	 Enabled the ETRAX Carbus driver.
+
+config PCI
+       bool
+       depends on ETRAX_CARDBUS
+       default y
+
+config ETRAX_IOP_FW_LOAD
+	tristate "IO-processor hotplug firmware loading support"
+	depends on ETRAX_ARCH_V32
+	select FW_LOADER
+	help
+	  Enables IO-processor hotplug firmware loading support.
+
+config ETRAX_STREAMCOPROC
+	tristate "Stream co-processor driver enabled"
+	depends on ETRAX_ARCH_V32
+	help
+	  This option enables a driver for the stream co-processor
+	  for cryptographic operations.
diff --git a/arch/cris/arch-v32/drivers/Makefile b/arch/cris/arch-v32/drivers/Makefile
new file mode 100644
index 00000000000..a359cd20ae7
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/Makefile
@@ -0,0 +1,13 @@
+#
+# Makefile for Etrax-specific drivers
+#
+
+obj-$(CONFIG_ETRAX_STREAMCOPROC)        += cryptocop.o
+obj-$(CONFIG_ETRAX_AXISFLASHMAP)        += axisflashmap.o
+obj-$(CONFIG_ETRAX_NANDFLASH)           += nandflash.o
+obj-$(CONFIG_ETRAX_GPIO) 	        += gpio.o
+obj-$(CONFIG_ETRAX_IOP_FW_LOAD)         += iop_fw_load.o
+obj-$(CONFIG_ETRAX_PCF8563)		+= pcf8563.o
+obj-$(CONFIG_ETRAX_I2C)			+= i2c.o
+obj-$(CONFIG_ETRAX_SYNCHRONOUS_SERIAL)	+= sync_serial.o
+obj-$(CONFIG_PCI)			+= pci/
diff --git a/arch/cris/arch-v32/drivers/axisflashmap.c b/arch/cris/arch-v32/drivers/axisflashmap.c
new file mode 100644
index 00000000000..78ed52b1cda
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/axisflashmap.c
@@ -0,0 +1,455 @@
+/*
+ * Physical mapping layer for MTD using the Axis partitiontable format
+ *
+ * Copyright (c) 2001, 2002, 2003 Axis Communications AB
+ *
+ * This file is under the GPL.
+ *
+ * First partition is always sector 0 regardless of if we find a partitiontable
+ * or not. In the start of the next sector, there can be a partitiontable that
+ * tells us what other partitions to define. If there isn't, we use a default
+ * partition split defined below.
+ *
+ * Copy of os/lx25/arch/cris/arch-v10/drivers/axisflashmap.c 1.5
+ * with minor changes.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/config.h>
+#include <linux/init.h>
+
+#include <linux/mtd/concat.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/mtdram.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/arch/hwregs/config_defs.h>
+#include <asm/axisflashmap.h>
+#include <asm/mmu.h>
+
+#define MEM_CSE0_SIZE (0x04000000)
+#define MEM_CSE1_SIZE (0x04000000)
+
+#define FLASH_UNCACHED_ADDR  KSEG_E
+#define FLASH_CACHED_ADDR    KSEG_F
+
+#if CONFIG_ETRAX_FLASH_BUSWIDTH==1
+#define flash_data __u8
+#elif CONFIG_ETRAX_FLASH_BUSWIDTH==2
+#define flash_data __u16
+#elif CONFIG_ETRAX_FLASH_BUSWIDTH==4
+#define flash_data __u16
+#endif
+
+/* From head.S */
+extern unsigned long romfs_start, romfs_length, romfs_in_flash;
+
+/* The master mtd for the entire flash. */
+struct mtd_info* axisflash_mtd = NULL;
+
+/* Map driver functions. */
+
+static map_word flash_read(struct map_info *map, unsigned long ofs)
+{
+	map_word tmp;
+	tmp.x[0] = *(flash_data *)(map->map_priv_1 + ofs);
+	return tmp;
+}
+
+static void flash_copy_from(struct map_info *map, void *to,
+			    unsigned long from, ssize_t len)
+{
+	memcpy(to, (void *)(map->map_priv_1 + from), len);
+}
+
+static void flash_write(struct map_info *map, map_word d, unsigned long adr)
+{
+	*(flash_data *)(map->map_priv_1 + adr) = (flash_data)d.x[0];
+}
+
+/*
+ * The map for chip select e0.
+ *
+ * We run into tricky coherence situations if we mix cached with uncached
+ * accesses to we only use the uncached version here.
+ *
+ * The size field is the total size where the flash chips may be mapped on the
+ * chip select. MTD probes should find all devices there and it does not matter
+ * if there are unmapped gaps or aliases (mirrors of flash devices). The MTD
+ * probes will ignore them.
+ *
+ * The start address in map_priv_1 is in virtual memory so we cannot use
+ * MEM_CSE0_START but must rely on that FLASH_UNCACHED_ADDR is the start
+ * address of cse0.
+ */
+static struct map_info map_cse0 = {
+	.name = "cse0",
+	.size = MEM_CSE0_SIZE,
+	.bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH,
+	.read = flash_read,
+	.copy_from = flash_copy_from,
+	.write = flash_write,
+	.map_priv_1 = FLASH_UNCACHED_ADDR
+};
+
+/*
+ * The map for chip select e1.
+ *
+ * If there was a gap between cse0 and cse1, map_priv_1 would get the wrong
+ * address, but there isn't.
+ */
+static struct map_info map_cse1 = {
+	.name = "cse1",
+	.size = MEM_CSE1_SIZE,
+	.bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH,
+	.read = flash_read,
+	.copy_from = flash_copy_from,
+	.write = flash_write,
+	.map_priv_1 = FLASH_UNCACHED_ADDR + MEM_CSE0_SIZE
+};
+
+/* If no partition-table was found, we use this default-set. */
+#define MAX_PARTITIONS         7
+#define NUM_DEFAULT_PARTITIONS 3
+
+/*
+ * Default flash size is 2MB. CONFIG_ETRAX_PTABLE_SECTOR is most likely the
+ * size of one flash block and "filesystem"-partition needs 5 blocks to be able
+ * to use JFFS.
+ */
+static struct mtd_partition axis_default_partitions[NUM_DEFAULT_PARTITIONS] = {
+	{
+		.name = "boot firmware",
+		.size = CONFIG_ETRAX_PTABLE_SECTOR,
+		.offset = 0
+	},
+	{
+		.name = "kernel",
+		.size = 0x200000 - (6 * CONFIG_ETRAX_PTABLE_SECTOR),
+		.offset = CONFIG_ETRAX_PTABLE_SECTOR
+	},
+	{
+		.name = "filesystem",
+		.size = 5 * CONFIG_ETRAX_PTABLE_SECTOR,
+		.offset = 0x200000 - (5 * CONFIG_ETRAX_PTABLE_SECTOR)
+	}
+};
+
+/* Initialize the ones normally used. */
+static struct mtd_partition axis_partitions[MAX_PARTITIONS] = {
+	{
+		.name = "part0",
+		.size = CONFIG_ETRAX_PTABLE_SECTOR,
+		.offset = 0
+	},
+	{
+		.name = "part1",
+		.size = 0,
+		.offset = 0
+	},
+	{
+		.name = "part2",
+		.size = 0,
+		.offset = 0
+	},
+	{
+		.name = "part3",
+		.size = 0,
+		.offset = 0
+	},
+	{
+		.name = "part4",
+		.size = 0,
+		.offset = 0
+	},
+	{
+		.name = "part5",
+		.size = 0,
+		.offset = 0
+	},
+	{
+		.name = "part6",
+		.size = 0,
+		.offset = 0
+	},
+};
+
+/*
+ * Probe a chip select for AMD-compatible (JEDEC) or CFI-compatible flash
+ * chips in that order (because the amd_flash-driver is faster).
+ */
+static struct mtd_info *probe_cs(struct map_info *map_cs)
+{
+	struct mtd_info *mtd_cs = NULL;
+
+	printk(KERN_INFO
+	       "%s: Probing a 0x%08lx bytes large window at 0x%08lx.\n",
+	       map_cs->name, map_cs->size, map_cs->map_priv_1);
+
+#ifdef CONFIG_MTD_AMDSTD
+	mtd_cs = do_map_probe("amd_flash", map_cs);
+#endif
+#ifdef CONFIG_MTD_CFI
+	if (!mtd_cs) {
+		mtd_cs = do_map_probe("cfi_probe", map_cs);
+	}
+#endif
+
+	return mtd_cs;
+}
+
+/*
+ * Probe each chip select individually for flash chips. If there are chips on
+ * both cse0 and cse1, the mtd_info structs will be concatenated to one struct
+ * so that MTD partitions can cross chip boundries.
+ *
+ * The only known restriction to how you can mount your chips is that each
+ * chip select must hold similar flash chips. But you need external hardware
+ * to do that anyway and you can put totally different chips on cse0 and cse1
+ * so it isn't really much of a restriction.
+ */
+extern struct mtd_info* __init crisv32_nand_flash_probe (void);
+static struct mtd_info *flash_probe(void)
+{
+	struct mtd_info *mtd_cse0;
+	struct mtd_info *mtd_cse1;
+	struct mtd_info *mtd_nand = NULL;
+	struct mtd_info *mtd_total;
+	struct mtd_info *mtds[3];
+	int count = 0;
+
+	if ((mtd_cse0 = probe_cs(&map_cse0)) != NULL)
+		mtds[count++] = mtd_cse0;
+	if ((mtd_cse1 = probe_cs(&map_cse1)) != NULL)
+		mtds[count++] = mtd_cse1;
+
+#ifdef CONFIG_ETRAX_NANDFLASH
+	if ((mtd_nand = crisv32_nand_flash_probe()) != NULL)
+		mtds[count++] = mtd_nand;
+#endif
+
+	if (!mtd_cse0 && !mtd_cse1 && !mtd_nand) {
+		/* No chip found. */
+		return NULL;
+	}
+
+	if (count > 1) {
+#ifdef CONFIG_MTD_CONCAT
+		/* Since the concatenation layer adds a small overhead we
+		 * could try to figure out if the chips in cse0 and cse1 are
+		 * identical and reprobe the whole cse0+cse1 window. But since
+		 * flash chips are slow, the overhead is relatively small.
+		 * So we use the MTD concatenation layer instead of further
+		 * complicating the probing procedure.
+		 */
+		mtd_total = mtd_concat_create(mtds,
+		                              count,
+		                              "cse0+cse1+nand");
+#else
+		printk(KERN_ERR "%s and %s: Cannot concatenate due to kernel "
+		       "(mis)configuration!\n", map_cse0.name, map_cse1.name);
+		mtd_toal = NULL;
+#endif
+		if (!mtd_total) {
+			printk(KERN_ERR "%s and %s: Concatenation failed!\n",
+			       map_cse0.name, map_cse1.name);
+
+			/* The best we can do now is to only use what we found
+			 * at cse0.
+			 */
+			mtd_total = mtd_cse0;
+			map_destroy(mtd_cse1);
+		}
+	} else {
+		mtd_total = mtd_cse0? mtd_cse0 : mtd_cse1 ? mtd_cse1 : mtd_nand;
+
+	}
+
+	return mtd_total;
+}
+
+extern unsigned long crisv32_nand_boot;
+extern unsigned long crisv32_nand_cramfs_offset;
+
+/*
+ * Probe the flash chip(s) and, if it succeeds, read the partition-table
+ * and register the partitions with MTD.
+ */
+static int __init init_axis_flash(void)
+{
+	struct mtd_info *mymtd;
+	int err = 0;
+	int pidx = 0;
+	struct partitiontable_head *ptable_head = NULL;
+	struct partitiontable_entry *ptable;
+	int use_default_ptable = 1; /* Until proven otherwise. */
+	const char *pmsg = KERN_INFO "  /dev/flash%d at 0x%08x, size 0x%08x\n";
+	static char page[512];
+	size_t len;
+
+#ifndef CONFIG_ETRAXFS_SIM
+	mymtd = flash_probe();
+	mymtd->read(mymtd, CONFIG_ETRAX_PTABLE_SECTOR, 512, &len, page);
+	ptable_head = (struct partitiontable_head *)(page + PARTITION_TABLE_OFFSET);
+
+	if (!mymtd) {
+		/* There's no reason to use this module if no flash chip can
+		 * be identified. Make sure that's understood.
+		 */
+		printk(KERN_INFO "axisflashmap: Found no flash chip.\n");
+	} else {
+		printk(KERN_INFO "%s: 0x%08x bytes of flash memory.\n",
+		       mymtd->name, mymtd->size);
+		axisflash_mtd = mymtd;
+	}
+
+	if (mymtd) {
+		mymtd->owner = THIS_MODULE;
+	}
+	pidx++;  /* First partition is always set to the default. */
+
+	if (ptable_head && (ptable_head->magic == PARTITION_TABLE_MAGIC)
+	    && (ptable_head->size <
+		(MAX_PARTITIONS * sizeof(struct partitiontable_entry) +
+		PARTITIONTABLE_END_MARKER_SIZE))
+	    && (*(unsigned long*)((void*)ptable_head + sizeof(*ptable_head) +
+				  ptable_head->size -
+				  PARTITIONTABLE_END_MARKER_SIZE)
+		== PARTITIONTABLE_END_MARKER)) {
+		/* Looks like a start, sane length and end of a
+		 * partition table, lets check csum etc.
+		 */
+		int ptable_ok = 0;
+		struct partitiontable_entry *max_addr =
+			(struct partitiontable_entry *)
+			((unsigned long)ptable_head + sizeof(*ptable_head) +
+			 ptable_head->size);
+		unsigned long offset = CONFIG_ETRAX_PTABLE_SECTOR;
+		unsigned char *p;
+		unsigned long csum = 0;
+
+		ptable = (struct partitiontable_entry *)
+			((unsigned long)ptable_head + sizeof(*ptable_head));
+
+		/* Lets be PARANOID, and check the checksum. */
+		p = (unsigned char*) ptable;
+
+		while (p <= (unsigned char*)max_addr) {
+			csum += *p++;
+			csum += *p++;
+			csum += *p++;
+			csum += *p++;
+		}
+		ptable_ok = (csum == ptable_head->checksum);
+
+		/* Read the entries and use/show the info.  */
+		printk(KERN_INFO " Found a%s partition table at 0x%p-0x%p.\n",
+		       (ptable_ok ? " valid" : "n invalid"), ptable_head,
+		       max_addr);
+
+		/* We have found a working bootblock.  Now read the
+		 * partition table.  Scan the table.  It ends when
+		 * there is 0xffffffff, that is, empty flash.
+		 */
+		while (ptable_ok
+		       && ptable->offset != 0xffffffff
+		       && ptable < max_addr
+		       && pidx < MAX_PARTITIONS) {
+
+			axis_partitions[pidx].offset = offset + ptable->offset + (crisv32_nand_boot ? 16384 : 0);
+			axis_partitions[pidx].size = ptable->size;
+
+			printk(pmsg, pidx, axis_partitions[pidx].offset,
+			       axis_partitions[pidx].size);
+			pidx++;
+			ptable++;
+		}
+		use_default_ptable = !ptable_ok;
+	}
+
+	if (romfs_in_flash) {
+		/* Add an overlapping device for the root partition (romfs). */
+
+		axis_partitions[pidx].name = "romfs";
+		if (crisv32_nand_boot) {
+			char* data = kmalloc(1024, GFP_KERNEL);
+			int len;
+			int offset = crisv32_nand_cramfs_offset & ~(1024-1);
+			char* tmp;
+
+			mymtd->read(mymtd, offset, 1024, &len, data);
+			tmp = &data[crisv32_nand_cramfs_offset % 512];
+			axis_partitions[pidx].size = *(unsigned*)(tmp + 4);
+			axis_partitions[pidx].offset = crisv32_nand_cramfs_offset;
+			kfree(data);
+		} else {
+			axis_partitions[pidx].size = romfs_length;
+			axis_partitions[pidx].offset = romfs_start - FLASH_CACHED_ADDR;
+		}
+
+		axis_partitions[pidx].mask_flags |= MTD_WRITEABLE;
+
+		printk(KERN_INFO
+                       " Adding readonly flash partition for romfs image:\n");
+		printk(pmsg, pidx, axis_partitions[pidx].offset,
+		       axis_partitions[pidx].size);
+		pidx++;
+	}
+
+        if (mymtd) {
+		if (use_default_ptable) {
+			printk(KERN_INFO " Using default partition table.\n");
+			err = add_mtd_partitions(mymtd, axis_default_partitions,
+						 NUM_DEFAULT_PARTITIONS);
+		} else {
+			err = add_mtd_partitions(mymtd, axis_partitions, pidx);
+		}
+
+		if (err) {
+			panic("axisflashmap could not add MTD partitions!\n");
+		}
+	}
+/* CONFIG_EXTRAXFS_SIM */
+#endif
+
+	if (!romfs_in_flash) {
+		/* Create an RAM device for the root partition (romfs). */
+
+#if !defined(CONFIG_MTD_MTDRAM) || (CONFIG_MTDRAM_TOTAL_SIZE != 0) || (CONFIG_MTDRAM_ABS_POS != 0)
+		/* No use trying to boot this kernel from RAM. Panic! */
+		printk(KERN_EMERG "axisflashmap: Cannot create an MTD RAM "
+		       "device due to kernel (mis)configuration!\n");
+		panic("This kernel cannot boot from RAM!\n");
+#else
+		struct mtd_info *mtd_ram;
+
+		mtd_ram = (struct mtd_info *)kmalloc(sizeof(struct mtd_info),
+						     GFP_KERNEL);
+		if (!mtd_ram) {
+			panic("axisflashmap couldn't allocate memory for "
+			      "mtd_info!\n");
+		}
+
+		printk(KERN_INFO " Adding RAM partition for romfs image:\n");
+		printk(pmsg, pidx, romfs_start, romfs_length);
+
+		err = mtdram_init_device(mtd_ram, (void*)romfs_start,
+		                         romfs_length, "romfs");
+		if (err) {
+			panic("axisflashmap could not initialize MTD RAM "
+			      "device!\n");
+		}
+#endif
+	}
+
+	return err;
+}
+
+/* This adds the above to the kernels init-call chain. */
+module_init(init_axis_flash);
+
+EXPORT_SYMBOL(axisflash_mtd);
diff --git a/arch/cris/arch-v32/drivers/cryptocop.c b/arch/cris/arch-v32/drivers/cryptocop.c
new file mode 100644
index 00000000000..ca72076c630
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/cryptocop.c
@@ -0,0 +1,3522 @@
+/* $Id: cryptocop.c,v 1.13 2005/04/21 17:27:55 henriken Exp $
+ *
+ * Stream co-processor driver for the ETRAX FS
+ *
+ *    Copyright (C) 2003-2005  Axis Communications AB
+ */
+
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/spinlock.h>
+#include <linux/stddef.h>
+
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm/atomic.h>
+
+#include <linux/list.h>
+#include <linux/interrupt.h>
+
+#include <asm/signal.h>
+#include <asm/irq.h>
+
+#include <asm/arch/dma.h>
+#include <asm/arch/hwregs/dma.h>
+#include <asm/arch/hwregs/reg_map.h>
+#include <asm/arch/hwregs/reg_rdwr.h>
+#include <asm/arch/hwregs/intr_vect_defs.h>
+
+#include <asm/arch/hwregs/strcop.h>
+#include <asm/arch/hwregs/strcop_defs.h>
+#include <asm/arch/cryptocop.h>
+
+
+
+#define DESCR_ALLOC_PAD  (31)
+
+struct cryptocop_dma_desc {
+	char *free_buf; /* If non-null will be kfreed in free_cdesc() */
+	dma_descr_data *dma_descr;
+
+	unsigned char dma_descr_buf[sizeof(dma_descr_data) + DESCR_ALLOC_PAD];
+
+	unsigned int from_pool:1; /* If 1 'allocated' from the descriptor pool. */
+	struct cryptocop_dma_desc *next;
+};
+
+
+struct cryptocop_int_operation{
+	void                        *alloc_ptr;
+	cryptocop_session_id        sid;
+
+	dma_descr_context           ctx_out;
+	dma_descr_context           ctx_in;
+
+	/* DMA descriptors allocated by driver. */
+	struct cryptocop_dma_desc   *cdesc_out;
+	struct cryptocop_dma_desc   *cdesc_in;
+
+	/* Strcop config to use. */
+	cryptocop_3des_mode         tdes_mode;
+	cryptocop_csum_type         csum_mode;
+
+	/* DMA descrs provided by consumer. */
+	dma_descr_data              *ddesc_out;
+	dma_descr_data              *ddesc_in;
+};
+
+
+struct cryptocop_tfrm_ctx {
+	cryptocop_tfrm_id tid;
+	unsigned int blocklength;
+
+	unsigned int start_ix;
+
+	struct cryptocop_tfrm_cfg *tcfg;
+	struct cryptocop_transform_ctx *tctx;
+
+	unsigned char previous_src;
+	unsigned char current_src;
+
+	/* Values to use in metadata out. */
+	unsigned char hash_conf;
+	unsigned char hash_mode;
+	unsigned char ciph_conf;
+	unsigned char cbcmode;
+	unsigned char decrypt;
+
+	unsigned int requires_padding:1;
+	unsigned int strict_block_length:1;
+	unsigned int active:1;
+	unsigned int done:1;
+	size_t consumed;
+	size_t produced;
+
+	/* Pad (input) descriptors to put in the DMA out list when the transform
+	 * output is put on the DMA in list. */
+	struct cryptocop_dma_desc *pad_descs;
+
+	struct cryptocop_tfrm_ctx *prev_src;
+	struct cryptocop_tfrm_ctx *curr_src;
+
+	/* Mapping to HW. */
+	unsigned char unit_no;
+};
+
+
+struct cryptocop_private{
+	cryptocop_session_id sid;
+	struct cryptocop_private *next;
+};
+
+/* Session list. */
+
+struct cryptocop_transform_ctx{
+	struct cryptocop_transform_init init;
+	unsigned char dec_key[CRYPTOCOP_MAX_KEY_LENGTH];
+	unsigned int dec_key_set:1;
+
+	struct cryptocop_transform_ctx *next;
+};
+
+
+struct cryptocop_session{
+	cryptocop_session_id sid;
+
+	struct cryptocop_transform_ctx *tfrm_ctx;
+
+	struct cryptocop_session *next;
+};
+
+/* Priority levels for jobs sent to the cryptocop.  Checksum operations from
+   kernel have highest priority since TCPIP stack processing must not
+   be a bottleneck. */
+typedef enum {
+	cryptocop_prio_kernel_csum = 0,
+	cryptocop_prio_kernel = 1,
+	cryptocop_prio_user = 2,
+	cryptocop_prio_no_prios = 3
+} cryptocop_queue_priority;
+
+struct cryptocop_prio_queue{
+	struct list_head jobs;
+	cryptocop_queue_priority prio;
+};
+
+struct cryptocop_prio_job{
+	struct list_head node;
+	cryptocop_queue_priority prio;
+
+	struct cryptocop_operation *oper;
+	struct cryptocop_int_operation *iop;
+};
+
+struct ioctl_job_cb_ctx {
+	unsigned int processed:1;
+};
+
+
+static struct cryptocop_session *cryptocop_sessions = NULL;
+spinlock_t cryptocop_sessions_lock;
+
+/* Next Session ID to assign. */
+static cryptocop_session_id next_sid = 1;
+
+/* Pad for checksum. */
+static const char csum_zero_pad[1] = {0x00};
+
+/* Trash buffer for mem2mem operations. */
+#define MEM2MEM_DISCARD_BUF_LENGTH  (512)
+static unsigned char mem2mem_discard_buf[MEM2MEM_DISCARD_BUF_LENGTH];
+
+/* Descriptor pool. */
+/* FIXME Tweak this value. */
+#define CRYPTOCOP_DESCRIPTOR_POOL_SIZE   (100)
+static struct cryptocop_dma_desc descr_pool[CRYPTOCOP_DESCRIPTOR_POOL_SIZE];
+static struct cryptocop_dma_desc *descr_pool_free_list;
+static int descr_pool_no_free;
+static spinlock_t descr_pool_lock;
+
+/* Lock to stop cryptocop to start processing of a new operation. The holder
+   of this lock MUST call cryptocop_start_job() after it is unlocked. */
+spinlock_t cryptocop_process_lock;
+
+static struct cryptocop_prio_queue cryptocop_job_queues[cryptocop_prio_no_prios];
+static spinlock_t cryptocop_job_queue_lock;
+static struct cryptocop_prio_job *cryptocop_running_job = NULL;
+static spinlock_t running_job_lock;
+
+/* The interrupt handler appends completed jobs to this list. The scehduled
+ * tasklet removes them upon sending the response to the crypto consumer. */
+static struct list_head cryptocop_completed_jobs;
+static spinlock_t cryptocop_completed_jobs_lock;
+
+DECLARE_WAIT_QUEUE_HEAD(cryptocop_ioc_process_wq);
+
+
+/** Local functions. **/
+
+static int cryptocop_open(struct inode *, struct file *);
+
+static int cryptocop_release(struct inode *, struct file *);
+
+static int cryptocop_ioctl(struct inode *inode, struct file *file,
+			   unsigned int cmd, unsigned long arg);
+
+static void cryptocop_start_job(void);
+
+static int cryptocop_job_queue_insert(cryptocop_queue_priority prio, struct cryptocop_operation *operation);
+static int cryptocop_job_setup(struct cryptocop_prio_job **pj, struct cryptocop_operation *operation);
+
+static int cryptocop_job_queue_init(void);
+static void cryptocop_job_queue_close(void);
+
+static int create_md5_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length);
+
+static int create_sha1_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length);
+
+static int transform_ok(struct cryptocop_transform_init *tinit);
+
+static struct cryptocop_session *get_session(cryptocop_session_id sid);
+
+static struct cryptocop_transform_ctx *get_transform_ctx(struct cryptocop_session *sess, cryptocop_tfrm_id tid);
+
+static void delete_internal_operation(struct cryptocop_int_operation *iop);
+
+static void get_aes_decrypt_key(unsigned char *dec_key, const unsigned  char *key, unsigned int keylength);
+
+static int init_stream_coprocessor(void);
+
+static void __exit exit_stream_coprocessor(void);
+
+/*#define LDEBUG*/
+#ifdef LDEBUG
+#define DEBUG(s) s
+#define DEBUG_API(s) s
+static void print_cryptocop_operation(struct cryptocop_operation *cop);
+static void print_dma_descriptors(struct cryptocop_int_operation *iop);
+static void print_strcop_crypto_op(struct strcop_crypto_op *cop);
+static void print_lock_status(void);
+static void print_user_dma_lists(struct cryptocop_dma_list_operation *dma_op);
+#define assert(s) do{if (!(s)) panic(#s);} while(0);
+#else
+#define DEBUG(s)
+#define DEBUG_API(s)
+#define assert(s)
+#endif
+
+
+/* Transform constants. */
+#define DES_BLOCK_LENGTH   (8)
+#define AES_BLOCK_LENGTH   (16)
+#define MD5_BLOCK_LENGTH   (64)
+#define SHA1_BLOCK_LENGTH  (64)
+#define CSUM_BLOCK_LENGTH  (2)
+#define MD5_STATE_LENGTH   (16)
+#define SHA1_STATE_LENGTH  (20)
+
+/* The device number. */
+#define CRYPTOCOP_MAJOR    (254)
+#define CRYPTOCOP_MINOR    (0)
+
+
+
+struct file_operations cryptocop_fops = {
+	owner: THIS_MODULE,
+	open: cryptocop_open,
+	release: cryptocop_release,
+	ioctl: cryptocop_ioctl
+};
+
+
+static void free_cdesc(struct cryptocop_dma_desc *cdesc)
+{
+	DEBUG(printk("free_cdesc: cdesc 0x%p, from_pool=%d\n", cdesc, cdesc->from_pool));
+	if (cdesc->free_buf) kfree(cdesc->free_buf);
+
+	if (cdesc->from_pool) {
+		unsigned long int flags;
+		spin_lock_irqsave(&descr_pool_lock, flags);
+		cdesc->next = descr_pool_free_list;
+		descr_pool_free_list = cdesc;
+		++descr_pool_no_free;
+		spin_unlock_irqrestore(&descr_pool_lock, flags);
+	} else {
+		kfree(cdesc);
+	}
+}
+
+
+static struct cryptocop_dma_desc *alloc_cdesc(int alloc_flag)
+{
+	int use_pool = (alloc_flag & GFP_ATOMIC) ? 1 : 0;
+	struct cryptocop_dma_desc *cdesc;
+
+	if (use_pool) {
+		unsigned long int flags;
+		spin_lock_irqsave(&descr_pool_lock, flags);
+		if (!descr_pool_free_list) {
+			spin_unlock_irqrestore(&descr_pool_lock, flags);
+			DEBUG_API(printk("alloc_cdesc: pool is empty\n"));
+			return NULL;
+		}
+		cdesc = descr_pool_free_list;
+		descr_pool_free_list = descr_pool_free_list->next;
+		--descr_pool_no_free;
+		spin_unlock_irqrestore(&descr_pool_lock, flags);
+		cdesc->from_pool = 1;
+	} else {
+		cdesc = kmalloc(sizeof(struct cryptocop_dma_desc), alloc_flag);
+		if (!cdesc) {
+			DEBUG_API(printk("alloc_cdesc: kmalloc\n"));
+			return NULL;
+		}
+		cdesc->from_pool = 0;
+	}
+	cdesc->dma_descr = (dma_descr_data*)(((unsigned long int)cdesc + offsetof(struct cryptocop_dma_desc, dma_descr_buf) + DESCR_ALLOC_PAD) & ~0x0000001F);
+
+	cdesc->next = NULL;
+
+	cdesc->free_buf = NULL;
+	cdesc->dma_descr->out_eop = 0;
+	cdesc->dma_descr->in_eop = 0;
+	cdesc->dma_descr->intr = 0;
+	cdesc->dma_descr->eol = 0;
+	cdesc->dma_descr->wait = 0;
+	cdesc->dma_descr->buf = NULL;
+	cdesc->dma_descr->after = NULL;
+
+	DEBUG_API(printk("alloc_cdesc: return 0x%p, cdesc->dma_descr=0x%p, from_pool=%d\n", cdesc, cdesc->dma_descr, cdesc->from_pool));
+	return cdesc;
+}
+
+
+static void setup_descr_chain(struct cryptocop_dma_desc *cd)
+{
+	DEBUG(printk("setup_descr_chain: entering\n"));
+	while (cd) {
+		if (cd->next) {
+			cd->dma_descr->next = (dma_descr_data*)virt_to_phys(cd->next->dma_descr);
+		} else {
+			cd->dma_descr->next = NULL;
+		}
+		cd = cd->next;
+	}
+	DEBUG(printk("setup_descr_chain: exit\n"));
+}
+
+
+/* Create a pad descriptor for the transform.
+ * Return -1 for error, 0 if pad created. */
+static int create_pad_descriptor(struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **pad_desc, int alloc_flag)
+{
+	struct cryptocop_dma_desc        *cdesc = NULL;
+	int                              error = 0;
+	struct strcop_meta_out           mo = {
+		.ciphsel = src_none,
+		.hashsel = src_none,
+		.csumsel = src_none
+	};
+	char                             *pad;
+	size_t                           plen;
+
+	DEBUG(printk("create_pad_descriptor: start.\n"));
+	/* Setup pad descriptor. */
+
+	DEBUG(printk("create_pad_descriptor: setting up padding.\n"));
+	cdesc = alloc_cdesc(alloc_flag);
+	if (!cdesc){
+		DEBUG_API(printk("create_pad_descriptor: alloc pad desc\n"));
+		goto error_cleanup;
+	}
+	switch (tc->unit_no) {
+	case src_md5:
+		error = create_md5_pad(alloc_flag, tc->consumed, &pad, &plen);
+		if (error){
+			DEBUG_API(printk("create_pad_descriptor: create_md5_pad_failed\n"));
+			goto error_cleanup;
+		}
+		cdesc->free_buf = pad;
+		mo.hashsel = src_dma;
+		mo.hashconf = tc->hash_conf;
+		mo.hashmode = tc->hash_mode;
+		break;
+	case src_sha1:
+		error = create_sha1_pad(alloc_flag, tc->consumed, &pad, &plen);
+		if (error){
+			DEBUG_API(printk("create_pad_descriptor: create_sha1_pad_failed\n"));
+			goto error_cleanup;
+		}
+		cdesc->free_buf = pad;
+		mo.hashsel = src_dma;
+		mo.hashconf = tc->hash_conf;
+		mo.hashmode = tc->hash_mode;
+		break;
+	case src_csum:
+		if (tc->consumed % tc->blocklength){
+			pad = (char*)csum_zero_pad;
+			plen = 1;
+		} else {
+			pad = (char*)cdesc; /* Use any pointer. */
+			plen = 0;
+		}
+		mo.csumsel = src_dma;
+		break;
+	}
+	cdesc->dma_descr->wait = 1;
+	cdesc->dma_descr->out_eop = 1; /* Since this is a pad output is pushed.  EOP is ok here since the padded unit is the only one active. */
+	cdesc->dma_descr->buf = (char*)virt_to_phys((char*)pad);
+	cdesc->dma_descr->after = cdesc->dma_descr->buf + plen;
+
+	cdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, mo);
+	*pad_desc = cdesc;
+
+	return 0;
+
+ error_cleanup:
+	if (cdesc) free_cdesc(cdesc);
+	return -1;
+}
+
+
+static int setup_key_dl_desc(struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **kd, int alloc_flag)
+{
+	struct cryptocop_dma_desc  *key_desc = alloc_cdesc(alloc_flag);
+	struct strcop_meta_out     mo = {0};
+
+	DEBUG(printk("setup_key_dl_desc\n"));
+
+	if (!key_desc) {
+		DEBUG_API(printk("setup_key_dl_desc: failed descriptor allocation.\n"));
+		return -ENOMEM;
+	}
+
+	/* Download key. */
+	if ((tc->tctx->init.alg == cryptocop_alg_aes) && (tc->tcfg->flags & CRYPTOCOP_DECRYPT)) {
+		/* Precook the AES decrypt key. */
+		if (!tc->tctx->dec_key_set){
+			get_aes_decrypt_key(tc->tctx->dec_key, tc->tctx->init.key, tc->tctx->init.keylen);
+			tc->tctx->dec_key_set = 1;
+		}
+		key_desc->dma_descr->buf = (char*)virt_to_phys(tc->tctx->dec_key);
+		key_desc->dma_descr->after = key_desc->dma_descr->buf + tc->tctx->init.keylen/8;
+	} else {
+		key_desc->dma_descr->buf = (char*)virt_to_phys(tc->tctx->init.key);
+		key_desc->dma_descr->after = key_desc->dma_descr->buf + tc->tctx->init.keylen/8;
+	}
+	/* Setup metadata. */
+	mo.dlkey = 1;
+	switch (tc->tctx->init.keylen) {
+	case 64:
+		mo.decrypt = 0;
+		mo.hashmode = 0;
+		break;
+	case 128:
+		mo.decrypt = 0;
+		mo.hashmode = 1;
+		break;
+	case 192:
+		mo.decrypt = 1;
+		mo.hashmode = 0;
+		break;
+	case 256:
+		mo.decrypt = 1;
+		mo.hashmode = 1;
+		break;
+	default:
+		break;
+	}
+	mo.ciphsel = mo.hashsel = mo.csumsel = src_none;
+	key_desc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, mo);
+
+	key_desc->dma_descr->out_eop = 1;
+	key_desc->dma_descr->wait = 1;
+	key_desc->dma_descr->intr = 0;
+
+	*kd = key_desc;
+	return 0;
+}
+
+static int setup_cipher_iv_desc(struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **id, int alloc_flag)
+{
+	struct cryptocop_dma_desc  *iv_desc = alloc_cdesc(alloc_flag);
+	struct strcop_meta_out     mo = {0};
+
+	DEBUG(printk("setup_cipher_iv_desc\n"));
+
+	if (!iv_desc) {
+		DEBUG_API(printk("setup_cipher_iv_desc: failed CBC IV descriptor allocation.\n"));
+		return -ENOMEM;
+	}
+	/* Download IV. */
+	iv_desc->dma_descr->buf = (char*)virt_to_phys(tc->tcfg->iv);
+	iv_desc->dma_descr->after = iv_desc->dma_descr->buf + tc->blocklength;
+
+	/* Setup metadata. */
+	mo.hashsel = mo.csumsel = src_none;
+	mo.ciphsel = src_dma;
+	mo.ciphconf = tc->ciph_conf;
+	mo.cbcmode = tc->cbcmode;
+
+	iv_desc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, mo);
+
+	iv_desc->dma_descr->out_eop = 0;
+	iv_desc->dma_descr->wait = 1;
+	iv_desc->dma_descr->intr = 0;
+
+	*id = iv_desc;
+	return 0;
+}
+
+/* Map the ouput length of the transform to operation output starting on the inject index. */
+static int create_input_descriptors(struct cryptocop_operation *operation, struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **id, int alloc_flag)
+{
+	int                        err = 0;
+	struct cryptocop_dma_desc  head = {0};
+	struct cryptocop_dma_desc  *outdesc = &head;
+	size_t                     iov_offset = 0;
+	size_t                     out_ix = 0;
+	int                        outiov_ix = 0;
+	struct strcop_meta_in      mi = {0};
+
+	size_t                     out_length = tc->produced;
+	int                        rem_length;
+	int                        dlength;
+
+	assert(out_length != 0);
+	if (((tc->produced + tc->tcfg->inject_ix) > operation->tfrm_op.outlen) || (tc->produced && (operation->tfrm_op.outlen == 0))) {
+		DEBUG_API(printk("create_input_descriptors: operation outdata too small\n"));
+		return -EINVAL;
+	}
+	/* Traverse the out iovec until the result inject index is reached. */
+	while ((outiov_ix < operation->tfrm_op.outcount) && ((out_ix + operation->tfrm_op.outdata[outiov_ix].iov_len) <= tc->tcfg->inject_ix)){
+		out_ix += operation->tfrm_op.outdata[outiov_ix].iov_len;
+		outiov_ix++;
+	}
+	if (outiov_ix >= operation->tfrm_op.outcount){
+		DEBUG_API(printk("create_input_descriptors: operation outdata too small\n"));
+		return -EINVAL;
+	}
+	iov_offset = tc->tcfg->inject_ix - out_ix;
+	mi.dmasel = tc->unit_no;
+
+	/* Setup the output descriptors. */
+	while ((out_length > 0) && (outiov_ix < operation->tfrm_op.outcount)) {
+		outdesc->next = alloc_cdesc(alloc_flag);
+		if (!outdesc->next) {
+			DEBUG_API(printk("create_input_descriptors: alloc_cdesc\n"));
+			err = -ENOMEM;
+			goto error_cleanup;
+		}
+		outdesc = outdesc->next;
+		rem_length = operation->tfrm_op.outdata[outiov_ix].iov_len - iov_offset;
+		dlength = (out_length < rem_length) ? out_length : rem_length;
+
+		DEBUG(printk("create_input_descriptors:\n"
+			     "outiov_ix=%d, rem_length=%d, dlength=%d\n"
+			     "iov_offset=%d, outdata[outiov_ix].iov_len=%d\n"
+			     "outcount=%d, outiov_ix=%d\n",
+			     outiov_ix, rem_length, dlength, iov_offset, operation->tfrm_op.outdata[outiov_ix].iov_len, operation->tfrm_op.outcount, outiov_ix));
+
+		outdesc->dma_descr->buf = (char*)virt_to_phys(operation->tfrm_op.outdata[outiov_ix].iov_base + iov_offset);
+		outdesc->dma_descr->after = outdesc->dma_descr->buf + dlength;
+		outdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi);
+
+		out_length -= dlength;
+		iov_offset += dlength;
+		if (iov_offset >= operation->tfrm_op.outdata[outiov_ix].iov_len) {
+			iov_offset = 0;
+			++outiov_ix;
+		}
+	}
+	if (out_length > 0){
+		DEBUG_API(printk("create_input_descriptors: not enough room for output, %d remained\n", out_length));
+		err = -EINVAL;
+		goto error_cleanup;
+	}
+	/* Set sync in last descriptor. */
+	mi.sync = 1;
+	outdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi);
+
+	*id = head.next;
+	return 0;
+
+ error_cleanup:
+	while (head.next) {
+		outdesc = head.next->next;
+		free_cdesc(head.next);
+		head.next = outdesc;
+	}
+	return err;
+}
+
+
+static int create_output_descriptors(struct cryptocop_operation *operation, int *iniov_ix, int *iniov_offset, size_t desc_len, struct cryptocop_dma_desc **current_out_cdesc, struct strcop_meta_out *meta_out, int alloc_flag)
+{
+	while (desc_len != 0) {
+		struct cryptocop_dma_desc  *cdesc;
+		int                        rem_length = operation->tfrm_op.indata[*iniov_ix].iov_len - *iniov_offset;
+		int                        dlength = (desc_len < rem_length) ? desc_len : rem_length;
+
+		cdesc = alloc_cdesc(alloc_flag);
+		if (!cdesc) {
+			DEBUG_API(printk("create_output_descriptors: alloc_cdesc\n"));
+			return -ENOMEM;
+		}
+		(*current_out_cdesc)->next = cdesc;
+		(*current_out_cdesc) = cdesc;
+
+		cdesc->free_buf = NULL;
+
+		cdesc->dma_descr->buf = (char*)virt_to_phys(operation->tfrm_op.indata[*iniov_ix].iov_base + *iniov_offset);
+		cdesc->dma_descr->after = cdesc->dma_descr->buf + dlength;
+
+		desc_len -= dlength;
+		*iniov_offset += dlength;
+		assert(desc_len >= 0);
+		if (*iniov_offset >= operation->tfrm_op.indata[*iniov_ix].iov_len) {
+			*iniov_offset = 0;
+			++(*iniov_ix);
+			if (*iniov_ix > operation->tfrm_op.incount) {
+				DEBUG_API(printk("create_output_descriptors: not enough indata in operation."));
+				return  -EINVAL;
+			}
+		}
+		cdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, (*meta_out));
+	} /* while (desc_len != 0) */
+	/* Last DMA descriptor gets a 'wait' bit to signal expected change in metadata. */
+	(*current_out_cdesc)->dma_descr->wait = 1; /* This will set extraneous WAIT in some situations, e.g. when padding hashes and checksums. */
+
+	return 0;
+}
+
+
+static int append_input_descriptors(struct cryptocop_operation *operation, struct cryptocop_dma_desc **current_in_cdesc, struct cryptocop_dma_desc **current_out_cdesc, struct cryptocop_tfrm_ctx *tc, int alloc_flag)
+{
+	DEBUG(printk("append_input_descriptors, tc=0x%p, unit_no=%d\n", tc, tc->unit_no));
+	if (tc->tcfg) {
+		int                        failed = 0;
+		struct cryptocop_dma_desc  *idescs = NULL;
+		DEBUG(printk("append_input_descriptors: pushing output, consumed %d produced %d bytes.\n", tc->consumed, tc->produced));
+		if (tc->pad_descs) {
+			DEBUG(printk("append_input_descriptors: append pad descriptors to DMA out list.\n"));
+			while (tc->pad_descs) {
+				DEBUG(printk("append descriptor 0x%p\n", tc->pad_descs));
+				(*current_out_cdesc)->next = tc->pad_descs;
+				tc->pad_descs = tc->pad_descs->next;
+				(*current_out_cdesc) = (*current_out_cdesc)->next;
+			}
+		}
+
+		/* Setup and append output descriptors to DMA in list. */
+		if (tc->unit_no == src_dma){
+			/* mem2mem.  Setup DMA in descriptors to discard all input prior to the requested mem2mem data. */
+			struct strcop_meta_in mi = {.sync = 0, .dmasel = src_dma};
+			unsigned int start_ix = tc->start_ix;
+			while (start_ix){
+				unsigned int desclen = start_ix < MEM2MEM_DISCARD_BUF_LENGTH ? start_ix : MEM2MEM_DISCARD_BUF_LENGTH;
+				(*current_in_cdesc)->next = alloc_cdesc(alloc_flag);
+				if (!(*current_in_cdesc)->next){
+					DEBUG_API(printk("append_input_descriptors: alloc_cdesc mem2mem discard failed\n"));
+					return -ENOMEM;
+				}
+				(*current_in_cdesc) = (*current_in_cdesc)->next;
+				(*current_in_cdesc)->dma_descr->buf = (char*)virt_to_phys(mem2mem_discard_buf);
+				(*current_in_cdesc)->dma_descr->after = (*current_in_cdesc)->dma_descr->buf + desclen;
+				(*current_in_cdesc)->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi);
+				start_ix -= desclen;
+			}
+			mi.sync = 1;
+			(*current_in_cdesc)->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi);
+		}
+
+		failed = create_input_descriptors(operation, tc, &idescs, alloc_flag);
+		if (failed){
+			DEBUG_API(printk("append_input_descriptors: output descriptor setup failed\n"));
+			return failed;
+		}
+		DEBUG(printk("append_input_descriptors: append output descriptors to DMA in list.\n"));
+		while (idescs) {
+			DEBUG(printk("append descriptor 0x%p\n", idescs));
+			(*current_in_cdesc)->next = idescs;
+			idescs = idescs->next;
+			(*current_in_cdesc) = (*current_in_cdesc)->next;
+		}
+	}
+	return 0;
+}
+
+
+
+static int cryptocop_setup_dma_list(struct cryptocop_operation *operation, struct cryptocop_int_operation **int_op, int alloc_flag)
+{
+	struct cryptocop_session *sess;
+	struct cryptocop_transform_ctx *tctx;
+
+	struct cryptocop_tfrm_ctx digest_ctx = {
+		.previous_src = src_none,
+		.current_src = src_none,
+		.start_ix = 0,
+		.requires_padding = 1,
+		.strict_block_length = 0,
+		.hash_conf = 0,
+		.hash_mode = 0,
+		.ciph_conf = 0,
+		.cbcmode = 0,
+		.decrypt = 0,
+		.consumed = 0,
+		.produced = 0,
+		.pad_descs = NULL,
+		.active = 0,
+		.done = 0,
+		.prev_src = NULL,
+		.curr_src = NULL,
+		.tcfg = NULL};
+	struct cryptocop_tfrm_ctx cipher_ctx = {
+		.previous_src = src_none,
+		.current_src = src_none,
+		.start_ix = 0,
+		.requires_padding = 0,
+		.strict_block_length = 1,
+		.hash_conf = 0,
+		.hash_mode = 0,
+		.ciph_conf = 0,
+		.cbcmode = 0,
+		.decrypt = 0,
+		.consumed = 0,
+		.produced = 0,
+		.pad_descs = NULL,
+		.active = 0,
+		.done = 0,
+		.prev_src = NULL,
+		.curr_src = NULL,
+		.tcfg = NULL};
+	struct cryptocop_tfrm_ctx csum_ctx = {
+		.previous_src = src_none,
+		.current_src = src_none,
+		.start_ix = 0,
+		.blocklength = 2,
+		.requires_padding = 1,
+		.strict_block_length = 0,
+		.hash_conf = 0,
+		.hash_mode = 0,
+		.ciph_conf = 0,
+		.cbcmode = 0,
+		.decrypt = 0,
+		.consumed = 0,
+		.produced = 0,
+		.pad_descs = NULL,
+		.active = 0,
+		.done = 0,
+		.tcfg = NULL,
+		.prev_src = NULL,
+		.curr_src = NULL,
+		.unit_no = src_csum};
+	struct cryptocop_tfrm_cfg *tcfg = operation->tfrm_op.tfrm_cfg;
+
+	unsigned int indata_ix = 0;
+
+	/* iovec accounting. */
+	int iniov_ix = 0;
+	int iniov_offset = 0;
+
+	/* Operation descriptor cfg traversal pointer. */
+	struct cryptocop_desc *odsc;
+
+	int failed = 0;
+	/* List heads for allocated descriptors. */
+	struct cryptocop_dma_desc out_cdesc_head = {0};
+	struct cryptocop_dma_desc in_cdesc_head = {0};
+
+	struct cryptocop_dma_desc *current_out_cdesc = &out_cdesc_head;
+	struct cryptocop_dma_desc *current_in_cdesc = &in_cdesc_head;
+
+	struct cryptocop_tfrm_ctx *output_tc = NULL;
+	void                      *iop_alloc_ptr;
+
+	assert(operation != NULL);
+	assert(int_op != NULL);
+
+	DEBUG(printk("cryptocop_setup_dma_list: start\n"));
+	DEBUG(print_cryptocop_operation(operation));
+
+	sess = get_session(operation->sid);
+	if (!sess) {
+		DEBUG_API(printk("cryptocop_setup_dma_list: no session found for operation.\n"));
+		failed = -EINVAL;
+		goto error_cleanup;
+	}
+	iop_alloc_ptr = kmalloc(DESCR_ALLOC_PAD + sizeof(struct cryptocop_int_operation), alloc_flag);
+	if (!iop_alloc_ptr) {
+		DEBUG_API(printk("cryptocop_setup_dma_list:  kmalloc cryptocop_int_operation\n"));
+		failed = -ENOMEM;
+		goto error_cleanup;
+	}
+	(*int_op) = (struct cryptocop_int_operation*)(((unsigned long int)(iop_alloc_ptr + DESCR_ALLOC_PAD + offsetof(struct cryptocop_int_operation, ctx_out)) & ~0x0000001F) - offsetof(struct cryptocop_int_operation, ctx_out));
+	DEBUG(memset((*int_op), 0xff, sizeof(struct cryptocop_int_operation)));
+	(*int_op)->alloc_ptr = iop_alloc_ptr;
+	DEBUG(printk("cryptocop_setup_dma_list: *int_op=0x%p, alloc_ptr=0x%p\n", *int_op, (*int_op)->alloc_ptr));
+
+	(*int_op)->sid = operation->sid;
+	(*int_op)->cdesc_out = NULL;
+	(*int_op)->cdesc_in = NULL;
+	(*int_op)->tdes_mode = cryptocop_3des_ede;
+	(*int_op)->csum_mode = cryptocop_csum_le;
+	(*int_op)->ddesc_out = NULL;
+	(*int_op)->ddesc_in = NULL;
+
+	/* Scan operation->tfrm_op.tfrm_cfg for bad configuration and set up the local contexts. */
+	if (!tcfg) {
+		DEBUG_API(printk("cryptocop_setup_dma_list: no configured transforms in operation.\n"));
+		failed = -EINVAL;
+		goto error_cleanup;
+	}
+	while (tcfg) {
+		tctx = get_transform_ctx(sess, tcfg->tid);
+		if (!tctx) {
+			DEBUG_API(printk("cryptocop_setup_dma_list: no transform id %d in session.\n", tcfg->tid));
+			failed = -EINVAL;
+			goto error_cleanup;
+		}
+		if (tcfg->inject_ix > operation->tfrm_op.outlen){
+			DEBUG_API(printk("cryptocop_setup_dma_list: transform id %d inject_ix (%d) > operation->tfrm_op.outlen(%d)", tcfg->tid, tcfg->inject_ix, operation->tfrm_op.outlen));
+			failed = -EINVAL;
+			goto error_cleanup;
+		}
+		switch (tctx->init.alg){
+		case cryptocop_alg_mem2mem:
+			if (cipher_ctx.tcfg != NULL){
+				DEBUG_API(printk("cryptocop_setup_dma_list: multiple ciphers in operation.\n"));
+				failed = -EINVAL;
+				goto error_cleanup;
+			}
+			/* mem2mem is handled as a NULL cipher. */
+			cipher_ctx.cbcmode = 0;
+			cipher_ctx.decrypt = 0;
+			cipher_ctx.blocklength = 1;
+			cipher_ctx.ciph_conf = 0;
+			cipher_ctx.unit_no = src_dma;
+			cipher_ctx.tcfg = tcfg;
+			cipher_ctx.tctx = tctx;
+			break;
+		case cryptocop_alg_des:
+		case cryptocop_alg_3des:
+		case cryptocop_alg_aes:
+			/* cipher */
+			if (cipher_ctx.tcfg != NULL){
+				DEBUG_API(printk("cryptocop_setup_dma_list: multiple ciphers in operation.\n"));
+				failed = -EINVAL;
+				goto error_cleanup;
+			}
+			cipher_ctx.tcfg = tcfg;
+			cipher_ctx.tctx = tctx;
+			if (cipher_ctx.tcfg->flags & CRYPTOCOP_DECRYPT){
+				cipher_ctx.decrypt = 1;
+			}
+			switch (tctx->init.cipher_mode) {
+			case cryptocop_cipher_mode_ecb:
+				cipher_ctx.cbcmode = 0;
+				break;
+			case cryptocop_cipher_mode_cbc:
+				cipher_ctx.cbcmode = 1;
+				break;
+			default:
+				DEBUG_API(printk("cryptocop_setup_dma_list: cipher_ctx, bad cipher mode==%d\n", tctx->init.cipher_mode));
+				failed = -EINVAL;
+				goto error_cleanup;
+			}
+			DEBUG(printk("cryptocop_setup_dma_list: cipher_ctx, set CBC mode==%d\n", cipher_ctx.cbcmode));
+			switch (tctx->init.alg){
+			case cryptocop_alg_des:
+				cipher_ctx.ciph_conf = 0;
+				cipher_ctx.unit_no = src_des;
+				cipher_ctx.blocklength = DES_BLOCK_LENGTH;
+				break;
+			case cryptocop_alg_3des:
+				cipher_ctx.ciph_conf = 1;
+				cipher_ctx.unit_no = src_des;
+				cipher_ctx.blocklength = DES_BLOCK_LENGTH;
+				break;
+			case cryptocop_alg_aes:
+				cipher_ctx.ciph_conf = 2;
+				cipher_ctx.unit_no = src_aes;
+				cipher_ctx.blocklength = AES_BLOCK_LENGTH;
+				break;
+			default:
+				panic("cryptocop_setup_dma_list: impossible algorithm %d\n", tctx->init.alg);
+			}
+			(*int_op)->tdes_mode = tctx->init.tdes_mode;
+			break;
+		case cryptocop_alg_md5:
+		case cryptocop_alg_sha1:
+			/* digest */
+			if (digest_ctx.tcfg != NULL){
+				DEBUG_API(printk("cryptocop_setup_dma_list: multiple digests in operation.\n"));
+				failed = -EINVAL;
+				goto error_cleanup;
+			}
+			digest_ctx.tcfg = tcfg;
+			digest_ctx.tctx = tctx;
+			digest_ctx.hash_mode = 0; /* Don't use explicit IV in this API. */
+			switch (tctx->init.alg){
+			case cryptocop_alg_md5:
+				digest_ctx.blocklength = MD5_BLOCK_LENGTH;
+				digest_ctx.unit_no = src_md5;
+				digest_ctx.hash_conf = 1; /* 1 => MD-5 */
+				break;
+			case cryptocop_alg_sha1:
+				digest_ctx.blocklength = SHA1_BLOCK_LENGTH;
+				digest_ctx.unit_no = src_sha1;
+				digest_ctx.hash_conf = 0; /* 0 => SHA-1 */
+				break;
+			default:
+				panic("cryptocop_setup_dma_list: impossible digest algorithm\n");
+			}
+			break;
+		case cryptocop_alg_csum:
+			/* digest */
+			if (csum_ctx.tcfg != NULL){
+				DEBUG_API(printk("cryptocop_setup_dma_list: multiple checksums in operation.\n"));
+				failed = -EINVAL;
+				goto error_cleanup;
+			}
+			(*int_op)->csum_mode = tctx->init.csum_mode;
+			csum_ctx.tcfg = tcfg;
+			csum_ctx.tctx = tctx;
+			break;
+		default:
+			/* no algorithm. */
+			DEBUG_API(printk("cryptocop_setup_dma_list: invalid algorithm %d specified in tfrm %d.\n", tctx->init.alg, tcfg->tid));
+			failed = -EINVAL;
+			goto error_cleanup;
+		}
+		tcfg = tcfg->next;
+	}
+	/* Download key if a cipher is used. */
+	if (cipher_ctx.tcfg && (cipher_ctx.tctx->init.alg != cryptocop_alg_mem2mem)){
+		struct cryptocop_dma_desc  *key_desc = NULL;
+
+		failed = setup_key_dl_desc(&cipher_ctx, &key_desc, alloc_flag);
+		if (failed) {
+			DEBUG_API(printk("cryptocop_setup_dma_list: setup key dl\n"));
+			goto error_cleanup;
+		}
+		current_out_cdesc->next = key_desc;
+		current_out_cdesc = key_desc;
+		indata_ix += (unsigned int)(key_desc->dma_descr->after - key_desc->dma_descr->buf);
+
+		/* Download explicit IV if a cipher is used and CBC mode and explicit IV selected. */
+		if ((cipher_ctx.tctx->init.cipher_mode == cryptocop_cipher_mode_cbc) && (cipher_ctx.tcfg->flags & CRYPTOCOP_EXPLICIT_IV)) {
+			struct cryptocop_dma_desc  *iv_desc = NULL;
+
+			DEBUG(printk("cryptocop_setup_dma_list: setup cipher CBC IV descriptor.\n"));
+
+			failed = setup_cipher_iv_desc(&cipher_ctx, &iv_desc, alloc_flag);
+			if (failed) {
+				DEBUG_API(printk("cryptocop_setup_dma_list: CBC IV descriptor.\n"));
+				goto error_cleanup;
+			}
+			current_out_cdesc->next = iv_desc;
+			current_out_cdesc = iv_desc;
+			indata_ix += (unsigned int)(iv_desc->dma_descr->after - iv_desc->dma_descr->buf);
+		}
+	}
+
+	/* Process descriptors. */
+	odsc = operation->tfrm_op.desc;
+	while (odsc) {
+		struct cryptocop_desc_cfg   *dcfg = odsc->cfg;
+		struct strcop_meta_out      meta_out = {0};
+		size_t                      desc_len = odsc->length;
+		int                         active_count, eop_needed_count;
+
+		output_tc = NULL;
+
+		DEBUG(printk("cryptocop_setup_dma_list: parsing an operation descriptor\n"));
+
+		while (dcfg) {
+			struct cryptocop_tfrm_ctx  *tc = NULL;
+
+			DEBUG(printk("cryptocop_setup_dma_list: parsing an operation descriptor configuration.\n"));
+			/* Get the local context for the transform and mark it as the output unit if it produces output. */
+			if (digest_ctx.tcfg && (digest_ctx.tcfg->tid == dcfg->tid)){
+				tc = &digest_ctx;
+			} else if (cipher_ctx.tcfg && (cipher_ctx.tcfg->tid == dcfg->tid)){
+				tc = &cipher_ctx;
+			} else if (csum_ctx.tcfg && (csum_ctx.tcfg->tid == dcfg->tid)){
+				tc = &csum_ctx;
+			}
+			if (!tc) {
+				DEBUG_API(printk("cryptocop_setup_dma_list: invalid transform %d specified in descriptor.\n", dcfg->tid));
+				failed = -EINVAL;
+				goto error_cleanup;
+			}
+			if (tc->done) {
+				DEBUG_API(printk("cryptocop_setup_dma_list: completed transform %d reused.\n", dcfg->tid));
+				failed = -EINVAL;
+				goto error_cleanup;
+			}
+			if (!tc->active) {
+				tc->start_ix = indata_ix;
+				tc->active = 1;
+			}
+
+			tc->previous_src = tc->current_src;
+			tc->prev_src = tc->curr_src;
+			/* Map source unit id to DMA source config. */
+			switch (dcfg->src){
+			case cryptocop_source_dma:
+				tc->current_src = src_dma;
+				break;
+			case cryptocop_source_des:
+				tc->current_src = src_des;
+				break;
+			case cryptocop_source_3des:
+				tc->current_src = src_des;
+				break;
+			case cryptocop_source_aes:
+				tc->current_src = src_aes;
+				break;
+			case cryptocop_source_md5:
+			case cryptocop_source_sha1:
+			case cryptocop_source_csum:
+			case cryptocop_source_none:
+			default:
+				/* We do not allow using accumulating style units (SHA-1, MD5, checksum) as sources to other units.
+				 */
+				DEBUG_API(printk("cryptocop_setup_dma_list: bad unit source configured %d.\n", dcfg->src));
+				failed = -EINVAL;
+				goto error_cleanup;
+			}
+			if (tc->current_src != src_dma) {
+				/* Find the unit we are sourcing from. */
+				if (digest_ctx.unit_no == tc->current_src){
+					tc->curr_src = &digest_ctx;
+				} else if (cipher_ctx.unit_no == tc->current_src){
+					tc->curr_src = &cipher_ctx;
+				} else if (csum_ctx.unit_no == tc->current_src){
+					tc->curr_src = &csum_ctx;
+				}
+				if ((tc->curr_src == tc) && (tc->unit_no != src_dma)){
+					DEBUG_API(printk("cryptocop_setup_dma_list: unit %d configured to source from itself.\n", tc->unit_no));
+					failed = -EINVAL;
+					goto error_cleanup;
+				}
+			} else {
+				tc->curr_src = NULL;
+			}
+
+			/* Detect source switch. */
+			DEBUG(printk("cryptocop_setup_dma_list: tc->active=%d tc->unit_no=%d tc->current_src=%d tc->previous_src=%d, tc->curr_src=0x%p, tc->prev_srv=0x%p\n", tc->active, tc->unit_no, tc->current_src, tc->previous_src, tc->curr_src, tc->prev_src));
+			if (tc->active && (tc->current_src != tc->previous_src)) {
+				/* Only allow source switch when both the old source unit and the new one have
+				 * no pending data to process (i.e. the consumed length must be a multiple of the
+				 * transform blocklength). */
+				/* Note: if the src == NULL we are actually sourcing from DMA out. */
+				if (((tc->prev_src != NULL) && (tc->prev_src->consumed % tc->prev_src->blocklength)) ||
+				    ((tc->curr_src != NULL) && (tc->curr_src->consumed % tc->curr_src->blocklength)))
+				{
+					DEBUG_API(printk("cryptocop_setup_dma_list: can only disconnect from or connect to a unit on a multiple of the blocklength, old: cons=%d, prod=%d, block=%d, new: cons=%d prod=%d, block=%d.\n", tc->prev_src ? tc->prev_src->consumed : INT_MIN, tc->prev_src ? tc->prev_src->produced : INT_MIN, tc->prev_src ? tc->prev_src->blocklength : INT_MIN, tc->curr_src ? tc->curr_src->consumed : INT_MIN, tc->curr_src ? tc->curr_src->produced : INT_MIN, tc->curr_src ? tc->curr_src->blocklength : INT_MIN));
+					failed = -EINVAL;
+					goto error_cleanup;
+				}
+			}
+			/* Detect unit deactivation. */
+			if (dcfg->last) {
+				/* Length check of this is handled below. */
+				tc->done = 1;
+			}
+			dcfg = dcfg->next;
+		} /* while (dcfg) */
+		DEBUG(printk("cryptocop_setup_dma_list: parsing operation descriptor configuration complete.\n"));
+
+		if (cipher_ctx.active && (cipher_ctx.curr_src != NULL) && !cipher_ctx.curr_src->active){
+			DEBUG_API(printk("cryptocop_setup_dma_list: cipher source from inactive unit %d\n", cipher_ctx.curr_src->unit_no));
+			failed = -EINVAL;
+			goto error_cleanup;
+		}
+		if (digest_ctx.active && (digest_ctx.curr_src != NULL) && !digest_ctx.curr_src->active){
+			DEBUG_API(printk("cryptocop_setup_dma_list: digest source from inactive unit %d\n", digest_ctx.curr_src->unit_no));
+			failed = -EINVAL;
+			goto error_cleanup;
+		}
+		if (csum_ctx.active && (csum_ctx.curr_src != NULL) && !csum_ctx.curr_src->active){
+			DEBUG_API(printk("cryptocop_setup_dma_list: cipher source from inactive unit %d\n", csum_ctx.curr_src->unit_no));
+			failed = -EINVAL;
+			goto error_cleanup;
+		}
+
+		/* Update consumed and produced lengths.
+
+		   The consumed length accounting here is actually cheating.  If a unit source from DMA (or any
+		   other unit that process data in blocks of one octet) it is correct, but if it source from a
+		   block processing unit, i.e. a cipher, it will be temporarily incorrect at some times.  However
+		   since it is only allowed--by the HW--to change source to or from a block processing unit at times where that
+		   unit has processed an exact multiple of its block length the end result will be correct.
+		   Beware that if the source change restriction change this code will need to be (much) reworked.
+		*/
+		DEBUG(printk("cryptocop_setup_dma_list: desc->length=%d, desc_len=%d.\n", odsc->length, desc_len));
+
+		if (csum_ctx.active) {
+			csum_ctx.consumed += desc_len;
+			if (csum_ctx.done) {
+				csum_ctx.produced = 2;
+			}
+			DEBUG(printk("cryptocop_setup_dma_list: csum_ctx producing: consumed=%d, produced=%d, blocklength=%d.\n", csum_ctx.consumed, csum_ctx.produced, csum_ctx.blocklength));
+		}
+		if (digest_ctx.active) {
+			digest_ctx.consumed += desc_len;
+			if (digest_ctx.done) {
+				if (digest_ctx.unit_no == src_md5) {
+					digest_ctx.produced = MD5_STATE_LENGTH;
+				} else {
+					digest_ctx.produced = SHA1_STATE_LENGTH;
+				}
+			}
+			DEBUG(printk("cryptocop_setup_dma_list: digest_ctx producing: consumed=%d, produced=%d, blocklength=%d.\n", digest_ctx.consumed, digest_ctx.produced, digest_ctx.blocklength));
+		}
+		if (cipher_ctx.active) {
+			/* Ciphers are allowed only to source from DMA out.  That is filtered above. */
+			assert(cipher_ctx.current_src == src_dma);
+			cipher_ctx.consumed += desc_len;
+			cipher_ctx.produced = cipher_ctx.blocklength * (cipher_ctx.consumed / cipher_ctx.blocklength);
+			if (cipher_ctx.cbcmode && !(cipher_ctx.tcfg->flags & CRYPTOCOP_EXPLICIT_IV) && cipher_ctx.produced){
+				cipher_ctx.produced -= cipher_ctx.blocklength; /* Compensate for CBC iv. */
+			}
+			DEBUG(printk("cryptocop_setup_dma_list: cipher_ctx producing: consumed=%d, produced=%d, blocklength=%d.\n", cipher_ctx.consumed, cipher_ctx.produced, cipher_ctx.blocklength));
+		}
+
+		/* Setup the DMA out descriptors. */
+		/* Configure the metadata. */
+		active_count = 0;
+		eop_needed_count = 0;
+		if (cipher_ctx.active) {
+			++active_count;
+			if (cipher_ctx.unit_no == src_dma){
+				/* mem2mem */
+				meta_out.ciphsel = src_none;
+			} else {
+				meta_out.ciphsel = cipher_ctx.current_src;
+			}
+			meta_out.ciphconf = cipher_ctx.ciph_conf;
+			meta_out.cbcmode = cipher_ctx.cbcmode;
+			meta_out.decrypt = cipher_ctx.decrypt;
+			DEBUG(printk("set ciphsel=%d ciphconf=%d cbcmode=%d decrypt=%d\n", meta_out.ciphsel, meta_out.ciphconf, meta_out.cbcmode, meta_out.decrypt));
+			if (cipher_ctx.done) ++eop_needed_count;
+		} else {
+			meta_out.ciphsel = src_none;
+		}
+
+		if (digest_ctx.active) {
+			++active_count;
+			meta_out.hashsel = digest_ctx.current_src;
+			meta_out.hashconf = digest_ctx.hash_conf;
+			meta_out.hashmode = 0; /* Explicit mode is not used here. */
+			DEBUG(printk("set hashsel=%d hashconf=%d hashmode=%d\n", meta_out.hashsel, meta_out.hashconf, meta_out.hashmode));
+			if (digest_ctx.done) {
+				assert(digest_ctx.pad_descs == NULL);
+				failed = create_pad_descriptor(&digest_ctx, &digest_ctx.pad_descs, alloc_flag);
+				if (failed) {
+					DEBUG_API(printk("cryptocop_setup_dma_list: failed digest pad creation.\n"));
+					goto error_cleanup;
+				}
+			}
+		} else {
+			meta_out.hashsel = src_none;
+		}
+
+		if (csum_ctx.active) {
+			++active_count;
+			meta_out.csumsel = csum_ctx.current_src;
+			if (csum_ctx.done) {
+				assert(csum_ctx.pad_descs == NULL);
+				failed = create_pad_descriptor(&csum_ctx, &csum_ctx.pad_descs, alloc_flag);
+				if (failed) {
+					DEBUG_API(printk("cryptocop_setup_dma_list: failed csum pad creation.\n"));
+					goto error_cleanup;
+				}
+			}
+		} else {
+			meta_out.csumsel = src_none;
+		}
+		DEBUG(printk("cryptocop_setup_dma_list: %d eop needed, %d active units\n", eop_needed_count, active_count));
+		/* Setup DMA out descriptors for the indata. */
+		failed = create_output_descriptors(operation, &iniov_ix, &iniov_offset, desc_len, &current_out_cdesc, &meta_out, alloc_flag);
+		if (failed) {
+			DEBUG_API(printk("cryptocop_setup_dma_list: create_output_descriptors %d\n", failed));
+			goto error_cleanup;
+		}
+		/* Setup out EOP.  If there are active units that are not done here they cannot get an EOP
+		 * so we ust setup a zero length descriptor to DMA to signal EOP only to done units.
+		 * If there is a pad descriptor EOP for the padded unit will be EOPed by it.
+		 */
+		assert(active_count >= eop_needed_count);
+		assert((eop_needed_count == 0) || (eop_needed_count == 1));
+		if (eop_needed_count) {
+			/* This means that the bulk operation (cipeher/m2m) is terminated. */
+			if (active_count > 1) {
+				/* Use zero length EOP descriptor. */
+				struct cryptocop_dma_desc *ed = alloc_cdesc(alloc_flag);
+				struct strcop_meta_out    ed_mo = {0};
+				if (!ed) {
+					DEBUG_API(printk("cryptocop_setup_dma_list: alloc EOP descriptor for cipher\n"));
+					failed = -ENOMEM;
+					goto error_cleanup;
+				}
+
+				assert(cipher_ctx.active && cipher_ctx.done);
+
+				if (cipher_ctx.unit_no == src_dma){
+					/* mem2mem */
+					ed_mo.ciphsel = src_none;
+				} else {
+					ed_mo.ciphsel = cipher_ctx.current_src;
+				}
+				ed_mo.ciphconf = cipher_ctx.ciph_conf;
+				ed_mo.cbcmode = cipher_ctx.cbcmode;
+				ed_mo.decrypt = cipher_ctx.decrypt;
+
+				ed->free_buf = NULL;
+				ed->dma_descr->wait = 1;
+				ed->dma_descr->out_eop = 1;
+
+				ed->dma_descr->buf = (char*)virt_to_phys(&ed); /* Use any valid physical address for zero length descriptor. */
+				ed->dma_descr->after = ed->dma_descr->buf;
+				ed->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, ed_mo);
+				current_out_cdesc->next = ed;
+				current_out_cdesc = ed;
+			} else {
+				/* Set EOP in the current out descriptor since the only active module is
+				 * the one needing the EOP. */
+
+				current_out_cdesc->dma_descr->out_eop = 1;
+			}
+		}
+
+		if (cipher_ctx.done && cipher_ctx.active) cipher_ctx.active = 0;
+		if (digest_ctx.done && digest_ctx.active) digest_ctx.active = 0;
+		if (csum_ctx.done && csum_ctx.active) csum_ctx.active = 0;
+		indata_ix += odsc->length;
+		odsc = odsc->next;
+	} /* while (odsc) */ /* Process descriptors. */
+	DEBUG(printk("cryptocop_setup_dma_list: done parsing operation descriptors\n"));
+	if (cipher_ctx.tcfg && (cipher_ctx.active || !cipher_ctx.done)){
+		DEBUG_API(printk("cryptocop_setup_dma_list: cipher operation not terminated.\n"));
+		failed = -EINVAL;
+		goto error_cleanup;
+	}
+	if (digest_ctx.tcfg && (digest_ctx.active || !digest_ctx.done)){
+		DEBUG_API(printk("cryptocop_setup_dma_list: digest operation not terminated.\n"));
+		failed = -EINVAL;
+		goto error_cleanup;
+	}
+	if (csum_ctx.tcfg && (csum_ctx.active || !csum_ctx.done)){
+		DEBUG_API(printk("cryptocop_setup_dma_list: csum operation not terminated.\n"));
+		failed = -EINVAL;
+		goto error_cleanup;
+	}
+
+	failed = append_input_descriptors(operation, &current_in_cdesc, &current_out_cdesc, &cipher_ctx, alloc_flag);
+	if (failed){
+		DEBUG_API(printk("cryptocop_setup_dma_list: append_input_descriptors cipher_ctx %d\n", failed));
+		goto error_cleanup;
+	}
+	failed = append_input_descriptors(operation, &current_in_cdesc, &current_out_cdesc, &digest_ctx, alloc_flag);
+	if (failed){
+		DEBUG_API(printk("cryptocop_setup_dma_list: append_input_descriptors cipher_ctx %d\n", failed));
+		goto error_cleanup;
+	}
+	failed = append_input_descriptors(operation, &current_in_cdesc, &current_out_cdesc, &csum_ctx, alloc_flag);
+	if (failed){
+		DEBUG_API(printk("cryptocop_setup_dma_list: append_input_descriptors cipher_ctx %d\n", failed));
+		goto error_cleanup;
+	}
+
+	DEBUG(printk("cryptocop_setup_dma_list: int_op=0x%p, *int_op=0x%p\n", int_op, *int_op));
+	(*int_op)->cdesc_out = out_cdesc_head.next;
+	(*int_op)->cdesc_in = in_cdesc_head.next;
+	DEBUG(printk("cryptocop_setup_dma_list: out_cdesc_head=0x%p in_cdesc_head=0x%p\n", (*int_op)->cdesc_out, (*int_op)->cdesc_in));
+
+	setup_descr_chain(out_cdesc_head.next);
+	setup_descr_chain(in_cdesc_head.next);
+
+	/* Last but not least: mark the last DMA in descriptor for a INTR and EOL and the the
+	 * last DMA out descriptor for EOL.
+	 */
+	current_in_cdesc->dma_descr->intr = 1;
+	current_in_cdesc->dma_descr->eol = 1;
+	current_out_cdesc->dma_descr->eol = 1;
+
+	/* Setup DMA contexts. */
+	(*int_op)->ctx_out.next = NULL;
+	(*int_op)->ctx_out.eol = 1;
+	(*int_op)->ctx_out.intr = 0;
+	(*int_op)->ctx_out.store_mode = 0;
+	(*int_op)->ctx_out.en = 0;
+	(*int_op)->ctx_out.dis = 0;
+	(*int_op)->ctx_out.md0 = 0;
+	(*int_op)->ctx_out.md1 = 0;
+	(*int_op)->ctx_out.md2 = 0;
+	(*int_op)->ctx_out.md3 = 0;
+	(*int_op)->ctx_out.md4 = 0;
+	(*int_op)->ctx_out.saved_data = (dma_descr_data*)virt_to_phys((*int_op)->cdesc_out->dma_descr);
+	(*int_op)->ctx_out.saved_data_buf = (*int_op)->cdesc_out->dma_descr->buf; /* Already physical address. */
+
+	(*int_op)->ctx_in.next = NULL;
+	(*int_op)->ctx_in.eol = 1;
+	(*int_op)->ctx_in.intr = 0;
+	(*int_op)->ctx_in.store_mode = 0;
+	(*int_op)->ctx_in.en = 0;
+	(*int_op)->ctx_in.dis = 0;
+	(*int_op)->ctx_in.md0 = 0;
+	(*int_op)->ctx_in.md1 = 0;
+	(*int_op)->ctx_in.md2 = 0;
+	(*int_op)->ctx_in.md3 = 0;
+	(*int_op)->ctx_in.md4 = 0;
+
+	(*int_op)->ctx_in.saved_data = (dma_descr_data*)virt_to_phys((*int_op)->cdesc_in->dma_descr);
+	(*int_op)->ctx_in.saved_data_buf = (*int_op)->cdesc_in->dma_descr->buf; /* Already physical address. */
+
+	DEBUG(printk("cryptocop_setup_dma_list: done\n"));
+	return 0;
+
+error_cleanup:
+	{
+		/* Free all allocated resources. */
+		struct cryptocop_dma_desc *tmp_cdesc;
+		while (digest_ctx.pad_descs){
+			tmp_cdesc = digest_ctx.pad_descs->next;
+			free_cdesc(digest_ctx.pad_descs);
+			digest_ctx.pad_descs = tmp_cdesc;
+		}
+		while (csum_ctx.pad_descs){
+			tmp_cdesc = csum_ctx.pad_descs->next;
+			free_cdesc(csum_ctx.pad_descs);
+			csum_ctx.pad_descs = tmp_cdesc;
+		}
+		assert(cipher_ctx.pad_descs == NULL); /* The ciphers are never padded. */
+
+		if (*int_op != NULL) delete_internal_operation(*int_op);
+	}
+	DEBUG_API(printk("cryptocop_setup_dma_list: done with error %d\n", failed));
+	return failed;
+}
+
+
+static void delete_internal_operation(struct cryptocop_int_operation *iop)
+{
+	void                      *ptr = iop->alloc_ptr;
+	struct cryptocop_dma_desc *cd = iop->cdesc_out;
+	struct cryptocop_dma_desc *next;
+
+	DEBUG(printk("delete_internal_operation: iop=0x%p, alloc_ptr=0x%p\n", iop, ptr));
+
+	while (cd) {
+		next = cd->next;
+		free_cdesc(cd);
+		cd = next;
+	}
+	cd = iop->cdesc_in;
+	while (cd) {
+		next = cd->next;
+		free_cdesc(cd);
+		cd = next;
+	}
+	kfree(ptr);
+}
+
+#define MD5_MIN_PAD_LENGTH (9)
+#define MD5_PAD_LENGTH_FIELD_LENGTH (8)
+
+static int create_md5_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length)
+{
+	size_t                  padlen = MD5_BLOCK_LENGTH - (hashed_length % MD5_BLOCK_LENGTH);
+	unsigned char           *p;
+	int                     i;
+	unsigned long long int  bit_length = hashed_length << 3;
+
+	if (padlen < MD5_MIN_PAD_LENGTH) padlen += MD5_BLOCK_LENGTH;
+
+	p = kmalloc(padlen, alloc_flag);
+	if (!pad) return -ENOMEM;
+
+	*p = 0x80;
+	memset(p+1, 0, padlen - 1);
+
+	DEBUG(printk("create_md5_pad: hashed_length=%lld bits == %lld bytes\n", bit_length, hashed_length));
+
+	i = padlen - MD5_PAD_LENGTH_FIELD_LENGTH;
+	while (bit_length != 0){
+		p[i++] = bit_length % 0x100;
+		bit_length >>= 8;
+	}
+
+	*pad = (char*)p;
+	*pad_length = padlen;
+
+	return 0;
+}
+
+#define SHA1_MIN_PAD_LENGTH (9)
+#define SHA1_PAD_LENGTH_FIELD_LENGTH (8)
+
+static int create_sha1_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length)
+{
+	size_t                  padlen = SHA1_BLOCK_LENGTH - (hashed_length % SHA1_BLOCK_LENGTH);
+	unsigned char           *p;
+	int                     i;
+	unsigned long long int  bit_length = hashed_length << 3;
+
+	if (padlen < SHA1_MIN_PAD_LENGTH) padlen += SHA1_BLOCK_LENGTH;
+
+	p = kmalloc(padlen, alloc_flag);
+	if (!pad) return -ENOMEM;
+
+	*p = 0x80;
+	memset(p+1, 0, padlen - 1);
+
+	DEBUG(printk("create_sha1_pad: hashed_length=%lld bits == %lld bytes\n", bit_length, hashed_length));
+
+	i = padlen - 1;
+	while (bit_length != 0){
+		p[i--] = bit_length % 0x100;
+		bit_length >>= 8;
+	}
+
+	*pad = (char*)p;
+	*pad_length = padlen;
+
+	return 0;
+}
+
+
+static int transform_ok(struct cryptocop_transform_init *tinit)
+{
+	switch (tinit->alg){
+	case cryptocop_alg_csum:
+		switch (tinit->csum_mode){
+		case cryptocop_csum_le:
+		case cryptocop_csum_be:
+			break;
+		default:
+			DEBUG_API(printk("transform_ok: Bad mode set for csum transform\n"));
+			return -EINVAL;
+		}
+	case cryptocop_alg_mem2mem:
+	case cryptocop_alg_md5:
+	case cryptocop_alg_sha1:
+		if (tinit->keylen != 0) {
+			DEBUG_API(printk("transform_ok: non-zero keylength, %d, for a digest/csum algorithm\n", tinit->keylen));
+			return -EINVAL; /* This check is a bit strict. */
+		}
+		break;
+	case cryptocop_alg_des:
+		if (tinit->keylen != 64) {
+			DEBUG_API(printk("transform_ok: keylen %d invalid for DES\n", tinit->keylen));
+			return -EINVAL;
+		}
+		break;
+	case cryptocop_alg_3des:
+		if (tinit->keylen != 192) {
+			DEBUG_API(printk("transform_ok: keylen %d invalid for 3DES\n", tinit->keylen));
+			return -EINVAL;
+		}
+		break;
+	case cryptocop_alg_aes:
+		if (tinit->keylen != 128 && tinit->keylen != 192 && tinit->keylen != 256) {
+			DEBUG_API(printk("transform_ok: keylen %d invalid for AES\n", tinit->keylen));
+			return -EINVAL;
+		}
+		break;
+	case cryptocop_no_alg:
+	default:
+		DEBUG_API(printk("transform_ok: no such algorithm %d\n", tinit->alg));
+		return -EINVAL;
+	}
+
+	switch (tinit->alg){
+	case cryptocop_alg_des:
+	case cryptocop_alg_3des:
+	case cryptocop_alg_aes:
+		if (tinit->cipher_mode != cryptocop_cipher_mode_ecb && tinit->cipher_mode != cryptocop_cipher_mode_cbc) return -EINVAL;
+	default:
+		 break;
+	}
+	return 0;
+}
+
+
+int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag)
+{
+	struct cryptocop_session         *sess;
+	struct cryptocop_transform_init  *tfrm_in = tinit;
+	struct cryptocop_transform_init  *tmp_in;
+	int                              no_tfrms = 0;
+	int                              i;
+	unsigned long int                flags;
+
+	init_stream_coprocessor(); /* For safety if we are called early */
+
+	while (tfrm_in){
+		int err;
+		++no_tfrms;
+		if ((err = transform_ok(tfrm_in))) {
+			DEBUG_API(printk("cryptocop_new_session, bad transform\n"));
+			return err;
+		}
+		tfrm_in = tfrm_in->next;
+	}
+	if (0 == no_tfrms) {
+		DEBUG_API(printk("cryptocop_new_session, no transforms specified\n"));
+		return -EINVAL;
+	}
+
+	sess = kmalloc(sizeof(struct cryptocop_session), alloc_flag);
+	if (!sess){
+		DEBUG_API(printk("cryptocop_new_session, kmalloc cryptocop_session\n"));
+		return -ENOMEM;
+	}
+
+	sess->tfrm_ctx = kmalloc(no_tfrms * sizeof(struct cryptocop_transform_ctx), alloc_flag);
+	if (!sess->tfrm_ctx) {
+		DEBUG_API(printk("cryptocop_new_session, kmalloc cryptocop_transform_ctx\n"));
+		kfree(sess);
+		return -ENOMEM;
+	}
+
+	tfrm_in = tinit;
+	for (i = 0; i < no_tfrms; i++){
+		tmp_in = tfrm_in->next;
+		while (tmp_in){
+			if (tmp_in->tid == tfrm_in->tid) {
+				DEBUG_API(printk("cryptocop_new_session, duplicate transform ids\n"));
+				kfree(sess->tfrm_ctx);
+				kfree(sess);
+				return -EINVAL;
+			}
+			tmp_in = tmp_in->next;
+		}
+		memcpy(&sess->tfrm_ctx[i].init, tfrm_in, sizeof(struct cryptocop_transform_init));
+		sess->tfrm_ctx[i].dec_key_set = 0;
+		sess->tfrm_ctx[i].next = &sess->tfrm_ctx[i] + 1;
+
+		tfrm_in = tfrm_in->next;
+	}
+	sess->tfrm_ctx[i-1].next = NULL;
+
+	spin_lock_irqsave(&cryptocop_sessions_lock, flags);
+	sess->sid = next_sid;
+	next_sid++;
+	/* TODO If we are really paranoid we should do duplicate check to handle sid wraparound.
+	 *      OTOH 2^64 is a really large number of session. */
+	if (next_sid == 0) next_sid = 1;
+
+	/* Prepend to session list. */
+	sess->next = cryptocop_sessions;
+	cryptocop_sessions = sess;
+	spin_unlock_irqrestore(&cryptocop_sessions_lock, flags);
+	*sid = sess->sid;
+	return 0;
+}
+
+
+int cryptocop_free_session(cryptocop_session_id sid)
+{
+	struct cryptocop_transform_ctx    *tc;
+	struct cryptocop_session          *sess = NULL;
+	struct cryptocop_session          *psess = NULL;
+	unsigned long int                 flags;
+	int                               i;
+	LIST_HEAD(remove_list);
+	struct list_head                  *node, *tmp;
+	struct cryptocop_prio_job         *pj;
+
+	DEBUG(printk("cryptocop_free_session: sid=%lld\n", sid));
+
+	spin_lock_irqsave(&cryptocop_sessions_lock, flags);
+	sess = cryptocop_sessions;
+	while (sess && sess->sid != sid){
+		psess = sess;
+		sess = sess->next;
+	}
+	if (sess){
+		if (psess){
+			psess->next = sess->next;
+		} else {
+			cryptocop_sessions = sess->next;
+		}
+	}
+	spin_unlock_irqrestore(&cryptocop_sessions_lock, flags);
+
+	if (!sess) return -EINVAL;
+
+	/* Remove queued jobs. */
+	spin_lock_irqsave(&cryptocop_job_queue_lock, flags);
+
+	for (i = 0; i < cryptocop_prio_no_prios; i++){
+		if (!list_empty(&(cryptocop_job_queues[i].jobs))){
+			list_for_each_safe(node, tmp, &(cryptocop_job_queues[i].jobs)) {
+				pj = list_entry(node, struct cryptocop_prio_job, node);
+				if (pj->oper->sid == sid) {
+					list_move_tail(node, &remove_list);
+				}
+			}
+		}
+	}
+	spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags);
+
+	list_for_each_safe(node, tmp, &remove_list) {
+		list_del(node);
+		pj = list_entry(node, struct cryptocop_prio_job, node);
+		pj->oper->operation_status = -EAGAIN;  /* EAGAIN is not ideal for job/session terminated but it's the best choice I know of. */
+		DEBUG(printk("cryptocop_free_session: pj=0x%p, pj->oper=0x%p, pj->iop=0x%p\n", pj, pj->oper, pj->iop));
+		pj->oper->cb(pj->oper, pj->oper->cb_data);
+		delete_internal_operation(pj->iop);
+		kfree(pj);
+	}
+
+	tc = sess->tfrm_ctx;
+	/* Erase keying data. */
+	while (tc){
+		DEBUG(printk("cryptocop_free_session: memset keys, tfrm id=%d\n", tc->init.tid));
+		memset(tc->init.key, 0xff, CRYPTOCOP_MAX_KEY_LENGTH);
+		memset(tc->dec_key, 0xff, CRYPTOCOP_MAX_KEY_LENGTH);
+		tc = tc->next;
+	}
+	kfree(sess->tfrm_ctx);
+	kfree(sess);
+
+	return 0;
+}
+
+static struct cryptocop_session *get_session(cryptocop_session_id sid)
+{
+	struct cryptocop_session    *sess;
+	unsigned long int           flags;
+
+	spin_lock_irqsave(&cryptocop_sessions_lock, flags);
+	sess = cryptocop_sessions;
+	while (sess && (sess->sid != sid)){
+		sess = sess->next;
+	}
+	spin_unlock_irqrestore(&cryptocop_sessions_lock, flags);
+
+	return sess;
+}
+
+static struct cryptocop_transform_ctx *get_transform_ctx(struct cryptocop_session *sess, cryptocop_tfrm_id tid)
+{
+	struct cryptocop_transform_ctx *tc = sess->tfrm_ctx;
+
+	DEBUG(printk("get_transform_ctx, sess=0x%p, tid=%d\n", sess, tid));
+	assert(sess != NULL);
+	while (tc && tc->init.tid != tid){
+		DEBUG(printk("tc=0x%p, tc->next=0x%p\n", tc, tc->next));
+		tc = tc->next;
+	}
+	DEBUG(printk("get_transform_ctx, returning tc=0x%p\n", tc));
+	return tc;
+}
+
+
+
+/* The AES s-transform matrix (s-box). */
+static const u8 aes_sbox[256] = {
+	99,  124, 119, 123, 242, 107, 111, 197, 48,  1,   103, 43,  254, 215, 171, 118,
+	202, 130, 201, 125, 250, 89,  71,  240, 173, 212, 162, 175, 156, 164, 114, 192,
+	183, 253, 147, 38,  54,  63,  247, 204, 52,  165, 229, 241, 113, 216, 49,  21,
+	4,   199, 35,  195, 24,  150, 5,   154, 7,   18,  128, 226, 235, 39,  178, 117,
+	9,   131, 44,  26,  27,  110, 90,  160, 82,  59,  214, 179, 41,  227, 47,  132,
+	83,  209, 0,   237, 32,  252, 177, 91,  106, 203, 190, 57,  74,  76,  88,  207,
+	208, 239, 170, 251, 67,  77,  51,  133, 69,  249, 2,   127, 80,  60,  159, 168,
+	81,  163, 64,  143, 146, 157, 56,  245, 188, 182, 218, 33,  16,  255, 243, 210,
+	205, 12,  19,  236, 95,  151, 68,  23,  196, 167, 126, 61,  100, 93,  25,  115,
+	96,  129, 79,  220, 34,  42,  144, 136, 70,  238, 184, 20,  222, 94,  11,  219,
+	224, 50,  58,  10,  73,  6,   36,  92,  194, 211, 172, 98,  145, 149, 228, 121,
+	231, 200, 55,  109, 141, 213, 78,  169, 108, 86,  244, 234, 101, 122, 174, 8,
+	186, 120, 37,  46,  28,  166, 180, 198, 232, 221, 116, 31,  75,  189, 139, 138,
+	112, 62,  181, 102, 72,  3,   246, 14,  97,  53,  87,  185, 134, 193, 29,  158,
+	225, 248, 152, 17,  105, 217, 142, 148, 155, 30,  135, 233, 206, 85,  40,  223,
+	140, 161, 137, 13,  191, 230, 66,  104, 65,  153, 45,  15,  176, 84,  187, 22
+};
+
+/* AES has a 32 bit word round constants for each round in the
+ * key schedule.  round_constant[i] is really Rcon[i+1] in FIPS187.
+ */
+static u32 round_constant[11] = {
+	0x01000000, 0x02000000, 0x04000000, 0x08000000,
+	0x10000000, 0x20000000, 0x40000000, 0x80000000,
+	0x1B000000, 0x36000000, 0x6C000000
+};
+
+/* Apply the s-box to each of the four occtets in w. */
+static u32 aes_ks_subword(const u32 w)
+{
+	u8 bytes[4];
+
+	*(u32*)(&bytes[0]) = w;
+	bytes[0] = aes_sbox[bytes[0]];
+	bytes[1] = aes_sbox[bytes[1]];
+	bytes[2] = aes_sbox[bytes[2]];
+	bytes[3] = aes_sbox[bytes[3]];
+	return *(u32*)(&bytes[0]);
+}
+
+/* The encrypt (forward) Rijndael key schedule algorithm pseudo code:
+ * (Note that AES words are 32 bit long)
+ *
+ * KeyExpansion(byte key[4*Nk], word w[Nb*(Nr+1)], Nk){
+ * word temp
+ * i = 0
+ * while (i < Nk) {
+ *   w[i] = word(key[4*i, 4*i + 1, 4*i + 2, 4*i + 3])
+ *   i = i + 1
+ * }
+ * i = Nk
+ *
+ * while (i < (Nb * (Nr + 1))) {
+ *   temp = w[i - 1]
+ *   if ((i mod Nk) == 0) {
+ *     temp = SubWord(RotWord(temp)) xor Rcon[i/Nk]
+ *   }
+ *   else if ((Nk > 6) && ((i mod Nk) == 4)) {
+ *     temp = SubWord(temp)
+ *   }
+ *   w[i] = w[i - Nk] xor temp
+ * }
+ * RotWord(t) does a 8 bit cyclic shift left on a 32 bit word.
+ * SubWord(t) applies the AES s-box individually to each octet
+ * in a 32 bit word.
+ *
+ * For AES Nk can have the values 4, 6, and 8 (corresponding to
+ * values for Nr of 10, 12, and 14).  Nb is always 4.
+ *
+ * To construct w[i], w[i - 1] and w[i - Nk] must be
+ * available.  Consequently we must keep a state of the last Nk words
+ * to be able to create the last round keys.
+ */
+static void get_aes_decrypt_key(unsigned char *dec_key, const unsigned  char *key, unsigned int keylength)
+{
+	u32 temp;
+	u32 w_ring[8]; /* nk is max 8, use elements 0..(nk - 1) as a ringbuffer */
+	u8  w_last_ix;
+	int i;
+	u8  nr, nk;
+
+	switch (keylength){
+	case 128:
+		nk = 4;
+		nr = 10;
+		break;
+	case 192:
+		nk = 6;
+		nr = 12;
+		break;
+	case 256:
+		nk = 8;
+		nr = 14;
+		break;
+	default:
+		panic("stream co-processor: bad aes key length in get_aes_decrypt_key\n");
+	};
+
+	/* Need to do host byte order correction here since key is byte oriented and the
+	 * kx algorithm is word (u32) oriented. */
+	for (i = 0; i < nk; i+=1) {
+		w_ring[i] = be32_to_cpu(*(u32*)&key[4*i]);
+	}
+
+	i = (int)nk;
+	w_last_ix = i - 1;
+	while (i < (4 * (nr + 2))) {
+		temp = w_ring[w_last_ix];
+		if (!(i % nk)) {
+			/* RotWord(temp) */
+			temp = (temp << 8) | (temp >> 24);
+			temp = aes_ks_subword(temp);
+			temp ^= round_constant[i/nk - 1];
+		} else if ((nk > 6) && ((i % nk) == 4)) {
+			temp = aes_ks_subword(temp);
+		}
+		w_last_ix = (w_last_ix + 1) % nk; /* This is the same as (i-Nk) mod Nk */
+		temp ^= w_ring[w_last_ix];
+		w_ring[w_last_ix] = temp;
+
+		/* We need the round keys for round Nr+1 and Nr+2 (round key
+		 * Nr+2 is the round key beyond the last one used when
+		 * encrypting).  Rounds are numbered starting from 0, Nr=10
+		 * implies 11 rounds are used in encryption/decryption.
+		 */
+		if (i >= (4 * nr)) {
+			/* Need to do host byte order correction here, the key
+			 * is byte oriented. */
+			*(u32*)dec_key = cpu_to_be32(temp);
+			dec_key += 4;
+		}
+		++i;
+	}
+}
+
+
+/**** Job/operation management. ****/
+
+int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation)
+{
+	return cryptocop_job_queue_insert(cryptocop_prio_kernel_csum, operation);
+}
+
+int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation)
+{
+	return cryptocop_job_queue_insert(cryptocop_prio_kernel, operation);
+}
+
+int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation)
+{
+	return cryptocop_job_queue_insert(cryptocop_prio_user, operation);
+}
+
+static int cryptocop_job_queue_insert(cryptocop_queue_priority prio, struct cryptocop_operation *operation)
+{
+	int                           ret;
+	struct cryptocop_prio_job     *pj = NULL;
+	unsigned long int             flags;
+
+	DEBUG(printk("cryptocop_job_queue_insert(%d, 0x%p)\n", prio, operation));
+
+	if (!operation || !operation->cb){
+		DEBUG_API(printk("cryptocop_job_queue_insert oper=0x%p, NULL operation or callback\n", operation));
+		return -EINVAL;
+	}
+
+	if ((ret = cryptocop_job_setup(&pj, operation)) != 0){
+		DEBUG_API(printk("cryptocop_job_queue_insert: job setup failed\n"));
+		return ret;
+	}
+	assert(pj != NULL);
+
+	spin_lock_irqsave(&cryptocop_job_queue_lock, flags);
+	list_add_tail(&pj->node, &cryptocop_job_queues[prio].jobs);
+	spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags);
+
+	/* Make sure a job is running */
+	cryptocop_start_job();
+	return 0;
+}
+
+static void cryptocop_do_tasklet(unsigned long unused);
+DECLARE_TASKLET (cryptocop_tasklet, cryptocop_do_tasklet, 0);
+
+static void cryptocop_do_tasklet(unsigned long unused)
+{
+	struct list_head             *node;
+	struct cryptocop_prio_job    *pj = NULL;
+	unsigned long                flags;
+
+	DEBUG(printk("cryptocop_do_tasklet: entering\n"));
+
+	do {
+		spin_lock_irqsave(&cryptocop_completed_jobs_lock, flags);
+		if (!list_empty(&cryptocop_completed_jobs)){
+			node = cryptocop_completed_jobs.next;
+			list_del(node);
+			pj = list_entry(node, struct cryptocop_prio_job, node);
+		} else {
+			pj = NULL;
+		}
+		spin_unlock_irqrestore(&cryptocop_completed_jobs_lock, flags);
+		if (pj) {
+			assert(pj->oper != NULL);
+
+			/* Notify consumer of operation completeness. */
+			DEBUG(printk("cryptocop_do_tasklet: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data));
+
+			pj->oper->operation_status = 0; /* Job is completed. */
+			pj->oper->cb(pj->oper, pj->oper->cb_data);
+			delete_internal_operation(pj->iop);
+			kfree(pj);
+		}
+	} while (pj != NULL);
+
+	DEBUG(printk("cryptocop_do_tasklet: exiting\n"));
+}
+
+static irqreturn_t
+dma_done_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+	struct cryptocop_prio_job *done_job;
+	reg_dma_rw_ack_intr ack_intr = {
+		.data = 1,
+	};
+
+	REG_WR (dma, regi_dma9, rw_ack_intr, ack_intr);
+
+	DEBUG(printk("cryptocop DMA done\n"));
+
+	spin_lock(&running_job_lock);
+	if (cryptocop_running_job == NULL){
+		printk("stream co-processor got interrupt when not busy\n");
+		spin_unlock(&running_job_lock);
+		return IRQ_HANDLED;
+	}
+	done_job = cryptocop_running_job;
+	cryptocop_running_job = NULL;
+	spin_unlock(&running_job_lock);
+
+	/* Start processing a job. */
+	if (!spin_trylock(&cryptocop_process_lock)){
+		DEBUG(printk("cryptocop irq handler, not starting a job\n"));
+	} else {
+		cryptocop_start_job();
+		spin_unlock(&cryptocop_process_lock);
+	}
+
+	done_job->oper->operation_status = 0; /* Job is completed. */
+	if (done_job->oper->fast_callback){
+		/* This operation wants callback from interrupt. */
+		done_job->oper->cb(done_job->oper, done_job->oper->cb_data);
+		delete_internal_operation(done_job->iop);
+		kfree(done_job);
+	} else {
+		spin_lock(&cryptocop_completed_jobs_lock);
+		list_add_tail(&(done_job->node), &cryptocop_completed_jobs);
+		spin_unlock(&cryptocop_completed_jobs_lock);
+		tasklet_schedule(&cryptocop_tasklet);
+	}
+
+	DEBUG(printk("cryptocop leave irq handler\n"));
+	return IRQ_HANDLED;
+}
+
+
+/* Setup interrupts and DMA channels. */
+static int init_cryptocop(void)
+{
+	unsigned long          flags;
+	reg_intr_vect_rw_mask  intr_mask;
+	reg_dma_rw_cfg         dma_cfg = {.en = 1};
+	reg_dma_rw_intr_mask   intr_mask_in = {.data = regk_dma_yes}; /* Only want descriptor interrupts from the DMA in channel. */
+	reg_dma_rw_ack_intr    ack_intr = {.data = 1,.in_eop = 1 };
+	reg_strcop_rw_cfg      strcop_cfg = {
+		.ipend = regk_strcop_little,
+		.td1 = regk_strcop_e,
+		.td2 = regk_strcop_d,
+		.td3 = regk_strcop_e,
+		.ignore_sync = 0,
+		.en = 1
+	};
+
+	if (request_irq(DMA9_INTR_VECT, dma_done_interrupt, 0, "stream co-processor DMA", NULL)) panic("request_irq stream co-processor irq dma9");
+
+	(void)crisv32_request_dma(8, "strcop", DMA_PANIC_ON_ERROR, 0, dma_strp);
+	(void)crisv32_request_dma(9, "strcop", DMA_PANIC_ON_ERROR, 0, dma_strp);
+
+	local_irq_save(flags);
+
+	/* Reset and enable the cryptocop. */
+	strcop_cfg.en = 0;
+	REG_WR(strcop, regi_strcop, rw_cfg, strcop_cfg);
+	strcop_cfg.en = 1;
+	REG_WR(strcop, regi_strcop, rw_cfg, strcop_cfg);
+
+	/* Enable DMA9 interrupt */
+	intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
+	intr_mask.dma9 = 1;
+	REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
+
+	/* Enable DMAs. */
+	REG_WR(dma, regi_dma9, rw_cfg, dma_cfg); /* input DMA */
+	REG_WR(dma, regi_dma8, rw_cfg, dma_cfg); /* output DMA */
+
+	/* Set up wordsize = 4 for DMAs. */
+	DMA_WR_CMD (regi_dma8, regk_dma_set_w_size4);
+	DMA_WR_CMD (regi_dma9, regk_dma_set_w_size4);
+
+	/* Enable interrupts. */
+	REG_WR(dma, regi_dma9, rw_intr_mask, intr_mask_in);
+
+	/* Clear intr ack. */
+	REG_WR(dma, regi_dma9, rw_ack_intr, ack_intr);
+
+	local_irq_restore(flags);
+
+	return 0;
+}
+
+/* Free used cryptocop hw resources (interrupt and DMA channels). */
+static void release_cryptocop(void)
+{
+	unsigned long          flags;
+	reg_intr_vect_rw_mask  intr_mask;
+	reg_dma_rw_cfg         dma_cfg = {.en = 0};
+	reg_dma_rw_intr_mask   intr_mask_in = {0};
+	reg_dma_rw_ack_intr    ack_intr = {.data = 1,.in_eop = 1 };
+
+	local_irq_save(flags);
+
+	/* Clear intr ack. */
+	REG_WR(dma, regi_dma9, rw_ack_intr, ack_intr);
+
+	/* Disable DMA9 interrupt */
+	intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
+	intr_mask.dma9 = 0;
+	REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
+
+	/* Disable DMAs. */
+	REG_WR(dma, regi_dma9, rw_cfg, dma_cfg); /* input DMA */
+	REG_WR(dma, regi_dma8, rw_cfg, dma_cfg); /* output DMA */
+
+	/* Disable interrupts. */
+	REG_WR(dma, regi_dma9, rw_intr_mask, intr_mask_in);
+
+	local_irq_restore(flags);
+
+	free_irq(DMA9_INTR_VECT, NULL);
+
+	(void)crisv32_free_dma(8);
+	(void)crisv32_free_dma(9);
+}
+
+
+/* Init job queue. */
+static int cryptocop_job_queue_init(void)
+{
+	int i;
+
+	INIT_LIST_HEAD(&cryptocop_completed_jobs);
+
+	for (i = 0; i < cryptocop_prio_no_prios; i++){
+		cryptocop_job_queues[i].prio = (cryptocop_queue_priority)i;
+		INIT_LIST_HEAD(&cryptocop_job_queues[i].jobs);
+	}
+	return 0;
+}
+
+
+static void cryptocop_job_queue_close(void)
+{
+	struct list_head               *node, *tmp;
+	struct cryptocop_prio_job      *pj = NULL;
+	unsigned long int              process_flags, flags;
+	int                            i;
+
+	/* FIXME: This is as yet untested code. */
+
+	/* Stop strcop from getting an operation to process while we are closing the
+	   module. */
+	spin_lock_irqsave(&cryptocop_process_lock, process_flags);
+
+	/* Empty the job queue. */
+	spin_lock_irqsave(&cryptocop_process_lock, process_flags);
+	for (i = 0; i < cryptocop_prio_no_prios; i++){
+		if (!list_empty(&(cryptocop_job_queues[i].jobs))){
+			list_for_each_safe(node, tmp, &(cryptocop_job_queues[i].jobs)) {
+				pj = list_entry(node, struct cryptocop_prio_job, node);
+				list_del(node);
+
+				/* Call callback to notify consumer of job removal. */
+				DEBUG(printk("cryptocop_job_queue_close: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data));
+				pj->oper->operation_status = -EINTR; /* Job is terminated without completion. */
+				pj->oper->cb(pj->oper, pj->oper->cb_data);
+
+				delete_internal_operation(pj->iop);
+				kfree(pj);
+			}
+		}
+	}
+	spin_unlock_irqrestore(&cryptocop_process_lock, process_flags);
+
+	/* Remove the running job, if any. */
+	spin_lock_irqsave(&running_job_lock, flags);
+	if (cryptocop_running_job){
+		reg_strcop_rw_cfg rw_cfg;
+		reg_dma_rw_cfg    dma_out_cfg, dma_in_cfg;
+
+		/* Stop DMA. */
+		dma_out_cfg = REG_RD(dma, regi_dma8, rw_cfg);
+		dma_out_cfg.en = regk_dma_no;
+		REG_WR(dma, regi_dma8, rw_cfg, dma_out_cfg);
+
+		dma_in_cfg = REG_RD(dma, regi_dma9, rw_cfg);
+		dma_in_cfg.en = regk_dma_no;
+		REG_WR(dma, regi_dma9, rw_cfg, dma_in_cfg);
+
+		/* Disble the cryptocop. */
+		rw_cfg = REG_RD(strcop, regi_strcop, rw_cfg);
+		rw_cfg.en = 0;
+		REG_WR(strcop, regi_strcop, rw_cfg, rw_cfg);
+
+		pj = cryptocop_running_job;
+		cryptocop_running_job = NULL;
+
+		/* Call callback to notify consumer of job removal. */
+		DEBUG(printk("cryptocop_job_queue_close: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data));
+		pj->oper->operation_status = -EINTR; /* Job is terminated without completion. */
+		pj->oper->cb(pj->oper, pj->oper->cb_data);
+
+		delete_internal_operation(pj->iop);
+		kfree(pj);
+	}
+	spin_unlock_irqrestore(&running_job_lock, flags);
+
+	/* Remove completed jobs, if any. */
+	spin_lock_irqsave(&cryptocop_completed_jobs_lock, flags);
+
+	list_for_each_safe(node, tmp, &cryptocop_completed_jobs) {
+		pj = list_entry(node, struct cryptocop_prio_job, node);
+		list_del(node);
+		/* Call callback to notify consumer of job removal. */
+		DEBUG(printk("cryptocop_job_queue_close: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data));
+		pj->oper->operation_status = -EINTR; /* Job is terminated without completion. */
+		pj->oper->cb(pj->oper, pj->oper->cb_data);
+
+		delete_internal_operation(pj->iop);
+		kfree(pj);
+	}
+	spin_unlock_irqrestore(&cryptocop_completed_jobs_lock, flags);
+}
+
+
+static void cryptocop_start_job(void)
+{
+	int                          i;
+	struct cryptocop_prio_job    *pj;
+	unsigned long int            flags;
+	unsigned long int            running_job_flags;
+	reg_strcop_rw_cfg            rw_cfg = {.en = 1, .ignore_sync = 0};
+
+	DEBUG(printk("cryptocop_start_job: entering\n"));
+
+	spin_lock_irqsave(&running_job_lock, running_job_flags);
+	if (cryptocop_running_job != NULL){
+		/* Already running. */
+		DEBUG(printk("cryptocop_start_job: already running, exit\n"));
+		spin_unlock_irqrestore(&running_job_lock, running_job_flags);
+		return;
+	}
+	spin_lock_irqsave(&cryptocop_job_queue_lock, flags);
+
+	/* Check the queues in priority order. */
+	for (i = cryptocop_prio_kernel_csum; (i < cryptocop_prio_no_prios) && list_empty(&cryptocop_job_queues[i].jobs); i++);
+	if (i == cryptocop_prio_no_prios) {
+		spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags);
+		spin_unlock_irqrestore(&running_job_lock, running_job_flags);
+		DEBUG(printk("cryptocop_start_job: no jobs to run\n"));
+		return; /* No jobs to run */
+	}
+	DEBUG(printk("starting job for prio %d\n", i));
+
+	/* TODO: Do not starve lower priority jobs.  Let in a lower
+	 * prio job for every N-th processed higher prio job or some
+	 * other scheduling policy.  This could reasonably be
+	 * tweakable since the optimal balance would depend on the
+	 * type of load on the system. */
+
+	/* Pull the DMA lists from the job and start the DMA client. */
+	pj = list_entry(cryptocop_job_queues[i].jobs.next, struct cryptocop_prio_job, node);
+	list_del(&pj->node);
+	spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags);
+	cryptocop_running_job = pj;
+
+	/* Set config register (3DES and CSUM modes). */
+	switch (pj->iop->tdes_mode){
+	case cryptocop_3des_eee:
+		rw_cfg.td1 = regk_strcop_e;
+		rw_cfg.td2 = regk_strcop_e;
+		rw_cfg.td3 = regk_strcop_e;
+		break;
+	case cryptocop_3des_eed:
+		rw_cfg.td1 = regk_strcop_e;
+		rw_cfg.td2 = regk_strcop_e;
+		rw_cfg.td3 = regk_strcop_d;
+		break;
+	case cryptocop_3des_ede:
+		rw_cfg.td1 = regk_strcop_e;
+		rw_cfg.td2 = regk_strcop_d;
+		rw_cfg.td3 = regk_strcop_e;
+		break;
+	case cryptocop_3des_edd:
+		rw_cfg.td1 = regk_strcop_e;
+		rw_cfg.td2 = regk_strcop_d;
+		rw_cfg.td3 = regk_strcop_d;
+		break;
+	case cryptocop_3des_dee:
+		rw_cfg.td1 = regk_strcop_d;
+		rw_cfg.td2 = regk_strcop_e;
+		rw_cfg.td3 = regk_strcop_e;
+		break;
+	case cryptocop_3des_ded:
+		rw_cfg.td1 = regk_strcop_d;
+		rw_cfg.td2 = regk_strcop_e;
+		rw_cfg.td3 = regk_strcop_d;
+		break;
+	case cryptocop_3des_dde:
+		rw_cfg.td1 = regk_strcop_d;
+		rw_cfg.td2 = regk_strcop_d;
+		rw_cfg.td3 = regk_strcop_e;
+		break;
+	case cryptocop_3des_ddd:
+		rw_cfg.td1 = regk_strcop_d;
+		rw_cfg.td2 = regk_strcop_d;
+		rw_cfg.td3 = regk_strcop_d;
+		break;
+	default:
+		DEBUG(printk("cryptocop_setup_dma_list: bad 3DES mode\n"));
+	}
+	switch (pj->iop->csum_mode){
+	case cryptocop_csum_le:
+		rw_cfg.ipend = regk_strcop_little;
+		break;
+	case cryptocop_csum_be:
+		rw_cfg.ipend = regk_strcop_big;
+		break;
+	default:
+		DEBUG(printk("cryptocop_setup_dma_list: bad checksum mode\n"));
+	}
+	REG_WR(strcop, regi_strcop, rw_cfg, rw_cfg);
+
+	DEBUG(printk("cryptocop_start_job: starting DMA, new cryptocop_running_job=0x%p\n"
+		     "ctx_in: 0x%p, phys: 0x%p\n"
+		     "ctx_out: 0x%p, phys: 0x%p\n",
+		     pj,
+		     &pj->iop->ctx_in, (char*)virt_to_phys(&pj->iop->ctx_in),
+		     &pj->iop->ctx_out, (char*)virt_to_phys(&pj->iop->ctx_out)));
+
+	/* Start input DMA. */
+	DMA_START_CONTEXT(regi_dma9, virt_to_phys(&pj->iop->ctx_in));
+
+	/* Start output DMA. */
+	DMA_START_CONTEXT(regi_dma8, virt_to_phys(&pj->iop->ctx_out));
+
+	spin_unlock_irqrestore(&running_job_lock, running_job_flags);
+	DEBUG(printk("cryptocop_start_job: exiting\n"));
+}
+
+
+static int cryptocop_job_setup(struct cryptocop_prio_job **pj, struct cryptocop_operation *operation)
+{
+	int  err;
+	int  alloc_flag = operation->in_interrupt ? GFP_ATOMIC : GFP_KERNEL;
+	void *iop_alloc_ptr = NULL;
+
+	*pj = kmalloc(sizeof (struct cryptocop_prio_job), alloc_flag);
+	if (!*pj) return -ENOMEM;
+
+	DEBUG(printk("cryptocop_job_setup: operation=0x%p\n", operation));
+
+	(*pj)->oper = operation;
+	DEBUG(printk("cryptocop_job_setup, cb=0x%p cb_data=0x%p\n",  (*pj)->oper->cb, (*pj)->oper->cb_data));
+
+	if (operation->use_dmalists) {
+		DEBUG(print_user_dma_lists(&operation->list_op));
+		if (!operation->list_op.inlist || !operation->list_op.outlist || !operation->list_op.out_data_buf || !operation->list_op.in_data_buf){
+			DEBUG_API(printk("cryptocop_job_setup: bad indata (use_dmalists)\n"));
+			kfree(*pj);
+			return -EINVAL;
+		}
+		iop_alloc_ptr = kmalloc(DESCR_ALLOC_PAD + sizeof(struct cryptocop_int_operation), alloc_flag);
+		if (!iop_alloc_ptr) {
+			DEBUG_API(printk("cryptocop_job_setup: kmalloc cryptocop_int_operation\n"));
+			kfree(*pj);
+			return -ENOMEM;
+		}
+		(*pj)->iop = (struct cryptocop_int_operation*)(((unsigned long int)(iop_alloc_ptr + DESCR_ALLOC_PAD + offsetof(struct cryptocop_int_operation, ctx_out)) & ~0x0000001F) - offsetof(struct cryptocop_int_operation, ctx_out));
+		DEBUG(memset((*pj)->iop, 0xff, sizeof(struct cryptocop_int_operation)));
+		(*pj)->iop->alloc_ptr = iop_alloc_ptr;
+		(*pj)->iop->sid = operation->sid;
+		(*pj)->iop->cdesc_out = NULL;
+		(*pj)->iop->cdesc_in = NULL;
+		(*pj)->iop->tdes_mode = operation->list_op.tdes_mode;
+		(*pj)->iop->csum_mode = operation->list_op.csum_mode;
+		(*pj)->iop->ddesc_out = operation->list_op.outlist;
+		(*pj)->iop->ddesc_in = operation->list_op.inlist;
+
+		/* Setup DMA contexts. */
+		(*pj)->iop->ctx_out.next = NULL;
+		(*pj)->iop->ctx_out.eol = 1;
+		(*pj)->iop->ctx_out.saved_data = operation->list_op.outlist;
+		(*pj)->iop->ctx_out.saved_data_buf = operation->list_op.out_data_buf;
+
+		(*pj)->iop->ctx_in.next = NULL;
+		(*pj)->iop->ctx_in.eol = 1;
+		(*pj)->iop->ctx_in.saved_data = operation->list_op.inlist;
+		(*pj)->iop->ctx_in.saved_data_buf = operation->list_op.in_data_buf;
+	} else {
+		if ((err = cryptocop_setup_dma_list(operation, &(*pj)->iop, alloc_flag))) {
+			DEBUG_API(printk("cryptocop_job_setup: cryptocop_setup_dma_list failed %d\n", err));
+			kfree(*pj);
+			return err;
+		}
+	}
+	DEBUG(print_dma_descriptors((*pj)->iop));
+
+	DEBUG(printk("cryptocop_job_setup, DMA list setup successful\n"));
+
+	return 0;
+}
+
+
+static int cryptocop_open(struct inode *inode, struct file *filp)
+{
+	int p = MINOR(inode->i_rdev);
+
+	if (p != CRYPTOCOP_MINOR) return -EINVAL;
+
+	filp->private_data = NULL;
+	return 0;
+}
+
+
+static int cryptocop_release(struct inode *inode, struct file *filp)
+{
+	struct cryptocop_private *dev = filp->private_data;
+	struct cryptocop_private *dev_next;
+
+	while (dev){
+		dev_next = dev->next;
+		if (dev->sid != CRYPTOCOP_SESSION_ID_NONE) {
+			(void)cryptocop_free_session(dev->sid);
+		}
+		kfree(dev);
+		dev = dev_next;
+	}
+
+	return 0;
+}
+
+
+static int cryptocop_ioctl_close_session(struct inode *inode, struct file *filp,
+					 unsigned int cmd, unsigned long arg)
+{
+	struct cryptocop_private  *dev = filp->private_data;
+	struct cryptocop_private  *prev_dev = NULL;
+	struct strcop_session_op  *sess_op = (struct strcop_session_op *)arg;
+	struct strcop_session_op  sop;
+	int                       err;
+
+	DEBUG(printk("cryptocop_ioctl_close_session\n"));
+
+	if (!access_ok(VERIFY_READ, sess_op, sizeof(struct strcop_session_op)))
+		return -EFAULT;
+	err = copy_from_user(&sop, sess_op, sizeof(struct strcop_session_op));
+	if (err) return -EFAULT;
+
+	while (dev && (dev->sid != sop.ses_id)) {
+		prev_dev = dev;
+		dev = dev->next;
+	}
+	if (dev){
+		if (prev_dev){
+			prev_dev->next = dev->next;
+		} else {
+			filp->private_data = dev->next;
+		}
+		err = cryptocop_free_session(dev->sid);
+		if (err) return -EFAULT;
+	} else {
+		DEBUG_API(printk("cryptocop_ioctl_close_session: session %lld not found\n", sop.ses_id));
+		return -EINVAL;
+	}
+	return 0;
+}
+
+
+static void ioctl_process_job_callback(struct cryptocop_operation *op, void*cb_data)
+{
+	struct ioctl_job_cb_ctx *jc = (struct ioctl_job_cb_ctx *)cb_data;
+
+	DEBUG(printk("ioctl_process_job_callback: op=0x%p, cb_data=0x%p\n", op, cb_data));
+
+	jc->processed = 1;
+	wake_up(&cryptocop_ioc_process_wq);
+}
+
+
+#define CRYPTOCOP_IOCTL_CIPHER_TID  (1)
+#define CRYPTOCOP_IOCTL_DIGEST_TID  (2)
+#define CRYPTOCOP_IOCTL_CSUM_TID    (3)
+
+static size_t first_cfg_change_ix(struct strcop_crypto_op *crp_op)
+{
+	size_t ch_ix = 0;
+
+	if (crp_op->do_cipher) ch_ix = crp_op->cipher_start;
+	if (crp_op->do_digest && (crp_op->digest_start < ch_ix)) ch_ix = crp_op->digest_start;
+	if (crp_op->do_csum && (crp_op->csum_start < ch_ix)) ch_ix = crp_op->csum_start;
+
+	DEBUG(printk("first_cfg_change_ix: ix=%d\n", ch_ix));
+	return ch_ix;
+}
+
+
+static size_t next_cfg_change_ix(struct strcop_crypto_op *crp_op, size_t ix)
+{
+	size_t ch_ix = INT_MAX;
+	size_t tmp_ix = 0;
+
+	if (crp_op->do_cipher && ((crp_op->cipher_start + crp_op->cipher_len) > ix)){
+		if (crp_op->cipher_start > ix) {
+			ch_ix = crp_op->cipher_start;
+		} else {
+			ch_ix = crp_op->cipher_start + crp_op->cipher_len;
+		}
+	}
+	if (crp_op->do_digest && ((crp_op->digest_start + crp_op->digest_len) > ix)){
+		if (crp_op->digest_start > ix) {
+			tmp_ix = crp_op->digest_start;
+		} else {
+			tmp_ix = crp_op->digest_start + crp_op->digest_len;
+		}
+		if (tmp_ix < ch_ix) ch_ix = tmp_ix;
+	}
+	if (crp_op->do_csum && ((crp_op->csum_start + crp_op->csum_len) > ix)){
+		if (crp_op->csum_start > ix) {
+			tmp_ix = crp_op->csum_start;
+		} else {
+			tmp_ix = crp_op->csum_start + crp_op->csum_len;
+		}
+		if (tmp_ix < ch_ix) ch_ix = tmp_ix;
+	}
+	if (ch_ix == INT_MAX) ch_ix = ix;
+	DEBUG(printk("next_cfg_change_ix prev ix=%d, next ix=%d\n", ix, ch_ix));
+	return ch_ix;
+}
+
+
+/* Map map_length bytes from the pages starting on *pageix and *pageoffset to iovecs starting on *iovix.
+ * Return -1 for ok, 0 for fail. */
+static int map_pages_to_iovec(struct iovec *iov, int iovlen, int *iovix, struct page **pages, int nopages, int *pageix, int *pageoffset, int map_length )
+{
+	int tmplen;
+
+	assert(iov != NULL);
+	assert(iovix != NULL);
+	assert(pages != NULL);
+	assert(pageix != NULL);
+	assert(pageoffset != NULL);
+
+	DEBUG(printk("map_pages_to_iovec, map_length=%d, iovlen=%d, *iovix=%d, nopages=%d, *pageix=%d, *pageoffset=%d\n", map_length, iovlen, *iovix, nopages, *pageix, *pageoffset));
+
+	while (map_length > 0){
+		DEBUG(printk("map_pages_to_iovec, map_length=%d, iovlen=%d, *iovix=%d, nopages=%d, *pageix=%d, *pageoffset=%d\n", map_length, iovlen, *iovix, nopages, *pageix, *pageoffset));
+		if (*iovix >= iovlen){
+			DEBUG_API(printk("map_page_to_iovec: *iovix=%d >= iovlen=%d\n", *iovix, iovlen));
+			return 0;
+		}
+		if (*pageix >= nopages){
+			DEBUG_API(printk("map_page_to_iovec: *pageix=%d >= nopages=%d\n", *pageix, nopages));
+			return 0;
+		}
+		iov[*iovix].iov_base = (unsigned char*)page_address(pages[*pageix]) + *pageoffset;
+		tmplen = PAGE_SIZE - *pageoffset;
+		if (tmplen < map_length){
+			(*pageoffset) = 0;
+			(*pageix)++;
+		} else {
+			tmplen = map_length;
+			(*pageoffset) += map_length;
+		}
+		DEBUG(printk("mapping %d bytes from page %d (or %d) to iovec %d\n", tmplen, *pageix, *pageix-1, *iovix));
+		iov[*iovix].iov_len = tmplen;
+		map_length -= tmplen;
+		(*iovix)++;
+	}
+	DEBUG(printk("map_page_to_iovec, exit, *iovix=%d\n", *iovix));
+	return -1;
+}
+
+
+
+static int cryptocop_ioctl_process(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
+{
+	int                             i;
+	struct cryptocop_private        *dev = filp->private_data;
+	struct strcop_crypto_op         *crp_oper = (struct strcop_crypto_op *)arg;
+	struct strcop_crypto_op         oper = {0};
+	int                             err = 0;
+	struct cryptocop_operation      *cop = NULL;
+
+	struct ioctl_job_cb_ctx         *jc = NULL;
+
+	struct page                     **inpages = NULL;
+	struct page                     **outpages = NULL;
+	int                             noinpages = 0;
+	int                             nooutpages = 0;
+
+	struct cryptocop_desc           descs[5]; /* Max 5 descriptors are needed, there are three transforms that
+						   * can get connected/disconnected on different places in the indata. */
+	struct cryptocop_desc_cfg       dcfgs[5*3];
+	int                             desc_ix = 0;
+	int                             dcfg_ix = 0;
+	struct cryptocop_tfrm_cfg       ciph_tcfg = {0};
+	struct cryptocop_tfrm_cfg       digest_tcfg = {0};
+	struct cryptocop_tfrm_cfg       csum_tcfg = {0};
+
+	unsigned char                   *digest_result = NULL;
+	int                             digest_length = 0;
+	int                             cblocklen = 0;
+	unsigned char                   csum_result[CSUM_BLOCK_LENGTH];
+	struct cryptocop_session        *sess;
+
+	int    iovlen = 0;
+	int    iovix = 0;
+	int    pageix = 0;
+	int    pageoffset = 0;
+
+	size_t prev_ix = 0;
+	size_t next_ix;
+
+	int    cipher_active, digest_active, csum_active;
+	int    end_digest, end_csum;
+	int    digest_done = 0;
+	int    cipher_done = 0;
+	int    csum_done = 0;
+
+	DEBUG(printk("cryptocop_ioctl_process\n"));
+
+	if (!access_ok(VERIFY_WRITE, crp_oper, sizeof(struct strcop_crypto_op))){
+		DEBUG_API(printk("cryptocop_ioctl_process: !access_ok crp_oper!\n"));
+		return -EFAULT;
+	}
+	if (copy_from_user(&oper, crp_oper, sizeof(struct strcop_crypto_op))) {
+		DEBUG_API(printk("cryptocop_ioctl_process: copy_from_user\n"));
+		return -EFAULT;
+	}
+	DEBUG(print_strcop_crypto_op(&oper));
+
+	while (dev && dev->sid != oper.ses_id) dev = dev->next;
+	if (!dev){
+		DEBUG_API(printk("cryptocop_ioctl_process: session %lld not found\n", oper.ses_id));
+		return -EINVAL;
+	}
+
+	/* Check buffers. */
+	if (((oper.indata + oper.inlen) < oper.indata) || ((oper.cipher_outdata + oper.cipher_outlen) < oper.cipher_outdata)){
+		DEBUG_API(printk("cryptocop_ioctl_process: user buffers wrapped around, bad user!\n"));
+		return -EINVAL;
+	}
+
+	if (!access_ok(VERIFY_WRITE, oper.cipher_outdata, oper.cipher_outlen)){
+		DEBUG_API(printk("cryptocop_ioctl_process: !access_ok out data!\n"));
+		return -EFAULT;
+	}
+	if (!access_ok(VERIFY_READ, oper.indata, oper.inlen)){
+		DEBUG_API(printk("cryptocop_ioctl_process: !access_ok in data!\n"));
+		return -EFAULT;
+	}
+
+	cop = kmalloc(sizeof(struct cryptocop_operation), GFP_KERNEL);
+	if (!cop) {
+		DEBUG_API(printk("cryptocop_ioctl_process: kmalloc\n"));
+		return -ENOMEM;
+	}
+	jc = kmalloc(sizeof(struct ioctl_job_cb_ctx), GFP_KERNEL);
+	if (!jc) {
+		DEBUG_API(printk("cryptocop_ioctl_process: kmalloc\n"));
+		err = -ENOMEM;
+		goto error_cleanup;
+	}
+	jc->processed = 0;
+
+	cop->cb_data = jc;
+	cop->cb = ioctl_process_job_callback;
+	cop->operation_status = 0;
+	cop->use_dmalists = 0;
+	cop->in_interrupt = 0;
+	cop->fast_callback = 0;
+	cop->tfrm_op.tfrm_cfg = NULL;
+	cop->tfrm_op.desc = NULL;
+	cop->tfrm_op.indata = NULL;
+	cop->tfrm_op.incount = 0;
+	cop->tfrm_op.inlen = 0;
+	cop->tfrm_op.outdata = NULL;
+	cop->tfrm_op.outcount = 0;
+	cop->tfrm_op.outlen = 0;
+
+	sess = get_session(oper.ses_id);
+	if (!sess){
+		DEBUG_API(printk("cryptocop_ioctl_process: bad session id.\n"));
+		kfree(cop);
+		kfree(jc);
+		return -EINVAL;
+	}
+
+	if (oper.do_cipher) {
+		unsigned int                    cipher_outlen = 0;
+		struct cryptocop_transform_ctx  *tc = get_transform_ctx(sess, CRYPTOCOP_IOCTL_CIPHER_TID);
+		if (!tc) {
+			DEBUG_API(printk("cryptocop_ioctl_process: no cipher transform in session.\n"));
+			err = -EINVAL;
+			goto error_cleanup;
+		}
+		ciph_tcfg.tid = CRYPTOCOP_IOCTL_CIPHER_TID;
+		ciph_tcfg.inject_ix = 0;
+		ciph_tcfg.flags = 0;
+		if ((oper.cipher_start < 0) || (oper.cipher_len <= 0) || (oper.cipher_start > oper.inlen) || ((oper.cipher_start + oper.cipher_len) > oper.inlen)){
+			DEBUG_API(printk("cryptocop_ioctl_process: bad cipher length\n"));
+			kfree(cop);
+			kfree(jc);
+			return -EINVAL;
+		}
+		cblocklen = tc->init.alg == cryptocop_alg_aes ? AES_BLOCK_LENGTH : DES_BLOCK_LENGTH;
+		if (oper.cipher_len % cblocklen) {
+			kfree(cop);
+			kfree(jc);
+			DEBUG_API(printk("cryptocop_ioctl_process: cipher inlength not multiple of block length.\n"));
+			return -EINVAL;
+		}
+		cipher_outlen = oper.cipher_len;
+		if (tc->init.cipher_mode == cryptocop_cipher_mode_cbc){
+			if (oper.cipher_explicit) {
+				ciph_tcfg.flags |= CRYPTOCOP_EXPLICIT_IV;
+				memcpy(ciph_tcfg.iv, oper.cipher_iv, cblocklen);
+			} else {
+				cipher_outlen = oper.cipher_len - cblocklen;
+			}
+		} else {
+			if (oper.cipher_explicit){
+				kfree(cop);
+				kfree(jc);
+				DEBUG_API(printk("cryptocop_ioctl_process: explicit_iv when not CBC mode\n"));
+				return -EINVAL;
+			}
+		}
+		if (oper.cipher_outlen != cipher_outlen) {
+			kfree(cop);
+			kfree(jc);
+			DEBUG_API(printk("cryptocop_ioctl_process: cipher_outlen incorrect, should be %d not %d.\n", cipher_outlen, oper.cipher_outlen));
+			return -EINVAL;
+		}
+
+		if (oper.decrypt){
+			ciph_tcfg.flags |= CRYPTOCOP_DECRYPT;
+		} else {
+			ciph_tcfg.flags |= CRYPTOCOP_ENCRYPT;
+		}
+		ciph_tcfg.next = cop->tfrm_op.tfrm_cfg;
+		cop->tfrm_op.tfrm_cfg = &ciph_tcfg;
+	}
+	if (oper.do_digest){
+		struct cryptocop_transform_ctx *tc = get_transform_ctx(sess, CRYPTOCOP_IOCTL_DIGEST_TID);
+		if (!tc) {
+			DEBUG_API(printk("cryptocop_ioctl_process: no digest transform in session.\n"));
+			err = -EINVAL;
+			goto error_cleanup;
+		}
+		digest_length = tc->init.alg == cryptocop_alg_md5 ? 16 : 20;
+		digest_result = kmalloc(digest_length, GFP_KERNEL);
+		if (!digest_result) {
+			DEBUG_API(printk("cryptocop_ioctl_process: kmalloc digest_result\n"));
+			err = -EINVAL;
+			goto error_cleanup;
+		}
+		DEBUG(memset(digest_result, 0xff, digest_length));
+
+		digest_tcfg.tid = CRYPTOCOP_IOCTL_DIGEST_TID;
+		digest_tcfg.inject_ix = 0;
+		ciph_tcfg.inject_ix += digest_length;
+		if ((oper.digest_start < 0) || (oper.digest_len <= 0) || (oper.digest_start > oper.inlen) || ((oper.digest_start + oper.digest_len) > oper.inlen)){
+			DEBUG_API(printk("cryptocop_ioctl_process: bad digest length\n"));
+			err = -EINVAL;
+			goto error_cleanup;
+		}
+
+		digest_tcfg.next = cop->tfrm_op.tfrm_cfg;
+		cop->tfrm_op.tfrm_cfg = &digest_tcfg;
+	}
+	if (oper.do_csum){
+		csum_tcfg.tid = CRYPTOCOP_IOCTL_CSUM_TID;
+		csum_tcfg.inject_ix = digest_length;
+		ciph_tcfg.inject_ix += 2;
+
+		if ((oper.csum_start < 0) || (oper.csum_len <= 0) || (oper.csum_start > oper.inlen) || ((oper.csum_start + oper.csum_len) > oper.inlen)){
+			DEBUG_API(printk("cryptocop_ioctl_process: bad csum length\n"));
+			kfree(cop);
+			kfree(jc);
+			return -EINVAL;
+		}
+
+		csum_tcfg.next = cop->tfrm_op.tfrm_cfg;
+		cop->tfrm_op.tfrm_cfg = &csum_tcfg;
+	}
+
+	prev_ix = first_cfg_change_ix(&oper);
+	if (prev_ix > oper.inlen) {
+		DEBUG_API(printk("cryptocop_ioctl_process: length mismatch\n"));
+		nooutpages = noinpages = 0;
+		err = -EINVAL;
+		goto error_cleanup;
+	}
+	DEBUG(printk("cryptocop_ioctl_process: inlen=%d, cipher_outlen=%d\n", oper.inlen, oper.cipher_outlen));
+
+	/* Map user pages for in and out data of the operation. */
+	noinpages = (((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK) + oper.inlen - 1 - prev_ix + ~PAGE_MASK) >> PAGE_SHIFT;
+	DEBUG(printk("cryptocop_ioctl_process: noinpages=%d\n", noinpages));
+	inpages = kmalloc(noinpages * sizeof(struct page*), GFP_KERNEL);
+	if (!inpages){
+		DEBUG_API(printk("cryptocop_ioctl_process: kmalloc inpages\n"));
+		nooutpages = noinpages = 0;
+		err = -ENOMEM;
+		goto error_cleanup;
+	}
+	if (oper.do_cipher){
+		nooutpages = (((unsigned long int)oper.cipher_outdata & ~PAGE_MASK) + oper.cipher_outlen - 1 + ~PAGE_MASK) >> PAGE_SHIFT;
+		DEBUG(printk("cryptocop_ioctl_process: nooutpages=%d\n", nooutpages));
+		outpages = kmalloc(nooutpages * sizeof(struct page*), GFP_KERNEL);
+		if (!outpages){
+			DEBUG_API(printk("cryptocop_ioctl_process: kmalloc outpages\n"));
+			nooutpages = noinpages = 0;
+			err = -ENOMEM;
+			goto error_cleanup;
+		}
+	}
+
+	/* Acquire the mm page semaphore. */
+	down_read(&current->mm->mmap_sem);
+
+	err = get_user_pages(current,
+			     current->mm,
+			     (unsigned long int)(oper.indata + prev_ix),
+			     noinpages,
+			     0,  /* read access only for in data */
+			     0, /* no force */
+			     inpages,
+			     NULL);
+
+	if (err < 0) {
+		up_read(&current->mm->mmap_sem);
+		nooutpages = noinpages = 0;
+		DEBUG_API(printk("cryptocop_ioctl_process: get_user_pages indata\n"));
+		goto error_cleanup;
+	}
+	noinpages = err;
+	if (oper.do_cipher){
+		err = get_user_pages(current,
+				     current->mm,
+				     (unsigned long int)oper.cipher_outdata,
+				     nooutpages,
+				     1, /* write access for out data */
+				     0, /* no force */
+				     outpages,
+				     NULL);
+		up_read(&current->mm->mmap_sem);
+		if (err < 0) {
+			nooutpages = 0;
+			DEBUG_API(printk("cryptocop_ioctl_process: get_user_pages outdata\n"));
+			goto error_cleanup;
+		}
+		nooutpages = err;
+	} else {
+		up_read(&current->mm->mmap_sem);
+	}
+
+	/* Add 6 to nooutpages to make room for possibly inserted buffers for storing digest and
+	 * csum output and splits when units are (dis-)connected. */
+	cop->tfrm_op.indata = kmalloc((noinpages) * sizeof(struct iovec), GFP_KERNEL);
+	cop->tfrm_op.outdata = kmalloc((6 + nooutpages) * sizeof(struct iovec), GFP_KERNEL);
+	if (!cop->tfrm_op.indata || !cop->tfrm_op.outdata) {
+		DEBUG_API(printk("cryptocop_ioctl_process: kmalloc iovecs\n"));
+		err = -ENOMEM;
+		goto error_cleanup;
+	}
+
+	cop->tfrm_op.inlen = oper.inlen - prev_ix;
+	cop->tfrm_op.outlen = 0;
+	if (oper.do_cipher) cop->tfrm_op.outlen += oper.cipher_outlen;
+	if (oper.do_digest) cop->tfrm_op.outlen += digest_length;
+	if (oper.do_csum) cop->tfrm_op.outlen += 2;
+
+	/* Setup the in iovecs. */
+	cop->tfrm_op.incount = noinpages;
+	if (noinpages > 1){
+		size_t tmplen = cop->tfrm_op.inlen;
+
+		cop->tfrm_op.indata[0].iov_len = PAGE_SIZE - ((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK);
+		cop->tfrm_op.indata[0].iov_base = (unsigned char*)page_address(inpages[0]) + ((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK);
+		tmplen -= cop->tfrm_op.indata[0].iov_len;
+		for (i = 1; i<noinpages; i++){
+			cop->tfrm_op.indata[i].iov_len = tmplen < PAGE_SIZE ? tmplen : PAGE_SIZE;
+			cop->tfrm_op.indata[i].iov_base = (unsigned char*)page_address(inpages[i]);
+			tmplen -= PAGE_SIZE;
+		}
+	} else {
+		cop->tfrm_op.indata[0].iov_len = oper.inlen - prev_ix;
+		cop->tfrm_op.indata[0].iov_base = (unsigned char*)page_address(inpages[0]) + ((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK);
+	}
+
+	iovlen = nooutpages + 6;
+	pageoffset = oper.do_cipher ? ((unsigned long int)oper.cipher_outdata & ~PAGE_MASK) : 0;
+
+	next_ix = next_cfg_change_ix(&oper, prev_ix);
+	if (prev_ix == next_ix){
+		DEBUG_API(printk("cryptocop_ioctl_process: length configuration broken.\n"));
+		err = -EINVAL;  /* This should be impossible barring bugs. */
+		goto error_cleanup;
+	}
+	while (prev_ix != next_ix){
+		end_digest = end_csum = cipher_active = digest_active = csum_active = 0;
+		descs[desc_ix].cfg = NULL;
+		descs[desc_ix].length = next_ix - prev_ix;
+
+		if (oper.do_cipher && (oper.cipher_start < next_ix) && (prev_ix < (oper.cipher_start + oper.cipher_len))) {
+			dcfgs[dcfg_ix].tid = CRYPTOCOP_IOCTL_CIPHER_TID;
+			dcfgs[dcfg_ix].src = cryptocop_source_dma;
+			cipher_active = 1;
+
+			if (next_ix == (oper.cipher_start + oper.cipher_len)){
+				cipher_done = 1;
+				dcfgs[dcfg_ix].last = 1;
+			} else {
+				dcfgs[dcfg_ix].last = 0;
+			}
+			dcfgs[dcfg_ix].next = descs[desc_ix].cfg;
+			descs[desc_ix].cfg = &dcfgs[dcfg_ix];
+			++dcfg_ix;
+		}
+		if (oper.do_digest && (oper.digest_start < next_ix) && (prev_ix < (oper.digest_start + oper.digest_len))) {
+			digest_active = 1;
+			dcfgs[dcfg_ix].tid = CRYPTOCOP_IOCTL_DIGEST_TID;
+			dcfgs[dcfg_ix].src = cryptocop_source_dma;
+			if (next_ix == (oper.digest_start + oper.digest_len)){
+				assert(!digest_done);
+				digest_done = 1;
+				dcfgs[dcfg_ix].last = 1;
+			} else {
+				dcfgs[dcfg_ix].last = 0;
+			}
+			dcfgs[dcfg_ix].next = descs[desc_ix].cfg;
+			descs[desc_ix].cfg = &dcfgs[dcfg_ix];
+			++dcfg_ix;
+		}
+		if (oper.do_csum && (oper.csum_start < next_ix) && (prev_ix < (oper.csum_start + oper.csum_len))){
+			csum_active = 1;
+			dcfgs[dcfg_ix].tid = CRYPTOCOP_IOCTL_CSUM_TID;
+			dcfgs[dcfg_ix].src = cryptocop_source_dma;
+			if (next_ix == (oper.csum_start + oper.csum_len)){
+				csum_done = 1;
+				dcfgs[dcfg_ix].last = 1;
+			} else {
+				dcfgs[dcfg_ix].last = 0;
+			}
+			dcfgs[dcfg_ix].next = descs[desc_ix].cfg;
+			descs[desc_ix].cfg = &dcfgs[dcfg_ix];
+			++dcfg_ix;
+		}
+		if (!descs[desc_ix].cfg){
+			DEBUG_API(printk("cryptocop_ioctl_process: data segment %d (%d to %d) had no active transforms\n", desc_ix, prev_ix, next_ix));
+			err = -EINVAL;
+			goto error_cleanup;
+		}
+		descs[desc_ix].next = &(descs[desc_ix]) + 1;
+		++desc_ix;
+		prev_ix = next_ix;
+		next_ix = next_cfg_change_ix(&oper, prev_ix);
+	}
+	if (desc_ix > 0){
+		descs[desc_ix-1].next = NULL;
+	} else {
+		descs[0].next = NULL;
+	}
+	if (oper.do_digest) {
+		DEBUG(printk("cryptocop_ioctl_process: mapping %d byte digest output to iovec %d\n", digest_length, iovix));
+		/* Add outdata iovec, length == <length of type of digest> */
+		cop->tfrm_op.outdata[iovix].iov_base = digest_result;
+		cop->tfrm_op.outdata[iovix].iov_len = digest_length;
+		++iovix;
+	}
+	if (oper.do_csum) {
+		/* Add outdata iovec, length == 2, the length of csum. */
+		DEBUG(printk("cryptocop_ioctl_process: mapping 2 byte csum output to iovec %d\n", iovix));
+		/* Add outdata iovec, length == <length of type of digest> */
+		cop->tfrm_op.outdata[iovix].iov_base = csum_result;
+		cop->tfrm_op.outdata[iovix].iov_len = 2;
+		++iovix;
+	}
+	if (oper.do_cipher) {
+		if (!map_pages_to_iovec(cop->tfrm_op.outdata, iovlen, &iovix, outpages, nooutpages, &pageix, &pageoffset, oper.cipher_outlen)){
+			DEBUG_API(printk("cryptocop_ioctl_process: failed to map pages to iovec.\n"));
+			err = -ENOSYS; /* This should be impossible barring bugs. */
+			goto error_cleanup;
+		}
+	}
+	DEBUG(printk("cryptocop_ioctl_process: setting cop->tfrm_op.outcount %d\n", iovix));
+	cop->tfrm_op.outcount = iovix;
+	assert(iovix <= (nooutpages + 6));
+
+	cop->sid = oper.ses_id;
+	cop->tfrm_op.desc = &descs[0];
+
+	DEBUG(printk("cryptocop_ioctl_process: inserting job, cb_data=0x%p\n", cop->cb_data));
+
+	if ((err = cryptocop_job_queue_insert_user_job(cop)) != 0) {
+		DEBUG_API(printk("cryptocop_ioctl_process: insert job %d\n", err));
+		err = -EINVAL;
+		goto error_cleanup;
+	}
+
+	DEBUG(printk("cryptocop_ioctl_process: begin wait for result\n"));
+
+	wait_event(cryptocop_ioc_process_wq, (jc->processed != 0));
+	DEBUG(printk("cryptocop_ioctl_process: end wait for result\n"));
+        if (!jc->processed){
+		printk(KERN_WARNING "cryptocop_ioctl_process: job not processed at completion\n");
+		err = -EIO;
+		goto error_cleanup;
+	}
+
+	/* Job process done.  Cipher output should already be correct in job so no post processing of outdata. */
+	DEBUG(printk("cryptocop_ioctl_process: operation_status = %d\n", cop->operation_status));
+	if (cop->operation_status == 0){
+		if (oper.do_digest){
+			DEBUG(printk("cryptocop_ioctl_process: copy %d bytes digest to user\n", digest_length));
+			err = copy_to_user((unsigned char*)crp_oper + offsetof(struct strcop_crypto_op, digest), digest_result, digest_length);
+			if (0 != err){
+				DEBUG_API(printk("cryptocop_ioctl_process: copy_to_user, digest length %d, err %d\n", digest_length, err));
+				err = -EFAULT;
+				goto error_cleanup;
+			}
+		}
+		if (oper.do_csum){
+			DEBUG(printk("cryptocop_ioctl_process: copy 2 bytes checksum to user\n"));
+			err = copy_to_user((unsigned char*)crp_oper + offsetof(struct strcop_crypto_op, csum), csum_result, 2);
+			if (0 != err){
+				DEBUG_API(printk("cryptocop_ioctl_process: copy_to_user, csum, err %d\n", err));
+				err = -EFAULT;
+				goto error_cleanup;
+			}
+		}
+		err = 0;
+	} else {
+		DEBUG(printk("cryptocop_ioctl_process: returning err = operation_status = %d\n", cop->operation_status));
+		err = cop->operation_status;
+	}
+
+ error_cleanup:
+	/* Release page caches. */
+	for (i = 0; i < noinpages; i++){
+		put_page(inpages[i]);
+	}
+	for (i = 0; i < nooutpages; i++){
+		int spdl_err;
+		/* Mark output pages dirty. */
+		spdl_err = set_page_dirty_lock(outpages[i]);
+		DEBUG(if (spdl_err)printk("cryptocop_ioctl_process: set_page_dirty_lock returned %d\n", spdl_err));
+	}
+	for (i = 0; i < nooutpages; i++){
+		put_page(outpages[i]);
+	}
+
+	if (digest_result) kfree(digest_result);
+	if (inpages) kfree(inpages);
+	if (outpages) kfree(outpages);
+	if (cop){
+		if (cop->tfrm_op.indata) kfree(cop->tfrm_op.indata);
+		if (cop->tfrm_op.outdata) kfree(cop->tfrm_op.outdata);
+		kfree(cop);
+	}
+	if (jc) kfree(jc);
+
+	DEBUG(print_lock_status());
+
+	return err;
+}
+
+
+static int cryptocop_ioctl_create_session(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
+{
+	cryptocop_session_id             sid;
+	int                              err;
+	struct cryptocop_private         *dev;
+	struct strcop_session_op         *sess_op = (struct strcop_session_op *)arg;
+	struct strcop_session_op         sop;
+	struct cryptocop_transform_init  *tis = NULL;
+	struct cryptocop_transform_init  ti_cipher = {0};
+	struct cryptocop_transform_init  ti_digest = {0};
+	struct cryptocop_transform_init  ti_csum = {0};
+
+	if (!access_ok(VERIFY_WRITE, sess_op, sizeof(struct strcop_session_op)))
+		return -EFAULT;
+	err = copy_from_user(&sop, sess_op, sizeof(struct strcop_session_op));
+	if (err) return -EFAULT;
+	if (sop.cipher != cryptocop_cipher_none) {
+		if (!access_ok(VERIFY_READ, sop.key, sop.keylen)) return -EFAULT;
+	}
+	DEBUG(printk("cryptocop_ioctl_create_session, sess_op:\n"));
+
+	DEBUG(printk("\tcipher:%d\n"
+		     "\tcipher_mode:%d\n"
+		     "\tdigest:%d\n"
+		     "\tcsum:%d\n",
+		     (int)sop.cipher,
+		     (int)sop.cmode,
+		     (int)sop.digest,
+		     (int)sop.csum));
+
+	if (sop.cipher != cryptocop_cipher_none){
+		/* Init the cipher. */
+		switch (sop.cipher){
+		case cryptocop_cipher_des:
+			ti_cipher.alg = cryptocop_alg_des;
+			break;
+		case cryptocop_cipher_3des:
+			ti_cipher.alg = cryptocop_alg_3des;
+			break;
+		case cryptocop_cipher_aes:
+			ti_cipher.alg = cryptocop_alg_aes;
+			break;
+		default:
+			DEBUG_API(printk("create session, bad cipher algorithm %d\n", sop.cipher));
+			return -EINVAL;
+		};
+		DEBUG(printk("setting cipher transform %d\n", ti_cipher.alg));
+		copy_from_user(ti_cipher.key, sop.key, sop.keylen/8);
+		ti_cipher.keylen = sop.keylen;
+		switch (sop.cmode){
+		case cryptocop_cipher_mode_cbc:
+		case cryptocop_cipher_mode_ecb:
+			ti_cipher.cipher_mode = sop.cmode;
+			break;
+		default:
+			DEBUG_API(printk("create session, bad cipher mode %d\n", sop.cmode));
+			return -EINVAL;
+		}
+		DEBUG(printk("cryptocop_ioctl_create_session: setting CBC mode %d\n", ti_cipher.cipher_mode));
+		switch (sop.des3_mode){
+		case cryptocop_3des_eee:
+		case cryptocop_3des_eed:
+		case cryptocop_3des_ede:
+		case cryptocop_3des_edd:
+		case cryptocop_3des_dee:
+		case cryptocop_3des_ded:
+		case cryptocop_3des_dde:
+		case cryptocop_3des_ddd:
+			ti_cipher.tdes_mode = sop.des3_mode;
+			break;
+		default:
+			DEBUG_API(printk("create session, bad 3DES mode %d\n", sop.des3_mode));
+			return -EINVAL;
+		}
+		ti_cipher.tid = CRYPTOCOP_IOCTL_CIPHER_TID;
+		ti_cipher.next = tis;
+		tis = &ti_cipher;
+	} /* if (sop.cipher != cryptocop_cipher_none) */
+	if (sop.digest != cryptocop_digest_none){
+		DEBUG(printk("setting digest transform\n"));
+		switch (sop.digest){
+		case cryptocop_digest_md5:
+			ti_digest.alg = cryptocop_alg_md5;
+			break;
+		case cryptocop_digest_sha1:
+			ti_digest.alg = cryptocop_alg_sha1;
+			break;
+		default:
+			DEBUG_API(printk("create session, bad digest algorithm %d\n", sop.digest));
+			return -EINVAL;
+		}
+		ti_digest.tid = CRYPTOCOP_IOCTL_DIGEST_TID;
+		ti_digest.next = tis;
+		tis = &ti_digest;
+	} /* if (sop.digest != cryptocop_digest_none) */
+	if (sop.csum != cryptocop_csum_none){
+		DEBUG(printk("setting csum transform\n"));
+		switch (sop.csum){
+		case cryptocop_csum_le:
+		case cryptocop_csum_be:
+			ti_csum.csum_mode = sop.csum;
+			break;
+		default:
+			DEBUG_API(printk("create session, bad checksum algorithm %d\n", sop.csum));
+			return -EINVAL;
+		}
+		ti_csum.alg = cryptocop_alg_csum;
+		ti_csum.tid = CRYPTOCOP_IOCTL_CSUM_TID;
+		ti_csum.next = tis;
+		tis = &ti_csum;
+	} /* (sop.csum != cryptocop_csum_none) */
+	dev = kmalloc(sizeof(struct cryptocop_private), GFP_KERNEL);
+	if (!dev){
+		DEBUG_API(printk("create session, alloc dev\n"));
+		return -ENOMEM;
+	}
+
+	err = cryptocop_new_session(&sid, tis, GFP_KERNEL);
+	DEBUG({ if (err) printk("create session, cryptocop_new_session %d\n", err);});
+
+	if (err) {
+		kfree(dev);
+		return err;
+	}
+	sess_op->ses_id = sid;
+	dev->sid = sid;
+	dev->next = filp->private_data;
+	filp->private_data = dev;
+
+	return 0;
+}
+
+static int cryptocop_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
+{
+	int err = 0;
+	if (_IOC_TYPE(cmd) != ETRAXCRYPTOCOP_IOCTYPE) {
+		DEBUG_API(printk("cryptocop_ioctl: wrong type\n"));
+		return -ENOTTY;
+	}
+	if (_IOC_NR(cmd) > CRYPTOCOP_IO_MAXNR){
+		return -ENOTTY;
+	}
+	/* Access check of the argument.  Some commands, e.g. create session and process op,
+	   needs additional checks.  Those are handled in the command handling functions. */
+	if (_IOC_DIR(cmd) & _IOC_READ)
+		err = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd));
+	else if (_IOC_DIR(cmd) & _IOC_WRITE)
+		err = !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd));
+	if (err) return -EFAULT;
+
+	switch (cmd) {
+	case CRYPTOCOP_IO_CREATE_SESSION:
+		return cryptocop_ioctl_create_session(inode, filp, cmd, arg);
+	case CRYPTOCOP_IO_CLOSE_SESSION:
+		return cryptocop_ioctl_close_session(inode, filp, cmd, arg);
+	case CRYPTOCOP_IO_PROCESS_OP:
+		return cryptocop_ioctl_process(inode, filp, cmd, arg);
+	default:
+		DEBUG_API(printk("cryptocop_ioctl: unknown command\n"));
+		return -ENOTTY;
+	}
+	return 0;
+}
+
+
+#ifdef LDEBUG
+static void print_dma_descriptors(struct cryptocop_int_operation *iop)
+{
+	struct cryptocop_dma_desc *cdesc_out = iop->cdesc_out;
+	struct cryptocop_dma_desc *cdesc_in = iop->cdesc_in;
+	int                       i;
+
+	printk("print_dma_descriptors start\n");
+
+	printk("iop:\n");
+	printk("\tsid: 0x%lld\n", iop->sid);
+
+	printk("\tcdesc_out: 0x%p\n", iop->cdesc_out);
+	printk("\tcdesc_in: 0x%p\n", iop->cdesc_in);
+	printk("\tddesc_out: 0x%p\n", iop->ddesc_out);
+	printk("\tddesc_in: 0x%p\n", iop->ddesc_in);
+
+	printk("\niop->ctx_out: 0x%p phys: 0x%p\n", &iop->ctx_out, (char*)virt_to_phys(&iop->ctx_out));
+	printk("\tnext: 0x%p\n"
+	       "\tsaved_data: 0x%p\n"
+	       "\tsaved_data_buf: 0x%p\n",
+	       iop->ctx_out.next,
+	       iop->ctx_out.saved_data,
+	       iop->ctx_out.saved_data_buf);
+
+	printk("\niop->ctx_in: 0x%p phys: 0x%p\n", &iop->ctx_in, (char*)virt_to_phys(&iop->ctx_in));
+	printk("\tnext: 0x%p\n"
+	       "\tsaved_data: 0x%p\n"
+	       "\tsaved_data_buf: 0x%p\n",
+	       iop->ctx_in.next,
+	       iop->ctx_in.saved_data,
+	       iop->ctx_in.saved_data_buf);
+
+	i = 0;
+	while (cdesc_out) {
+		dma_descr_data *td;
+		printk("cdesc_out %d, desc=0x%p\n", i, cdesc_out->dma_descr);
+		printk("\n\tvirt_to_phys(desc): 0x%p\n", (char*)virt_to_phys(cdesc_out->dma_descr));
+		td = cdesc_out->dma_descr;
+		printk("\n\tbuf: 0x%p\n"
+		       "\tafter: 0x%p\n"
+		       "\tmd: 0x%04x\n"
+		       "\tnext: 0x%p\n",
+		       td->buf,
+		       td->after,
+		       td->md,
+		       td->next);
+		printk("flags:\n"
+		       "\twait:\t%d\n"
+		       "\teol:\t%d\n"
+		       "\touteop:\t%d\n"
+		       "\tineop:\t%d\n"
+		       "\tintr:\t%d\n",
+		       td->wait,
+		       td->eol,
+		       td->out_eop,
+		       td->in_eop,
+		       td->intr);
+		cdesc_out = cdesc_out->next;
+		i++;
+	}
+	i = 0;
+	while (cdesc_in) {
+		dma_descr_data *td;
+		printk("cdesc_in %d, desc=0x%p\n", i, cdesc_in->dma_descr);
+		printk("\n\tvirt_to_phys(desc): 0x%p\n", (char*)virt_to_phys(cdesc_in->dma_descr));
+		td = cdesc_in->dma_descr;
+		printk("\n\tbuf: 0x%p\n"
+		       "\tafter: 0x%p\n"
+		       "\tmd: 0x%04x\n"
+		       "\tnext: 0x%p\n",
+		       td->buf,
+		       td->after,
+		       td->md,
+		       td->next);
+		printk("flags:\n"
+		       "\twait:\t%d\n"
+		       "\teol:\t%d\n"
+		       "\touteop:\t%d\n"
+		       "\tineop:\t%d\n"
+		       "\tintr:\t%d\n",
+		       td->wait,
+		       td->eol,
+		       td->out_eop,
+		       td->in_eop,
+		       td->intr);
+		cdesc_in = cdesc_in->next;
+		i++;
+	}
+
+	printk("print_dma_descriptors end\n");
+}
+
+
+static void print_strcop_crypto_op(struct strcop_crypto_op *cop)
+{
+	printk("print_strcop_crypto_op, 0x%p\n", cop);
+
+	/* Indata. */
+	printk("indata=0x%p\n"
+	       "inlen=%d\n"
+	       "do_cipher=%d\n"
+	       "decrypt=%d\n"
+	       "cipher_explicit=%d\n"
+	       "cipher_start=%d\n"
+	       "cipher_len=%d\n"
+	       "outdata=0x%p\n"
+	       "outlen=%d\n",
+	       cop->indata,
+	       cop->inlen,
+	       cop->do_cipher,
+	       cop->decrypt,
+	       cop->cipher_explicit,
+	       cop->cipher_start,
+	       cop->cipher_len,
+	       cop->cipher_outdata,
+	       cop->cipher_outlen);
+
+	printk("do_digest=%d\n"
+	       "digest_start=%d\n"
+	       "digest_len=%d\n",
+	       cop->do_digest,
+	       cop->digest_start,
+	       cop->digest_len);
+
+	printk("do_csum=%d\n"
+	       "csum_start=%d\n"
+	       "csum_len=%d\n",
+	       cop->do_csum,
+	       cop->csum_start,
+	       cop->csum_len);
+}
+
+static void print_cryptocop_operation(struct cryptocop_operation *cop)
+{
+	struct cryptocop_desc      *d;
+	struct cryptocop_tfrm_cfg  *tc;
+	struct cryptocop_desc_cfg  *dc;
+	int                        i;
+
+	printk("print_cryptocop_operation, cop=0x%p\n\n", cop);
+	printk("sid: %lld\n", cop->sid);
+	printk("operation_status=%d\n"
+	       "use_dmalists=%d\n"
+	       "in_interrupt=%d\n"
+	       "fast_callback=%d\n",
+	       cop->operation_status,
+	       cop->use_dmalists,
+	       cop->in_interrupt,
+	       cop->fast_callback);
+
+	if (cop->use_dmalists){
+		print_user_dma_lists(&cop->list_op);
+	} else {
+		printk("cop->tfrm_op\n"
+		       "tfrm_cfg=0x%p\n"
+		       "desc=0x%p\n"
+		       "indata=0x%p\n"
+		       "incount=%d\n"
+		       "inlen=%d\n"
+		       "outdata=0x%p\n"
+		       "outcount=%d\n"
+		       "outlen=%d\n\n",
+		       cop->tfrm_op.tfrm_cfg,
+		       cop->tfrm_op.desc,
+		       cop->tfrm_op.indata,
+		       cop->tfrm_op.incount,
+		       cop->tfrm_op.inlen,
+		       cop->tfrm_op.outdata,
+		       cop->tfrm_op.outcount,
+		       cop->tfrm_op.outlen);
+
+		tc = cop->tfrm_op.tfrm_cfg;
+		while (tc){
+			printk("tfrm_cfg, 0x%p\n"
+			       "tid=%d\n"
+			       "flags=%d\n"
+			       "inject_ix=%d\n"
+			       "next=0x%p\n",
+			       tc,
+			       tc->tid,
+			       tc->flags,
+			       tc->inject_ix,
+			       tc->next);
+			tc = tc->next;
+		}
+		d = cop->tfrm_op.desc;
+		while (d){
+			printk("\n======================desc, 0x%p\n"
+			       "length=%d\n"
+			       "cfg=0x%p\n"
+			       "next=0x%p\n",
+			       d,
+			       d->length,
+			       d->cfg,
+			       d->next);
+			dc = d->cfg;
+			while (dc){
+				printk("=========desc_cfg, 0x%p\n"
+				       "tid=%d\n"
+				       "src=%d\n"
+				       "last=%d\n"
+				       "next=0x%p\n",
+				       dc,
+				       dc->tid,
+				       dc->src,
+				       dc->last,
+				       dc->next);
+				dc = dc->next;
+			}
+			d = d->next;
+		}
+		printk("\n====iniov\n");
+		for (i = 0; i < cop->tfrm_op.incount; i++){
+			printk("indata[%d]\n"
+			       "base=0x%p\n"
+			       "len=%d\n",
+			       i,
+			       cop->tfrm_op.indata[i].iov_base,
+			       cop->tfrm_op.indata[i].iov_len);
+		}
+		printk("\n====outiov\n");
+		for (i = 0; i < cop->tfrm_op.outcount; i++){
+			printk("outdata[%d]\n"
+			       "base=0x%p\n"
+			       "len=%d\n",
+			       i,
+			       cop->tfrm_op.outdata[i].iov_base,
+			       cop->tfrm_op.outdata[i].iov_len);
+		}
+	}
+	printk("------------end print_cryptocop_operation\n");
+}
+
+
+static void print_user_dma_lists(struct cryptocop_dma_list_operation *dma_op)
+{
+	dma_descr_data *dd;
+	int i;
+
+	printk("print_user_dma_lists, dma_op=0x%p\n", dma_op);
+
+	printk("out_data_buf = 0x%p, phys_to_virt(out_data_buf) = 0x%p\n", dma_op->out_data_buf, phys_to_virt((unsigned long int)dma_op->out_data_buf));
+	printk("in_data_buf = 0x%p, phys_to_virt(in_data_buf) = 0x%p\n", dma_op->in_data_buf, phys_to_virt((unsigned long int)dma_op->in_data_buf));
+
+	printk("##############outlist\n");
+	dd = phys_to_virt((unsigned long int)dma_op->outlist);
+	i = 0;
+	while (dd != NULL) {
+		printk("#%d phys_to_virt(desc) 0x%p\n", i, dd);
+		printk("\n\tbuf: 0x%p\n"
+		       "\tafter: 0x%p\n"
+		       "\tmd: 0x%04x\n"
+		       "\tnext: 0x%p\n",
+		       dd->buf,
+		       dd->after,
+		       dd->md,
+		       dd->next);
+		printk("flags:\n"
+		       "\twait:\t%d\n"
+		       "\teol:\t%d\n"
+		       "\touteop:\t%d\n"
+		       "\tineop:\t%d\n"
+		       "\tintr:\t%d\n",
+		       dd->wait,
+		       dd->eol,
+		       dd->out_eop,
+		       dd->in_eop,
+		       dd->intr);
+		if (dd->eol)
+			dd = NULL;
+		else
+			dd = phys_to_virt((unsigned long int)dd->next);
+		++i;
+	}
+
+	printk("##############inlist\n");
+	dd = phys_to_virt((unsigned long int)dma_op->inlist);
+	i = 0;
+	while (dd != NULL) {
+		printk("#%d phys_to_virt(desc) 0x%p\n", i, dd);
+		printk("\n\tbuf: 0x%p\n"
+		       "\tafter: 0x%p\n"
+		       "\tmd: 0x%04x\n"
+		       "\tnext: 0x%p\n",
+		       dd->buf,
+		       dd->after,
+		       dd->md,
+		       dd->next);
+		printk("flags:\n"
+		       "\twait:\t%d\n"
+		       "\teol:\t%d\n"
+		       "\touteop:\t%d\n"
+		       "\tineop:\t%d\n"
+		       "\tintr:\t%d\n",
+		       dd->wait,
+		       dd->eol,
+		       dd->out_eop,
+		       dd->in_eop,
+		       dd->intr);
+		if (dd->eol)
+			dd = NULL;
+		else
+			dd = phys_to_virt((unsigned long int)dd->next);
+		++i;
+	}
+}
+
+
+static void print_lock_status(void)
+{
+	printk("**********************print_lock_status\n");
+	printk("cryptocop_completed_jobs_lock %d\n", spin_is_locked(&cryptocop_completed_jobs_lock));
+	printk("cryptocop_job_queue_lock %d\n", spin_is_locked(&cryptocop_job_queue_lock));
+	printk("descr_pool_lock %d\n", spin_is_locked(&descr_pool_lock));
+	printk("cryptocop_sessions_lock %d\n", spin_is_locked(cryptocop_sessions_lock));
+	printk("running_job_lock %d\n", spin_is_locked(running_job_lock));
+	printk("cryptocop_process_lock %d\n", spin_is_locked(cryptocop_process_lock));
+}
+#endif /* LDEBUG */
+
+
+static const char cryptocop_name[] = "ETRAX FS stream co-processor";
+
+static int init_stream_coprocessor(void)
+{
+	int err;
+	int i;
+	static int initialized = 0;
+
+	if (initialized)
+		return 0;
+
+	initialized = 1;
+
+	printk("ETRAX FS stream co-processor driver v0.01, (c) 2003 Axis Communications AB\n");
+
+	err = register_chrdev(CRYPTOCOP_MAJOR, cryptocop_name, &cryptocop_fops);
+	if (err < 0) {
+		printk(KERN_ERR "stream co-processor: could not get major number.\n");
+		return err;
+	}
+
+	err = init_cryptocop();
+	if (err) {
+		(void)unregister_chrdev(CRYPTOCOP_MAJOR, cryptocop_name);
+		return err;
+	}
+	err = cryptocop_job_queue_init();
+	if (err) {
+		release_cryptocop();
+		(void)unregister_chrdev(CRYPTOCOP_MAJOR, cryptocop_name);
+		return err;
+	}
+	/* Init the descriptor pool. */
+	for (i = 0; i < CRYPTOCOP_DESCRIPTOR_POOL_SIZE - 1; i++) {
+		descr_pool[i].from_pool = 1;
+		descr_pool[i].next = &descr_pool[i + 1];
+	}
+	descr_pool[i].from_pool = 1;
+	descr_pool[i].next = NULL;
+	descr_pool_free_list = &descr_pool[0];
+	descr_pool_no_free = CRYPTOCOP_DESCRIPTOR_POOL_SIZE;
+
+	spin_lock_init(&cryptocop_completed_jobs_lock);
+	spin_lock_init(&cryptocop_job_queue_lock);
+	spin_lock_init(&descr_pool_lock);
+	spin_lock_init(&cryptocop_sessions_lock);
+	spin_lock_init(&running_job_lock);
+	spin_lock_init(&cryptocop_process_lock);
+
+	cryptocop_sessions = NULL;
+	next_sid = 1;
+
+	cryptocop_running_job = NULL;
+
+	printk("stream co-processor: init done.\n");
+	return 0;
+}
+
+static void __exit exit_stream_coprocessor(void)
+{
+	release_cryptocop();
+	cryptocop_job_queue_close();
+}
+
+module_init(init_stream_coprocessor);
+module_exit(exit_stream_coprocessor);
+
diff --git a/arch/cris/arch-v32/drivers/gpio.c b/arch/cris/arch-v32/drivers/gpio.c
new file mode 100644
index 00000000000..a551237dcb5
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/gpio.c
@@ -0,0 +1,766 @@
+/* $Id: gpio.c,v 1.16 2005/06/19 17:06:49 starvik Exp $
+ *
+ * ETRAX CRISv32 general port I/O device
+ *
+ * Copyright (c) 1999, 2000, 2001, 2002, 2003 Axis Communications AB
+ *
+ * Authors:    Bjorn Wesen      (initial version)
+ *             Ola Knutsson     (LED handling)
+ *             Johan Adolfsson  (read/set directions, write, port G,
+ *                               port to ETRAX FS.
+ *
+ * $Log: gpio.c,v $
+ * Revision 1.16  2005/06/19 17:06:49  starvik
+ * Merge of Linux 2.6.12.
+ *
+ * Revision 1.15  2005/05/25 08:22:20  starvik
+ * Changed GPIO port order to fit packages/devices/axis-2.4.
+ *
+ * Revision 1.14  2005/04/24 18:35:08  starvik
+ * Updated with final register headers.
+ *
+ * Revision 1.13  2005/03/15 15:43:00  starvik
+ * dev_id needs to be supplied for shared IRQs.
+ *
+ * Revision 1.12  2005/03/10 17:12:00  starvik
+ * Protect alarm list with spinlock.
+ *
+ * Revision 1.11  2005/01/05 06:08:59  starvik
+ * No need to do local_irq_disable after local_irq_save.
+ *
+ * Revision 1.10  2004/11/19 08:38:31  starvik
+ * Removed old crap.
+ *
+ * Revision 1.9  2004/05/14 07:58:02  starvik
+ * Merge of changes from 2.4
+ *
+ * Revision 1.8  2003/09/11 07:29:50  starvik
+ * Merge of Linux 2.6.0-test5
+ *
+ * Revision 1.7  2003/07/10 13:25:46  starvik
+ * Compiles for 2.5.74
+ * Lindented ethernet.c
+ *
+ * Revision 1.6  2003/07/04 08:27:46  starvik
+ * Merge of Linux 2.5.74
+ *
+ * Revision 1.5  2003/06/10 08:26:37  johana
+ * Etrax -> ETRAX CRISv32
+ *
+ * Revision 1.4  2003/06/05 14:22:48  johana
+ * Initialise some_alarms.
+ *
+ * Revision 1.3  2003/06/05 10:15:46  johana
+ * New INTR_VECT macros.
+ * Enable interrupts in global config.
+ *
+ * Revision 1.2  2003/06/03 15:52:50  johana
+ * Initial CRIS v32 version.
+ *
+ * Revision 1.1  2003/06/03 08:53:15  johana
+ * Copy of os/lx25/arch/cris/arch-v10/drivers/gpio.c version 1.7.
+ *
+ */
+
+#include <linux/config.h>
+
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/ioport.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/string.h>
+#include <linux/poll.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+
+#include <asm/etraxgpio.h>
+#include <asm/arch/hwregs/reg_map.h>
+#include <asm/arch/hwregs/reg_rdwr.h>
+#include <asm/arch/hwregs/gio_defs.h>
+#include <asm/arch/hwregs/intr_vect_defs.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+
+/* The following gio ports on ETRAX FS is available:
+ * pa  8 bits, supports interrupts off, hi, low, set, posedge, negedge anyedge
+ * pb 18 bits
+ * pc 18 bits
+ * pd 18 bits
+ * pe 18 bits
+ * each port has a rw_px_dout, r_px_din and rw_px_oe register.
+ */
+
+#define GPIO_MAJOR 120  /* experimental MAJOR number */
+
+#define D(x)
+
+#if 0
+static int dp_cnt;
+#define DP(x) do { dp_cnt++; if (dp_cnt % 1000 == 0) x; }while(0)
+#else
+#define DP(x)
+#endif
+
+static char gpio_name[] = "etrax gpio";
+
+#if 0
+static wait_queue_head_t *gpio_wq;
+#endif
+
+static int gpio_ioctl(struct inode *inode, struct file *file,
+		      unsigned int cmd, unsigned long arg);
+static ssize_t gpio_write(struct file * file, const char * buf, size_t count,
+                          loff_t *off);
+static int gpio_open(struct inode *inode, struct file *filp);
+static int gpio_release(struct inode *inode, struct file *filp);
+static unsigned int gpio_poll(struct file *filp, struct poll_table_struct *wait);
+
+/* private data per open() of this driver */
+
+struct gpio_private {
+	struct gpio_private *next;
+	/* The IO_CFG_WRITE_MODE_VALUE only support 8 bits: */
+	unsigned char clk_mask;
+	unsigned char data_mask;
+	unsigned char write_msb;
+	unsigned char pad1;
+	/* These fields are generic */
+	unsigned long highalarm, lowalarm;
+	wait_queue_head_t alarm_wq;
+	int minor;
+};
+
+/* linked list of alarms to check for */
+
+static struct gpio_private *alarmlist = 0;
+
+static int gpio_some_alarms = 0; /* Set if someone uses alarm */
+static unsigned long gpio_pa_high_alarms = 0;
+static unsigned long gpio_pa_low_alarms = 0;
+
+static DEFINE_SPINLOCK(alarm_lock);
+
+#define NUM_PORTS (GPIO_MINOR_LAST+1)
+#define GIO_REG_RD_ADDR(reg) (volatile unsigned long*) (regi_gio + REG_RD_ADDR_gio_##reg )
+#define GIO_REG_WR_ADDR(reg) (volatile unsigned long*) (regi_gio + REG_RD_ADDR_gio_##reg )
+unsigned long led_dummy;
+
+static volatile unsigned long *data_out[NUM_PORTS] = {
+	GIO_REG_WR_ADDR(rw_pa_dout),
+	GIO_REG_WR_ADDR(rw_pb_dout),
+	&led_dummy,
+	GIO_REG_WR_ADDR(rw_pc_dout),
+	GIO_REG_WR_ADDR(rw_pd_dout),
+	GIO_REG_WR_ADDR(rw_pe_dout),
+};
+
+static volatile unsigned long *data_in[NUM_PORTS] = {
+	GIO_REG_RD_ADDR(r_pa_din),
+	GIO_REG_RD_ADDR(r_pb_din),
+	&led_dummy,
+	GIO_REG_RD_ADDR(r_pc_din),
+	GIO_REG_RD_ADDR(r_pd_din),
+	GIO_REG_RD_ADDR(r_pe_din),
+};
+
+static unsigned long changeable_dir[NUM_PORTS] = {
+	CONFIG_ETRAX_PA_CHANGEABLE_DIR,
+	CONFIG_ETRAX_PB_CHANGEABLE_DIR,
+	0,
+	CONFIG_ETRAX_PC_CHANGEABLE_DIR,
+	CONFIG_ETRAX_PD_CHANGEABLE_DIR,
+	CONFIG_ETRAX_PE_CHANGEABLE_DIR,
+};
+
+static unsigned long changeable_bits[NUM_PORTS] = {
+	CONFIG_ETRAX_PA_CHANGEABLE_BITS,
+	CONFIG_ETRAX_PB_CHANGEABLE_BITS,
+	0,
+	CONFIG_ETRAX_PC_CHANGEABLE_BITS,
+	CONFIG_ETRAX_PD_CHANGEABLE_BITS,
+	CONFIG_ETRAX_PE_CHANGEABLE_BITS,
+};
+
+static volatile unsigned long *dir_oe[NUM_PORTS] = {
+	GIO_REG_WR_ADDR(rw_pa_oe),
+	GIO_REG_WR_ADDR(rw_pb_oe),
+	&led_dummy,
+	GIO_REG_WR_ADDR(rw_pc_oe),
+	GIO_REG_WR_ADDR(rw_pd_oe),
+	GIO_REG_WR_ADDR(rw_pe_oe),
+};
+
+
+
+static unsigned int
+gpio_poll(struct file *file,
+	  poll_table *wait)
+{
+	unsigned int mask = 0;
+	struct gpio_private *priv = (struct gpio_private *)file->private_data;
+	unsigned long data;
+	poll_wait(file, &priv->alarm_wq, wait);
+	if (priv->minor == GPIO_MINOR_A) {
+		reg_gio_rw_intr_cfg intr_cfg;
+		unsigned long tmp;
+		unsigned long flags;
+
+		local_irq_save(flags);
+		data = REG_TYPE_CONV(unsigned long, reg_gio_r_pa_din, REG_RD(gio, regi_gio, r_pa_din));
+		/* PA has support for interrupt
+		 * lets activate high for those low and with highalarm set
+		 */
+		intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
+
+		tmp = ~data & priv->highalarm & 0xFF;
+                if (tmp & (1 << 0)) {
+			intr_cfg.pa0 = regk_gio_hi;
+		}
+                if (tmp & (1 << 1)) {
+			intr_cfg.pa1 = regk_gio_hi;
+		}
+                if (tmp & (1 << 2)) {
+			intr_cfg.pa2 = regk_gio_hi;
+		}
+                if (tmp & (1 << 3)) {
+			intr_cfg.pa3 = regk_gio_hi;
+		}
+                if (tmp & (1 << 4)) {
+			intr_cfg.pa4 = regk_gio_hi;
+		}
+                if (tmp & (1 << 5)) {
+			intr_cfg.pa5 = regk_gio_hi;
+		}
+                if (tmp & (1 << 6)) {
+			intr_cfg.pa6 = regk_gio_hi;
+		}
+                if (tmp & (1 << 7)) {
+			intr_cfg.pa7 = regk_gio_hi;
+		}
+		/*
+		 * lets activate low for those high and with lowalarm set
+		 */
+		tmp = data & priv->lowalarm & 0xFF;
+                if (tmp & (1 << 0)) {
+			intr_cfg.pa0 = regk_gio_lo;
+		}
+                if (tmp & (1 << 1)) {
+			intr_cfg.pa1 = regk_gio_lo;
+		}
+                if (tmp & (1 << 2)) {
+			intr_cfg.pa2 = regk_gio_lo;
+		}
+                if (tmp & (1 << 3)) {
+			intr_cfg.pa3 = regk_gio_lo;
+		}
+                if (tmp & (1 << 4)) {
+			intr_cfg.pa4 = regk_gio_lo;
+		}
+                if (tmp & (1 << 5)) {
+			intr_cfg.pa5 = regk_gio_lo;
+		}
+                if (tmp & (1 << 6)) {
+			intr_cfg.pa6 = regk_gio_lo;
+		}
+                if (tmp & (1 << 7)) {
+			intr_cfg.pa7 = regk_gio_lo;
+		}
+
+		REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
+		local_irq_restore(flags);
+	} else if (priv->minor <= GPIO_MINOR_E)
+		data = *data_in[priv->minor];
+	else
+		return 0;
+
+	if ((data & priv->highalarm) ||
+	    (~data & priv->lowalarm)) {
+		mask = POLLIN|POLLRDNORM;
+	}
+
+	DP(printk("gpio_poll ready: mask 0x%08X\n", mask));
+	return mask;
+}
+
+int etrax_gpio_wake_up_check(void)
+{
+	struct gpio_private *priv = alarmlist;
+	unsigned long data = 0;
+        int ret = 0;
+	while (priv) {
+		data = *data_in[priv->minor];
+		if ((data & priv->highalarm) ||
+		    (~data & priv->lowalarm)) {
+			DP(printk("etrax_gpio_wake_up_check %i\n",priv->minor));
+			wake_up_interruptible(&priv->alarm_wq);
+                        ret = 1;
+		}
+		priv = priv->next;
+	}
+        return ret;
+}
+
+static irqreturn_t
+gpio_poll_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	if (gpio_some_alarms) {
+		return IRQ_RETVAL(etrax_gpio_wake_up_check());
+	}
+        return IRQ_NONE;
+}
+
+static irqreturn_t
+gpio_pa_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	reg_gio_rw_intr_mask intr_mask;
+	reg_gio_r_masked_intr masked_intr;
+	reg_gio_rw_ack_intr ack_intr;
+	unsigned long tmp;
+	unsigned long tmp2;
+
+	/* Find what PA interrupts are active */
+	masked_intr = REG_RD(gio, regi_gio, r_masked_intr);
+	tmp = REG_TYPE_CONV(unsigned long, reg_gio_r_masked_intr, masked_intr);
+
+	/* Find those that we have enabled */
+	spin_lock(&alarm_lock);
+	tmp &= (gpio_pa_high_alarms | gpio_pa_low_alarms);
+	spin_unlock(&alarm_lock);
+
+	/* Ack them */
+	ack_intr = REG_TYPE_CONV(reg_gio_rw_ack_intr, unsigned long, tmp);
+	REG_WR(gio, regi_gio, rw_ack_intr, ack_intr);
+
+	/* Disable those interrupts.. */
+	intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
+	tmp2 = REG_TYPE_CONV(unsigned long, reg_gio_rw_intr_mask, intr_mask);
+	tmp2 &= ~tmp;
+	intr_mask = REG_TYPE_CONV(reg_gio_rw_intr_mask, unsigned long, tmp2);
+	REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
+
+	if (gpio_some_alarms) {
+		return IRQ_RETVAL(etrax_gpio_wake_up_check());
+	}
+        return IRQ_NONE;
+}
+
+
+static ssize_t gpio_write(struct file * file, const char * buf, size_t count,
+                          loff_t *off)
+{
+	struct gpio_private *priv = (struct gpio_private *)file->private_data;
+	unsigned char data, clk_mask, data_mask, write_msb;
+	unsigned long flags;
+	unsigned long shadow;
+	volatile unsigned long *port;
+	ssize_t retval = count;
+	/* Only bits 0-7 may be used for write operations but allow all
+	   devices except leds... */
+	if (priv->minor == GPIO_MINOR_LEDS) {
+		return -EFAULT;
+	}
+
+	if (!access_ok(VERIFY_READ, buf, count)) {
+		return -EFAULT;
+	}
+	clk_mask = priv->clk_mask;
+	data_mask = priv->data_mask;
+	/* It must have been configured using the IO_CFG_WRITE_MODE */
+	/* Perhaps a better error code? */
+	if (clk_mask == 0 || data_mask == 0) {
+		return -EPERM;
+	}
+	write_msb = priv->write_msb;
+	D(printk("gpio_write: %lu to data 0x%02X clk 0x%02X msb: %i\n",count, data_mask, clk_mask, write_msb));
+	port = data_out[priv->minor];
+
+	while (count--) {
+		int i;
+		data = *buf++;
+		if (priv->write_msb) {
+			for (i = 7; i >= 0;i--) {
+				local_irq_save(flags);
+				shadow = *port;
+				*port = shadow &= ~clk_mask;
+				if (data & 1<<i)
+					*port = shadow |= data_mask;
+				else
+					*port = shadow &= ~data_mask;
+			/* For FPGA: min 5.0ns (DCC) before CCLK high */
+				*port = shadow |= clk_mask;
+				local_irq_restore(flags);
+			}
+		} else {
+			for (i = 0; i <= 7;i++) {
+				local_irq_save(flags);
+				shadow = *port;
+				*port = shadow &= ~clk_mask;
+				if (data & 1<<i)
+					*port = shadow |= data_mask;
+				else
+					*port = shadow &= ~data_mask;
+			/* For FPGA: min 5.0ns (DCC) before CCLK high */
+				*port = shadow |= clk_mask;
+				local_irq_restore(flags);
+			}
+		}
+	}
+	return retval;
+}
+
+
+
+static int
+gpio_open(struct inode *inode, struct file *filp)
+{
+	struct gpio_private *priv;
+	int p = MINOR(inode->i_rdev);
+
+	if (p > GPIO_MINOR_LAST)
+		return -EINVAL;
+
+	priv = (struct gpio_private *)kmalloc(sizeof(struct gpio_private),
+					      GFP_KERNEL);
+
+	if (!priv)
+		return -ENOMEM;
+
+	priv->minor = p;
+
+	/* initialize the io/alarm struct and link it into our alarmlist */
+
+	priv->next = alarmlist;
+	alarmlist = priv;
+	priv->clk_mask = 0;
+	priv->data_mask = 0;
+	priv->highalarm = 0;
+	priv->lowalarm = 0;
+	init_waitqueue_head(&priv->alarm_wq);
+
+	filp->private_data = (void *)priv;
+
+	return 0;
+}
+
+static int
+gpio_release(struct inode *inode, struct file *filp)
+{
+	struct gpio_private *p = alarmlist;
+	struct gpio_private *todel = (struct gpio_private *)filp->private_data;
+	/* local copies while updating them: */
+	unsigned long a_high, a_low;
+	unsigned long some_alarms;
+
+	/* unlink from alarmlist and free the private structure */
+
+	if (p == todel) {
+		alarmlist = todel->next;
+	} else {
+		while (p->next != todel)
+			p = p->next;
+		p->next = todel->next;
+	}
+
+	kfree(todel);
+	/* Check if there are still any alarms set */
+	p = alarmlist;
+        some_alarms = 0;
+	a_high = 0;
+	a_low = 0;
+	while (p) {
+		if (p->minor == GPIO_MINOR_A) {
+			a_high |= p->highalarm;
+			a_low |= p->lowalarm;
+		}
+
+		if (p->highalarm | p->lowalarm) {
+			some_alarms = 1;
+		}
+		p = p->next;
+	}
+
+	spin_lock(&alarm_lock);
+	gpio_some_alarms = some_alarms;
+	gpio_pa_high_alarms = a_high;
+	gpio_pa_low_alarms = a_low;
+	spin_unlock(&alarm_lock);
+
+	return 0;
+}
+
+/* Main device API. ioctl's to read/set/clear bits, as well as to
+ * set alarms to wait for using a subsequent select().
+ */
+
+unsigned long inline setget_input(struct gpio_private *priv, unsigned long arg)
+{
+	/* Set direction 0=unchanged 1=input,
+	 * return mask with 1=input
+	 */
+	unsigned long flags;
+	unsigned long dir_shadow;
+
+	local_irq_save(flags);
+	dir_shadow = *dir_oe[priv->minor];
+	dir_shadow &= ~(arg & changeable_dir[priv->minor]);
+	*dir_oe[priv->minor] = dir_shadow;
+	local_irq_restore(flags);
+
+	if (priv->minor == GPIO_MINOR_A)
+		dir_shadow ^= 0xFF;    /* Only 8 bits */
+	else
+		dir_shadow ^= 0x3FFFF; /* Only 18 bits */
+	return dir_shadow;
+
+} /* setget_input */
+
+unsigned long inline setget_output(struct gpio_private *priv, unsigned long arg)
+{
+	unsigned long flags;
+	unsigned long dir_shadow;
+
+	local_irq_save(flags);
+	dir_shadow = *dir_oe[priv->minor];
+	dir_shadow |=  (arg & changeable_dir[priv->minor]);
+	*dir_oe[priv->minor] = dir_shadow;
+	local_irq_restore(flags);
+	return dir_shadow;
+} /* setget_output */
+
+static int
+gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
+
+static int
+gpio_ioctl(struct inode *inode, struct file *file,
+	   unsigned int cmd, unsigned long arg)
+{
+	unsigned long flags;
+	unsigned long val;
+	unsigned long shadow;
+	struct gpio_private *priv = (struct gpio_private *)file->private_data;
+	if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE) {
+		return -EINVAL;
+	}
+
+	switch (_IOC_NR(cmd)) {
+	case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
+		// read the port
+		return *data_in[priv->minor];
+		break;
+	case IO_SETBITS:
+		local_irq_save(flags);
+                if (arg & 0x04)
+                  printk("GPIO SET 2\n");
+		// set changeable bits with a 1 in arg
+		shadow = *data_out[priv->minor];
+		shadow |=  (arg & changeable_bits[priv->minor]);
+		*data_out[priv->minor] = shadow;
+		local_irq_restore(flags);
+		break;
+	case IO_CLRBITS:
+		local_irq_save(flags);
+                if (arg & 0x04)
+                  printk("GPIO CLR 2\n");
+		// clear changeable bits with a 1 in arg
+		shadow = *data_out[priv->minor];
+		shadow &=  ~(arg & changeable_bits[priv->minor]);
+		*data_out[priv->minor] = shadow;
+		local_irq_restore(flags);
+		break;
+	case IO_HIGHALARM:
+		// set alarm when bits with 1 in arg go high
+		priv->highalarm |= arg;
+		spin_lock(&alarm_lock);
+		gpio_some_alarms = 1;
+		if (priv->minor == GPIO_MINOR_A) {
+			gpio_pa_high_alarms |= arg;
+		}
+		spin_unlock(&alarm_lock);
+		break;
+	case IO_LOWALARM:
+		// set alarm when bits with 1 in arg go low
+		priv->lowalarm |= arg;
+		spin_lock(&alarm_lock);
+		gpio_some_alarms = 1;
+		if (priv->minor == GPIO_MINOR_A) {
+			gpio_pa_low_alarms |= arg;
+		}
+		spin_unlock(&alarm_lock);
+		break;
+	case IO_CLRALARM:
+		// clear alarm for bits with 1 in arg
+		priv->highalarm &= ~arg;
+		priv->lowalarm  &= ~arg;
+		spin_lock(&alarm_lock);
+		if (priv->minor == GPIO_MINOR_A) {
+			if (gpio_pa_high_alarms & arg ||
+			    gpio_pa_low_alarms & arg) {
+				/* Must update the gpio_pa_*alarms masks */
+			}
+		}
+		spin_unlock(&alarm_lock);
+		break;
+	case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
+		/* Read direction 0=input 1=output */
+		return *dir_oe[priv->minor];
+	case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
+		/* Set direction 0=unchanged 1=input,
+		 * return mask with 1=input
+		 */
+		return setget_input(priv, arg);
+		break;
+	case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
+		/* Set direction 0=unchanged 1=output,
+		 * return mask with 1=output
+		 */
+		return setget_output(priv, arg);
+
+	case IO_CFG_WRITE_MODE:
+	{
+		unsigned long dir_shadow;
+		dir_shadow = *dir_oe[priv->minor];
+
+		priv->clk_mask = arg & 0xFF;
+		priv->data_mask = (arg >> 8) & 0xFF;
+		priv->write_msb = (arg >> 16) & 0x01;
+		/* Check if we're allowed to change the bits and
+		 * the direction is correct
+		 */
+		if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
+		      (priv->data_mask & changeable_bits[priv->minor]) &&
+		      (priv->clk_mask & dir_shadow) &&
+		      (priv->data_mask & dir_shadow)))
+		{
+			priv->clk_mask = 0;
+			priv->data_mask = 0;
+			return -EPERM;
+		}
+		break;
+	}
+	case IO_READ_INBITS:
+		/* *arg is result of reading the input pins */
+		val = *data_in[priv->minor];
+		if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
+			return -EFAULT;
+		return 0;
+		break;
+	case IO_READ_OUTBITS:
+		 /* *arg is result of reading the output shadow */
+		val = *data_out[priv->minor];
+		if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
+			return -EFAULT;
+		break;
+	case IO_SETGET_INPUT:
+		/* bits set in *arg is set to input,
+		 * *arg updated with current input pins.
+		 */
+		if (copy_from_user(&val, (unsigned long*)arg, sizeof(val)))
+			return -EFAULT;
+		val = setget_input(priv, val);
+		if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
+			return -EFAULT;
+		break;
+	case IO_SETGET_OUTPUT:
+		/* bits set in *arg is set to output,
+		 * *arg updated with current output pins.
+		 */
+		if (copy_from_user(&val, (unsigned long*)arg, sizeof(val)))
+			return -EFAULT;
+		val = setget_output(priv, val);
+		if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
+			return -EFAULT;
+		break;
+	default:
+		if (priv->minor == GPIO_MINOR_LEDS)
+			return gpio_leds_ioctl(cmd, arg);
+		else
+			return -EINVAL;
+	} /* switch */
+
+	return 0;
+}
+
+static int
+gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
+{
+	unsigned char green;
+	unsigned char red;
+
+	switch (_IOC_NR(cmd)) {
+	case IO_LEDACTIVE_SET:
+		green = ((unsigned char) arg) & 1;
+		red   = (((unsigned char) arg) >> 1) & 1;
+		LED_ACTIVE_SET_G(green);
+		LED_ACTIVE_SET_R(red);
+		break;
+
+	default:
+		return -EINVAL;
+	} /* switch */
+
+	return 0;
+}
+
+struct file_operations gpio_fops = {
+	.owner       = THIS_MODULE,
+	.poll        = gpio_poll,
+	.ioctl       = gpio_ioctl,
+	.write       = gpio_write,
+	.open        = gpio_open,
+	.release     = gpio_release,
+};
+
+
+/* main driver initialization routine, called from mem.c */
+
+static __init int
+gpio_init(void)
+{
+	int res;
+	reg_intr_vect_rw_mask intr_mask;
+
+	/* do the formalities */
+
+	res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
+	if (res < 0) {
+		printk(KERN_ERR "gpio: couldn't get a major number.\n");
+		return res;
+	}
+
+	/* Clear all leds */
+	LED_NETWORK_SET(0);
+	LED_ACTIVE_SET(0);
+	LED_DISK_READ(0);
+	LED_DISK_WRITE(0);
+
+	printk("ETRAX FS GPIO driver v2.5, (c) 2003-2005 Axis Communications AB\n");
+	/* We call etrax_gpio_wake_up_check() from timer interrupt and
+	 * from cpu_idle() in kernel/process.c
+	 * The check in cpu_idle() reduces latency from ~15 ms to ~6 ms
+	 * in some tests.
+	 */
+	if (request_irq(TIMER_INTR_VECT, gpio_poll_timer_interrupt,
+			SA_SHIRQ | SA_INTERRUPT,"gpio poll", &alarmlist)) {
+		printk("err: timer0 irq for gpio\n");
+	}
+	if (request_irq(GEN_IO_INTR_VECT, gpio_pa_interrupt,
+			SA_SHIRQ | SA_INTERRUPT,"gpio PA", &alarmlist)) {
+		printk("err: PA irq for gpio\n");
+	}
+	/* enable the gio and timer irq in global config */
+	intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
+	intr_mask.timer = 1;
+	intr_mask.gen_io = 1;
+	REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
+
+	return res;
+}
+
+/* this makes sure that gpio_init is called during kernel boot */
+
+module_init(gpio_init);
diff --git a/arch/cris/arch-v32/drivers/i2c.c b/arch/cris/arch-v32/drivers/i2c.c
new file mode 100644
index 00000000000..440c20a9496
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/i2c.c
@@ -0,0 +1,611 @@
+/*!***************************************************************************
+*!
+*! FILE NAME  : i2c.c
+*!
+*! DESCRIPTION: implements an interface for IIC/I2C, both directly from other
+*!              kernel modules (i2c_writereg/readreg) and from userspace using
+*!              ioctl()'s
+*!
+*! Nov 30 1998  Torbjorn Eliasson  Initial version.
+*!              Bjorn Wesen        Elinux kernel version.
+*! Jan 14 2000  Johan Adolfsson    Fixed PB shadow register stuff -
+*!                                 don't use PB_I2C if DS1302 uses same bits,
+*!                                 use PB.
+*| June 23 2003 Pieter Grimmerink  Added 'i2c_sendnack'. i2c_readreg now
+*|                                 generates nack on last received byte,
+*|                                 instead of ack.
+*|                                 i2c_getack changed data level while clock
+*|                                 was high, causing DS75 to see  a stop condition
+*!
+*! ---------------------------------------------------------------------------
+*!
+*! (C) Copyright 1999-2002 Axis Communications AB, LUND, SWEDEN
+*!
+*!***************************************************************************/
+/* $Id: i2c.c,v 1.2 2005/05/09 15:29:49 starvik Exp $ */
+/****************** INCLUDE FILES SECTION ***********************************/
+
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/config.h>
+
+#include <asm/etraxi2c.h>
+
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/delay.h>
+
+#include "i2c.h"
+
+/****************** I2C DEFINITION SECTION *************************/
+
+#define D(x)
+
+#define I2C_MAJOR 123  /* LOCAL/EXPERIMENTAL */
+static const char i2c_name[] = "i2c";
+
+#define CLOCK_LOW_TIME            8
+#define CLOCK_HIGH_TIME           8
+#define START_CONDITION_HOLD_TIME 8
+#define STOP_CONDITION_HOLD_TIME  8
+#define ENABLE_OUTPUT 0x01
+#define ENABLE_INPUT 0x00
+#define I2C_CLOCK_HIGH 1
+#define I2C_CLOCK_LOW 0
+#define I2C_DATA_HIGH 1
+#define I2C_DATA_LOW 0
+
+#define i2c_enable()
+#define i2c_disable()
+
+/* enable or disable output-enable, to select output or input on the i2c bus */
+
+#define i2c_dir_out() crisv32_io_set_dir(&cris_i2c_data, crisv32_io_dir_out)
+#define i2c_dir_in() crisv32_io_set_dir(&cris_i2c_data, crisv32_io_dir_in)
+
+/* control the i2c clock and data signals */
+
+#define i2c_clk(x) crisv32_io_set(&cris_i2c_clk, x)
+#define i2c_data(x) crisv32_io_set(&cris_i2c_data, x)
+
+/* read a bit from the i2c interface */
+
+#define i2c_getbit() crisv32_io_rd(&cris_i2c_data)
+
+#define i2c_delay(usecs) udelay(usecs)
+
+/****************** VARIABLE SECTION ************************************/
+
+static struct crisv32_iopin cris_i2c_clk;
+static struct crisv32_iopin cris_i2c_data;
+
+/****************** FUNCTION DEFINITION SECTION *************************/
+
+
+/* generate i2c start condition */
+
+void
+i2c_start(void)
+{
+	/*
+	 * SCL=1 SDA=1
+	 */
+	i2c_dir_out();
+	i2c_delay(CLOCK_HIGH_TIME/6);
+	i2c_data(I2C_DATA_HIGH);
+	i2c_clk(I2C_CLOCK_HIGH);
+	i2c_delay(CLOCK_HIGH_TIME);
+	/*
+	 * SCL=1 SDA=0
+	 */
+	i2c_data(I2C_DATA_LOW);
+	i2c_delay(START_CONDITION_HOLD_TIME);
+	/*
+	 * SCL=0 SDA=0
+	 */
+	i2c_clk(I2C_CLOCK_LOW);
+	i2c_delay(CLOCK_LOW_TIME);
+}
+
+/* generate i2c stop condition */
+
+void
+i2c_stop(void)
+{
+	i2c_dir_out();
+
+	/*
+	 * SCL=0 SDA=0
+	 */
+	i2c_clk(I2C_CLOCK_LOW);
+	i2c_data(I2C_DATA_LOW);
+	i2c_delay(CLOCK_LOW_TIME*2);
+	/*
+	 * SCL=1 SDA=0
+	 */
+	i2c_clk(I2C_CLOCK_HIGH);
+	i2c_delay(CLOCK_HIGH_TIME*2);
+	/*
+	 * SCL=1 SDA=1
+	 */
+	i2c_data(I2C_DATA_HIGH);
+	i2c_delay(STOP_CONDITION_HOLD_TIME);
+
+	i2c_dir_in();
+}
+
+/* write a byte to the i2c interface */
+
+void
+i2c_outbyte(unsigned char x)
+{
+	int i;
+
+	i2c_dir_out();
+
+	for (i = 0; i < 8; i++) {
+		if (x & 0x80) {
+			i2c_data(I2C_DATA_HIGH);
+		} else {
+			i2c_data(I2C_DATA_LOW);
+		}
+
+		i2c_delay(CLOCK_LOW_TIME/2);
+		i2c_clk(I2C_CLOCK_HIGH);
+		i2c_delay(CLOCK_HIGH_TIME);
+		i2c_clk(I2C_CLOCK_LOW);
+		i2c_delay(CLOCK_LOW_TIME/2);
+		x <<= 1;
+	}
+	i2c_data(I2C_DATA_LOW);
+	i2c_delay(CLOCK_LOW_TIME/2);
+
+	/*
+	 * enable input
+	 */
+	i2c_dir_in();
+}
+
+/* read a byte from the i2c interface */
+
+unsigned char
+i2c_inbyte(void)
+{
+	unsigned char aBitByte = 0;
+	int i;
+
+	/* Switch off I2C to get bit */
+	i2c_disable();
+	i2c_dir_in();
+	i2c_delay(CLOCK_HIGH_TIME/2);
+
+	/* Get bit */
+	aBitByte |= i2c_getbit();
+
+	/* Enable I2C */
+	i2c_enable();
+	i2c_delay(CLOCK_LOW_TIME/2);
+
+	for (i = 1; i < 8; i++) {
+		aBitByte <<= 1;
+		/* Clock pulse */
+		i2c_clk(I2C_CLOCK_HIGH);
+		i2c_delay(CLOCK_HIGH_TIME);
+		i2c_clk(I2C_CLOCK_LOW);
+		i2c_delay(CLOCK_LOW_TIME);
+
+		/* Switch off I2C to get bit */
+		i2c_disable();
+		i2c_dir_in();
+		i2c_delay(CLOCK_HIGH_TIME/2);
+
+		/* Get bit */
+		aBitByte |= i2c_getbit();
+
+		/* Enable I2C */
+		i2c_enable();
+		i2c_delay(CLOCK_LOW_TIME/2);
+	}
+	i2c_clk(I2C_CLOCK_HIGH);
+	i2c_delay(CLOCK_HIGH_TIME);
+
+	/*
+	 * we leave the clock low, getbyte is usually followed
+	 * by sendack/nack, they assume the clock to be low
+	 */
+	i2c_clk(I2C_CLOCK_LOW);
+	return aBitByte;
+}
+
+/*#---------------------------------------------------------------------------
+*#
+*# FUNCTION NAME: i2c_getack
+*#
+*# DESCRIPTION  : checks if ack was received from ic2
+*#
+*#--------------------------------------------------------------------------*/
+
+int
+i2c_getack(void)
+{
+	int ack = 1;
+	/*
+	 * enable output
+	 */
+	i2c_dir_out();
+	/*
+	 * Release data bus by setting
+	 * data high
+	 */
+	i2c_data(I2C_DATA_HIGH);
+	/*
+	 * enable input
+	 */
+	i2c_dir_in();
+	i2c_delay(CLOCK_HIGH_TIME/4);
+	/*
+	 * generate ACK clock pulse
+	 */
+	i2c_clk(I2C_CLOCK_HIGH);
+	/*
+	 * Use PORT PB instead of I2C
+	 * for input. (I2C not working)
+	 */
+	i2c_clk(1);
+	i2c_data(1);
+	/*
+	 * switch off I2C
+	 */
+	i2c_data(1);
+	i2c_disable();
+	i2c_dir_in();
+	/*
+	 * now wait for ack
+	 */
+	i2c_delay(CLOCK_HIGH_TIME/2);
+	/*
+	 * check for ack
+	 */
+	if(i2c_getbit())
+		ack = 0;
+	i2c_delay(CLOCK_HIGH_TIME/2);
+	if(!ack){
+		if(!i2c_getbit()) /* receiver pulld SDA low */
+			ack = 1;
+		i2c_delay(CLOCK_HIGH_TIME/2);
+	}
+
+   /*
+    * our clock is high now, make sure data is low
+    * before we enable our output. If we keep data high
+    * and enable output, we would generate a stop condition.
+    */
+   i2c_data(I2C_DATA_LOW);
+
+	/*
+	 * end clock pulse
+	 */
+	i2c_enable();
+	i2c_dir_out();
+	i2c_clk(I2C_CLOCK_LOW);
+	i2c_delay(CLOCK_HIGH_TIME/4);
+	/*
+	 * enable output
+	 */
+	i2c_dir_out();
+	/*
+	 * remove ACK clock pulse
+	 */
+	i2c_data(I2C_DATA_HIGH);
+	i2c_delay(CLOCK_LOW_TIME/2);
+	return ack;
+}
+
+/*#---------------------------------------------------------------------------
+*#
+*# FUNCTION NAME: I2C::sendAck
+*#
+*# DESCRIPTION  : Send ACK on received data
+*#
+*#--------------------------------------------------------------------------*/
+void
+i2c_sendack(void)
+{
+	/*
+	 * enable output
+	 */
+	i2c_delay(CLOCK_LOW_TIME);
+	i2c_dir_out();
+	/*
+	 * set ack pulse high
+	 */
+	i2c_data(I2C_DATA_LOW);
+	/*
+	 * generate clock pulse
+	 */
+	i2c_delay(CLOCK_HIGH_TIME/6);
+	i2c_clk(I2C_CLOCK_HIGH);
+	i2c_delay(CLOCK_HIGH_TIME);
+	i2c_clk(I2C_CLOCK_LOW);
+	i2c_delay(CLOCK_LOW_TIME/6);
+	/*
+	 * reset data out
+	 */
+	i2c_data(I2C_DATA_HIGH);
+	i2c_delay(CLOCK_LOW_TIME);
+
+	i2c_dir_in();
+}
+
+/*#---------------------------------------------------------------------------
+*#
+*# FUNCTION NAME: i2c_sendnack
+*#
+*# DESCRIPTION  : Sends NACK on received data
+*#
+*#--------------------------------------------------------------------------*/
+void
+i2c_sendnack(void)
+{
+	/*
+	 * enable output
+	 */
+	i2c_delay(CLOCK_LOW_TIME);
+	i2c_dir_out();
+	/*
+	 * set data high
+	 */
+	i2c_data(I2C_DATA_HIGH);
+	/*
+	 * generate clock pulse
+	 */
+	i2c_delay(CLOCK_HIGH_TIME/6);
+	i2c_clk(I2C_CLOCK_HIGH);
+	i2c_delay(CLOCK_HIGH_TIME);
+	i2c_clk(I2C_CLOCK_LOW);
+	i2c_delay(CLOCK_LOW_TIME);
+
+	i2c_dir_in();
+}
+
+/*#---------------------------------------------------------------------------
+*#
+*# FUNCTION NAME: i2c_writereg
+*#
+*# DESCRIPTION  : Writes a value to an I2C device
+*#
+*#--------------------------------------------------------------------------*/
+int
+i2c_writereg(unsigned char theSlave, unsigned char theReg,
+	     unsigned char theValue)
+{
+	int error, cntr = 3;
+	unsigned long flags;
+
+	do {
+		error = 0;
+		/*
+		 * we don't like to be interrupted
+		 */
+                local_irq_save(flags);
+
+		i2c_start();
+		/*
+		 * send slave address
+		 */
+		i2c_outbyte((theSlave & 0xfe));
+		/*
+		 * wait for ack
+		 */
+		if(!i2c_getack())
+			error = 1;
+		/*
+		 * now select register
+		 */
+		i2c_dir_out();
+		i2c_outbyte(theReg);
+		/*
+		 * now it's time to wait for ack
+		 */
+		if(!i2c_getack())
+			error |= 2;
+		/*
+		 * send register register data
+		 */
+		i2c_outbyte(theValue);
+		/*
+		 * now it's time to wait for ack
+		 */
+		if(!i2c_getack())
+			error |= 4;
+		/*
+		 * end byte stream
+		 */
+		i2c_stop();
+		/*
+		 * enable interrupt again
+		 */
+		local_irq_restore(flags);
+
+	} while(error && cntr--);
+
+	i2c_delay(CLOCK_LOW_TIME);
+
+	return -error;
+}
+
+/*#---------------------------------------------------------------------------
+*#
+*# FUNCTION NAME: i2c_readreg
+*#
+*# DESCRIPTION  : Reads a value from the decoder registers.
+*#
+*#--------------------------------------------------------------------------*/
+unsigned char
+i2c_readreg(unsigned char theSlave, unsigned char theReg)
+{
+	unsigned char b = 0;
+	int error, cntr = 3;
+	unsigned long flags;
+
+	do {
+		error = 0;
+		/*
+		 * we don't like to be interrupted
+		 */
+                local_irq_save(flags);
+		/*
+		 * generate start condition
+		 */
+		i2c_start();
+
+		/*
+		 * send slave address
+		 */
+		i2c_outbyte((theSlave & 0xfe));
+		/*
+		 * wait for ack
+		 */
+		if(!i2c_getack())
+			error = 1;
+		/*
+		 * now select register
+		 */
+		i2c_dir_out();
+		i2c_outbyte(theReg);
+		/*
+		 * now it's time to wait for ack
+		 */
+		if(!i2c_getack())
+			error = 1;
+		/*
+		 * repeat start condition
+		 */
+		i2c_delay(CLOCK_LOW_TIME);
+		i2c_start();
+		/*
+		 * send slave address
+		 */
+		i2c_outbyte(theSlave | 0x01);
+		/*
+		 * wait for ack
+		 */
+		if(!i2c_getack())
+			error = 1;
+		/*
+		 * fetch register
+		 */
+		b = i2c_inbyte();
+		/*
+		 * last received byte needs to be nacked
+		 * instead of acked
+		 */
+		i2c_sendnack();
+		/*
+		 * end sequence
+		 */
+		i2c_stop();
+		/*
+		 * enable interrupt again
+		 */
+		local_irq_restore(flags);
+
+	} while(error && cntr--);
+
+	return b;
+}
+
+static int
+i2c_open(struct inode *inode, struct file *filp)
+{
+	return 0;
+}
+
+static int
+i2c_release(struct inode *inode, struct file *filp)
+{
+	return 0;
+}
+
+/* Main device API. ioctl's to write or read to/from i2c registers.
+ */
+
+static int
+i2c_ioctl(struct inode *inode, struct file *file,
+	  unsigned int cmd, unsigned long arg)
+{
+	if(_IOC_TYPE(cmd) != ETRAXI2C_IOCTYPE) {
+		return -EINVAL;
+	}
+
+	switch (_IOC_NR(cmd)) {
+		case I2C_WRITEREG:
+			/* write to an i2c slave */
+			D(printk("i2cw %d %d %d\n",
+				 I2C_ARGSLAVE(arg),
+				 I2C_ARGREG(arg),
+				 I2C_ARGVALUE(arg)));
+
+			return i2c_writereg(I2C_ARGSLAVE(arg),
+					    I2C_ARGREG(arg),
+					    I2C_ARGVALUE(arg));
+		case I2C_READREG:
+		{
+			unsigned char val;
+			/* read from an i2c slave */
+			D(printk("i2cr %d %d ",
+				I2C_ARGSLAVE(arg),
+				I2C_ARGREG(arg)));
+			val = i2c_readreg(I2C_ARGSLAVE(arg), I2C_ARGREG(arg));
+			D(printk("= %d\n", val));
+			return val;
+		}
+		default:
+			return -EINVAL;
+
+	}
+
+	return 0;
+}
+
+static struct file_operations i2c_fops = {
+	owner:    THIS_MODULE,
+	ioctl:    i2c_ioctl,
+	open:     i2c_open,
+	release:  i2c_release,
+};
+
+int __init
+i2c_init(void)
+{
+	int res;
+
+	/* Setup and enable the Port B I2C interface */
+
+        crisv32_io_get_name(&cris_i2c_data, CONFIG_ETRAX_I2C_DATA_PORT);
+        crisv32_io_get_name(&cris_i2c_clk, CONFIG_ETRAX_I2C_CLK_PORT);
+
+	/* register char device */
+
+	res = register_chrdev(I2C_MAJOR, i2c_name, &i2c_fops);
+	if(res < 0) {
+		printk(KERN_ERR "i2c: couldn't get a major number.\n");
+		return res;
+	}
+
+	printk(KERN_INFO "I2C driver v2.2, (c) 1999-2001 Axis Communications AB\n");
+
+	return 0;
+}
+
+/* this makes sure that i2c_init is called during boot */
+
+module_init(i2c_init);
+
+/****************** END OF FILE i2c.c ********************************/
diff --git a/arch/cris/arch-v32/drivers/i2c.h b/arch/cris/arch-v32/drivers/i2c.h
new file mode 100644
index 00000000000..bfe1a13f9f3
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/i2c.h
@@ -0,0 +1,15 @@
+
+#include <linux/init.h>
+
+/* High level I2C actions */
+int __init i2c_init(void);
+int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue);
+unsigned char i2c_readreg(unsigned char theSlave, unsigned char theReg);
+
+/* Low level I2C */
+void i2c_start(void);
+void i2c_stop(void);
+void i2c_outbyte(unsigned char x);
+unsigned char i2c_inbyte(void);
+int i2c_getack(void);
+void i2c_sendack(void);
diff --git a/arch/cris/arch-v32/drivers/iop_fw_load.c b/arch/cris/arch-v32/drivers/iop_fw_load.c
new file mode 100644
index 00000000000..11f9895ded5
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/iop_fw_load.c
@@ -0,0 +1,219 @@
+/* $Id: iop_fw_load.c,v 1.4 2005/04/07 09:27:46 larsv Exp $
+ *
+ * Firmware loader for ETRAX FS IO-Processor
+ *
+ * Copyright (C) 2004  Axis Communications AB
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/firmware.h>
+
+#include <asm/arch/hwregs/reg_map.h>
+#include <asm/arch/hwregs/iop/iop_reg_space.h>
+#include <asm/arch/hwregs/iop/iop_mpu_macros.h>
+#include <asm/arch/hwregs/iop/iop_mpu_defs.h>
+#include <asm/arch/hwregs/iop/iop_spu_defs.h>
+#include <asm/arch/hwregs/iop/iop_sw_cpu_defs.h>
+
+#define IOP_TIMEOUT 100
+
+static struct device iop_spu_device[2] = {
+	{ .bus_id =     "iop-spu0", },
+	{ .bus_id =     "iop-spu1", },
+};
+
+static struct device iop_mpu_device = {
+	.bus_id =       "iop-mpu",
+};
+
+static int wait_mpu_idle(void)
+{
+	reg_iop_mpu_r_stat mpu_stat;
+	unsigned int timeout = IOP_TIMEOUT;
+
+	do {
+		mpu_stat = REG_RD(iop_mpu, regi_iop_mpu, r_stat);
+	} while (mpu_stat.instr_reg_busy == regk_iop_mpu_yes && --timeout > 0);
+	if (timeout == 0) {
+		printk(KERN_ERR "Timeout waiting for MPU to be idle\n");
+		return -EBUSY;
+	}
+	return 0;
+}
+
+int iop_fw_load_spu(const unsigned char *fw_name, unsigned int spu_inst)
+{
+	reg_iop_sw_cpu_rw_mc_ctrl mc_ctrl = {
+		.wr_spu0_mem =    regk_iop_sw_cpu_no,
+		.wr_spu1_mem =    regk_iop_sw_cpu_no,
+		.size =           4,
+		.cmd =            regk_iop_sw_cpu_reg_copy,
+		.keep_owner =     regk_iop_sw_cpu_yes
+	};
+	reg_iop_spu_rw_ctrl spu_ctrl = {
+		.en  =            regk_iop_spu_no,
+		.fsm =            regk_iop_spu_no,
+	};
+	reg_iop_sw_cpu_r_mc_stat mc_stat;
+        const struct firmware *fw_entry;
+	u32 *data;
+	unsigned int timeout;
+	int retval, i;
+
+	if (spu_inst > 1)
+		return -ENODEV;
+
+	/* get firmware */
+	retval = request_firmware(&fw_entry,
+				  fw_name,
+				  &iop_spu_device[spu_inst]);
+	if (retval != 0)
+	{
+		printk(KERN_ERR
+		       "iop_load_spu: Failed to load firmware \"%s\"\n",
+		       fw_name);
+		return retval;
+	}
+	data = (u32 *) fw_entry->data;
+
+	/* acquire ownership of memory controller */
+	switch (spu_inst) {
+	case 0:
+		mc_ctrl.wr_spu0_mem = regk_iop_sw_cpu_yes;
+		REG_WR(iop_spu, regi_iop_spu0, rw_ctrl, spu_ctrl);
+		break;
+	case 1:
+		mc_ctrl.wr_spu1_mem = regk_iop_sw_cpu_yes;
+		REG_WR(iop_spu, regi_iop_spu1, rw_ctrl, spu_ctrl);
+		break;
+	}
+	timeout = IOP_TIMEOUT;
+	do {
+		REG_WR(iop_sw_cpu, regi_iop_sw_cpu, rw_mc_ctrl, mc_ctrl);
+		mc_stat = REG_RD(iop_sw_cpu, regi_iop_sw_cpu, r_mc_stat);
+	} while (mc_stat.owned_by_cpu == regk_iop_sw_cpu_no && --timeout > 0);
+	if (timeout == 0) {
+		printk(KERN_ERR "Timeout waiting to acquire MC\n");
+		retval = -EBUSY;
+		goto out;
+	}
+
+	/* write to SPU memory */
+	for (i = 0; i < (fw_entry->size/4); i++) {
+		switch (spu_inst) {
+		case 0:
+			REG_WR_INT(iop_spu, regi_iop_spu0, rw_seq_pc, (i*4));
+			break;
+		case 1:
+			REG_WR_INT(iop_spu, regi_iop_spu1, rw_seq_pc, (i*4));
+			break;
+		}
+		REG_WR_INT(iop_sw_cpu, regi_iop_sw_cpu, rw_mc_data, *data);
+		data++;
+	}
+
+	/* release ownership of memory controller */
+	(void) REG_RD(iop_sw_cpu, regi_iop_sw_cpu, rs_mc_data);
+
+ out:
+	release_firmware(fw_entry);
+	return retval;
+}
+
+int iop_fw_load_mpu(unsigned char *fw_name)
+{
+	const unsigned int start_addr = 0;
+	reg_iop_mpu_rw_ctrl mpu_ctrl;
+        const struct firmware *fw_entry;
+	u32 *data;
+	int retval, i;
+
+	/* get firmware */
+	retval = request_firmware(&fw_entry, fw_name, &iop_mpu_device);
+	if (retval != 0)
+	{
+		printk(KERN_ERR
+		       "iop_load_spu: Failed to load firmware \"%s\"\n",
+		       fw_name);
+		return retval;
+	}
+	data = (u32 *) fw_entry->data;
+
+	/* disable MPU */
+	mpu_ctrl.en = regk_iop_mpu_no;
+	REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl);
+	/* put start address in R0 */
+	REG_WR_VECT(iop_mpu, regi_iop_mpu, rw_r, 0, start_addr);
+	/* write to memory by executing 'SWX i, 4, R0' for each word */
+	if ((retval = wait_mpu_idle()) != 0)
+		goto out;
+	REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_SWX_IIR_INSTR(0, 4, 0));
+	for (i = 0; i < (fw_entry->size / 4); i++) {
+		REG_WR_INT(iop_mpu, regi_iop_mpu, rw_immediate, *data);
+		if ((retval = wait_mpu_idle()) != 0)
+			goto out;
+		data++;
+	}
+
+ out:
+	release_firmware(fw_entry);
+	return retval;
+}
+
+int iop_start_mpu(unsigned int start_addr)
+{
+	reg_iop_mpu_rw_ctrl mpu_ctrl = { .en = regk_iop_mpu_yes };
+	int retval;
+
+	/* disable MPU */
+	if ((retval = wait_mpu_idle()) != 0)
+		goto out;
+	REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_HALT());
+	if ((retval = wait_mpu_idle()) != 0)
+		goto out;
+	/* set PC and wait for it to bite */
+	if ((retval = wait_mpu_idle()) != 0)
+		goto out;
+	REG_WR_INT(iop_mpu, regi_iop_mpu, rw_instr, MPU_BA_I(start_addr));
+	if ((retval = wait_mpu_idle()) != 0)
+		goto out;
+	/* make sure the MPU starts executing with interrupts disabled */
+	REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_DI());
+	if ((retval = wait_mpu_idle()) != 0)
+		goto out;
+	/* enable MPU */
+	REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl);
+ out:
+	return retval;
+}
+
+static int __init iop_fw_load_init(void)
+{
+	device_initialize(&iop_spu_device[0]);
+	kobject_set_name(&iop_spu_device[0].kobj, "iop-spu0");
+	kobject_add(&iop_spu_device[0].kobj);
+	device_initialize(&iop_spu_device[1]);
+	kobject_set_name(&iop_spu_device[1].kobj, "iop-spu1");
+	kobject_add(&iop_spu_device[1].kobj);
+	device_initialize(&iop_mpu_device);
+	kobject_set_name(&iop_mpu_device.kobj, "iop-mpu");
+	kobject_add(&iop_mpu_device.kobj);
+	return 0;
+}
+
+static void __exit iop_fw_load_exit(void)
+{
+}
+
+module_init(iop_fw_load_init);
+module_exit(iop_fw_load_exit);
+
+MODULE_DESCRIPTION("ETRAX FS IO-Processor Firmware Loader");
+MODULE_LICENSE("GPL");
+
+EXPORT_SYMBOL(iop_fw_load_spu);
+EXPORT_SYMBOL(iop_fw_load_mpu);
+EXPORT_SYMBOL(iop_start_mpu);
diff --git a/arch/cris/arch-v32/drivers/nandflash.c b/arch/cris/arch-v32/drivers/nandflash.c
new file mode 100644
index 00000000000..fc2a619b035
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/nandflash.c
@@ -0,0 +1,157 @@
+/*
+ *  arch/cris/arch-v32/drivers/nandflash.c
+ *
+ *  Copyright (c) 2004
+ *
+ *  Derived from drivers/mtd/nand/spia.c
+ * 	  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
+ *
+ * $Id: nandflash.c,v 1.3 2005/06/01 10:57:12 starvik Exp $
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/version.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/memmap.h>
+#include <asm/arch/hwregs/reg_map.h>
+#include <asm/arch/hwregs/reg_rdwr.h>
+#include <asm/arch/hwregs/gio_defs.h>
+#include <asm/arch/hwregs/bif_core_defs.h>
+#include <asm/io.h>
+
+#define CE_BIT 4
+#define CLE_BIT 5
+#define ALE_BIT 6
+#define BY_BIT 7
+
+static struct mtd_info *crisv32_mtd = NULL;
+/*
+ *	hardware specific access to control-lines
+*/
+static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+	unsigned long flags;
+	reg_gio_rw_pa_dout dout = REG_RD(gio, regi_gio, rw_pa_dout);
+
+	local_irq_save(flags);
+	switch(cmd){
+		case NAND_CTL_SETCLE:
+		     dout.data |= (1<<CLE_BIT);
+		     break;
+		case NAND_CTL_CLRCLE:
+		     dout.data &= ~(1<<CLE_BIT);
+		     break;
+		case NAND_CTL_SETALE:
+		     dout.data |= (1<<ALE_BIT);
+		     break;
+		case NAND_CTL_CLRALE:
+		     dout.data &= ~(1<<ALE_BIT);
+		     break;
+		case NAND_CTL_SETNCE:
+		     dout.data |= (1<<CE_BIT);
+		     break;
+		case NAND_CTL_CLRNCE:
+		     dout.data &= ~(1<<CE_BIT);
+		     break;
+	}
+	REG_WR(gio, regi_gio, rw_pa_dout, dout);
+	local_irq_restore(flags);
+}
+
+/*
+*	read device ready pin
+*/
+int crisv32_device_ready(struct mtd_info *mtd)
+{
+	reg_gio_r_pa_din din = REG_RD(gio, regi_gio, r_pa_din);
+	return ((din.data & (1 << BY_BIT)) >> BY_BIT);
+}
+
+/*
+ * Main initialization routine
+ */
+struct mtd_info* __init crisv32_nand_flash_probe (void)
+{
+	void __iomem *read_cs;
+	void __iomem *write_cs;
+
+	reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core, rw_grp3_cfg);
+	reg_gio_rw_pa_oe pa_oe = REG_RD(gio, regi_gio, rw_pa_oe);
+	struct nand_chip *this;
+	int err = 0;
+
+	/* Allocate memory for MTD device structure and private data */
+	crisv32_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct nand_chip),
+				GFP_KERNEL);
+	if (!crisv32_mtd) {
+		printk ("Unable to allocate CRISv32 NAND MTD device structure.\n");
+		err = -ENOMEM;
+		return NULL;
+	}
+
+	read_cs = ioremap(MEM_CSP0_START | MEM_NON_CACHEABLE, 8192);
+	write_cs = ioremap(MEM_CSP1_START | MEM_NON_CACHEABLE, 8192);
+
+	if (!read_cs || !write_cs) {
+		printk("CRISv32 NAND ioremap failed\n");
+		err = -EIO;
+		goto out_mtd;
+	}
+
+	/* Get pointer to private data */
+	this = (struct nand_chip *) (&crisv32_mtd[1]);
+
+	pa_oe.oe |= 1 << CE_BIT;
+	pa_oe.oe |= 1 << ALE_BIT;
+	pa_oe.oe |= 1 << CLE_BIT;
+	pa_oe.oe &= ~ (1 << BY_BIT);
+	REG_WR(gio, regi_gio, rw_pa_oe, pa_oe);
+
+	bif_cfg.gated_csp0 = regk_bif_core_rd;
+	bif_cfg.gated_csp1 = regk_bif_core_wr;
+	REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg);
+
+	/* Initialize structures */
+	memset((char *) crisv32_mtd, 0, sizeof(struct mtd_info));
+	memset((char *) this, 0, sizeof(struct nand_chip));
+
+	/* Link the private data with the MTD structure */
+	crisv32_mtd->priv = this;
+
+	/* Set address of NAND IO lines */
+	this->IO_ADDR_R = read_cs;
+	this->IO_ADDR_W = write_cs;
+	this->hwcontrol = crisv32_hwcontrol;
+	this->dev_ready = crisv32_device_ready;
+	/* 20 us command delay time */
+	this->chip_delay = 20;
+	this->eccmode = NAND_ECC_SOFT;
+
+	/* Enable the following for a flash based bad block table */
+	this->options = NAND_USE_FLASH_BBT;
+
+	/* Scan to find existance of the device */
+	if (nand_scan (crisv32_mtd, 1)) {
+		err = -ENXIO;
+		goto out_ior;
+	}
+
+	return crisv32_mtd;
+
+out_ior:
+	iounmap((void *)read_cs);
+	iounmap((void *)write_cs);
+out_mtd:
+	kfree (crisv32_mtd);
+        return NULL;
+}
+
diff --git a/arch/cris/arch-v32/drivers/pcf8563.c b/arch/cris/arch-v32/drivers/pcf8563.c
new file mode 100644
index 00000000000..f894580b648
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/pcf8563.c
@@ -0,0 +1,341 @@
+/*
+ * PCF8563 RTC
+ *
+ * From Phillips' datasheet:
+ *
+ * The PCF8563 is a CMOS real-time clock/calendar optimized for low power
+ * consumption. A programmable clock output, interupt output and voltage
+ * low detector are also provided. All address and data are transferred
+ * serially via two-line bidirectional I2C-bus. Maximum bus speed is
+ * 400 kbits/s. The built-in word address register is incremented
+ * automatically after each written or read byte.
+ *
+ * Copyright (c) 2002-2003, Axis Communications AB
+ * All rights reserved.
+ *
+ * Author: Tobias Anderberg <tobiasa@axis.com>.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/ioctl.h>
+#include <linux/delay.h>
+#include <linux/bcd.h>
+
+#include <asm/uaccess.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/rtc.h>
+
+#include "i2c.h"
+
+#define PCF8563_MAJOR	121	/* Local major number. */
+#define DEVICE_NAME	"rtc"	/* Name which is registered in /proc/devices. */
+#define PCF8563_NAME	"PCF8563"
+#define DRIVER_VERSION	"$Revision: 1.1 $"
+
+/* Two simple wrapper macros, saves a few keystrokes. */
+#define rtc_read(x) i2c_readreg(RTC_I2C_READ, x)
+#define rtc_write(x,y) i2c_writereg(RTC_I2C_WRITE, x, y)
+
+static const unsigned char days_in_month[] =
+	{ 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
+
+int pcf8563_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
+int pcf8563_open(struct inode *, struct file *);
+int pcf8563_release(struct inode *, struct file *);
+
+static struct file_operations pcf8563_fops = {
+	owner: THIS_MODULE,
+	ioctl: pcf8563_ioctl,
+	open: pcf8563_open,
+	release: pcf8563_release,
+};
+
+unsigned char
+pcf8563_readreg(int reg)
+{
+	unsigned char res = rtc_read(reg);
+
+	/* The PCF8563 does not return 0 for unimplemented bits */
+	switch (reg) {
+		case RTC_SECONDS:
+		case RTC_MINUTES:
+			res &= 0x7F;
+			break;
+		case RTC_HOURS:
+		case RTC_DAY_OF_MONTH:
+			res &= 0x3F;
+			break;
+		case RTC_WEEKDAY:
+			res &= 0x07;
+			break;
+		case RTC_MONTH:
+			res &= 0x1F;
+			break;
+		case RTC_CONTROL1:
+			res &= 0xA8;
+			break;
+		case RTC_CONTROL2:
+			res &= 0x1F;
+			break;
+		case RTC_CLOCKOUT_FREQ:
+		case RTC_TIMER_CONTROL:
+			res &= 0x83;
+			break;
+	}
+	return res;
+}
+
+void
+pcf8563_writereg(int reg, unsigned char val)
+{
+#ifdef CONFIG_ETRAX_RTC_READONLY
+	if (reg == RTC_CONTROL1 || (reg >= RTC_SECONDS && reg <= RTC_YEAR))
+		return;
+#endif
+
+	rtc_write(reg, val);
+}
+
+void
+get_rtc_time(struct rtc_time *tm)
+{
+	tm->tm_sec  = rtc_read(RTC_SECONDS);
+	tm->tm_min  = rtc_read(RTC_MINUTES);
+	tm->tm_hour = rtc_read(RTC_HOURS);
+	tm->tm_mday = rtc_read(RTC_DAY_OF_MONTH);
+	tm->tm_wday = rtc_read(RTC_WEEKDAY);
+	tm->tm_mon  = rtc_read(RTC_MONTH);
+	tm->tm_year = rtc_read(RTC_YEAR);
+
+	if (tm->tm_sec & 0x80)
+		printk(KERN_WARNING "%s: RTC Voltage Low - reliable date/time "
+		       "information is no longer guaranteed!\n", PCF8563_NAME);
+
+	tm->tm_year  = BCD_TO_BIN(tm->tm_year) + ((tm->tm_mon & 0x80) ? 100 : 0);
+	tm->tm_sec  &= 0x7F;
+	tm->tm_min  &= 0x7F;
+	tm->tm_hour &= 0x3F;
+	tm->tm_mday &= 0x3F;
+	tm->tm_wday &= 0x07; /* Not coded in BCD. */
+	tm->tm_mon  &= 0x1F;
+
+	BCD_TO_BIN(tm->tm_sec);
+	BCD_TO_BIN(tm->tm_min);
+	BCD_TO_BIN(tm->tm_hour);
+	BCD_TO_BIN(tm->tm_mday);
+	BCD_TO_BIN(tm->tm_mon);
+	tm->tm_mon--; /* Month is 1..12 in RTC but 0..11 in linux */
+}
+
+int __init
+pcf8563_init(void)
+{
+	/* Initiate the i2c protocol. */
+	i2c_init();
+
+	/*
+	 * First of all we need to reset the chip. This is done by
+	 * clearing control1, control2 and clk freq and resetting
+	 * all alarms.
+	 */
+	if (rtc_write(RTC_CONTROL1, 0x00) < 0)
+		goto err;
+
+	if (rtc_write(RTC_CONTROL2, 0x00) < 0)
+		goto err;
+
+	if (rtc_write(RTC_CLOCKOUT_FREQ, 0x00) < 0)
+		goto err;
+
+	if (rtc_write(RTC_TIMER_CONTROL, 0x03) < 0)
+		goto err;
+
+	/* Reset the alarms. */
+	if (rtc_write(RTC_MINUTE_ALARM, 0x80) < 0)
+		goto err;
+
+	if (rtc_write(RTC_HOUR_ALARM, 0x80) < 0)
+		goto err;
+
+	if (rtc_write(RTC_DAY_ALARM, 0x80) < 0)
+		goto err;
+
+	if (rtc_write(RTC_WEEKDAY_ALARM, 0x80) < 0)
+		goto err;
+
+	if (register_chrdev(PCF8563_MAJOR, DEVICE_NAME, &pcf8563_fops) < 0) {
+		printk(KERN_INFO "%s: Unable to get major numer %d for RTC device.\n",
+		       PCF8563_NAME, PCF8563_MAJOR);
+		return -1;
+	}
+
+	printk(KERN_INFO "%s Real-Time Clock Driver, %s\n", PCF8563_NAME, DRIVER_VERSION);
+
+	/* Check for low voltage, and warn about it.. */
+	if (rtc_read(RTC_SECONDS) & 0x80)
+		printk(KERN_WARNING "%s: RTC Voltage Low - reliable date/time "
+		       "information is no longer guaranteed!\n", PCF8563_NAME);
+
+	return 0;
+
+err:
+	printk(KERN_INFO "%s: Error initializing chip.\n", PCF8563_NAME);
+	return -1;
+}
+
+void __exit
+pcf8563_exit(void)
+{
+	if (unregister_chrdev(PCF8563_MAJOR, DEVICE_NAME) < 0) {
+		printk(KERN_INFO "%s: Unable to unregister device.\n", PCF8563_NAME);
+	}
+}
+
+/*
+ * ioctl calls for this driver. Why return -ENOTTY upon error? Because
+ * POSIX says so!
+ */
+int
+pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
+{
+	/* Some sanity checks. */
+	if (_IOC_TYPE(cmd) != RTC_MAGIC)
+		return -ENOTTY;
+
+	if (_IOC_NR(cmd) > RTC_MAX_IOCTL)
+		return -ENOTTY;
+
+	switch (cmd) {
+		case RTC_RD_TIME:
+		{
+			struct rtc_time tm;
+
+			memset(&tm, 0, sizeof (struct rtc_time));
+			get_rtc_time(&tm);
+
+			if (copy_to_user((struct rtc_time *) arg, &tm, sizeof tm)) {
+				return -EFAULT;
+			}
+
+			return 0;
+		}
+
+		case RTC_SET_TIME:
+		{
+#ifdef CONFIG_ETRAX_RTC_READONLY
+			return -EPERM;
+#else
+			int leap;
+			int year;
+			int century;
+			struct rtc_time tm;
+
+			if (!capable(CAP_SYS_TIME))
+				return -EPERM;
+
+			if (copy_from_user(&tm, (struct rtc_time *) arg, sizeof tm))
+				return -EFAULT;
+
+			/* Convert from struct tm to struct rtc_time. */
+			tm.tm_year += 1900;
+			tm.tm_mon += 1;
+
+			/*
+			 * Check if tm.tm_year is a leap year. A year is a leap
+			 * year if it is divisible by 4 but not 100, except
+			 * that years divisible by 400 _are_ leap years.
+			 */
+			year = tm.tm_year;
+			leap = (tm.tm_mon == 2) && ((year % 4 == 0 && year % 100 != 0) || year % 400 == 0);
+
+			/* Perform some sanity checks. */
+			if ((tm.tm_year < 1970) ||
+			    (tm.tm_mon > 12) ||
+			    (tm.tm_mday == 0) ||
+			    (tm.tm_mday > days_in_month[tm.tm_mon] + leap) ||
+			    (tm.tm_wday >= 7) ||
+			    (tm.tm_hour >= 24) ||
+			    (tm.tm_min >= 60) ||
+			    (tm.tm_sec >= 60))
+				return -EINVAL;
+
+			century = (tm.tm_year >= 2000) ? 0x80 : 0;
+			tm.tm_year = tm.tm_year % 100;
+
+			BIN_TO_BCD(tm.tm_year);
+			BIN_TO_BCD(tm.tm_mday);
+			BIN_TO_BCD(tm.tm_hour);
+			BIN_TO_BCD(tm.tm_min);
+			BIN_TO_BCD(tm.tm_sec);
+			tm.tm_mon |= century;
+
+			rtc_write(RTC_YEAR, tm.tm_year);
+			rtc_write(RTC_MONTH, tm.tm_mon);
+			rtc_write(RTC_WEEKDAY, tm.tm_wday); /* Not coded in BCD. */
+			rtc_write(RTC_DAY_OF_MONTH, tm.tm_mday);
+			rtc_write(RTC_HOURS, tm.tm_hour);
+			rtc_write(RTC_MINUTES, tm.tm_min);
+			rtc_write(RTC_SECONDS, tm.tm_sec);
+
+			return 0;
+#endif /* !CONFIG_ETRAX_RTC_READONLY */
+		}
+
+		case RTC_VLOW_RD:
+		{
+			int vl_bit = 0;
+
+			if (rtc_read(RTC_SECONDS) & 0x80) {
+				vl_bit = 1;
+				printk(KERN_WARNING "%s: RTC Voltage Low - reliable "
+				       "date/time information is no longer guaranteed!\n",
+				       PCF8563_NAME);
+			}
+			if (copy_to_user((int *) arg, &vl_bit, sizeof(int)))
+				return -EFAULT;
+
+			return 0;
+		}
+
+		case RTC_VLOW_SET:
+		{
+			/* Clear the VL bit in the seconds register */
+			int ret = rtc_read(RTC_SECONDS);
+
+			rtc_write(RTC_SECONDS, (ret & 0x7F));
+
+			return 0;
+		}
+
+		default:
+			return -ENOTTY;
+	}
+
+	return 0;
+}
+
+int
+pcf8563_open(struct inode *inode, struct file *filp)
+{
+	MOD_INC_USE_COUNT;
+	return 0;
+}
+
+int
+pcf8563_release(struct inode *inode, struct file *filp)
+{
+	MOD_DEC_USE_COUNT;
+	return 0;
+}
+
+module_init(pcf8563_init);
+module_exit(pcf8563_exit);
diff --git a/arch/cris/arch-v32/drivers/pci/Makefile b/arch/cris/arch-v32/drivers/pci/Makefile
new file mode 100644
index 00000000000..bff7482f244
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/pci/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for Etrax cardbus driver
+#
+
+obj-$(CONFIG_ETRAX_CARDBUS)        += bios.o dma.o
diff --git a/arch/cris/arch-v32/drivers/pci/bios.c b/arch/cris/arch-v32/drivers/pci/bios.c
new file mode 100644
index 00000000000..24bc149889b
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/pci/bios.c
@@ -0,0 +1,131 @@
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <asm/arch/hwregs/intr_vect.h>
+
+void __devinit  pcibios_fixup_bus(struct pci_bus *b)
+{
+}
+
+char * __devinit  pcibios_setup(char *str)
+{
+	return NULL;
+}
+
+void pcibios_set_master(struct pci_dev *dev)
+{
+	u8 lat;
+	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
+	printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
+	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
+}
+
+int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
+			enum pci_mmap_state mmap_state, int write_combine)
+{
+	unsigned long prot;
+
+	/* Leave vm_pgoff as-is, the PCI space address is the physical
+	 * address on this platform.
+	 */
+	vma->vm_flags |= (VM_SHM | VM_LOCKED | VM_IO);
+
+	prot = pgprot_val(vma->vm_page_prot);
+	vma->vm_page_prot = __pgprot(prot);
+
+	/* Write-combine setting is ignored, it is changed via the mtrr
+	 * interfaces on this platform.
+	 */
+	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+			     vma->vm_end - vma->vm_start,
+			     vma->vm_page_prot))
+		return -EAGAIN;
+
+	return 0;
+}
+
+void
+pcibios_align_resource(void *data, struct resource *res,
+		       unsigned long size, unsigned long align)
+{
+	if (res->flags & IORESOURCE_IO) {
+		unsigned long start = res->start;
+
+		if (start & 0x300) {
+			start = (start + 0x3ff) & ~0x3ff;
+			res->start = start;
+		}
+	}
+}
+
+int pcibios_enable_resources(struct pci_dev *dev, int mask)
+{
+	u16 cmd, old_cmd;
+	int idx;
+	struct resource *r;
+
+	pci_read_config_word(dev, PCI_COMMAND, &cmd);
+	old_cmd = cmd;
+	for(idx=0; idx<6; idx++) {
+		/* Only set up the requested stuff */
+		if (!(mask & (1<<idx)))
+			continue;
+
+		r = &dev->resource[idx];
+		if (!r->start && r->end) {
+			printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
+			return -EINVAL;
+		}
+		if (r->flags & IORESOURCE_IO)
+			cmd |= PCI_COMMAND_IO;
+		if (r->flags & IORESOURCE_MEM)
+			cmd |= PCI_COMMAND_MEMORY;
+	}
+	if (dev->resource[PCI_ROM_RESOURCE].start)
+		cmd |= PCI_COMMAND_MEMORY;
+	if (cmd != old_cmd) {
+		printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
+		pci_write_config_word(dev, PCI_COMMAND, cmd);
+	}
+	return 0;
+}
+
+int pcibios_enable_irq(struct pci_dev *dev)
+{
+	dev->irq = EXT_INTR_VECT;
+	return 0;
+}
+
+int pcibios_enable_device(struct pci_dev *dev, int mask)
+{
+	int err;
+
+	if ((err = pcibios_enable_resources(dev, mask)) < 0)
+		return err;
+
+	return pcibios_enable_irq(dev);
+}
+
+int pcibios_assign_resources(void)
+{
+	struct pci_dev *dev = NULL;
+	int idx;
+	struct resource *r;
+
+	while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
+		int class = dev->class >> 8;
+
+		/* Don't touch classless devices and host bridges */
+		if (!class || class == PCI_CLASS_BRIDGE_HOST)
+			continue;
+
+		for(idx=0; idx<6; idx++) {
+			r = &dev->resource[idx];
+
+			if (!r->start && r->end)
+				pci_assign_resource(dev, idx);
+		}
+	}
+	return 0;
+}
+
+EXPORT_SYMBOL(pcibios_assign_resources);
diff --git a/arch/cris/arch-v32/drivers/pci/dma.c b/arch/cris/arch-v32/drivers/pci/dma.c
new file mode 100644
index 00000000000..10329306d23
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/pci/dma.c
@@ -0,0 +1,149 @@
+/*
+ * Dynamic DMA mapping support.
+ *
+ * On cris there is no hardware dynamic DMA address translation,
+ * so consistent alloc/free are merely page allocation/freeing.
+ * The rest of the dynamic DMA mapping interface is implemented
+ * in asm/pci.h.
+ *
+ * Borrowed from i386.
+ */
+
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/string.h>
+#include <linux/pci.h>
+#include <asm/io.h>
+
+struct dma_coherent_mem {
+	void		*virt_base;
+	u32		device_base;
+	int		size;
+	int		flags;
+	unsigned long	*bitmap;
+};
+
+void *dma_alloc_coherent(struct device *dev, size_t size,
+			   dma_addr_t *dma_handle, unsigned int __nocast gfp)
+{
+	void *ret;
+	struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
+	int order = get_order(size);
+	/* ignore region specifiers */
+	gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
+
+	if (mem) {
+		int page = bitmap_find_free_region(mem->bitmap, mem->size,
+						     order);
+		if (page >= 0) {
+			*dma_handle = mem->device_base + (page << PAGE_SHIFT);
+			ret = mem->virt_base + (page << PAGE_SHIFT);
+			memset(ret, 0, size);
+			return ret;
+		}
+		if (mem->flags & DMA_MEMORY_EXCLUSIVE)
+			return NULL;
+	}
+
+	if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff))
+		gfp |= GFP_DMA;
+
+	ret = (void *)__get_free_pages(gfp, order);
+
+	if (ret != NULL) {
+		memset(ret, 0, size);
+		*dma_handle = virt_to_phys(ret);
+	}
+	return ret;
+}
+
+void dma_free_coherent(struct device *dev, size_t size,
+			 void *vaddr, dma_addr_t dma_handle)
+{
+	struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
+	int order = get_order(size);
+
+	if (mem && vaddr >= mem->virt_base && vaddr < (mem->virt_base + (mem->size << PAGE_SHIFT))) {
+		int page = (vaddr - mem->virt_base) >> PAGE_SHIFT;
+
+		bitmap_release_region(mem->bitmap, page, order);
+	} else
+		free_pages((unsigned long)vaddr, order);
+}
+
+int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
+				dma_addr_t device_addr, size_t size, int flags)
+{
+	void __iomem *mem_base;
+	int pages = size >> PAGE_SHIFT;
+	int bitmap_size = (pages + 31)/32;
+
+	if ((flags & (DMA_MEMORY_MAP | DMA_MEMORY_IO)) == 0)
+		goto out;
+	if (!size)
+		goto out;
+	if (dev->dma_mem)
+		goto out;
+
+	/* FIXME: this routine just ignores DMA_MEMORY_INCLUDES_CHILDREN */
+
+	mem_base = ioremap(bus_addr, size);
+	if (!mem_base)
+		goto out;
+
+	dev->dma_mem = kmalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL);
+	if (!dev->dma_mem)
+		goto out;
+	memset(dev->dma_mem, 0, sizeof(struct dma_coherent_mem));
+	dev->dma_mem->bitmap = kmalloc(bitmap_size, GFP_KERNEL);
+	if (!dev->dma_mem->bitmap)
+		goto free1_out;
+	memset(dev->dma_mem->bitmap, 0, bitmap_size);
+
+	dev->dma_mem->virt_base = mem_base;
+	dev->dma_mem->device_base = device_addr;
+	dev->dma_mem->size = pages;
+	dev->dma_mem->flags = flags;
+
+	if (flags & DMA_MEMORY_MAP)
+		return DMA_MEMORY_MAP;
+
+	return DMA_MEMORY_IO;
+
+ free1_out:
+	kfree(dev->dma_mem->bitmap);
+ out:
+	return 0;
+}
+EXPORT_SYMBOL(dma_declare_coherent_memory);
+
+void dma_release_declared_memory(struct device *dev)
+{
+	struct dma_coherent_mem *mem = dev->dma_mem;
+
+	if(!mem)
+		return;
+	dev->dma_mem = NULL;
+	iounmap(mem->virt_base);
+	kfree(mem->bitmap);
+	kfree(mem);
+}
+EXPORT_SYMBOL(dma_release_declared_memory);
+
+void *dma_mark_declared_memory_occupied(struct device *dev,
+					dma_addr_t device_addr, size_t size)
+{
+	struct dma_coherent_mem *mem = dev->dma_mem;
+	int pages = (size + (device_addr & ~PAGE_MASK) + PAGE_SIZE - 1) >> PAGE_SHIFT;
+	int pos, err;
+
+	if (!mem)
+		return ERR_PTR(-EINVAL);
+
+	pos = (device_addr - mem->device_base) >> PAGE_SHIFT;
+	err = bitmap_allocate_region(mem->bitmap, pos, get_order(pages));
+	if (err != 0)
+		return ERR_PTR(err);
+	return mem->virt_base + (pos << PAGE_SHIFT);
+}
+EXPORT_SYMBOL(dma_mark_declared_memory_occupied);
diff --git a/arch/cris/arch-v32/drivers/sync_serial.c b/arch/cris/arch-v32/drivers/sync_serial.c
new file mode 100644
index 00000000000..c85a6df8558
--- /dev/null
+++ b/arch/cris/arch-v32/drivers/sync_serial.c
@@ -0,0 +1,1283 @@
+/*
+ * Simple synchronous serial port driver for ETRAX FS.
+ *
+ * Copyright (c) 2005 Axis Communications AB
+ *
+ * Author: Mikael Starvik
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/major.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/poll.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/spinlock.h>
+
+#include <asm/io.h>
+#include <asm/arch/dma.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/hwregs/reg_rdwr.h>
+#include <asm/arch/hwregs/sser_defs.h>
+#include <asm/arch/hwregs/dma_defs.h>
+#include <asm/arch/hwregs/dma.h>
+#include <asm/arch/hwregs/intr_vect_defs.h>
+#include <asm/arch/hwregs/intr_vect.h>
+#include <asm/arch/hwregs/reg_map.h>
+#include <asm/sync_serial.h>
+
+/* The receiver is a bit tricky beacuse of the continuous stream of data.*/
+/*                                                                       */
+/* Three DMA descriptors are linked together. Each DMA descriptor is     */
+/* responsible for port->bufchunk of a common buffer.                    */
+/*                                                                       */
+/* +---------------------------------------------+                       */
+/* |   +----------+   +----------+   +----------+ |                      */
+/* +-> | Descr[0] |-->| Descr[1] |-->| Descr[2] |-+                      */
+/*     +----------+   +----------+   +----------+                        */
+/*         |            |              |                                 */
+/*         v            v              v                                 */
+/*   +-------------------------------------+                             */
+/*   |        BUFFER                       |                             */
+/*   +-------------------------------------+                             */
+/*      |<- data_avail ->|                                               */
+/*    readp          writep                                              */
+/*                                                                       */
+/* If the application keeps up the pace readp will be right after writep.*/
+/* If the application can't keep the pace we have to throw away data.    */
+/* The idea is that readp should be ready with the data pointed out by	 */
+/* Descr[i] when the DMA has filled in Descr[i+1].                       */
+/* Otherwise we will discard	                                         */
+/* the rest of the data pointed out by Descr1 and set readp to the start */
+/* of Descr2                                                             */
+
+#define SYNC_SERIAL_MAJOR 125
+
+/* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */
+/* words can be handled */
+#define IN_BUFFER_SIZE 12288
+#define IN_DESCR_SIZE 256
+#define NUM_IN_DESCR (IN_BUFFER_SIZE/IN_DESCR_SIZE)
+#define OUT_BUFFER_SIZE 4096
+
+#define DEFAULT_FRAME_RATE 0
+#define DEFAULT_WORD_RATE 7
+
+/* NOTE: Enabling some debug will likely cause overrun or underrun,
+ * especially if manual mode is use.
+ */
+#define DEBUG(x)
+#define DEBUGREAD(x)
+#define DEBUGWRITE(x)
+#define DEBUGPOLL(x)
+#define DEBUGRXINT(x)
+#define DEBUGTXINT(x)
+
+typedef struct sync_port
+{
+	reg_scope_instances regi_sser;
+	reg_scope_instances regi_dmain;
+	reg_scope_instances regi_dmaout;
+
+	char started; /* 1 if port has been started */
+	char port_nbr; /* Port 0 or 1 */
+	char busy; /* 1 if port is busy */
+
+	char enabled;  /* 1 if port is enabled */
+	char use_dma;  /* 1 if port uses dma */
+	char tr_running;
+
+	char init_irqs;
+	int output;
+	int input;
+
+	volatile unsigned int out_count; /* Remaining bytes for current transfer */
+	unsigned char* outp; /* Current position in out_buffer */
+	volatile unsigned char* volatile readp;  /* Next byte to be read by application */
+	volatile unsigned char* volatile writep; /* Next byte to be written by etrax */
+	unsigned int in_buffer_size;
+	unsigned int inbufchunk;
+	unsigned char out_buffer[OUT_BUFFER_SIZE] __attribute__ ((aligned(32)));
+	unsigned char in_buffer[IN_BUFFER_SIZE]__attribute__ ((aligned(32)));
+	unsigned char flip[IN_BUFFER_SIZE] __attribute__ ((aligned(32)));
+	struct dma_descr_data* next_rx_desc;
+	struct dma_descr_data* prev_rx_desc;
+	int full;
+
+	dma_descr_data in_descr[NUM_IN_DESCR] __attribute__ ((__aligned__(16)));
+	dma_descr_context in_context __attribute__ ((__aligned__(32)));
+	dma_descr_data out_descr __attribute__ ((__aligned__(16)));
+	dma_descr_context out_context __attribute__ ((__aligned__(32)));
+	wait_queue_head_t out_wait_q;
+	wait_queue_head_t in_wait_q;
+
+	spinlock_t lock;
+} sync_port;
+
+static int etrax_sync_serial_init(void);
+static void initialize_port(int portnbr);
+static inline int sync_data_avail(struct sync_port *port);
+
+static int sync_serial_open(struct inode *, struct file*);
+static int sync_serial_release(struct inode*, struct file*);
+static unsigned int sync_serial_poll(struct file *filp, poll_table *wait);
+
+static int sync_serial_ioctl(struct inode*, struct file*,
+			     unsigned int cmd, unsigned long arg);
+static ssize_t sync_serial_write(struct file * file, const char * buf,
+				 size_t count, loff_t *ppos);
+static ssize_t sync_serial_read(struct file *file, char *buf,
+				size_t count, loff_t *ppos);
+
+#if (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
+     defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
+    (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
+     defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))
+#define SYNC_SER_DMA
+#endif
+
+static void send_word(sync_port* port);
+static void start_dma(struct sync_port *port, const char* data, int count);
+static void start_dma_in(sync_port* port);
+#ifdef SYNC_SER_DMA
+static irqreturn_t tr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
+static irqreturn_t rx_interrupt(int irq, void *dev_id, struct pt_regs * regs);
+#endif
+
+#if (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
+     !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
+    (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
+     !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))
+#define SYNC_SER_MANUAL
+#endif
+#ifdef SYNC_SER_MANUAL
+static irqreturn_t manual_interrupt(int irq, void *dev_id, struct pt_regs * regs);
+#endif
+
+/* The ports */
+static struct sync_port ports[]=
+{
+	{
+		.regi_sser             = regi_sser0,
+		.regi_dmaout           = regi_dma4,
+		.regi_dmain            = regi_dma5,
+#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)
+                .use_dma               = 1,
+#else
+                .use_dma               = 0,
+#endif
+	},
+	{
+		.regi_sser             = regi_sser1,
+		.regi_dmaout           = regi_dma6,
+		.regi_dmain            = regi_dma7,
+#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)
+                .use_dma               = 1,
+#else
+                .use_dma               = 0,
+#endif
+	}
+};
+
+#define NUMBER_OF_PORTS (sizeof(ports)/sizeof(sync_port))
+
+static struct file_operations sync_serial_fops = {
+	.owner   = THIS_MODULE,
+	.write   = sync_serial_write,
+	.read    = sync_serial_read,
+	.poll    = sync_serial_poll,
+	.ioctl   = sync_serial_ioctl,
+	.open    = sync_serial_open,
+	.release = sync_serial_release
+};
+
+static int __init etrax_sync_serial_init(void)
+{
+	ports[0].enabled = 0;
+	ports[1].enabled = 0;
+
+	if (register_chrdev(SYNC_SERIAL_MAJOR,"sync serial", &sync_serial_fops) <0 )
+	{
+		printk("unable to get major for synchronous serial port\n");
+		return -EBUSY;
+	}
+
+	/* Initialize Ports */
+#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
+	if (crisv32_pinmux_alloc_fixed(pinmux_sser0))
+	{
+		printk("Unable to allocate pins for syncrhronous serial port 0\n");
+		return -EIO;
+	}
+	ports[0].enabled = 1;
+	initialize_port(0);
+#endif
+
+#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
+	if (crisv32_pinmux_alloc_fixed(pinmux_sser1))
+	{
+		printk("Unable to allocate pins for syncrhronous serial port 0\n");
+		return -EIO;
+	}
+	ports[1].enabled = 1;
+	initialize_port(1);
+#endif
+
+	printk("ETRAX FS synchronous serial port driver\n");
+	return 0;
+}
+
+static void __init initialize_port(int portnbr)
+{
+	struct sync_port* port = &ports[portnbr];
+	reg_sser_rw_cfg cfg = {0};
+	reg_sser_rw_frm_cfg frm_cfg = {0};
+	reg_sser_rw_tr_cfg tr_cfg = {0};
+	reg_sser_rw_rec_cfg rec_cfg = {0};
+
+	DEBUG(printk("Init sync serial port %d\n", portnbr));
+
+	port->port_nbr = portnbr;
+	port->init_irqs = 1;
+
+	port->outp = port->out_buffer;
+	port->output = 1;
+	port->input = 0;
+
+	port->readp = port->flip;
+	port->writep = port->flip;
+	port->in_buffer_size = IN_BUFFER_SIZE;
+	port->inbufchunk = IN_DESCR_SIZE;
+	port->next_rx_desc = &port->in_descr[0];
+	port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR-1];
+	port->prev_rx_desc->eol = 1;
+
+	init_waitqueue_head(&port->out_wait_q);
+	init_waitqueue_head(&port->in_wait_q);
+
+	spin_lock_init(&port->lock);
+
+	cfg.out_clk_src = regk_sser_intern_clk;
+	cfg.out_clk_pol = regk_sser_pos;
+	cfg.clk_od_mode = regk_sser_no;
+	cfg.clk_dir = regk_sser_out;
+	cfg.gate_clk = regk_sser_no;
+	cfg.base_freq = regk_sser_f29_493;
+	cfg.clk_div = 256;
+	REG_WR(sser, port->regi_sser, rw_cfg, cfg);
+
+	frm_cfg.wordrate = DEFAULT_WORD_RATE;
+	frm_cfg.type = regk_sser_edge;
+	frm_cfg.frame_pin_dir = regk_sser_out;
+	frm_cfg.frame_pin_use = regk_sser_frm;
+	frm_cfg.status_pin_dir = regk_sser_in;
+	frm_cfg.status_pin_use = regk_sser_hold;
+	frm_cfg.out_on = regk_sser_tr;
+	frm_cfg.tr_delay = 1;
+	REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg);
+
+	tr_cfg.urun_stop = regk_sser_no;
+	tr_cfg.sample_size = 7;
+	tr_cfg.sh_dir = regk_sser_msbfirst;
+	tr_cfg.use_dma = port->use_dma ? regk_sser_yes : regk_sser_no;
+	tr_cfg.rate_ctrl = regk_sser_bulk;
+	tr_cfg.data_pin_use = regk_sser_dout;
+	tr_cfg.bulk_wspace = 1;
+	REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
+
+	rec_cfg.sample_size = 7;
+	rec_cfg.sh_dir = regk_sser_msbfirst;
+	rec_cfg.use_dma = port->use_dma ? regk_sser_yes : regk_sser_no;
+	rec_cfg.fifo_thr = regk_sser_inf;
+	REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
+}
+
+static inline int sync_data_avail(struct sync_port *port)
+{
+	int avail;
+	unsigned char *start;
+	unsigned char *end;
+
+	start = (unsigned char*)port->readp; /* cast away volatile */
+	end = (unsigned char*)port->writep;  /* cast away volatile */
+	/* 0123456789  0123456789
+	 *  -----      -    -----
+	 *  ^rp  ^wp    ^wp ^rp
+	 */
+
+  	if (end >= start)
+		avail = end - start;
+	else
+		avail = port->in_buffer_size - (start - end);
+	return avail;
+}
+
+static inline int sync_data_avail_to_end(struct sync_port *port)
+{
+	int avail;
+	unsigned char *start;
+	unsigned char *end;
+
+	start = (unsigned char*)port->readp; /* cast away volatile */
+	end = (unsigned char*)port->writep;  /* cast away volatile */
+	/* 0123456789  0123456789
+	 *  -----           -----
+	 *  ^rp  ^wp    ^wp ^rp
+	 */
+
+  	if (end >= start)
+		avail = end - start;
+	else
+		avail = port->flip + port->in_buffer_size - start;
+	return avail;
+}
+
+static int sync_serial_open(struct inode *inode, struct file *file)
+{
+	int dev = MINOR(inode->i_rdev);
+	sync_port* port;
+	reg_dma_rw_cfg cfg = {.en = regk_dma_yes};
+	reg_dma_rw_intr_mask intr_mask = {.data = regk_dma_yes};
+
+	DEBUG(printk("Open sync serial port %d\n", dev));
+
+	if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
+	{
+		DEBUG(printk("Invalid minor %d\n", dev));
+		return -ENODEV;
+	}
+	port = &ports[dev];
+	/* Allow open this device twice (assuming one reader and one writer) */
+	if (port->busy == 2)
+	{
+		DEBUG(printk("Device is busy.. \n"));
+		return -EBUSY;
+	}
+	if (port->init_irqs) {
+		if (port->use_dma) {
+			if (port == &ports[0]){
+#ifdef SYNC_SER_DMA
+				if(request_irq(DMA4_INTR_VECT,
+					       tr_interrupt,
+					       0,
+					       "synchronous serial 0 dma tr",
+					       &ports[0])) {
+					printk(KERN_CRIT "Can't allocate sync serial port 0 IRQ");
+					return -EBUSY;
+				} else if(request_irq(DMA5_INTR_VECT,
+						      rx_interrupt,
+						      0,
+						      "synchronous serial 1 dma rx",
+						      &ports[0])) {
+					free_irq(DMA4_INTR_VECT, &port[0]);
+					printk(KERN_CRIT "Can't allocate sync serial port 0 IRQ");
+					return -EBUSY;
+				} else if (crisv32_request_dma(SYNC_SER0_TX_DMA_NBR,
+                                                               "synchronous serial 0 dma tr",
+                                                               DMA_VERBOSE_ON_ERROR,
+                                                               0,
+                                                               dma_sser0)) {
+					free_irq(DMA4_INTR_VECT, &port[0]);
+					free_irq(DMA5_INTR_VECT, &port[0]);
+					printk(KERN_CRIT "Can't allocate sync serial port 0 TX DMA channel");
+					return -EBUSY;
+				} else if (crisv32_request_dma(SYNC_SER0_RX_DMA_NBR,
+                                                               "synchronous serial 0 dma rec",
+                                                               DMA_VERBOSE_ON_ERROR,
+                                                               0,
+                                                               dma_sser0)) {
+					crisv32_free_dma(SYNC_SER0_TX_DMA_NBR);
+					free_irq(DMA4_INTR_VECT, &port[0]);
+					free_irq(DMA5_INTR_VECT, &port[0]);
+					printk(KERN_CRIT "Can't allocate sync serial port 1 RX DMA channel");
+					return -EBUSY;
+				}
+#endif
+			}
+			else if (port == &ports[1]){
+#ifdef SYNC_SER_DMA
+				if (request_irq(DMA6_INTR_VECT,
+						tr_interrupt,
+						0,
+						"synchronous serial 1 dma tr",
+						&ports[1])) {
+					printk(KERN_CRIT "Can't allocate sync serial port 1 IRQ");
+					return -EBUSY;
+				} else if (request_irq(DMA7_INTR_VECT,
+						       rx_interrupt,
+						       0,
+						       "synchronous serial 1 dma rx",
+						       &ports[1])) {
+					free_irq(DMA6_INTR_VECT, &ports[1]);
+					printk(KERN_CRIT "Can't allocate sync serial port 3 IRQ");
+					return -EBUSY;
+				} else if (crisv32_request_dma(SYNC_SER1_TX_DMA_NBR,
+                                                               "synchronous serial 1 dma tr",
+                                                               DMA_VERBOSE_ON_ERROR,
+                                                               0,
+                                                               dma_sser1)) {
+					free_irq(21, &ports[1]);
+					free_irq(20, &ports[1]);
+					printk(KERN_CRIT "Can't allocate sync serial port 3 TX DMA channel");
+					return -EBUSY;
+				} else if (crisv32_request_dma(SYNC_SER1_RX_DMA_NBR,
+							    "synchronous serial 3 dma rec",
+							    DMA_VERBOSE_ON_ERROR,
+							    0,
+							    dma_sser1)) {
+					crisv32_free_dma(SYNC_SER1_TX_DMA_NBR);
+					free_irq(DMA6_INTR_VECT, &ports[1]);
+					free_irq(DMA7_INTR_VECT, &ports[1]);
+					printk(KERN_CRIT "Can't allocate sync serial port 3 RX DMA channel");
+					return -EBUSY;
+				}
+#endif
+			}
+
+                        /* Enable DMAs */
+			REG_WR(dma, port->regi_dmain, rw_cfg, cfg);
+			REG_WR(dma, port->regi_dmaout, rw_cfg, cfg);
+			/* Enable DMA IRQs */
+			REG_WR(dma, port->regi_dmain, rw_intr_mask, intr_mask);
+			REG_WR(dma, port->regi_dmaout, rw_intr_mask, intr_mask);
+			/* Set up wordsize = 2 for DMAs. */
+			DMA_WR_CMD (port->regi_dmain, regk_dma_set_w_size1);
+			DMA_WR_CMD (port->regi_dmaout, regk_dma_set_w_size1);
+
+			start_dma_in(port);
+			port->init_irqs = 0;
+		} else { /* !port->use_dma */
+#ifdef SYNC_SER_MANUAL
+			if (port == &ports[0]) {
+				if (request_irq(SSER0_INTR_VECT,
+						manual_interrupt,
+						0,
+						"synchronous serial manual irq",
+						&ports[0])) {
+					printk("Can't allocate sync serial manual irq");
+					return -EBUSY;
+				}
+			} else if (port == &ports[1]) {
+				if (request_irq(SSER1_INTR_VECT,
+						manual_interrupt,
+						0,
+						"synchronous serial manual irq",
+						&ports[1])) {
+					printk(KERN_CRIT "Can't allocate sync serial manual irq");
+					return -EBUSY;
+				}
+			}
+			port->init_irqs = 0;
+#else
+			panic("sync_serial: Manual mode not supported.\n");
+#endif /* SYNC_SER_MANUAL */
+		}
+	} /* port->init_irqs */
+
+	port->busy++;
+	return 0;
+}
+
+static int sync_serial_release(struct inode *inode, struct file *file)
+{
+	int dev = MINOR(inode->i_rdev);
+	sync_port* port;
+
+	if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
+	{
+		DEBUG(printk("Invalid minor %d\n", dev));
+		return -ENODEV;
+	}
+	port = &ports[dev];
+	if (port->busy)
+		port->busy--;
+	if (!port->busy)
+          /* XXX */ ;
+	return 0;
+}
+
+static unsigned int sync_serial_poll(struct file *file, poll_table *wait)
+{
+	int dev = MINOR(file->f_dentry->d_inode->i_rdev);
+	unsigned int mask = 0;
+	sync_port* port;
+	DEBUGPOLL( static unsigned int prev_mask = 0; );
+
+	port = &ports[dev];
+	poll_wait(file, &port->out_wait_q, wait);
+	poll_wait(file, &port->in_wait_q, wait);
+	/* Some room to write */
+	if (port->out_count < OUT_BUFFER_SIZE)
+		mask |=  POLLOUT | POLLWRNORM;
+	/* At least an inbufchunk of data */
+	if (sync_data_avail(port) >= port->inbufchunk)
+		mask |= POLLIN | POLLRDNORM;
+
+	DEBUGPOLL(if (mask != prev_mask)
+	      printk("sync_serial_poll: mask 0x%08X %s %s\n", mask,
+		     mask&POLLOUT?"POLLOUT":"", mask&POLLIN?"POLLIN":"");
+	      prev_mask = mask;
+	      );
+	return mask;
+}
+
+static int sync_serial_ioctl(struct inode *inode, struct file *file,
+		  unsigned int cmd, unsigned long arg)
+{
+	int return_val = 0;
+	int dev = MINOR(file->f_dentry->d_inode->i_rdev);
+	sync_port* port;
+	reg_sser_rw_tr_cfg tr_cfg;
+	reg_sser_rw_rec_cfg rec_cfg;
+	reg_sser_rw_frm_cfg frm_cfg;
+	reg_sser_rw_cfg gen_cfg;
+	reg_sser_rw_intr_mask intr_mask;
+
+	if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
+	{
+		DEBUG(printk("Invalid minor %d\n", dev));
+		return -1;
+	}
+        port = &ports[dev];
+	spin_lock_irq(&port->lock);
+
+	tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg);
+	rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg);
+	frm_cfg = REG_RD(sser, port->regi_sser, rw_frm_cfg);
+	gen_cfg = REG_RD(sser, port->regi_sser, rw_cfg);
+	intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask);
+
+	switch(cmd)
+	{
+	case SSP_SPEED:
+		if (GET_SPEED(arg) == CODEC)
+		{
+			gen_cfg.base_freq = regk_sser_f32;
+			/* FREQ = 0 => 4 MHz => clk_div = 7*/
+			gen_cfg.clk_div = 6 + (1 << GET_FREQ(arg));
+		}
+		else
+		{
+			gen_cfg.base_freq = regk_sser_f29_493;
+			switch (GET_SPEED(arg))
+			{
+				case SSP150:
+					gen_cfg.clk_div = 29493000 / (150 * 8) - 1;
+					break;
+				case SSP300:
+					gen_cfg.clk_div = 29493000 / (300 * 8) - 1;
+					break;
+				case SSP600:
+					gen_cfg.clk_div = 29493000 / (600 * 8) - 1;
+					break;
+				case SSP1200:
+					gen_cfg.clk_div = 29493000 / (1200 * 8) - 1;
+					break;
+				case SSP2400:
+					gen_cfg.clk_div = 29493000 / (2400 * 8) - 1;
+					break;
+				case SSP4800:
+					gen_cfg.clk_div = 29493000 / (4800 * 8) - 1;
+					break;
+				case SSP9600:
+					gen_cfg.clk_div = 29493000 / (9600 * 8) - 1;
+					break;
+				case SSP19200:
+					gen_cfg.clk_div = 29493000 / (19200 * 8) - 1;
+					break;
+				case SSP28800:
+					gen_cfg.clk_div = 29493000 / (28800 * 8) - 1;
+					break;
+				case SSP57600:
+					gen_cfg.clk_div = 29493000 / (57600 * 8) - 1;
+					break;
+				case SSP115200:
+					gen_cfg.clk_div = 29493000 / (115200 * 8) - 1;
+					break;
+				case SSP230400:
+					gen_cfg.clk_div = 29493000 / (230400 * 8) - 1;
+					break;
+				case SSP460800:
+					gen_cfg.clk_div = 29493000 / (460800 * 8) - 1;
+					break;
+				case SSP921600:
+					gen_cfg.clk_div = 29493000 / (921600 * 8) - 1;
+					break;
+				case SSP3125000:
+					gen_cfg.base_freq = regk_sser_f100;
+					gen_cfg.clk_div = 100000000 / (3125000 * 8) - 1;
+					break;
+
+			}
+		}
+		frm_cfg.wordrate = GET_WORD_RATE(arg);
+
+		break;
+	case SSP_MODE:
+		switch(arg)
+		{
+			case MASTER_OUTPUT:
+				port->output = 1;
+				port->input = 0;
+				gen_cfg.clk_dir = regk_sser_out;
+				break;
+			case SLAVE_OUTPUT:
+				port->output = 1;
+				port->input = 0;
+				gen_cfg.clk_dir = regk_sser_in;
+				break;
+			case MASTER_INPUT:
+				port->output = 0;
+				port->input = 1;
+				gen_cfg.clk_dir = regk_sser_out;
+				break;
+			case SLAVE_INPUT:
+				port->output = 0;
+				port->input = 1;
+				gen_cfg.clk_dir = regk_sser_in;
+				break;
+			case MASTER_BIDIR:
+				port->output = 1;
+				port->input = 1;
+				gen_cfg.clk_dir = regk_sser_out;
+				break;
+			case SLAVE_BIDIR:
+				port->output = 1;
+				port->input = 1;
+				gen_cfg.clk_dir = regk_sser_in;
+				break;
+			default:
+				spin_unlock_irq(&port->lock);
+				return -EINVAL;
+
+		}
+		if (!port->use_dma || (arg == MASTER_OUTPUT || arg == SLAVE_OUTPUT))
+			intr_mask.rdav = regk_sser_yes;
+		break;
+	case SSP_FRAME_SYNC:
+		if (arg & NORMAL_SYNC)
+			frm_cfg.tr_delay = 1;
+		else if (arg & EARLY_SYNC)
+			frm_cfg.tr_delay = 0;
+
+		tr_cfg.bulk_wspace = frm_cfg.tr_delay;
+		frm_cfg.early_wend = regk_sser_yes;
+		if (arg & BIT_SYNC)
+			frm_cfg.type = regk_sser_edge;
+		else if (arg & WORD_SYNC)
+			frm_cfg.type = regk_sser_level;
+		else if (arg & EXTENDED_SYNC)
+			frm_cfg.early_wend = regk_sser_no;
+
+		if (arg & SYNC_ON)
+			frm_cfg.frame_pin_use = regk_sser_frm;
+		else if (arg & SYNC_OFF)
+			frm_cfg.frame_pin_use = regk_sser_gio0;
+
+		if (arg & WORD_SIZE_8)
+			rec_cfg.sample_size = tr_cfg.sample_size = 7;
+		else if (arg & WORD_SIZE_12)
+			rec_cfg.sample_size = tr_cfg.sample_size = 11;
+		else if (arg & WORD_SIZE_16)
+			rec_cfg.sample_size = tr_cfg.sample_size = 15;
+		else if (arg & WORD_SIZE_24)
+			rec_cfg.sample_size = tr_cfg.sample_size = 23;
+		else if (arg & WORD_SIZE_32)
+			rec_cfg.sample_size = tr_cfg.sample_size = 31;
+
+		if (arg & BIT_ORDER_MSB)
+			rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_msbfirst;
+		else if (arg & BIT_ORDER_LSB)
+			rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_lsbfirst;
+
+		if (arg & FLOW_CONTROL_ENABLE)
+			rec_cfg.fifo_thr = regk_sser_thr16;
+		else if (arg & FLOW_CONTROL_DISABLE)
+			rec_cfg.fifo_thr = regk_sser_inf;
+
+		if (arg & CLOCK_NOT_GATED)
+			gen_cfg.gate_clk = regk_sser_no;
+		else if (arg & CLOCK_GATED)
+			gen_cfg.gate_clk = regk_sser_yes;
+
+		break;
+	case SSP_IPOLARITY:
+		/* NOTE!! negedge is considered NORMAL */
+		if (arg & CLOCK_NORMAL)
+			rec_cfg.clk_pol = regk_sser_neg;
+		else if (arg & CLOCK_INVERT)
+			rec_cfg.clk_pol = regk_sser_pos;
+
+		if (arg & FRAME_NORMAL)
+			frm_cfg.level = regk_sser_pos_hi;
+		else if (arg & FRAME_INVERT)
+			frm_cfg.level = regk_sser_neg_lo;
+
+		if (arg & STATUS_NORMAL)
+			gen_cfg.hold_pol = regk_sser_pos;
+		else if (arg & STATUS_INVERT)
+			gen_cfg.hold_pol = regk_sser_neg;
+		break;
+	case SSP_OPOLARITY:
+		if (arg & CLOCK_NORMAL)
+			gen_cfg.out_clk_pol = regk_sser_neg;
+		else if (arg & CLOCK_INVERT)
+			gen_cfg.out_clk_pol = regk_sser_pos;
+
+		if (arg & FRAME_NORMAL)
+			frm_cfg.level = regk_sser_pos_hi;
+		else if (arg & FRAME_INVERT)
+			frm_cfg.level = regk_sser_neg_lo;
+
+		if (arg & STATUS_NORMAL)
+			gen_cfg.hold_pol = regk_sser_pos;
+		else if (arg & STATUS_INVERT)
+			gen_cfg.hold_pol = regk_sser_neg;
+		break;
+	case SSP_SPI:
+		rec_cfg.fifo_thr = regk_sser_inf;
+		rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_msbfirst;
+		rec_cfg.sample_size = tr_cfg.sample_size = 7;
+		frm_cfg.frame_pin_use = regk_sser_frm;
+		frm_cfg.type = regk_sser_level;
+		frm_cfg.tr_delay = 1;
+		frm_cfg.level = regk_sser_neg_lo;
+		if (arg & SPI_SLAVE)
+		{
+			rec_cfg.clk_pol = regk_sser_neg;
+			gen_cfg.clk_dir = regk_sser_in;
+			port->input = 1;
+			port->output = 0;
+		}
+		else
+		{
+			gen_cfg.out_clk_pol = regk_sser_pos;
+			port->input = 0;
+			port->output = 1;
+			gen_cfg.clk_dir = regk_sser_out;
+		}
+		break;
+	case SSP_INBUFCHUNK:
+		break;
+	default:
+		return_val = -1;
+	}
+
+
+	if (port->started)
+	{
+		tr_cfg.tr_en = port->output;
+		rec_cfg.rec_en = port->input;
+	}
+
+	REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
+	REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
+	REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg);
+	REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask);
+	REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg);
+
+	spin_unlock_irq(&port->lock);
+	return return_val;
+}
+
+static ssize_t sync_serial_write(struct file * file, const char * buf,
+                                 size_t count, loff_t *ppos)
+{
+	int dev = MINOR(file->f_dentry->d_inode->i_rdev);
+	DECLARE_WAITQUEUE(wait, current);
+	sync_port *port;
+	unsigned long c, c1;
+	unsigned long free_outp;
+	unsigned long outp;
+	unsigned long out_buffer;
+	unsigned long flags;
+
+	if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
+	{
+		DEBUG(printk("Invalid minor %d\n", dev));
+		return -ENODEV;
+	}
+	port = &ports[dev];
+
+	DEBUGWRITE(printk("W d%d c %lu (%d/%d)\n", port->port_nbr, count, port->out_count, OUT_BUFFER_SIZE));
+	/* Space to end of buffer */
+	/*
+	 * out_buffer <c1>012345<-   c    ->OUT_BUFFER_SIZE
+	 *            outp^    +out_count
+	                        ^free_outp
+	 * out_buffer 45<-     c      ->0123OUT_BUFFER_SIZE
+	 *             +out_count   outp^
+	 *              free_outp
+	 *
+	 */
+
+	/* Read variables that may be updated by interrupts */
+	spin_lock_irqsave(&port->lock, flags);
+	count = count > OUT_BUFFER_SIZE - port->out_count ? OUT_BUFFER_SIZE  - port->out_count : count;
+	outp = (unsigned long)port->outp;
+	free_outp = outp + port->out_count;
+	spin_unlock_irqrestore(&port->lock, flags);
+	out_buffer = (unsigned long)port->out_buffer;
+
+	/* Find out where and how much to write */
+	if (free_outp >= out_buffer + OUT_BUFFER_SIZE)
+		free_outp -= OUT_BUFFER_SIZE;
+	if (free_outp >= outp)
+		c = out_buffer + OUT_BUFFER_SIZE - free_outp;
+	else
+		c = outp - free_outp;
+	if (c > count)
+		c = count;
+
+//	DEBUGWRITE(printk("w op %08lX fop %08lX c %lu\n", outp, free_outp, c));
+	if (copy_from_user((void*)free_outp, buf, c))
+		return -EFAULT;
+
+	if (c != count) {
+		buf += c;
+		c1 = count - c;
+		DEBUGWRITE(printk("w2 fi %lu c %lu c1 %lu\n", free_outp-out_buffer, c, c1));
+		if (copy_from_user((void*)out_buffer, buf, c1))
+			return -EFAULT;
+	}
+	spin_lock_irqsave(&port->lock, flags);
+	port->out_count += count;
+	spin_unlock_irqrestore(&port->lock, flags);
+
+	/* Make sure transmitter/receiver is running */
+	if (!port->started)
+	{
+		reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg);
+		reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg);
+		reg_sser_rw_rec_cfg rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg);
+		cfg.en = regk_sser_yes;
+		tr_cfg.tr_en = port->output;
+		rec_cfg.rec_en = port->input;
+		REG_WR(sser, port->regi_sser, rw_cfg, cfg);
+		REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
+		REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
+		port->started = 1;
+	}
+
+	if (file->f_flags & O_NONBLOCK)	{
+		spin_lock_irqsave(&port->lock, flags);
+		if (!port->tr_running) {
+			if (!port->use_dma) {
+				reg_sser_rw_intr_mask intr_mask;
+				intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask);
+				/* Start sender by writing data */
+				send_word(port);
+				/* and enable transmitter ready IRQ */
+				intr_mask.trdy = 1;
+				REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask);
+			} else {
+				start_dma(port, (unsigned char* volatile )port->outp, c);
+			}
+		}
+		spin_unlock_irqrestore(&port->lock, flags);
+		DEBUGWRITE(printk("w d%d c %lu NB\n",
+				  port->port_nbr, count));
+		return count;
+	}
+
+	/* Sleep until all sent */
+
+	add_wait_queue(&port->out_wait_q, &wait);
+	set_current_state(TASK_INTERRUPTIBLE);
+	spin_lock_irqsave(&port->lock, flags);
+	if (!port->tr_running) {
+		if (!port->use_dma) {
+			reg_sser_rw_intr_mask intr_mask;
+			intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask);
+			/* Start sender by writing data */
+			send_word(port);
+			/* and enable transmitter ready IRQ */
+			intr_mask.trdy = 1;
+			REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask);
+		} else {
+			start_dma(port, port->outp, c);
+		}
+	}
+	spin_unlock_irqrestore(&port->lock, flags);
+	schedule();
+	set_current_state(TASK_RUNNING);
+	remove_wait_queue(&port->out_wait_q, &wait);
+	if (signal_pending(current))
+	{
+		return -EINTR;
+	}
+	DEBUGWRITE(printk("w d%d c %lu\n", port->port_nbr, count));
+	return count;
+}
+
+static ssize_t sync_serial_read(struct file * file, char * buf,
+				size_t count, loff_t *ppos)
+{
+	int dev = MINOR(file->f_dentry->d_inode->i_rdev);
+	int avail;
+	sync_port *port;
+	unsigned char* start;
+	unsigned char* end;
+	unsigned long flags;
+
+	if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
+	{
+		DEBUG(printk("Invalid minor %d\n", dev));
+		return -ENODEV;
+	}
+	port = &ports[dev];
+
+	DEBUGREAD(printk("R%d c %d ri %lu wi %lu /%lu\n", dev, count, port->readp - port->flip, port->writep - port->flip, port->in_buffer_size));
+
+	if (!port->started)
+	{
+		reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg);
+		reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg);
+		reg_sser_rw_rec_cfg rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg);
+		cfg.en = regk_sser_yes;
+		tr_cfg.tr_en = regk_sser_yes;
+		rec_cfg.rec_en = regk_sser_yes;
+		REG_WR(sser, port->regi_sser, rw_cfg, cfg);
+		REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
+		REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
+		port->started = 1;
+	}
+
+
+	/* Calculate number of available bytes */
+	/* Save pointers to avoid that they are modified by interrupt */
+	spin_lock_irqsave(&port->lock, flags);
+	start = (unsigned char*)port->readp; /* cast away volatile */
+	end = (unsigned char*)port->writep;  /* cast away volatile */
+	spin_unlock_irqrestore(&port->lock, flags);
+	while ((start == end) && !port->full) /* No data */
+	{
+		if (file->f_flags & O_NONBLOCK)
+		{
+			return -EAGAIN;
+		}
+
+		interruptible_sleep_on(&port->in_wait_q);
+		if (signal_pending(current))
+		{
+			return -EINTR;
+		}
+		spin_lock_irqsave(&port->lock, flags);
+		start = (unsigned char*)port->readp; /* cast away volatile */
+		end = (unsigned char*)port->writep;  /* cast away volatile */
+		spin_unlock_irqrestore(&port->lock, flags);
+	}
+
+	/* Lazy read, never return wrapped data. */
+	if (port->full)
+		avail = port->in_buffer_size;
+	else if (end > start)
+		avail = end - start;
+	else
+		avail = port->flip + port->in_buffer_size - start;
+
+	count = count > avail ? avail : count;
+	if (copy_to_user(buf, start, count))
+		return -EFAULT;
+	/* Disable interrupts while updating readp */
+	spin_lock_irqsave(&port->lock, flags);
+	port->readp += count;
+	if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */
+		port->readp = port->flip;
+	port->full = 0;
+	spin_unlock_irqrestore(&port->lock, flags);
+	DEBUGREAD(printk("r %d\n", count));
+	return count;
+}
+
+static void send_word(sync_port* port)
+{
+	reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg);
+	reg_sser_rw_tr_data tr_data =  {0};
+
+	switch(tr_cfg.sample_size)
+	{
+	 case 8:
+		 port->out_count--;
+		 tr_data.data = *port->outp++;
+		 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
+		 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
+			 port->outp = port->out_buffer;
+		 break;
+	 case 12:
+	 {
+		int data = (*port->outp++) << 8;
+		data |= *port->outp++;
+		port->out_count-=2;
+		tr_data.data = data;
+		REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
+		if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
+			port->outp = port->out_buffer;
+	}
+	break;
+	case 16:
+		port->out_count-=2;
+		tr_data.data = *(unsigned short *)port->outp;
+		REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
+		port->outp+=2;
+		if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
+			port->outp = port->out_buffer;
+		break;
+	case 24:
+		port->out_count-=3;
+		tr_data.data = *(unsigned short *)port->outp;
+		REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
+		port->outp+=2;
+		tr_data.data = *port->outp++;
+		REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
+		if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
+			port->outp = port->out_buffer;
+		break;
+	case 32:
+		port->out_count-=4;
+		tr_data.data = *(unsigned short *)port->outp;
+		REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
+		port->outp+=2;
+		tr_data.data = *(unsigned short *)port->outp;
+		REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
+		port->outp+=2;
+		if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
+			port->outp = port->out_buffer;
+		break;
+	}
+}
+
+
+static void start_dma(struct sync_port* port, const char* data, int count)
+{
+	port->tr_running = 1;
+	port->out_descr.buf = (char*)virt_to_phys((char*)data);
+	port->out_descr.after = port->out_descr.buf + count;
+	port->out_descr.eol = port->out_descr.intr = 1;
+
+	port->out_context.saved_data = (dma_descr_data*)virt_to_phys(&port->out_descr);
+	port->out_context.saved_data_buf = port->out_descr.buf;
+
+	DMA_START_CONTEXT(port->regi_dmaout, virt_to_phys((char*)&port->out_context));
+	DEBUGTXINT(printk("dma %08lX c %d\n", (unsigned long)data, count));
+}
+
+static void start_dma_in(sync_port* port)
+{
+	int i;
+	char* buf;
+	port->writep = port->flip;
+
+	if (port->writep > port->flip + port->in_buffer_size)
+	{
+		panic("Offset too large in sync serial driver\n");
+		return;
+	}
+	buf = (char*)virt_to_phys(port->in_buffer);
+	for (i = 0; i < NUM_IN_DESCR; i++) {
+		port->in_descr[i].buf = buf;
+		port->in_descr[i].after = buf + port->inbufchunk;
+		port->in_descr[i].intr = 1;
+		port->in_descr[i].next = (dma_descr_data*)virt_to_phys(&port->in_descr[i+1]);
+		port->in_descr[i].buf = buf;
+		buf += port->inbufchunk;
+	}
+	/* Link the last descriptor to the first */
+	port->in_descr[i-1].next = (dma_descr_data*)virt_to_phys(&port->in_descr[0]);
+	port->in_descr[i-1].eol = regk_sser_yes;
+	port->next_rx_desc = &port->in_descr[0];
+	port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR - 1];
+	port->in_context.saved_data = (dma_descr_data*)virt_to_phys(&port->in_descr[0]);
+	port->in_context.saved_data_buf = port->in_descr[0].buf;
+	DMA_START_CONTEXT(port->regi_dmain, virt_to_phys(&port->in_context));
+}
+
+#ifdef SYNC_SER_DMA
+static irqreturn_t tr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+	reg_dma_r_masked_intr masked;
+	reg_dma_rw_ack_intr ack_intr = {.data = regk_dma_yes};
+	int i;
+	struct dma_descr_data *descr;
+	unsigned int sentl;
+	int found = 0;
+
+	for (i = 0; i < NUMBER_OF_PORTS; i++)
+	{
+		sync_port *port = &ports[i];
+		if (!port->enabled  || !port->use_dma )
+			continue;
+
+		masked = REG_RD(dma, port->regi_dmaout, r_masked_intr);
+
+		if (masked.data) /* IRQ active for the port? */
+		{
+			found = 1;
+			/* Clear IRQ */
+			REG_WR(dma, port->regi_dmaout, rw_ack_intr, ack_intr);
+			descr = &port->out_descr;
+			sentl = descr->after - descr->buf;
+			port->out_count -= sentl;
+			port->outp += sentl;
+			if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
+				port->outp = port->out_buffer;
+			if (port->out_count)  {
+				int c;
+				c = port->out_buffer + OUT_BUFFER_SIZE - port->outp;
+				if (c > port->out_count)
+					c = port->out_count;
+				DEBUGTXINT(printk("tx_int DMAWRITE %i %i\n", sentl, c));
+				start_dma(port, port->outp, c);
+			} else  {
+				DEBUGTXINT(printk("tx_int DMA stop %i\n", sentl));
+				port->tr_running = 0;
+			}
+			wake_up_interruptible(&port->out_wait_q); /* wake up the waiting process */
+		}
+	}
+	return IRQ_RETVAL(found);
+} /* tr_interrupt */
+
+static irqreturn_t rx_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+	reg_dma_r_masked_intr masked;
+	reg_dma_rw_ack_intr ack_intr = {.data = regk_dma_yes};
+
+	int i;
+	int found = 0;
+
+	for (i = 0; i < NUMBER_OF_PORTS; i++)
+	{
+		sync_port *port = &ports[i];
+
+		if (!port->enabled || !port->use_dma )
+			continue;
+
+		masked = REG_RD(dma, port->regi_dmain, r_masked_intr);
+
+		if (masked.data) /* Descriptor interrupt */
+		{
+			found = 1;
+			while (REG_RD(dma, port->regi_dmain, rw_data) !=
+			       virt_to_phys(port->next_rx_desc)) {
+
+				if (port->writep + port->inbufchunk > port->flip + port->in_buffer_size) {
+					int first_size = port->flip + port->in_buffer_size - port->writep;
+					memcpy((char*)port->writep, phys_to_virt((unsigned)port->next_rx_desc->buf), first_size);
+					memcpy(port->flip, phys_to_virt((unsigned)port->next_rx_desc->buf+first_size), port->inbufchunk - first_size);
+					port->writep = port->flip + port->inbufchunk - first_size;
+				} else {
+					memcpy((char*)port->writep,
+					       phys_to_virt((unsigned)port->next_rx_desc->buf),
+					       port->inbufchunk);
+					port->writep += port->inbufchunk;
+					if (port->writep >= port->flip + port->in_buffer_size)
+						port->writep = port->flip;
+				}
+                                if (port->writep == port->readp)
+                                {
+				  port->full = 1;
+                                }
+
+				port->next_rx_desc->eol = 0;
+				port->prev_rx_desc->eol = 1;
+				port->prev_rx_desc = phys_to_virt((unsigned)port->next_rx_desc);
+				port->next_rx_desc = phys_to_virt((unsigned)port->next_rx_desc->next);
+				wake_up_interruptible(&port->in_wait_q); /* wake up the waiting process */
+				DMA_CONTINUE(port->regi_dmain);
+				REG_WR(dma, port->regi_dmain, rw_ack_intr, ack_intr);
+
+			}
+		}
+	}
+	return IRQ_RETVAL(found);
+} /* rx_interrupt */
+#endif /* SYNC_SER_DMA */
+
+#ifdef SYNC_SER_MANUAL
+static irqreturn_t manual_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+	int i;
+	int found = 0;
+	reg_sser_r_masked_intr masked;
+
+	for (i = 0; i < NUMBER_OF_PORTS; i++)
+	{
+		sync_port* port = &ports[i];
+
+		if (!port->enabled || port->use_dma)
+		{
+			continue;
+		}
+
+		masked = REG_RD(sser, port->regi_sser, r_masked_intr);
+		if (masked.rdav)	/* Data received? */
+		{
+			reg_sser_rw_rec_cfg rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg);
+			reg_sser_r_rec_data data = REG_RD(sser, port->regi_sser, r_rec_data);
+			found = 1;
+			/* Read data */
+			switch(rec_cfg.sample_size)
+			{
+			case 8:
+				*port->writep++ = data.data & 0xff;
+				break;
+			case 12:
+				*port->writep = (data.data & 0x0ff0) >> 4;
+				*(port->writep + 1) = data.data & 0x0f;
+				port->writep+=2;
+				break;
+			case 16:
+				*(unsigned short*)port->writep = data.data;
+				port->writep+=2;
+				break;
+			case 24:
+				*(unsigned int*)port->writep = data.data;
+				port->writep+=3;
+				break;
+			case 32:
+				*(unsigned int*)port->writep = data.data;
+				port->writep+=4;
+				break;
+			}
+
+			if (port->writep >= port->flip + port->in_buffer_size) /* Wrap? */
+				port->writep = port->flip;
+			if (port->writep == port->readp) {
+				/* receive buffer overrun, discard oldest data
+				 */
+				port->readp++;
+				if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */
+					port->readp = port->flip;
+			}
+			if (sync_data_avail(port) >= port->inbufchunk)
+				wake_up_interruptible(&port->in_wait_q); /* Wake up application */
+		}
+
+		if (masked.trdy) /* Transmitter ready? */
+		{
+			found = 1;
+			if (port->out_count > 0) /* More data to send */
+				send_word(port);
+			else /* transmission finished */
+			{
+				reg_sser_rw_intr_mask intr_mask;
+				intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask);
+				intr_mask.trdy = 0;
+				REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask);
+				wake_up_interruptible(&port->out_wait_q); /* Wake up application */
+			}
+		}
+	}
+	return IRQ_RETVAL(found);
+}
+#endif
+
+module_init(etrax_sync_serial_init);
diff --git a/arch/cris/arch-v32/kernel/Makefile b/arch/cris/arch-v32/kernel/Makefile
new file mode 100644
index 00000000000..5d5b613cde8
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/Makefile
@@ -0,0 +1,21 @@
+# $Id: Makefile,v 1.11 2004/12/17 10:16:13 starvik Exp $
+#
+# Makefile for the linux kernel.
+#
+
+extra-y	:= head.o
+
+
+obj-y   := entry.o traps.o irq.o debugport.o dma.o pinmux.o \
+	   process.o ptrace.o setup.o signal.o traps.o time.o \
+	   arbiter.o io.o
+
+obj-$(CONFIG_ETRAXFS_SIM) += vcs_hook.o
+
+obj-$(CONFIG_SMP) += smp.o
+obj-$(CONFIG_ETRAX_KGDB) += kgdb.o kgdb_asm.o
+obj-$(CONFIG_ETRAX_FAST_TIMER) += fasttimer.o
+obj-$(CONFIG_MODULES)    += crisksyms.o
+
+clean:
+
diff --git a/arch/cris/arch-v32/kernel/arbiter.c b/arch/cris/arch-v32/kernel/arbiter.c
new file mode 100644
index 00000000000..3870d2fd516
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/arbiter.c
@@ -0,0 +1,297 @@
+/*
+ * Memory arbiter functions. Allocates bandwith through the
+ * arbiter and sets up arbiter breakpoints.
+ *
+ * The algorithm first assigns slots to the clients that has specified
+ * bandwith (e.g. ethernet) and then the remaining slots are divided
+ * on all the active clients.
+ *
+ * Copyright (c) 2004, 2005 Axis Communications AB.
+ */
+
+#include <linux/config.h>
+#include <asm/arch/hwregs/reg_map.h>
+#include <asm/arch/hwregs/reg_rdwr.h>
+#include <asm/arch/hwregs/marb_defs.h>
+#include <asm/arch/arbiter.h>
+#include <asm/arch/hwregs/intr_vect.h>
+#include <linux/interrupt.h>
+#include <linux/signal.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <asm/io.h>
+
+struct crisv32_watch_entry
+{
+  unsigned long instance;
+  watch_callback* cb;
+  unsigned long start;
+  unsigned long end;
+  int used;
+};
+
+#define NUMBER_OF_BP 4
+#define NBR_OF_CLIENTS 14
+#define NBR_OF_SLOTS 64
+#define SDRAM_BANDWIDTH 100000000 /* Some kind of expected value */
+#define INTMEM_BANDWIDTH 400000000
+#define NBR_OF_REGIONS 2
+
+static struct crisv32_watch_entry watches[NUMBER_OF_BP] =
+{
+  {regi_marb_bp0},
+  {regi_marb_bp1},
+  {regi_marb_bp2},
+  {regi_marb_bp3}
+};
+
+static int requested_slots[NBR_OF_REGIONS][NBR_OF_CLIENTS];
+static int active_clients[NBR_OF_REGIONS][NBR_OF_CLIENTS];
+static int max_bandwidth[NBR_OF_REGIONS] = {SDRAM_BANDWIDTH, INTMEM_BANDWIDTH};
+
+DEFINE_SPINLOCK(arbiter_lock);
+
+static irqreturn_t
+crisv32_arbiter_irq(int irq, void* dev_id, struct pt_regs* regs);
+
+static void crisv32_arbiter_config(int region)
+{
+	int slot;
+	int client;
+	int interval = 0;
+	int val[NBR_OF_SLOTS];
+
+	for (slot = 0; slot < NBR_OF_SLOTS; slot++)
+	    val[slot] = NBR_OF_CLIENTS + 1;
+
+	for (client = 0; client < NBR_OF_CLIENTS; client++)
+	{
+	    int pos;
+	    if (!requested_slots[region][client])
+	       continue;
+	    interval = NBR_OF_SLOTS / requested_slots[region][client];
+	    pos = 0;
+	    while (pos < NBR_OF_SLOTS)
+	    {
+		if (val[pos] != NBR_OF_CLIENTS + 1)
+		   pos++;
+		else
+		{
+			val[pos] = client;
+			pos += interval;
+		}
+	    }
+	}
+
+	client = 0;
+	for (slot = 0; slot < NBR_OF_SLOTS; slot++)
+	{
+		if (val[slot] == NBR_OF_CLIENTS + 1)
+		{
+			int first = client;
+			while(!active_clients[region][client]) {
+				client = (client + 1) % NBR_OF_CLIENTS;
+				if (client == first)
+				   break;
+			}
+			val[slot] = client;
+			client = (client + 1) % NBR_OF_CLIENTS;
+		}
+		if (region == EXT_REGION)
+		   REG_WR_INT_VECT(marb, regi_marb, rw_ext_slots, slot, val[slot]);
+		else if (region == INT_REGION)
+		   REG_WR_INT_VECT(marb, regi_marb, rw_int_slots, slot, val[slot]);
+	}
+}
+
+extern char _stext, _etext;
+
+static void crisv32_arbiter_init(void)
+{
+	static int initialized = 0;
+
+	if (initialized)
+		return;
+
+	initialized = 1;
+
+	/* CPU caches are active. */
+	active_clients[EXT_REGION][10] = active_clients[EXT_REGION][11] = 1;
+        crisv32_arbiter_config(EXT_REGION);
+        crisv32_arbiter_config(INT_REGION);
+
+	if (request_irq(MEMARB_INTR_VECT, crisv32_arbiter_irq, SA_INTERRUPT,
+                        "arbiter", NULL))
+		printk(KERN_ERR "Couldn't allocate arbiter IRQ\n");
+
+#ifndef CONFIG_ETRAX_KGDB
+        /* Global watch for writes to kernel text segment. */
+        crisv32_arbiter_watch(virt_to_phys(&_stext), &_etext - &_stext,
+                              arbiter_all_clients, arbiter_all_write, NULL);
+#endif
+}
+
+
+
+int crisv32_arbiter_allocate_bandwith(int client, int region,
+	                              unsigned long bandwidth)
+{
+	int i;
+	int total_assigned = 0;
+	int total_clients = 0;
+	int req;
+
+	crisv32_arbiter_init();
+
+	for (i = 0; i < NBR_OF_CLIENTS; i++)
+	{
+		total_assigned += requested_slots[region][i];
+		total_clients += active_clients[region][i];
+	}
+	req = NBR_OF_SLOTS / (max_bandwidth[region] / bandwidth);
+
+	if (total_assigned + total_clients + req + 1 > NBR_OF_SLOTS)
+	   return -ENOMEM;
+
+	active_clients[region][client] = 1;
+	requested_slots[region][client] = req;
+	crisv32_arbiter_config(region);
+
+	return 0;
+}
+
+int crisv32_arbiter_watch(unsigned long start, unsigned long size,
+                          unsigned long clients, unsigned long accesses,
+                          watch_callback* cb)
+{
+	int i;
+
+	crisv32_arbiter_init();
+
+	if (start > 0x80000000) {
+		printk("Arbiter: %lX doesn't look like a physical address", start);
+		return -EFAULT;
+	}
+
+	spin_lock(&arbiter_lock);
+
+	for (i = 0; i < NUMBER_OF_BP; i++) {
+		if (!watches[i].used) {
+			reg_marb_rw_intr_mask intr_mask = REG_RD(marb, regi_marb, rw_intr_mask);
+
+			watches[i].used = 1;
+			watches[i].start = start;
+			watches[i].end = start + size;
+			watches[i].cb = cb;
+
+			REG_WR_INT(marb_bp, watches[i].instance, rw_first_addr, watches[i].start);
+			REG_WR_INT(marb_bp, watches[i].instance, rw_last_addr, watches[i].end);
+			REG_WR_INT(marb_bp, watches[i].instance, rw_op, accesses);
+			REG_WR_INT(marb_bp, watches[i].instance, rw_clients, clients);
+
+			if (i == 0)
+				intr_mask.bp0 = regk_marb_yes;
+			else if (i == 1)
+				intr_mask.bp1 = regk_marb_yes;
+			else if (i == 2)
+				intr_mask.bp2 = regk_marb_yes;
+			else if (i == 3)
+				intr_mask.bp3 = regk_marb_yes;
+
+			REG_WR(marb, regi_marb, rw_intr_mask, intr_mask);
+			spin_unlock(&arbiter_lock);
+
+			return i;
+		}
+	}
+	spin_unlock(&arbiter_lock);
+	return -ENOMEM;
+}
+
+int crisv32_arbiter_unwatch(int id)
+{
+	reg_marb_rw_intr_mask intr_mask = REG_RD(marb, regi_marb, rw_intr_mask);
+
+	crisv32_arbiter_init();
+
+	spin_lock(&arbiter_lock);
+
+	if ((id < 0) || (id >= NUMBER_OF_BP) || (!watches[id].used)) {
+		spin_unlock(&arbiter_lock);
+		return -EINVAL;
+	}
+
+	memset(&watches[id], 0, sizeof(struct crisv32_watch_entry));
+
+	if (id == 0)
+		intr_mask.bp0 = regk_marb_no;
+	else if (id == 1)
+		intr_mask.bp2 = regk_marb_no;
+	else if (id == 2)
+		intr_mask.bp2 = regk_marb_no;
+	else if (id == 3)
+		intr_mask.bp3 = regk_marb_no;
+
+	REG_WR(marb, regi_marb, rw_intr_mask, intr_mask);
+
+	spin_unlock(&arbiter_lock);
+	return 0;
+}
+
+extern void show_registers(struct pt_regs *regs);
+
+static irqreturn_t
+crisv32_arbiter_irq(int irq, void* dev_id, struct pt_regs* regs)
+{
+	reg_marb_r_masked_intr masked_intr = REG_RD(marb, regi_marb, r_masked_intr);
+	reg_marb_bp_r_brk_clients r_clients;
+	reg_marb_bp_r_brk_addr r_addr;
+	reg_marb_bp_r_brk_op r_op;
+	reg_marb_bp_r_brk_first_client r_first;
+	reg_marb_bp_r_brk_size r_size;
+	reg_marb_bp_rw_ack ack = {0};
+	reg_marb_rw_ack_intr ack_intr = {.bp0=1,.bp1=1,.bp2=1,.bp3=1};
+	struct crisv32_watch_entry* watch;
+
+	if (masked_intr.bp0) {
+		watch = &watches[0];
+		ack_intr.bp0 = regk_marb_yes;
+	} else if (masked_intr.bp1) {
+		watch = &watches[1];
+		ack_intr.bp1 = regk_marb_yes;
+	} else if (masked_intr.bp2) {
+		watch = &watches[2];
+		ack_intr.bp2 = regk_marb_yes;
+	} else if (masked_intr.bp3) {
+		watch = &watches[3];
+		ack_intr.bp3 = regk_marb_yes;
+	} else {
+		return IRQ_NONE;
+	}
+
+	/* Retrieve all useful information and print it. */
+	r_clients = REG_RD(marb_bp, watch->instance, r_brk_clients);
+	r_addr = REG_RD(marb_bp, watch->instance, r_brk_addr);
+	r_op = REG_RD(marb_bp, watch->instance, r_brk_op);
+	r_first = REG_RD(marb_bp, watch->instance, r_brk_first_client);
+	r_size = REG_RD(marb_bp, watch->instance, r_brk_size);
+
+	printk("Arbiter IRQ\n");
+	printk("Clients %X addr %X op %X first %X size %X\n",
+	       REG_TYPE_CONV(int, reg_marb_bp_r_brk_clients, r_clients),
+	       REG_TYPE_CONV(int, reg_marb_bp_r_brk_addr, r_addr),
+	       REG_TYPE_CONV(int, reg_marb_bp_r_brk_op, r_op),
+	       REG_TYPE_CONV(int, reg_marb_bp_r_brk_first_client, r_first),
+	       REG_TYPE_CONV(int, reg_marb_bp_r_brk_size, r_size));
+
+	REG_WR(marb_bp, watch->instance, rw_ack, ack);
+	REG_WR(marb, regi_marb, rw_ack_intr, ack_intr);
+
+	printk("IRQ occured at %lX\n", regs->erp);
+
+	if (watch->cb)
+		watch->cb();
+
+
+	return IRQ_HANDLED;
+}
diff --git a/arch/cris/arch-v32/kernel/asm-offsets.c b/arch/cris/arch-v32/kernel/asm-offsets.c
new file mode 100644
index 00000000000..15b3d93a049
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/asm-offsets.c
@@ -0,0 +1,49 @@
+#include <linux/sched.h>
+#include <asm/thread_info.h>
+
+/*
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed to extract
+ * and format the required data.
+ */
+
+#define DEFINE(sym, val) \
+        asm volatile("\n->" #sym " %0 " #val : : "i" (val))
+
+#define BLANK() asm volatile("\n->" : : )
+
+int main(void)
+{
+#define ENTRY(entry) DEFINE(PT_ ## entry, offsetof(struct pt_regs, entry))
+	ENTRY(orig_r10);
+	ENTRY(r13);
+	ENTRY(r12);
+	ENTRY(r11);
+        ENTRY(r10);
+        ENTRY(r9);
+	ENTRY(acr);
+	ENTRY(srs);
+        ENTRY(mof);
+        ENTRY(ccs);
+        ENTRY(srp);
+	BLANK();
+#undef ENTRY
+#define ENTRY(entry) DEFINE(TI_ ## entry, offsetof(struct thread_info, entry))
+        ENTRY(task);
+        ENTRY(flags);
+        ENTRY(preempt_count);
+        BLANK();
+#undef ENTRY
+#define ENTRY(entry) DEFINE(THREAD_ ## entry, offsetof(struct thread_struct, entry))
+	ENTRY(ksp);
+        ENTRY(usp);
+        ENTRY(ccs);
+        BLANK();
+#undef ENTRY
+#define ENTRY(entry) DEFINE(TASK_ ## entry, offsetof(struct task_struct, entry))
+        ENTRY(pid);
+        BLANK();
+        DEFINE(LCLONE_VM, CLONE_VM);
+        DEFINE(LCLONE_UNTRACED, CLONE_UNTRACED);
+        return 0;
+}
diff --git a/arch/cris/arch-v32/kernel/crisksyms.c b/arch/cris/arch-v32/kernel/crisksyms.c
new file mode 100644
index 00000000000..2c3bb9a0afe
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/crisksyms.c
@@ -0,0 +1,24 @@
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/irq.h>
+#include <asm/arch/dma.h>
+#include <asm/arch/intmem.h>
+#include <asm/arch/pinmux.h>
+
+/* Functions for allocating DMA channels */
+EXPORT_SYMBOL(crisv32_request_dma);
+EXPORT_SYMBOL(crisv32_free_dma);
+
+/* Functions for handling internal RAM */
+EXPORT_SYMBOL(crisv32_intmem_alloc);
+EXPORT_SYMBOL(crisv32_intmem_free);
+EXPORT_SYMBOL(crisv32_intmem_phys_to_virt);
+EXPORT_SYMBOL(crisv32_intmem_virt_to_phys);
+
+/* Functions for handling pinmux */
+EXPORT_SYMBOL(crisv32_pinmux_alloc);
+EXPORT_SYMBOL(crisv32_pinmux_dealloc);
+
+/* Functions masking/unmasking interrupts */
+EXPORT_SYMBOL(mask_irq);
+EXPORT_SYMBOL(unmask_irq);
diff --git a/arch/cris/arch-v32/kernel/debugport.c b/arch/cris/arch-v32/kernel/debugport.c
new file mode 100644
index 00000000000..ffc1ebf2dfe
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/debugport.c
@@ -0,0 +1,461 @@
+/*
+ * Copyright (C) 2003, Axis Communications AB.
+ */
+
+#include <linux/config.h>
+#include <linux/console.h>
+#include <linux/init.h>
+#include <linux/major.h>
+#include <linux/delay.h>
+#include <linux/tty.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/arch/hwregs/ser_defs.h>
+#include <asm/arch/hwregs/dma_defs.h>
+#include <asm/arch/pinmux.h>
+
+#include <asm/irq.h>
+#include <asm/arch/hwregs/intr_vect_defs.h>
+
+struct dbg_port
+{
+	unsigned char nbr;
+	unsigned long instance;
+	unsigned int started;
+	unsigned long baudrate;
+	unsigned char parity;
+	unsigned int bits;
+};
+
+struct dbg_port ports[] =
+{
+  {
+    0,
+    regi_ser0,
+    0,
+    115200,
+    'N',
+    8
+  },
+  {
+    1,
+    regi_ser1,
+    0,
+    115200,
+    'N',
+    8
+  },
+  {
+    2,
+    regi_ser2,
+    0,
+    115200,
+    'N',
+    8
+  },
+  {
+    3,
+    regi_ser3,
+    0,
+    115200,
+    'N',
+    8
+  }
+};
+static struct dbg_port *port =
+#if defined(CONFIG_ETRAX_DEBUG_PORT0)
+&ports[0];
+#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
+&ports[1];
+#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
+&ports[2];
+#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
+&ports[3];
+#else
+NULL;
+#endif
+
+#ifdef CONFIG_ETRAX_KGDB
+static struct dbg_port *kgdb_port =
+#if defined(CONFIG_ETRAX_KGDB_PORT0)
+&ports[0];
+#elif defined(CONFIG_ETRAX_KGDB_PORT1)
+&ports[1];
+#elif defined(CONFIG_ETRAX_KGDB_PORT2)
+&ports[2];
+#elif defined(CONFIG_ETRAX_KGDB_PORT3)
+&ports[3];
+#else
+NULL;
+#endif
+#endif
+
+#ifdef CONFIG_ETRAXFS_SIM
+extern void print_str( const char *str );
+static char buffer[1024];
+static char msg[] = "Debug: ";
+static int buffer_pos = sizeof(msg) - 1;
+#endif
+
+extern struct tty_driver *serial_driver;
+
+static void
+start_port(struct dbg_port* p)
+{
+	if (!p)
+		return;
+
+	if (p->started)
+		return;
+	p->started = 1;
+
+	if (p->nbr == 1)
+		crisv32_pinmux_alloc_fixed(pinmux_ser1);
+	else if (p->nbr == 2)
+		crisv32_pinmux_alloc_fixed(pinmux_ser2);
+	else if (p->nbr == 3)
+		crisv32_pinmux_alloc_fixed(pinmux_ser3);
+
+	/* Set up serial port registers */
+	reg_ser_rw_tr_ctrl tr_ctrl = {0};
+	reg_ser_rw_tr_dma_en tr_dma_en = {0};
+
+	reg_ser_rw_rec_ctrl rec_ctrl = {0};
+	reg_ser_rw_tr_baud_div tr_baud_div = {0};
+	reg_ser_rw_rec_baud_div rec_baud_div = {0};
+
+	tr_ctrl.base_freq = rec_ctrl.base_freq = regk_ser_f29_493;
+	tr_dma_en.en = rec_ctrl.dma_mode = regk_ser_no;
+	tr_baud_div.div = rec_baud_div.div = 29493000 / p->baudrate / 8;
+	tr_ctrl.en = rec_ctrl.en = 1;
+
+	if (p->parity == 'O')
+	{
+		tr_ctrl.par_en = regk_ser_yes;
+		tr_ctrl.par = regk_ser_odd;
+		rec_ctrl.par_en = regk_ser_yes;
+		rec_ctrl.par = regk_ser_odd;
+	}
+	else if (p->parity == 'E')
+	{
+		tr_ctrl.par_en = regk_ser_yes;
+		tr_ctrl.par = regk_ser_even;
+		rec_ctrl.par_en = regk_ser_yes;
+		rec_ctrl.par = regk_ser_odd;
+	}
+
+	if (p->bits == 7)
+	{
+		tr_ctrl.data_bits = regk_ser_bits7;
+		rec_ctrl.data_bits = regk_ser_bits7;
+	}
+
+	REG_WR (ser, p->instance, rw_tr_baud_div, tr_baud_div);
+	REG_WR (ser, p->instance, rw_rec_baud_div, rec_baud_div);
+	REG_WR (ser, p->instance, rw_tr_dma_en, tr_dma_en);
+	REG_WR (ser, p->instance, rw_tr_ctrl, tr_ctrl);
+	REG_WR (ser, p->instance, rw_rec_ctrl, rec_ctrl);
+}
+
+/* No debug */
+#ifdef CONFIG_ETRAX_DEBUG_PORT_NULL
+
+static void
+console_write(struct console *co, const char *buf, unsigned int len)
+{
+	return;
+}
+
+/* Target debug */
+#elif !defined(CONFIG_ETRAXFS_SIM)
+
+static void
+console_write_direct(struct console *co, const char *buf, unsigned int len)
+{
+	int i;
+	reg_ser_r_stat_din stat;
+	reg_ser_rw_tr_dma_en tr_dma_en, old;
+
+	/* Switch to manual mode */
+	tr_dma_en = old = REG_RD (ser, port->instance, rw_tr_dma_en);
+	if (tr_dma_en.en == regk_ser_yes) {
+		tr_dma_en.en = regk_ser_no;
+		REG_WR(ser, port->instance, rw_tr_dma_en, tr_dma_en);
+	}
+
+	/* Send data */
+	for (i = 0; i < len; i++) {
+		/* LF -> CRLF */
+		if (buf[i] == '\n') {
+			do {
+				stat = REG_RD (ser, port->instance, r_stat_din);
+			} while (!stat.tr_rdy);
+			REG_WR_INT (ser, port->instance, rw_dout, '\r');
+		}
+		/* Wait until transmitter is ready and send.*/
+		do {
+			stat = REG_RD (ser, port->instance, r_stat_din);
+		} while (!stat.tr_rdy);
+		REG_WR_INT (ser, port->instance, rw_dout, buf[i]);
+	}
+
+	/* Restore mode */
+	if (tr_dma_en.en != old.en)
+		REG_WR(ser, port->instance, rw_tr_dma_en, old);
+}
+
+static void
+console_write(struct console *co, const char *buf, unsigned int len)
+{
+	if (!port)
+		return;
+        console_write_direct(co, buf, len);
+}
+
+
+
+#else
+
+/* VCS debug */
+
+static void
+console_write(struct console *co, const char *buf, unsigned int len)
+{
+	char* pos;
+	pos = memchr(buf, '\n', len);
+	if (pos) {
+		int l = ++pos - buf;
+		memcpy(buffer + buffer_pos, buf, l);
+		memcpy(buffer, msg, sizeof(msg) - 1);
+		buffer[buffer_pos + l] = '\0';
+		print_str(buffer);
+		buffer_pos = sizeof(msg) - 1;
+		if (pos - buf != len) {
+			memcpy(buffer + buffer_pos, pos, len - l);
+			buffer_pos += len - l;
+		}
+	} else {
+		memcpy(buffer + buffer_pos, buf, len);
+		buffer_pos += len;
+	}
+}
+
+#endif
+
+int raw_printk(const char *fmt, ...)
+{
+	static char buf[1024];
+	int printed_len;
+	va_list args;
+	va_start(args, fmt);
+	printed_len = vsnprintf(buf, sizeof(buf), fmt, args);
+	va_end(args);
+	console_write(NULL, buf, strlen(buf));
+	return printed_len;
+}
+
+void
+stupid_debug(char* buf)
+{
+  console_write(NULL, buf, strlen(buf));
+}
+
+#ifdef CONFIG_ETRAX_KGDB
+/* Use polling to get a single character from the kernel debug port */
+int
+getDebugChar(void)
+{
+	reg_ser_rs_status_data stat;
+	reg_ser_rw_ack_intr ack_intr = { 0 };
+
+	do {
+		stat = REG_RD(ser, kgdb_instance, rs_status_data);
+	} while (!stat.data_avail);
+
+	/* Ack the data_avail interrupt. */
+	ack_intr.data_avail = 1;
+	REG_WR(ser, kgdb_instance, rw_ack_intr, ack_intr);
+
+	return stat.data;
+}
+
+/* Use polling to put a single character to the kernel debug port */
+void
+putDebugChar(int val)
+{
+	reg_ser_r_status_data stat;
+	do {
+		stat = REG_RD (ser, kgdb_instance, r_status_data);
+	} while (!stat.tr_ready);
+	REG_WR (ser, kgdb_instance, rw_data_out, REG_TYPE_CONV(reg_ser_rw_data_out, int, val));
+}
+#endif /* CONFIG_ETRAX_KGDB */
+
+static int __init
+console_setup(struct console *co, char *options)
+{
+	char* s;
+
+	if (options) {
+		port = &ports[co->index];
+		port->baudrate = 115200;
+		port->parity = 'N';
+		port->bits = 8;
+		port->baudrate = simple_strtoul(options, NULL, 10);
+		s = options;
+		while(*s >= '0' && *s <= '9')
+			s++;
+		if (*s) port->parity = *s++;
+		if (*s) port->bits   = *s++ - '0';
+		port->started = 0;
+		start_port(port);
+	}
+	return 0;
+}
+
+/* This is a dummy serial device that throws away anything written to it.
+ * This is used when no debug output is wanted.
+ */
+static struct tty_driver dummy_driver;
+
+static int dummy_open(struct tty_struct *tty, struct file * filp)
+{
+	return 0;
+}
+
+static void dummy_close(struct tty_struct *tty, struct file * filp)
+{
+}
+
+static int dummy_write(struct tty_struct * tty,
+                       const unsigned char *buf, int count)
+{
+	return count;
+}
+
+static int
+dummy_write_room(struct tty_struct *tty)
+{
+	return 8192;
+}
+
+void __init
+init_dummy_console(void)
+{
+	memset(&dummy_driver, 0, sizeof(struct tty_driver));
+	dummy_driver.driver_name = "serial";
+	dummy_driver.name = "ttyS";
+	dummy_driver.major = TTY_MAJOR;
+	dummy_driver.minor_start = 68;
+	dummy_driver.num = 1;       /* etrax100 has 4 serial ports */
+	dummy_driver.type = TTY_DRIVER_TYPE_SERIAL;
+	dummy_driver.subtype = SERIAL_TYPE_NORMAL;
+	dummy_driver.init_termios = tty_std_termios;
+	dummy_driver.init_termios.c_cflag =
+		B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */
+	dummy_driver.flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_NO_DEVFS;
+
+	dummy_driver.open = dummy_open;
+	dummy_driver.close = dummy_close;
+	dummy_driver.write = dummy_write;
+	dummy_driver.write_room = dummy_write_room;
+	if (tty_register_driver(&dummy_driver))
+		panic("Couldn't register dummy serial driver\n");
+}
+
+static struct tty_driver*
+crisv32_console_device(struct console* co, int *index)
+{
+	if (port)
+		*index = port->nbr;
+        return port ? serial_driver : &dummy_driver;
+}
+
+static struct console sercons = {
+	name : "ttyS",
+	write: console_write,
+	read : NULL,
+	device : crisv32_console_device,
+	unblank : NULL,
+	setup : console_setup,
+	flags : CON_PRINTBUFFER,
+	index : -1,
+	cflag : 0,
+	next : NULL
+};
+static struct console sercons0 = {
+	name : "ttyS",
+	write: console_write,
+	read : NULL,
+	device : crisv32_console_device,
+	unblank : NULL,
+	setup : console_setup,
+	flags : CON_PRINTBUFFER,
+	index : 0,
+	cflag : 0,
+	next : NULL
+};
+
+static struct console sercons1 = {
+	name : "ttyS",
+	write: console_write,
+	read : NULL,
+	device : crisv32_console_device,
+	unblank : NULL,
+	setup : console_setup,
+	flags : CON_PRINTBUFFER,
+	index : 1,
+	cflag : 0,
+	next : NULL
+};
+static struct console sercons2 = {
+	name : "ttyS",
+	write: console_write,
+	read : NULL,
+	device : crisv32_console_device,
+	unblank : NULL,
+	setup : console_setup,
+	flags : CON_PRINTBUFFER,
+	index : 2,
+	cflag : 0,
+	next : NULL
+};
+static struct console sercons3 = {
+	name : "ttyS",
+	write: console_write,
+	read : NULL,
+	device : crisv32_console_device,
+	unblank : NULL,
+	setup : console_setup,
+	flags : CON_PRINTBUFFER,
+	index : 3,
+	cflag : 0,
+	next : NULL
+};
+
+/* Register console for printk's, etc. */
+int __init
+init_etrax_debug(void)
+{
+  	static int first = 1;
+
+	if (!first) {
+		unregister_console(&sercons);
+		register_console(&sercons0);
+		register_console(&sercons1);
+		register_console(&sercons2);
+		register_console(&sercons3);
+		init_dummy_console();
+		return 0;
+	}
+	first = 0;
+        register_console(&sercons);
+        start_port(port);
+
+#ifdef CONFIG_ETRAX_KGDB
+	start_port(kgdb_port);
+#endif /* CONFIG_ETRAX_KGDB */
+	return 0;
+}
+
+__initcall(init_etrax_debug);
diff --git a/arch/cris/arch-v32/kernel/dma.c b/arch/cris/arch-v32/kernel/dma.c
new file mode 100644
index 00000000000..b92e85799b4
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/dma.c
@@ -0,0 +1,224 @@
+/* Wrapper for DMA channel allocator that starts clocks etc */
+
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <asm/dma.h>
+#include <asm/arch/hwregs/reg_map.h>
+#include <asm/arch/hwregs/reg_rdwr.h>
+#include <asm/arch/hwregs/marb_defs.h>
+#include <asm/arch/hwregs/config_defs.h>
+#include <asm/arch/hwregs/strmux_defs.h>
+#include <linux/errno.h>
+#include <asm/system.h>
+#include <asm/arch/arbiter.h>
+
+static char used_dma_channels[MAX_DMA_CHANNELS];
+static const char * used_dma_channels_users[MAX_DMA_CHANNELS];
+
+static DEFINE_SPINLOCK(dma_lock);
+
+int crisv32_request_dma(unsigned int dmanr, const char * device_id,
+                        unsigned options, unsigned int bandwidth,
+			enum dma_owner owner)
+{
+	unsigned long flags;
+	reg_config_rw_clk_ctrl clk_ctrl;
+	reg_strmux_rw_cfg strmux_cfg;
+
+        if (crisv32_arbiter_allocate_bandwith(dmanr,
+                                              options & DMA_INT_MEM ? INT_REGION : EXT_REGION,
+                                              bandwidth))
+          return -ENOMEM;
+
+	spin_lock_irqsave(&dma_lock, flags);
+
+	if (used_dma_channels[dmanr]) {
+		spin_unlock_irqrestore(&dma_lock, flags);
+		if (options & DMA_VERBOSE_ON_ERROR) {
+			printk("Failed to request DMA %i for %s, already allocated by %s\n", dmanr, device_id, used_dma_channels_users[dmanr]);
+		}
+		if (options & DMA_PANIC_ON_ERROR)
+			panic("request_dma error!");
+		return -EBUSY;
+	}
+	clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
+	strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
+
+	switch(dmanr)
+	{
+	case 0:
+	case 1:
+		clk_ctrl.dma01_eth0 = 1;
+		break;
+	case 2:
+	case 3:
+		clk_ctrl.dma23 = 1;
+		break;
+	case 4:
+	case 5:
+		clk_ctrl.dma45 = 1;
+		break;
+	case 6:
+	case 7:
+		clk_ctrl.dma67 = 1;
+		break;
+	case 8:
+	case 9:
+		clk_ctrl.dma89_strcop = 1;
+		break;
+#if MAX_DMA_CHANNELS-1 != 9
+#error Check dma.c
+#endif
+	default:
+		spin_unlock_irqrestore(&dma_lock, flags);
+		if (options & DMA_VERBOSE_ON_ERROR) {
+			printk("Failed to request DMA %i for %s, only 0-%i valid)\n", dmanr, device_id, MAX_DMA_CHANNELS-1);
+		}
+
+		if (options & DMA_PANIC_ON_ERROR)
+			panic("request_dma error!");
+		return -EINVAL;
+	}
+
+	switch(owner)
+	{
+	case dma_eth0:
+		if (dmanr == 0)
+			strmux_cfg.dma0 = regk_strmux_eth0;
+		else if (dmanr == 1)
+			strmux_cfg.dma1 = regk_strmux_eth0;
+		else
+			panic("Invalid DMA channel for eth0\n");
+		break;
+	case dma_eth1:
+		if (dmanr == 6)
+			strmux_cfg.dma6 = regk_strmux_eth1;
+		else if (dmanr == 7)
+			strmux_cfg.dma7 = regk_strmux_eth1;
+		else
+			panic("Invalid DMA channel for eth1\n");
+		break;
+	case dma_iop0:
+		if (dmanr == 2)
+			strmux_cfg.dma2 = regk_strmux_iop0;
+		else if (dmanr == 3)
+			strmux_cfg.dma3 = regk_strmux_iop0;
+		else
+			panic("Invalid DMA channel for iop0\n");
+		break;
+	case dma_iop1:
+		if (dmanr == 4)
+			strmux_cfg.dma4 = regk_strmux_iop1;
+		else if (dmanr == 5)
+			strmux_cfg.dma5 = regk_strmux_iop1;
+		else
+			panic("Invalid DMA channel for iop1\n");
+		break;
+	case dma_ser0:
+		if (dmanr == 6)
+			strmux_cfg.dma6 = regk_strmux_ser0;
+		else if (dmanr == 7)
+			strmux_cfg.dma7 = regk_strmux_ser0;
+		else
+			panic("Invalid DMA channel for ser0\n");
+		break;
+	case dma_ser1:
+		if (dmanr == 4)
+			strmux_cfg.dma4 = regk_strmux_ser1;
+		else if (dmanr == 5)
+			strmux_cfg.dma5 = regk_strmux_ser1;
+		else
+			panic("Invalid DMA channel for ser1\n");
+		break;
+	case dma_ser2:
+		if (dmanr == 2)
+			strmux_cfg.dma2 = regk_strmux_ser2;
+		else if (dmanr == 3)
+			strmux_cfg.dma3 = regk_strmux_ser2;
+		else
+			panic("Invalid DMA channel for ser2\n");
+		break;
+	case dma_ser3:
+		if (dmanr == 8)
+			strmux_cfg.dma8 = regk_strmux_ser3;
+		else if (dmanr == 9)
+			strmux_cfg.dma9 = regk_strmux_ser3;
+		else
+			panic("Invalid DMA channel for ser3\n");
+		break;
+	case dma_sser0:
+		if (dmanr == 4)
+			strmux_cfg.dma4 = regk_strmux_sser0;
+		else if (dmanr == 5)
+			strmux_cfg.dma5 = regk_strmux_sser0;
+		else
+			panic("Invalid DMA channel for sser0\n");
+		break;
+	case dma_sser1:
+		if (dmanr == 6)
+			strmux_cfg.dma6 = regk_strmux_sser1;
+		else if (dmanr == 7)
+			strmux_cfg.dma7 = regk_strmux_sser1;
+		else
+			panic("Invalid DMA channel for sser1\n");
+		break;
+	case dma_ata:
+		if (dmanr == 2)
+			strmux_cfg.dma2 = regk_strmux_ata;
+		else if (dmanr == 3)
+			strmux_cfg.dma3 = regk_strmux_ata;
+		else
+			panic("Invalid DMA channel for ata\n");
+		break;
+	case dma_strp:
+		if (dmanr == 8)
+			strmux_cfg.dma8 = regk_strmux_strcop;
+		else if (dmanr == 9)
+			strmux_cfg.dma9 = regk_strmux_strcop;
+		else
+			panic("Invalid DMA channel for strp\n");
+		break;
+	case dma_ext0:
+		if (dmanr == 6)
+			strmux_cfg.dma6 = regk_strmux_ext0;
+		else
+			panic("Invalid DMA channel for ext0\n");
+		break;
+	case dma_ext1:
+		if (dmanr == 7)
+			strmux_cfg.dma7 = regk_strmux_ext1;
+		else
+			panic("Invalid DMA channel for ext1\n");
+		break;
+	case dma_ext2:
+		if (dmanr == 2)
+			strmux_cfg.dma2 = regk_strmux_ext2;
+		else if (dmanr == 8)
+			strmux_cfg.dma8 = regk_strmux_ext2;
+		else
+			panic("Invalid DMA channel for ext2\n");
+		break;
+	case dma_ext3:
+		if (dmanr == 3)
+			strmux_cfg.dma3 = regk_strmux_ext3;
+		else if (dmanr == 9)
+			strmux_cfg.dma9 = regk_strmux_ext2;
+		else
+			panic("Invalid DMA channel for ext2\n");
+		break;
+	}
+
+	used_dma_channels[dmanr] = 1;
+	used_dma_channels_users[dmanr] = device_id;
+	REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl);
+	REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
+	spin_unlock_irqrestore(&dma_lock,flags);
+	return 0;
+}
+
+void crisv32_free_dma(unsigned int dmanr)
+{
+	spin_lock(&dma_lock);
+	used_dma_channels[dmanr] = 0;
+	spin_unlock(&dma_lock);
+}
diff --git a/arch/cris/arch-v32/kernel/entry.S b/arch/cris/arch-v32/kernel/entry.S
new file mode 100644
index 00000000000..a8ed55e5b40
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/entry.S
@@ -0,0 +1,820 @@
+/*
+ *  Copyright (C) 2000-2003 Axis Communications AB
+ *
+ *  Authors:	Bjorn Wesen (bjornw@axis.com)
+ *              Tobias Anderberg (tobiasa@axis.com), CRISv32 port.
+ *
+ * Code for the system-call and fault low-level handling routines.
+ *
+ * NOTE: This code handles signal-recognition, which happens every time
+ * after a timer-interrupt and after each system call.
+ *
+ * Stack layout in 'ret_from_system_call':
+ * 	ptrace needs to have all regs on the stack.
+ *	if the order here is changed, it needs to be
+ *	updated in fork.c:copy_process, signal.c:do_signal,
+ *	ptrace.c and ptrace.h
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/linkage.h>
+#include <linux/sys.h>
+#include <asm/unistd.h>
+#include <asm/errno.h>
+#include <asm/thread_info.h>
+#include <asm/arch/offset.h>
+
+#include <asm/arch/hwregs/asm/reg_map_asm.h>
+#include <asm/arch/hwregs/asm/intr_vect_defs_asm.h>
+
+	;; Exported functions.
+	.globl system_call
+	.globl ret_from_intr
+	.globl ret_from_fork
+	.globl resume
+	.globl multiple_interrupt
+	.globl nmi_interrupt
+	.globl spurious_interrupt
+	.globl do_sigtrap
+	.globl gdb_handle_exception
+	.globl sys_call_table
+
+	; Check if preemptive kernel scheduling should be done.
+#ifdef CONFIG_PREEMPT
+_resume_kernel:
+	di
+	; Load current task struct.
+	movs.w	-8192, $r0		; THREAD_SIZE = 8192
+	and.d	$sp, $r0
+
+	addoq	+TI_preempt_count, $r0, $acr
+	move.d	[$acr], $r10		; Preemption disabled?
+	bne	_Rexit
+	nop
+
+_need_resched:
+	addoq	+TI_flags, $r0, $acr
+	move.d	[$acr], $r10
+	btstq	TIF_NEED_RESCHED, $r10	; Check if need_resched is set.
+	bpl	_Rexit
+	nop
+
+	; Do preemptive kernel scheduling.
+	jsr	preempt_schedule_irq
+	nop
+
+	; Load new task struct.
+	movs.w	-8192, $r0		; THREAD_SIZE = 8192.
+	and.d	$sp, $r0
+
+	; One more time with new task.
+	ba	_need_resched
+	nop
+#else
+#define _resume_kernel _Rexit
+#endif
+
+	; Called at exit from fork. schedule_tail must be called to drop
+	; spinlock if CONFIG_PREEMPT.
+ret_from_fork:
+	jsr schedule_tail
+	nop
+	ba  ret_from_sys_call
+	nop
+
+ret_from_intr:
+	;; Check for resched if preemptive kernel, or if we're going back to
+	;; user-mode. This test matches the user_regs(regs) macro. Don't simply
+	;; test CCS since that doesn't necessarily reflect what mode we'll
+	;; return into.
+	addoq	+PT_ccs, $sp, $acr
+	move.d	[$acr], $r0
+	btstq	16, $r0			; User-mode flag.
+	bpl	_resume_kernel
+
+	; Note that di below is in delay slot.
+
+_resume_userspace:
+	di			; So need_resched and sigpending don't change.
+
+	movs.w	-8192, $r0		; THREAD_SIZE == 8192
+	and.d	$sp, $r0
+
+	addoq	+TI_flags, $r0, $acr	; current->work
+	move.d	[$acr], $r10
+	and.d	_TIF_WORK_MASK, $r10	; Work to be done on return?
+	bne	_work_pending
+	nop
+	ba	_Rexit
+	nop
+
+	;; The system_call is called by a BREAK instruction, which looks pretty
+	;; much like any other exception.
+	;;
+	;; System calls can't be made from interrupts but we still stack ERP
+	;; to have a complete stack frame.
+	;;
+	;; In r9 we have the wanted syscall number. Arguments come in r10,r11,r12,
+	;; r13,mof,srp
+	;;
+	;; This function looks on the _surface_ like spaghetti programming, but it's
+	;; really designed so that the fast-path does not force cache-loading of
+	;; non-used instructions. Only the non-common cases cause the outlined code
+	;; to run..
+
+system_call:
+	;; Stack-frame similar to the irq heads, which is reversed in
+	;; ret_from_sys_call.
+	subq	12, $sp		; Skip EXS, EDA.
+	move	$erp, [$sp]
+	subq	4, $sp
+	move	$srp, [$sp]
+	subq	4, $sp
+	move	$ccs, [$sp]
+	subq	4, $sp
+	ei			; Allow IRQs while handling system call
+	move	$spc, [$sp]
+	subq	4, $sp
+	move	$mof, [$sp]
+	subq	4, $sp
+	move	$srs, [$sp]
+	subq	4, $sp
+	move.d	$acr, [$sp]
+	subq	14*4, $sp	; Make room for R0-R13.
+	movem	$r13, [$sp]	; Push R0-R13
+	subq	4, $sp
+	move.d	$r10, [$sp]	; Push orig_r10.
+
+; Set S-bit when kernel debugging to keep hardware breakpoints active.
+#ifdef CONFIG_ETRAX_KGDB
+	move $ccs, $r0
+	or.d (1<<9), $r0
+	move $r0, $ccs
+#endif
+
+	movs.w	-ENOSYS, $r0
+	addoq	+PT_r10, $sp, $acr
+	move.d	$r0, [$acr]
+
+	;; Check if this process is syscall-traced.
+	movs.w	-8192, $r0	; THREAD_SIZE == 8192
+	and.d	$sp, $r0
+
+	addoq	+TI_flags, $r0, $acr
+	move.d	[$acr], $r0
+	btstq	TIF_SYSCALL_TRACE, $r0
+	bmi	_syscall_trace_entry
+	nop
+
+_syscall_traced:
+	;; Check for sanity in the requested syscall number.
+	cmpu.w	NR_syscalls, $r9
+	bhs	ret_from_sys_call
+	lslq	2, $r9		;  Multiply by 4, in the delay slot.
+
+	;; The location on the stack for the register structure is passed as a
+	;; seventh argument. Some system calls need this.
+	move.d  $sp, $r0
+	subq	4, $sp
+	move.d	$r0, [$sp]
+
+	;; The registers carrying parameters (R10-R13) are intact. The optional
+	;; fifth and sixth parameters is in MOF and SRP respectivly. Put them
+	;; back on the stack.
+	subq	4, $sp
+	move	$srp, [$sp]
+	subq	4, $sp
+	move	$mof, [$sp]
+
+	;; Actually to the system call.
+	addo.d	+sys_call_table, $r9, $acr
+	move.d	[$acr], $acr
+	jsr	$acr
+	nop
+
+	addq	3*4, $sp		; Pop the mof, srp and regs parameters.
+	addoq	+PT_r10, $sp, $acr
+	move.d	$r10, [$acr]		; Save the return value.
+
+	moveq	1, $r9			; "Parameter" to ret_from_sys_call to
+					; show it was a sys call.
+
+	;; Fall through into ret_from_sys_call to return.
+
+ret_from_sys_call:
+	;; R9 is a parameter:
+	;;  >= 1 from syscall
+	;;     0 from irq
+
+	;; Get the current task-struct pointer.
+	movs.w	-8192, $r0	; THREAD_SIZE == 8192
+	and.d	$sp, $r0
+
+	di		; Make sure need_resched and sigpending don't change.
+
+	addoq	+TI_flags, $r0, $acr
+	move.d	[$acr], $r1
+	and.d	_TIF_ALLWORK_MASK, $r1
+	bne	_syscall_exit_work
+	nop
+
+_Rexit:
+	;; This epilogue MUST match the prologues in multiple_interrupt, irq.h
+	;; and ptregs.h.
+	addq	4, $sp		; Skip orig_r10.
+	movem	[$sp+], $r13	; Registers R0-R13.
+	move.d	[$sp+], $acr
+	move	[$sp], $srs
+	addq	4, $sp
+	move	[$sp+], $mof
+	move	[$sp+], $spc
+	move	[$sp+], $ccs
+	move	[$sp+], $srp
+	move	[$sp+], $erp
+	addq    8, $sp		; Skip EXS, EDA.
+	jump	$erp
+	rfe			; Restore condition code stack in delay-slot.
+
+	;; We get here after doing a syscall if extra work might need to be done
+	;; perform syscall exit tracing if needed.
+
+_syscall_exit_work:
+	;; R0 contains current at this point and irq's are disabled.
+
+	addoq	+TI_flags, $r0, $acr
+	move.d	[$acr], $r1
+	btstq	TIF_SYSCALL_TRACE, $r1
+	bpl	_work_pending
+	nop
+	ei
+	move.d	$r9, $r1		; Preserve R9.
+	jsr	do_syscall_trace
+	nop
+	move.d	$r1, $r9
+	ba	_resume_userspace
+	nop
+
+_work_pending:
+	addoq	+TI_flags, $r0, $acr
+	move.d	[$acr], $r10
+	btstq	TIF_NEED_RESCHED, $r10	; Need resched?
+	bpl	_work_notifysig		; No, must be signal/notify.
+	nop
+
+_work_resched:
+	move.d	$r9, $r1		; Preserve R9.
+	jsr	schedule
+	nop
+	move.d	$r1, $r9
+	di
+
+	addoq	+TI_flags, $r0, $acr
+	move.d	[$acr], $r1
+	and.d	_TIF_WORK_MASK, $r1	; Ignore sycall trace counter.
+	beq	_Rexit
+	nop
+	btstq	TIF_NEED_RESCHED, $r1
+	bmi	_work_resched		; current->work.need_resched.
+	nop
+
+_work_notifysig:
+	;; Deal with pending signals and notify-resume requests.
+
+	addoq	+TI_flags, $r0, $acr
+	move.d	[$acr], $r13		; The thread_info_flags parameter.
+	move.d	$r9, $r10		; do_notify_resume syscall/irq param.
+	moveq	0, $r11			; oldset param - 0 in this case.
+	move.d	$sp, $r12		; The regs param.
+	jsr	do_notify_resume
+	nop
+
+	ba _Rexit
+	nop
+
+	;; We get here as a sidetrack when we've entered a syscall with the
+	;; trace-bit set. We need to call do_syscall_trace and then continue
+	;; with the call.
+
+_syscall_trace_entry:
+	;; PT_r10 in the frame contains -ENOSYS as required, at this point.
+
+	jsr	do_syscall_trace
+	nop
+
+	;; Now re-enter the syscall code to do the syscall itself. We need to
+	;; restore R9 here to contain the wanted syscall, and the other
+	;; parameter-bearing registers.
+	addoq	+PT_r9, $sp, $acr
+	move.d	[$acr], $r9
+	addoq	+PT_orig_r10, $sp, $acr
+	move.d	[$acr], $r10		; PT_r10 is already -ENOSYS.
+	addoq	+PT_r11, $sp, $acr
+	move.d	[$acr], $r11
+	addoq	+PT_r12, $sp, $acr
+	move.d	[$acr], $r12
+	addoq	+PT_r13, $sp, $acr
+	move.d	[$acr], $r13
+	addoq	+PT_mof, $sp, $acr
+	move	[$acr], $mof
+	addoq	+PT_srp, $sp, $acr
+	move	[$acr], $srp
+
+	ba	_syscall_traced
+	nop
+
+	;; Resume performs the actual task-switching, by switching stack
+	;; pointers. Input arguments are:
+	;;
+	;; R10 = prev
+	;; R11 = next
+	;; R12 = thread offset in task struct.
+	;;
+	;; Returns old current in R10.
+
+resume:
+	subq	4, $sp
+	move	$srp, [$sp]		; Keep old/new PC on the stack.
+	add.d	$r12, $r10		; R10 = current tasks tss.
+	addoq	+THREAD_ccs, $r10, $acr
+	move	$ccs, [$acr]		; Save IRQ enable state.
+	di
+
+	addoq	+THREAD_usp, $r10, $acr
+	move	$usp, [$acr]		; Save user-mode stackpointer.
+
+	;; See copy_thread for the reason why register R9 is saved.
+	subq	10*4, $sp
+	movem	$r9, [$sp]		; Save non-scratch registers and R9.
+
+	addoq	+THREAD_ksp, $r10, $acr
+	move.d	$sp, [$acr]		; Save kernel SP for old task.
+
+	move.d	$sp, $r10		; Return last running task in R10.
+	and.d   -8192, $r10		; Get thread_info from stackpointer.
+	addoq	+TI_task, $r10, $acr
+	move.d	[$acr], $r10		; Get task.
+	add.d	$r12, $r11		; Find the new tasks tss.
+	addoq	+THREAD_ksp, $r11, $acr
+	move.d	[$acr], $sp		; Switch to new stackframe.
+	movem	[$sp+], $r9		; Restore non-scratch registers and R9.
+
+	addoq	+THREAD_usp, $r11, $acr
+	move	[$acr], $usp		; Restore user-mode stackpointer.
+
+	addoq	+THREAD_ccs, $r11, $acr
+	move	[$acr], $ccs		; Restore IRQ enable status.
+	move.d	[$sp+], $acr
+	jump	$acr			; Restore PC.
+	nop
+
+nmi_interrupt:
+
+;; If we receive a watchdog interrupt while it is not expected, then set
+;; up a canonical frame and dump register contents before dying.
+
+	;; This prologue MUST match the one in irq.h and the struct in ptregs.h!
+	subq	12, $sp		;  Skip EXS, EDA.
+	move	$nrp, [$sp]
+	subq	4, $sp
+	move	$srp, [$sp]
+	subq	4, $sp
+	move	$ccs, [$sp]
+	subq	4, $sp
+	move	$spc, [$sp]
+	subq	4, $sp
+	move	$mof, [$sp]
+	subq	4, $sp
+	move	$srs, [$sp]
+	subq	4, $sp
+	move.d	$acr, [$sp]
+	subq	14*4, $sp		; Make room for R0-R13.
+	movem	$r13, [$sp]		; Push R0-R13.
+	subq	4, $sp
+	move.d	$r10, [$sp]		; Push orig_r10.
+	move.d  REG_ADDR(intr_vect, regi_irq, r_nmi), $r0
+	move.d  [$r0], $r0
+	btstq	REG_BIT(intr_vect, r_nmi, watchdog), $r0
+	bpl     1f
+	nop
+	jsr 	handle_watchdog_bite	; In time.c.
+        move.d	$sp, $r10		; Pointer to registers
+1:	btstq	REG_BIT(intr_vect, r_nmi, ext), $r0
+	bpl     1f
+	nop
+	jsr	handle_nmi
+	move.d	$sp, $r10		; Pointer to registers
+1:	addq    4, $sp			; Skip orig_r10
+	movem   [$sp+], $r13
+	move.d  [$sp+], $acr
+	move    [$sp], $srs
+	addq    4, $sp
+	move    [$sp+], $mof
+	move    [$sp+], $spc
+	move    [$sp+], $ccs
+	move	[$sp+], $srp
+	move	[$sp+], $nrp
+	addq    8, $sp			; Skip EXS, EDA.
+	jump    $nrp
+	rfn
+
+	.comm	cause_of_death, 4	;; Don't declare this anywhere.
+
+spurious_interrupt:
+	di
+	jump hard_reset_now
+	nop
+
+	;; This handles the case when multiple interrupts arrive at the same
+	;; time. Jump to the first set interrupt bit in a priotiry fashion. The
+	;; hardware will call the unserved interrupts after the handler
+	;; finishes.
+multiple_interrupt:
+	;; This prologue MUST match the one in irq.h and the struct in ptregs.h!
+	subq	12, $sp		; Skip EXS, EDA.
+	move	$erp, [$sp]
+	subq	4, $sp
+	move	$srp, [$sp]
+	subq	4, $sp
+	move	$ccs, [$sp]
+	subq	4, $sp
+	move	$spc, [$sp]
+	subq	4, $sp
+	move	$mof, [$sp]
+	subq	4, $sp
+	move	$srs, [$sp]
+	subq	4, $sp
+	move.d	$acr, [$sp]
+	subq	14*4, $sp	; Make room for R0-R13.
+	movem	$r13, [$sp]	; Push R0-R13.
+	subq	4, $sp
+	move.d	$r10, [$sp]	; Push orig_r10.
+
+; Set S-bit when kernel debugging to keep hardware breakpoints active.
+#ifdef CONFIG_ETRAX_KGDB
+	move $ccs, $r0
+	or.d (1<<9), $r0
+	move $r0, $ccs
+#endif
+
+	jsr	crisv32_do_multiple
+	move.d	$sp, $r10
+	jump    ret_from_intr
+	nop
+
+do_sigtrap:
+	;; Sigtraps the process that executed the BREAK instruction. Creates a
+	;; frame that Rexit expects.
+	subq	4, $sp
+	move    $eda, [$sp]
+	subq    4, $sp
+	move    $exs, [$sp]
+	subq    4, $sp
+	move	$erp, [$sp]
+	subq	4, $sp
+	move	$srp, [$sp]
+	subq	4, $sp
+	move	$ccs, [$sp]
+	subq	4, $sp
+	move	$spc, [$sp]
+	subq	4, $sp
+	move	$mof, [$sp]
+	subq	4, $sp
+	move	$srs, [$sp]
+	subq	4, $sp
+	move.d	$acr, [$sp]
+	di				; Need to disable irq's at this point.
+	subq	14*4, $sp		; Make room for r0-r13.
+	movem	$r13, [$sp]		; Push the r0-r13 registers.
+	subq	4, $sp
+	move.d	$r10, [$sp]		; Push orig_r10.
+
+	movs.w	-8192, $r9		; THREAD_SIZE == 8192
+	and.d	$sp, $r9
+
+	;; thread_info as first parameter
+	move.d  $r9, $r10
+	moveq	5, $r11			; SIGTRAP as second argument.
+	jsr	ugdb_trap_user
+	nop
+	jump	ret_from_intr		; Use the return routine for interrupts.
+	nop
+
+gdb_handle_exception:
+	subq	4, $sp
+	move.d	$r0, [$sp]
+#ifdef CONFIG_ETRAX_KGDB
+	move	$ccs, $r0		; U-flag not affected by previous insns.
+	btstq	16, $r0			; Test the U-flag.
+	bmi	_ugdb_handle_exception	; Go to user mode debugging.
+	nop				; Empty delay-slot (cannot pop R0 here).
+	ba	kgdb_handle_exception	; Go to kernel debugging.
+	move.d	[$sp+], $r0		; Restore R0 in delay slot.
+#endif
+
+_ugdb_handle_exception:
+	ba	do_sigtrap		; SIGTRAP the offending process.
+	move.d	[$sp+], $r0		; Restore R0 in delay slot.
+
+	.data
+
+	.section .rodata,"a"
+sys_call_table:
+	.long sys_restart_syscall	; 0 - old "setup()" system call, used
+					; for restarting.
+	.long sys_exit
+	.long sys_fork
+	.long sys_read
+	.long sys_write
+	.long sys_open		/* 5 */
+	.long sys_close
+	.long sys_waitpid
+	.long sys_creat
+	.long sys_link
+	.long sys_unlink	/* 10 */
+	.long sys_execve
+	.long sys_chdir
+	.long sys_time
+	.long sys_mknod
+	.long sys_chmod		/* 15 */
+	.long sys_lchown16
+	.long sys_ni_syscall	/* old break syscall holder */
+	.long sys_stat
+	.long sys_lseek
+	.long sys_getpid	/* 20 */
+	.long sys_mount
+	.long sys_oldumount
+	.long sys_setuid16
+	.long sys_getuid16
+	.long sys_stime		/* 25 */
+	.long sys_ptrace
+	.long sys_alarm
+	.long sys_fstat
+	.long sys_pause
+	.long sys_utime		/* 30 */
+	.long sys_ni_syscall	/* old stty syscall holder */
+	.long sys_ni_syscall	/* old gtty syscall holder */
+	.long sys_access
+	.long sys_nice
+	.long sys_ni_syscall	/* 35  old ftime syscall holder */
+	.long sys_sync
+	.long sys_kill
+	.long sys_rename
+	.long sys_mkdir
+	.long sys_rmdir		/* 40 */
+	.long sys_dup
+	.long sys_pipe
+	.long sys_times
+	.long sys_ni_syscall	/* old prof syscall holder */
+	.long sys_brk		/* 45 */
+	.long sys_setgid16
+	.long sys_getgid16
+	.long sys_signal
+	.long sys_geteuid16
+	.long sys_getegid16	/* 50 */
+	.long sys_acct
+	.long sys_umount	/* recycled never used phys( */
+	.long sys_ni_syscall	/* old lock syscall holder */
+	.long sys_ioctl
+	.long sys_fcntl		/* 55 */
+	.long sys_ni_syscall	/* old mpx syscall holder */
+	.long sys_setpgid
+	.long sys_ni_syscall	/* old ulimit syscall holder */
+	.long sys_ni_syscall	/* old sys_olduname holder */
+	.long sys_umask		/* 60 */
+	.long sys_chroot
+	.long sys_ustat
+	.long sys_dup2
+	.long sys_getppid
+	.long sys_getpgrp	/* 65 */
+	.long sys_setsid
+	.long sys_sigaction
+	.long sys_sgetmask
+	.long sys_ssetmask
+	.long sys_setreuid16	/* 70 */
+	.long sys_setregid16
+	.long sys_sigsuspend
+	.long sys_sigpending
+	.long sys_sethostname
+	.long sys_setrlimit	/* 75 */
+	.long sys_old_getrlimit
+	.long sys_getrusage
+	.long sys_gettimeofday
+	.long sys_settimeofday
+	.long sys_getgroups16	/* 80 */
+	.long sys_setgroups16
+	.long sys_select	/* was old_select in Linux/E100 */
+	.long sys_symlink
+	.long sys_lstat
+	.long sys_readlink	/* 85 */
+	.long sys_uselib
+	.long sys_swapon
+	.long sys_reboot
+	.long old_readdir
+	.long old_mmap		/* 90 */
+	.long sys_munmap
+	.long sys_truncate
+	.long sys_ftruncate
+	.long sys_fchmod
+	.long sys_fchown16	/* 95 */
+	.long sys_getpriority
+	.long sys_setpriority
+	.long sys_ni_syscall	/* old profil syscall holder */
+	.long sys_statfs
+	.long sys_fstatfs	/* 100 */
+	.long sys_ni_syscall	/* sys_ioperm in i386 */
+	.long sys_socketcall
+	.long sys_syslog
+	.long sys_setitimer
+	.long sys_getitimer	/* 105 */
+	.long sys_newstat
+	.long sys_newlstat
+	.long sys_newfstat
+	.long sys_ni_syscall	/* old sys_uname holder */
+	.long sys_ni_syscall	/* sys_iopl in i386 */
+	.long sys_vhangup
+	.long sys_ni_syscall	/* old "idle" system call */
+	.long sys_ni_syscall	/* vm86old in i386 */
+	.long sys_wait4
+	.long sys_swapoff	/* 115 */
+	.long sys_sysinfo
+	.long sys_ipc
+	.long sys_fsync
+	.long sys_sigreturn
+	.long sys_clone		/* 120 */
+	.long sys_setdomainname
+	.long sys_newuname
+	.long sys_ni_syscall	/* sys_modify_ldt */
+	.long sys_adjtimex
+	.long sys_mprotect	/* 125 */
+	.long sys_sigprocmask
+	.long sys_ni_syscall	/* old "create_module" */
+	.long sys_init_module
+	.long sys_delete_module
+	.long sys_ni_syscall	/* 130:	old "get_kernel_syms" */
+	.long sys_quotactl
+	.long sys_getpgid
+	.long sys_fchdir
+	.long sys_bdflush
+	.long sys_sysfs		/* 135 */
+	.long sys_personality
+	.long sys_ni_syscall	/* for afs_syscall */
+	.long sys_setfsuid16
+	.long sys_setfsgid16
+	.long sys_llseek	/* 140 */
+	.long sys_getdents
+	.long sys_select
+	.long sys_flock
+	.long sys_msync
+	.long sys_readv		/* 145 */
+	.long sys_writev
+	.long sys_getsid
+	.long sys_fdatasync
+	.long sys_sysctl
+	.long sys_mlock		/* 150 */
+	.long sys_munlock
+	.long sys_mlockall
+	.long sys_munlockall
+	.long sys_sched_setparam
+	.long sys_sched_getparam	/* 155 */
+	.long sys_sched_setscheduler
+	.long sys_sched_getscheduler
+	.long sys_sched_yield
+	.long sys_sched_get_priority_max
+	.long sys_sched_get_priority_min	/* 160 */
+	.long sys_sched_rr_get_interval
+	.long sys_nanosleep
+	.long sys_mremap
+	.long sys_setresuid16
+	.long sys_getresuid16	/* 165 */
+	.long sys_ni_syscall	/* sys_vm86 */
+	.long sys_ni_syscall	/* Old sys_query_module */
+	.long sys_poll
+	.long sys_nfsservctl
+	.long sys_setresgid16	/* 170 */
+	.long sys_getresgid16
+	.long sys_prctl
+	.long sys_rt_sigreturn
+	.long sys_rt_sigaction
+	.long sys_rt_sigprocmask	/* 175 */
+	.long sys_rt_sigpending
+	.long sys_rt_sigtimedwait
+	.long sys_rt_sigqueueinfo
+	.long sys_rt_sigsuspend
+	.long sys_pread64	/* 180 */
+	.long sys_pwrite64
+	.long sys_chown16
+	.long sys_getcwd
+	.long sys_capget
+	.long sys_capset	/* 185 */
+	.long sys_sigaltstack
+	.long sys_sendfile
+	.long sys_ni_syscall	/* streams1 */
+	.long sys_ni_syscall	/* streams2 */
+	.long sys_vfork		/* 190 */
+	.long sys_getrlimit
+	.long sys_mmap2
+	.long sys_truncate64
+	.long sys_ftruncate64
+	.long sys_stat64	/* 195 */
+	.long sys_lstat64
+	.long sys_fstat64
+	.long sys_lchown
+	.long sys_getuid
+	.long sys_getgid	/* 200 */
+	.long sys_geteuid
+	.long sys_getegid
+	.long sys_setreuid
+	.long sys_setregid
+	.long sys_getgroups	/* 205 */
+	.long sys_setgroups
+	.long sys_fchown
+	.long sys_setresuid
+	.long sys_getresuid
+	.long sys_setresgid	/* 210 */
+	.long sys_getresgid
+	.long sys_chown
+	.long sys_setuid
+	.long sys_setgid
+	.long sys_setfsuid	/* 215 */
+	.long sys_setfsgid
+	.long sys_pivot_root
+	.long sys_mincore
+	.long sys_madvise
+	.long sys_getdents64	/* 220 */
+	.long sys_fcntl64
+	.long sys_ni_syscall	/* reserved for TUX */
+	.long sys_ni_syscall
+	.long sys_gettid
+	.long sys_readahead	/* 225 */
+	.long sys_setxattr
+	.long sys_lsetxattr
+	.long sys_fsetxattr
+	.long sys_getxattr
+	.long sys_lgetxattr	/* 230 */
+	.long sys_fgetxattr
+	.long sys_listxattr
+	.long sys_llistxattr
+	.long sys_flistxattr
+	.long sys_removexattr	/* 235 */
+	.long sys_lremovexattr
+	.long sys_fremovexattr
+	.long sys_tkill
+	.long sys_sendfile64
+	.long sys_futex		/* 240 */
+	.long sys_sched_setaffinity
+	.long sys_sched_getaffinity
+	.long sys_ni_syscall	/* sys_set_thread_area */
+	.long sys_ni_syscall	/* sys_get_thread_area */
+	.long sys_io_setup	/* 245 */
+	.long sys_io_destroy
+	.long sys_io_getevents
+	.long sys_io_submit
+	.long sys_io_cancel
+	.long sys_fadvise64	/* 250 */
+	.long sys_ni_syscall
+	.long sys_exit_group
+	.long sys_lookup_dcookie
+	.long sys_epoll_create
+	.long sys_epoll_ctl	/* 255 */
+	.long sys_epoll_wait
+	.long sys_remap_file_pages
+ 	.long sys_set_tid_address
+ 	.long sys_timer_create
+ 	.long sys_timer_settime		/* 260 */
+ 	.long sys_timer_gettime
+ 	.long sys_timer_getoverrun
+ 	.long sys_timer_delete
+ 	.long sys_clock_settime
+ 	.long sys_clock_gettime		/* 265 */
+ 	.long sys_clock_getres
+ 	.long sys_clock_nanosleep
+	.long sys_statfs64
+	.long sys_fstatfs64
+	.long sys_tgkill	/* 270 */
+	.long sys_utimes
+ 	.long sys_fadvise64_64
+	.long sys_ni_syscall	/* sys_vserver */
+	.long sys_ni_syscall	/* sys_mbind */
+	.long sys_ni_syscall	/* 275 sys_get_mempolicy */
+	.long sys_ni_syscall	/* sys_set_mempolicy */
+	.long sys_mq_open
+	.long sys_mq_unlink
+	.long sys_mq_timedsend
+	.long sys_mq_timedreceive	/* 280 */
+	.long sys_mq_notify
+	.long sys_mq_getsetattr
+	.long sys_ni_syscall		/* reserved for kexec */
+	.long sys_waitid
+
+        /*
+         * NOTE!! This doesn't have to be exact - we just have
+         * to make sure we have _enough_ of the "sys_ni_syscall"
+         * entries. Don't panic if you notice that this hasn't
+         * been shrunk every time we add a new system call.
+         */
+
+	.rept NR_syscalls - (.-sys_call_table) / 4
+		.long sys_ni_syscall
+	.endr
+
diff --git a/arch/cris/arch-v32/kernel/fasttimer.c b/arch/cris/arch-v32/kernel/fasttimer.c
new file mode 100644
index 00000000000..ea2b4a97c8c
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/fasttimer.c
@@ -0,0 +1,996 @@
+/* $Id: fasttimer.c,v 1.11 2005/01/04 11:15:46 starvik Exp $
+ * linux/arch/cris/kernel/fasttimer.c
+ *
+ * Fast timers for ETRAX FS
+ * This may be useful in other OS than Linux so use 2 space indentation...
+ *
+ * $Log: fasttimer.c,v $
+ * Revision 1.11  2005/01/04 11:15:46  starvik
+ * Don't share timer IRQ.
+ *
+ * Revision 1.10  2004/12/07 09:19:38  starvik
+ * Corrected includes.
+ * Use correct interrupt macros.
+ *
+ * Revision 1.9  2004/05/14 10:18:58  starvik
+ * Export fast_timer_list
+ *
+ * Revision 1.8  2004/05/14 07:58:03  starvik
+ * Merge of changes from 2.4
+ *
+ * Revision 1.7  2003/07/10 12:06:14  starvik
+ * Return IRQ_NONE if irq wasn't handled
+ *
+ * Revision 1.6  2003/07/04 08:27:49  starvik
+ * Merge of Linux 2.5.74
+ *
+ * Revision 1.5  2003/06/05 10:16:22  johana
+ * New INTR_VECT macros.
+ *
+ * Revision 1.4  2003/06/03 08:49:45  johana
+ * Fixed typo.
+ *
+ * Revision 1.3  2003/06/02 12:51:27  johana
+ * Now compiles.
+ * Commented some include files that probably can be removed.
+ *
+ * Revision 1.2  2003/06/02 12:09:41  johana
+ * Ported to ETRAX FS using the trig interrupt instead of timer1.
+ *
+ * Revision 1.3  2002/12/12 08:26:32  starvik
+ * Don't use C-comments inside CVS comments
+ *
+ * Revision 1.2  2002/12/11 15:42:02  starvik
+ * Extracted v10 (ETRAX 100LX) specific stuff from arch/cris/kernel/
+ *
+ * Revision 1.1  2002/11/18 07:58:06  starvik
+ * Fast timers (from Linux 2.4)
+ *
+ * Revision 1.5  2002/10/15 06:21:39  starvik
+ * Added call to init_waitqueue_head
+ *
+ * Revision 1.4  2002/05/28 17:47:59  johana
+ * Added del_fast_timer()
+ *
+ * Revision 1.3  2002/05/28 16:16:07  johana
+ * Handle empty fast_timer_list
+ *
+ * Revision 1.2  2002/05/27 15:38:42  johana
+ * Made it compile without warnings on Linux 2.4.
+ * (includes, wait_queue, PROC_FS and snprintf)
+ *
+ * Revision 1.1  2002/05/27 15:32:25  johana
+ * arch/etrax100/kernel/fasttimer.c v1.8 from the elinux tree.
+ *
+ * Revision 1.8  2001/11/27 13:50:40  pkj
+ * Disable interrupts while stopping the timer and while modifying the
+ * list of active timers in timer1_handler() as it may be interrupted
+ * by other interrupts (e.g., the serial interrupt) which may add fast
+ * timers.
+ *
+ * Revision 1.7  2001/11/22 11:50:32  pkj
+ * * Only store information about the last 16 timers.
+ * * proc_fasttimer_read() now uses an allocated buffer, since it
+ *   requires more space than just a page even for only writing the
+ *   last 16 timers. The buffer is only allocated on request, so
+ *   unless /proc/fasttimer is read, it is never allocated.
+ * * Renamed fast_timer_started to fast_timers_started to match
+ *   fast_timers_added and fast_timers_expired.
+ * * Some clean-up.
+ *
+ * Revision 1.6  2000/12/13 14:02:08  johana
+ * Removed volatile for fast_timer_list
+ *
+ * Revision 1.5  2000/12/13 13:55:35  johana
+ * Added DEBUG_LOG, added som cli() and cleanup
+ *
+ * Revision 1.4  2000/12/05 13:48:50  johana
+ * Added range check when writing proc file, modified timer int handling
+ *
+ * Revision 1.3  2000/11/23 10:10:20  johana
+ * More debug/logging possibilities.
+ * Moved GET_JIFFIES_USEC() to timex.h and time.c
+ *
+ * Revision 1.2  2000/11/01 13:41:04  johana
+ * Clean up and bugfixes.
+ * Created new do_gettimeofday_fast() that gets a timeval struct
+ * with time based on jiffies and *R_TIMER0_DATA, uses a table
+ * for fast conversion of timer value to microseconds.
+ * (Much faster the standard do_gettimeofday() and we don't really
+ * wan't to use the true time - we wan't the "uptime" so timers don't screw up
+ * when we change the time.
+ * TODO: Add efficient support for continuous timers as well.
+ *
+ * Revision 1.1  2000/10/26 15:49:16  johana
+ * Added fasttimer, highresolution timers.
+ *
+ * Copyright (C) 2000,2001 2002, 2003 Axis Communications AB, Lund, Sweden
+ */
+
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/string.h>
+#include <linux/vmalloc.h>
+#include <linux/interrupt.h>
+#include <linux/time.h>
+#include <linux/delay.h>
+
+#include <asm/irq.h>
+#include <asm/system.h>
+
+#include <linux/config.h>
+#include <linux/version.h>
+
+#include <asm/arch/hwregs/reg_map.h>
+#include <asm/arch/hwregs/reg_rdwr.h>
+#include <asm/arch/hwregs/timer_defs.h>
+#include <asm/fasttimer.h>
+#include <linux/proc_fs.h>
+
+/*
+ * timer0 is running at 100MHz and generating jiffies timer ticks
+ * at 100 or 1000 HZ.
+ * fasttimer gives an API that gives timers that expire "between" the jiffies
+ * giving microsecond resolution (10 ns).
+ * fasttimer uses reg_timer_rw_trig register to get interrupt when
+ * r_time reaches a certain value.
+ */
+
+
+#define DEBUG_LOG_INCLUDED
+#define FAST_TIMER_LOG
+//#define FAST_TIMER_TEST
+
+#define FAST_TIMER_SANITY_CHECKS
+
+#ifdef FAST_TIMER_SANITY_CHECKS
+#define SANITYCHECK(x) x
+static int sanity_failed = 0;
+#else
+#define SANITYCHECK(x)
+#endif
+
+#define D1(x)
+#define D2(x)
+#define DP(x)
+
+#define __INLINE__ inline
+
+static int fast_timer_running = 0;
+static int fast_timers_added = 0;
+static int fast_timers_started = 0;
+static int fast_timers_expired = 0;
+static int fast_timers_deleted = 0;
+static int fast_timer_is_init = 0;
+static int fast_timer_ints = 0;
+
+struct fast_timer *fast_timer_list = NULL;
+
+#ifdef DEBUG_LOG_INCLUDED
+#define DEBUG_LOG_MAX 128
+static const char * debug_log_string[DEBUG_LOG_MAX];
+static unsigned long debug_log_value[DEBUG_LOG_MAX];
+static int debug_log_cnt = 0;
+static int debug_log_cnt_wrapped = 0;
+
+#define DEBUG_LOG(string, value) \
+{ \
+  unsigned long log_flags; \
+  local_irq_save(log_flags); \
+  debug_log_string[debug_log_cnt] = (string); \
+  debug_log_value[debug_log_cnt] = (unsigned long)(value); \
+  if (++debug_log_cnt >= DEBUG_LOG_MAX) \
+  { \
+    debug_log_cnt = debug_log_cnt % DEBUG_LOG_MAX; \
+    debug_log_cnt_wrapped = 1; \
+  } \
+  local_irq_restore(log_flags); \
+}
+#else
+#define DEBUG_LOG(string, value)
+#endif
+
+
+#define NUM_TIMER_STATS 16
+#ifdef FAST_TIMER_LOG
+struct fast_timer timer_added_log[NUM_TIMER_STATS];
+struct fast_timer timer_started_log[NUM_TIMER_STATS];
+struct fast_timer timer_expired_log[NUM_TIMER_STATS];
+#endif
+
+int timer_div_settings[NUM_TIMER_STATS];
+int timer_delay_settings[NUM_TIMER_STATS];
+
+
+static void
+timer_trig_handler(void);
+
+
+
+/* Not true gettimeofday, only checks the jiffies (uptime) + useconds */
+void __INLINE__ do_gettimeofday_fast(struct timeval *tv)
+{
+  unsigned long sec = jiffies;
+  unsigned long usec = GET_JIFFIES_USEC();
+
+  usec += (sec % HZ) * (1000000 / HZ);
+  sec = sec / HZ;
+
+  if (usec > 1000000)
+  {
+    usec -= 1000000;
+    sec++;
+  }
+  tv->tv_sec = sec;
+  tv->tv_usec = usec;
+}
+
+int __INLINE__ timeval_cmp(struct timeval *t0, struct timeval *t1)
+{
+  if (t0->tv_sec < t1->tv_sec)
+  {
+    return -1;
+  }
+  else if (t0->tv_sec > t1->tv_sec)
+  {
+    return 1;
+  }
+  if (t0->tv_usec < t1->tv_usec)
+  {
+    return -1;
+  }
+  else if (t0->tv_usec > t1->tv_usec)
+  {
+    return 1;
+  }
+  return 0;
+}
+
+/* Called with ints off */
+void __INLINE__ start_timer_trig(unsigned long delay_us)
+{
+  reg_timer_rw_ack_intr ack_intr = { 0 };
+  reg_timer_rw_intr_mask intr_mask;
+  reg_timer_rw_trig trig;
+  reg_timer_rw_trig_cfg trig_cfg = { 0 };
+  reg_timer_r_time r_time;
+
+  r_time = REG_RD(timer, regi_timer, r_time);
+
+  D1(printk("start_timer_trig : %d us freq: %i div: %i\n",
+            delay_us, freq_index, div));
+  /* Clear trig irq */
+  intr_mask = REG_RD(timer, regi_timer, rw_intr_mask);
+  intr_mask.trig = 0;
+  REG_WR(timer, regi_timer, rw_intr_mask, intr_mask);
+
+  /* Set timer values */
+  /* r_time is 100MHz (10 ns resolution) */
+  trig = r_time + delay_us*(1000/10);
+
+  timer_div_settings[fast_timers_started % NUM_TIMER_STATS] = trig;
+  timer_delay_settings[fast_timers_started % NUM_TIMER_STATS] = delay_us;
+
+  /* Ack interrupt */
+  ack_intr.trig = 1;
+  REG_WR(timer, regi_timer, rw_ack_intr, ack_intr);
+
+  /* Start timer */
+  REG_WR(timer, regi_timer, rw_trig, trig);
+  trig_cfg.tmr = regk_timer_time;
+  REG_WR(timer, regi_timer, rw_trig_cfg, trig_cfg);
+
+  /* Check if we have already passed the trig time */
+  r_time = REG_RD(timer, regi_timer, r_time);
+  if (r_time < trig) {
+    /* No, Enable trig irq */
+    intr_mask = REG_RD(timer, regi_timer, rw_intr_mask);
+    intr_mask.trig = 1;
+    REG_WR(timer, regi_timer, rw_intr_mask, intr_mask);
+    fast_timers_started++;
+    fast_timer_running = 1;
+  }
+  else
+  {
+    /* We have passed the time, disable trig point, ack intr */
+    trig_cfg.tmr = regk_timer_off;
+    REG_WR(timer, regi_timer, rw_trig_cfg, trig_cfg);
+    REG_WR(timer, regi_timer, rw_ack_intr, ack_intr);
+    /* call the int routine directly */
+    timer_trig_handler();
+  }
+
+}
+
+/* In version 1.4 this function takes 27 - 50 us */
+void start_one_shot_timer(struct fast_timer *t,
+                          fast_timer_function_type *function,
+                          unsigned long data,
+                          unsigned long delay_us,
+                          const char *name)
+{
+  unsigned long flags;
+  struct fast_timer *tmp;
+
+  D1(printk("sft %s %d us\n", name, delay_us));
+
+  local_irq_save(flags);
+
+  do_gettimeofday_fast(&t->tv_set);
+  tmp = fast_timer_list;
+
+  SANITYCHECK({ /* Check so this is not in the list already... */
+    while (tmp != NULL)
+    {
+      if (tmp == t)
+      {
+        printk("timer name: %s data: 0x%08lX already in list!\n", name, data);
+        sanity_failed++;
+        return;
+      }
+      else
+      {
+        tmp = tmp->next;
+      }
+    }
+    tmp = fast_timer_list;
+  });
+
+  t->delay_us = delay_us;
+  t->function = function;
+  t->data = data;
+  t->name = name;
+
+  t->tv_expires.tv_usec = t->tv_set.tv_usec + delay_us % 1000000;
+  t->tv_expires.tv_sec  = t->tv_set.tv_sec  + delay_us / 1000000;
+  if (t->tv_expires.tv_usec > 1000000)
+  {
+    t->tv_expires.tv_usec -= 1000000;
+    t->tv_expires.tv_sec++;
+  }
+#ifdef FAST_TIMER_LOG
+  timer_added_log[fast_timers_added % NUM_TIMER_STATS] = *t;
+#endif
+  fast_timers_added++;
+
+  /* Check if this should timeout before anything else */
+  if (tmp == NULL || timeval_cmp(&t->tv_expires, &tmp->tv_expires) < 0)
+  {
+    /* Put first in list and modify the timer value */
+    t->prev = NULL;
+    t->next = fast_timer_list;
+    if (fast_timer_list)
+    {
+      fast_timer_list->prev = t;
+    }
+    fast_timer_list = t;
+#ifdef FAST_TIMER_LOG
+    timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t;
+#endif
+    start_timer_trig(delay_us);
+  } else {
+    /* Put in correct place in list */
+    while (tmp->next &&
+           timeval_cmp(&t->tv_expires, &tmp->next->tv_expires) > 0)
+    {
+      tmp = tmp->next;
+    }
+    /* Insert t after tmp */
+    t->prev = tmp;
+    t->next = tmp->next;
+    if (tmp->next)
+    {
+      tmp->next->prev = t;
+    }
+    tmp->next = t;
+  }
+
+  D2(printk("start_one_shot_timer: %d us done\n", delay_us));
+
+  local_irq_restore(flags);
+} /* start_one_shot_timer */
+
+static inline int fast_timer_pending (const struct fast_timer * t)
+{
+  return (t->next != NULL) || (t->prev != NULL) || (t == fast_timer_list);
+}
+
+static inline int detach_fast_timer (struct fast_timer *t)
+{
+  struct fast_timer *next, *prev;
+  if (!fast_timer_pending(t))
+    return 0;
+  next = t->next;
+  prev = t->prev;
+  if (next)
+    next->prev = prev;
+  if (prev)
+    prev->next = next;
+  else
+    fast_timer_list = next;
+  fast_timers_deleted++;
+  return 1;
+}
+
+int del_fast_timer(struct fast_timer * t)
+{
+  unsigned long flags;
+  int ret;
+
+  local_irq_save(flags);
+  ret = detach_fast_timer(t);
+  t->next = t->prev = NULL;
+  local_irq_restore(flags);
+  return ret;
+} /* del_fast_timer */
+
+
+/* Interrupt routines or functions called in interrupt context */
+
+/* Timer interrupt handler for trig interrupts */
+
+static irqreturn_t
+timer_trig_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+  reg_timer_r_masked_intr masked_intr;
+
+  /* Check if the timer interrupt is for us (a trig int) */
+  masked_intr = REG_RD(timer, regi_timer, r_masked_intr);
+  if (!masked_intr.trig)
+    return IRQ_NONE;
+  timer_trig_handler();
+  return IRQ_HANDLED;
+}
+
+static void timer_trig_handler(void)
+{
+  reg_timer_rw_ack_intr ack_intr = { 0 };
+  reg_timer_rw_intr_mask intr_mask;
+  reg_timer_rw_trig_cfg trig_cfg = { 0 };
+  struct fast_timer *t;
+  unsigned long flags;
+
+  local_irq_save(flags);
+
+  /* Clear timer trig interrupt */
+  intr_mask = REG_RD(timer, regi_timer, rw_intr_mask);
+  intr_mask.trig = 0;
+  REG_WR(timer, regi_timer, rw_intr_mask, intr_mask);
+
+  /* First stop timer, then ack interrupt */
+  /* Stop timer */
+  trig_cfg.tmr = regk_timer_off;
+  REG_WR(timer, regi_timer, rw_trig_cfg, trig_cfg);
+
+  /* Ack interrupt */
+  ack_intr.trig = 1;
+  REG_WR(timer, regi_timer, rw_ack_intr, ack_intr);
+
+  fast_timer_running = 0;
+  fast_timer_ints++;
+
+  local_irq_restore(flags);
+
+  t = fast_timer_list;
+  while (t)
+  {
+    struct timeval tv;
+
+    /* Has it really expired? */
+    do_gettimeofday_fast(&tv);
+    D1(printk("t: %is %06ius\n", tv.tv_sec, tv.tv_usec));
+
+    if (timeval_cmp(&t->tv_expires, &tv) <= 0)
+    {
+      /* Yes it has expired */
+#ifdef FAST_TIMER_LOG
+      timer_expired_log[fast_timers_expired % NUM_TIMER_STATS] = *t;
+#endif
+      fast_timers_expired++;
+
+      /* Remove this timer before call, since it may reuse the timer */
+      local_irq_save(flags);
+      if (t->prev)
+      {
+        t->prev->next = t->next;
+      }
+      else
+      {
+        fast_timer_list = t->next;
+      }
+      if (t->next)
+      {
+        t->next->prev = t->prev;
+      }
+      t->prev = NULL;
+      t->next = NULL;
+      local_irq_restore(flags);
+
+      if (t->function != NULL)
+      {
+        t->function(t->data);
+      }
+      else
+      {
+        DEBUG_LOG("!trimertrig %i function==NULL!\n", fast_timer_ints);
+      }
+    }
+    else
+    {
+      /* Timer is to early, let's set it again using the normal routines */
+      D1(printk(".\n"));
+    }
+
+    local_irq_save(flags);
+    if ((t = fast_timer_list) != NULL)
+    {
+      /* Start next timer.. */
+      long us;
+      struct timeval tv;
+
+      do_gettimeofday_fast(&tv);
+      us = ((t->tv_expires.tv_sec - tv.tv_sec) * 1000000 +
+            t->tv_expires.tv_usec - tv.tv_usec);
+      if (us > 0)
+      {
+        if (!fast_timer_running)
+        {
+#ifdef FAST_TIMER_LOG
+          timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t;
+#endif
+          start_timer_trig(us);
+        }
+        local_irq_restore(flags);
+        break;
+      }
+      else
+      {
+        /* Timer already expired, let's handle it better late than never.
+         * The normal loop handles it
+         */
+        D1(printk("e! %d\n", us));
+      }
+    }
+    local_irq_restore(flags);
+  }
+
+  if (!t)
+  {
+    D1(printk("ttrig stop!\n"));
+  }
+}
+
+static void wake_up_func(unsigned long data)
+{
+#ifdef DECLARE_WAITQUEUE
+  wait_queue_head_t  *sleep_wait_p = (wait_queue_head_t*)data;
+#else
+  struct wait_queue **sleep_wait_p = (struct wait_queue **)data;
+#endif
+  wake_up(sleep_wait_p);
+}
+
+
+/* Useful API */
+
+void schedule_usleep(unsigned long us)
+{
+  struct fast_timer t;
+#ifdef DECLARE_WAITQUEUE
+  wait_queue_head_t sleep_wait;
+  init_waitqueue_head(&sleep_wait);
+  {
+  DECLARE_WAITQUEUE(wait, current);
+#else
+  struct wait_queue *sleep_wait = NULL;
+  struct wait_queue wait = { current, NULL };
+#endif
+
+  D1(printk("schedule_usleep(%d)\n", us));
+  add_wait_queue(&sleep_wait, &wait);
+  set_current_state(TASK_INTERRUPTIBLE);
+  start_one_shot_timer(&t, wake_up_func, (unsigned long)&sleep_wait, us,
+                       "usleep");
+  schedule();
+  set_current_state(TASK_RUNNING);
+  remove_wait_queue(&sleep_wait, &wait);
+  D1(printk("done schedule_usleep(%d)\n", us));
+#ifdef DECLARE_WAITQUEUE
+  }
+#endif
+}
+
+#ifdef CONFIG_PROC_FS
+static int proc_fasttimer_read(char *buf, char **start, off_t offset, int len
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0)
+                       ,int *eof, void *data_unused
+#else
+                        ,int unused
+#endif
+                               );
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0)
+static struct proc_dir_entry *fasttimer_proc_entry;
+#else
+static struct proc_dir_entry fasttimer_proc_entry =
+{
+  0, 9, "fasttimer",
+  S_IFREG | S_IRUGO, 1, 0, 0,
+  0, NULL /* ops -- default to array */,
+  &proc_fasttimer_read /* get_info */,
+};
+#endif
+#endif /* CONFIG_PROC_FS */
+
+#ifdef CONFIG_PROC_FS
+
+/* This value is very much based on testing */
+#define BIG_BUF_SIZE (500 + NUM_TIMER_STATS * 300)
+
+static int proc_fasttimer_read(char *buf, char **start, off_t offset, int len
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0)
+                       ,int *eof, void *data_unused
+#else
+                        ,int unused
+#endif
+                               )
+{
+  unsigned long flags;
+  int i = 0;
+  int num_to_show;
+  struct timeval tv;
+  struct fast_timer *t, *nextt;
+  static char *bigbuf = NULL;
+  static unsigned long used;
+
+  if (!bigbuf && !(bigbuf = vmalloc(BIG_BUF_SIZE)))
+  {
+    used = 0;
+    bigbuf[0] = '\0';
+    return 0;
+  }
+
+  if (!offset || !used)
+  {
+    do_gettimeofday_fast(&tv);
+
+    used = 0;
+    used += sprintf(bigbuf + used, "Fast timers added:     %i\n",
+                    fast_timers_added);
+    used += sprintf(bigbuf + used, "Fast timers started:   %i\n",
+                    fast_timers_started);
+    used += sprintf(bigbuf + used, "Fast timer interrupts: %i\n",
+                    fast_timer_ints);
+    used += sprintf(bigbuf + used, "Fast timers expired:   %i\n",
+                    fast_timers_expired);
+    used += sprintf(bigbuf + used, "Fast timers deleted:   %i\n",
+                    fast_timers_deleted);
+    used += sprintf(bigbuf + used, "Fast timer running:    %s\n",
+                    fast_timer_running ? "yes" : "no");
+    used += sprintf(bigbuf + used, "Current time:          %lu.%06lu\n",
+                    (unsigned long)tv.tv_sec,
+                    (unsigned long)tv.tv_usec);
+#ifdef FAST_TIMER_SANITY_CHECKS
+    used += sprintf(bigbuf + used, "Sanity failed:         %i\n",
+                    sanity_failed);
+#endif
+    used += sprintf(bigbuf + used, "\n");
+
+#ifdef DEBUG_LOG_INCLUDED
+    {
+      int end_i = debug_log_cnt;
+      i = 0;
+
+      if (debug_log_cnt_wrapped)
+      {
+        i = debug_log_cnt;
+      }
+
+      while ((i != end_i || (debug_log_cnt_wrapped && !used)) &&
+             used+100 < BIG_BUF_SIZE)
+      {
+        used += sprintf(bigbuf + used, debug_log_string[i],
+                        debug_log_value[i]);
+        i = (i+1) % DEBUG_LOG_MAX;
+      }
+    }
+    used += sprintf(bigbuf + used, "\n");
+#endif
+
+    num_to_show = (fast_timers_started < NUM_TIMER_STATS ? fast_timers_started:
+                   NUM_TIMER_STATS);
+    used += sprintf(bigbuf + used, "Timers started: %i\n", fast_timers_started);
+    for (i = 0; i < num_to_show && (used+100 < BIG_BUF_SIZE) ; i++)
+    {
+      int cur = (fast_timers_started - i - 1) % NUM_TIMER_STATS;
+
+#if 1 //ndef FAST_TIMER_LOG
+      used += sprintf(bigbuf + used, "div: %i delay: %i"
+                      "\n",
+                      timer_div_settings[cur],
+                      timer_delay_settings[cur]
+                      );
+#endif
+#ifdef FAST_TIMER_LOG
+      t = &timer_started_log[cur];
+      used += sprintf(bigbuf + used, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
+                      "d: %6li us data: 0x%08lX"
+                      "\n",
+                      t->name,
+                      (unsigned long)t->tv_set.tv_sec,
+                      (unsigned long)t->tv_set.tv_usec,
+                      (unsigned long)t->tv_expires.tv_sec,
+                      (unsigned long)t->tv_expires.tv_usec,
+                      t->delay_us,
+                      t->data
+                      );
+#endif
+    }
+    used += sprintf(bigbuf + used, "\n");
+
+#ifdef FAST_TIMER_LOG
+    num_to_show = (fast_timers_added < NUM_TIMER_STATS ? fast_timers_added:
+                   NUM_TIMER_STATS);
+    used += sprintf(bigbuf + used, "Timers added: %i\n", fast_timers_added);
+    for (i = 0; i < num_to_show && (used+100 < BIG_BUF_SIZE); i++)
+    {
+      t = &timer_added_log[(fast_timers_added - i - 1) % NUM_TIMER_STATS];
+      used += sprintf(bigbuf + used, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
+                      "d: %6li us data: 0x%08lX"
+                      "\n",
+                      t->name,
+                      (unsigned long)t->tv_set.tv_sec,
+                      (unsigned long)t->tv_set.tv_usec,
+                      (unsigned long)t->tv_expires.tv_sec,
+                      (unsigned long)t->tv_expires.tv_usec,
+                      t->delay_us,
+                      t->data
+                      );
+    }
+    used += sprintf(bigbuf + used, "\n");
+
+    num_to_show = (fast_timers_expired < NUM_TIMER_STATS ? fast_timers_expired:
+                   NUM_TIMER_STATS);
+    used += sprintf(bigbuf + used, "Timers expired: %i\n", fast_timers_expired);
+    for (i = 0; i < num_to_show && (used+100 < BIG_BUF_SIZE); i++)
+    {
+      t = &timer_expired_log[(fast_timers_expired - i - 1) % NUM_TIMER_STATS];
+      used += sprintf(bigbuf + used, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
+                      "d: %6li us data: 0x%08lX"
+                      "\n",
+                      t->name,
+                      (unsigned long)t->tv_set.tv_sec,
+                      (unsigned long)t->tv_set.tv_usec,
+                      (unsigned long)t->tv_expires.tv_sec,
+                      (unsigned long)t->tv_expires.tv_usec,
+                      t->delay_us,
+                      t->data
+                      );
+    }
+    used += sprintf(bigbuf + used, "\n");
+#endif
+
+    used += sprintf(bigbuf + used, "Active timers:\n");
+    local_irq_save(flags);
+    local_irq_save(flags);
+    t = fast_timer_list;
+    while (t != NULL && (used+100 < BIG_BUF_SIZE))
+    {
+      nextt = t->next;
+      local_irq_restore(flags);
+      used += sprintf(bigbuf + used, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
+                      "d: %6li us data: 0x%08lX"
+/*                      " func: 0x%08lX" */
+                      "\n",
+                      t->name,
+                      (unsigned long)t->tv_set.tv_sec,
+                      (unsigned long)t->tv_set.tv_usec,
+                      (unsigned long)t->tv_expires.tv_sec,
+                      (unsigned long)t->tv_expires.tv_usec,
+                      t->delay_us,
+                      t->data
+/*                      , t->function */
+                      );
+      local_irq_disable();
+      if (t->next != nextt)
+      {
+        printk("timer removed!\n");
+      }
+      t = nextt;
+    }
+    local_irq_restore(flags);
+  }
+
+  if (used - offset < len)
+  {
+    len = used - offset;
+  }
+
+  memcpy(buf, bigbuf + offset, len);
+  *start = buf;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0)
+  *eof = 1;
+#endif
+
+  return len;
+}
+#endif /* PROC_FS */
+
+#ifdef FAST_TIMER_TEST
+static volatile unsigned long i = 0;
+static volatile int num_test_timeout = 0;
+static struct fast_timer tr[10];
+static int exp_num[10];
+
+static struct timeval tv_exp[100];
+
+static void test_timeout(unsigned long data)
+{
+  do_gettimeofday_fast(&tv_exp[data]);
+  exp_num[data] = num_test_timeout;
+
+  num_test_timeout++;
+}
+
+static void test_timeout1(unsigned long data)
+{
+  do_gettimeofday_fast(&tv_exp[data]);
+  exp_num[data] = num_test_timeout;
+  if (data < 7)
+  {
+    start_one_shot_timer(&tr[i], test_timeout1, i, 1000, "timeout1");
+    i++;
+  }
+  num_test_timeout++;
+}
+
+DP(
+static char buf0[2000];
+static char buf1[2000];
+static char buf2[2000];
+static char buf3[2000];
+static char buf4[2000];
+);
+
+static char buf5[6000];
+static int j_u[1000];
+
+static void fast_timer_test(void)
+{
+  int prev_num;
+  int j;
+
+  struct timeval tv, tv0, tv1, tv2;
+
+  printk("fast_timer_test() start\n");
+  do_gettimeofday_fast(&tv);
+
+  for (j = 0; j < 1000; j++)
+  {
+    j_u[j] = GET_JIFFIES_USEC();
+  }
+  for (j = 0; j < 100; j++)
+  {
+    do_gettimeofday_fast(&tv_exp[j]);
+  }
+  printk("fast_timer_test() %is %06i\n", tv.tv_sec, tv.tv_usec);
+
+  for (j = 0; j < 1000; j++)
+  {
+    printk("%i %i %i %i %i\n",j_u[j], j_u[j+1], j_u[j+2], j_u[j+3], j_u[j+4]);
+    j += 4;
+  }
+  for (j = 0; j < 100; j++)
+  {
+    printk("%i.%i %i.%i %i.%i %i.%i %i.%i\n",
+           tv_exp[j].tv_sec,tv_exp[j].tv_usec,
+           tv_exp[j+1].tv_sec,tv_exp[j+1].tv_usec,
+           tv_exp[j+2].tv_sec,tv_exp[j+2].tv_usec,
+           tv_exp[j+3].tv_sec,tv_exp[j+3].tv_usec,
+           tv_exp[j+4].tv_sec,tv_exp[j+4].tv_usec);
+    j += 4;
+  }
+  do_gettimeofday_fast(&tv0);
+  start_one_shot_timer(&tr[i], test_timeout, i, 50000, "test0");
+  DP(proc_fasttimer_read(buf0, NULL, 0, 0, 0));
+  i++;
+  start_one_shot_timer(&tr[i], test_timeout, i, 70000, "test1");
+  DP(proc_fasttimer_read(buf1, NULL, 0, 0, 0));
+  i++;
+  start_one_shot_timer(&tr[i], test_timeout, i, 40000, "test2");
+  DP(proc_fasttimer_read(buf2, NULL, 0, 0, 0));
+  i++;
+  start_one_shot_timer(&tr[i], test_timeout, i, 60000, "test3");
+  DP(proc_fasttimer_read(buf3, NULL, 0, 0, 0));
+  i++;
+  start_one_shot_timer(&tr[i], test_timeout1, i, 55000, "test4xx");
+  DP(proc_fasttimer_read(buf4, NULL, 0, 0, 0));
+  i++;
+  do_gettimeofday_fast(&tv1);
+
+  proc_fasttimer_read(buf5, NULL, 0, 0, 0);
+
+  prev_num = num_test_timeout;
+  while (num_test_timeout < i)
+  {
+    if (num_test_timeout != prev_num)
+    {
+      prev_num = num_test_timeout;
+    }
+  }
+  do_gettimeofday_fast(&tv2);
+  printk("Timers started    %is %06i\n", tv0.tv_sec, tv0.tv_usec);
+  printk("Timers started at %is %06i\n", tv1.tv_sec, tv1.tv_usec);
+  printk("Timers done       %is %06i\n", tv2.tv_sec, tv2.tv_usec);
+  DP(printk("buf0:\n");
+     printk(buf0);
+     printk("buf1:\n");
+     printk(buf1);
+     printk("buf2:\n");
+     printk(buf2);
+     printk("buf3:\n");
+     printk(buf3);
+     printk("buf4:\n");
+     printk(buf4);
+  );
+  printk("buf5:\n");
+  printk(buf5);
+
+  printk("timers set:\n");
+  for(j = 0; j<i; j++)
+  {
+    struct fast_timer *t = &tr[j];
+    printk("%-10s set: %6is %06ius exp: %6is %06ius "
+           "data: 0x%08X func: 0x%08X\n",
+           t->name,
+           t->tv_set.tv_sec,
+           t->tv_set.tv_usec,
+           t->tv_expires.tv_sec,
+           t->tv_expires.tv_usec,
+           t->data,
+           t->function
+           );
+
+    printk("           del: %6ius     did exp: %6is %06ius as #%i error: %6li\n",
+           t->delay_us,
+           tv_exp[j].tv_sec,
+           tv_exp[j].tv_usec,
+           exp_num[j],
+           (tv_exp[j].tv_sec - t->tv_expires.tv_sec)*1000000 + tv_exp[j].tv_usec - t->tv_expires.tv_usec);
+  }
+  proc_fasttimer_read(buf5, NULL, 0, 0, 0);
+  printk("buf5 after all done:\n");
+  printk(buf5);
+  printk("fast_timer_test() done\n");
+}
+#endif
+
+
+void fast_timer_init(void)
+{
+  /* For some reason, request_irq() hangs when called froom time_init() */
+  if (!fast_timer_is_init)
+  {
+    printk("fast_timer_init()\n");
+
+#ifdef CONFIG_PROC_FS
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0)
+   if ((fasttimer_proc_entry = create_proc_entry( "fasttimer", 0, 0 )))
+     fasttimer_proc_entry->read_proc = proc_fasttimer_read;
+#else
+    proc_register_dynamic(&proc_root, &fasttimer_proc_entry);
+#endif
+#endif /* PROC_FS */
+    if(request_irq(TIMER_INTR_VECT, timer_trig_interrupt, SA_INTERRUPT,
+                   "fast timer int", NULL))
+    {
+      printk("err: timer1 irq\n");
+    }
+    fast_timer_is_init = 1;
+#ifdef FAST_TIMER_TEST
+    printk("do test\n");
+    fast_timer_test();
+#endif
+  }
+}
diff --git a/arch/cris/arch-v32/kernel/head.S b/arch/cris/arch-v32/kernel/head.S
new file mode 100644
index 00000000000..3cfe57dc391
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/head.S
@@ -0,0 +1,448 @@
+/*
+ * CRISv32 kernel startup code.
+ *
+ * Copyright (C) 2003, Axis Communications AB
+ */
+
+#include <linux/config.h>
+
+#define ASSEMBLER_MACROS_ONLY
+
+/*
+ * The macros found in mmu_defs_asm.h uses the ## concatenation operator, so
+ * -traditional must not be used when assembling this file.
+ */
+#include <asm/arch/hwregs/reg_rdwr.h>
+#include <asm/arch/hwregs/asm/mmu_defs_asm.h>
+#include <asm/arch/hwregs/asm/reg_map_asm.h>
+#include <asm/arch/hwregs/asm/config_defs_asm.h>
+#include <asm/arch/hwregs/asm/bif_core_defs_asm.h>
+
+#define CRAMFS_MAGIC 0x28cd3d45
+#define RAM_INIT_MAGIC 0x56902387
+#define COMMAND_LINE_MAGIC 0x87109563
+
+	;; NOTE: R8 and R9 carry information from the decompressor (if the
+	;; kernel was compressed). They must not be used in the code below
+	;; until they are read!
+
+	;; Exported symbols.
+	.global etrax_irv
+	.global romfs_start
+	.global romfs_length
+	.global romfs_in_flash
+	.global swapper_pg_dir
+	.global crisv32_nand_boot
+	.global crisv32_nand_cramfs_offset
+
+	;; Dummy section to make it bootable with current VCS simulator
+#ifdef CONFIG_ETRAXFS_SIM
+	.section ".boot", "ax"
+	ba tstart
+	nop
+#endif
+
+	.text
+tstart:
+	;; This is the entry point of the kernel. The CPU is currently in
+	;; supervisor mode.
+	;;
+	;; 0x00000000 if flash.
+	;; 0x40004000 if DRAM.
+	;;
+	di
+
+	;; Start clocks for used blocks.
+	move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1
+	move.d [$r1], $r0
+	or.d   REG_STATE(config, rw_clk_ctrl, cpu, yes) | \
+	       REG_STATE(config, rw_clk_ctrl, bif, yes) | \
+	       REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0
+	move.d $r0, [$r1]
+
+	;; Set up waitstates etc
+	move.d   REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r0
+	move.d   CONFIG_ETRAX_MEM_GRP1_CONFIG, $r1
+	move.d   $r1, [$r0]
+	move.d   REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg), $r0
+	move.d   CONFIG_ETRAX_MEM_GRP2_CONFIG, $r1
+	move.d   $r1, [$r0]
+	move.d   REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r0
+	move.d   CONFIG_ETRAX_MEM_GRP3_CONFIG, $r1
+	move.d   $r1, [$r0]
+	move.d   REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg), $r0
+	move.d   CONFIG_ETRAX_MEM_GRP4_CONFIG, $r1
+	move.d   $r1, [$r0]
+
+#ifdef CONFIG_ETRAXFS_SIM
+	;; Set up minimal flash waitstates
+	move.d 0, $r10
+	move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r11
+	move.d $r10, [$r11]
+#endif
+
+	;; Setup and enable the MMU. Use same configuration for both the data
+	;; and the instruction MMU.
+	;;
+	;; Note; 3 cycles is needed for a bank-select to take effect. Further;
+	;; bank 1 is the instruction MMU, bank 2 is the data MMU.
+#ifndef CONFIG_ETRAXFS_SIM
+	move.d	REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8)	\
+		| REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4)	\
+		| REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb), $r0
+#else
+	;; Map the virtual DRAM to the RW eprom area at address 0.
+	;; Also map 0xa for the hook calls,
+	move.d	REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8)	\
+		| REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0)	\
+		| REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb)   \
+		| REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0xa), $r0
+#endif
+
+	;; Temporary map of 0x40 -> 0x40 and 0x00 -> 0x00.
+	move.d	REG_FIELD(mmu, rw_mm_kbase_lo, base_4, 4)  \
+		| REG_FIELD(mmu, rw_mm_kbase_lo, base_0, 0), $r1
+
+	;; Enable certain page protections and setup linear mapping
+	;; for f,e,c,b,4,0.
+#ifndef CONFIG_ETRAXFS_SIM
+	move.d	REG_STATE(mmu, rw_mm_cfg, we, on)		\
+		| REG_STATE(mmu, rw_mm_cfg, acc, on)		\
+		| REG_STATE(mmu, rw_mm_cfg, ex, on)		\
+		| REG_STATE(mmu, rw_mm_cfg, inv, on)		\
+		| REG_STATE(mmu, rw_mm_cfg, seg_f, linear)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_e, linear)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_d, page)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_c, linear)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_b, linear)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_a, page)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_9, page)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_8, page)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_7, page)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_6, page)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_5, page)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_4, linear)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_3, page)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_2, page)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_1, page)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2
+#else
+	move.d	REG_STATE(mmu, rw_mm_cfg, we, on)		\
+		| REG_STATE(mmu, rw_mm_cfg, acc, on)		\
+		| REG_STATE(mmu, rw_mm_cfg, ex, on)		\
+		| REG_STATE(mmu, rw_mm_cfg, inv, on)		\
+		| REG_STATE(mmu, rw_mm_cfg, seg_f, linear)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_e, linear)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_d, page)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_c, linear)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_b, linear)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_a, linear)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_9, page)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_8, page)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_7, page)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_6, page)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_5, page)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_4, linear)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_3, page)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_2, page)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_1, page)	\
+		| REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2
+#endif
+
+	;; Update instruction MMU.
+	move	1, $srs
+	nop
+	nop
+	nop
+	move	$r0, $s2	; kbase_hi.
+	move	$r1, $s1	; kbase_lo.
+	move	$r2, $s0	; mm_cfg, virtual memory configuration.
+
+	;; Update data MMU.
+	move	2, $srs
+	nop
+	nop
+	nop
+	move	$r0, $s2	; kbase_hi.
+	move	$r1, $s1	; kbase_lo
+	move	$r2, $s0	; mm_cfg, virtual memory configuration.
+
+	;; Enable data and instruction MMU.
+	move	0, $srs
+	moveq	0xf, $r0	;  IMMU, DMMU, DCache, Icache on
+	nop
+	nop
+	nop
+	move	$r0, $s0
+	nop
+	nop
+	nop
+
+#ifdef CONFIG_SMP
+	;; Read CPU ID
+	move    0, $srs
+	nop
+	nop
+	nop
+	move    $s10, $r0
+	cmpq    0, $r0
+	beq	master_cpu
+	nop
+slave_cpu:
+	; A slave waits for cpu_now_booting to be equal to CPU ID.
+	move.d	cpu_now_booting, $r1
+slave_wait:
+	cmp.d	[$r1], $r0
+	bne	slave_wait
+	nop
+	; Time to boot-up. Get stack location provided by master CPU.
+	move.d  smp_init_current_idle_thread, $r1
+	move.d  [$r1], $sp
+	add.d	8192, $sp
+	move.d	ebp_start, $r0	; Defined in linker-script.
+	move	$r0, $ebp
+	jsr	smp_callin
+	nop
+master_cpu:
+#endif
+#ifndef CONFIG_ETRAXFS_SIM
+	;; Check if starting from DRAM or flash.
+	lapcq	., $r0
+	and.d	0x7fffffff, $r0 ; Mask off the non-cache bit.
+	cmp.d	0x10000, $r0	; Arbitrary, something above this code.
+	blo	_inflash0
+	nop
+#endif
+
+	jump	_inram		; Jump to cached RAM.
+	nop
+
+	;; Jumpgate.
+_inflash0:
+	jump _inflash
+	nop
+
+	;; Put the following in a section so that storage for it can be
+	;; reclaimed after init is finished.
+	.section ".init.text", "ax"
+
+_inflash:
+
+	;; Initialize DRAM.
+	cmp.d	RAM_INIT_MAGIC, $r8 ; Already initialized?
+	beq	_dram_initialized
+	nop
+
+#include "../lib/dram_init.S"
+
+_dram_initialized:
+	;; Copy the text and data section to DRAM. This depends on that the
+	;; variables used below are correctly set up by the linker script.
+	;; The calculated value stored in R4 is used below.
+	moveq	0, $r0		; Source.
+	move.d	text_start, $r1	; Destination.
+	move.d	__vmlinux_end, $r2
+	move.d	$r2, $r4
+	sub.d	$r1, $r4
+1:	move.w	[$r0+], $r3
+	move.w	$r3, [$r1+]
+	cmp.d	$r2, $r1
+	blo	1b
+	nop
+
+	;; Keep CRAMFS in flash.
+	moveq	0, $r0
+	move.d	romfs_length, $r1
+	move.d	$r0, [$r1]
+	move.d	[$r4], $r0	; cramfs_super.magic
+	cmp.d	CRAMFS_MAGIC, $r0
+	bne 1f
+	nop
+
+	addoq	+4, $r4, $acr
+	move.d	[$acr], $r0
+	move.d	romfs_length, $r1
+	move.d	$r0, [$r1]
+	add.d	0xf0000000, $r4	; Add cached flash start in virtual memory.
+	move.d	romfs_start, $r1
+	move.d	$r4, [$r1]
+1:	moveq	1, $r0
+	move.d	romfs_in_flash, $r1
+	move.d	$r0, [$r1]
+
+	jump	_start_it	; Jump to cached code.
+	nop
+
+_inram:
+	;; Check if booting from NAND flash (in that case we just remember the offset
+	;; into the flash where cramfs should be).
+	move.d	REG_ADDR(config, regi_config, r_bootsel), $r0
+	move.d	[$r0], $r0
+	and.d	REG_MASK(config, r_bootsel, boot_mode), $r0
+	cmp.d	REG_STATE(config, r_bootsel, boot_mode, nand), $r0
+	bne	move_cramfs
+	moveq	1,$r0
+	move.d	crisv32_nand_boot, $r1
+	move.d	$r0, [$r1]
+	move.d	crisv32_nand_cramfs_offset, $r1
+	move.d	$r9, [$r1]
+	moveq	1, $r0
+	move.d	romfs_in_flash, $r1
+	move.d	$r0, [$r1]
+	jump	_start_it
+	nop
+
+move_cramfs:
+	;; Move the cramfs after BSS.
+	moveq	0, $r0
+	move.d	romfs_length, $r1
+	move.d	$r0, [$r1]
+
+#ifndef CONFIG_ETRAXFS_SIM
+	;; The kernel could have been unpacked to DRAM by the loader, but
+	;; the cramfs image could still be inte the flash immediately
+	;; following the compressed kernel image. The loaded passes the address
+	;; of the bute succeeding the last compressed byte in the flash in
+	;; register R9 when starting the kernel.
+	cmp.d	0x0ffffff8, $r9
+	bhs	_no_romfs_in_flash ; R9 points outside the flash area.
+	nop
+#else
+	ba _no_romfs_in_flash
+	nop
+#endif
+	move.d	[$r9], $r0	; cramfs_super.magic
+	cmp.d	CRAMFS_MAGIC, $r0
+	bne	_no_romfs_in_flash
+	nop
+
+	addoq	+4, $r9, $acr
+	move.d	[$acr], $r0
+	move.d	romfs_length, $r1
+	move.d	$r0, [$r1]
+	add.d	0xf0000000, $r9	; Add cached flash start in virtual memory.
+	move.d	romfs_start, $r1
+	move.d	$r9, [$r1]
+	moveq	1, $r0
+	move.d	romfs_in_flash, $r1
+	move.d	$r0, [$r1]
+
+	jump	_start_it	; Jump to cached code.
+	nop
+
+_no_romfs_in_flash:
+	;; Look for cramfs.
+#ifndef CONFIG_ETRAXFS_SIM
+	move.d	__vmlinux_end, $r0
+#else
+	move.d	__end, $r0
+#endif
+	move.d	[$r0], $r1
+	cmp.d	CRAMFS_MAGIC, $r1
+	bne	2f
+	nop
+
+	addoq	+4, $r0, $acr
+	move.d	[$acr], $r2
+	move.d	_end, $r1
+	move.d	romfs_start, $r3
+	move.d	$r1, [$r3]
+	move.d	romfs_length, $r3
+	move.d	$r2, [$r3]
+
+#ifndef CONFIG_ETRAXFS_SIM
+	add.d	$r2, $r0
+	add.d	$r2, $r1
+
+	lsrq	1, $r2		; Size is in bytes, we copy words.
+	addq    1, $r2
+1:
+	move.w	[$r0], $r3
+	move.w	$r3, [$r1]
+	subq	2, $r0
+	subq	2, $r1
+	subq	1, $r2
+	bne	1b
+	nop
+#endif
+
+2:
+	moveq	0, $r0
+	move.d	romfs_in_flash, $r1
+	move.d	$r0, [$r1]
+
+	jump	_start_it	; Jump to cached code.
+	nop
+
+_start_it:
+
+	;; Check if kernel command line is supplied
+	cmp.d	COMMAND_LINE_MAGIC, $r10
+	bne	no_command_line
+	nop
+
+	move.d	256, $r13
+	move.d  cris_command_line, $r10
+	or.d	0x80000000, $r11 ; Make it virtual
+1:
+	move.b  [$r11+], $r12
+	move.b  $r12, [$r10+]
+	subq	1, $r13
+	bne	1b
+	nop
+
+no_command_line:
+
+	;; The kernel stack contains a task structure for each task. This
+	;; the initial kernel stack is in the same page as the init_task,
+	;; but starts at the top of the page, i.e. + 8192 bytes.
+	move.d	init_thread_union + 8192, $sp
+	move.d	ebp_start, $r0	; Defined in linker-script.
+	move	$r0, $ebp
+	move.d	etrax_irv, $r1	; Set the exception base register and pointer.
+	move.d	$r0, [$r1]
+
+#ifndef CONFIG_ETRAXFS_SIM
+	;; Clear the BSS region from _bss_start to _end.
+	move.d	__bss_start, $r0
+	move.d	_end, $r1
+1:	clear.d	[$r0+]
+	cmp.d	$r1, $r0
+	blo 1b
+	nop
+#endif
+
+#ifdef CONFIG_ETRAXFS_SIM
+	/* Set the watchdog timeout to something big. Will be removed when */
+	/* watchdog can be disabled with command line option */
+	move.d  0x7fffffff, $r10
+	jsr     CPU_WATCHDOG_TIMEOUT
+	nop
+#endif
+
+	; Initialize registers to increase determinism
+	move.d __bss_start, $r0
+	movem [$r0], $r13
+
+	jump	start_kernel	; Jump to start_kernel() in init/main.c.
+	nop
+
+	.data
+etrax_irv:
+	.dword 0
+romfs_start:
+	.dword 0
+romfs_length:
+	.dword 0
+romfs_in_flash:
+	.dword 0
+crisv32_nand_boot:
+	.dword 0
+crisv32_nand_cramfs_offset:
+	.dword 0
+
+swapper_pg_dir = 0xc0002000
+
+	.section ".init.data", "aw"
+
+#include "../lib/hw_settings.S"
diff --git a/arch/cris/arch-v32/kernel/io.c b/arch/cris/arch-v32/kernel/io.c
new file mode 100644
index 00000000000..6bc9f263c3d
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/io.c
@@ -0,0 +1,154 @@
+/*
+ * Helper functions for I/O pins.
+ *
+ * Copyright (c) 2004 Axis Communications AB.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <asm/io.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/hwregs/gio_defs.h>
+
+struct crisv32_ioport crisv32_ioports[] =
+{
+	{
+		(unsigned long*)REG_ADDR(gio, regi_gio, rw_pa_oe),
+		(unsigned long*)REG_ADDR(gio, regi_gio, rw_pa_dout),
+		(unsigned long*)REG_ADDR(gio, regi_gio, r_pa_din),
+		8
+	},
+	{
+		(unsigned long*)REG_ADDR(gio, regi_gio, rw_pb_oe),
+		(unsigned long*)REG_ADDR(gio, regi_gio, rw_pb_dout),
+		(unsigned long*)REG_ADDR(gio, regi_gio, r_pb_din),
+		18
+	},
+	{
+		(unsigned long*)REG_ADDR(gio, regi_gio, rw_pc_oe),
+		(unsigned long*)REG_ADDR(gio, regi_gio, rw_pc_dout),
+		(unsigned long*)REG_ADDR(gio, regi_gio, r_pc_din),
+		18
+	},
+	{
+		(unsigned long*)REG_ADDR(gio, regi_gio, rw_pd_oe),
+		(unsigned long*)REG_ADDR(gio, regi_gio, rw_pd_dout),
+		(unsigned long*)REG_ADDR(gio, regi_gio, r_pd_din),
+		18
+	},
+	{
+		(unsigned long*)REG_ADDR(gio, regi_gio, rw_pe_oe),
+		(unsigned long*)REG_ADDR(gio, regi_gio, rw_pe_dout),
+		(unsigned long*)REG_ADDR(gio, regi_gio, r_pe_din),
+		18
+	}
+};
+
+#define NBR_OF_PORTS sizeof(crisv32_ioports)/sizeof(struct crisv32_ioport)
+
+struct crisv32_iopin crisv32_led1_green;
+struct crisv32_iopin crisv32_led1_red;
+struct crisv32_iopin crisv32_led2_green;
+struct crisv32_iopin crisv32_led2_red;
+struct crisv32_iopin crisv32_led3_green;
+struct crisv32_iopin crisv32_led3_red;
+
+/* Dummy port used when green LED and red LED is on the same bit */
+static unsigned long io_dummy;
+static struct crisv32_ioport dummy_port =
+{
+	&io_dummy,
+	&io_dummy,
+	&io_dummy,
+	18
+};
+static struct crisv32_iopin dummy_led =
+{
+	&dummy_port,
+	0
+};
+
+static int __init crisv32_io_init(void)
+{
+	int ret = 0;
+	/* Initialize LEDs */
+	ret += crisv32_io_get_name(&crisv32_led1_green, CONFIG_ETRAX_LED1G);
+	ret += crisv32_io_get_name(&crisv32_led1_red, CONFIG_ETRAX_LED1R);
+	ret += crisv32_io_get_name(&crisv32_led2_green, CONFIG_ETRAX_LED2G);
+	ret += crisv32_io_get_name(&crisv32_led2_red, CONFIG_ETRAX_LED2R);
+	ret += crisv32_io_get_name(&crisv32_led3_green, CONFIG_ETRAX_LED3G);
+	ret += crisv32_io_get_name(&crisv32_led3_red, CONFIG_ETRAX_LED3R);
+	crisv32_io_set_dir(&crisv32_led1_green, crisv32_io_dir_out);
+	crisv32_io_set_dir(&crisv32_led1_red, crisv32_io_dir_out);
+	crisv32_io_set_dir(&crisv32_led2_green, crisv32_io_dir_out);
+	crisv32_io_set_dir(&crisv32_led2_red, crisv32_io_dir_out);
+	crisv32_io_set_dir(&crisv32_led3_green, crisv32_io_dir_out);
+	crisv32_io_set_dir(&crisv32_led3_red, crisv32_io_dir_out);
+
+	if (!strcmp(CONFIG_ETRAX_LED1G, CONFIG_ETRAX_LED1R))
+		crisv32_led1_red = dummy_led;
+	if (!strcmp(CONFIG_ETRAX_LED2G, CONFIG_ETRAX_LED2R))
+		crisv32_led2_red = dummy_led;
+
+	return ret;
+}
+
+__initcall(crisv32_io_init);
+
+int crisv32_io_get(struct crisv32_iopin* iopin,
+                   unsigned int port, unsigned int pin)
+{
+	if (port > NBR_OF_PORTS)
+		return -EINVAL;
+	if (port > crisv32_ioports[port].pin_count)
+		return -EINVAL;
+
+	iopin->bit = 1 << pin;
+	iopin->port = &crisv32_ioports[port];
+
+	if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio))
+		return -EIO;
+
+	return 0;
+}
+
+int crisv32_io_get_name(struct crisv32_iopin* iopin,
+                         char* name)
+{
+	int port;
+	int pin;
+
+	if (toupper(*name) == 'P')
+		name++;
+
+	if (toupper(*name) < 'A' || toupper(*name) > 'E')
+		return -EINVAL;
+
+	port = toupper(*name) - 'A';
+	name++;
+	pin = simple_strtoul(name, NULL, 10);
+
+	if (pin < 0 || pin > crisv32_ioports[port].pin_count)
+		return -EINVAL;
+
+	iopin->bit = 1 << pin;
+	iopin->port = &crisv32_ioports[port];
+
+	if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio))
+		return -EIO;
+
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+/* PCI I/O access stuff */
+struct cris_io_operations* cris_iops = NULL;
+EXPORT_SYMBOL(cris_iops);
+#endif
+
diff --git a/arch/cris/arch-v32/kernel/irq.c b/arch/cris/arch-v32/kernel/irq.c
new file mode 100644
index 00000000000..c78cc268513
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/irq.c
@@ -0,0 +1,413 @@
+/*
+ * Copyright (C) 2003, Axis Communications AB.
+ */
+
+#include <asm/irq.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/profile.h>
+#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
+#include <linux/threads.h>
+#include <linux/spinlock.h>
+#include <linux/kernel_stat.h>
+#include <asm/arch/hwregs/reg_map.h>
+#include <asm/arch/hwregs/reg_rdwr.h>
+#include <asm/arch/hwregs/intr_vect.h>
+#include <asm/arch/hwregs/intr_vect_defs.h>
+
+#define CPU_FIXED -1
+
+/* IRQ masks (refer to comment for crisv32_do_multiple) */
+#define TIMER_MASK (1 << (TIMER_INTR_VECT - FIRST_IRQ))
+#ifdef CONFIG_ETRAX_KGDB
+#if defined(CONFIG_ETRAX_KGDB_PORT0)
+#define IGNOREMASK (1 << (SER0_INTR_VECT - FIRST_IRQ))
+#elif defined(CONFIG_ETRAX_KGDB_PORT1)
+#define IGNOREMASK (1 << (SER1_INTR_VECT - FIRST_IRQ))
+#elif defined(CONFIG_ETRAX_KGB_PORT2)
+#define IGNOREMASK (1 << (SER2_INTR_VECT - FIRST_IRQ))
+#elif defined(CONFIG_ETRAX_KGDB_PORT3)
+#define IGNOREMASK (1 << (SER3_INTR_VECT - FIRST_IRQ))
+#endif
+#endif
+
+DEFINE_SPINLOCK(irq_lock);
+
+struct cris_irq_allocation
+{
+  int cpu; /* The CPU to which the IRQ is currently allocated. */
+  cpumask_t mask; /* The CPUs to which the IRQ may be allocated. */
+};
+
+struct cris_irq_allocation irq_allocations[NR_IRQS] =
+  {[0 ... NR_IRQS - 1] = {0, CPU_MASK_ALL}};
+
+static unsigned long irq_regs[NR_CPUS] =
+{
+  regi_irq,
+#ifdef CONFIG_SMP
+  regi_irq2,
+#endif
+};
+
+unsigned long cpu_irq_counters[NR_CPUS];
+unsigned long irq_counters[NR_REAL_IRQS];
+
+/* From irq.c. */
+extern void weird_irq(void);
+
+/* From entry.S. */
+extern void system_call(void);
+extern void nmi_interrupt(void);
+extern void multiple_interrupt(void);
+extern void gdb_handle_exception(void);
+extern void i_mmu_refill(void);
+extern void i_mmu_invalid(void);
+extern void i_mmu_access(void);
+extern void i_mmu_execute(void);
+extern void d_mmu_refill(void);
+extern void d_mmu_invalid(void);
+extern void d_mmu_access(void);
+extern void d_mmu_write(void);
+
+/* From kgdb.c. */
+extern void kgdb_init(void);
+extern void breakpoint(void);
+
+/*
+ * Build the IRQ handler stubs using macros from irq.h. First argument is the
+ * IRQ number, the second argument is the corresponding bit in
+ * intr_rw_vect_mask found in asm/arch/hwregs/intr_vect_defs.h.
+ */
+BUILD_IRQ(0x31, (1 << 0))	/* memarb */
+BUILD_IRQ(0x32, (1 << 1))	/* gen_io */
+BUILD_IRQ(0x33, (1 << 2))	/* iop0 */
+BUILD_IRQ(0x34, (1 << 3))	/* iop1 */
+BUILD_IRQ(0x35, (1 << 4))	/* iop2 */
+BUILD_IRQ(0x36, (1 << 5))	/* iop3 */
+BUILD_IRQ(0x37, (1 << 6))	/* dma0 */
+BUILD_IRQ(0x38, (1 << 7))	/* dma1 */
+BUILD_IRQ(0x39, (1 << 8))	/* dma2 */
+BUILD_IRQ(0x3a, (1 << 9))	/* dma3 */
+BUILD_IRQ(0x3b, (1 << 10))	/* dma4 */
+BUILD_IRQ(0x3c, (1 << 11))	/* dma5 */
+BUILD_IRQ(0x3d, (1 << 12))	/* dma6 */
+BUILD_IRQ(0x3e, (1 << 13))	/* dma7 */
+BUILD_IRQ(0x3f, (1 << 14))	/* dma8 */
+BUILD_IRQ(0x40, (1 << 15))	/* dma9 */
+BUILD_IRQ(0x41, (1 << 16))	/* ata */
+BUILD_IRQ(0x42, (1 << 17))	/* sser0 */
+BUILD_IRQ(0x43, (1 << 18))	/* sser1 */
+BUILD_IRQ(0x44, (1 << 19))	/* ser0 */
+BUILD_IRQ(0x45, (1 << 20))	/* ser1 */
+BUILD_IRQ(0x46, (1 << 21))	/* ser2 */
+BUILD_IRQ(0x47, (1 << 22))	/* ser3 */
+BUILD_IRQ(0x48, (1 << 23))
+BUILD_IRQ(0x49, (1 << 24))	/* eth0 */
+BUILD_IRQ(0x4a, (1 << 25))	/* eth1 */
+BUILD_TIMER_IRQ(0x4b, (1 << 26))/* timer */
+BUILD_IRQ(0x4c, (1 << 27))	/* bif_arb */
+BUILD_IRQ(0x4d, (1 << 28))	/* bif_dma */
+BUILD_IRQ(0x4e, (1 << 29))	/* ext */
+BUILD_IRQ(0x4f, (1 << 29))	/* ipi */
+
+/* Pointers to the low-level handlers. */
+static void (*interrupt[NR_IRQS])(void) = {
+	IRQ0x31_interrupt, IRQ0x32_interrupt, IRQ0x33_interrupt,
+	IRQ0x34_interrupt, IRQ0x35_interrupt, IRQ0x36_interrupt,
+	IRQ0x37_interrupt, IRQ0x38_interrupt, IRQ0x39_interrupt,
+	IRQ0x3a_interrupt, IRQ0x3b_interrupt, IRQ0x3c_interrupt,
+	IRQ0x3d_interrupt, IRQ0x3e_interrupt, IRQ0x3f_interrupt,
+	IRQ0x40_interrupt, IRQ0x41_interrupt, IRQ0x42_interrupt,
+	IRQ0x43_interrupt, IRQ0x44_interrupt, IRQ0x45_interrupt,
+	IRQ0x46_interrupt, IRQ0x47_interrupt, IRQ0x48_interrupt,
+	IRQ0x49_interrupt, IRQ0x4a_interrupt, IRQ0x4b_interrupt,
+	IRQ0x4c_interrupt, IRQ0x4d_interrupt, IRQ0x4e_interrupt,
+	IRQ0x4f_interrupt
+};
+
+void
+block_irq(int irq, int cpu)
+{
+	int intr_mask;
+        unsigned long flags;
+
+        spin_lock_irqsave(&irq_lock, flags);
+        intr_mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask);
+
+	/* Remember; 1 let thru, 0 block. */
+	intr_mask &= ~(1 << (irq - FIRST_IRQ));
+
+	REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, intr_mask);
+        spin_unlock_irqrestore(&irq_lock, flags);
+}
+
+void
+unblock_irq(int irq, int cpu)
+{
+	int intr_mask;
+        unsigned long flags;
+
+        spin_lock_irqsave(&irq_lock, flags);
+        intr_mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask);
+
+	/* Remember; 1 let thru, 0 block. */
+	intr_mask |= (1 << (irq - FIRST_IRQ));
+
+	REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, intr_mask);
+        spin_unlock_irqrestore(&irq_lock, flags);
+}
+
+/* Find out which CPU the irq should be allocated to. */
+static int irq_cpu(int irq)
+{
+	int cpu;
+        unsigned long flags;
+
+        spin_lock_irqsave(&irq_lock, flags);
+        cpu = irq_allocations[irq - FIRST_IRQ].cpu;
+
+	/* Fixed interrupts stay on the local CPU. */
+	if (cpu == CPU_FIXED)
+        {
+		spin_unlock_irqrestore(&irq_lock, flags);
+		return smp_processor_id();
+        }
+
+
+	/* Let the interrupt stay if possible */
+	if (cpu_isset(cpu, irq_allocations[irq - FIRST_IRQ].mask))
+		goto out;
+
+	/* IRQ must be moved to another CPU. */
+	cpu = first_cpu(irq_allocations[irq - FIRST_IRQ].mask);
+	irq_allocations[irq - FIRST_IRQ].cpu = cpu;
+out:
+	spin_unlock_irqrestore(&irq_lock, flags);
+	return cpu;
+}
+
+void
+mask_irq(int irq)
+{
+	int cpu;
+
+	for (cpu = 0; cpu < NR_CPUS; cpu++)
+		block_irq(irq, cpu);
+}
+
+void
+unmask_irq(int irq)
+{
+	unblock_irq(irq, irq_cpu(irq));
+}
+
+
+static unsigned int startup_crisv32_irq(unsigned int irq)
+{
+	unmask_irq(irq);
+	return 0;
+}
+
+static void shutdown_crisv32_irq(unsigned int irq)
+{
+	mask_irq(irq);
+}
+
+static void enable_crisv32_irq(unsigned int irq)
+{
+	unmask_irq(irq);
+}
+
+static void disable_crisv32_irq(unsigned int irq)
+{
+	mask_irq(irq);
+}
+
+static void ack_crisv32_irq(unsigned int irq)
+{
+}
+
+static void end_crisv32_irq(unsigned int irq)
+{
+}
+
+void set_affinity_crisv32_irq(unsigned int irq, cpumask_t dest)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&irq_lock, flags);
+	irq_allocations[irq - FIRST_IRQ].mask = dest;
+	spin_unlock_irqrestore(&irq_lock, flags);
+}
+
+static struct hw_interrupt_type crisv32_irq_type = {
+	.typename =    "CRISv32",
+	.startup =     startup_crisv32_irq,
+	.shutdown =    shutdown_crisv32_irq,
+	.enable =      enable_crisv32_irq,
+	.disable =     disable_crisv32_irq,
+	.ack =         ack_crisv32_irq,
+	.end =         end_crisv32_irq,
+	.set_affinity = set_affinity_crisv32_irq
+};
+
+void
+set_exception_vector(int n, irqvectptr addr)
+{
+	etrax_irv->v[n] = (irqvectptr) addr;
+}
+
+extern void do_IRQ(int irq, struct pt_regs * regs);
+
+void
+crisv32_do_IRQ(int irq, int block, struct pt_regs* regs)
+{
+	/* Interrupts that may not be moved to another CPU and
+         * are SA_INTERRUPT may skip blocking. This is currently
+         * only valid for the timer IRQ and the IPI and is used
+         * for the timer interrupt to avoid watchdog starvation.
+         */
+	if (!block) {
+		do_IRQ(irq, regs);
+		return;
+	}
+
+	block_irq(irq, smp_processor_id());
+	do_IRQ(irq, regs);
+
+	unblock_irq(irq, irq_cpu(irq));
+}
+
+/* If multiple interrupts occur simultaneously we get a multiple
+ * interrupt from the CPU and software has to sort out which
+ * interrupts that happened. There are two special cases here:
+ *
+ * 1. Timer interrupts may never be blocked because of the
+ *    watchdog (refer to comment in include/asr/arch/irq.h)
+ * 2. GDB serial port IRQs are unhandled here and will be handled
+ *    as a single IRQ when it strikes again because the GDB
+ *    stubb wants to save the registers in its own fashion.
+ */
+void
+crisv32_do_multiple(struct pt_regs* regs)
+{
+	int cpu;
+	int mask;
+	int masked;
+	int bit;
+
+	cpu = smp_processor_id();
+
+	/* An extra irq_enter here to prevent softIRQs to run after
+         * each do_IRQ. This will decrease the interrupt latency.
+	 */
+	irq_enter();
+
+	/* Get which IRQs that happend. */
+	masked = REG_RD_INT(intr_vect, irq_regs[cpu], r_masked_vect);
+
+	/* Calculate new IRQ mask with these IRQs disabled. */
+	mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask);
+	mask &= ~masked;
+
+	/* Timer IRQ is never masked */
+	if (masked & TIMER_MASK)
+		mask |= TIMER_MASK;
+
+	/* Block all the IRQs */
+	REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, mask);
+
+	/* Check for timer IRQ and handle it special. */
+	if (masked & TIMER_MASK) {
+	        masked &= ~TIMER_MASK;
+		do_IRQ(TIMER_INTR_VECT, regs);
+	}
+
+#ifdef IGNORE_MASK
+	/* Remove IRQs that can't be handled as multiple. */
+	masked &= ~IGNORE_MASK;
+#endif
+
+	/* Handle the rest of the IRQs. */
+	for (bit = 0; bit < 32; bit++)
+	{
+		if (masked & (1 << bit))
+			do_IRQ(bit + FIRST_IRQ, regs);
+	}
+
+	/* Unblock all the IRQs. */
+	mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask);
+	mask |= masked;
+	REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, mask);
+
+	/* This irq_exit() will trigger the soft IRQs. */
+	irq_exit();
+}
+
+/*
+ * This is called by start_kernel. It fixes the IRQ masks and setup the
+ * interrupt vector table to point to bad_interrupt pointers.
+ */
+void __init
+init_IRQ(void)
+{
+	int i;
+	int j;
+	reg_intr_vect_rw_mask vect_mask = {0};
+
+	/* Clear all interrupts masks. */
+	REG_WR(intr_vect, regi_irq, rw_mask, vect_mask);
+
+	for (i = 0; i < 256; i++)
+		etrax_irv->v[i] = weird_irq;
+
+	/* Point all IRQ's to bad handlers. */
+	for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) {
+		irq_desc[j].handler = &crisv32_irq_type;
+		set_exception_vector(i, interrupt[j]);
+	}
+
+        /* Mark Timer and IPI IRQs as CPU local */
+	irq_allocations[TIMER_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
+	irq_desc[TIMER_INTR_VECT].status |= IRQ_PER_CPU;
+	irq_allocations[IPI_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
+	irq_desc[IPI_INTR_VECT].status |= IRQ_PER_CPU;
+
+	set_exception_vector(0x00, nmi_interrupt);
+	set_exception_vector(0x30, multiple_interrupt);
+
+	/* Set up handler for various MMU bus faults. */
+	set_exception_vector(0x04, i_mmu_refill);
+	set_exception_vector(0x05, i_mmu_invalid);
+	set_exception_vector(0x06, i_mmu_access);
+	set_exception_vector(0x07, i_mmu_execute);
+	set_exception_vector(0x08, d_mmu_refill);
+	set_exception_vector(0x09, d_mmu_invalid);
+	set_exception_vector(0x0a, d_mmu_access);
+	set_exception_vector(0x0b, d_mmu_write);
+
+	/* The system-call trap is reached by "break 13". */
+	set_exception_vector(0x1d, system_call);
+
+	/* Exception handlers for debugging, both user-mode and kernel-mode. */
+
+	/* Break 8. */
+	set_exception_vector(0x18, gdb_handle_exception);
+	/* Hardware single step. */
+	set_exception_vector(0x3, gdb_handle_exception);
+	/* Hardware breakpoint. */
+	set_exception_vector(0xc, gdb_handle_exception);
+
+#ifdef CONFIG_ETRAX_KGDB
+	kgdb_init();
+	/* Everything is set up; now trap the kernel. */
+	breakpoint();
+#endif
+}
+
diff --git a/arch/cris/arch-v32/kernel/kgdb.c b/arch/cris/arch-v32/kernel/kgdb.c
new file mode 100644
index 00000000000..480e56348be
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/kgdb.c
@@ -0,0 +1,1660 @@
+/*
+ *  arch/cris/arch-v32/kernel/kgdb.c
+ *
+ *  CRIS v32 version by Orjan Friberg, Axis Communications AB.
+ *
+ *  S390 version
+ *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
+ *
+ *  Originally written by Glenn Engel, Lake Stevens Instrument Division
+ *
+ *  Contributed by HP Systems
+ *
+ *  Modified for SPARC by Stu Grossman, Cygnus Support.
+ *
+ *  Modified for Linux/MIPS (and MIPS in general) by Andreas Busse
+ *  Send complaints, suggestions etc. to <andy@waldorf-gmbh.de>
+ *
+ *  Copyright (C) 1995 Andreas Busse
+ */
+
+/* FIXME: Check the documentation. */
+
+/*
+ *  kgdb usage notes:
+ *  -----------------
+ *
+ * If you select CONFIG_ETRAX_KGDB in the configuration, the kernel will be
+ * built with different gcc flags: "-g" is added to get debug infos, and
+ * "-fomit-frame-pointer" is omitted to make debugging easier. Since the
+ * resulting kernel will be quite big (approx. > 7 MB), it will be stripped
+ * before compresion. Such a kernel will behave just as usually, except if
+ * given a "debug=<device>" command line option. (Only serial devices are
+ * allowed for <device>, i.e. no printers or the like; possible values are
+ * machine depedend and are the same as for the usual debug device, the one
+ * for logging kernel messages.) If that option is given and the device can be
+ * initialized, the kernel will connect to the remote gdb in trap_init(). The
+ * serial parameters are fixed to 8N1 and 115200 bps, for easyness of
+ * implementation.
+ *
+ * To start a debugging session, start that gdb with the debugging kernel
+ * image (the one with the symbols, vmlinux.debug) named on the command line.
+ * This file will be used by gdb to get symbol and debugging infos about the
+ * kernel. Next, select remote debug mode by
+ *    target remote <device>
+ * where <device> is the name of the serial device over which the debugged
+ * machine is connected. Maybe you have to adjust the baud rate by
+ *    set remotebaud <rate>
+ * or also other parameters with stty:
+ *    shell stty ... </dev/...
+ * If the kernel to debug has already booted, it waited for gdb and now
+ * connects, and you'll see a breakpoint being reported. If the kernel isn't
+ * running yet, start it now. The order of gdb and the kernel doesn't matter.
+ * Another thing worth knowing about in the getting-started phase is how to
+ * debug the remote protocol itself. This is activated with
+ *    set remotedebug 1
+ * gdb will then print out each packet sent or received. You'll also get some
+ * messages about the gdb stub on the console of the debugged machine.
+ *
+ * If all that works, you can use lots of the usual debugging techniques on
+ * the kernel, e.g. inspecting and changing variables/memory, setting
+ * breakpoints, single stepping and so on. It's also possible to interrupt the
+ * debugged kernel by pressing C-c in gdb. Have fun! :-)
+ *
+ * The gdb stub is entered (and thus the remote gdb gets control) in the
+ * following situations:
+ *
+ *  - If breakpoint() is called. This is just after kgdb initialization, or if
+ *    a breakpoint() call has been put somewhere into the kernel source.
+ *    (Breakpoints can of course also be set the usual way in gdb.)
+ *    In eLinux, we call breakpoint() in init/main.c after IRQ initialization.
+ *
+ *  - If there is a kernel exception, i.e. bad_super_trap() or die_if_kernel()
+ *    are entered. All the CPU exceptions are mapped to (more or less..., see
+ *    the hard_trap_info array below) appropriate signal, which are reported
+ *    to gdb. die_if_kernel() is usually called after some kind of access
+ *    error and thus is reported as SIGSEGV.
+ *
+ *  - When panic() is called. This is reported as SIGABRT.
+ *
+ *  - If C-c is received over the serial line, which is treated as
+ *    SIGINT.
+ *
+ * Of course, all these signals are just faked for gdb, since there is no
+ * signal concept as such for the kernel. It also isn't possible --obviously--
+ * to set signal handlers from inside gdb, or restart the kernel with a
+ * signal.
+ *
+ * Current limitations:
+ *
+ *  - While the kernel is stopped, interrupts are disabled for safety reasons
+ *    (i.e., variables not changing magically or the like). But this also
+ *    means that the clock isn't running anymore, and that interrupts from the
+ *    hardware may get lost/not be served in time. This can cause some device
+ *    errors...
+ *
+ *  - When single-stepping, only one instruction of the current thread is
+ *    executed, but interrupts are allowed for that time and will be serviced
+ *    if pending. Be prepared for that.
+ *
+ *  - All debugging happens in kernel virtual address space. There's no way to
+ *    access physical memory not mapped in kernel space, or to access user
+ *    space. A way to work around this is using get_user_long & Co. in gdb
+ *    expressions, but only for the current process.
+ *
+ *  - Interrupting the kernel only works if interrupts are currently allowed,
+ *    and the interrupt of the serial line isn't blocked by some other means
+ *    (IPL too high, disabled, ...)
+ *
+ *  - The gdb stub is currently not reentrant, i.e. errors that happen therein
+ *    (e.g. accessing invalid memory) may not be caught correctly. This could
+ *    be removed in future by introducing a stack of struct registers.
+ *
+ */
+
+/*
+ *  To enable debugger support, two things need to happen.  One, a
+ *  call to kgdb_init() is necessary in order to allow any breakpoints
+ *  or error conditions to be properly intercepted and reported to gdb.
+ *  Two, a breakpoint needs to be generated to begin communication.  This
+ *  is most easily accomplished by a call to breakpoint().
+ *
+ *    The following gdb commands are supported:
+ *
+ * command          function                               Return value
+ *
+ *    g             return the value of the CPU registers  hex data or ENN
+ *    G             set the value of the CPU registers     OK or ENN
+ *
+ *    mAA..AA,LLLL  Read LLLL bytes at address AA..AA      hex data or ENN
+ *    MAA..AA,LLLL: Write LLLL bytes at address AA.AA      OK or ENN
+ *
+ *    c             Resume at current address              SNN   ( signal NN)
+ *    cAA..AA       Continue at address AA..AA             SNN
+ *
+ *    s             Step one instruction                   SNN
+ *    sAA..AA       Step one instruction from AA..AA       SNN
+ *
+ *    k             kill
+ *
+ *    ?             What was the last sigval ?             SNN   (signal NN)
+ *
+ *    bBB..BB	    Set baud rate to BB..BB		   OK or BNN, then sets
+ *							   baud rate
+ *
+ * All commands and responses are sent with a packet which includes a
+ * checksum.  A packet consists of
+ *
+ * $<packet info>#<checksum>.
+ *
+ * where
+ * <packet info> :: <characters representing the command or response>
+ * <checksum>    :: < two hex digits computed as modulo 256 sum of <packetinfo>>
+ *
+ * When a packet is received, it is first acknowledged with either '+' or '-'.
+ * '+' indicates a successful transfer.  '-' indicates a failed transfer.
+ *
+ * Example:
+ *
+ * Host:                  Reply:
+ * $m0,10#2a               +$00010203040506070809101112131415#42
+ *
+ */
+
+
+#include <linux/string.h>
+#include <linux/signal.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/linkage.h>
+#include <linux/reboot.h>
+
+#include <asm/setup.h>
+#include <asm/ptrace.h>
+
+#include <asm/irq.h>
+#include <asm/arch/hwregs/reg_map.h>
+#include <asm/arch/hwregs/reg_rdwr.h>
+#include <asm/arch/hwregs/intr_vect_defs.h>
+#include <asm/arch/hwregs/ser_defs.h>
+
+/* From entry.S. */
+extern void gdb_handle_exception(void);
+/* From kgdb_asm.S. */
+extern void kgdb_handle_exception(void);
+
+static int kgdb_started = 0;
+
+/********************************* Register image ****************************/
+
+typedef
+struct register_image
+{
+	                      /* Offset */
+	unsigned int   r0;    /* 0x00 */
+	unsigned int   r1;    /* 0x04 */
+	unsigned int   r2;    /* 0x08 */
+	unsigned int   r3;    /* 0x0C */
+	unsigned int   r4;    /* 0x10 */
+	unsigned int   r5;    /* 0x14 */
+	unsigned int   r6;    /* 0x18 */
+	unsigned int   r7;    /* 0x1C */
+	unsigned int   r8;    /* 0x20; Frame pointer (if any) */
+	unsigned int   r9;    /* 0x24 */
+	unsigned int   r10;   /* 0x28 */
+	unsigned int   r11;   /* 0x2C */
+	unsigned int   r12;   /* 0x30 */
+	unsigned int   r13;   /* 0x34 */
+	unsigned int   sp;    /* 0x38; R14, Stack pointer */
+	unsigned int   acr;   /* 0x3C; R15, Address calculation register. */
+
+	unsigned char  bz;    /* 0x40; P0, 8-bit zero register */
+	unsigned char  vr;    /* 0x41; P1, Version register (8-bit) */
+	unsigned int   pid;   /* 0x42; P2, Process ID */
+	unsigned char  srs;   /* 0x46; P3, Support register select (8-bit) */
+        unsigned short wz;    /* 0x47; P4, 16-bit zero register */
+	unsigned int   exs;   /* 0x49; P5, Exception status */
+	unsigned int   eda;   /* 0x4D; P6, Exception data address */
+	unsigned int   mof;   /* 0x51; P7, Multiply overflow register */
+	unsigned int   dz;    /* 0x55; P8, 32-bit zero register */
+	unsigned int   ebp;   /* 0x59; P9, Exception base pointer */
+	unsigned int   erp;   /* 0x5D; P10, Exception return pointer. Contains the PC we are interested in. */
+	unsigned int   srp;   /* 0x61; P11, Subroutine return pointer */
+	unsigned int   nrp;   /* 0x65; P12, NMI return pointer */
+	unsigned int   ccs;   /* 0x69; P13, Condition code stack */
+	unsigned int   usp;   /* 0x6D; P14, User mode stack pointer */
+	unsigned int   spc;   /* 0x71; P15, Single step PC */
+	unsigned int   pc;    /* 0x75; Pseudo register (for the most part set to ERP). */
+
+} registers;
+
+typedef
+struct bp_register_image
+{
+	/* Support register bank 0. */
+	unsigned int   s0_0;
+	unsigned int   s1_0;
+	unsigned int   s2_0;
+	unsigned int   s3_0;
+	unsigned int   s4_0;
+	unsigned int   s5_0;
+	unsigned int   s6_0;
+	unsigned int   s7_0;
+	unsigned int   s8_0;
+	unsigned int   s9_0;
+	unsigned int   s10_0;
+	unsigned int   s11_0;
+	unsigned int   s12_0;
+	unsigned int   s13_0;
+	unsigned int   s14_0;
+	unsigned int   s15_0;
+
+	/* Support register bank 1. */
+	unsigned int   s0_1;
+	unsigned int   s1_1;
+	unsigned int   s2_1;
+	unsigned int   s3_1;
+	unsigned int   s4_1;
+	unsigned int   s5_1;
+	unsigned int   s6_1;
+	unsigned int   s7_1;
+	unsigned int   s8_1;
+	unsigned int   s9_1;
+	unsigned int   s10_1;
+	unsigned int   s11_1;
+	unsigned int   s12_1;
+	unsigned int   s13_1;
+	unsigned int   s14_1;
+	unsigned int   s15_1;
+
+	/* Support register bank 2. */
+	unsigned int   s0_2;
+	unsigned int   s1_2;
+	unsigned int   s2_2;
+	unsigned int   s3_2;
+	unsigned int   s4_2;
+	unsigned int   s5_2;
+	unsigned int   s6_2;
+	unsigned int   s7_2;
+	unsigned int   s8_2;
+	unsigned int   s9_2;
+	unsigned int   s10_2;
+	unsigned int   s11_2;
+	unsigned int   s12_2;
+	unsigned int   s13_2;
+	unsigned int   s14_2;
+	unsigned int   s15_2;
+
+	/* Support register bank 3. */
+	unsigned int   s0_3; /* BP_CTRL */
+	unsigned int   s1_3; /* BP_I0_START */
+	unsigned int   s2_3; /* BP_I0_END */
+	unsigned int   s3_3; /* BP_D0_START */
+	unsigned int   s4_3; /* BP_D0_END */
+	unsigned int   s5_3; /* BP_D1_START */
+	unsigned int   s6_3; /* BP_D1_END */
+	unsigned int   s7_3; /* BP_D2_START */
+	unsigned int   s8_3; /* BP_D2_END */
+	unsigned int   s9_3; /* BP_D3_START */
+	unsigned int   s10_3; /* BP_D3_END */
+	unsigned int   s11_3; /* BP_D4_START */
+	unsigned int   s12_3; /* BP_D4_END */
+	unsigned int   s13_3; /* BP_D5_START */
+	unsigned int   s14_3; /* BP_D5_END */
+	unsigned int   s15_3; /* BP_RESERVED */
+
+} support_registers;
+
+enum register_name
+{
+	R0,  R1,  R2,  R3,
+	R4,  R5,  R6,  R7,
+	R8,  R9,  R10, R11,
+	R12, R13, SP,  ACR,
+
+	BZ,  VR,  PID, SRS,
+	WZ,  EXS, EDA, MOF,
+	DZ,  EBP, ERP, SRP,
+	NRP, CCS, USP, SPC,
+	PC,
+
+	S0,  S1,  S2,  S3,
+	S4,  S5,  S6,  S7,
+	S8,  S9,  S10, S11,
+	S12, S13, S14, S15
+
+};
+
+/* The register sizes of the registers in register_name. An unimplemented register
+   is designated by size 0 in this array. */
+static int register_size[] =
+{
+	4, 4, 4, 4,
+	4, 4, 4, 4,
+	4, 4, 4, 4,
+	4, 4, 4, 4,
+
+	1, 1, 4, 1,
+	2, 4, 4, 4,
+	4, 4, 4, 4,
+	4, 4, 4, 4,
+
+	4,
+
+	4, 4, 4, 4,
+	4, 4, 4, 4,
+	4, 4, 4, 4,
+	4, 4, 4
+
+};
+
+/* Contains the register image of the kernel.
+   (Global so that they can be reached from assembler code.) */
+registers reg;
+support_registers sreg;
+
+/************** Prototypes for local library functions ***********************/
+
+/* Copy of strcpy from libc. */
+static char *gdb_cris_strcpy(char *s1, const char *s2);
+
+/* Copy of strlen from libc. */
+static int gdb_cris_strlen(const char *s);
+
+/* Copy of memchr from libc. */
+static void *gdb_cris_memchr(const void *s, int c, int n);
+
+/* Copy of strtol from libc. Does only support base 16. */
+static int gdb_cris_strtol(const char *s, char **endptr, int base);
+
+/********************** Prototypes for local functions. **********************/
+
+/* Write a value to a specified register regno in the register image
+   of the current thread. */
+static int write_register(int regno, char *val);
+
+/* Read a value from a specified register in the register image. Returns the
+   status of the read operation. The register value is returned in valptr. */
+static int read_register(char regno, unsigned int *valptr);
+
+/* Serial port, reads one character. ETRAX 100 specific. from debugport.c */
+int getDebugChar(void);
+
+#ifdef CONFIG_ETRAXFS_SIM
+int getDebugChar(void)
+{
+  return socketread();
+}
+#endif
+
+/* Serial port, writes one character. ETRAX 100 specific. from debugport.c */
+void putDebugChar(int val);
+
+#ifdef CONFIG_ETRAXFS_SIM
+void putDebugChar(int val)
+{
+  socketwrite((char *)&val, 1);
+}
+#endif
+
+/* Returns the character equivalent of a nibble, bit 7, 6, 5, and 4 of a byte,
+   represented by int x. */
+static char highhex(int x);
+
+/* Returns the character equivalent of a nibble, bit 3, 2, 1, and 0 of a byte,
+   represented by int x. */
+static char lowhex(int x);
+
+/* Returns the integer equivalent of a hexadecimal character. */
+static int hex(char ch);
+
+/* Convert the memory, pointed to by mem into hexadecimal representation.
+   Put the result in buf, and return a pointer to the last character
+   in buf (null). */
+static char *mem2hex(char *buf, unsigned char *mem, int count);
+
+/* Convert the array, in hexadecimal representation, pointed to by buf into
+   binary representation. Put the result in mem, and return a pointer to
+   the character after the last byte written. */
+static unsigned char *hex2mem(unsigned char *mem, char *buf, int count);
+
+/* Put the content of the array, in binary representation, pointed to by buf
+   into memory pointed to by mem, and return a pointer to
+   the character after the last byte written. */
+static unsigned char *bin2mem(unsigned char *mem, unsigned char *buf, int count);
+
+/* Await the sequence $<data>#<checksum> and store <data> in the array buffer
+   returned. */
+static void getpacket(char *buffer);
+
+/* Send $<data>#<checksum> from the <data> in the array buffer. */
+static void putpacket(char *buffer);
+
+/* Build and send a response packet in order to inform the host the
+   stub is stopped. */
+static void stub_is_stopped(int sigval);
+
+/* All expected commands are sent from remote.c. Send a response according
+   to the description in remote.c. Not static since it needs to be reached
+   from assembler code. */
+void handle_exception(int sigval);
+
+/* Performs a complete re-start from scratch. ETRAX specific. */
+static void kill_restart(void);
+
+/******************** Prototypes for global functions. ***********************/
+
+/* The string str is prepended with the GDB printout token and sent. */
+void putDebugString(const unsigned char *str, int len);
+
+/* A static breakpoint to be used at startup. */
+void breakpoint(void);
+
+/* Avoid warning as the internal_stack is not used in the C-code. */
+#define USEDVAR(name)    { if (name) { ; } }
+#define USEDFUN(name) { void (*pf)(void) = (void *)name; USEDVAR(pf) }
+
+/********************************** Packet I/O ******************************/
+/* BUFMAX defines the maximum number of characters in
+   inbound/outbound buffers */
+/* FIXME: How do we know it's enough? */
+#define BUFMAX 512
+
+/* Run-length encoding maximum length. Send 64 at most. */
+#define RUNLENMAX 64
+
+/* Definition of all valid hexadecimal characters */
+static const char hexchars[] = "0123456789abcdef";
+
+/* The inbound/outbound buffers used in packet I/O */
+static char input_buffer[BUFMAX];
+static char output_buffer[BUFMAX];
+
+/* Error and warning messages. */
+enum error_type
+{
+	SUCCESS, E01, E02, E03, E04, E05, E06,
+};
+
+static char *error_message[] =
+{
+	"",
+	"E01 Set current or general thread - H[c,g] - internal error.",
+	"E02 Change register content - P - cannot change read-only register.",
+	"E03 Thread is not alive.", /* T, not used. */
+	"E04 The command is not supported - [s,C,S,!,R,d,r] - internal error.",
+	"E05 Change register content - P - the register is not implemented..",
+	"E06 Change memory content - M - internal error.",
+};
+
+/********************************** Breakpoint *******************************/
+/* Use an internal stack in the breakpoint and interrupt response routines.
+   FIXME: How do we know the size of this stack is enough?
+   Global so it can be reached from assembler code. */
+#define INTERNAL_STACK_SIZE 1024
+char internal_stack[INTERNAL_STACK_SIZE];
+
+/* Due to the breakpoint return pointer, a state variable is needed to keep
+   track of whether it is a static (compiled) or dynamic (gdb-invoked)
+   breakpoint to be handled. A static breakpoint uses the content of register
+   ERP as it is whereas a dynamic breakpoint requires subtraction with 2
+   in order to execute the instruction. The first breakpoint is static; all
+   following are assumed to be dynamic. */
+static int dynamic_bp = 0;
+
+/********************************* String library ****************************/
+/* Single-step over library functions creates trap loops. */
+
+/* Copy char s2[] to s1[]. */
+static char*
+gdb_cris_strcpy(char *s1, const char *s2)
+{
+	char *s = s1;
+
+	for (s = s1; (*s++ = *s2++) != '\0'; )
+		;
+	return s1;
+}
+
+/* Find length of s[]. */
+static int
+gdb_cris_strlen(const char *s)
+{
+	const char *sc;
+
+	for (sc = s; *sc != '\0'; sc++)
+		;
+	return (sc - s);
+}
+
+/* Find first occurrence of c in s[n]. */
+static void*
+gdb_cris_memchr(const void *s, int c, int n)
+{
+	const unsigned char uc = c;
+	const unsigned char *su;
+
+	for (su = s; 0 < n; ++su, --n)
+		if (*su == uc)
+			return (void *)su;
+	return NULL;
+}
+/******************************* Standard library ****************************/
+/* Single-step over library functions creates trap loops. */
+/* Convert string to long. */
+static int
+gdb_cris_strtol(const char *s, char **endptr, int base)
+{
+	char *s1;
+	char *sd;
+	int x = 0;
+
+	for (s1 = (char*)s; (sd = gdb_cris_memchr(hexchars, *s1, base)) != NULL; ++s1)
+		x = x * base + (sd - hexchars);
+
+        if (endptr) {
+                /* Unconverted suffix is stored in endptr unless endptr is NULL. */
+                *endptr = s1;
+        }
+
+	return x;
+}
+
+/********************************* Register image ****************************/
+
+/* Write a value to a specified register in the register image of the current
+   thread. Returns status code SUCCESS, E02 or E05. */
+static int
+write_register(int regno, char *val)
+{
+	int status = SUCCESS;
+
+        if (regno >= R0 && regno <= ACR) {
+		/* Consecutive 32-bit registers. */
+		hex2mem((unsigned char *)&reg.r0 + (regno - R0) * sizeof(unsigned int),
+			val, sizeof(unsigned int));
+
+	} else if (regno == BZ || regno == VR || regno == WZ || regno == DZ) {
+		/* Read-only registers. */
+		status = E02;
+
+	} else if (regno == PID) {
+		/* 32-bit register. (Even though we already checked SRS and WZ, we cannot
+		   combine this with the EXS - SPC write since SRS and WZ have different size.) */
+		hex2mem((unsigned char *)&reg.pid, val, sizeof(unsigned int));
+
+	} else if (regno == SRS) {
+		/* 8-bit register. */
+		hex2mem((unsigned char *)&reg.srs, val, sizeof(unsigned char));
+
+	} else if (regno >= EXS && regno <= SPC) {
+		/* Consecutive 32-bit registers. */
+		hex2mem((unsigned char *)&reg.exs + (regno - EXS) * sizeof(unsigned int),
+			 val, sizeof(unsigned int));
+
+       } else if (regno == PC) {
+               /* Pseudo-register. Treat as read-only. */
+               status = E02;
+
+       } else if (regno >= S0 && regno <= S15) {
+               /* 32-bit registers. */
+               hex2mem((unsigned char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int), val, sizeof(unsigned int));
+	} else {
+		/* Non-existing register. */
+		status = E05;
+	}
+	return status;
+}
+
+/* Read a value from a specified register in the register image. Returns the
+   value in the register or -1 for non-implemented registers. */
+static int
+read_register(char regno, unsigned int *valptr)
+{
+	int status = SUCCESS;
+
+	/* We read the zero registers from the register struct (instead of just returning 0)
+	   to catch errors. */
+
+	if (regno >= R0 && regno <= ACR) {
+		/* Consecutive 32-bit registers. */
+		*valptr = *(unsigned int *)((char *)&reg.r0 + (regno - R0) * sizeof(unsigned int));
+
+	} else if (regno == BZ || regno == VR) {
+		/* Consecutive 8-bit registers. */
+		*valptr = (unsigned int)(*(unsigned char *)
+                                         ((char *)&reg.bz + (regno - BZ) * sizeof(char)));
+
+	} else if (regno == PID) {
+		/* 32-bit register. */
+		*valptr =  *(unsigned int *)((char *)&reg.pid);
+
+	} else if (regno == SRS) {
+		/* 8-bit register. */
+		*valptr = (unsigned int)(*(unsigned char *)((char *)&reg.srs));
+
+	} else if (regno == WZ) {
+		/* 16-bit register. */
+		*valptr = (unsigned int)(*(unsigned short *)(char *)&reg.wz);
+
+	} else if (regno >= EXS && regno <= PC) {
+		/* Consecutive 32-bit registers. */
+		*valptr = *(unsigned int *)((char *)&reg.exs + (regno - EXS) * sizeof(unsigned int));
+
+	} else if (regno >= S0 && regno <= S15) {
+		/* Consecutive 32-bit registers, located elsewhere. */
+		*valptr = *(unsigned int *)((char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int));
+
+	} else {
+		/* Non-existing register. */
+		status = E05;
+	}
+	return status;
+
+}
+
+/********************************** Packet I/O ******************************/
+/* Returns the character equivalent of a nibble, bit 7, 6, 5, and 4 of a byte,
+   represented by int x. */
+static inline char
+highhex(int x)
+{
+	return hexchars[(x >> 4) & 0xf];
+}
+
+/* Returns the character equivalent of a nibble, bit 3, 2, 1, and 0 of a byte,
+   represented by int x. */
+static inline char
+lowhex(int x)
+{
+	return hexchars[x & 0xf];
+}
+
+/* Returns the integer equivalent of a hexadecimal character. */
+static int
+hex(char ch)
+{
+	if ((ch >= 'a') && (ch <= 'f'))
+		return (ch - 'a' + 10);
+	if ((ch >= '0') && (ch <= '9'))
+		return (ch - '0');
+	if ((ch >= 'A') && (ch <= 'F'))
+		return (ch - 'A' + 10);
+	return -1;
+}
+
+/* Convert the memory, pointed to by mem into hexadecimal representation.
+   Put the result in buf, and return a pointer to the last character
+   in buf (null). */
+
+static char *
+mem2hex(char *buf, unsigned char *mem, int count)
+{
+	int i;
+	int ch;
+
+        if (mem == NULL) {
+		/* Invalid address, caught by 'm' packet handler. */
+                for (i = 0; i < count; i++) {
+                        *buf++ = '0';
+                        *buf++ = '0';
+                }
+        } else {
+                /* Valid mem address. */
+		for (i = 0; i < count; i++) {
+			ch = *mem++;
+			*buf++ = highhex (ch);
+			*buf++ = lowhex (ch);
+		}
+        }
+        /* Terminate properly. */
+	*buf = '\0';
+	return buf;
+}
+
+/* Same as mem2hex, but puts it in network byte order. */
+static char *
+mem2hex_nbo(char *buf, unsigned char *mem, int count)
+{
+	int i;
+	int ch;
+
+	mem += count - 1;
+	for (i = 0; i < count; i++) {
+		ch = *mem--;
+		*buf++ = highhex (ch);
+		*buf++ = lowhex (ch);
+        }
+
+        /* Terminate properly. */
+	*buf = '\0';
+	return buf;
+}
+
+/* Convert the array, in hexadecimal representation, pointed to by buf into
+   binary representation. Put the result in mem, and return a pointer to
+   the character after the last byte written. */
+static unsigned char*
+hex2mem(unsigned char *mem, char *buf, int count)
+{
+	int i;
+	unsigned char ch;
+	for (i = 0; i < count; i++) {
+		ch = hex (*buf++) << 4;
+		ch = ch + hex (*buf++);
+		*mem++ = ch;
+	}
+	return mem;
+}
+
+/* Put the content of the array, in binary representation, pointed to by buf
+   into memory pointed to by mem, and return a pointer to the character after
+   the last byte written.
+   Gdb will escape $, #, and the escape char (0x7d). */
+static unsigned char*
+bin2mem(unsigned char *mem, unsigned char *buf, int count)
+{
+	int i;
+	unsigned char *next;
+	for (i = 0; i < count; i++) {
+		/* Check for any escaped characters. Be paranoid and
+		   only unescape chars that should be escaped. */
+		if (*buf == 0x7d) {
+			next = buf + 1;
+			if (*next == 0x3 || *next == 0x4 || *next == 0x5D) {
+				 /* #, $, ESC */
+				buf++;
+				*buf += 0x20;
+			}
+		}
+		*mem++ = *buf++;
+	}
+	return mem;
+}
+
+/* Await the sequence $<data>#<checksum> and store <data> in the array buffer
+   returned. */
+static void
+getpacket(char *buffer)
+{
+	unsigned char checksum;
+	unsigned char xmitcsum;
+	int i;
+	int count;
+	char ch;
+
+	do {
+		while((ch = getDebugChar ()) != '$')
+			/* Wait for the start character $ and ignore all other characters */;
+		checksum = 0;
+		xmitcsum = -1;
+		count = 0;
+		/* Read until a # or the end of the buffer is reached */
+		while (count < BUFMAX) {
+			ch = getDebugChar();
+			if (ch == '#')
+				break;
+			checksum = checksum + ch;
+			buffer[count] = ch;
+			count = count + 1;
+		}
+
+		if (count >= BUFMAX)
+			continue;
+
+		buffer[count] = 0;
+
+		if (ch == '#') {
+			xmitcsum = hex(getDebugChar()) << 4;
+			xmitcsum += hex(getDebugChar());
+			if (checksum != xmitcsum) {
+				/* Wrong checksum */
+				putDebugChar('-');
+			} else {
+				/* Correct checksum */
+				putDebugChar('+');
+				/* If sequence characters are received, reply with them */
+				if (buffer[2] == ':') {
+					putDebugChar(buffer[0]);
+					putDebugChar(buffer[1]);
+					/* Remove the sequence characters from the buffer */
+					count = gdb_cris_strlen(buffer);
+					for (i = 3; i <= count; i++)
+						buffer[i - 3] = buffer[i];
+				}
+			}
+		}
+	} while (checksum != xmitcsum);
+}
+
+/* Send $<data>#<checksum> from the <data> in the array buffer. */
+
+static void
+putpacket(char *buffer)
+{
+	int checksum;
+	int runlen;
+	int encode;
+
+	do {
+		char *src = buffer;
+		putDebugChar('$');
+		checksum = 0;
+		while (*src) {
+			/* Do run length encoding */
+			putDebugChar(*src);
+			checksum += *src;
+			runlen = 0;
+			while (runlen < RUNLENMAX && *src == src[runlen]) {
+				runlen++;
+			}
+			if (runlen > 3) {
+				/* Got a useful amount */
+				putDebugChar ('*');
+				checksum += '*';
+				encode = runlen + ' ' - 4;
+				putDebugChar(encode);
+				checksum += encode;
+				src += runlen;
+			} else {
+				src++;
+			}
+		}
+		putDebugChar('#');
+		putDebugChar(highhex (checksum));
+		putDebugChar(lowhex (checksum));
+	} while(kgdb_started && (getDebugChar() != '+'));
+}
+
+/* The string str is prepended with the GDB printout token and sent. Required
+   in traditional implementations. */
+void
+putDebugString(const unsigned char *str, int len)
+{
+	/* Move SPC forward if we are single-stepping. */
+	asm("spchere:");
+	asm("move $spc, $r10");
+	asm("cmp.d spchere, $r10");
+	asm("bne nosstep");
+	asm("nop");
+	asm("move.d spccont, $r10");
+	asm("move $r10, $spc");
+	asm("nosstep:");
+
+        output_buffer[0] = 'O';
+        mem2hex(&output_buffer[1], (unsigned char *)str, len);
+        putpacket(output_buffer);
+
+	asm("spccont:");
+}
+
+/********************************** Handle exceptions ************************/
+/* Build and send a response packet in order to inform the host the
+   stub is stopped. TAAn...:r...;n...:r...;n...:r...;
+                    AA = signal number
+                    n... = register number (hex)
+                    r... = register contents
+                    n... = `thread'
+                    r... = thread process ID.  This is a hex integer.
+                    n... = other string not starting with valid hex digit.
+                    gdb should ignore this n,r pair and go on to the next.
+                    This way we can extend the protocol. */
+static void
+stub_is_stopped(int sigval)
+{
+	char *ptr = output_buffer;
+	unsigned int reg_cont;
+
+	/* Send trap type (converted to signal) */
+
+	*ptr++ = 'T';
+	*ptr++ = highhex(sigval);
+	*ptr++ = lowhex(sigval);
+
+	if (((reg.exs & 0xff00) >> 8) == 0xc) {
+
+		/* Some kind of hardware watchpoint triggered. Find which one
+		   and determine its type (read/write/access).  */
+		int S, bp, trig_bits = 0, rw_bits = 0;
+		int trig_mask = 0;
+		unsigned int *bp_d_regs = &sreg.s3_3;
+		/* In a lot of cases, the stopped data address will simply be EDA.
+		   In some cases, we adjust it to match the watched data range.
+		   (We don't want to change the actual EDA though). */
+		unsigned int stopped_data_address;
+		/* The S field of EXS. */
+		S = (reg.exs & 0xffff0000) >> 16;
+
+		if (S & 1) {
+			/* Instruction watchpoint. */
+			/* FIXME: Check against, and possibly adjust reported EDA. */
+		} else {
+			/* Data watchpoint.  Find the one that triggered. */
+			for (bp = 0; bp < 6; bp++) {
+
+				/* Dx_RD, Dx_WR in the S field of EXS for this BP. */
+				int bitpos_trig = 1 + bp * 2;
+				/* Dx_BPRD, Dx_BPWR in BP_CTRL for this BP. */
+				int bitpos_config = 2 + bp * 4;
+
+				/* Get read/write trig bits for this BP. */
+				trig_bits = (S & (3 << bitpos_trig)) >> bitpos_trig;
+
+				/* Read/write config bits for this BP. */
+				rw_bits = (sreg.s0_3 & (3 << bitpos_config)) >> bitpos_config;
+				if (trig_bits) {
+					/* Sanity check: the BP shouldn't trigger for accesses
+					   that it isn't configured for. */
+					if ((rw_bits == 0x1 && trig_bits != 0x1) ||
+					    (rw_bits == 0x2 && trig_bits != 0x2))
+						panic("Invalid r/w trigging for this BP");
+
+					/* Mark this BP as trigged for future reference. */
+					trig_mask |= (1 << bp);
+
+					if (reg.eda >= bp_d_regs[bp * 2] &&
+					    reg.eda <= bp_d_regs[bp * 2 + 1]) {
+						/* EDA withing range for this BP; it must be the one
+						   we're looking for. */
+						stopped_data_address = reg.eda;
+						break;
+					}
+				}
+			}
+			if (bp < 6) {
+				/* Found a trigged BP with EDA within its configured data range. */
+			} else if (trig_mask) {
+				/* Something triggered, but EDA doesn't match any BP's range. */
+				for (bp = 0; bp < 6; bp++) {
+					/* Dx_BPRD, Dx_BPWR in BP_CTRL for this BP. */
+					int bitpos_config = 2 + bp * 4;
+
+					/* Read/write config bits for this BP (needed later). */
+					rw_bits = (sreg.s0_3 & (3 << bitpos_config)) >> bitpos_config;
+
+					if (trig_mask & (1 << bp)) {
+						/* EDA within 31 bytes of the configured start address? */
+						if (reg.eda + 31 >= bp_d_regs[bp * 2]) {
+							/* Changing the reported address to match
+							   the start address of the first applicable BP. */
+							stopped_data_address = bp_d_regs[bp * 2];
+							break;
+						} else {
+							/* We continue since we might find another useful BP. */
+							printk("EDA doesn't match trigged BP's range");
+						}
+					}
+				}
+			}
+
+			/* No match yet? */
+			BUG_ON(bp >= 6);
+			/* Note that we report the type according to what the BP is configured
+			   for (otherwise we'd never report an 'awatch'), not according to how
+			   it trigged. We did check that the trigged bits match what the BP is
+			   configured for though. */
+			if (rw_bits == 0x1) {
+				/* read */
+				strncpy(ptr, "rwatch", 6);
+				ptr += 6;
+			} else if (rw_bits == 0x2) {
+				/* write */
+				strncpy(ptr, "watch", 5);
+				ptr += 5;
+			} else if (rw_bits == 0x3) {
+				/* access */
+				strncpy(ptr, "awatch", 6);
+				ptr += 6;
+			} else {
+				panic("Invalid r/w bits for this BP.");
+			}
+
+			*ptr++ = ':';
+			/* Note that we don't read_register(EDA, ...) */
+			ptr = mem2hex_nbo(ptr, (unsigned char *)&stopped_data_address, register_size[EDA]);
+			*ptr++ = ';';
+		}
+	}
+	/* Only send PC, frame and stack pointer. */
+	read_register(PC, &reg_cont);
+	*ptr++ = highhex(PC);
+	*ptr++ = lowhex(PC);
+	*ptr++ = ':';
+	ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[PC]);
+	*ptr++ = ';';
+
+	read_register(R8, &reg_cont);
+	*ptr++ = highhex(R8);
+	*ptr++ = lowhex(R8);
+	*ptr++ = ':';
+	ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[R8]);
+	*ptr++ = ';';
+
+	read_register(SP, &reg_cont);
+	*ptr++ = highhex(SP);
+	*ptr++ = lowhex(SP);
+	*ptr++ = ':';
+	ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[SP]);
+	*ptr++ = ';';
+
+	/* Send ERP as well; this will save us an entire register fetch in some cases. */
+        read_register(ERP, &reg_cont);
+        *ptr++ = highhex(ERP);
+        *ptr++ = lowhex(ERP);
+        *ptr++ = ':';
+        ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[ERP]);
+        *ptr++ = ';';
+
+	/* null-terminate and send it off */
+	*ptr = 0;
+	putpacket(output_buffer);
+}
+
+/* Returns the size of an instruction that has a delay slot. */
+
+int insn_size(unsigned long pc)
+{
+	unsigned short opcode = *(unsigned short *)pc;
+	int size = 0;
+
+	switch ((opcode & 0x0f00) >> 8) {
+	case 0x0:
+	case 0x9:
+	case 0xb:
+		size = 2;
+		break;
+	case 0xe:
+	case 0xf:
+		size = 6;
+		break;
+	case 0xd:
+		/* Could be 4 or 6; check more bits. */
+		if ((opcode & 0xff) == 0xff)
+			size = 4;
+		else
+			size = 6;
+		break;
+	default:
+		panic("Couldn't find size of opcode 0x%x at 0x%lx\n", opcode, pc);
+	}
+
+	return size;
+}
+
+void register_fixup(int sigval)
+{
+	/* Compensate for ACR push at the beginning of exception handler. */
+	reg.sp += 4;
+
+	/* Standard case. */
+	reg.pc = reg.erp;
+	if (reg.erp & 0x1) {
+		/* Delay slot bit set.  Report as stopped on proper instruction.  */
+		if (reg.spc) {
+			/* Rely on SPC if set. */
+			reg.pc = reg.spc;
+		} else {
+			/* Calculate the PC from the size of the instruction
+			   that the delay slot we're in belongs to. */
+			reg.pc += insn_size(reg.erp & ~1) - 1 ;
+		}
+	}
+
+	if ((reg.exs & 0x3) == 0x0) {
+		/* Bits 1 - 0 indicate the type of memory operation performed
+		   by the interrupted instruction. 0 means no memory operation,
+		   and EDA is undefined in that case. We zero it to avoid confusion. */
+		reg.eda = 0;
+	}
+
+	if (sigval == SIGTRAP) {
+		/* Break 8, single step or hardware breakpoint exception. */
+
+		/* Check IDX field of EXS. */
+		if (((reg.exs & 0xff00) >> 8) == 0x18) {
+
+			/* Break 8. */
+
+                        /* Static (compiled) breakpoints must return to the next instruction
+			   in order to avoid infinite loops (default value of ERP). Dynamic
+			   (gdb-invoked) must subtract the size of the break instruction from
+			   the ERP so that the instruction that was originally in the break
+			   instruction's place will be run when we return from the exception. */
+			if (!dynamic_bp) {
+				/* Assuming that all breakpoints are dynamic from now on. */
+				dynamic_bp = 1;
+			} else {
+
+				/* Only if not in a delay slot. */
+				if (!(reg.erp & 0x1)) {
+					reg.erp -= 2;
+					reg.pc -= 2;
+				}
+			}
+
+		} else if (((reg.exs & 0xff00) >> 8) == 0x3) {
+			/* Single step. */
+			/* Don't fiddle with S1. */
+
+		} else if (((reg.exs & 0xff00) >> 8) == 0xc) {
+
+			/* Hardware watchpoint exception. */
+
+			/* SPC has been updated so that we will get a single step exception
+			   when we return, but we don't want that. */
+			reg.spc = 0;
+
+			/* Don't fiddle with S1. */
+		}
+
+	} else if (sigval == SIGINT) {
+		/* Nothing special. */
+	}
+}
+
+static void insert_watchpoint(char type, int addr, int len)
+{
+	/* Breakpoint/watchpoint types (GDB terminology):
+	   0 = memory breakpoint for instructions
+	   (not supported; done via memory write instead)
+	   1 = hardware breakpoint for instructions (supported)
+	   2 = write watchpoint (supported)
+	   3 = read watchpoint (supported)
+	   4 = access watchpoint (supported) */
+
+	if (type < '1' || type > '4') {
+		output_buffer[0] = 0;
+		return;
+	}
+
+	/* Read watchpoints are set as access watchpoints, because of GDB's
+	   inability to deal with pure read watchpoints. */
+	if (type == '3')
+		type = '4';
+
+	if (type == '1') {
+		/* Hardware (instruction) breakpoint. */
+		/* Bit 0 in BP_CTRL holds the configuration for I0. */
+		if (sreg.s0_3 & 0x1) {
+			/* Already in use. */
+			gdb_cris_strcpy(output_buffer, error_message[E04]);
+			return;
+		}
+		/* Configure. */
+		sreg.s1_3 = addr;
+		sreg.s2_3 = (addr + len - 1);
+		sreg.s0_3 |= 1;
+	} else {
+		int bp;
+		unsigned int *bp_d_regs = &sreg.s3_3;
+
+		/* The watchpoint allocation scheme is the simplest possible.
+		   For example, if a region is watched for read and
+		   a write watch is requested, a new watchpoint will
+		   be used. Also, if a watch for a region that is already
+		   covered by one or more existing watchpoints, a new
+		   watchpoint will be used. */
+
+		/* First, find a free data watchpoint. */
+		for (bp = 0; bp < 6; bp++) {
+			/* Each data watchpoint's control registers occupy 2 bits
+			   (hence the 3), starting at bit 2 for D0 (hence the 2)
+			   with 4 bits between for each watchpoint (yes, the 4). */
+			if (!(sreg.s0_3 & (0x3 << (2 + (bp * 4))))) {
+				break;
+			}
+		}
+
+		if (bp > 5) {
+			/* We're out of watchpoints. */
+			gdb_cris_strcpy(output_buffer, error_message[E04]);
+			return;
+		}
+
+		/* Configure the control register first. */
+		if (type == '3' || type == '4') {
+			/* Trigger on read. */
+			sreg.s0_3 |= (1 << (2 + bp * 4));
+		}
+		if (type == '2' || type == '4') {
+			/* Trigger on write. */
+			sreg.s0_3 |= (2 << (2 + bp * 4));
+		}
+
+		/* Ugly pointer arithmetics to configure the watched range. */
+		bp_d_regs[bp * 2] = addr;
+		bp_d_regs[bp * 2 + 1] = (addr + len - 1);
+	}
+
+	/* Set the S1 flag to enable watchpoints. */
+	reg.ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT));
+	gdb_cris_strcpy(output_buffer, "OK");
+}
+
+static void remove_watchpoint(char type, int addr, int len)
+{
+	/* Breakpoint/watchpoint types:
+	   0 = memory breakpoint for instructions
+	   (not supported; done via memory write instead)
+	   1 = hardware breakpoint for instructions (supported)
+	   2 = write watchpoint (supported)
+	   3 = read watchpoint (supported)
+	   4 = access watchpoint (supported) */
+	if (type < '1' || type > '4') {
+		output_buffer[0] = 0;
+		return;
+	}
+
+	/* Read watchpoints are set as access watchpoints, because of GDB's
+	   inability to deal with pure read watchpoints. */
+	if (type == '3')
+		type = '4';
+
+	if (type == '1') {
+		/* Hardware breakpoint. */
+		/* Bit 0 in BP_CTRL holds the configuration for I0. */
+		if (!(sreg.s0_3 & 0x1)) {
+			/* Not in use. */
+			gdb_cris_strcpy(output_buffer, error_message[E04]);
+			return;
+		}
+		/* Deconfigure. */
+		sreg.s1_3 = 0;
+		sreg.s2_3 = 0;
+		sreg.s0_3 &= ~1;
+	} else {
+		int bp;
+		unsigned int *bp_d_regs = &sreg.s3_3;
+		/* Try to find a watchpoint that is configured for the
+		   specified range, then check that read/write also matches. */
+
+		/* Ugly pointer arithmetic, since I cannot rely on a
+		   single switch (addr) as there may be several watchpoints with
+		   the same start address for example. */
+
+		for (bp = 0; bp < 6; bp++) {
+			if (bp_d_regs[bp * 2] == addr &&
+			    bp_d_regs[bp * 2 + 1] == (addr + len - 1)) {
+				/* Matching range. */
+				int bitpos = 2 + bp * 4;
+				int rw_bits;
+
+				/* Read/write bits for this BP. */
+				rw_bits = (sreg.s0_3 & (0x3 << bitpos)) >> bitpos;
+
+				if ((type == '3' && rw_bits == 0x1) ||
+				    (type == '2' && rw_bits == 0x2) ||
+				    (type == '4' && rw_bits == 0x3)) {
+					/* Read/write matched. */
+					break;
+				}
+			}
+		}
+
+		if (bp > 5) {
+			/* No watchpoint matched. */
+			gdb_cris_strcpy(output_buffer, error_message[E04]);
+			return;
+		}
+
+		/* Found a matching watchpoint. Now, deconfigure it by
+		   both disabling read/write in bp_ctrl and zeroing its
+		   start/end addresses. */
+		sreg.s0_3 &= ~(3 << (2 + (bp * 4)));
+		bp_d_regs[bp * 2] = 0;
+		bp_d_regs[bp * 2 + 1] = 0;
+	}
+
+	/* Note that we don't clear the S1 flag here. It's done when continuing.  */
+	gdb_cris_strcpy(output_buffer, "OK");
+}
+
+
+
+/* All expected commands are sent from remote.c. Send a response according
+   to the description in remote.c. */
+void
+handle_exception(int sigval)
+{
+	/* Avoid warning of not used. */
+
+	USEDFUN(handle_exception);
+	USEDVAR(internal_stack[0]);
+
+	register_fixup(sigval);
+
+	/* Send response. */
+	stub_is_stopped(sigval);
+
+	for (;;) {
+		output_buffer[0] = '\0';
+		getpacket(input_buffer);
+		switch (input_buffer[0]) {
+			case 'g':
+				/* Read registers: g
+				   Success: Each byte of register data is described by two hex digits.
+				   Registers are in the internal order for GDB, and the bytes
+				   in a register  are in the same order the machine uses.
+				   Failure: void. */
+			{
+				char *buf;
+				/* General and special registers. */
+				buf = mem2hex(output_buffer, (char *)&reg, sizeof(registers));
+				/* Support registers. */
+				/* -1 because of the null termination that mem2hex adds. */
+				mem2hex(buf,
+					(char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)),
+					16 * sizeof(unsigned int));
+				break;
+			}
+			case 'G':
+				/* Write registers. GXX..XX
+				   Each byte of register data  is described by two hex digits.
+				   Success: OK
+				   Failure: void. */
+				/* General and special registers. */
+				hex2mem((char *)&reg, &input_buffer[1], sizeof(registers));
+				/* Support registers. */
+				hex2mem((char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)),
+					&input_buffer[1] + sizeof(registers),
+					16 * sizeof(unsigned int));
+				gdb_cris_strcpy(output_buffer, "OK");
+				break;
+
+			case 'P':
+				/* Write register. Pn...=r...
+				   Write register n..., hex value without 0x, with value r...,
+				   which contains a hex value without 0x and two hex digits
+				   for each byte in the register (target byte order). P1f=11223344 means
+				   set register 31 to 44332211.
+				   Success: OK
+				   Failure: E02, E05 */
+				{
+					char *suffix;
+					int regno = gdb_cris_strtol(&input_buffer[1], &suffix, 16);
+					int status;
+
+					status = write_register(regno, suffix+1);
+
+					switch (status) {
+						case E02:
+							/* Do not support read-only registers. */
+							gdb_cris_strcpy(output_buffer, error_message[E02]);
+							break;
+						case E05:
+							/* Do not support non-existing registers. */
+							gdb_cris_strcpy(output_buffer, error_message[E05]);
+							break;
+						default:
+							/* Valid register number. */
+							gdb_cris_strcpy(output_buffer, "OK");
+							break;
+					}
+				}
+				break;
+
+			case 'm':
+				/* Read from memory. mAA..AA,LLLL
+				   AA..AA is the address and LLLL is the length.
+				   Success: XX..XX is the memory content.  Can be fewer bytes than
+				   requested if only part of the data may be read. m6000120a,6c means
+				   retrieve 108 byte from base address 6000120a.
+				   Failure: void. */
+				{
+                                        char *suffix;
+					unsigned char *addr = (unsigned char *)gdb_cris_strtol(&input_buffer[1],
+                                                                                               &suffix, 16);
+					int len = gdb_cris_strtol(suffix+1, 0, 16);
+
+					/* Bogus read (i.e. outside the kernel's
+					   segment)? . */
+					if (!((unsigned int)addr >= 0xc0000000 &&
+					      (unsigned int)addr < 0xd0000000))
+						addr = NULL;
+
+                                        mem2hex(output_buffer, addr, len);
+                                }
+				break;
+
+			case 'X':
+				/* Write to memory. XAA..AA,LLLL:XX..XX
+				   AA..AA is the start address,  LLLL is the number of bytes, and
+				   XX..XX is the binary data.
+				   Success: OK
+				   Failure: void. */
+			case 'M':
+				/* Write to memory. MAA..AA,LLLL:XX..XX
+				   AA..AA is the start address,  LLLL is the number of bytes, and
+				   XX..XX is the hexadecimal data.
+				   Success: OK
+				   Failure: void. */
+				{
+					char *lenptr;
+					char *dataptr;
+					unsigned char *addr = (unsigned char *)gdb_cris_strtol(&input_buffer[1],
+										      &lenptr, 16);
+					int len = gdb_cris_strtol(lenptr+1, &dataptr, 16);
+					if (*lenptr == ',' && *dataptr == ':') {
+						if (input_buffer[0] == 'M') {
+							hex2mem(addr, dataptr + 1, len);
+						} else /* X */ {
+							bin2mem(addr, dataptr + 1, len);
+						}
+						gdb_cris_strcpy(output_buffer, "OK");
+					}
+					else {
+						gdb_cris_strcpy(output_buffer, error_message[E06]);
+					}
+				}
+				break;
+
+			case 'c':
+				/* Continue execution. cAA..AA
+				   AA..AA is the address where execution is resumed. If AA..AA is
+				   omitted, resume at the present address.
+				   Success: return to the executing thread.
+				   Failure: will never know. */
+
+				if (input_buffer[1] != '\0') {
+					/* FIXME: Doesn't handle address argument. */
+					gdb_cris_strcpy(output_buffer, error_message[E04]);
+					break;
+				}
+
+				/* Before continuing, make sure everything is set up correctly. */
+
+				/* Set the SPC to some unlikely value.  */
+				reg.spc = 0;
+				/* Set the S1 flag to 0 unless some watchpoint is enabled (since setting
+				   S1 to 0 would also disable watchpoints). (Note that bits 26-31 in BP_CTRL
+				   are reserved, so don't check against those). */
+				if ((sreg.s0_3 & 0x3fff) == 0) {
+					reg.ccs &= ~(1 << (S_CCS_BITNR + CCS_SHIFT));
+				}
+
+				return;
+
+			case 's':
+				/* Step. sAA..AA
+				   AA..AA is the address where execution is resumed. If AA..AA is
+				   omitted, resume at the present address. Success: return to the
+				   executing thread. Failure: will never know. */
+
+				if (input_buffer[1] != '\0') {
+					/* FIXME: Doesn't handle address argument. */
+					gdb_cris_strcpy(output_buffer, error_message[E04]);
+					break;
+				}
+
+				/* Set the SPC to PC, which is where we'll return
+				   (deduced previously). */
+				reg.spc = reg.pc;
+
+				/* Set the S1 (first stacked, not current) flag, which will
+				   kick into action when we rfe. */
+				reg.ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT));
+				return;
+
+                       case 'Z':
+
+                               /* Insert breakpoint or watchpoint, Ztype,addr,length.
+                                  Remote protocol says: A remote target shall return an empty string
+                                  for an unrecognized breakpoint or watchpoint packet type. */
+                               {
+                                       char *lenptr;
+                                       char *dataptr;
+                                       int addr = gdb_cris_strtol(&input_buffer[3], &lenptr, 16);
+                                       int len = gdb_cris_strtol(lenptr + 1, &dataptr, 16);
+                                       char type = input_buffer[1];
+
+				       insert_watchpoint(type, addr, len);
+                                       break;
+                               }
+
+                       case 'z':
+                               /* Remove breakpoint or watchpoint, Ztype,addr,length.
+                                  Remote protocol says: A remote target shall return an empty string
+                                  for an unrecognized breakpoint or watchpoint packet type. */
+                               {
+                                       char *lenptr;
+                                       char *dataptr;
+                                       int addr = gdb_cris_strtol(&input_buffer[3], &lenptr, 16);
+                                       int len = gdb_cris_strtol(lenptr + 1, &dataptr, 16);
+                                       char type = input_buffer[1];
+
+                                       remove_watchpoint(type, addr, len);
+                                       break;
+                               }
+
+
+			case '?':
+				/* The last signal which caused a stop. ?
+				   Success: SAA, where AA is the signal number.
+				   Failure: void. */
+				output_buffer[0] = 'S';
+				output_buffer[1] = highhex(sigval);
+				output_buffer[2] = lowhex(sigval);
+				output_buffer[3] = 0;
+				break;
+
+			case 'D':
+				/* Detach from host. D
+				   Success: OK, and return to the executing thread.
+				   Failure: will never know */
+				putpacket("OK");
+				return;
+
+			case 'k':
+			case 'r':
+				/* kill request or reset request.
+				   Success: restart of target.
+				   Failure: will never know. */
+				kill_restart();
+				break;
+
+			case 'C':
+			case 'S':
+			case '!':
+			case 'R':
+			case 'd':
+				/* Continue with signal sig. Csig;AA..AA
+				   Step with signal sig. Ssig;AA..AA
+				   Use the extended remote protocol. !
+				   Restart the target system. R0
+				   Toggle debug flag. d
+				   Search backwards. tAA:PP,MM
+				   Not supported: E04 */
+
+				/* FIXME: What's the difference between not supported
+				   and ignored (below)? */
+				gdb_cris_strcpy(output_buffer, error_message[E04]);
+				break;
+
+			default:
+				/* The stub should ignore other request and send an empty
+				   response ($#<checksum>). This way we can extend the protocol and GDB
+				   can tell whether the stub it is talking to uses the old or the new. */
+				output_buffer[0] = 0;
+				break;
+		}
+		putpacket(output_buffer);
+	}
+}
+
+void
+kgdb_init(void)
+{
+	reg_intr_vect_rw_mask intr_mask;
+	reg_ser_rw_intr_mask ser_intr_mask;
+
+	/* Configure the kgdb serial port. */
+#if defined(CONFIG_ETRAX_KGDB_PORT0)
+	/* Note: no shortcut registered (not handled by multiple_interrupt).
+	   See entry.S.  */
+	set_exception_vector(SER0_INTR_VECT, kgdb_handle_exception);
+	/* Enable the ser irq in the global config. */
+	intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
+	intr_mask.ser0 = 1;
+	REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
+
+	ser_intr_mask = REG_RD(ser, regi_ser0, rw_intr_mask);
+	ser_intr_mask.data_avail = regk_ser_yes;
+	REG_WR(ser, regi_ser0, rw_intr_mask, ser_intr_mask);
+#elif defined(CONFIG_ETRAX_KGDB_PORT1)
+	/* Note: no shortcut registered (not handled by multiple_interrupt).
+	   See entry.S.  */
+	set_exception_vector(SER1_INTR_VECT, kgdb_handle_exception);
+	/* Enable the ser irq in the global config. */
+	intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
+	intr_mask.ser1 = 1;
+	REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
+
+	ser_intr_mask = REG_RD(ser, regi_ser1, rw_intr_mask);
+	ser_intr_mask.data_avail = regk_ser_yes;
+	REG_WR(ser, regi_ser1, rw_intr_mask, ser_intr_mask);
+#elif defined(CONFIG_ETRAX_KGDB_PORT2)
+	/* Note: no shortcut registered (not handled by multiple_interrupt).
+	   See entry.S.  */
+	set_exception_vector(SER2_INTR_VECT, kgdb_handle_exception);
+	/* Enable the ser irq in the global config. */
+	intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
+	intr_mask.ser2 = 1;
+	REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
+
+	ser_intr_mask = REG_RD(ser, regi_ser2, rw_intr_mask);
+	ser_intr_mask.data_avail = regk_ser_yes;
+	REG_WR(ser, regi_ser2, rw_intr_mask, ser_intr_mask);
+#elif defined(CONFIG_ETRAX_KGDB_PORT3)
+	/* Note: no shortcut registered (not handled by multiple_interrupt).
+	   See entry.S.  */
+	set_exception_vector(SER3_INTR_VECT, kgdb_handle_exception);
+	/* Enable the ser irq in the global config. */
+	intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
+	intr_mask.ser3 = 1;
+	REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
+
+	ser_intr_mask = REG_RD(ser, regi_ser3, rw_intr_mask);
+	ser_intr_mask.data_avail = regk_ser_yes;
+	REG_WR(ser, regi_ser3, rw_intr_mask, ser_intr_mask);
+#endif
+
+}
+/* Performs a complete re-start from scratch. */
+static void
+kill_restart(void)
+{
+	machine_restart("");
+}
+
+/* Use this static breakpoint in the start-up only. */
+
+void
+breakpoint(void)
+{
+	kgdb_started = 1;
+	dynamic_bp = 0;     /* This is a static, not a dynamic breakpoint. */
+	__asm__ volatile ("break 8"); /* Jump to kgdb_handle_breakpoint. */
+}
+
+/****************************** End of file **********************************/
diff --git a/arch/cris/arch-v32/kernel/kgdb_asm.S b/arch/cris/arch-v32/kernel/kgdb_asm.S
new file mode 100644
index 00000000000..b350dd279ed
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/kgdb_asm.S
@@ -0,0 +1,552 @@
+/*
+ *  Copyright (C) 2004 Axis Communications AB
+ *
+ * Code for handling break 8, hardware breakpoint, single step, and serial
+ * port exceptions for kernel debugging purposes.
+ */
+
+#include <linux/config.h>
+#include <asm/arch/hwregs/intr_vect.h>
+
+	;; Exported functions.
+	.globl kgdb_handle_exception
+
+kgdb_handle_exception:
+
+;; Create a register image of the caller.
+;;
+;; First of all, save the ACR on the stack since we need it for address calculations.
+;; We put it into the register struct later.
+
+  subq     4, $sp
+  move.d   $acr, [$sp]
+
+;; Now we are free to use ACR all we want.
+;; If we were running this handler with interrupts on, we would have to be careful
+;; to save and restore CCS manually, but since we aren't we treat it like every other
+;; register.
+
+  move.d   reg,  $acr
+  move.d   $r0,  [$acr]        ; Save R0 (start of register struct)
+  addq     4,    $acr
+  move.d   $r1,  [$acr]        ; Save R1
+  addq     4,    $acr
+  move.d   $r2,  [$acr]        ; Save R2
+  addq     4,    $acr
+  move.d   $r3,  [$acr]        ; Save R3
+  addq     4,    $acr
+  move.d   $r4,  [$acr]        ; Save R4
+  addq     4,    $acr
+  move.d   $r5,  [$acr]        ; Save R5
+  addq     4,    $acr
+  move.d   $r6,  [$acr]        ; Save R6
+  addq     4,    $acr
+  move.d   $r7,  [$acr]        ; Save R7
+  addq     4,    $acr
+  move.d   $r8,  [$acr]        ; Save R8
+  addq     4,    $acr
+  move.d   $r9,  [$acr]        ; Save R9
+  addq     4,    $acr
+  move.d   $r10, [$acr]        ; Save R10
+  addq     4,    $acr
+  move.d   $r11, [$acr]        ; Save R11
+  addq     4,    $acr
+  move.d   $r12, [$acr]        ; Save R12
+  addq     4,    $acr
+  move.d   $r13, [$acr]        ; Save R13
+  addq     4,    $acr
+  move.d   $sp,  [$acr]        ; Save SP (R14)
+  addq     4,    $acr
+
+  ;; The ACR register is already saved on the stack, so pop it from there.
+  move.d   [$sp],$r0
+  move.d   $r0,  [$acr]
+  addq     4,    $acr
+
+  move     $bz,  [$acr]
+  addq     1,    $acr
+  move     $vr,  [$acr]
+  addq     1,    $acr
+  move     $pid, [$acr]
+  addq     4,    $acr
+  move     $srs, [$acr]
+  addq     1,    $acr
+  move     $wz,  [$acr]
+  addq     2,    $acr
+  move     $exs, [$acr]
+  addq     4,    $acr
+  move     $eda, [$acr]
+  addq     4,    $acr
+  move     $mof, [$acr]
+  addq     4,    $acr
+  move     $dz,  [$acr]
+  addq     4,    $acr
+  move     $ebp, [$acr]
+  addq     4,    $acr
+  move     $erp, [$acr]
+  addq     4,    $acr
+  move     $srp, [$acr]
+  addq     4,    $acr
+  move     $nrp, [$acr]
+  addq     4,    $acr
+  move     $ccs, [$acr]
+  addq     4,    $acr
+  move     $usp, [$acr]
+  addq     4,    $acr
+  move     $spc, [$acr]
+  addq     4,     $acr
+
+;; Skip the pseudo-PC.
+  addq     4,     $acr
+
+;; Save the support registers in bank 0 - 3.
+  clear.d $r1 ; Bank counter
+  move.d  sreg, $acr
+
+;; Bank 0
+  move    $r1,  $srs
+  nop
+  nop
+  nop
+  move    $s0,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s1,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s2,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s3,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s4,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s5,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s6,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s7,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s8,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s9,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s10,  $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s11,  $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s12,  $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+
+  ;; Nothing in S13 - S15, bank 0
+  clear.d [$acr]
+  addq    4,     $acr
+  clear.d [$acr]
+  addq    4,     $acr
+  clear.d [$acr]
+  addq    4,     $acr
+
+;; Bank 1 and bank 2 have the same layout, hence the loop.
+  addq    1, $r1
+1:
+  move    $r1,  $srs
+  nop
+  nop
+  nop
+  move    $s0,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s1,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s2,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s3,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s4,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s5,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s6,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+
+  ;; Nothing in S7 - S15, bank 1 and 2
+  clear.d [$acr]
+  addq    4,     $acr
+  clear.d [$acr]
+  addq    4,     $acr
+  clear.d [$acr]
+  addq    4,     $acr
+  clear.d [$acr]
+  addq    4,     $acr
+  clear.d [$acr]
+  addq    4,     $acr
+  clear.d [$acr]
+  addq    4,     $acr
+  clear.d [$acr]
+  addq    4,     $acr
+  clear.d [$acr]
+  addq    4,     $acr
+  clear.d [$acr]
+  addq    4,     $acr
+
+  addq 1, $r1
+  cmpq 3, $r1
+  bne 1b
+  nop
+
+;; Bank 3
+  move    $r1,  $srs
+  nop
+  nop
+  nop
+  move    $s0,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s1,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s2,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s3,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s4,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s5,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s6,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s7,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s8,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s9,   $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s10,  $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s11,  $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s12,  $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s13,  $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+  move    $s14,  $r0
+  move.d  $r0,   [$acr]
+  addq    4,     $acr
+;; Nothing in S15, bank 3
+  clear.d [$acr]
+  addq    4,     $acr
+
+;; Check what got us here: get IDX field of EXS.
+  move $exs,    $r10
+  and.d 0xff00, $r10
+  lsrq 8,       $r10
+#if defined(CONFIG_ETRAX_KGDB_PORT0)
+  cmp.d SER0_INTR_VECT,   $r10 ; IRQ for serial port 0
+  beq sigint
+  nop
+#elif defined(CONFIG_ETRAX_KGDB_PORT1)
+  cmp.d SER1_INTR_VECT,   $r10 ; IRQ for serial port 1
+  beq sigint
+  nop
+#elif defined(CONFIG_ETRAX_KGDB_PORT2)
+  cmp.d SER2_INTR_VECT,   $r10 ; IRQ for serial port 2
+  beq sigint
+  nop
+#elif defined(CONFIG_ETRAX_KGDB_PORT3)
+  cmp.d SER3_INTR_VECT,   $r10 ; IRQ for serial port 3
+  beq sigint
+  nop
+#endif
+;; Multiple interrupt must be due to serial break.
+  cmp.d 0x30,   $r10 ; Multiple interrupt
+  beq sigint
+  nop
+;; Neither of those? Then it's a sigtrap.
+  ba handle_comm
+  moveq 5, $r10      ; Set SIGTRAP (delay slot)
+
+sigint:
+  ;; Serial interrupt; get character
+  jsr getDebugChar
+  nop                ; Delay slot
+  cmp.b 3, $r10      ; \003 (Ctrl-C)?
+  bne return         ; No, get out of here
+  nop
+  moveq 2, $r10      ; Set SIGINT
+
+;;
+;; Handle the communication
+;;
+handle_comm:
+  move.d   internal_stack+1020, $sp ; Use the internal stack which grows upwards
+  jsr      handle_exception         ; Interactive routine
+  nop
+
+;;
+;; Return to the caller
+;;
+return:
+
+;; First of all, write the support registers.
+  clear.d $r1 ; Bank counter
+  move.d  sreg, $acr
+
+;; Bank 0
+  move    $r1,  $srs
+  nop
+  nop
+  nop
+  move.d  [$acr], $r0
+  move    $r0,    $s0
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s1
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s2
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s3
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s4
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s5
+  addq    4,      $acr
+
+;; Nothing in S6 - S7, bank 0.
+  addq    4,      $acr
+  addq    4,      $acr
+
+  move.d  [$acr], $r0
+  move    $r0,    $s8
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s9
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s10
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s11
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s12
+  addq    4,      $acr
+
+;; Nothing in S13 - S15, bank 0
+  addq    4,      $acr
+  addq    4,      $acr
+  addq    4,      $acr
+
+;; Bank 1 and bank 2 have the same layout, hence the loop.
+  addq    1, $r1
+2:
+  move    $r1,  $srs
+  nop
+  nop
+  nop
+  move.d  [$acr], $r0
+  move    $r0,    $s0
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s1
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s2
+  addq    4,      $acr
+
+;; S3 (MM_CAUSE) is read-only.
+  addq    4,      $acr
+
+  move.d  [$acr], $r0
+  move    $r0,    $s4
+  addq    4,      $acr
+
+;; FIXME: Actually write S5/S6? (Affects MM_CAUSE.)
+  addq    4,      $acr
+  addq    4,      $acr
+
+;; Nothing in S7 - S15, bank 1 and 2
+  addq    4,      $acr
+  addq    4,      $acr
+  addq    4,      $acr
+  addq    4,      $acr
+  addq    4,      $acr
+  addq    4,      $acr
+  addq    4,      $acr
+  addq    4,      $acr
+  addq    4,      $acr
+
+  addq 1, $r1
+  cmpq 3, $r1
+  bne 2b
+  nop
+
+;; Bank 3
+  move    $r1,  $srs
+  nop
+  nop
+  nop
+  move.d  [$acr], $r0
+  move    $r0,    $s0
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s1
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s2
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s3
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s4
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s5
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s6
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s7
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s8
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s9
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s10
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s11
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s12
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s13
+  addq    4,      $acr
+  move.d  [$acr], $r0
+  move    $r0,    $s14
+  addq    4,      $acr
+
+;; Nothing in S15, bank 3
+  addq    4,      $acr
+
+;; Now, move on to the regular register restoration process.
+
+   move.d  reg,    $acr   ; Reset ACR to point at the beginning of the register image
+   move.d  [$acr], $r0    ; Restore R0
+   addq    4,      $acr
+   move.d  [$acr], $r1    ; Restore R1
+   addq    4,      $acr
+   move.d  [$acr], $r2    ; Restore R2
+   addq    4,      $acr
+   move.d  [$acr], $r3    ; Restore R3
+   addq    4,      $acr
+   move.d  [$acr], $r4    ; Restore R4
+   addq    4,      $acr
+   move.d  [$acr], $r5    ; Restore R5
+   addq    4,      $acr
+   move.d  [$acr], $r6    ; Restore R6
+   addq    4,      $acr
+   move.d  [$acr], $r7    ; Restore R7
+   addq    4,      $acr
+   move.d  [$acr], $r8    ; Restore R8
+   addq    4,      $acr
+   move.d  [$acr], $r9    ; Restore R9
+   addq    4,      $acr
+   move.d  [$acr], $r10   ; Restore R10
+   addq    4,      $acr
+   move.d  [$acr], $r11   ; Restore R11
+   addq    4,      $acr
+   move.d  [$acr], $r12   ; Restore R12
+   addq    4,      $acr
+   move.d  [$acr], $r13   ; Restore R13
+
+;;
+;; We restore all registers, even though some of them probably haven't changed.
+;;
+
+   addq    4,      $acr
+   move.d  [$acr], $sp    ; Restore SP (R14)
+
+   ;; ACR cannot be restored just yet.
+   addq    8,      $acr
+
+   ;; Skip BZ, VR.
+   addq    2,      $acr
+
+   move    [$acr], $pid   ; Restore PID
+   addq    4,      $acr
+   move    [$acr], $srs   ; Restore SRS
+   nop
+   nop
+   nop
+   addq    1,      $acr
+
+   ;; Skip WZ.
+   addq    2,      $acr
+
+   move    [$acr], $exs    ; Restore EXS.
+   addq    4,      $acr
+   move    [$acr], $eda    ; Restore EDA.
+   addq    4,      $acr
+   move    [$acr], $mof    ; Restore MOF.
+
+   ;; Skip DZ.
+   addq    8,      $acr
+
+   move    [$acr], $ebp    ; Restore EBP.
+   addq    4,      $acr
+   move    [$acr], $erp    ; Restore ERP.
+   addq    4,      $acr
+   move    [$acr], $srp    ; Restore SRP.
+   addq    4,      $acr
+   move    [$acr], $nrp    ; Restore NRP.
+   addq    4,      $acr
+   move    [$acr], $ccs    ; Restore CCS like an ordinary register.
+   addq    4,      $acr
+   move    [$acr], $usp    ; Restore USP
+   addq    4,      $acr
+   move    [$acr], $spc    ; Restore SPC
+                           ; No restoration of pseudo-PC of course.
+
+   move.d  reg,    $acr    ; Reset ACR to point at the beginning of the register image
+   add.d   15*4,   $acr
+   move.d  [$acr], $acr    ; Finally, restore ACR.
+   rete                    ; Same as jump ERP
+   rfe                     ; Shifts CCS
diff --git a/arch/cris/arch-v32/kernel/pinmux.c b/arch/cris/arch-v32/kernel/pinmux.c
new file mode 100644
index 00000000000..a2b8aa37c1b
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/pinmux.c
@@ -0,0 +1,229 @@
+/*
+ * Allocator for I/O pins. All pins are allocated to GPIO at bootup.
+ * Unassigned pins and GPIO pins can be allocated to a fixed interface
+ * or the I/O processor instead.
+ *
+ * Copyright (c) 2004 Axis Communications AB.
+ */
+
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/spinlock.h>
+#include <asm/arch/hwregs/reg_map.h>
+#include <asm/arch/hwregs/reg_rdwr.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/hwregs/pinmux_defs.h>
+
+#undef DEBUG
+
+#define PORT_PINS 18
+#define PORTS 4
+
+static char pins[PORTS][PORT_PINS];
+static DEFINE_SPINLOCK(pinmux_lock);
+
+static void crisv32_pinmux_set(int port);
+
+int
+crisv32_pinmux_init(void)
+{
+	static int initialized = 0;
+
+	if (!initialized) {
+		reg_pinmux_rw_pa pa = REG_RD(pinmux, regi_pinmux, rw_pa);
+		initialized = 1;
+		pa.pa0 = pa.pa1 = pa.pa2 = pa.pa3 =
+		pa.pa4 = pa.pa5 = pa.pa6 = pa.pa7 = regk_pinmux_yes;
+		REG_WR(pinmux, regi_pinmux, rw_pa, pa);
+		crisv32_pinmux_alloc(PORT_B, 0, PORT_PINS - 1, pinmux_gpio);
+		crisv32_pinmux_alloc(PORT_C, 0, PORT_PINS - 1, pinmux_gpio);
+		crisv32_pinmux_alloc(PORT_D, 0, PORT_PINS - 1, pinmux_gpio);
+		crisv32_pinmux_alloc(PORT_E, 0, PORT_PINS - 1, pinmux_gpio);
+	}
+
+	return 0;
+}
+
+int
+crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode mode)
+{
+	int i;
+	unsigned long flags;
+
+	crisv32_pinmux_init();
+
+	if (port > PORTS)
+		return -EINVAL;
+
+	spin_lock_irqsave(&pinmux_lock, flags);
+
+	for (i = first_pin; i <= last_pin; i++)
+	{
+		if ((pins[port][i] != pinmux_none) && (pins[port][i] != pinmux_gpio) &&
+		    (pins[port][i] != mode))
+		{
+			spin_unlock_irqrestore(&pinmux_lock, flags);
+#ifdef DEBUG
+			panic("Pinmux alloc failed!\n");
+#endif
+			return -EPERM;
+		}
+	}
+
+	for (i = first_pin; i <= last_pin; i++)
+		pins[port][i] = mode;
+
+	crisv32_pinmux_set(port);
+
+	spin_unlock_irqrestore(&pinmux_lock, flags);
+
+	return 0;
+}
+
+int
+crisv32_pinmux_alloc_fixed(enum fixed_function function)
+{
+	int ret = -EINVAL;
+	char saved[sizeof pins];
+	unsigned long flags;
+
+	spin_lock_irqsave(&pinmux_lock, flags);
+
+	/* Save internal data for recovery */
+	memcpy(saved, pins, sizeof pins);
+
+	reg_pinmux_rw_hwprot hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
+
+	switch(function)
+	{
+	case pinmux_ser1:
+		ret = crisv32_pinmux_alloc(PORT_C, 4, 7, pinmux_fixed);
+		hwprot.ser1 = regk_pinmux_yes;
+		break;
+	case pinmux_ser2:
+		ret = crisv32_pinmux_alloc(PORT_C, 8, 11, pinmux_fixed);
+		hwprot.ser2 = regk_pinmux_yes;
+		break;
+	case pinmux_ser3:
+		ret = crisv32_pinmux_alloc(PORT_C, 12, 15, pinmux_fixed);
+		hwprot.ser3 = regk_pinmux_yes;
+		break;
+	case pinmux_sser0:
+		ret = crisv32_pinmux_alloc(PORT_C, 0, 3, pinmux_fixed);
+		ret |= crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed);
+		hwprot.sser0 = regk_pinmux_yes;
+		break;
+	case pinmux_sser1:
+		ret = crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed);
+		hwprot.sser1 = regk_pinmux_yes;
+		break;
+	case pinmux_ata0:
+		ret = crisv32_pinmux_alloc(PORT_D, 5, 7, pinmux_fixed);
+		ret |= crisv32_pinmux_alloc(PORT_D, 15, 17, pinmux_fixed);
+		hwprot.ata0 = regk_pinmux_yes;
+		break;
+	case pinmux_ata1:
+		ret = crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed);
+		ret |= crisv32_pinmux_alloc(PORT_E, 17, 17, pinmux_fixed);
+		hwprot.ata1 = regk_pinmux_yes;
+		break;
+	case pinmux_ata2:
+		ret = crisv32_pinmux_alloc(PORT_C, 11, 15, pinmux_fixed);
+		ret |= crisv32_pinmux_alloc(PORT_E, 3, 3, pinmux_fixed);
+		hwprot.ata2 = regk_pinmux_yes;
+		break;
+	case pinmux_ata3:
+		ret = crisv32_pinmux_alloc(PORT_C, 8, 10, pinmux_fixed);
+		ret |= crisv32_pinmux_alloc(PORT_C, 0, 2, pinmux_fixed);
+		hwprot.ata2 = regk_pinmux_yes;
+		break;
+	case pinmux_ata:
+		ret = crisv32_pinmux_alloc(PORT_B, 0, 15, pinmux_fixed);
+		ret |= crisv32_pinmux_alloc(PORT_D, 8, 15, pinmux_fixed);
+		hwprot.ata = regk_pinmux_yes;
+		break;
+	case pinmux_eth1:
+		ret = crisv32_pinmux_alloc(PORT_E, 0, 17, pinmux_fixed);
+		hwprot.eth1 = regk_pinmux_yes;
+		hwprot.eth1_mgm = regk_pinmux_yes;
+		break;
+	case pinmux_timer:
+		ret = crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed);
+		hwprot.timer = regk_pinmux_yes;
+		spin_unlock_irqrestore(&pinmux_lock, flags);
+		return ret;
+	}
+
+	if (!ret)
+		REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
+	else
+		memcpy(pins, saved, sizeof pins);
+
+  spin_unlock_irqrestore(&pinmux_lock, flags);
+
+  return ret;
+}
+
+void
+crisv32_pinmux_set(int port)
+{
+	int i;
+	int gpio_val = 0;
+	int iop_val = 0;
+
+	for (i = 0; i < PORT_PINS; i++)
+	{
+		if (pins[port][i] == pinmux_gpio)
+			gpio_val |= (1 << i);
+		else if (pins[port][i] == pinmux_iop)
+			iop_val |= (1 << i);
+	}
+
+	REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_pb_gio + 8*port, gpio_val);
+	REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_pb_iop + 8*port, iop_val);
+
+#ifdef DEBUG
+       crisv32_pinmux_dump();
+#endif
+}
+
+int
+crisv32_pinmux_dealloc(int port, int first_pin, int last_pin)
+{
+	int i;
+	unsigned long flags;
+
+	crisv32_pinmux_init();
+
+	if (port > PORTS)
+		return -EINVAL;
+
+	spin_lock_irqsave(&pinmux_lock, flags);
+
+	for (i = first_pin; i <= last_pin; i++)
+		pins[port][i] = pinmux_none;
+
+	crisv32_pinmux_set(port);
+	spin_unlock_irqrestore(&pinmux_lock, flags);
+
+	return 0;
+}
+
+void
+crisv32_pinmux_dump(void)
+{
+	int i, j;
+
+	crisv32_pinmux_init();
+
+	for (i = 0; i < PORTS; i++)
+	{
+		printk("Port %c\n", 'B'+i);
+		for (j = 0; j < PORT_PINS; j++)
+			printk("  Pin %d = %d\n", j, pins[i][j]);
+	}
+}
+
+__initcall(crisv32_pinmux_init);
diff --git a/arch/cris/arch-v32/kernel/process.c b/arch/cris/arch-v32/kernel/process.c
new file mode 100644
index 00000000000..882be42114f
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/process.c
@@ -0,0 +1,270 @@
+/*
+ *  Copyright (C) 2000-2003  Axis Communications AB
+ *
+ *  Authors:   Bjorn Wesen (bjornw@axis.com)
+ *             Mikael Starvik (starvik@axis.com)
+ *             Tobias Anderberg (tobiasa@axis.com), CRISv32 port.
+ *
+ * This file handles the architecture-dependent parts of process handling..
+ */
+
+#include <linux/config.h>
+#include <linux/sched.h>
+#include <linux/err.h>
+#include <linux/fs.h>
+#include <linux/slab.h>
+#include <asm/arch/hwregs/reg_rdwr.h>
+#include <asm/arch/hwregs/reg_map.h>
+#include <asm/arch/hwregs/timer_defs.h>
+#include <asm/arch/hwregs/intr_vect_defs.h>
+
+extern void stop_watchdog(void);
+
+#ifdef CONFIG_ETRAX_GPIO
+extern void etrax_gpio_wake_up_check(void); /* Defined in drivers/gpio.c. */
+#endif
+
+extern int cris_hlt_counter;
+
+/* We use this if we don't have any better idle routine. */
+void default_idle(void)
+{
+	local_irq_disable();
+	if (!need_resched() && !cris_hlt_counter) {
+	        /* Halt until exception. */
+		__asm__ volatile("ei    \n\t"
+                                 "halt      ");
+	}
+	local_irq_enable();
+}
+
+/*
+ * Free current thread data structures etc..
+ */
+
+extern void deconfigure_bp(long pid);
+void exit_thread(void)
+{
+	deconfigure_bp(current->pid);
+}
+
+/*
+ * If the watchdog is enabled, disable interrupts and enter an infinite loop.
+ * The watchdog will reset the CPU after 0.1s. If the watchdog isn't enabled
+ * then enable it and wait.
+ */
+extern void arch_enable_nmi(void);
+
+void
+hard_reset_now(void)
+{
+	/*
+	 * Don't declare this variable elsewhere.  We don't want any other
+	 * code to know about it than the watchdog handler in entry.S and
+	 * this code, implementing hard reset through the watchdog.
+	 */
+#if defined(CONFIG_ETRAX_WATCHDOG)
+	extern int cause_of_death;
+#endif
+
+	printk("*** HARD RESET ***\n");
+	local_irq_disable();
+
+#if defined(CONFIG_ETRAX_WATCHDOG)
+	cause_of_death = 0xbedead;
+#else
+{
+	reg_timer_rw_wd_ctrl wd_ctrl = {0};
+
+	stop_watchdog();
+
+	wd_ctrl.key = 16;	/* Arbitrary key. */
+	wd_ctrl.cnt = 1;	/* Minimum time. */
+	wd_ctrl.cmd = regk_timer_start;
+
+        arch_enable_nmi();
+	REG_WR(timer, regi_timer, rw_wd_ctrl, wd_ctrl);
+}
+#endif
+
+	while (1)
+		; /* Wait for reset. */
+}
+
+/*
+ * Return saved PC of a blocked thread.
+ */
+unsigned long thread_saved_pc(struct task_struct *t)
+{
+	return (unsigned long)user_regs(t->thread_info)->erp;
+}
+
+static void
+kernel_thread_helper(void* dummy, int (*fn)(void *), void * arg)
+{
+	fn(arg);
+	do_exit(-1); /* Should never be called, return bad exit value. */
+}
+
+/* Create a kernel thread. */
+int
+kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
+{
+	struct pt_regs regs;
+
+	memset(&regs, 0, sizeof(regs));
+
+        /* Don't use r10 since that is set to 0 in copy_thread. */
+	regs.r11 = (unsigned long) fn;
+	regs.r12 = (unsigned long) arg;
+	regs.erp = (unsigned long) kernel_thread_helper;
+	regs.ccs = 1 << (I_CCS_BITNR + CCS_SHIFT);
+
+	/* Create the new process. */
+        return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
+}
+
+/*
+ * Setup the child's kernel stack with a pt_regs and call switch_stack() on it.
+ * It will be unnested during _resume and _ret_from_sys_call when the new thread
+ * is scheduled.
+ *
+ * Also setup the thread switching structure which is used to keep
+ * thread-specific data during _resumes.
+ */
+
+extern asmlinkage void ret_from_fork(void);
+
+int
+copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
+	unsigned long unused,
+	struct task_struct *p, struct pt_regs *regs)
+{
+	struct pt_regs *childregs;
+	struct switch_stack *swstack;
+
+	/*
+	 * Put the pt_regs structure at the end of the new kernel stack page and
+	 * fix it up. Note: the task_struct doubles as the kernel stack for the
+	 * task.
+	 */
+	childregs = user_regs(p->thread_info);
+	*childregs = *regs;	/* Struct copy of pt_regs. */
+        p->set_child_tid = p->clear_child_tid = NULL;
+        childregs->r10 = 0;	/* Child returns 0 after a fork/clone. */
+
+	/* Set a new TLS ?
+	 * The TLS is in $mof beacuse it is the 5th argument to sys_clone.
+	 */
+	if (p->mm && (clone_flags & CLONE_SETTLS)) {
+		p->thread_info->tls = regs->mof;
+	}
+
+	/* Put the switch stack right below the pt_regs. */
+	swstack = ((struct switch_stack *) childregs) - 1;
+
+	/* Paramater to ret_from_sys_call. 0 is don't restart the syscall. */
+	swstack->r9 = 0;
+
+	/*
+	 * We want to return into ret_from_sys_call after the _resume.
+	 * ret_from_fork will call ret_from_sys_call.
+	 */
+	swstack->return_ip = (unsigned long) ret_from_fork;
+
+	/* Fix the user-mode and kernel-mode stackpointer. */
+	p->thread.usp = usp;
+	p->thread.ksp = (unsigned long) swstack;
+
+	return 0;
+}
+
+/*
+ * Be aware of the "magic" 7th argument in the four system-calls below.
+ * They need the latest stackframe, which is put as the 7th argument by
+ * entry.S. The previous arguments are dummies or actually used, but need
+ * to be defined to reach the 7th argument.
+ *
+ * N.B.: Another method to get the stackframe is to use current_regs(). But
+ * it returns the latest stack-frame stacked when going from _user mode_ and
+ * some of these (at least sys_clone) are called from kernel-mode sometimes
+ * (for example during kernel_thread, above) and thus cannot use it. Thus,
+ * to be sure not to get any surprises, we use the method for the other calls
+ * as well.
+ */
+asmlinkage int
+sys_fork(long r10, long r11, long r12, long r13, long mof, long srp,
+	struct pt_regs *regs)
+{
+	return do_fork(SIGCHLD, rdusp(), regs, 0, NULL, NULL);
+}
+
+/* FIXME: Is parent_tid/child_tid really third/fourth argument? Update lib? */
+asmlinkage int
+sys_clone(unsigned long newusp, unsigned long flags, int *parent_tid, int *child_tid,
+	unsigned long tls, long srp, struct pt_regs *regs)
+{
+	if (!newusp)
+		newusp = rdusp();
+
+	return do_fork(flags, newusp, regs, 0, parent_tid, child_tid);
+}
+
+/*
+ * vfork is a system call in i386 because of register-pressure - maybe
+ * we can remove it and handle it in libc but we put it here until then.
+ */
+asmlinkage int
+sys_vfork(long r10, long r11, long r12, long r13, long mof, long srp,
+	struct pt_regs *regs)
+{
+	return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, rdusp(), regs, 0, NULL, NULL);
+}
+
+/* sys_execve() executes a new program. */
+asmlinkage int
+sys_execve(const char *fname, char **argv, char **envp, long r13, long mof, long srp,
+	struct pt_regs *regs)
+{
+	int error;
+	char *filename;
+
+	filename = getname(fname);
+	error = PTR_ERR(filename);
+
+	if (IS_ERR(filename))
+	        goto out;
+
+	error = do_execve(filename, argv, envp, regs);
+	putname(filename);
+ out:
+	return error;
+}
+
+unsigned long
+get_wchan(struct task_struct *p)
+{
+	/* TODO */
+	return 0;
+}
+#undef last_sched
+#undef first_sched
+
+void show_regs(struct pt_regs * regs)
+{
+	unsigned long usp = rdusp();
+        printk("ERP: %08lx SRP: %08lx  CCS: %08lx USP: %08lx MOF: %08lx\n",
+		regs->erp, regs->srp, regs->ccs, usp, regs->mof);
+
+	printk(" r0: %08lx  r1: %08lx   r2: %08lx  r3: %08lx\n",
+		regs->r0, regs->r1, regs->r2, regs->r3);
+
+	printk(" r4: %08lx  r5: %08lx   r6: %08lx  r7: %08lx\n",
+		regs->r4, regs->r5, regs->r6, regs->r7);
+
+	printk(" r8: %08lx  r9: %08lx  r10: %08lx r11: %08lx\n",
+		regs->r8, regs->r9, regs->r10, regs->r11);
+
+	printk("r12: %08lx r13: %08lx oR10: %08lx\n",
+		regs->r12, regs->r13, regs->orig_r10);
+}
diff --git a/arch/cris/arch-v32/kernel/ptrace.c b/arch/cris/arch-v32/kernel/ptrace.c
new file mode 100644
index 00000000000..208489da2a8
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/ptrace.c
@@ -0,0 +1,597 @@
+/*
+ * Copyright (C) 2000-2003, Axis Communications AB.
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/smp_lock.h>
+#include <linux/errno.h>
+#include <linux/ptrace.h>
+#include <linux/user.h>
+#include <linux/signal.h>
+#include <linux/security.h>
+
+#include <asm/uaccess.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/system.h>
+#include <asm/processor.h>
+#include <asm/arch/hwregs/supp_reg.h>
+
+/*
+ * Determines which bits in CCS the user has access to.
+ * 1 = access, 0 = no access.
+ */
+#define CCS_MASK 0x00087c00     /* SXNZVC */
+
+#define SBIT_USER (1 << (S_CCS_BITNR + CCS_SHIFT))
+
+static int put_debugreg(long pid, unsigned int regno, long data);
+static long get_debugreg(long pid, unsigned int regno);
+static unsigned long get_pseudo_pc(struct task_struct *child);
+void deconfigure_bp(long pid);
+
+extern unsigned long cris_signal_return_page;
+
+/*
+ * Get contents of register REGNO in task TASK.
+ */
+long get_reg(struct task_struct *task, unsigned int regno)
+{
+	/* USP is a special case, it's not in the pt_regs struct but
+	 * in the tasks thread struct
+	 */
+	unsigned long ret;
+
+	if (regno <= PT_EDA)
+		ret = ((unsigned long *)user_regs(task->thread_info))[regno];
+	else if (regno == PT_USP)
+		ret = task->thread.usp;
+	else if (regno == PT_PPC)
+		ret = get_pseudo_pc(task);
+	else if (regno <= PT_MAX)
+		ret = get_debugreg(task->pid, regno);
+	else
+		ret = 0;
+
+	return ret;
+}
+
+/*
+ * Write contents of register REGNO in task TASK.
+ */
+int put_reg(struct task_struct *task, unsigned int regno, unsigned long data)
+{
+	if (regno <= PT_EDA)
+		((unsigned long *)user_regs(task->thread_info))[regno] = data;
+	else if (regno == PT_USP)
+		task->thread.usp = data;
+	else if (regno == PT_PPC) {
+		/* Write pseudo-PC to ERP only if changed. */
+		if (data != get_pseudo_pc(task))
+			((unsigned long *)user_regs(task->thread_info))[PT_ERP] = data;
+	} else if (regno <= PT_MAX)
+		return put_debugreg(task->pid, regno, data);
+	else
+		return -1;
+	return 0;
+}
+
+/*
+ * Called by kernel/ptrace.c when detaching.
+ *
+ * Make sure the single step bit is not set.
+ */
+void
+ptrace_disable(struct task_struct *child)
+{
+	unsigned long tmp;
+
+	/* Deconfigure SPC and S-bit. */
+	tmp = get_reg(child, PT_CCS) & ~SBIT_USER;
+	put_reg(child, PT_CCS, tmp);
+	put_reg(child, PT_SPC, 0);
+
+	/* Deconfigure any watchpoints associated with the child. */
+	deconfigure_bp(child->pid);
+}
+
+
+asmlinkage int
+sys_ptrace(long request, long pid, long addr, long data)
+{
+	struct task_struct *child;
+	int ret;
+	unsigned long __user *datap = (unsigned long __user *)data;
+
+	lock_kernel();
+	ret = -EPERM;
+
+	if (request == PTRACE_TRACEME) {
+		/* are we already being traced? */
+		if (current->ptrace & PT_PTRACED)
+			goto out;
+		ret = security_ptrace(current->parent, current);
+		if (ret)
+			goto out;
+		/* set the ptrace bit in the process flags. */
+		current->ptrace |= PT_PTRACED;
+		ret = 0;
+		goto out;
+	}
+
+	ret = -ESRCH;
+	read_lock(&tasklist_lock);
+	child = find_task_by_pid(pid);
+
+	if (child)
+		get_task_struct(child);
+
+	read_unlock(&tasklist_lock);
+
+	if (!child)
+		goto out;
+
+	ret = -EPERM;
+
+	if (pid == 1)		/* Leave the init process alone! */
+		goto out_tsk;
+
+	if (request == PTRACE_ATTACH) {
+		ret = ptrace_attach(child);
+		goto out_tsk;
+	}
+
+	ret = ptrace_check_attach(child, request == PTRACE_KILL);
+	if (ret < 0)
+		goto out_tsk;
+
+	switch (request) {
+		/* Read word at location address. */
+		case PTRACE_PEEKTEXT:
+		case PTRACE_PEEKDATA: {
+			unsigned long tmp;
+			int copied;
+
+			ret = -EIO;
+
+			/* The signal trampoline page is outside the normal user-addressable
+			 * space but still accessible. This is hack to make it possible to
+			 * access the signal handler code in GDB.
+			 */
+			if ((addr & PAGE_MASK) == cris_signal_return_page) {
+				/* The trampoline page is globally mapped, no page table to traverse.*/
+				tmp = *(unsigned long*)addr;
+			} else {
+				copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0);
+
+				if (copied != sizeof(tmp))
+					break;
+			}
+
+			ret = put_user(tmp,datap);
+			break;
+		}
+
+		/* Read the word at location address in the USER area. */
+		case PTRACE_PEEKUSR: {
+			unsigned long tmp;
+
+			ret = -EIO;
+			if ((addr & 3) || addr < 0 || addr > PT_MAX << 2)
+				break;
+
+			tmp = get_reg(child, addr >> 2);
+			ret = put_user(tmp, datap);
+			break;
+		}
+
+		/* Write the word at location address. */
+		case PTRACE_POKETEXT:
+		case PTRACE_POKEDATA:
+			ret = 0;
+
+			if (access_process_vm(child, addr, &data, sizeof(data), 1) == sizeof(data))
+				break;
+
+			ret = -EIO;
+			break;
+
+ 		/* Write the word at location address in the USER area. */
+		case PTRACE_POKEUSR:
+			ret = -EIO;
+			if ((addr & 3) || addr < 0 || addr > PT_MAX << 2)
+				break;
+
+			addr >>= 2;
+
+			if (addr == PT_CCS) {
+				/* don't allow the tracing process to change stuff like
+				 * interrupt enable, kernel/user bit, dma enables etc.
+				 */
+				data &= CCS_MASK;
+				data |= get_reg(child, PT_CCS) & ~CCS_MASK;
+			}
+			if (put_reg(child, addr, data))
+				break;
+			ret = 0;
+			break;
+
+		case PTRACE_SYSCALL:
+		case PTRACE_CONT:
+			ret = -EIO;
+
+			if (!valid_signal(data))
+				break;
+
+			/* Continue means no single-step. */
+			put_reg(child, PT_SPC, 0);
+
+			if (!get_debugreg(child->pid, PT_BP_CTRL)) {
+				unsigned long tmp;
+				/* If no h/w bp configured, disable S bit. */
+				tmp = get_reg(child, PT_CCS) & ~SBIT_USER;
+				put_reg(child, PT_CCS, tmp);
+			}
+
+			if (request == PTRACE_SYSCALL) {
+				set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
+			}
+			else {
+				clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
+			}
+
+			child->exit_code = data;
+
+			/* TODO: make sure any pending breakpoint is killed */
+			wake_up_process(child);
+			ret = 0;
+
+			break;
+
+ 		/* Make the child exit by sending it a sigkill. */
+		case PTRACE_KILL:
+			ret = 0;
+
+			if (child->exit_state == EXIT_ZOMBIE)
+				break;
+
+			child->exit_code = SIGKILL;
+
+			/* Deconfigure single-step and h/w bp. */
+			ptrace_disable(child);
+
+			/* TODO: make sure any pending breakpoint is killed */
+			wake_up_process(child);
+			break;
+
+		/* Set the trap flag. */
+		case PTRACE_SINGLESTEP:	{
+			unsigned long tmp;
+			ret = -EIO;
+
+			/* Set up SPC if not set already (in which case we have
+			   no other choice but to trust it). */
+			if (!get_reg(child, PT_SPC)) {
+				/* In case we're stopped in a delay slot. */
+				tmp = get_reg(child, PT_ERP) & ~1;
+				put_reg(child, PT_SPC, tmp);
+			}
+			tmp = get_reg(child, PT_CCS) | SBIT_USER;
+			put_reg(child, PT_CCS, tmp);
+
+			if (!valid_signal(data))
+				break;
+
+			clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
+
+			/* TODO: set some clever breakpoint mechanism... */
+
+			child->exit_code = data;
+			wake_up_process(child);
+			ret = 0;
+			break;
+
+		}
+		case PTRACE_DETACH:
+			ret = ptrace_detach(child, data);
+			break;
+
+		/* Get all GP registers from the child. */
+		case PTRACE_GETREGS: {
+		  	int i;
+			unsigned long tmp;
+
+			for (i = 0; i <= PT_MAX; i++) {
+				tmp = get_reg(child, i);
+
+				if (put_user(tmp, datap)) {
+					ret = -EFAULT;
+					goto out_tsk;
+				}
+
+				datap++;
+			}
+
+			ret = 0;
+			break;
+		}
+
+		/* Set all GP registers in the child. */
+		case PTRACE_SETREGS: {
+			int i;
+			unsigned long tmp;
+
+			for (i = 0; i <= PT_MAX; i++) {
+				if (get_user(tmp, datap)) {
+					ret = -EFAULT;
+					goto out_tsk;
+				}
+
+				if (i == PT_CCS) {
+					tmp &= CCS_MASK;
+					tmp |= get_reg(child, PT_CCS) & ~CCS_MASK;
+				}
+
+				put_reg(child, i, tmp);
+				datap++;
+			}
+
+			ret = 0;
+			break;
+		}
+
+		default:
+			ret = ptrace_request(child, request, addr, data);
+			break;
+	}
+out_tsk:
+	put_task_struct(child);
+out:
+	unlock_kernel();
+	return ret;
+}
+
+void do_syscall_trace(void)
+{
+	if (!test_thread_flag(TIF_SYSCALL_TRACE))
+		return;
+
+	if (!(current->ptrace & PT_PTRACED))
+		return;
+
+	/* the 0x80 provides a way for the tracing parent to distinguish
+	   between a syscall stop and SIGTRAP delivery */
+	ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
+				 ? 0x80 : 0));
+
+	/*
+	 * This isn't the same as continuing with a signal, but it will do for
+	 * normal use.
+	 */
+	if (current->exit_code) {
+		send_sig(current->exit_code, current, 1);
+		current->exit_code = 0;
+	}
+}
+
+/* Returns the size of an instruction that has a delay slot. */
+
+static int insn_size(struct task_struct *child, unsigned long pc)
+{
+  unsigned long opcode;
+  int copied;
+  int opsize = 0;
+
+  /* Read the opcode at pc (do what PTRACE_PEEKTEXT would do). */
+  copied = access_process_vm(child, pc, &opcode, sizeof(opcode), 0);
+  if (copied != sizeof(opcode))
+    return 0;
+
+  switch ((opcode & 0x0f00) >> 8) {
+  case 0x0:
+  case 0x9:
+  case 0xb:
+	  opsize = 2;
+	  break;
+  case 0xe:
+  case 0xf:
+	  opsize = 6;
+	  break;
+  case 0xd:
+	  /* Could be 4 or 6; check more bits. */
+	  if ((opcode & 0xff) == 0xff)
+		  opsize = 4;
+	  else
+		  opsize = 6;
+	  break;
+  default:
+	  panic("ERROR: Couldn't find size of opcode 0x%lx at 0x%lx\n",
+		opcode, pc);
+  }
+
+  return opsize;
+}
+
+static unsigned long get_pseudo_pc(struct task_struct *child)
+{
+	/* Default value for PC is ERP. */
+	unsigned long pc = get_reg(child, PT_ERP);
+
+	if (pc & 0x1) {
+		unsigned long spc = get_reg(child, PT_SPC);
+		/* Delay slot bit set. Report as stopped on proper
+		   instruction. */
+		if (spc) {
+			/* Rely on SPC if set. FIXME: We might want to check
+			   that EXS indicates we stopped due to a single-step
+			   exception. */
+			pc = spc;
+		} else {
+			/* Calculate the PC from the size of the instruction
+			   that the delay slot we're in belongs to. */
+			pc += insn_size(child, pc & ~1) - 1;
+		}
+	}
+	return pc;
+}
+
+static long bp_owner = 0;
+
+/* Reachable from exit_thread in signal.c, so not static. */
+void deconfigure_bp(long pid)
+{
+	int bp;
+
+	/* Only deconfigure if the pid is the owner. */
+	if (bp_owner != pid)
+		return;
+
+	for (bp = 0; bp < 6; bp++) {
+		unsigned long tmp;
+		/* Deconfigure start and end address (also gets rid of ownership). */
+		put_debugreg(pid, PT_BP + 3 + (bp * 2), 0);
+		put_debugreg(pid, PT_BP + 4 + (bp * 2), 0);
+
+		/* Deconfigure relevant bits in control register. */
+		tmp = get_debugreg(pid, PT_BP_CTRL) & ~(3 << (2 + (bp * 4)));
+		put_debugreg(pid, PT_BP_CTRL, tmp);
+	}
+	/* No owner now. */
+	bp_owner = 0;
+}
+
+static int put_debugreg(long pid, unsigned int regno, long data)
+{
+	int ret = 0;
+	register int old_srs;
+
+#ifdef CONFIG_ETRAX_KGDB
+	/* Ignore write, but pretend it was ok if value is 0
+	   (we don't want POKEUSR/SETREGS failing unnessecarily). */
+	return (data == 0) ? ret : -1;
+#endif
+
+	/* Simple owner management. */
+	if (!bp_owner)
+		bp_owner = pid;
+	else if (bp_owner != pid) {
+		/* Ignore write, but pretend it was ok if value is 0
+		   (we don't want POKEUSR/SETREGS failing unnessecarily). */
+		return (data == 0) ? ret : -1;
+	}
+
+	/* Remember old SRS. */
+	SPEC_REG_RD(SPEC_REG_SRS, old_srs);
+	/* Switch to BP bank. */
+	SUPP_BANK_SEL(BANK_BP);
+
+	switch (regno - PT_BP) {
+	case 0:
+		SUPP_REG_WR(0, data); break;
+	case 1:
+	case 2:
+		if (data)
+			ret = -1;
+		break;
+	case 3:
+		SUPP_REG_WR(3, data); break;
+	case 4:
+		SUPP_REG_WR(4, data); break;
+	case 5:
+		SUPP_REG_WR(5, data); break;
+	case 6:
+		SUPP_REG_WR(6, data); break;
+	case 7:
+		SUPP_REG_WR(7, data); break;
+	case 8:
+		SUPP_REG_WR(8, data); break;
+	case 9:
+		SUPP_REG_WR(9, data); break;
+	case 10:
+		SUPP_REG_WR(10, data); break;
+	case 11:
+		SUPP_REG_WR(11, data); break;
+	case 12:
+		SUPP_REG_WR(12, data); break;
+	case 13:
+		SUPP_REG_WR(13, data); break;
+	case 14:
+		SUPP_REG_WR(14, data); break;
+	default:
+		ret = -1;
+		break;
+	}
+
+	/* Restore SRS. */
+	SPEC_REG_WR(SPEC_REG_SRS, old_srs);
+	/* Just for show. */
+	NOP();
+	NOP();
+	NOP();
+
+	return ret;
+}
+
+static long get_debugreg(long pid, unsigned int regno)
+{
+	register int old_srs;
+	register long data;
+
+	if (pid != bp_owner) {
+		return 0;
+	}
+
+	/* Remember old SRS. */
+	SPEC_REG_RD(SPEC_REG_SRS, old_srs);
+	/* Switch to BP bank. */
+	SUPP_BANK_SEL(BANK_BP);
+
+	switch (regno - PT_BP) {
+	case 0:
+		SUPP_REG_RD(0, data); break;
+	case 1:
+	case 2:
+		/* error return value? */
+		data = 0;
+		break;
+	case 3:
+		SUPP_REG_RD(3, data); break;
+	case 4:
+		SUPP_REG_RD(4, data); break;
+	case 5:
+		SUPP_REG_RD(5, data); break;
+	case 6:
+		SUPP_REG_RD(6, data); break;
+	case 7:
+		SUPP_REG_RD(7, data); break;
+	case 8:
+		SUPP_REG_RD(8, data); break;
+	case 9:
+		SUPP_REG_RD(9, data); break;
+	case 10:
+		SUPP_REG_RD(10, data); break;
+	case 11:
+		SUPP_REG_RD(11, data); break;
+	case 12:
+		SUPP_REG_RD(12, data); break;
+	case 13:
+		SUPP_REG_RD(13, data); break;
+	case 14:
+		SUPP_REG_RD(14, data); break;
+	default:
+		/* error return value? */
+		data = 0;
+	}
+
+	/* Restore SRS. */
+	SPEC_REG_WR(SPEC_REG_SRS, old_srs);
+	/* Just for show. */
+	NOP();
+	NOP();
+	NOP();
+
+	return data;
+}
diff --git a/arch/cris/arch-v32/kernel/setup.c b/arch/cris/arch-v32/kernel/setup.c
new file mode 100644
index 00000000000..b17a39a2e16
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/setup.c
@@ -0,0 +1,118 @@
+/*
+ * Display CPU info in /proc/cpuinfo.
+ *
+ * Copyright (C) 2003, Axis Communications AB.
+ */
+
+#include <linux/config.h>
+#include <linux/seq_file.h>
+#include <linux/proc_fs.h>
+#include <linux/delay.h>
+#include <linux/param.h>
+
+#ifdef CONFIG_PROC_FS
+
+#define HAS_FPU         0x0001
+#define HAS_MMU         0x0002
+#define HAS_ETHERNET100 0x0004
+#define HAS_TOKENRING   0x0008
+#define HAS_SCSI        0x0010
+#define HAS_ATA         0x0020
+#define HAS_USB         0x0040
+#define HAS_IRQ_BUG     0x0080
+#define HAS_MMU_BUG     0x0100
+
+struct cpu_info {
+	char *cpu_model;
+	unsigned short rev;
+	unsigned short cache_size;
+	unsigned short flags;
+};
+
+/* Some of these model are here for historical reasons only. */
+static struct cpu_info cpinfo[] = {
+	{"ETRAX 1", 0, 0, 0},
+	{"ETRAX 2", 1, 0, 0},
+	{"ETRAX 3", 2, 0, 0},
+	{"ETRAX 4", 3, 0, 0},
+	{"Simulator", 7, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA},
+	{"ETRAX 100", 8, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_IRQ_BUG},
+	{"ETRAX 100", 9, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA},
+
+	{"ETRAX 100LX", 10, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_USB
+			     | HAS_MMU | HAS_MMU_BUG},
+
+	{"ETRAX 100LX v2", 11, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_USB
+			        | HAS_MMU},
+
+	{"ETRAX FS", 32, 32, HAS_ETHERNET100 | HAS_ATA | HAS_MMU},
+
+	{"Unknown", 0, 0, 0}
+};
+
+int
+show_cpuinfo(struct seq_file *m, void *v)
+{
+	int i;
+	int cpu = (int)v - 1;
+	int entries;
+	unsigned long revision;
+	struct cpu_info *info;
+
+	entries = sizeof cpinfo / sizeof(struct cpu_info);
+	info = &cpinfo[entries - 1];
+
+#ifdef CONFIG_SMP
+	if (!cpu_online(cpu))
+		return 0;
+#endif
+
+	revision = rdvr();
+
+	for (i = 0; i < entries; i++) {
+		if (cpinfo[i].rev == revision) {
+			info = &cpinfo[i];
+			break;
+		}
+	}
+
+	return seq_printf(m,
+		"processor\t: %d\n"
+		"cpu\t\t: CRIS\n"
+		"cpu revision\t: %lu\n"
+		"cpu model\t: %s\n"
+		"cache size\t: %d KB\n"
+		"fpu\t\t: %s\n"
+		"mmu\t\t: %s\n"
+		"mmu DMA bug\t: %s\n"
+		"ethernet\t: %s Mbps\n"
+		"token ring\t: %s\n"
+		"scsi\t\t: %s\n"
+		"ata\t\t: %s\n"
+		"usb\t\t: %s\n"
+		"bogomips\t: %lu.%02lu\n\n",
+
+		cpu,
+		revision,
+		info->cpu_model,
+		info->cache_size,
+		info->flags & HAS_FPU ? "yes" : "no",
+		info->flags & HAS_MMU ? "yes" : "no",
+		info->flags & HAS_MMU_BUG ? "yes" : "no",
+		info->flags & HAS_ETHERNET100 ? "10/100" : "10",
+		info->flags & HAS_TOKENRING ? "4/16 Mbps" : "no",
+		info->flags & HAS_SCSI ? "yes" : "no",
+		info->flags & HAS_ATA ? "yes" : "no",
+		info->flags & HAS_USB ? "yes" : "no",
+		(loops_per_jiffy * HZ + 500) / 500000,
+		((loops_per_jiffy * HZ + 500) / 5000) % 100);
+}
+
+#endif /* CONFIG_PROC_FS */
+
+void
+show_etrax_copyright(void)
+{
+	printk(KERN_INFO
+               "Linux/CRISv32 port on ETRAX FS (C) 2003, 2004 Axis Communications AB\n");
+}
diff --git a/arch/cris/arch-v32/kernel/signal.c b/arch/cris/arch-v32/kernel/signal.c
new file mode 100644
index 00000000000..fb4c79d5b76
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/signal.c
@@ -0,0 +1,708 @@
+/*
+ * Copyright (C) 2003, Axis Communications AB.
+ */
+
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/kernel.h>
+#include <linux/signal.h>
+#include <linux/errno.h>
+#include <linux/wait.h>
+#include <linux/ptrace.h>
+#include <linux/unistd.h>
+#include <linux/stddef.h>
+#include <linux/syscalls.h>
+#include <linux/vmalloc.h>
+
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/ucontext.h>
+#include <asm/uaccess.h>
+#include <asm/arch/ptrace.h>
+#include <asm/arch/hwregs/cpu_vect.h>
+
+extern unsigned long cris_signal_return_page;
+
+/* Flag to check if a signal is blockable. */
+#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
+
+/*
+ * A syscall in CRIS is really a "break 13" instruction, which is 2
+ * bytes. The registers is manipulated so upon return the instruction
+ * will be executed again.
+ *
+ * This relies on that PC points to the instruction after the break call.
+ */
+#define RESTART_CRIS_SYS(regs) regs->r10 = regs->orig_r10; regs->erp -= 2;
+
+/* Signal frames. */
+struct signal_frame {
+	struct sigcontext sc;
+	unsigned long extramask[_NSIG_WORDS - 1];
+	unsigned char retcode[8];	/* Trampoline code. */
+};
+
+struct rt_signal_frame {
+	struct siginfo *pinfo;
+	void *puc;
+	struct siginfo info;
+	struct ucontext uc;
+	unsigned char retcode[8];	/* Trampoline code. */
+};
+
+int do_signal(int restart, sigset_t *oldset, struct pt_regs *regs);
+void keep_debug_flags(unsigned long oldccs, unsigned long oldspc,
+		      struct pt_regs *regs);
+/*
+ * Swap in the new signal mask, and wait for a signal. Define some
+ * dummy arguments to be able to reach the regs argument.
+ */
+int
+sys_sigsuspend(old_sigset_t mask, long r11, long r12, long r13, long mof,
+	       long srp, struct pt_regs *regs)
+{
+	sigset_t saveset;
+
+	mask &= _BLOCKABLE;
+
+	spin_lock_irq(&current->sighand->siglock);
+
+	saveset = current->blocked;
+
+	siginitset(&current->blocked, mask);
+
+	recalc_sigpending();
+	spin_unlock_irq(&current->sighand->siglock);
+
+	regs->r10 = -EINTR;
+
+	while (1) {
+		current->state = TASK_INTERRUPTIBLE;
+		schedule();
+
+		if (do_signal(0, &saveset, regs)) {
+			/*
+			 * This point is reached twice: once to call
+			 * the signal handler, then again to return
+			 * from the sigsuspend system call. When
+			 * calling the signal handler, R10 hold the
+			 * signal number as set by do_signal(). The
+			 * sigsuspend  call will always return with
+			 * the restored value above; -EINTR.
+			 */
+			return regs->r10;
+		}
+	}
+}
+
+/* Define some dummy arguments to be able to reach the regs argument. */
+int
+sys_rt_sigsuspend(sigset_t *unewset, size_t sigsetsize, long r12, long r13,
+		  long mof, long srp, struct pt_regs *regs)
+{
+	sigset_t saveset;
+	sigset_t newset;
+
+	if (sigsetsize != sizeof(sigset_t))
+		return -EINVAL;
+
+	if (copy_from_user(&newset, unewset, sizeof(newset)))
+		return -EFAULT;
+
+	sigdelsetmask(&newset, ~_BLOCKABLE);
+	spin_lock_irq(&current->sighand->siglock);
+
+	saveset = current->blocked;
+	current->blocked = newset;
+
+	recalc_sigpending();
+	spin_unlock_irq(&current->sighand->siglock);
+
+	regs->r10 = -EINTR;
+
+	while (1) {
+		current->state = TASK_INTERRUPTIBLE;
+		schedule();
+
+		if (do_signal(0, &saveset, regs)) {
+			/* See comment in function above. */
+			return regs->r10;
+		}
+	}
+}
+
+int
+sys_sigaction(int signal, const struct old_sigaction *act,
+	      struct old_sigaction *oact)
+{
+	int retval;
+	struct k_sigaction newk;
+	struct k_sigaction oldk;
+
+	if (act) {
+		old_sigset_t mask;
+
+		if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
+		    __get_user(newk.sa.sa_handler, &act->sa_handler) ||
+		    __get_user(newk.sa.sa_restorer, &act->sa_restorer))
+			return -EFAULT;
+
+		__get_user(newk.sa.sa_flags, &act->sa_flags);
+		__get_user(mask, &act->sa_mask);
+		siginitset(&newk.sa.sa_mask, mask);
+	}
+
+	retval = do_sigaction(signal, act ? &newk : NULL, oact ? &oldk : NULL);
+
+	if (!retval && oact) {
+		if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
+		    __put_user(oldk.sa.sa_handler, &oact->sa_handler) ||
+		    __put_user(oldk.sa.sa_restorer, &oact->sa_restorer))
+			return -EFAULT;
+
+		__put_user(oldk.sa.sa_flags, &oact->sa_flags);
+		__put_user(oldk.sa.sa_mask.sig[0], &oact->sa_mask);
+	}
+
+	return retval;
+}
+
+int
+sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss)
+{
+	return do_sigaltstack(uss, uoss, rdusp());
+}
+
+static int
+restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
+{
+	unsigned int err = 0;
+	unsigned long old_usp;
+
+        /* Always make any pending restarted system calls return -EINTR */
+	current_thread_info()->restart_block.fn = do_no_restart_syscall;
+
+	/*
+	 * Restore the registers from &sc->regs. sc is already checked
+	 * for VERIFY_READ since the signal_frame was previously
+	 * checked in sys_sigreturn().
+	 */
+	if (__copy_from_user(regs, sc, sizeof(struct pt_regs)))
+		goto badframe;
+
+	/* Make that the user-mode flag is set. */
+	regs->ccs |= (1 << (U_CCS_BITNR + CCS_SHIFT));
+
+	/* Restore the old USP. */
+	err |= __get_user(old_usp, &sc->usp);
+	wrusp(old_usp);
+
+	return err;
+
+badframe:
+	return 1;
+}
+
+/* Define some dummy arguments to be able to reach the regs argument. */
+asmlinkage int
+sys_sigreturn(long r10, long r11, long r12, long r13, long mof, long srp,
+	      struct pt_regs *regs)
+{
+	sigset_t set;
+	struct signal_frame __user *frame;
+	unsigned long oldspc = regs->spc;
+	unsigned long oldccs = regs->ccs;
+
+	frame = (struct signal_frame *) rdusp();
+
+	/*
+	 * Since the signal is stacked on a dword boundary, the frame
+	 * should be dword aligned here as well. It it's not, then the
+	 * user is trying some funny business.
+	 */
+	if (((long)frame) & 3)
+		goto badframe;
+
+	if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
+		goto badframe;
+
+	if (__get_user(set.sig[0], &frame->sc.oldmask) ||
+	    (_NSIG_WORDS > 1 && __copy_from_user(&set.sig[1],
+						 frame->extramask,
+						 sizeof(frame->extramask))))
+		goto badframe;
+
+	sigdelsetmask(&set, ~_BLOCKABLE);
+	spin_lock_irq(&current->sighand->siglock);
+
+	current->blocked = set;
+
+	recalc_sigpending();
+	spin_unlock_irq(&current->sighand->siglock);
+
+	if (restore_sigcontext(regs, &frame->sc))
+		goto badframe;
+
+	keep_debug_flags(oldccs, oldspc, regs);
+
+	return regs->r10;
+
+badframe:
+	force_sig(SIGSEGV, current);
+	return 0;
+}
+
+/* Define some dummy variables to be able to reach the regs argument. */
+asmlinkage int
+sys_rt_sigreturn(long r10, long r11, long r12, long r13, long mof, long srp,
+		 struct pt_regs *regs)
+{
+	sigset_t set;
+	struct rt_signal_frame __user *frame;
+	unsigned long oldspc = regs->spc;
+	unsigned long oldccs = regs->ccs;
+
+	frame = (struct rt_signal_frame *) rdusp();
+
+	/*
+	 * Since the signal is stacked on a dword boundary, the frame
+	 * should be dword aligned here as well. It it's not, then the
+	 * user is trying some funny business.
+	 */
+	if (((long)frame) & 3)
+		goto badframe;
+
+	if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
+		goto badframe;
+
+	if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
+		goto badframe;
+
+	sigdelsetmask(&set, ~_BLOCKABLE);
+	spin_lock_irq(&current->sighand->siglock);
+
+	current->blocked = set;
+
+	recalc_sigpending();
+	spin_unlock_irq(&current->sighand->siglock);
+
+	if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
+		goto badframe;
+
+	if (do_sigaltstack(&frame->uc.uc_stack, NULL, rdusp()) == -EFAULT)
+ 		goto badframe;
+
+	keep_debug_flags(oldccs, oldspc, regs);
+
+	return regs->r10;
+
+badframe:
+	force_sig(SIGSEGV, current);
+	return 0;
+}
+
+/* Setup a signal frame. */
+static int
+setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs,
+		 unsigned long mask)
+{
+	int err;
+	unsigned long usp;
+
+	err = 0;
+	usp = rdusp();
+
+	/*
+	 * Copy the registers. They are located first in sc, so it's
+	 * possible to use sc directly.
+	 */
+	err |= __copy_to_user(sc, regs, sizeof(struct pt_regs));
+
+	err |= __put_user(mask, &sc->oldmask);
+	err |= __put_user(usp, &sc->usp);
+
+	return err;
+}
+
+/* Figure out where to put the new signal frame - usually on the stack. */
+static inline void __user *
+get_sigframe(struct k_sigaction *ka, struct pt_regs * regs, size_t frame_size)
+{
+	unsigned long sp;
+
+	sp = rdusp();
+
+	/* This is the X/Open sanctioned signal stack switching. */
+	if (ka->sa.sa_flags & SA_ONSTACK) {
+		if (!on_sig_stack(sp))
+			sp = current->sas_ss_sp + current->sas_ss_size;
+	}
+
+	/* Make sure the frame is dword-aligned. */
+	sp &= ~3;
+
+	return (void __user *)(sp - frame_size);
+}
+
+/* Grab and setup a signal frame.
+ *
+ * Basically a lot of state-info is stacked, and arranged for the
+ * user-mode program to return to the kernel using either a trampiline
+ * which performs the syscall sigreturn(), or a provided user-mode
+ * trampoline.
+  */
+static void
+setup_frame(int sig, struct k_sigaction *ka,  sigset_t *set,
+	    struct pt_regs * regs)
+{
+	int err;
+	unsigned long return_ip;
+	struct signal_frame __user *frame;
+
+	err = 0;
+	frame = get_sigframe(ka, regs, sizeof(*frame));
+
+	if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
+		goto give_sigsegv;
+
+	err |= setup_sigcontext(&frame->sc, regs, set->sig[0]);
+
+	if (err)
+		goto give_sigsegv;
+
+	if (_NSIG_WORDS > 1) {
+		err |= __copy_to_user(frame->extramask, &set->sig[1],
+				      sizeof(frame->extramask));
+	}
+
+	if (err)
+		goto give_sigsegv;
+
+	/*
+	 * Set up to return from user-space. If provided, use a stub
+	 * already located in user-space.
+	 */
+	if (ka->sa.sa_flags & SA_RESTORER) {
+		return_ip = (unsigned long)ka->sa.sa_restorer;
+	} else {
+		/* Trampoline - the desired return ip is in the signal return page. */
+		return_ip = cris_signal_return_page;
+
+		/*
+		 * This is movu.w __NR_sigreturn, r9; break 13;
+		 *
+		 * WE DO NOT USE IT ANY MORE! It's only left here for historical
+		 * reasons and because gdb uses it as a signature to notice
+		 * signal handler stack frames.
+		 */
+		err |= __put_user(0x9c5f,         (short __user*)(frame->retcode+0));
+		err |= __put_user(__NR_sigreturn, (short __user*)(frame->retcode+2));
+		err |= __put_user(0xe93d,         (short __user*)(frame->retcode+4));
+	}
+
+	if (err)
+		goto give_sigsegv;
+
+	/*
+	 * Set up registers for signal handler.
+	 *
+	 * Where the code enters now.
+	 * Where the code enter later.
+	 * First argument, signo.
+	 */
+	regs->erp = (unsigned long) ka->sa.sa_handler;
+	regs->srp = return_ip;
+	regs->r10 = sig;
+
+	/* Actually move the USP to reflect the stacked frame. */
+	wrusp((unsigned long)frame);
+
+	return;
+
+give_sigsegv:
+	if (sig == SIGSEGV)
+		ka->sa.sa_handler = SIG_DFL;
+
+	force_sig(SIGSEGV, current);
+}
+
+static void
+setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
+	       sigset_t *set, struct pt_regs * regs)
+{
+	int err;
+	unsigned long return_ip;
+	struct rt_signal_frame __user *frame;
+
+	err = 0;
+	frame = get_sigframe(ka, regs, sizeof(*frame));
+
+	if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
+		goto give_sigsegv;
+
+	/* TODO: what is the current->exec_domain stuff and invmap ? */
+
+	err |= __put_user(&frame->info, &frame->pinfo);
+	err |= __put_user(&frame->uc, &frame->puc);
+	err |= copy_siginfo_to_user(&frame->info, info);
+
+	if (err)
+		goto give_sigsegv;
+
+	/* Clear all the bits of the ucontext we don't use.  */
+	err |= __clear_user(&frame->uc, offsetof(struct ucontext, uc_mcontext));
+	err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, set->sig[0]);
+	err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
+
+	if (err)
+		goto give_sigsegv;
+
+	/*
+	 * Set up to return from user-space. If provided, use a stub
+	 * already located in user-space.
+	 */
+	if (ka->sa.sa_flags & SA_RESTORER) {
+		return_ip = (unsigned long) ka->sa.sa_restorer;
+	} else {
+		/* Trampoline - the desired return ip is in the signal return page. */
+		return_ip = cris_signal_return_page + 6;
+
+		/*
+		 * This is movu.w __NR_rt_sigreturn, r9; break 13;
+		 *
+		 * WE DO NOT USE IT ANY MORE! It's only left here for historical
+		 * reasons and because gdb uses it as a signature to notice
+		 * signal handler stack frames.
+		 */
+		err |= __put_user(0x9c5f, (short __user*)(frame->retcode+0));
+
+		err |= __put_user(__NR_rt_sigreturn,
+				  (short __user*)(frame->retcode+2));
+
+		err |= __put_user(0xe93d, (short __user*)(frame->retcode+4));
+	}
+
+	if (err)
+		goto give_sigsegv;
+
+	/*
+	 * Set up registers for signal handler.
+	 *
+	 * Where the code enters now.
+	 * Where the code enters later.
+	 * First argument is signo.
+	 * Second argument is (siginfo_t *).
+	 * Third argument is unused.
+	 */
+	regs->erp = (unsigned long) ka->sa.sa_handler;
+	regs->srp = return_ip;
+	regs->r10 = sig;
+	regs->r11 = (unsigned long) &frame->info;
+	regs->r12 = 0;
+
+	/* Actually move the usp to reflect the stacked frame. */
+	wrusp((unsigned long)frame);
+
+	return;
+
+give_sigsegv:
+	if (sig == SIGSEGV)
+		ka->sa.sa_handler = SIG_DFL;
+
+	force_sig(SIGSEGV, current);
+}
+
+/* Invoke a singal handler to, well, handle the signal. */
+extern inline void
+handle_signal(int canrestart, unsigned long sig,
+	      siginfo_t *info, struct k_sigaction *ka,
+              sigset_t *oldset, struct pt_regs * regs)
+{
+	/* Check if this got called from a system call. */
+	if (canrestart) {
+		/* If so, check system call restarting. */
+		switch (regs->r10) {
+			case -ERESTART_RESTARTBLOCK:
+			case -ERESTARTNOHAND:
+				/*
+				 * This means that the syscall should
+				 * only be restarted if there was no
+				 * handler for the signal, and since
+				 * this point isn't reached unless
+				 * there is a handler, there's no need
+				 * to restart.
+				 */
+				regs->r10 = -EINTR;
+				break;
+
+                        case -ERESTARTSYS:
+				/*
+				 * This means restart the syscall if
+                                 * there is no handler, or the handler
+                                 * was registered with SA_RESTART.
+				 */
+				if (!(ka->sa.sa_flags & SA_RESTART)) {
+					regs->r10 = -EINTR;
+					break;
+				}
+
+				/* Fall through. */
+
+			case -ERESTARTNOINTR:
+				/*
+				 * This means that the syscall should
+                                 * be called again after the signal
+                                 * handler returns.
+				 */
+				RESTART_CRIS_SYS(regs);
+				break;
+                }
+        }
+
+	/* Set up the stack frame. */
+	if (ka->sa.sa_flags & SA_SIGINFO)
+		setup_rt_frame(sig, ka, info, oldset, regs);
+	else
+		setup_frame(sig, ka, oldset, regs);
+
+	if (ka->sa.sa_flags & SA_ONESHOT)
+		ka->sa.sa_handler = SIG_DFL;
+
+	if (!(ka->sa.sa_flags & SA_NODEFER)) {
+		spin_lock_irq(&current->sighand->siglock);
+		sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
+		sigaddset(&current->blocked,sig);
+		recalc_sigpending();
+		spin_unlock_irq(&current->sighand->siglock);
+	}
+}
+
+/*
+ * Note that 'init' is a special process: it doesn't get signals it doesn't
+ * want to handle. Thus you cannot kill init even with a SIGKILL even by
+ * mistake.
+ *
+ * Also note that the regs structure given here as an argument, is the latest
+ * pushed pt_regs. It may or may not be the same as the first pushed registers
+ * when the initial usermode->kernelmode transition took place. Therefore
+ * we can use user_mode(regs) to see if we came directly from kernel or user
+ * mode below.
+ */
+int
+do_signal(int canrestart, sigset_t *oldset, struct pt_regs *regs)
+{
+	int signr;
+	siginfo_t info;
+        struct k_sigaction ka;
+
+	/*
+	 * The common case should go fast, which is why this point is
+	 * reached from kernel-mode. If that's the case, just return
+	 * without doing anything.
+	 */
+	if (!user_mode(regs))
+		return 1;
+
+	if (!oldset)
+		oldset = &current->blocked;
+
+	signr = get_signal_to_deliver(&info, &ka, regs, NULL);
+
+	if (signr > 0) {
+		/* Deliver the signal. */
+		handle_signal(canrestart, signr, &info, &ka, oldset, regs);
+		return 1;
+	}
+
+	/* Got here from a system call? */
+	if (canrestart) {
+		/* Restart the system call - no handlers present. */
+		if (regs->r10 == -ERESTARTNOHAND ||
+		    regs->r10 == -ERESTARTSYS ||
+		    regs->r10 == -ERESTARTNOINTR) {
+			RESTART_CRIS_SYS(regs);
+		}
+
+		if (regs->r10 == -ERESTART_RESTARTBLOCK){
+			regs->r10 = __NR_restart_syscall;
+			regs->erp -= 2;
+		}
+	}
+
+	return 0;
+}
+
+asmlinkage void
+ugdb_trap_user(struct thread_info *ti, int sig)
+{
+	if (((user_regs(ti)->exs & 0xff00) >> 8) != SINGLE_STEP_INTR_VECT) {
+		/* Zero single-step PC if the reason we stopped wasn't a single
+		   step exception. This is to avoid relying on it when it isn't
+		   reliable. */
+		user_regs(ti)->spc = 0;
+	}
+	/* FIXME: Filter out false h/w breakpoint hits (i.e. EDA
+	   not withing any configured h/w breakpoint range). Synchronize with
+	   what already exists for kernel debugging.  */
+	if (((user_regs(ti)->exs & 0xff00) >> 8) == BREAK_8_INTR_VECT) {
+		/* Break 8: subtract 2 from ERP unless in a delay slot. */
+		if (!(user_regs(ti)->erp & 0x1))
+			user_regs(ti)->erp -= 2;
+	}
+	sys_kill(ti->task->pid, sig);
+}
+
+void
+keep_debug_flags(unsigned long oldccs, unsigned long oldspc,
+		 struct pt_regs *regs)
+{
+	if (oldccs & (1 << Q_CCS_BITNR)) {
+		/* Pending single step due to single-stepping the break 13
+		   in the signal trampoline: keep the Q flag. */
+		regs->ccs |= (1 << Q_CCS_BITNR);
+		/* S flag should be set - complain if it's not. */
+		if (!(oldccs & (1 << (S_CCS_BITNR + CCS_SHIFT)))) {
+			printk("Q flag but no S flag?");
+		}
+		regs->ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT));
+		/* Assume the SPC is valid and interesting. */
+		regs->spc = oldspc;
+
+	} else if (oldccs & (1 << (S_CCS_BITNR + CCS_SHIFT))) {
+		/* If a h/w bp was set in the signal handler we need
+		   to keep the S flag. */
+		regs->ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT));
+		/* Don't keep the old SPC though; if we got here due to
+		   a single-step, the Q flag should have been set. */
+	} else if (regs->spc) {
+		/* If we were single-stepping *before* the signal was taken,
+		   we don't want to restore that state now, because GDB will
+		   have forgotten all about it. */
+		regs->spc = 0;
+		regs->ccs &= ~(1 << (S_CCS_BITNR + CCS_SHIFT));
+	}
+}
+
+/* Set up the trampolines on the signal return page. */
+int __init
+cris_init_signal(void)
+{
+	u16* data = (u16*)kmalloc(PAGE_SIZE, GFP_KERNEL);
+
+	/* This is movu.w __NR_sigreturn, r9; break 13; */
+	data[0] = 0x9c5f;
+	data[1] = __NR_sigreturn;
+	data[2] = 0xe93d;
+	/* This is movu.w __NR_rt_sigreturn, r9; break 13; */
+	data[3] = 0x9c5f;
+	data[4] = __NR_rt_sigreturn;
+	data[5] = 0xe93d;
+
+	/* Map to userspace with appropriate permissions (no write access...) */
+	cris_signal_return_page = (unsigned long)
+          __ioremap_prot(virt_to_phys(data), PAGE_SIZE, PAGE_SIGNAL_TRAMPOLINE);
+
+	return 0;
+}
+
+__initcall(cris_init_signal);
diff --git a/arch/cris/arch-v32/kernel/smp.c b/arch/cris/arch-v32/kernel/smp.c
new file mode 100644
index 00000000000..2c5cae04a95
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/smp.c
@@ -0,0 +1,348 @@
+#include <asm/delay.h>
+#include <asm/arch/irq.h>
+#include <asm/arch/hwregs/intr_vect.h>
+#include <asm/arch/hwregs/intr_vect_defs.h>
+#include <asm/tlbflush.h>
+#include <asm/mmu_context.h>
+#include <asm/arch/hwregs/mmu_defs_asm.h>
+#include <asm/arch/hwregs/supp_reg.h>
+#include <asm/atomic.h>
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/timex.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/cpumask.h>
+#include <linux/interrupt.h>
+
+#define IPI_SCHEDULE 1
+#define IPI_CALL 2
+#define IPI_FLUSH_TLB 4
+
+#define FLUSH_ALL (void*)0xffffffff
+
+/* Vector of locks used for various atomic operations */
+spinlock_t cris_atomic_locks[] = { [0 ... LOCK_COUNT - 1] = SPIN_LOCK_UNLOCKED};
+
+/* CPU masks */
+cpumask_t cpu_online_map = CPU_MASK_NONE;
+cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
+
+/* Variables used during SMP boot */
+volatile int cpu_now_booting = 0;
+volatile struct thread_info *smp_init_current_idle_thread;
+
+/* Variables used during IPI */
+static DEFINE_SPINLOCK(call_lock);
+static DEFINE_SPINLOCK(tlbstate_lock);
+
+struct call_data_struct {
+	void (*func) (void *info);
+	void *info;
+	int wait;
+};
+
+static struct call_data_struct * call_data;
+
+static struct mm_struct* flush_mm;
+static struct vm_area_struct* flush_vma;
+static unsigned long flush_addr;
+
+extern int setup_irq(int, struct irqaction *);
+
+/* Mode registers */
+static unsigned long irq_regs[NR_CPUS] =
+{
+  regi_irq,
+  regi_irq2
+};
+
+static irqreturn_t crisv32_ipi_interrupt(int irq, void *dev_id, struct pt_regs *regs);
+static int send_ipi(int vector, int wait, cpumask_t cpu_mask);
+static struct irqaction irq_ipi  = { crisv32_ipi_interrupt, SA_INTERRUPT,
+                                     CPU_MASK_NONE, "ipi", NULL, NULL};
+
+extern void cris_mmu_init(void);
+extern void cris_timer_init(void);
+
+/* SMP initialization */
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+	int i;
+
+	/* From now on we can expect IPIs so set them up */
+	setup_irq(IPI_INTR_VECT, &irq_ipi);
+
+	/* Mark all possible CPUs as present */
+	for (i = 0; i < max_cpus; i++)
+	    cpu_set(i, phys_cpu_present_map);
+}
+
+void __devinit smp_prepare_boot_cpu(void)
+{
+	/* PGD pointer has moved after per_cpu initialization so
+	 * update the MMU.
+	 */
+  	pgd_t **pgd;
+	pgd = (pgd_t**)&per_cpu(current_pgd, smp_processor_id());
+
+	SUPP_BANK_SEL(1);
+	SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
+	SUPP_BANK_SEL(2);
+	SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
+
+	cpu_set(0, cpu_online_map);
+	cpu_set(0, phys_cpu_present_map);
+}
+
+void __init smp_cpus_done(unsigned int max_cpus)
+{
+}
+
+/* Bring one cpu online.*/
+static int __init
+smp_boot_one_cpu(int cpuid)
+{
+	unsigned timeout;
+	struct task_struct *idle;
+
+	idle = fork_idle(cpuid);
+	if (IS_ERR(idle))
+		panic("SMP: fork failed for CPU:%d", cpuid);
+
+	idle->thread_info->cpu = cpuid;
+
+	/* Information to the CPU that is about to boot */
+	smp_init_current_idle_thread = idle->thread_info;
+	cpu_now_booting = cpuid;
+
+	/* Wait for CPU to come online */
+	for (timeout = 0; timeout < 10000; timeout++) {
+		if(cpu_online(cpuid)) {
+			cpu_now_booting = 0;
+			smp_init_current_idle_thread = NULL;
+			return 0; /* CPU online */
+		}
+		udelay(100);
+		barrier();
+	}
+
+	put_task_struct(idle);
+	idle = NULL;
+
+	printk(KERN_CRIT "SMP: CPU:%d is stuck.\n", cpuid);
+	return -1;
+}
+
+/* Secondary CPUs starts uing C here. Here we need to setup CPU
+ * specific stuff such as the local timer and the MMU. */
+void __init smp_callin(void)
+{
+	extern void cpu_idle(void);
+
+	int cpu = cpu_now_booting;
+	reg_intr_vect_rw_mask vect_mask = {0};
+
+	/* Initialise the idle task for this CPU */
+	atomic_inc(&init_mm.mm_count);
+	current->active_mm = &init_mm;
+
+	/* Set up MMU */
+	cris_mmu_init();
+	__flush_tlb_all();
+
+	/* Setup local timer. */
+	cris_timer_init();
+
+	/* Enable IRQ and idle */
+	REG_WR(intr_vect, irq_regs[cpu], rw_mask, vect_mask);
+	unmask_irq(IPI_INTR_VECT);
+	unmask_irq(TIMER_INTR_VECT);
+	local_irq_enable();
+
+	cpu_set(cpu, cpu_online_map);
+	cpu_idle();
+}
+
+/* Stop execution on this CPU.*/
+void stop_this_cpu(void* dummy)
+{
+	local_irq_disable();
+	asm volatile("halt");
+}
+
+/* Other calls */
+void smp_send_stop(void)
+{
+	smp_call_function(stop_this_cpu, NULL, 1, 0);
+}
+
+int setup_profiling_timer(unsigned int multiplier)
+{
+	return -EINVAL;
+}
+
+
+/* cache_decay_ticks is used by the scheduler to decide if a process
+ * is "hot" on one CPU. A higher value means a higher penalty to move
+ * a process to another CPU. Our cache is rather small so we report
+ * 1 tick.
+ */
+unsigned long cache_decay_ticks = 1;
+
+int __devinit __cpu_up(unsigned int cpu)
+{
+	smp_boot_one_cpu(cpu);
+	return cpu_online(cpu) ? 0 : -ENOSYS;
+}
+
+void smp_send_reschedule(int cpu)
+{
+	cpumask_t cpu_mask = CPU_MASK_NONE;
+	cpu_set(cpu, cpu_mask);
+	send_ipi(IPI_SCHEDULE, 0, cpu_mask);
+}
+
+/* TLB flushing
+ *
+ * Flush needs to be done on the local CPU and on any other CPU that
+ * may have the same mapping. The mm->cpu_vm_mask is used to keep track
+ * of which CPUs that a specific process has been executed on.
+ */
+void flush_tlb_common(struct mm_struct* mm, struct vm_area_struct* vma, unsigned long addr)
+{
+	unsigned long flags;
+	cpumask_t cpu_mask;
+
+	spin_lock_irqsave(&tlbstate_lock, flags);
+	cpu_mask = (mm == FLUSH_ALL ? CPU_MASK_ALL : mm->cpu_vm_mask);
+	cpu_clear(smp_processor_id(), cpu_mask);
+	flush_mm = mm;
+	flush_vma = vma;
+	flush_addr = addr;
+	send_ipi(IPI_FLUSH_TLB, 1, cpu_mask);
+	spin_unlock_irqrestore(&tlbstate_lock, flags);
+}
+
+void flush_tlb_all(void)
+{
+	__flush_tlb_all();
+	flush_tlb_common(FLUSH_ALL, FLUSH_ALL, 0);
+}
+
+void flush_tlb_mm(struct mm_struct *mm)
+{
+	__flush_tlb_mm(mm);
+	flush_tlb_common(mm, FLUSH_ALL, 0);
+	/* No more mappings in other CPUs */
+	cpus_clear(mm->cpu_vm_mask);
+	cpu_set(smp_processor_id(), mm->cpu_vm_mask);
+}
+
+void flush_tlb_page(struct vm_area_struct *vma,
+			   unsigned long addr)
+{
+	__flush_tlb_page(vma, addr);
+	flush_tlb_common(vma->vm_mm, vma, addr);
+}
+
+/* Inter processor interrupts
+ *
+ * The IPIs are used for:
+ *   * Force a schedule on a CPU
+ *   * FLush TLB on other CPUs
+ *   * Call a function on other CPUs
+ */
+
+int send_ipi(int vector, int wait, cpumask_t cpu_mask)
+{
+	int i = 0;
+	reg_intr_vect_rw_ipi ipi = REG_RD(intr_vect, irq_regs[i], rw_ipi);
+	int ret = 0;
+
+	/* Calculate CPUs to send to. */
+	cpus_and(cpu_mask, cpu_mask, cpu_online_map);
+
+	/* Send the IPI. */
+	for_each_cpu_mask(i, cpu_mask)
+	{
+		ipi.vector |= vector;
+		REG_WR(intr_vect, irq_regs[i], rw_ipi, ipi);
+	}
+
+	/* Wait for IPI to finish on other CPUS */
+	if (wait) {
+		for_each_cpu_mask(i, cpu_mask) {
+                        int j;
+                        for (j = 0 ; j < 1000; j++) {
+				ipi = REG_RD(intr_vect, irq_regs[i], rw_ipi);
+				if (!ipi.vector)
+					break;
+				udelay(100);
+			}
+
+			/* Timeout? */
+			if (ipi.vector) {
+				printk("SMP call timeout from %d to %d\n", smp_processor_id(), i);
+				ret = -ETIMEDOUT;
+				dump_stack();
+			}
+		}
+	}
+	return ret;
+}
+
+/*
+ * You must not call this function with disabled interrupts or from a
+ * hardware interrupt handler or from a bottom half handler.
+ */
+int smp_call_function(void (*func)(void *info), void *info,
+		      int nonatomic, int wait)
+{
+	cpumask_t cpu_mask = CPU_MASK_ALL;
+	struct call_data_struct data;
+	int ret;
+
+	cpu_clear(smp_processor_id(), cpu_mask);
+
+	WARN_ON(irqs_disabled());
+
+	data.func = func;
+	data.info = info;
+	data.wait = wait;
+
+	spin_lock(&call_lock);
+	call_data = &data;
+	ret = send_ipi(IPI_CALL, wait, cpu_mask);
+	spin_unlock(&call_lock);
+
+	return ret;
+}
+
+irqreturn_t crisv32_ipi_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	void (*func) (void *info) = call_data->func;
+	void *info = call_data->info;
+	reg_intr_vect_rw_ipi ipi;
+
+	ipi = REG_RD(intr_vect, irq_regs[smp_processor_id()], rw_ipi);
+
+	if (ipi.vector & IPI_CALL) {
+	         func(info);
+	}
+	if (ipi.vector & IPI_FLUSH_TLB) {
+		     if (flush_mm == FLUSH_ALL)
+			 __flush_tlb_all();
+		     else if (flush_vma == FLUSH_ALL)
+			__flush_tlb_mm(flush_mm);
+		     else
+			__flush_tlb_page(flush_vma, flush_addr);
+	}
+
+	ipi.vector = 0;
+	REG_WR(intr_vect, irq_regs[smp_processor_id()], rw_ipi, ipi);
+
+	return IRQ_HANDLED;
+}
+
diff --git a/arch/cris/arch-v32/kernel/time.c b/arch/cris/arch-v32/kernel/time.c
new file mode 100644
index 00000000000..d48e397f5fa
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/time.c
@@ -0,0 +1,341 @@
+/* $Id: time.c,v 1.19 2005/04/29 05:40:09 starvik Exp $
+ *
+ *  linux/arch/cris/arch-v32/kernel/time.c
+ *
+ *  Copyright (C) 2003 Axis Communications AB
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/timex.h>
+#include <linux/time.h>
+#include <linux/jiffies.h>
+#include <linux/interrupt.h>
+#include <linux/swap.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/threads.h>
+#include <asm/types.h>
+#include <asm/signal.h>
+#include <asm/io.h>
+#include <asm/delay.h>
+#include <asm/rtc.h>
+#include <asm/irq.h>
+
+#include <asm/arch/hwregs/reg_map.h>
+#include <asm/arch/hwregs/reg_rdwr.h>
+#include <asm/arch/hwregs/timer_defs.h>
+#include <asm/arch/hwregs/intr_vect_defs.h>
+
+/* Watchdog defines */
+#define ETRAX_WD_KEY_MASK 0x7F /* key is 7 bit */
+#define ETRAX_WD_HZ       763 /* watchdog counts at 763 Hz */
+#define ETRAX_WD_CNT      ((2*ETRAX_WD_HZ)/HZ + 1) /* Number of 763 counts before watchdog bites */
+
+unsigned long timer_regs[NR_CPUS] =
+{
+  regi_timer,
+#ifdef CONFIG_SMP
+  regi_timer2
+#endif
+};
+
+extern void update_xtime_from_cmos(void);
+extern int set_rtc_mmss(unsigned long nowtime);
+extern int setup_irq(int, struct irqaction *);
+extern int have_rtc;
+
+unsigned long get_ns_in_jiffie(void)
+{
+	reg_timer_r_tmr0_data data;
+	unsigned long ns;
+
+	data = REG_RD(timer, regi_timer, r_tmr0_data);
+	ns = (TIMER0_DIV - data) * 10;
+	return ns;
+}
+
+unsigned long do_slow_gettimeoffset(void)
+{
+	unsigned long count;
+	unsigned long usec_count = 0;
+
+	static unsigned long count_p = TIMER0_DIV;/* for the first call after boot */
+	static unsigned long jiffies_p = 0;
+
+	/*
+	 * cache volatile jiffies temporarily; we have IRQs turned off.
+	 */
+	unsigned long jiffies_t;
+
+	/* The timer interrupt comes from Etrax timer 0. In order to get
+	 * better precision, we check the current value. It might have
+	 * underflowed already though.
+	 */
+
+	count = REG_RD(timer, regi_timer, r_tmr0_data);
+ 	jiffies_t = jiffies;
+
+	/*
+	 * avoiding timer inconsistencies (they are rare, but they happen)...
+	 * there are one problem that must be avoided here:
+	 *  1. the timer counter underflows
+	 */
+	if( jiffies_t == jiffies_p ) {
+		if( count > count_p ) {
+			/* Timer wrapped, use new count and prescale
+			 * increase the time corresponding to one jiffie
+			 */
+			usec_count = 1000000/HZ;
+		}
+	} else
+		jiffies_p = jiffies_t;
+        count_p = count;
+	/* Convert timer value to usec */
+	/* 100 MHz timer, divide by 100 to get usec */
+	usec_count +=  (TIMER0_DIV - count) / 100;
+	return usec_count;
+}
+
+/* From timer MDS describing the hardware watchdog:
+ * 4.3.1 Watchdog Operation
+ * The watchdog timer is an 8-bit timer with a configurable start value.
+ * Once started the whatchdog counts downwards with a frequency of 763 Hz
+ * (100/131072 MHz). When the watchdog counts down to 1, it generates an
+ * NMI (Non Maskable Interrupt), and when it counts down to 0, it resets the
+ * chip.
+ */
+/* This gives us 1.3 ms to do something useful when the NMI comes */
+
+/* right now, starting the watchdog is the same as resetting it */
+#define start_watchdog reset_watchdog
+
+#if defined(CONFIG_ETRAX_WATCHDOG)
+static short int watchdog_key = 42;  /* arbitrary 7 bit number */
+#endif
+
+/* number of pages to consider "out of memory". it is normal that the memory
+ * is used though, so put this really low.
+ */
+
+#define WATCHDOG_MIN_FREE_PAGES 8
+
+void
+reset_watchdog(void)
+{
+#if defined(CONFIG_ETRAX_WATCHDOG)
+	reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
+
+	/* only keep watchdog happy as long as we have memory left! */
+	if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
+		/* reset the watchdog with the inverse of the old key */
+		watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */
+		wd_ctrl.cnt = ETRAX_WD_CNT;
+		wd_ctrl.cmd = regk_timer_start;
+		wd_ctrl.key = watchdog_key;
+		REG_WR(timer, regi_timer, rw_wd_ctrl, wd_ctrl);
+	}
+#endif
+}
+
+/* stop the watchdog - we still need the correct key */
+
+void
+stop_watchdog(void)
+{
+#if defined(CONFIG_ETRAX_WATCHDOG)
+	reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
+	watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */
+	wd_ctrl.cnt = ETRAX_WD_CNT;
+	wd_ctrl.cmd = regk_timer_stop;
+	wd_ctrl.key = watchdog_key;
+	REG_WR(timer, regi_timer, rw_wd_ctrl, wd_ctrl);
+#endif
+}
+
+extern void show_registers(struct pt_regs *regs);
+
+void
+handle_watchdog_bite(struct pt_regs* regs)
+{
+#if defined(CONFIG_ETRAX_WATCHDOG)
+	extern int cause_of_death;
+
+	raw_printk("Watchdog bite\n");
+
+	/* Check if forced restart or unexpected watchdog */
+	if (cause_of_death == 0xbedead) {
+		while(1);
+	}
+
+	/* Unexpected watchdog, stop the watchdog and dump registers*/
+	stop_watchdog();
+	raw_printk("Oops: bitten by watchdog\n");
+        show_registers(regs);
+#ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
+	reset_watchdog();
+#endif
+	while(1) /* nothing */;
+#endif
+}
+
+/* last time the cmos clock got updated */
+static long last_rtc_update = 0;
+
+/*
+ * timer_interrupt() needs to keep up the real-time clock,
+ * as well as call the "do_timer()" routine every clocktick
+ */
+
+//static unsigned short myjiff; /* used by our debug routine print_timestamp */
+
+extern void cris_do_profile(struct pt_regs *regs);
+
+static inline irqreturn_t
+timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	int cpu = smp_processor_id();
+	reg_timer_r_masked_intr masked_intr;
+	reg_timer_rw_ack_intr ack_intr = { 0 };
+
+	/* Check if the timer interrupt is for us (a tmr0 int) */
+	masked_intr = REG_RD(timer, timer_regs[cpu], r_masked_intr);
+	if (!masked_intr.tmr0)
+		return IRQ_NONE;
+
+	/* acknowledge the timer irq */
+	ack_intr.tmr0 = 1;
+	REG_WR(timer, timer_regs[cpu], rw_ack_intr, ack_intr);
+
+	/* reset watchdog otherwise it resets us! */
+	reset_watchdog();
+
+        /* Update statistics. */
+	update_process_times(user_mode(regs));
+
+	cris_do_profile(regs); /* Save profiling information */
+
+	/* The master CPU is responsible for the time keeping. */
+	if (cpu != 0)
+		return IRQ_HANDLED;
+
+	/* call the real timer interrupt handler */
+	do_timer(regs);
+
+	/*
+	 * If we have an externally synchronized Linux clock, then update
+	 * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
+	 * called as close as possible to 500 ms before the new second starts.
+	 *
+	 * The division here is not time critical since it will run once in
+	 * 11 minutes
+	 */
+	if ((time_status & STA_UNSYNC) == 0 &&
+	    xtime.tv_sec > last_rtc_update + 660 &&
+	    (xtime.tv_nsec / 1000) >= 500000 - (tick_nsec / 1000) / 2 &&
+	    (xtime.tv_nsec / 1000) <= 500000 + (tick_nsec / 1000) / 2) {
+		if (set_rtc_mmss(xtime.tv_sec) == 0)
+			last_rtc_update = xtime.tv_sec;
+		else
+			last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
+	}
+        return IRQ_HANDLED;
+}
+
+/* timer is SA_SHIRQ so drivers can add stuff to the timer irq chain
+ * it needs to be SA_INTERRUPT to make the jiffies update work properly
+ */
+
+static struct irqaction irq_timer  = { timer_interrupt, SA_SHIRQ | SA_INTERRUPT,
+				  CPU_MASK_NONE, "timer", NULL, NULL};
+
+void __init
+cris_timer_init(void)
+{
+	int cpu = smp_processor_id();
+  	reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 };
+       	reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV;
+	reg_timer_rw_intr_mask timer_intr_mask;
+
+	/* Setup the etrax timers
+	 * Base frequency is 100MHz, divider 1000000 -> 100 HZ
+	 * We use timer0, so timer1 is free.
+	 * The trig timer is used by the fasttimer API if enabled.
+	 */
+
+       	tmr0_ctrl.op = regk_timer_ld;
+	tmr0_ctrl.freq = regk_timer_f100;
+       	REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div);
+       	REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */
+       	tmr0_ctrl.op = regk_timer_run;
+       	REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */
+
+       	/* enable the timer irq */
+       	timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask);
+       	timer_intr_mask.tmr0 = 1;
+       	REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask);
+}
+
+void __init
+time_init(void)
+{
+	reg_intr_vect_rw_mask intr_mask;
+
+	/* probe for the RTC and read it if it exists
+	 * Before the RTC can be probed the loops_per_usec variable needs
+	 * to be initialized to make usleep work. A better value for
+	 * loops_per_usec is calculated by the kernel later once the
+	 * clock has started.
+	 */
+	loops_per_usec = 50;
+
+	if(RTC_INIT() < 0) {
+		/* no RTC, start at 1980 */
+		xtime.tv_sec = 0;
+		xtime.tv_nsec = 0;
+		have_rtc = 0;
+	} else {
+		/* get the current time */
+		have_rtc = 1;
+		update_xtime_from_cmos();
+	}
+
+	/*
+	 * Initialize wall_to_monotonic such that adding it to xtime will yield zero, the
+	 * tv_nsec field must be normalized (i.e., 0 <= nsec < NSEC_PER_SEC).
+	 */
+	set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
+
+	/* Start CPU local timer */
+	cris_timer_init();
+
+	/* enable the timer irq in global config */
+	intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
+	intr_mask.timer = 1;
+	REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
+
+	/* now actually register the timer irq handler that calls timer_interrupt() */
+
+	setup_irq(TIMER_INTR_VECT, &irq_timer);
+
+	/* enable watchdog if we should use one */
+
+#if defined(CONFIG_ETRAX_WATCHDOG)
+	printk("Enabling watchdog...\n");
+	start_watchdog();
+
+	/* If we use the hardware watchdog, we want to trap it as an NMI
+	   and dump registers before it resets us.  For this to happen, we
+	   must set the "m" NMI enable flag (which once set, is unset only
+	   when an NMI is taken).
+
+	   The same goes for the external NMI, but that doesn't have any
+	   driver or infrastructure support yet.  */
+        {
+          unsigned long flags;
+          local_save_flags(flags);
+          flags |= (1<<30); /* NMI M flag is at bit 30 */
+          local_irq_restore(flags);
+        }
+#endif
+}
diff --git a/arch/cris/arch-v32/kernel/traps.c b/arch/cris/arch-v32/kernel/traps.c
new file mode 100644
index 00000000000..6e378704556
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/traps.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2003, Axis Communications AB.
+ */
+
+#include <linux/config.h>
+#include <linux/ptrace.h>
+#include <asm/uaccess.h>
+
+#include <asm/arch/hwregs/supp_reg.h>
+
+extern void reset_watchdog(void);
+extern void stop_watchdog(void);
+
+extern int raw_printk(const char *fmt, ...);
+
+void
+show_registers(struct pt_regs *regs)
+{
+	/*
+	 * It's possible to use either the USP register or current->thread.usp.
+	 * USP might not correspond to the current proccess for all cases this
+	 * function is called, and current->thread.usp isn't up to date for the
+	 * current proccess. Experience shows that using USP is the way to go.
+	 */
+	unsigned long usp;
+	unsigned long d_mmu_cause;
+	unsigned long i_mmu_cause;
+
+	usp = rdusp();
+
+	raw_printk("CPU: %d\n", smp_processor_id());
+
+	raw_printk("ERP: %08lx SRP: %08lx  CCS: %08lx USP: %08lx MOF: %08lx\n",
+		regs->erp, regs->srp, regs->ccs, usp, regs->mof);
+
+	raw_printk(" r0: %08lx  r1: %08lx   r2: %08lx  r3: %08lx\n",
+		regs->r0, regs->r1, regs->r2, regs->r3);
+
+	raw_printk(" r4: %08lx  r5: %08lx   r6: %08lx  r7: %08lx\n",
+		regs->r4, regs->r5, regs->r6, regs->r7);
+
+	raw_printk(" r8: %08lx  r9: %08lx  r10: %08lx r11: %08lx\n",
+		regs->r8, regs->r9, regs->r10, regs->r11);
+
+	raw_printk("r12: %08lx r13: %08lx oR10: %08lx acr: %08lx\n",
+		regs->r12, regs->r13, regs->orig_r10, regs->acr);
+
+	raw_printk("sp: %08lx\n", regs);
+
+	SUPP_BANK_SEL(BANK_IM);
+	SUPP_REG_RD(RW_MM_CAUSE, i_mmu_cause);
+
+	SUPP_BANK_SEL(BANK_DM);
+	SUPP_REG_RD(RW_MM_CAUSE, d_mmu_cause);
+
+	raw_printk("       Data MMU Cause: %08lx\n", d_mmu_cause);
+	raw_printk("Instruction MMU Cause: %08lx\n", i_mmu_cause);
+
+	raw_printk("Process %s (pid: %d, stackpage: %08lx)\n",
+		current->comm, current->pid, (unsigned long) current);
+
+	/* Show additional info if in kernel-mode. */
+	if (!user_mode(regs)) {
+		int i;
+		unsigned char c;
+
+		show_stack(NULL, (unsigned long *) usp);
+
+		/*
+		 * If the previous stack-dump wasn't a kernel one, dump the
+		 * kernel stack now.
+		 */
+		if (usp != 0)
+			show_stack(NULL, NULL);
+
+		raw_printk("\nCode: ");
+
+		if (regs->erp < PAGE_OFFSET)
+			goto bad_value;
+
+		/*
+		 * Quite often the value at regs->erp doesn't point to the
+		 * interesting instruction, which often is the previous
+		 * instruction. So dump at an offset large enough that the
+		 * instruction decoding should be in sync at the interesting
+		 * point, but small enough to fit on a row. The regs->erp
+		 * location is pointed out in a ksymoops-friendly way by
+		 * wrapping the byte for that address in parenthesis.
+		 */
+		for (i = -12; i < 12; i++) {
+			if (__get_user(c, &((unsigned char *) regs->erp)[i])) {
+bad_value:
+				raw_printk(" Bad IP value.");
+				break;
+			}
+
+			if (i == 0)
+				raw_printk("(%02x) ", c);
+			else
+				raw_printk("%02x ", c);
+		}
+
+		raw_printk("\n");
+	}
+}
+
+/*
+ * This gets called from entry.S when the watchdog has bitten. Show something
+ * similiar to an Oops dump, and if the kernel if configured to be a nice doggy;
+ * halt instead of reboot.
+ */
+void
+watchdog_bite_hook(struct pt_regs *regs)
+{
+#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
+	local_irq_disable();
+	stop_watchdog();
+	show_registers(regs);
+
+	while (1)
+		; /* Do nothing. */
+#else
+	show_registers(regs);
+#endif
+}
+
+/* This is normally the Oops function. */
+void
+die_if_kernel(const char *str, struct pt_regs *regs, long err)
+{
+	if (user_mode(regs))
+		return;
+
+#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
+	/*
+	 * This printout might take too long and could trigger
+	 * the watchdog normally. If NICE_DOGGY is set, simply
+	 * stop the watchdog during the printout.
+	 */
+	stop_watchdog();
+#endif
+
+	raw_printk("%s: %04lx\n", str, err & 0xffff);
+
+	show_registers(regs);
+
+#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
+	reset_watchdog();
+#endif
+
+	do_exit(SIGSEGV);
+}
+
+void arch_enable_nmi(void)
+{
+	unsigned long flags;
+	local_save_flags(flags);
+	flags |= (1<<30); /* NMI M flag is at bit 30 */
+	local_irq_restore(flags);
+}
diff --git a/arch/cris/arch-v32/kernel/vcs_hook.c b/arch/cris/arch-v32/kernel/vcs_hook.c
new file mode 100644
index 00000000000..64d71c54c22
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/vcs_hook.c
@@ -0,0 +1,96 @@
+// $Id: vcs_hook.c,v 1.2 2003/08/12 12:01:06 starvik Exp $
+//
+// Call simulator hook. This is the part running in the
+// simulated program.
+//
+
+#include "vcs_hook.h"
+#include <stdarg.h>
+#include <asm/arch-v32/hwregs/reg_map.h>
+#include <asm/arch-v32/hwregs/intr_vect_defs.h>
+
+#define HOOK_TRIG_ADDR     0xb7000000   /* hook cvlog model reg address */
+#define HOOK_MEM_BASE_ADDR 0xa0000000   /* csp4 (shared mem) base addr */
+
+#define HOOK_DATA(offset) ((unsigned*) HOOK_MEM_BASE_ADDR)[offset]
+#define VHOOK_DATA(offset) ((volatile unsigned*) HOOK_MEM_BASE_ADDR)[offset]
+#define HOOK_TRIG(funcid) do { *((unsigned *) HOOK_TRIG_ADDR) = funcid; } while(0)
+#define HOOK_DATA_BYTE(offset) ((unsigned char*) HOOK_MEM_BASE_ADDR)[offset]
+
+
+// ------------------------------------------------------------------ hook_call
+int hook_call( unsigned id, unsigned pcnt, ...) {
+  va_list ap;
+  unsigned i;
+  unsigned ret;
+#ifdef USING_SOS
+  PREEMPT_OFF_SAVE();
+#endif
+
+  // pass parameters
+  HOOK_DATA(0) = id;
+
+  /* Have to make hook_print_str a special case since we call with a
+     parameter of byte type. Should perhaps be a separate
+     hook_call. */
+
+  if (id == hook_print_str) {
+    int i;
+    char *str;
+
+    HOOK_DATA(1) = pcnt;
+
+    va_start(ap, pcnt);
+    str = (char*)va_arg(ap,unsigned);
+
+    for (i=0; i!=pcnt; i++) {
+      HOOK_DATA_BYTE(8+i) = str[i];
+    }
+    HOOK_DATA_BYTE(8+i) = 0;	/* null byte */
+  }
+  else {
+    va_start(ap, pcnt);
+    for( i = 1; i <= pcnt; i++ ) HOOK_DATA(i) = va_arg(ap,unsigned);
+    va_end(ap);
+  }
+
+  // read from mem to make sure data has propagated to memory before trigging
+  *((volatile unsigned*) HOOK_MEM_BASE_ADDR);
+
+  // trigger hook
+  HOOK_TRIG(id);
+
+  // wait for call to finish
+  while( VHOOK_DATA(0) > 0 ) {}
+
+  // extract return value
+
+  ret = VHOOK_DATA(1);
+
+#ifdef USING_SOS
+  PREEMPT_RESTORE();
+#endif
+  return ret;
+}
+
+unsigned
+hook_buf(unsigned i)
+{
+  return (HOOK_DATA(i));
+}
+
+void print_str( const char *str ) {
+  int i;
+  for (i=1; str[i]; i++);         /* find null at end of string */
+  hook_call(hook_print_str, i, str);
+}
+
+// --------------------------------------------------------------- CPU_KICK_DOG
+void CPU_KICK_DOG(void) {
+  (void) hook_call( hook_kick_dog, 0 );
+}
+
+// ------------------------------------------------------- CPU_WATCHDOG_TIMEOUT
+void CPU_WATCHDOG_TIMEOUT( unsigned t ) {
+  (void) hook_call( hook_dog_timeout, 1, t );
+}
diff --git a/arch/cris/arch-v32/kernel/vcs_hook.h b/arch/cris/arch-v32/kernel/vcs_hook.h
new file mode 100644
index 00000000000..7d73709e3cc
--- /dev/null
+++ b/arch/cris/arch-v32/kernel/vcs_hook.h
@@ -0,0 +1,42 @@
+// $Id: vcs_hook.h,v 1.1 2003/08/12 12:01:06 starvik Exp $
+//
+// Call simulator hook functions
+
+#ifndef HOOK_H
+#define HOOK_H
+
+int hook_call( unsigned id, unsigned pcnt, ...);
+
+enum hook_ids {
+  hook_debug_on = 1,
+  hook_debug_off,
+  hook_stop_sim_ok,
+  hook_stop_sim_fail,
+  hook_alloc_shared,
+  hook_ptr_shared,
+  hook_free_shared,
+  hook_file2shared,
+  hook_cmp_shared,
+  hook_print_params,
+  hook_sim_time,
+  hook_stop_sim,
+  hook_kick_dog,
+  hook_dog_timeout,
+  hook_rand,
+  hook_srand,
+  hook_rand_range,
+  hook_print_str,
+  hook_print_hex,
+  hook_cmp_offset_shared,
+  hook_fill_random_shared,
+  hook_alloc_random_data,
+  hook_calloc_random_data,
+  hook_print_int,
+  hook_print_uint,
+  hook_fputc,
+  hook_init_fd,
+  hook_sbrk
+
+};
+
+#endif
diff --git a/arch/cris/arch-v32/lib/Makefile b/arch/cris/arch-v32/lib/Makefile
new file mode 100644
index 00000000000..05b3ec6978d
--- /dev/null
+++ b/arch/cris/arch-v32/lib/Makefile
@@ -0,0 +1,6 @@
+#
+# Makefile for Etrax-specific library files..
+#
+
+lib-y  = checksum.o checksumcopy.o string.o usercopy.o memset.o csumcpfruser.o spinlock.o
+
diff --git a/arch/cris/arch-v32/lib/checksum.S b/arch/cris/arch-v32/lib/checksum.S
new file mode 100644
index 00000000000..32e66181b82
--- /dev/null
+++ b/arch/cris/arch-v32/lib/checksum.S
@@ -0,0 +1,111 @@
+/*
+ * A fast checksum routine using movem
+ * Copyright (c) 1998-2001, 2003 Axis Communications AB
+ *
+ * csum_partial(const unsigned char * buff, int len, unsigned int sum)
+ */
+
+	.globl	csum_partial
+csum_partial:
+
+	;; r10 - src
+	;; r11 - length
+	;; r12 - checksum
+
+	;; check for breakeven length between movem and normal word looping versions
+	;; we also do _NOT_ want to compute a checksum over more than the
+	;; actual length when length < 40
+
+	cmpu.w	80,$r11
+	blo	_word_loop
+	nop
+
+	;; need to save the registers we use below in the movem loop
+	;; this overhead is why we have a check above for breakeven length
+	;; only r0 - r8 have to be saved, the other ones are clobber-able
+	;; according to the ABI
+
+	subq	9*4,$sp
+	subq	10*4,$r11	; update length for the first loop
+	movem	$r8,[$sp]
+
+	;; do a movem checksum
+
+_mloop:	movem	[$r10+],$r9	; read 10 longwords
+
+	;; perform dword checksumming on the 10 longwords
+
+	add.d	$r0,$r12
+	addc	$r1,$r12
+	addc	$r2,$r12
+	addc	$r3,$r12
+	addc	$r4,$r12
+	addc	$r5,$r12
+	addc	$r6,$r12
+	addc	$r7,$r12
+	addc	$r8,$r12
+	addc	$r9,$r12
+
+	;; fold the carry into the checksum, to avoid having to loop the carry
+	;; back into the top
+
+	addc	0,$r12
+	addc	0,$r12		; do it again, since we might have generated a carry
+
+	subq	10*4,$r11
+	bge	_mloop
+	nop
+
+	addq	10*4,$r11	; compensate for last loop underflowing length
+
+	movem	[$sp+],$r8	; restore regs
+
+_word_loop:
+	;; only fold if there is anything to fold.
+
+	cmpq	0,$r12
+	beq	_no_fold
+
+	;; fold 32-bit checksum into a 16-bit checksum, to avoid carries below.
+	;; r9 and r13 can be used as temporaries.
+
+	moveq	-1,$r9		; put 0xffff in r9, faster than move.d 0xffff,r9
+	lsrq	16,$r9
+
+	move.d	$r12,$r13
+	lsrq	16,$r13		; r13 = checksum >> 16
+	and.d	$r9,$r12		; checksum = checksum & 0xffff
+	add.d	$r13,$r12		; checksum += r13
+	move.d	$r12,$r13		; do the same again, maybe we got a carry last add
+	lsrq	16,$r13
+	and.d	$r9,$r12
+	add.d	$r13,$r12
+
+_no_fold:
+	cmpq	2,$r11
+	blt	_no_words
+	nop
+
+	;; checksum the rest of the words
+
+	subq	2,$r11
+
+_wloop:	subq	2,$r11
+	bge	_wloop
+	addu.w	[$r10+],$r12
+
+	addq	2,$r11
+
+_no_words:
+	;; see if we have one odd byte more
+	cmpq	1,$r11
+	beq	_do_byte
+	nop
+	ret
+	move.d	$r12,$r10
+
+_do_byte:
+	;; copy and checksum the last byte
+	addu.b	[$r10],$r12
+	ret
+	move.d	$r12,$r10
diff --git a/arch/cris/arch-v32/lib/checksumcopy.S b/arch/cris/arch-v32/lib/checksumcopy.S
new file mode 100644
index 00000000000..9303ccbadc6
--- /dev/null
+++ b/arch/cris/arch-v32/lib/checksumcopy.S
@@ -0,0 +1,120 @@
+/*
+ * A fast checksum+copy routine using movem
+ * Copyright (c) 1998, 2001, 2003 Axis Communications AB
+ *
+ * Authors:	Bjorn Wesen
+ *
+ * csum_partial_copy_nocheck(const char *src, char *dst,
+ *		             int len, unsigned int sum)
+ */
+
+	.globl	csum_partial_copy_nocheck
+csum_partial_copy_nocheck:
+
+	;; r10 - src
+	;; r11 - dst
+	;; r12 - length
+	;; r13 - checksum
+
+	;; check for breakeven length between movem and normal word looping versions
+	;; we also do _NOT_ want to compute a checksum over more than the
+	;; actual length when length < 40
+
+	cmpu.w	80,$r12
+	blo	_word_loop
+	nop
+
+	;; need to save the registers we use below in the movem loop
+	;; this overhead is why we have a check above for breakeven length
+	;; only r0 - r8 have to be saved, the other ones are clobber-able
+	;; according to the ABI
+
+	subq	9*4,$sp
+	subq	10*4,$r12	; update length for the first loop
+	movem	$r8,[$sp]
+
+	;; do a movem copy and checksum
+
+1:	;; A failing userspace access (the read) will have this as PC.
+_mloop:	movem	[$r10+],$r9	; read 10 longwords
+	movem	$r9,[$r11+]	; write 10 longwords
+
+	;; perform dword checksumming on the 10 longwords
+
+	add.d	$r0,$r13
+	addc	$r1,$r13
+	addc	$r2,$r13
+	addc	$r3,$r13
+	addc	$r4,$r13
+	addc	$r5,$r13
+	addc	$r6,$r13
+	addc	$r7,$r13
+	addc	$r8,$r13
+	addc	$r9,$r13
+
+	;; fold the carry into the checksum, to avoid having to loop the carry
+	;; back into the top
+
+	addc	0,$r13
+	addc	0,$r13		; do it again, since we might have generated a carry
+
+	subq	10*4,$r12
+	bge	_mloop
+	nop
+
+	addq	10*4,$r12	; compensate for last loop underflowing length
+
+	movem	[$sp+],$r8	; restore regs
+
+_word_loop:
+	;; only fold if there is anything to fold.
+
+	cmpq	0,$r13
+	beq	_no_fold
+
+	;; fold 32-bit checksum into a 16-bit checksum, to avoid carries below
+	;; r9 can be used as temporary.
+
+	move.d	$r13,$r9
+	lsrq	16,$r9		; r0 = checksum >> 16
+	and.d	0xffff,$r13	; checksum = checksum & 0xffff
+	add.d	$r9,$r13	; checksum += r0
+	move.d	$r13,$r9	; do the same again, maybe we got a carry last add
+	lsrq	16,$r9
+	and.d	0xffff,$r13
+	add.d	$r9,$r13
+
+_no_fold:
+	cmpq	2,$r12
+	blt	_no_words
+	nop
+
+	;; copy and checksum the rest of the words
+
+	subq	2,$r12
+
+2:	;; A failing userspace access for the read below will have this as PC.
+_wloop:	move.w	[$r10+],$r9
+	addu.w	$r9,$r13
+	subq	2,$r12
+	bge	_wloop
+	move.w	$r9,[$r11+]
+
+	addq	2,$r12
+
+_no_words:
+	;; see if we have one odd byte more
+	cmpq	1,$r12
+	beq	_do_byte
+	nop
+	ret
+	move.d	$r13,$r10
+
+_do_byte:
+	;; copy and checksum the last byte
+3:	;; A failing userspace access for the read below will have this as PC.
+	move.b	[$r10],$r9
+	addu.b	$r9,$r13
+	move.b	$r9,[$r11]
+	ret
+	move.d	$r13,$r10
diff --git a/arch/cris/arch-v32/lib/csumcpfruser.S b/arch/cris/arch-v32/lib/csumcpfruser.S
new file mode 100644
index 00000000000..600ec16b9f2
--- /dev/null
+++ b/arch/cris/arch-v32/lib/csumcpfruser.S
@@ -0,0 +1,69 @@
+/*
+ * Add-on to transform csum_partial_copy_nocheck in checksumcopy.S into
+ * csum_partial_copy_from_user by adding exception records.
+ *
+ * Copyright (C) 2001, 2003 Axis Communications AB.
+ *
+ * Author: Hans-Peter Nilsson.
+ */
+
+#include <asm/errno.h>
+
+/* Same function body, but a different name.  If we just added exception
+   records to _csum_partial_copy_nocheck and made it generic, we wouldn't
+   know a user fault from a kernel fault and we would have overhead in
+   each kernel caller for the error-pointer argument.
+
+   unsigned int csum_partial_copy_from_user
+     (const char *src, char *dst, int len, unsigned int sum, int *errptr);
+
+   Note that the errptr argument is only set if we encounter an error.
+   It is conveniently located on the stack, so the normal function body
+   does not have to handle it.  */
+
+#define csum_partial_copy_nocheck csum_partial_copy_from_user
+
+/* There are local labels numbered 1, 2 and 3 present to mark the
+   different from-user accesses.  */
+#include "checksumcopy.S"
+
+	.section .fixup,"ax"
+
+;; Here from the movem loop; restore stack.
+4:
+	movem	[$sp+],$r8
+;; r12 is already decremented.  Add back chunk_size-2.
+	addq	40-2,$r12
+
+;; Here from the word loop; r12 is off by 2; add it back.
+5:
+	addq	2,$r12
+
+;; Here from a failing single byte.
+6:
+
+;; Signal in *errptr that we had a failing access.
+	move.d	[$sp],$acr
+	moveq	-EFAULT,$r9
+	subq	4,$sp
+	move.d	$r9,[$acr]
+
+;; Clear the rest of the destination area using memset.  Preserve the
+;; checksum for the readable bytes.
+	move.d	$r13,[$sp]
+	subq	4,$sp
+	move.d	$r11,$r10
+	move	$srp,[$sp]
+	jsr	memset
+	clear.d	$r11
+
+	move	[$sp+],$srp
+	ret
+	move.d	[$sp+],$r10
+
+	.previous
+	.section __ex_table,"a"
+	.dword 1b,4b
+	.dword 2b,5b
+	.dword 3b,6b
+	.previous
diff --git a/arch/cris/arch-v32/lib/dram_init.S b/arch/cris/arch-v32/lib/dram_init.S
new file mode 100644
index 00000000000..47b6cf5f4af
--- /dev/null
+++ b/arch/cris/arch-v32/lib/dram_init.S
@@ -0,0 +1,120 @@
+/* $Id: dram_init.S,v 1.4 2005/04/24 18:48:32 starvik Exp $
+ *
+ * DRAM/SDRAM initialization - alter with care
+ * This file is intended to be included from other assembler files
+ *
+ * Note: This file may not modify r8 or r9 because they are used to
+ * carry information from the decompresser to the kernel
+ *
+ * Copyright (C) 2000-2003 Axis Communications AB
+ *
+ * Authors:  Mikael Starvik (starvik@axis.com)
+ */
+
+/* Just to be certain the config file is included, we include it here
+ * explicitely instead of depending on it being included in the file that
+ * uses this code.
+ */
+
+#include <linux/config.h>
+#include <asm/arch/hwregs/asm/reg_map_asm.h>
+#include <asm/arch/hwregs/asm/bif_core_defs_asm.h>
+
+	;; WARNING! The registers r8 and r9 are used as parameters carrying
+	;; information from the decompressor (if the kernel was compressed).
+	;; They should not be used in the code below.
+
+	; Refer to BIF MDS for a description of SDRAM initialization
+
+	; Bank configuration
+	move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0), $r0
+	move.d   CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
+	move.d   $r1, [$r0]
+	move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1), $r0
+	move.d   CONFIG_ETRAX_SDRAM_GRP1_CONFIG, $r1
+	move.d   $r1, [$r0]
+
+	; Calculate value of mrs_data
+	; CAS latency = 2 && bus_width = 32 => 0x40
+	; CAS latency = 3 && bus_width = 32 => 0x60
+	; CAS latency = 2 && bus_width = 16 => 0x20
+	; CAS latency = 3 && bus_width = 16 => 0x30
+
+	; Check if value is already supplied in kernel config
+	move.d   CONFIG_ETRAX_SDRAM_COMMAND, $r2
+	bne	 _set_timing
+	nop
+
+	move.d   0x40, $r4       ; Assume 32 bits and CAS latency = 2
+	move.d   CONFIG_ETRAX_SDRAM_TIMING, $r1
+ 	and.d    0x07, $r1       ; Get CAS latency
+	cmpq	 2, $r1		 ; CL = 2 ?
+	beq	 _bw_check
+	nop
+	move.d   0x60, $r4
+
+_bw_check:
+	; Assume that group 0 width is equal to group 1. This assumption
+	; is wrong for a group 1 only hardware (such as the grand old
+	; StorPoint+).
+	move.d   CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
+	and.d    0x200, $r1	; DRAM width is bit 9
+	beq      _set_timing
+	lslq	 2, $r4		;  mrs_data starts at bit 2
+	lsrq     1, $r4		;  16 bits. Shift down value.
+
+	; Set timing parameters (refresh off to avoid Guinness TR 83)
+_set_timing:
+	move.d   CONFIG_ETRAX_SDRAM_TIMING, $r1
+	and.d    ~(3 << reg_bif_core_rw_sdram_timing___ref___lsb), $r1
+	move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0
+	move.d   $r1, [$r0]
+
+	; Issue NOP command
+	move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd), $r5
+	moveq regk_bif_core_nop, $r1
+	move.d $r1, [$r5]
+
+	; Wait 200us
+	move.d   10000, $r2
+1:	bne      1b
+	subq     1, $r2
+
+	; Issue initialization command sequence
+	move.d   _sdram_commands_start, $r2
+	and.d    0x000fffff, $r2 ; Make sure commands are read from flash
+	move.d   _sdram_commands_end,  $r3
+	and.d    0x000fffff, $r3
+1:	clear.d  $r6
+	move.b   [$r2+], $r6 	; Load command
+	or.d     $r4, $r6	; Add calculated mrs
+	move.d   $r6, [$r5]	; Write rw_sdram_cmd
+	; Wait 80 ns between each command
+	move.d	 4000, $r7
+2:	bne	 2b
+	subq	 1, $r7
+	cmp.d    $r2, $r3	; Last command?
+	bne      1b
+	nop
+
+	; Start refresh
+	move.d   CONFIG_ETRAX_SDRAM_TIMING, $r1
+	move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0
+	move.d   $r1, [$r0]
+
+	; Initialization finished
+	ba       _sdram_commands_end
+	nop
+
+_sdram_commands_start:
+	.byte   regk_bif_core_pre ; Precharge
+	.byte   regk_bif_core_ref ; refresh
+	.byte   regk_bif_core_ref ; refresh
+	.byte   regk_bif_core_ref ; refresh
+	.byte   regk_bif_core_ref ; refresh
+	.byte   regk_bif_core_ref ; refresh
+	.byte   regk_bif_core_ref ; refresh
+	.byte   regk_bif_core_ref ; refresh
+	.byte   regk_bif_core_ref ; refresh
+	.byte   regk_bif_core_mrs ; mrs
+_sdram_commands_end:
diff --git a/arch/cris/arch-v32/lib/hw_settings.S b/arch/cris/arch-v32/lib/hw_settings.S
new file mode 100644
index 00000000000..5182e8c2cff
--- /dev/null
+++ b/arch/cris/arch-v32/lib/hw_settings.S
@@ -0,0 +1,73 @@
+/*
+ * $Id: hw_settings.S,v 1.3 2005/04/24 18:36:57 starvik Exp $
+ *
+ * This table is used by some tools to extract hardware parameters.
+ * The table should be included in the kernel and the decompressor.
+ * Don't forget to update the tools if you change this table.
+ *
+ * Copyright (C) 2001 Axis Communications AB
+ *
+ * Authors:  Mikael Starvik (starvik@axis.com)
+ */
+
+#include <linux/config.h>
+#include <asm/arch/hwregs/asm/reg_map_asm.h>
+#include <asm/arch/hwregs/asm/bif_core_defs_asm.h>
+#include <asm/arch/hwregs/asm/gio_defs_asm.h>
+
+	.ascii "HW_PARAM_MAGIC" ; Magic number
+	.dword 0xc0004000	; Kernel start address
+
+	; Debug port
+#ifdef CONFIG_ETRAX_DEBUG_PORT0
+	.dword 0
+#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
+	.dword 1
+#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
+	.dword 2
+#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
+	.dword 3
+#else
+	.dword 4 ; No debug
+#endif
+
+	; Register values
+	.dword REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg)
+	.dword CONFIG_ETRAX_MEM_GRP1_CONFIG
+	.dword REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg)
+	.dword CONFIG_ETRAX_MEM_GRP2_CONFIG
+	.dword REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg)
+	.dword CONFIG_ETRAX_MEM_GRP3_CONFIG
+	.dword REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg)
+	.dword CONFIG_ETRAX_MEM_GRP4_CONFIG
+	.dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0)
+	.dword CONFIG_ETRAX_SDRAM_GRP0_CONFIG
+	.dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1)
+	.dword CONFIG_ETRAX_SDRAM_GRP1_CONFIG
+	.dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing)
+	.dword CONFIG_ETRAX_SDRAM_TIMING
+	.dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd)
+	.dword CONFIG_ETRAX_SDRAM_COMMAND
+
+	.dword REG_ADDR(gio, regi_gio, rw_pa_dout)
+	.dword CONFIG_ETRAX_DEF_GIO_PA_OUT
+	.dword REG_ADDR(gio, regi_gio, rw_pa_oe)
+	.dword CONFIG_ETRAX_DEF_GIO_PA_OE
+	.dword REG_ADDR(gio, regi_gio, rw_pb_dout)
+	.dword CONFIG_ETRAX_DEF_GIO_PB_OUT
+	.dword REG_ADDR(gio, regi_gio, rw_pb_oe)
+	.dword CONFIG_ETRAX_DEF_GIO_PB_OE
+	.dword REG_ADDR(gio, regi_gio, rw_pc_dout)
+	.dword CONFIG_ETRAX_DEF_GIO_PC_OUT
+	.dword REG_ADDR(gio, regi_gio, rw_pc_oe)
+	.dword CONFIG_ETRAX_DEF_GIO_PC_OE
+	.dword REG_ADDR(gio, regi_gio, rw_pd_dout)
+	.dword CONFIG_ETRAX_DEF_GIO_PD_OUT
+	.dword REG_ADDR(gio, regi_gio, rw_pd_oe)
+	.dword CONFIG_ETRAX_DEF_GIO_PD_OE
+	.dword REG_ADDR(gio, regi_gio, rw_pe_dout)
+	.dword CONFIG_ETRAX_DEF_GIO_PE_OUT
+	.dword REG_ADDR(gio, regi_gio, rw_pe_oe)
+	.dword CONFIG_ETRAX_DEF_GIO_PE_OE
+
+	.dword 0 ; No more register values
diff --git a/arch/cris/arch-v32/lib/memset.c b/arch/cris/arch-v32/lib/memset.c
new file mode 100644
index 00000000000..ffca1214674
--- /dev/null
+++ b/arch/cris/arch-v32/lib/memset.c
@@ -0,0 +1,253 @@
+/*#************************************************************************#*/
+/*#-------------------------------------------------------------------------*/
+/*#                                                                         */
+/*# FUNCTION NAME: memset()                                                 */
+/*#                                                                         */
+/*# PARAMETERS:  void* dst;   Destination address.                          */
+/*#              int     c;   Value of byte to write.                       */
+/*#              int   len;   Number of bytes to write.                     */
+/*#                                                                         */
+/*# RETURNS:     dst.                                                       */
+/*#                                                                         */
+/*# DESCRIPTION: Sets the memory dst of length len bytes to c, as standard. */
+/*#              Framework taken from memcpy.  This routine is              */
+/*#              very sensitive to compiler changes in register allocation. */
+/*#              Should really be rewritten to avoid this problem.          */
+/*#                                                                         */
+/*#-------------------------------------------------------------------------*/
+/*#                                                                         */
+/*# HISTORY                                                                 */
+/*#                                                                         */
+/*# DATE      NAME            CHANGES                                       */
+/*# ----      ----            -------                                       */
+/*# 990713    HP              Tired of watching this function (or           */
+/*#                           really, the nonoptimized generic              */
+/*#                           implementation) take up 90% of simulator      */
+/*#                           output.  Measurements needed.                 */
+/*#                                                                         */
+/*#-------------------------------------------------------------------------*/
+
+#include <linux/types.h>
+
+/* No, there's no macro saying 12*4, since it is "hard" to get it into
+   the asm in a good way.  Thus better to expose the problem everywhere.
+   */
+
+/* Assuming 1 cycle per dword written or read (ok, not really true), and
+   one per instruction, then 43+3*(n/48-1) <= 24+24*(n/48-1)
+   so n >= 45.7; n >= 0.9; we win on the first full 48-byte block to set. */
+
+#define ZERO_BLOCK_SIZE (1*12*4)
+
+void *memset(void *pdst,
+             int c,
+             size_t plen)
+{
+  /* Ok.  Now we want the parameters put in special registers.
+     Make sure the compiler is able to make something useful of this. */
+
+  register char *return_dst __asm__ ("r10") = pdst;
+  register int n __asm__ ("r12") = plen;
+  register int lc __asm__ ("r11") = c;
+
+  /* Most apps use memset sanely.  Only those memsetting about 3..4
+     bytes or less get penalized compared to the generic implementation
+     - and that's not really sane use. */
+
+  /* Ugh.  This is fragile at best.  Check with newer GCC releases, if
+     they compile cascaded "x |= x << 8" sanely! */
+  __asm__("movu.b %0,$r13	\n\
+           lslq 8,$r13		\n\
+	   move.b %0,$r13	\n\
+	   move.d $r13,%0	\n\
+	   lslq 16,$r13		\n\
+	   or.d $r13,%0"
+          : "=r" (lc) : "0" (lc) : "r13");
+
+  {
+    register char *dst __asm__ ("r13") = pdst;
+
+  /* This is NONPORTABLE, but since this whole routine is     */
+  /* grossly nonportable that doesn't matter.                 */
+
+  if (((unsigned long) pdst & 3) != 0
+     /* Oops! n=0 must be a legal call, regardless of alignment. */
+      && n >= 3)
+  {
+    if ((unsigned long)dst & 1)
+    {
+      *dst = (char) lc;
+      n--;
+      dst++;
+    }
+
+    if ((unsigned long)dst & 2)
+    {
+      *(short *)dst = lc;
+      n -= 2;
+      dst += 2;
+    }
+  }
+
+  /* Now the fun part.  For the threshold value of this, check the equation
+     above. */
+  /* Decide which copying method to use. */
+  if (n >= ZERO_BLOCK_SIZE)
+  {
+    /* For large copies we use 'movem' */
+
+  /* It is not optimal to tell the compiler about clobbering any
+     registers; that will move the saving/restoring of those registers
+     to the function prologue/epilogue, and make non-movem sizes
+     suboptimal.
+
+      This method is not foolproof; it assumes that the "asm reg"
+     declarations at the beginning of the function really are used
+     here (beware: they may be moved to temporary registers).
+      This way, we do not have to save/move the registers around into
+     temporaries; we can safely use them straight away.
+
+      If you want to check that the allocation was right; then
+      check the equalities in the first comment.  It should say
+      "r13=r13, r12=r12, r11=r11" */
+    __asm__ volatile ("							\n\
+        ;; Check that the register asm declaration got right.		\n\
+        ;; The GCC manual says it will work, but there *has* been bugs.	\n\
+	.ifnc %0-%1-%4,$r13-$r12-$r11					\n\
+	.err								\n\
+	.endif								\n\
+									\n\
+	;; Save the registers we'll clobber in the movem process	\n\
+	;; on the stack.  Don't mention them to gcc, it will only be	\n\
+	;; upset.							\n\
+	subq 	11*4,$sp						\n\
+        movem   $r10,[$sp]						\n\
+									\n\
+        move.d  $r11,$r0						\n\
+        move.d  $r11,$r1						\n\
+        move.d  $r11,$r2						\n\
+        move.d  $r11,$r3						\n\
+        move.d  $r11,$r4						\n\
+        move.d  $r11,$r5						\n\
+        move.d  $r11,$r6						\n\
+        move.d  $r11,$r7						\n\
+        move.d  $r11,$r8						\n\
+        move.d  $r11,$r9						\n\
+        move.d  $r11,$r10						\n\
+									\n\
+        ;; Now we've got this:						\n\
+	;; r13 - dst							\n\
+	;; r12 - n							\n\
+									\n\
+        ;; Update n for the first loop					\n\
+        subq    12*4,$r12						\n\
+0:									\n\
+        subq   12*4,$r12						\n\
+        bge     0b							\n\
+	movem	$r11,[$r13+]						\n\
+									\n\
+        addq   12*4,$r12  ;; compensate for last loop underflowing n	\n\
+									\n\
+	;; Restore registers from stack					\n\
+        movem [$sp+],$r10"
+
+     /* Outputs */ : "=r" (dst), "=r" (n)
+     /* Inputs */ : "0" (dst), "1" (n), "r" (lc));
+  }
+
+    /* Either we directly starts copying, using dword copying
+       in a loop, or we copy as much as possible with 'movem'
+       and then the last block (<44 bytes) is copied here.
+       This will work since 'movem' will have updated src,dst,n. */
+
+    while ( n >= 16 )
+    {
+      *((long*)dst)++ = lc;
+      *((long*)dst)++ = lc;
+      *((long*)dst)++ = lc;
+      *((long*)dst)++ = lc;
+      n -= 16;
+    }
+
+    /* A switch() is definitely the fastest although it takes a LOT of code.
+     * Particularly if you inline code this.
+     */
+    switch (n)
+    {
+      case 0:
+        break;
+      case 1:
+        *(char*)dst = (char) lc;
+        break;
+      case 2:
+        *(short*)dst = (short) lc;
+        break;
+      case 3:
+        *((short*)dst)++ = (short) lc;
+        *(char*)dst = (char) lc;
+        break;
+      case 4:
+        *((long*)dst)++ = lc;
+        break;
+      case 5:
+        *((long*)dst)++ = lc;
+        *(char*)dst = (char) lc;
+        break;
+      case 6:
+        *((long*)dst)++ = lc;
+        *(short*)dst = (short) lc;
+        break;
+      case 7:
+        *((long*)dst)++ = lc;
+        *((short*)dst)++ = (short) lc;
+        *(char*)dst = (char) lc;
+        break;
+      case 8:
+        *((long*)dst)++ = lc;
+        *((long*)dst)++ = lc;
+        break;
+      case 9:
+        *((long*)dst)++ = lc;
+        *((long*)dst)++ = lc;
+        *(char*)dst = (char) lc;
+        break;
+      case 10:
+        *((long*)dst)++ = lc;
+        *((long*)dst)++ = lc;
+        *(short*)dst = (short) lc;
+        break;
+      case 11:
+        *((long*)dst)++ = lc;
+        *((long*)dst)++ = lc;
+        *((short*)dst)++ = (short) lc;
+        *(char*)dst = (char) lc;
+        break;
+      case 12:
+        *((long*)dst)++ = lc;
+        *((long*)dst)++ = lc;
+        *((long*)dst)++ = lc;
+        break;
+      case 13:
+        *((long*)dst)++ = lc;
+        *((long*)dst)++ = lc;
+        *((long*)dst)++ = lc;
+        *(char*)dst = (char) lc;
+        break;
+      case 14:
+        *((long*)dst)++ = lc;
+        *((long*)dst)++ = lc;
+        *((long*)dst)++ = lc;
+        *(short*)dst = (short) lc;
+        break;
+      case 15:
+        *((long*)dst)++ = lc;
+        *((long*)dst)++ = lc;
+        *((long*)dst)++ = lc;
+        *((short*)dst)++ = (short) lc;
+        *(char*)dst = (char) lc;
+        break;
+    }
+  }
+
+  return return_dst; /* destination pointer. */
+} /* memset() */
diff --git a/arch/cris/arch-v32/lib/nand_init.S b/arch/cris/arch-v32/lib/nand_init.S
new file mode 100644
index 00000000000..aba5c751c28
--- /dev/null
+++ b/arch/cris/arch-v32/lib/nand_init.S
@@ -0,0 +1,179 @@
+##=============================================================================
+##
+##      nand_init.S
+##
+##      The bootrom copies data from the NAND flash to the internal RAM but
+##      due to a bug/feature we can only trust the 256 first bytes. So this
+##      code copies more data from NAND flash to internal RAM. Obvioulsy this
+##      code must fit in the first 256 bytes so alter with care.
+##
+##	Some notes about the bug/feature for future reference:
+##        The bootrom copies the first 127 KB from NAND flash to internal
+##        memory. The problem is that it does a bytewise copy. NAND flashes
+##        does autoincrement on the address so for a 16-bite device each
+##        read/write increases the address by two. So the copy loop in the
+##        bootrom will discard every second byte. This is solved by inserting
+##        zeroes in every second byte in the first erase block.
+##
+##        The bootrom also incorrectly assumes that it can read the flash
+##        linear with only one read command but the flash will actually
+##        switch between normal area and spare area if you do that so we
+##        can't trust more than the first 256 bytes.
+##
+##=============================================================================
+
+#include <asm/arch/hwregs/asm/reg_map_asm.h>
+#include <asm/arch/hwregs/asm/gio_defs_asm.h>
+#include <asm/arch/hwregs/asm/pinmux_defs_asm.h>
+#include <asm/arch/hwregs/asm/bif_core_defs_asm.h>
+#include <asm/arch/hwregs/asm/config_defs_asm.h>
+#include <linux/config.h>
+
+;; There are 8-bit NAND flashes and 16-bit NAND flashes.
+;; We need to treat them slightly different.
+#if CONFIG_ETRAX_FLASH_BUSWIDTH==2
+#define PAGE_SIZE 256
+#else
+#error 2
+#define PAGE_SIZE 512
+#endif
+#define ERASE_BLOCK 16384
+
+;; GPIO pins connected to NAND flash
+#define CE 4
+#define CLE 5
+#define ALE 6
+#define BY 7
+
+;; Address space for NAND flash
+#define NAND_RD_ADDR 0x90000000
+#define NAND_WR_ADDR 0x94000000
+
+#define READ_CMD 0x00
+
+;; Readability macros
+#define CSP_MASK \
+	REG_MASK(bif_core, rw_grp3_cfg, gated_csp0) | \
+	REG_MASK(bif_core, rw_grp3_cfg, gated_csp1)
+#define CSP_VAL \
+	REG_STATE(bif_core, rw_grp3_cfg, gated_csp0, rd) | \
+	REG_STATE(bif_core, rw_grp3_cfg, gated_csp1, wr)
+
+;;----------------------------------------------------------------------------
+;; Macros to set/clear GPIO bits
+
+.macro SET x
+	or.b   (1<<\x),$r9
+	move.d $r9, [$r2]
+.endm
+
+.macro CLR x
+	and.b  ~(1<<\x),$r9
+	move.d $r9, [$r2]
+.endm
+
+;;----------------------------------------------------------------------------
+
+nand_boot:
+	;; Check if nand boot was selected
+	move.d REG_ADDR(config, regi_config, r_bootsel), $r0
+	move.d [$r0], $r0
+	and.d  REG_MASK(config, r_bootsel, boot_mode), $r0
+	cmp.d  REG_STATE(config, r_bootsel, boot_mode, nand), $r0
+	bne normal_boot ; No NAND boot
+	nop
+
+copy_nand_to_ram:
+	;; copy_nand_to_ram
+	;; Arguments
+	;;   r10 - destination
+	;;   r11 - source offset
+	;;   r12 - size
+	;;   r13 - Address to jump to after completion
+	;; Note : r10-r12 are clobbered on return
+	;; Registers used:
+	;;   r0 - NAND_RD_ADDR
+	;;   r1 - NAND_WR_ADDR
+	;;   r2 - reg_gio_rw_pa_dout
+	;;   r3 - reg_gio_r_pa_din
+	;;   r4 - tmp
+	;;   r5 - byte counter within a page
+	;;   r6 - reg_pinmux_rw_pa
+	;;   r7 - reg_gio_rw_pa_oe
+	;;   r8 - reg_bif_core_rw_grp3_cfg
+	;;   r9 - reg_gio_rw_pa_dout shadow
+	move.d 0x90000000, $r0
+	move.d 0x94000000, $r1
+	move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r2
+	move.d REG_ADDR(gio, regi_gio, r_pa_din), $r3
+	move.d REG_ADDR(pinmux, regi_pinmux, rw_pa), $r6
+	move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r7
+	move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r8
+
+#if CONFIG_ETRAX_FLASH_BUSWIDTH==2
+	lsrq	1, $r11
+#endif
+	;; Set up GPIO
+	move.d [$r2], $r9
+	move.d [$r7], $r4
+	or.b (1<<ALE) | (1 << CLE) | (1<<CE), $r4
+	move.d $r4, [$r7]
+
+	;; Set up bif
+	move.d [$r8], $r4
+	and.d CSP_MASK, $r4
+	or.d CSP_VAL, $r4
+	move.d $r4, [$r8]
+
+1:	;; Copy one page
+	CLR CE
+	SET CLE
+	moveq	READ_CMD, $r4
+	move.b	$r4, [$r1]
+	moveq	20, $r4
+2:	bne	2b
+	subq	1, $r4
+	CLR CLE
+	SET ALE
+	clear.w [$r1] 		; Column address = 0
+	move.d	$r11, $r4
+	lsrq	8, $r4
+	move.b	$r4, [$r1]	; Row address
+	lsrq	8, $r4
+	move.b	$r4, [$r1]	; Row adddress
+	moveq	20, $r4
+2:	bne	2b
+	subq	1, $r4
+	CLR ALE
+2:	move.d	[$r3], $r4
+	and.d	1 << BY, $r4
+	beq 2b
+	movu.w  PAGE_SIZE, $r5
+2:	; Copy one byte/word
+#if CONFIG_ETRAX_FLASH_BUSWIDTH==2
+	move.w  [$r0], $r4
+#else
+	move.b  [$r0], $r4
+#endif
+	subq	1, $r5
+	bne	2b
+#if CONFIG_ETRAX_FLASH_BUSWIDTH==2
+	move.w  $r4, [$r10+]
+	subu.w	PAGE_SIZE*2, $r12
+#else
+	move.b  $r4, [$r10+]
+	subu.w	PAGE_SIZE, $r12
+#endif
+	bpl	1b
+	addu.w	PAGE_SIZE, $r11
+
+	;; End of copy
+	jump	$r13
+	nop
+
+	;; This will warn if the code above is too large. If you consider
+	;; to remove this you don't understand the bug/feature.
+	.org 256
+	.org ERASE_BLOCK
+
+normal_boot:
diff --git a/arch/cris/arch-v32/lib/spinlock.S b/arch/cris/arch-v32/lib/spinlock.S
new file mode 100644
index 00000000000..2437ae7f6ed
--- /dev/null
+++ b/arch/cris/arch-v32/lib/spinlock.S
@@ -0,0 +1,33 @@
+;; Core of the spinlock implementation
+;;
+;; Copyright (C) 2004 Axis Communications AB.
+;;
+;; Author: Mikael Starvik
+
+
+	.global cris_spin_lock
+	.global cris_spin_trylock
+
+	.text
+
+cris_spin_lock:
+	clearf	p
+1:	test.d	[$r10]
+	beq	1b
+	clearf	p
+	ax
+	clear.d [$r10]
+	bcs     1b
+	clearf	p
+	ret
+	nop
+
+cris_spin_trylock:
+	clearf	p
+1:	move.d	[$r10], $r11
+	ax
+	clear.d [$r10]
+        bcs	1b
+        clearf	p
+	ret
+	move.d	$r11,$r10
diff --git a/arch/cris/arch-v32/lib/string.c b/arch/cris/arch-v32/lib/string.c
new file mode 100644
index 00000000000..98e282ac824
--- /dev/null
+++ b/arch/cris/arch-v32/lib/string.c
@@ -0,0 +1,219 @@
+/*#************************************************************************#*/
+/*#-------------------------------------------------------------------------*/
+/*#                                                                         */
+/*# FUNCTION NAME: memcpy()                                                 */
+/*#                                                                         */
+/*# PARAMETERS:  void* dst;   Destination address.                          */
+/*#              void* src;   Source address.                               */
+/*#              int   len;   Number of bytes to copy.                      */
+/*#                                                                         */
+/*# RETURNS:     dst.                                                       */
+/*#                                                                         */
+/*# DESCRIPTION: Copies len bytes of memory from src to dst.  No guarantees */
+/*#              about copying of overlapping memory areas. This routine is */
+/*#              very sensitive to compiler changes in register allocation. */
+/*#              Should really be rewritten to avoid this problem.          */
+/*#                                                                         */
+/*#-------------------------------------------------------------------------*/
+/*#                                                                         */
+/*# HISTORY                                                                 */
+/*#                                                                         */
+/*# DATE      NAME            CHANGES                                       */
+/*# ----      ----            -------                                       */
+/*# 941007    Kenny R         Creation                                      */
+/*# 941011    Kenny R         Lots of optimizations and inlining.           */
+/*# 941129    Ulf A           Adapted for use in libc.                      */
+/*# 950216    HP              N==0 forgotten if non-aligned src/dst.        */
+/*#                           Added some optimizations.                     */
+/*# 001025    HP              Make src and dst char *.  Align dst to	    */
+/*#			      dword, not just word-if-both-src-and-dst-	    */
+/*#			      are-misaligned.				    */
+/*#                                                                         */
+/*#-------------------------------------------------------------------------*/
+
+#include <linux/types.h>
+
+void *memcpy(void *pdst,
+             const void *psrc,
+             size_t pn)
+{
+  /* Ok.  Now we want the parameters put in special registers.
+     Make sure the compiler is able to make something useful of this.
+      As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
+
+     If gcc was allright, it really would need no temporaries, and no
+     stack space to save stuff on. */
+
+  register void *return_dst __asm__ ("r10") = pdst;
+  register char *dst __asm__ ("r13") = pdst;
+  register const char *src __asm__ ("r11") = psrc;
+  register int n __asm__ ("r12") = pn;
+
+
+  /* When src is aligned but not dst, this makes a few extra needless
+     cycles.  I believe it would take as many to check that the
+     re-alignment was unnecessary.  */
+  if (((unsigned long) dst & 3) != 0
+      /* Don't align if we wouldn't copy more than a few bytes; so we
+	 don't have to check further for overflows.  */
+      && n >= 3)
+  {
+    if ((unsigned long) dst & 1)
+    {
+      n--;
+      *(char*)dst = *(char*)src;
+      src++;
+      dst++;
+    }
+
+    if ((unsigned long) dst & 2)
+    {
+      n -= 2;
+      *(short*)dst = *(short*)src;
+      src += 2;
+      dst += 2;
+    }
+  }
+
+  /* Decide which copying method to use.  Movem is dirt cheap, so the
+     overheap is low enough to always use the minimum block size as the
+     threshold.  */
+  if (n >= 44)
+  {
+    /* For large copies we use 'movem' */
+
+  /* It is not optimal to tell the compiler about clobbering any
+     registers; that will move the saving/restoring of those registers
+     to the function prologue/epilogue, and make non-movem sizes
+     suboptimal.  */
+    __asm__ volatile ("							\n\
+        ;; Check that the register asm declaration got right.		\n\
+        ;; The GCC manual explicitly says TRT will happen.		\n\
+	.ifnc %0-%1-%2,$r13-$r11-$r12					\n\
+	.err								\n\
+	.endif								\n\
+									\n\
+	;; Save the registers we'll use in the movem process		\n\
+									\n\
+	;; on the stack.						\n\
+	subq 	11*4,$sp						\n\
+	movem	$r10,[$sp]						\n\
+									\n\
+        ;; Now we've got this:						\n\
+	;; r11 - src							\n\
+	;; r13 - dst							\n\
+	;; r12 - n							\n\
+									\n\
+        ;; Update n for the first loop					\n\
+        subq    44,$r12							\n\
+0:									\n\
+	movem	[$r11+],$r10						\n\
+        subq   44,$r12							\n\
+        bge     0b							\n\
+	movem	$r10,[$r13+]						\n\
+									\n\
+        addq   44,$r12  ;; compensate for last loop underflowing n	\n\
+									\n\
+	;; Restore registers from stack					\n\
+        movem [$sp+],$r10"
+
+     /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n)
+     /* Inputs */ : "0" (dst), "1" (src), "2" (n));
+
+  }
+
+  /* Either we directly starts copying, using dword copying
+     in a loop, or we copy as much as possible with 'movem'
+     and then the last block (<44 bytes) is copied here.
+     This will work since 'movem' will have updated src,dst,n. */
+
+  while ( n >= 16 )
+  {
+    *((long*)dst)++ = *((long*)src)++;
+    *((long*)dst)++ = *((long*)src)++;
+    *((long*)dst)++ = *((long*)src)++;
+    *((long*)dst)++ = *((long*)src)++;
+    n -= 16;
+  }
+
+  /* A switch() is definitely the fastest although it takes a LOT of code.
+   * Particularly if you inline code this.
+   */
+  switch (n)
+  {
+    case 0:
+      break;
+    case 1:
+      *(char*)dst = *(char*)src;
+      break;
+    case 2:
+      *(short*)dst = *(short*)src;
+      break;
+    case 3:
+      *((short*)dst)++ = *((short*)src)++;
+      *(char*)dst = *(char*)src;
+      break;
+    case 4:
+      *((long*)dst)++ = *((long*)src)++;
+      break;
+    case 5:
+      *((long*)dst)++ = *((long*)src)++;
+      *(char*)dst = *(char*)src;
+      break;
+    case 6:
+      *((long*)dst)++ = *((long*)src)++;
+      *(short*)dst = *(short*)src;
+      break;
+    case 7:
+      *((long*)dst)++ = *((long*)src)++;
+      *((short*)dst)++ = *((short*)src)++;
+      *(char*)dst = *(char*)src;
+      break;
+    case 8:
+      *((long*)dst)++ = *((long*)src)++;
+      *((long*)dst)++ = *((long*)src)++;
+      break;
+    case 9:
+      *((long*)dst)++ = *((long*)src)++;
+      *((long*)dst)++ = *((long*)src)++;
+      *(char*)dst = *(char*)src;
+      break;
+    case 10:
+      *((long*)dst)++ = *((long*)src)++;
+      *((long*)dst)++ = *((long*)src)++;
+      *(short*)dst = *(short*)src;
+      break;
+    case 11:
+      *((long*)dst)++ = *((long*)src)++;
+      *((long*)dst)++ = *((long*)src)++;
+      *((short*)dst)++ = *((short*)src)++;
+      *(char*)dst = *(char*)src;
+      break;
+    case 12:
+      *((long*)dst)++ = *((long*)src)++;
+      *((long*)dst)++ = *((long*)src)++;
+      *((long*)dst)++ = *((long*)src)++;
+      break;
+    case 13:
+      *((long*)dst)++ = *((long*)src)++;
+      *((long*)dst)++ = *((long*)src)++;
+      *((long*)dst)++ = *((long*)src)++;
+      *(char*)dst = *(char*)src;
+      break;
+    case 14:
+      *((long*)dst)++ = *((long*)src)++;
+      *((long*)dst)++ = *((long*)src)++;
+      *((long*)dst)++ = *((long*)src)++;
+      *(short*)dst = *(short*)src;
+      break;
+    case 15:
+      *((long*)dst)++ = *((long*)src)++;
+      *((long*)dst)++ = *((long*)src)++;
+      *((long*)dst)++ = *((long*)src)++;
+      *((short*)dst)++ = *((short*)src)++;
+      *(char*)dst = *(char*)src;
+      break;
+  }
+
+  return return_dst; /* destination pointer. */
+} /* memcpy() */
diff --git a/arch/cris/arch-v32/lib/usercopy.c b/arch/cris/arch-v32/lib/usercopy.c
new file mode 100644
index 00000000000..f0b08460c1b
--- /dev/null
+++ b/arch/cris/arch-v32/lib/usercopy.c
@@ -0,0 +1,470 @@
+/*
+ * User address space access functions.
+ * The non-inlined parts of asm-cris/uaccess.h are here.
+ *
+ * Copyright (C) 2000, 2003 Axis Communications AB.
+ *
+ * Written by Hans-Peter Nilsson.
+ * Pieces used from memcpy, originally by Kenny Ranerup long time ago.
+ */
+
+#include <asm/uaccess.h>
+
+/* Asm:s have been tweaked (within the domain of correctness) to give
+   satisfactory results for "gcc version 3.2.1 Axis release R53/1.53-v32".
+
+   Check regularly...
+
+   Note that for CRISv32, the PC saved at a bus-fault is the address
+   *at* the faulting instruction, with a special case for instructions
+   in delay slots: then it's the address of the branch.  Note also that
+   in contrast to v10, a postincrement in the instruction is *not*
+   performed at a bus-fault; the register is seen having the original
+   value in fault handlers.  */
+
+
+/* Copy to userspace.  This is based on the memcpy used for
+   kernel-to-kernel copying; see "string.c".  */
+
+unsigned long
+__copy_user (void __user *pdst, const void *psrc, unsigned long pn)
+{
+  /* We want the parameters put in special registers.
+     Make sure the compiler is able to make something useful of this.
+     As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
+
+     FIXME: Comment for old gcc version.  Check.
+     If gcc was allright, it really would need no temporaries, and no
+     stack space to save stuff on. */
+
+  register char *dst __asm__ ("r13") = pdst;
+  register const char *src __asm__ ("r11") = psrc;
+  register int n __asm__ ("r12") = pn;
+  register int retn __asm__ ("r10") = 0;
+
+
+  /* When src is aligned but not dst, this makes a few extra needless
+     cycles.  I believe it would take as many to check that the
+     re-alignment was unnecessary.  */
+  if (((unsigned long) dst & 3) != 0
+      /* Don't align if we wouldn't copy more than a few bytes; so we
+	 don't have to check further for overflows.  */
+      && n >= 3)
+  {
+    if ((unsigned long) dst & 1)
+    {
+      __asm_copy_to_user_1 (dst, src, retn);
+      n--;
+    }
+
+    if ((unsigned long) dst & 2)
+    {
+      __asm_copy_to_user_2 (dst, src, retn);
+      n -= 2;
+    }
+  }
+
+  /* Movem is dirt cheap.  The overheap is low enough to always use the
+     minimum possible block size as the threshold.  */
+  if (n >= 44)
+  {
+    /* For large copies we use 'movem'.  */
+
+    /* It is not optimal to tell the compiler about clobbering any
+       registers; that will move the saving/restoring of those registers
+       to the function prologue/epilogue, and make non-movem sizes
+       suboptimal.  */
+    __asm__ volatile ("\
+        ;; Check that the register asm declaration got right.		\n\
+        ;; The GCC manual explicitly says TRT will happen.		\n\
+	.ifnc %0%1%2%3,$r13$r11$r12$r10					\n\
+	.err								\n\
+	.endif								\n\
+									\n\
+	;; Save the registers we'll use in the movem process		\n\
+	;; on the stack.						\n\
+	subq	11*4,$sp						\n\
+	movem	$r10,[$sp]						\n\
+									\n\
+	;; Now we've got this:						\n\
+	;; r11 - src							\n\
+	;; r13 - dst							\n\
+	;; r12 - n							\n\
+									\n\
+	;; Update n for the first loop					\n\
+	subq	44,$r12							\n\
+0:									\n\
+	movem	[$r11+],$r10						\n\
+	subq   44,$r12							\n\
+1:	bge	0b							\n\
+	movem	$r10,[$r13+]						\n\
+3:									\n\
+	addq   44,$r12  ;; compensate for last loop underflowing n	\n\
+									\n\
+	;; Restore registers from stack					\n\
+	movem [$sp+],$r10						\n\
+2:									\n\
+	.section .fixup,\"ax\"						\n\
+4:									\n\
+; When failing on any of the 1..44 bytes in a chunk, we adjust back the	\n\
+; source pointer and just drop through	to the by-16 and by-4 loops to	\n\
+; get the correct number of failing bytes.  This necessarily means a	\n\
+; few extra exceptions, but invalid user pointers shouldn't happen in	\n\
+; time-critical code anyway.						\n\
+	jump 3b								\n\
+	subq 44,$r11							\n\
+									\n\
+	.previous							\n\
+	.section __ex_table,\"a\"					\n\
+	.dword 1b,4b							\n\
+	.previous"
+
+     /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n), "=r" (retn)
+     /* Inputs */ : "0" (dst), "1" (src), "2" (n), "3" (retn));
+
+  }
+
+  while (n >= 16)
+  {
+    __asm_copy_to_user_16 (dst, src, retn);
+    n -= 16;
+  }
+
+  /* Having a separate by-four loops cuts down on cache footprint.
+     FIXME:  Test with and without; increasing switch to be 0..15.  */
+  while (n >= 4)
+  {
+    __asm_copy_to_user_4 (dst, src, retn);
+    n -= 4;
+  }
+
+  switch (n)
+  {
+    case 0:
+      break;
+    case 1:
+      __asm_copy_to_user_1 (dst, src, retn);
+      break;
+    case 2:
+      __asm_copy_to_user_2 (dst, src, retn);
+      break;
+    case 3:
+      __asm_copy_to_user_3 (dst, src, retn);
+      break;
+  }
+
+  return retn;
+}
+
+/* Copy from user to kernel, zeroing the bytes that were inaccessible in
+   userland.  The return-value is the number of bytes that were
+   inaccessible.  */
+
+unsigned long
+__copy_user_zeroing (void __user *pdst, const void *psrc, unsigned long pn)
+{
+  /* We want the parameters put in special registers.
+     Make sure the compiler is able to make something useful of this.
+     As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
+
+     FIXME: Comment for old gcc version.  Check.
+     If gcc was allright, it really would need no temporaries, and no
+     stack space to save stuff on.  */
+
+  register char *dst __asm__ ("r13") = pdst;
+  register const char *src __asm__ ("r11") = psrc;
+  register int n __asm__ ("r12") = pn;
+  register int retn __asm__ ("r10") = 0;
+
+  /* The best reason to align src is that we then know that a read-fault
+     was for aligned bytes; there's no 1..3 remaining good bytes to
+     pickle.  */
+  if (((unsigned long) src & 3) != 0)
+  {
+    if (((unsigned long) src & 1) && n != 0)
+    {
+      __asm_copy_from_user_1 (dst, src, retn);
+      n--;
+    }
+
+    if (((unsigned long) src & 2) && n >= 2)
+    {
+      __asm_copy_from_user_2 (dst, src, retn);
+      n -= 2;
+    }
+
+    /* We only need one check after the unalignment-adjustments, because
+       if both adjustments were done, either both or neither reference
+       had an exception.  */
+    if (retn != 0)
+      goto copy_exception_bytes;
+  }
+
+  /* Movem is dirt cheap.  The overheap is low enough to always use the
+     minimum possible block size as the threshold.  */
+  if (n >= 44)
+  {
+    /* It is not optimal to tell the compiler about clobbering any
+       registers; that will move the saving/restoring of those registers
+       to the function prologue/epilogue, and make non-movem sizes
+       suboptimal.  */
+    __asm__ volatile ("\
+	.ifnc %0%1%2%3,$r13$r11$r12$r10					\n\
+	.err								\n\
+	.endif								\n\
+									\n\
+	;; Save the registers we'll use in the movem process		\n\
+	;; on the stack.						\n\
+	subq	11*4,$sp						\n\
+	movem	$r10,[$sp]						\n\
+									\n\
+	;; Now we've got this:						\n\
+	;; r11 - src							\n\
+	;; r13 - dst							\n\
+	;; r12 - n							\n\
+									\n\
+	;; Update n for the first loop					\n\
+	subq	44,$r12							\n\
+0:									\n\
+	movem	[$r11+],$r10						\n\
+									\n\
+	subq   44,$r12							\n\
+	bge	0b							\n\
+	movem	$r10,[$r13+]						\n\
+									\n\
+4:									\n\
+	addq   44,$r12  ;; compensate for last loop underflowing n	\n\
+									\n\
+	;; Restore registers from stack					\n\
+	movem [$sp+],$r10						\n\
+	.section .fixup,\"ax\"						\n\
+									\n\
+;; Do not jump back into the loop if we fail.  For some uses, we get a	\n\
+;; page fault somewhere on the line.  Without checking for page limits,	\n\
+;; we don't know where, but we need to copy accurately and keep an	\n\
+;; accurate count; not just clear the whole line.  To do that, we fall	\n\
+;; down in the code below, proceeding with smaller amounts.  It should	\n\
+;; be kept in mind that we have to cater to code like what at one time	\n\
+;; was in fs/super.c:							\n\
+;;  i = size - copy_from_user((void *)page, data, size);		\n\
+;; which would cause repeated faults while clearing the remainder of	\n\
+;; the SIZE bytes at PAGE after the first fault.			\n\
+;; A caveat here is that we must not fall through from a failing page	\n\
+;; to a valid page.							\n\
+									\n\
+3:									\n\
+	jump	4b ;; Fall through, pretending the fault didn't happen.	\n\
+	nop								\n\
+									\n\
+	.previous							\n\
+	.section __ex_table,\"a\"					\n\
+	.dword 0b,3b							\n\
+	.previous"
+
+     /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n), "=r" (retn)
+     /* Inputs */ : "0" (dst), "1" (src), "2" (n), "3" (retn));
+  }
+
+  /* Either we directly start copying here, using dword copying in a loop,
+     or we copy as much as possible with 'movem' and then the last block
+     (<44 bytes) is copied here.  This will work since 'movem' will have
+     updated src, dst and n.  (Except with failing src.)
+
+     Since we want to keep src accurate, we can't use
+     __asm_copy_from_user_N with N != (1, 2, 4); it updates dst and
+     retn, but not src (by design; it's value is ignored elsewhere).  */
+
+  while (n >= 4)
+  {
+    __asm_copy_from_user_4 (dst, src, retn);
+    n -= 4;
+
+    if (retn)
+      goto copy_exception_bytes;
+  }
+
+  /* If we get here, there were no memory read faults.  */
+  switch (n)
+  {
+    /* These copies are at least "naturally aligned" (so we don't have
+       to check each byte), due to the src alignment code before the
+       movem loop.  The *_3 case *will* get the correct count for retn.  */
+    case 0:
+      /* This case deliberately left in (if you have doubts check the
+	 generated assembly code).  */
+      break;
+    case 1:
+      __asm_copy_from_user_1 (dst, src, retn);
+      break;
+    case 2:
+      __asm_copy_from_user_2 (dst, src, retn);
+      break;
+    case 3:
+      __asm_copy_from_user_3 (dst, src, retn);
+      break;
+  }
+
+  /* If we get here, retn correctly reflects the number of failing
+     bytes.  */
+  return retn;
+
+copy_exception_bytes:
+  /* We already have "retn" bytes cleared, and need to clear the
+     remaining "n" bytes.  A non-optimized simple byte-for-byte in-line
+     memset is preferred here, since this isn't speed-critical code and
+     we'd rather have this a leaf-function than calling memset.  */
+  {
+    char *endp;
+    for (endp = dst + n; dst < endp; dst++)
+      *dst = 0;
+  }
+
+  return retn + n;
+}
+
+/* Zero userspace.  */
+
+unsigned long
+__do_clear_user (void __user *pto, unsigned long pn)
+{
+  /* We want the parameters put in special registers.
+     Make sure the compiler is able to make something useful of this.
+      As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
+
+     FIXME: Comment for old gcc version.  Check.
+     If gcc was allright, it really would need no temporaries, and no
+     stack space to save stuff on. */
+
+  register char *dst __asm__ ("r13") = pto;
+  register int n __asm__ ("r12") = pn;
+  register int retn __asm__ ("r10") = 0;
+
+
+  if (((unsigned long) dst & 3) != 0
+     /* Don't align if we wouldn't copy more than a few bytes.  */
+      && n >= 3)
+  {
+    if ((unsigned long) dst & 1)
+    {
+      __asm_clear_1 (dst, retn);
+      n--;
+    }
+
+    if ((unsigned long) dst & 2)
+    {
+      __asm_clear_2 (dst, retn);
+      n -= 2;
+    }
+  }
+
+  /* Decide which copying method to use.
+     FIXME: This number is from the "ordinary" kernel memset.  */
+  if (n >= 48)
+  {
+    /* For large clears we use 'movem' */
+
+    /* It is not optimal to tell the compiler about clobbering any
+       call-saved registers; that will move the saving/restoring of
+       those registers to the function prologue/epilogue, and make
+       non-movem sizes suboptimal.
+
+       This method is not foolproof; it assumes that the "asm reg"
+       declarations at the beginning of the function really are used
+       here (beware: they may be moved to temporary registers).
+       This way, we do not have to save/move the registers around into
+       temporaries; we can safely use them straight away.
+
+      If you want to check that the allocation was right; then
+      check the equalities in the first comment.  It should say
+      something like "r13=r13, r11=r11, r12=r12". */
+    __asm__ volatile ("\
+	.ifnc %0%1%2,$r13$r12$r10					\n\
+	.err								\n\
+	.endif								\n\
+									\n\
+	;; Save the registers we'll clobber in the movem process	\n\
+	;; on the stack.  Don't mention them to gcc, it will only be	\n\
+	;; upset.							\n\
+	subq	11*4,$sp						\n\
+	movem	$r10,[$sp]						\n\
+									\n\
+	clear.d $r0							\n\
+	clear.d $r1							\n\
+	clear.d $r2							\n\
+	clear.d $r3							\n\
+	clear.d $r4							\n\
+	clear.d $r5							\n\
+	clear.d $r6							\n\
+	clear.d $r7							\n\
+	clear.d $r8							\n\
+	clear.d $r9							\n\
+	clear.d $r10							\n\
+	clear.d $r11							\n\
+									\n\
+	;; Now we've got this:						\n\
+	;; r13 - dst							\n\
+	;; r12 - n							\n\
+									\n\
+	;; Update n for the first loop					\n\
+	subq	12*4,$r12						\n\
+0:									\n\
+	subq   12*4,$r12						\n\
+1:									\n\
+	bge	0b							\n\
+	movem	$r11,[$r13+]						\n\
+									\n\
+	addq   12*4,$r12 ;; compensate for last loop underflowing n	\n\
+									\n\
+	;; Restore registers from stack					\n\
+	movem [$sp+],$r10						\n\
+2:									\n\
+	.section .fixup,\"ax\"						\n\
+3:									\n\
+	movem [$sp],$r10						\n\
+	addq 12*4,$r10							\n\
+	addq 12*4,$r13							\n\
+	movem $r10,[$sp]						\n\
+	jump 0b								\n\
+	clear.d $r10							\n\
+									\n\
+	.previous							\n\
+	.section __ex_table,\"a\"					\n\
+	.dword 1b,3b							\n\
+	.previous"
+
+     /* Outputs */ : "=r" (dst), "=r" (n), "=r" (retn)
+     /* Inputs */ : "0" (dst), "1" (n), "2" (retn)
+     /* Clobber */ : "r11");
+  }
+
+  while (n >= 16)
+  {
+    __asm_clear_16 (dst, retn);
+    n -= 16;
+  }
+
+  /* Having a separate by-four loops cuts down on cache footprint.
+     FIXME:  Test with and without; increasing switch to be 0..15.  */
+  while (n >= 4)
+  {
+    __asm_clear_4 (dst, retn);
+    n -= 4;
+  }
+
+  switch (n)
+  {
+    case 0:
+      break;
+    case 1:
+      __asm_clear_1 (dst, retn);
+      break;
+    case 2:
+      __asm_clear_2 (dst, retn);
+      break;
+    case 3:
+      __asm_clear_3 (dst, retn);
+      break;
+  }
+
+  return retn;
+}
diff --git a/arch/cris/arch-v32/mm/Makefile b/arch/cris/arch-v32/mm/Makefile
new file mode 100644
index 00000000000..9146f88484b
--- /dev/null
+++ b/arch/cris/arch-v32/mm/Makefile
@@ -0,0 +1,3 @@
+# Makefile for the Linux/cris parts of the memory manager.
+
+obj-y	 := mmu.o init.o tlb.o intmem.o
diff --git a/arch/cris/arch-v32/mm/init.c b/arch/cris/arch-v32/mm/init.c
new file mode 100644
index 00000000000..f2fba27d822
--- /dev/null
+++ b/arch/cris/arch-v32/mm/init.c
@@ -0,0 +1,174 @@
+/*
+ * Set up paging and the MMU.
+ *
+ * Copyright (C) 2000-2003, Axis Communications AB.
+ *
+ * Authors:   Bjorn Wesen <bjornw@axis.com>
+ *            Tobias Anderberg <tobiasa@axis.com>, CRISv32 port.
+ */
+#include <linux/config.h>
+#include <linux/mmzone.h>
+#include <linux/init.h>
+#include <linux/bootmem.h>
+#include <linux/mm.h>
+#include <linux/config.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/types.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <asm/mmu_context.h>
+#include <asm/arch/hwregs/asm/mmu_defs_asm.h>
+#include <asm/arch/hwregs/supp_reg.h>
+
+extern void tlb_init(void);
+
+/*
+ * The kernel is already mapped with linear mapping at kseg_c so there's no
+ * need to map it with a page table. However, head.S also temporarily mapped it
+ * at kseg_4 thus the ksegs are set up again. Also clear the TLB and do various
+ * other paging stuff.
+ */
+void __init
+cris_mmu_init(void)
+{
+	unsigned long mmu_config;
+	unsigned long mmu_kbase_hi;
+	unsigned long mmu_kbase_lo;
+	unsigned short mmu_page_id;
+
+	/*
+	 * Make sure the current pgd table points to something sane, even if it
+	 * is most probably not used until the next switch_mm.
+	 */
+	per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd;
+
+#ifdef CONFIG_SMP
+	{
+		pgd_t **pgd;
+		pgd = (pgd_t**)&per_cpu(current_pgd, smp_processor_id());
+		SUPP_BANK_SEL(1);
+		SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
+		SUPP_BANK_SEL(2);
+		SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
+	}
+#endif
+
+	/* Initialise the TLB. Function found in tlb.c. */
+	tlb_init();
+
+	/* Enable exceptions and initialize the kernel segments. */
+	mmu_config = ( REG_STATE(mmu, rw_mm_cfg, we, on)        |
+		       REG_STATE(mmu, rw_mm_cfg, acc, on)       |
+		       REG_STATE(mmu, rw_mm_cfg, ex, on)        |
+		       REG_STATE(mmu, rw_mm_cfg, inv, on)       |
+		       REG_STATE(mmu, rw_mm_cfg, seg_f, linear) |
+		       REG_STATE(mmu, rw_mm_cfg, seg_e, linear) |
+		       REG_STATE(mmu, rw_mm_cfg, seg_d, page)   |
+		       REG_STATE(mmu, rw_mm_cfg, seg_c, linear) |
+		       REG_STATE(mmu, rw_mm_cfg, seg_b, linear) |
+#ifndef CONFIG_ETRAXFS_SIM
+                       REG_STATE(mmu, rw_mm_cfg, seg_a, page)   |
+#else
+		       REG_STATE(mmu, rw_mm_cfg, seg_a, linear) |
+#endif
+		       REG_STATE(mmu, rw_mm_cfg, seg_9, page)   |
+		       REG_STATE(mmu, rw_mm_cfg, seg_8, page)   |
+		       REG_STATE(mmu, rw_mm_cfg, seg_7, page)   |
+		       REG_STATE(mmu, rw_mm_cfg, seg_6, page)   |
+		       REG_STATE(mmu, rw_mm_cfg, seg_5, page)   |
+		       REG_STATE(mmu, rw_mm_cfg, seg_4, page)   |
+		       REG_STATE(mmu, rw_mm_cfg, seg_3, page)   |
+		       REG_STATE(mmu, rw_mm_cfg, seg_2, page)   |
+		       REG_STATE(mmu, rw_mm_cfg, seg_1, page)   |
+		       REG_STATE(mmu, rw_mm_cfg, seg_0, page));
+
+	mmu_kbase_hi = ( REG_FIELD(mmu, rw_mm_kbase_hi, base_f, 0x0) |
+			 REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 0x8) |
+			 REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 0x0) |
+#ifndef CONFIG_ETRAXFS_SIM
+                         REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0x4) |
+#else
+			 REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0x0) |
+#endif
+			 REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb) |
+#ifndef CONFIG_ETRAXFS_SIM
+			 REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0x0) |
+#else
+                         REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0xa) |
+#endif
+			 REG_FIELD(mmu, rw_mm_kbase_hi, base_9, 0x0) |
+			 REG_FIELD(mmu, rw_mm_kbase_hi, base_8, 0x0));
+
+	mmu_kbase_lo = ( REG_FIELD(mmu, rw_mm_kbase_lo, base_7, 0x0) |
+			 REG_FIELD(mmu, rw_mm_kbase_lo, base_6, 0x0) |
+			 REG_FIELD(mmu, rw_mm_kbase_lo, base_5, 0x0) |
+			 REG_FIELD(mmu, rw_mm_kbase_lo, base_4, 0x0) |
+			 REG_FIELD(mmu, rw_mm_kbase_lo, base_3, 0x0) |
+			 REG_FIELD(mmu, rw_mm_kbase_lo, base_2, 0x0) |
+			 REG_FIELD(mmu, rw_mm_kbase_lo, base_1, 0x0) |
+			 REG_FIELD(mmu, rw_mm_kbase_lo, base_0, 0x0));
+
+	mmu_page_id = REG_FIELD(mmu, rw_mm_tlb_hi, pid, 0);
+
+	/* Update the instruction MMU. */
+	SUPP_BANK_SEL(BANK_IM);
+	SUPP_REG_WR(RW_MM_CFG, mmu_config);
+	SUPP_REG_WR(RW_MM_KBASE_HI, mmu_kbase_hi);
+	SUPP_REG_WR(RW_MM_KBASE_LO, mmu_kbase_lo);
+	SUPP_REG_WR(RW_MM_TLB_HI, mmu_page_id);
+
+	/* Update the data MMU. */
+	SUPP_BANK_SEL(BANK_DM);
+	SUPP_REG_WR(RW_MM_CFG, mmu_config);
+	SUPP_REG_WR(RW_MM_KBASE_HI, mmu_kbase_hi);
+	SUPP_REG_WR(RW_MM_KBASE_LO, mmu_kbase_lo);
+	SUPP_REG_WR(RW_MM_TLB_HI, mmu_page_id);
+
+	SPEC_REG_WR(SPEC_REG_PID, 0);
+
+	/*
+	 * The MMU has been enabled ever since head.S but just to make it
+	 * totally obvious enable it here as well.
+	 */
+	SUPP_BANK_SEL(BANK_GC);
+	SUPP_REG_WR(RW_GC_CFG, 0xf); /* IMMU, DMMU, ICache, DCache on */
+}
+
+void __init
+paging_init(void)
+{
+	int i;
+	unsigned long zones_size[MAX_NR_ZONES];
+
+	printk("Setting up paging and the MMU.\n");
+
+	/* Clear out the init_mm.pgd that will contain the kernel's mappings. */
+	for(i = 0; i < PTRS_PER_PGD; i++)
+		swapper_pg_dir[i] = __pgd(0);
+
+	cris_mmu_init();
+
+	/*
+	 * Initialize the bad page table and bad page to point to a couple of
+	 * allocated pages.
+	 */
+	empty_zero_page = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
+	memset((void *) empty_zero_page, 0, PAGE_SIZE);
+
+	/* All pages are DMA'able in Etrax, so put all in the DMA'able zone. */
+	zones_size[0] = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
+
+	for (i = 1; i < MAX_NR_ZONES; i++)
+		zones_size[i] = 0;
+
+	/*
+	 * Use free_area_init_node instead of free_area_init, because it is
+	 * designed for systems where the DRAM starts at an address
+	 * substantially higher than 0, like us (we start at PAGE_OFFSET). This
+	 * saves space in the mem_map page array.
+	 */
+	free_area_init_node(0, &contig_page_data, zones_size, PAGE_OFFSET >> PAGE_SHIFT, 0);
+
+	mem_map = contig_page_data.node_mem_map;
+}
diff --git a/arch/cris/arch-v32/mm/intmem.c b/arch/cris/arch-v32/mm/intmem.c
new file mode 100644
index 00000000000..41ee7f7997f
--- /dev/null
+++ b/arch/cris/arch-v32/mm/intmem.c
@@ -0,0 +1,139 @@
+/*
+ * Simple allocator for internal RAM in ETRAX FS
+ *
+ * Copyright (c) 2004 Axis Communications AB.
+ */
+
+#include <linux/list.h>
+#include <linux/slab.h>
+#include <asm/io.h>
+#include <asm/arch/memmap.h>
+
+#define STATUS_FREE 0
+#define STATUS_ALLOCATED 1
+
+struct intmem_allocation {
+	struct list_head entry;
+	unsigned int size;
+	unsigned offset;
+	char status;
+};
+
+
+static struct list_head intmem_allocations;
+static void* intmem_virtual;
+
+static void crisv32_intmem_init(void)
+{
+	static int initiated = 0;
+	if (!initiated) {
+		struct intmem_allocation* alloc =
+		  (struct intmem_allocation*)kmalloc(sizeof *alloc, GFP_KERNEL);
+		INIT_LIST_HEAD(&intmem_allocations);
+		intmem_virtual = ioremap(MEM_INTMEM_START, MEM_INTMEM_SIZE);
+		initiated = 1;
+		alloc->size = MEM_INTMEM_SIZE;
+		alloc->offset = 0;
+		alloc->status = STATUS_FREE;
+		list_add_tail(&alloc->entry, &intmem_allocations);
+	}
+}
+
+void* crisv32_intmem_alloc(unsigned size, unsigned align)
+{
+	struct intmem_allocation* allocation;
+	struct intmem_allocation* tmp;
+	void* ret = NULL;
+
+	preempt_disable();
+	crisv32_intmem_init();
+
+	list_for_each_entry_safe(allocation, tmp, &intmem_allocations, entry) {
+		int alignment = allocation->offset % align;
+		alignment = alignment ? align - alignment : alignment;
+
+		if (allocation->status == STATUS_FREE &&
+		    allocation->size >= size + alignment) {
+			if (allocation->size > size + alignment) {
+				struct intmem_allocation* alloc =
+					(struct intmem_allocation*)
+					kmalloc(sizeof *alloc, GFP_ATOMIC);
+				alloc->status = STATUS_FREE;
+				alloc->size = allocation->size - size - alignment;
+				alloc->offset = allocation->offset + size;
+				list_add(&alloc->entry, &allocation->entry);
+
+				if (alignment) {
+					struct intmem_allocation* tmp;
+					tmp = (struct intmem_allocation*)
+						kmalloc(sizeof *tmp, GFP_ATOMIC);
+					tmp->offset = allocation->offset;
+					tmp->size = alignment;
+					tmp->status = STATUS_FREE;
+					allocation->offset += alignment;
+					list_add_tail(&tmp->entry, &allocation->entry);
+				}
+			}
+			allocation->status = STATUS_ALLOCATED;
+			allocation->size = size;
+			ret = (void*)((int)intmem_virtual + allocation->offset);
+		}
+	}
+	preempt_enable();
+	return ret;
+}
+
+void crisv32_intmem_free(void* addr)
+{
+	struct intmem_allocation* allocation;
+	struct intmem_allocation* tmp;
+
+	if (addr == NULL)
+		return;
+
+	preempt_disable();
+	crisv32_intmem_init();
+
+	list_for_each_entry_safe(allocation, tmp, &intmem_allocations, entry) {
+		if (allocation->offset == (int)(addr - intmem_virtual)) {
+			struct intmem_allocation* prev =
+			  list_entry(allocation->entry.prev,
+			             struct intmem_allocation, entry);
+			struct intmem_allocation* next =
+			  list_entry(allocation->entry.next,
+				     struct intmem_allocation, entry);
+
+			allocation->status = STATUS_FREE;
+			/* Join with prev and/or next if also free */
+			if (prev->status == STATUS_FREE) {
+				prev->size += allocation->size;
+				list_del(&allocation->entry);
+				kfree(allocation);
+				allocation = prev;
+			}
+			if (next->status == STATUS_FREE) {
+				allocation->size += next->size;
+				list_del(&next->entry);
+				kfree(next);
+			}
+			preempt_enable();
+			return;
+		}
+	}
+	preempt_enable();
+}
+
+void* crisv32_intmem_phys_to_virt(unsigned long addr)
+{
+	return (void*)(addr - MEM_INTMEM_START+
+	               (unsigned long)intmem_virtual);
+}
+
+unsigned long crisv32_intmem_virt_to_phys(void* addr)
+{
+	return (unsigned long)((unsigned long )addr -
+	  (unsigned long)intmem_virtual + MEM_INTMEM_START);
+}
+
+
+
diff --git a/arch/cris/arch-v32/mm/mmu.S b/arch/cris/arch-v32/mm/mmu.S
new file mode 100644
index 00000000000..27b70e5006a
--- /dev/null
+++ b/arch/cris/arch-v32/mm/mmu.S
@@ -0,0 +1,141 @@
+/*
+ *  Copyright (C) 2003 Axis Communications AB
+ *
+ *  Authors:	Mikael Starvik (starvik@axis.com)
+ *
+ * Code for the fault low-level handling routines.
+ *
+ */
+
+#include <asm/page.h>
+#include <asm/pgtable.h>
+
+; Save all register. Must save in same order as struct pt_regs.
+.macro SAVE_ALL
+	subq	12, $sp
+	move	$erp, [$sp]
+	subq	4, $sp
+	move	$srp, [$sp]
+	subq	4, $sp
+	move	$ccs, [$sp]
+	subq	4, $sp
+	move	$spc, [$sp]
+	subq	4, $sp
+	move	$mof, [$sp]
+	subq	4, $sp
+	move	$srs, [$sp]
+	subq	4, $sp
+	move.d	$acr, [$sp]
+	subq	14*4, $sp
+	movem	$r13, [$sp]
+	subq	4, $sp
+	move.d	$r10, [$sp]
+.endm
+
+; Bus fault handler. Extracts relevant information and calls mm subsystem
+; to handle the fault.
+.macro	MMU_BUS_FAULT_HANDLER handler, mmu, we, ex
+	.globl	\handler
+\handler:
+	SAVE_ALL
+	move	\mmu, $srs	; Select MMU support register bank
+	move.d  $sp, $r11	; regs
+	moveq	1, $r12		; protection fault
+	moveq   \we, $r13	; write exception?
+	orq	\ex << 1, $r13	; execute?
+	move    $s3, $r10	; rw_mm_cause
+	and.d	~8191, $r10	; Get faulting page start address
+
+	jsr	do_page_fault
+	nop
+	ba	ret_from_intr
+	nop
+.endm
+
+; Refill handler. Three cases may occur:
+;   1. PMD and PTE exists in mm subsystem but not in TLB
+;   2. PMD exists but not PTE
+;   3. PMD doesn't exist
+; The code below handles case 1 and calls the mm subsystem for case 2 and 3.
+; Do not touch this code without very good reasons and extensive testing.
+; Note that the code is optimized to minimize stalls (makes the code harder
+; to read).
+;
+; Each page is 8 KB. Each PMD holds 8192/4 PTEs (each PTE is 4 bytes) so each
+; PMD holds 16 MB of virtual memory.
+;   Bits  0-12 : Offset within a page
+;   Bits 13-23 : PTE offset within a PMD
+;   Bits 24-31 : PMD offset within the PGD
+
+.macro MMU_REFILL_HANDLER handler, mmu
+	.globl \handler
+\handler:
+	subq	4, $sp
+; (The pipeline stalls for one cycle; $sp used as address in the next cycle.)
+	move	$srs, [$sp]
+	subq	4, $sp
+	move	\mmu, $srs	; Select MMU support register bank
+	move.d	$acr, [$sp]
+	subq	4, $sp
+	move.d	$r0, [$sp]
+#ifdef CONFIG_SMP
+	move    $s7, $acr	; PGD
+#else
+	move.d  per_cpu__current_pgd, $acr ; PGD
+#endif
+	; Look up PMD in PGD
+	move	$s3, $r0	; rw_mm_cause
+	lsrq	24, $r0	; Get PMD index into PGD (bit 24-31)
+	move.d  [$acr], $acr	; PGD for the current process
+	addi	$r0.d, $acr, $acr
+	move	$s3, $r0	; rw_mm_cause
+	move.d  [$acr], $acr	; Get PMD
+	beq	1f
+	; Look up PTE in PMD
+	lsrq	PAGE_SHIFT, $r0
+	and.w	PAGE_MASK, $acr	; Remove PMD flags
+	and.d	0x7ff, $r0	; Get PTE index into PMD (bit 13-23)
+	addi    $r0.d, $acr, $acr
+	move.d  [$acr], $acr	; Get PTE
+	beq	2f
+	move.d  [$sp+], $r0	; Pop r0 in delayslot
+	; Store in TLB
+	move	$acr, $s5
+	; Return
+	move.d	[$sp+], $acr
+	move  	[$sp], $srs
+	addq	4, $sp
+	rete
+	rfe
+1:	; PMD missing, let the mm subsystem fix it up.
+	move.d  [$sp+], $r0	; Pop r0
+2:      ; PTE missing, let the mm subsystem fix it up.
+	move.d	[$sp+], $acr
+	move  	[$sp], $srs
+	addq	4, $sp
+	SAVE_ALL
+	move    \mmu, $srs
+	move.d	$sp, $r11	; regs
+	clear.d	$r12		; Not a protection fault
+	move.w  PAGE_MASK, $acr
+	move    $s3, $r10	; rw_mm_cause
+	btstq   9, $r10		; Check if write access
+	smi     $r13
+	and.w	PAGE_MASK, $r10	; Get VPN (virtual address)
+	jsr	do_page_fault
+	and.w   $acr, $r10
+	; Return
+	ba	ret_from_intr
+	nop
+.endm
+
+	; This is the MMU bus fault handlers.
+
+MMU_REFILL_HANDLER i_mmu_refill, 1
+MMU_BUS_FAULT_HANDLER i_mmu_invalid, 1, 0, 0
+MMU_BUS_FAULT_HANDLER i_mmu_access,  1, 0, 0
+MMU_BUS_FAULT_HANDLER i_mmu_execute, 1, 0, 1
+MMU_REFILL_HANDLER d_mmu_refill,  2
+MMU_BUS_FAULT_HANDLER d_mmu_invalid, 2, 0, 0
+MMU_BUS_FAULT_HANDLER d_mmu_access,  2, 0, 0
+MMU_BUS_FAULT_HANDLER d_mmu_write,   2, 1, 0
diff --git a/arch/cris/arch-v32/mm/tlb.c b/arch/cris/arch-v32/mm/tlb.c
new file mode 100644
index 00000000000..8233406798d
--- /dev/null
+++ b/arch/cris/arch-v32/mm/tlb.c
@@ -0,0 +1,208 @@
+/*
+ * Low level TLB handling.
+ *
+ * Copyright (C) 2000-2003, Axis Communications AB.
+ *
+ * Authors:   Bjorn Wesen <bjornw@axis.com>
+ *            Tobias Anderberg <tobiasa@axis.com>, CRISv32 port.
+ */
+
+#include <asm/tlb.h>
+#include <asm/mmu_context.h>
+#include <asm/arch/hwregs/asm/mmu_defs_asm.h>
+#include <asm/arch/hwregs/supp_reg.h>
+
+#define UPDATE_TLB_SEL_IDX(val)					\
+do { 								\
+	unsigned long tlb_sel; 					\
+								\
+	tlb_sel = REG_FIELD(mmu, rw_mm_tlb_sel, idx, val);	\
+	SUPP_REG_WR(RW_MM_TLB_SEL, tlb_sel);			\
+} while(0)
+
+#define UPDATE_TLB_HILO(tlb_hi, tlb_lo)		\
+do {						\
+	SUPP_REG_WR(RW_MM_TLB_HI, tlb_hi);	\
+	SUPP_REG_WR(RW_MM_TLB_LO, tlb_lo);	\
+} while(0)
+
+/*
+ * The TLB can host up to 256 different mm contexts at the same time. The running
+ * context is found in the PID register. Each TLB entry contains a page_id that
+ * has to match the PID register to give a hit. page_id_map keeps track of which
+ * mm's is assigned to which page_id's, making sure it's known when to
+ * invalidate TLB entries.
+ *
+ * The last page_id is never running, it is used as an invalid page_id so that
+ * it's possible to make TLB entries that will nerver match.
+ *
+ * Note; the flushes needs to be atomic otherwise an interrupt hander that uses
+ * vmalloc'ed memory might cause a TLB load in the middle of a flush.
+ */
+
+/* Flush all TLB entries. */
+void
+__flush_tlb_all(void)
+{
+	int i;
+	int mmu;
+	unsigned long flags;
+	unsigned long mmu_tlb_hi;
+	unsigned long mmu_tlb_sel;
+
+	/*
+	 * Mask with 0xf so similar TLB entries aren't written in the same 4-way
+	 * entry group.
+	 */
+	local_save_flags(flags);
+	local_irq_disable();
+
+	for (mmu = 1; mmu <= 2; mmu++) {
+		SUPP_BANK_SEL(mmu); /* Select the MMU */
+		for (i = 0; i < NUM_TLB_ENTRIES; i++) {
+			/* Store invalid entry */
+			mmu_tlb_sel = REG_FIELD(mmu, rw_mm_tlb_sel, idx, i);
+
+			mmu_tlb_hi = (REG_FIELD(mmu, rw_mm_tlb_hi, pid, INVALID_PAGEID)
+				    | REG_FIELD(mmu, rw_mm_tlb_hi, vpn, i & 0xf));
+
+			SUPP_REG_WR(RW_MM_TLB_SEL, mmu_tlb_sel);
+			SUPP_REG_WR(RW_MM_TLB_HI, mmu_tlb_hi);
+			SUPP_REG_WR(RW_MM_TLB_LO, 0);
+		}
+	}
+
+	local_irq_restore(flags);
+}
+
+/* Flush an entire user address space. */
+void
+__flush_tlb_mm(struct mm_struct *mm)
+{
+	int i;
+	int mmu;
+	unsigned long flags;
+	unsigned long page_id;
+	unsigned long tlb_hi;
+	unsigned long mmu_tlb_hi;
+
+	page_id = mm->context.page_id;
+
+	if (page_id == NO_CONTEXT)
+		return;
+
+	/* Mark the TLB entries that match the page_id as invalid. */
+	local_save_flags(flags);
+	local_irq_disable();
+
+	for (mmu = 1; mmu <= 2; mmu++) {
+		SUPP_BANK_SEL(mmu);
+		for (i = 0; i < NUM_TLB_ENTRIES; i++) {
+			UPDATE_TLB_SEL_IDX(i);
+
+			/* Get the page_id */
+			SUPP_REG_RD(RW_MM_TLB_HI, tlb_hi);
+
+			/* Check if the page_id match. */
+			if ((tlb_hi & 0xff) == page_id) {
+				mmu_tlb_hi = (REG_FIELD(mmu, rw_mm_tlb_hi, pid,
+				                        INVALID_PAGEID)
+				            | REG_FIELD(mmu, rw_mm_tlb_hi, vpn,
+				                        i & 0xf));
+
+				UPDATE_TLB_HILO(mmu_tlb_hi, 0);
+			}
+		}
+	}
+
+	local_irq_restore(flags);
+}
+
+/* Invalidate a single page. */
+void
+__flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
+{
+	int i;
+	int mmu;
+	unsigned long page_id;
+	unsigned long flags;
+	unsigned long tlb_hi;
+	unsigned long mmu_tlb_hi;
+
+	page_id = vma->vm_mm->context.page_id;
+
+	if (page_id == NO_CONTEXT)
+		return;
+
+	addr &= PAGE_MASK;
+
+	/*
+	 * Invalidate those TLB entries that match both the mm context and the
+	 * requested virtual address.
+	 */
+	local_save_flags(flags);
+	local_irq_disable();
+
+	for (mmu = 1; mmu <= 2; mmu++) {
+		SUPP_BANK_SEL(mmu);
+		for (i = 0; i < NUM_TLB_ENTRIES; i++) {
+			UPDATE_TLB_SEL_IDX(i);
+			SUPP_REG_RD(RW_MM_TLB_HI, tlb_hi);
+
+			/* Check if page_id and address matches */
+			if (((tlb_hi & 0xff) == page_id) &&
+			    ((tlb_hi & PAGE_MASK) == addr)) {
+				mmu_tlb_hi = REG_FIELD(mmu, rw_mm_tlb_hi, pid,
+				                       INVALID_PAGEID) | addr;
+
+				UPDATE_TLB_HILO(mmu_tlb_hi, 0);
+			}
+		}
+	}
+
+	local_irq_restore(flags);
+}
+
+/*
+ * Initialize the context related info for a new mm_struct
+ * instance.
+ */
+
+int
+init_new_context(struct task_struct *tsk, struct mm_struct *mm)
+{
+	mm->context.page_id = NO_CONTEXT;
+	return 0;
+}
+
+/* Called in schedule() just before actually doing the switch_to. */
+void
+switch_mm(struct mm_struct *prev, struct mm_struct *next,
+	  struct task_struct *tsk)
+{
+	int cpu = smp_processor_id();
+
+	/* Make sure there is a MMU context. */
+	spin_lock(&next->page_table_lock);
+	get_mmu_context(next);
+	cpu_set(cpu, next->cpu_vm_mask);
+	spin_unlock(&next->page_table_lock);
+
+	/*
+	 * Remember the pgd for the fault handlers. Keep a seperate copy of it
+	 * because current and active_mm might be invalid at points where
+	 * there's still a need to derefer the pgd.
+	 */
+	per_cpu(current_pgd, cpu) = next->pgd;
+
+	/* Switch context in the MMU. */
+        if (tsk && tsk->thread_info)
+        {
+          SPEC_REG_WR(SPEC_REG_PID, next->context.page_id | tsk->thread_info->tls);
+        }
+        else
+        {
+          SPEC_REG_WR(SPEC_REG_PID, next->context.page_id);
+        }
+}
+
diff --git a/arch/cris/arch-v32/output_arch.ld b/arch/cris/arch-v32/output_arch.ld
new file mode 100644
index 00000000000..d60a57db0ec
--- /dev/null
+++ b/arch/cris/arch-v32/output_arch.ld
@@ -0,0 +1,2 @@
+/* At the time of this writing, there's no equivalent ld option. */
+OUTPUT_ARCH (crisv32)
diff --git a/arch/cris/arch-v32/vmlinux.lds.S b/arch/cris/arch-v32/vmlinux.lds.S
new file mode 100644
index 00000000000..adb94605d92
--- /dev/null
+++ b/arch/cris/arch-v32/vmlinux.lds.S
@@ -0,0 +1,134 @@
+/* ld script to make the Linux/CRIS kernel
+ * Authors: Bjorn Wesen (bjornw@axis.com)
+ *
+ * It is VERY DANGEROUS to fiddle around with the symbols in this
+ * script. It is for example quite vital that all generated sections
+ * that are used are actually named here, otherwise the linker will
+ * put them at the end, where the init stuff is which is FREED after
+ * the kernel has booted.
+ */
+
+#include <linux/config.h>
+#include <asm-generic/vmlinux.lds.h>
+
+jiffies = jiffies_64;
+SECTIONS
+{
+	. = DRAM_VIRTUAL_BASE;
+	dram_start = .;
+	ebp_start = .;
+
+	/* The boot section is only necessary until the VCS top level testbench */
+	/* includes both flash and DRAM. */
+	.boot : { *(.boot) }
+
+	. = DRAM_VIRTUAL_BASE + 0x4000;		/* See head.S and pages reserved at the start. */
+
+	_text = .;		/* Text and read-only data. */
+	text_start = .;		/* Lots of aliases. */
+	_stext = .;
+	__stext = .;
+	.text : {
+		*(.text)
+		SCHED_TEXT
+		LOCK_TEXT
+		*(.fixup)
+		*(.text.__*)
+	}
+
+	_etext = . ;		/* End of text section. */
+	__etext = .;
+
+	. = ALIGN(4);		/* Exception table. */
+  	__start___ex_table = .;
+  	__ex_table : { *(__ex_table) }
+  	__stop___ex_table = .;
+
+	RODATA
+
+	. = ALIGN (4);
+	___data_start = . ;
+	__Sdata = . ;
+	.data : {                     /* Data */
+		*(.data)
+	}
+	__edata = . ;		/* End of data section. */
+	_edata = . ;
+
+	. = ALIGN(8192);	/* init_task and stack, must be aligned. */
+  	.data.init_task : { *(.data.init_task) }
+
+  	. = ALIGN(8192);	/* Init code and data. */
+  	__init_begin = .;
+	.init.text : {
+		   _sinittext = .;
+		   *(.init.text)
+		   _einittext = .;
+	}
+  	.init.data : { *(.init.data) }
+  	. = ALIGN(16);
+  	__setup_start = .;
+  	.init.setup : { *(.init.setup) }
+  	__setup_end = .;
+	__start___param = .;
+	__param : { *(__param) }
+	__stop___param = .;
+  	.initcall.init : {
+		__initcall_start = .;
+		*(.initcall1.init);
+		*(.initcall2.init);
+		*(.initcall3.init);
+		*(.initcall4.init);
+		*(.initcall5.init);
+		*(.initcall6.init);
+		*(.initcall7.init);
+		__initcall_end = .;
+	}
+
+	.con_initcall.init : {
+		__con_initcall_start = .;
+		*(.con_initcall.init)
+		__con_initcall_end = .;
+	}
+	SECURITY_INIT
+
+	__per_cpu_start = .;
+	.data.percpu  : { *(.data.percpu) }
+	__per_cpu_end = .;
+
+	.init.ramfs : {
+		__initramfs_start = .;
+		*(.init.ramfs)
+		__initramfs_end = .;
+		/*
+		 * We fill to the next page, so we can discard all init
+		 * pages without needing to consider what payload might be
+		 * appended to the kernel image.
+		 */
+		FILL (0);
+		. = ALIGN (8192);
+	}
+
+	__vmlinux_end = .;	/* Last address of the physical file. */
+  	__init_end = .;
+
+	__data_end = . ;	/* Move to _edata? */
+	__bss_start = .;	/* BSS. */
+	.bss : {
+		*(COMMON)
+		*(.bss)
+	}
+
+	. =  ALIGN (0x20);
+	_end = .;
+	__end = .;
+
+	/* Sections to be discarded */
+  	/DISCARD/ : {
+        	*(.text.exit)
+        	*(.data.exit)
+		*(.exitcall.exit)
+        }
+
+	dram_end = dram_start + CONFIG_ETRAX_DRAM_SIZE*1024*1024;
+}
diff --git a/arch/cris/defconfig b/arch/cris/defconfig
index 32c9c987dba..142a10818af 100644
--- a/arch/cris/defconfig
+++ b/arch/cris/defconfig
@@ -1,22 +1,27 @@
 #
 # Automatically generated make config: don't edit
+# Linux kernel version: 2.6.11
+# Mon Jun 20 13:42:02 2005
 #
 CONFIG_MMU=y
 CONFIG_UID16=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_CRIS=y
 
 #
 # Code maturity level options
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_CLEAN_COMPILE=y
-CONFIG_STANDALONE=y
 CONFIG_BROKEN_ON_SMP=y
 
 #
 # General setup
 #
-CONFIG_SWAP=y
+CONFIG_LOCALVERSION=""
+# CONFIG_SWAP is not set
 # CONFIG_SYSVIPC is not set
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
@@ -24,16 +29,19 @@ CONFIG_SYSCTL=y
 # CONFIG_AUDIT is not set
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_HOTPLUG is not set
+CONFIG_KOBJECT_UEVENT=y
 # CONFIG_IKCONFIG is not set
 CONFIG_EMBEDDED=y
 # CONFIG_KALLSYMS is not set
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_TINY_SHMEM is not set
 
 #
 # Loadable module support
@@ -45,23 +53,28 @@ CONFIG_IOSCHED_CFQ=y
 #
 CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_MISC is not set
+CONFIG_GENERIC_HARDIRQS=y
+# CONFIG_SMP is not set
 CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc"
-CONFIG_ETRAX_WATCHDOG=y
-CONFIG_ETRAX_WATCHDOG_NICE_DOGGY=y
+# CONFIG_ETRAX_WATCHDOG is not set
 CONFIG_ETRAX_FAST_TIMER=y
 # CONFIG_PREEMPT is not set
+# CONFIG_OOM_REBOOT is not set
 
 #
 # Hardware setup
 #
-CONFIG_ETRAX100LX=y
-# CONFIG_ETRAX100LX_V2 is not set
+# CONFIG_ETRAX100LX is not set
+CONFIG_ETRAX100LX_V2=y
 # CONFIG_SVINTO_SIM is not set
+# CONFIG_ETRAXFS is not set
+# CONFIG_ETRAXFS_SIM is not set
 CONFIG_ETRAX_ARCH_V10=y
-CONFIG_ETRAX_DRAM_SIZE=16
+# CONFIG_ETRAX_ARCH_V32 is not set
+CONFIG_ETRAX_DRAM_SIZE=32
 CONFIG_ETRAX_FLASH_BUSWIDTH=2
-CONFIG_CRIS_LOW_MAP=y
-CONFIG_ETRAX_DRAM_VIRTUAL_BASE=60000000
+CONFIG_ETRAX_FLASH1_SIZE=4
+CONFIG_ETRAX_DRAM_VIRTUAL_BASE=c0000000
 CONFIG_ETRAX_PA_LEDS=y
 # CONFIG_ETRAX_PB_LEDS is not set
 # CONFIG_ETRAX_CSP0_LEDS is not set
@@ -81,13 +94,13 @@ CONFIG_ETRAX_RESCUE_SER0=y
 # CONFIG_ETRAX_RESCUE_SER1 is not set
 # CONFIG_ETRAX_RESCUE_SER2 is not set
 # CONFIG_ETRAX_RESCUE_SER3 is not set
-CONFIG_ETRAX_DEF_R_WAITSTATES=0x95f8
-CONFIG_ETRAX_DEF_R_BUS_CONFIG=0x104
+CONFIG_ETRAX_DEF_R_WAITSTATES=0x95a6
+CONFIG_ETRAX_DEF_R_BUS_CONFIG=0x4
 CONFIG_ETRAX_SDRAM=y
-CONFIG_ETRAX_DEF_R_SDRAM_CONFIG=0x00e03636
+CONFIG_ETRAX_DEF_R_SDRAM_CONFIG=0x09e05757
 CONFIG_ETRAX_DEF_R_SDRAM_TIMING=0x80008002
 CONFIG_ETRAX_DEF_R_PORT_PA_DIR=0x1d
-CONFIG_ETRAX_DEF_R_PORT_PA_DATA=0xf0
+CONFIG_ETRAX_DEF_R_PORT_PA_DATA=0x00
 CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG=0x00
 CONFIG_ETRAX_DEF_R_PORT_PB_DIR=0x1e
 CONFIG_ETRAX_DEF_R_PORT_PB_DATA=0xf3
@@ -97,16 +110,17 @@ CONFIG_ETRAX_DEF_R_PORT_PB_DATA=0xf3
 # Drivers for built-in interfaces
 #
 CONFIG_ETRAX_ETHERNET=y
-CONFIG_NET_ETHERNET=y
 # CONFIG_ETRAX_NETWORK_LED_ON_WHEN_LINK is not set
 CONFIG_ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY=y
 CONFIG_ETRAX_SERIAL=y
-CONFIG_ETRAX_SERIAL_FAST_TIMER=y
+# CONFIG_ETRAX_SERIAL_FAST_TIMER is not set
+# CONFIG_ETRAX_SERIAL_FLUSH_DMA_FAST is not set
+CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS=5
 CONFIG_ETRAX_SERIAL_PORT0=y
-# CONFIG_CONFIG_ETRAX_SERIAL_PORT0_NO_DMA_OUT is not set
-CONFIG_CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT=y
-# CONFIG_CONFIG_ETRAX_SERIAL_PORT0_NO_DMA_IN is not set
-CONFIG_CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN=y
+# CONFIG_ETRAX_SERIAL_PORT0_NO_DMA_OUT is not set
+CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT=y
+# CONFIG_ETRAX_SERIAL_PORT0_NO_DMA_IN is not set
+CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN=y
 CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_NONE=y
 # CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PA is not set
 # CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PB is not set
@@ -121,10 +135,10 @@ CONFIG_ETRAX_SER0_DSR_ON_PB_BIT=-1
 CONFIG_ETRAX_SER0_CD_ON_PB_BIT=-1
 # CONFIG_ETRAX_SERIAL_PORT1 is not set
 CONFIG_ETRAX_SERIAL_PORT2=y
-# CONFIG_CONFIG_ETRAX_SERIAL_PORT2_NO_DMA_OUT is not set
-CONFIG_CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT=y
-# CONFIG_CONFIG_ETRAX_SERIAL_PORT2_NO_DMA_IN is not set
-CONFIG_CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN=y
+# CONFIG_ETRAX_SERIAL_PORT2_NO_DMA_OUT is not set
+CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT=y
+# CONFIG_ETRAX_SERIAL_PORT2_NO_DMA_IN is not set
+CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN=y
 CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_NONE=y
 # CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PA is not set
 # CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PB is not set
@@ -138,44 +152,51 @@ CONFIG_ETRAX_SER2_RI_ON_PB_BIT=-1
 CONFIG_ETRAX_SER2_DSR_ON_PB_BIT=-1
 CONFIG_ETRAX_SER2_CD_ON_PB_BIT=-1
 # CONFIG_ETRAX_SERIAL_PORT3 is not set
-# CONFIG_ETRAX_RS485 is not set
-# CONFIG_ETRAX_IDE is not set
-# CONFIG_IDE is not set
-# CONFIG_ETRAX_USB_HOST is not set
+CONFIG_ETRAX_RS485=y
+# CONFIG_ETRAX_RS485_ON_PA is not set
+# CONFIG_ETRAX_RS485_DISABLE_RECEIVER is not set
+CONFIG_ETRAX_IDE=y
+CONFIG_ETRAX_IDE_DELAY=15
+CONFIG_ETRAX_IDE_PB7_RESET=y
+# CONFIG_ETRAX_IDE_G27_RESET is not set
+CONFIG_ETRAX_USB_HOST=y
+CONFIG_ETRAX_USB_HOST_PORT1=y
+CONFIG_ETRAX_USB_HOST_PORT2=y
 CONFIG_ETRAX_AXISFLASHMAP=y
 CONFIG_ETRAX_PTABLE_SECTOR=65536
-CONFIG_MTD=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_OBSOLETE_CHIPS=y
-CONFIG_MTD_AMDSTD=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CONCAT=y
 # CONFIG_ETRAX_I2C is not set
-CONFIG_ETRAX_GPIO=y
-CONFIG_ETRAX_PA_BUTTON_BITMASK=0x02
-CONFIG_ETRAX_PA_CHANGEABLE_DIR=0x00
-CONFIG_ETRAX_PA_CHANGEABLE_BITS=0xFF
-CONFIG_ETRAX_PB_CHANGEABLE_DIR=0x00
-CONFIG_ETRAX_PB_CHANGEABLE_BITS=0xFF
-# CONFIG_ETRAX_RTC is not set
+# CONFIG_ETRAX_GPIO is not set
+CONFIG_ETRAX_RTC=y
+CONFIG_ETRAX_DS1302=y
+# CONFIG_ETRAX_PCF8563 is not set
+CONFIG_ETRAX_DS1302_RST_ON_GENERIC_PORT=y
+CONFIG_ETRAX_DS1302_RSTBIT=0
+CONFIG_ETRAX_DS1302_SCLBIT=1
+CONFIG_ETRAX_DS1302_SDABIT=0
+CONFIG_ETRAX_DS1302_TRICKLE_CHARGE=0
 
 #
 # Generic Driver Options
 #
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
 
 #
 # Memory Technology Devices (MTD)
 #
+CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CONCAT=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
 
 #
 # User Modules And Translation Layers
 #
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
@@ -183,14 +204,30 @@ CONFIG_ETRAX_PB_CHANGEABLE_BITS=0xFF
 #
 # RAM/ROM/Flash chip drivers
 #
+CONFIG_MTD_CFI=y
 # CONFIG_MTD_JEDECPROBE is not set
 CONFIG_MTD_GEN_PROBE=y
 # CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
 # CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_AMDSTD_RETRY=0
 # CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
 CONFIG_MTD_RAM=y
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
+CONFIG_MTD_OBSOLETE_CHIPS=y
+CONFIG_MTD_AMDSTD=y
 # CONFIG_MTD_SHARP is not set
 # CONFIG_MTD_JEDEC is not set
 
@@ -204,11 +241,13 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
 # Self-contained MTD device drivers
 #
 # CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
 CONFIG_MTD_MTDRAM=y
 CONFIG_MTDRAM_TOTAL_SIZE=0
 CONFIG_MTDRAM_ERASE_SIZE=64
 CONFIG_MTDRAM_ABS_POS=0x0
 # CONFIG_MTD_BLKMTD is not set
+# CONFIG_MTD_BLOCK2MTD is not set
 
 #
 # Disk-On-Chip Device Drivers
@@ -235,11 +274,25 @@ CONFIG_MTDRAM_ABS_POS=0x0
 # Block devices
 #
 # CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
 CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
 # CONFIG_BLK_DEV_INITRD is not set
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CDROM_PKTCDVD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_ATA_OVER_ETH is not set
 
 #
 # Multi-device support (RAID and LVM)
@@ -249,6 +302,28 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
 #
 # ATA/ATAPI/MFM/RLL support
 #
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_BLK_DEV_IDECD=y
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_IDE_ARM is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_BLK_DEV_HD is not set
 
 #
 # SCSI device support
@@ -258,7 +333,6 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
 #
 # IEEE 1394 (FireWire) support
 #
-# CONFIG_IEEE1394 is not set
 
 #
 # I2O device support
@@ -288,6 +362,9 @@ CONFIG_INET=y
 # CONFIG_INET_AH is not set
 # CONFIG_INET_ESP is not set
 # CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_IP_TCPDIAG=y
+# CONFIG_IP_TCPDIAG_IPV6 is not set
 
 #
 # IP: Virtual Server Configuration
@@ -301,11 +378,10 @@ CONFIG_NETFILTER=y
 # IP: Netfilter Configuration
 #
 # CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_CONNTRACK_MARK is not set
 # CONFIG_IP_NF_QUEUE is not set
 # CONFIG_IP_NF_IPTABLES is not set
 # CONFIG_IP_NF_ARPTABLES is not set
-# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
-# CONFIG_IP_NF_COMPAT_IPFWADM is not set
 
 #
 # SCTP Configuration (EXPERIMENTAL)
@@ -323,12 +399,12 @@ CONFIG_NETFILTER=y
 # CONFIG_NET_DIVERT is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_HW_FLOWCONTROL is not set
 
 #
 # QoS and/or fair queueing
 #
 # CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
 
 #
 # Network testing
@@ -338,7 +414,26 @@ CONFIG_NETFILTER=y
 # CONFIG_NET_POLL_CONTROLLER is not set
 # CONFIG_HAMRADIO is not set
 # CONFIG_IRDA is not set
-# CONFIG_BT is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+# CONFIG_BT_SCO is not set
+CONFIG_BT_RFCOMM=y
+# CONFIG_BT_RFCOMM_TTY is not set
+CONFIG_BT_BNEP=y
+# CONFIG_BT_BNEP_MC_FILTER is not set
+# CONFIG_BT_BNEP_PROTO_FILTER is not set
+# CONFIG_BT_HIDP is not set
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIUSB=y
+# CONFIG_BT_HCIUSB_SCO is not set
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
@@ -348,6 +443,7 @@ CONFIG_NETDEVICES=y
 #
 # Ethernet (10 or 100Mbit)
 #
+CONFIG_NET_ETHERNET=y
 # CONFIG_MII is not set
 
 #
@@ -389,11 +485,19 @@ CONFIG_NETDEVICES=y
 #
 # Input device support
 #
-# CONFIG_INPUT is not set
+CONFIG_INPUT=y
 
 #
 # Userland interfaces
 #
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
 
 #
 # Input I/O drivers
@@ -404,10 +508,25 @@ CONFIG_SERIO=y
 # CONFIG_SERIO_I8042 is not set
 # CONFIG_SERIO_SERPORT is not set
 # CONFIG_SERIO_CT82C710 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
 
 #
 # Input Device Drivers
 #
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
 
 #
 # Character devices
@@ -426,7 +545,6 @@ CONFIG_SERIO=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-# CONFIG_QIC02_TAPE is not set
 
 #
 # IPMI
@@ -441,13 +559,10 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_GEN_RTC is not set
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
 
 #
 # Ftape, the floppy tape device driver
 #
-# CONFIG_FTAPE is not set
-# CONFIG_AGP is not set
 # CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
 
@@ -469,10 +584,15 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_JBD is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
+
+#
+# XFS support
+#
 # CONFIG_XFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set
 # CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 
@@ -485,7 +605,8 @@ CONFIG_LEGACY_PTY_COUNT=256
 #
 # DOS/FAT/NT Filesystems
 #
-# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
 # CONFIG_NTFS_FS is not set
 
 #
@@ -497,6 +618,7 @@ CONFIG_SYSFS=y
 # CONFIG_DEVFS_FS is not set
 # CONFIG_DEVPTS_FS_XATTR is not set
 CONFIG_TMPFS=y
+# CONFIG_TMPFS_XATTR is not set
 # CONFIG_HUGETLB_PAGE is not set
 CONFIG_RAMFS=y
 
@@ -512,7 +634,15 @@ CONFIG_RAMFS=y
 # CONFIG_EFS_FS is not set
 CONFIG_JFFS_FS=y
 CONFIG_JFFS_FS_VERBOSE=0
-# CONFIG_JFFS2_FS is not set
+# CONFIG_JFFS_PROC_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_NAND is not set
+# CONFIG_JFFS2_FS_NOR_ECC is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
 CONFIG_CRAMFS=y
 # CONFIG_VXFS_FS is not set
 # CONFIG_HPFS_FS is not set
@@ -530,14 +660,13 @@ CONFIG_NFS_V3=y
 # CONFIG_NFSD is not set
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
-# CONFIG_EXPORTFS is not set
 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
-# CONFIG_INTERMEZZO_FS is not set
 # CONFIG_AFS_FS is not set
 
 #
@@ -557,8 +686,120 @@ CONFIG_MSDOS_PARTITION=y
 # CONFIG_SOUND is not set
 
 #
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PC-card bridges
+#
+
+#
 # USB support
 #
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_ARCH_HAS_HCD is not set
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_SL811_HCD is not set
+
+#
+# USB Device Class drivers
+#
+
+#
+# USB Bluetooth TTY can only be used with disabled Bluetooth subsystem
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
+#
+# CONFIG_USB_STORAGE is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+# CONFIG_USB_AIPTEK is not set
+# CONFIG_USB_WACOM is not set
+# CONFIG_USB_KBTAB is not set
+# CONFIG_USB_POWERMATE is not set
+# CONFIG_USB_MTOUCH is not set
+# CONFIG_USB_EGALAX is not set
+# CONFIG_USB_XPAD is not set
+# CONFIG_USB_ATI_REMOTE is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+
+#
+# USB Multimedia devices
+#
+# CONFIG_USB_DABUSB is not set
+
+#
+# Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+CONFIG_USB_RTL8150=y
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGETKIT is not set
+# CONFIG_USB_PHIDGETSERVO is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB ATM/DSL drivers
+#
 
 #
 # USB Gadget Support
@@ -568,14 +809,17 @@ CONFIG_MSDOS_PARTITION=y
 #
 # Kernel hacking
 #
-# CONFIG_PROFILE is not set
+# CONFIG_PROFILING is not set
+# CONFIG_SYSTEM_PROFILER is not set
 # CONFIG_ETRAX_KGDB is not set
 # CONFIG_DEBUG_INFO is not set
 # CONFIG_FRAME_POINTER is not set
+# CONFIG_DEBUG_NMI_OOPS is not set
 
 #
 # Security options
 #
+# CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
 
 #
@@ -584,8 +828,14 @@ CONFIG_MSDOS_PARTITION=y
 # CONFIG_CRYPTO is not set
 
 #
+# Hardware crypto devices
+#
+
+#
 # Library routines
 #
-# CONFIG_CRC32 is not set
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/cris/kernel/Makefile b/arch/cris/kernel/Makefile
index 1546a0e7404..c8e8ea57098 100644
--- a/arch/cris/kernel/Makefile
+++ b/arch/cris/kernel/Makefile
@@ -1,4 +1,4 @@
-# $Id: Makefile,v 1.10 2004/05/14 10:18:12 starvik Exp $
+# $Id: Makefile,v 1.12 2004/10/19 13:07:43 starvik Exp $
 #
 # Makefile for the linux kernel.
 #
@@ -10,6 +10,7 @@ obj-y   := process.o traps.o irq.o ptrace.o setup.o \
 
 obj-$(CONFIG_MODULES)    += crisksyms.o
 obj-$(CONFIG_MODULES)	 += module.o
+obj-$(CONFIG_SYSTEM_PROFILER)   += profile.o
 
 clean:
 
diff --git a/arch/cris/kernel/crisksyms.c b/arch/cris/kernel/crisksyms.c
index 7141bbecd7e..85833d704eb 100644
--- a/arch/cris/kernel/crisksyms.c
+++ b/arch/cris/kernel/crisksyms.c
@@ -27,13 +27,13 @@ extern void __Udiv(void);
 extern void __Umod(void);
 extern void __Div(void);
 extern void __Mod(void);
+extern void __ashldi3(void);
 extern void __ashrdi3(void);
-extern void iounmap(void *addr);
+extern void __lshrdi3(void);
+extern void iounmap(volatile void * __iomem);
 
 /* Platform dependent support */
 EXPORT_SYMBOL(dump_thread);
-EXPORT_SYMBOL(enable_irq);
-EXPORT_SYMBOL(disable_irq);
 EXPORT_SYMBOL(kernel_thread);
 EXPORT_SYMBOL(get_cmos_time);
 EXPORT_SYMBOL(loops_per_usec);
@@ -57,7 +57,9 @@ EXPORT_SYMBOL(__Udiv);
 EXPORT_SYMBOL(__Umod);
 EXPORT_SYMBOL(__Div);
 EXPORT_SYMBOL(__Mod);
+EXPORT_SYMBOL(__ashldi3);
 EXPORT_SYMBOL(__ashrdi3);
+EXPORT_SYMBOL(__lshrdi3);
 
 /* Memory functions */
 EXPORT_SYMBOL(__ioremap);
@@ -69,23 +71,10 @@ EXPORT_SYMBOL(__down);
 EXPORT_SYMBOL(__down_interruptible);
 EXPORT_SYMBOL(__down_trylock);
 
-/* Export shadow registers for the CPU I/O pins */
-EXPORT_SYMBOL(genconfig_shadow);
-EXPORT_SYMBOL(port_pa_data_shadow);
-EXPORT_SYMBOL(port_pa_dir_shadow);
-EXPORT_SYMBOL(port_pb_data_shadow);
-EXPORT_SYMBOL(port_pb_dir_shadow);
-EXPORT_SYMBOL(port_pb_config_shadow);
-EXPORT_SYMBOL(port_g_data_shadow);
-
 /* Userspace access functions */
 EXPORT_SYMBOL(__copy_user_zeroing);
 EXPORT_SYMBOL(__copy_user);
 
-/* Cache flush functions */
-EXPORT_SYMBOL(flush_etrax_cache);
-EXPORT_SYMBOL(prepare_rx_descriptor);
-
 #undef memcpy
 #undef memset
 extern void * memset(void *, int, __kernel_size_t);
diff --git a/arch/cris/kernel/irq.c b/arch/cris/kernel/irq.c
index d848b940745..30deaf1b728 100644
--- a/arch/cris/kernel/irq.c
+++ b/arch/cris/kernel/irq.c
@@ -12,8 +12,6 @@
  * shouldn't result in any weird surprises, and installing new handlers
  * should be easier.
  *
- * Notice Linux/CRIS: these routines do not care about SMP
- *
  */
 
 /*
@@ -24,6 +22,7 @@
 #include <linux/config.h>
 #include <linux/module.h>
 #include <linux/ptrace.h>
+#include <linux/irq.h>
 
 #include <linux/kernel_stat.h>
 #include <linux/signal.h>
@@ -36,84 +35,56 @@
 #include <linux/init.h>
 #include <linux/seq_file.h>
 #include <linux/errno.h>
-#include <linux/bitops.h>
+#include <linux/spinlock.h>
 
 #include <asm/io.h>
 
-/* Defined in arch specific irq.c */
-extern void arch_setup_irq(int irq);
-extern void arch_free_irq(int irq);
-
-void
-disable_irq(unsigned int irq_nr)
-{
-	unsigned long flags;
-	
-	local_save_flags(flags);
-	local_irq_disable();
-	mask_irq(irq_nr);
-	local_irq_restore(flags);
-}
-
-void
-enable_irq(unsigned int irq_nr)
+void ack_bad_irq(unsigned int irq)
 {
-	unsigned long flags;
-	local_save_flags(flags);
-	local_irq_disable();
-	unmask_irq(irq_nr);
-	local_irq_restore(flags);
+	printk("unexpected IRQ trap at vector %02x\n", irq);
 }
 
-unsigned long
-probe_irq_on()
-{
-	return 0;
-}
-
-EXPORT_SYMBOL(probe_irq_on);
-
-int
-probe_irq_off(unsigned long x)
-{
-	return 0;
-}
-
-EXPORT_SYMBOL(probe_irq_off);
-
-/*
- * Initial irq handlers.
- */
-
-static struct irqaction *irq_action[NR_IRQS];
-
 int show_interrupts(struct seq_file *p, void *v)
 {
-	int i = *(loff_t *) v;
+	int i = *(loff_t *) v, j;
 	struct irqaction * action;
 	unsigned long flags;
 
+	if (i == 0) {
+		seq_printf(p, "           ");
+		for (j=0; j<NR_CPUS; j++)
+			if (cpu_online(j))
+				seq_printf(p, "CPU%d       ",j);
+		seq_putc(p, '\n');
+	}
+
 	if (i < NR_IRQS) {
-		local_irq_save(flags);
-		action = irq_action[i];
-		if (!action) 
+		spin_lock_irqsave(&irq_desc[i].lock, flags);
+		action = irq_desc[i].action;
+		if (!action)
 			goto skip;
-		seq_printf(p, "%2d: %10u %c %s",
-			i, kstat_this_cpu.irqs[i],
-			(action->flags & SA_INTERRUPT) ? '+' : ' ',
-			action->name);
-		for (action = action->next; action; action = action->next) {
-			seq_printf(p, ",%s %s",
-				(action->flags & SA_INTERRUPT) ? " +" : "",
-				action->name);
-		}
+		seq_printf(p, "%3d: ",i);
+#ifndef CONFIG_SMP
+		seq_printf(p, "%10u ", kstat_irqs(i));
+#else
+		for (j = 0; j < NR_CPUS; j++)
+			if (cpu_online(j))
+				seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
+#endif
+		seq_printf(p, " %14s", irq_desc[i].handler->typename);
+		seq_printf(p, "  %s", action->name);
+
+		for (action=action->next; action; action = action->next)
+			seq_printf(p, ", %s", action->name);
+
 		seq_putc(p, '\n');
 skip:
-		local_irq_restore(flags);
+		spin_unlock_irqrestore(&irq_desc[i].lock, flags);
 	}
 	return 0;
 }
 
+
 /* called by the assembler IRQ entry functions defined in irq.h
  * to dispatch the interrupts to registred handlers
  * interrupts are disabled upon entry - depending on if the
@@ -123,164 +94,17 @@ skip:
 
 asmlinkage void do_IRQ(int irq, struct pt_regs * regs)
 {
-	struct irqaction *action;
-	int do_random, cpu;
-        int ret, retval = 0;
-
-        cpu = smp_processor_id();
-        irq_enter();
-	kstat_cpu(cpu).irqs[irq - FIRST_IRQ]++;
-	action = irq_action[irq - FIRST_IRQ];
-
-        if (action) {
-                if (!(action->flags & SA_INTERRUPT))
-                        local_irq_enable();
-                do_random = 0;
-                do {
-			ret = action->handler(irq, action->dev_id, regs);
-			if (ret == IRQ_HANDLED)
-				do_random |= action->flags;
-                        retval |= ret;
-                        action = action->next;
-                } while (action);
-
-                if (retval != 1) {
-			if (retval) {
-				printk("irq event %d: bogus retval mask %x\n",
-					irq, retval);
-			} else {
-				printk("irq %d: nobody cared\n", irq);
-			}
-		}
-
-                if (do_random & SA_SAMPLE_RANDOM)
-                        add_interrupt_randomness(irq);
-		local_irq_disable();
-        }
-        irq_exit();
-}
-
-/* this function links in a handler into the chain of handlers for the
-   given irq, and if the irq has never been registred, the appropriate
-   handler is entered into the interrupt vector
-*/
-
-int setup_irq(int irq, struct irqaction * new)
-{
-	int shared = 0;
-	struct irqaction *old, **p;
-	unsigned long flags;
-
-	p = irq_action + irq - FIRST_IRQ;
-	if ((old = *p) != NULL) {
-		/* Can't share interrupts unless both agree to */
-		if (!(old->flags & new->flags & SA_SHIRQ))
-			return -EBUSY;
-
-		/* Can't share interrupts unless both are same type */
-		if ((old->flags ^ new->flags) & SA_INTERRUPT)
-			return -EBUSY;
-
-		/* add new interrupt at end of irq queue */
-		do {
-			p = &old->next;
-			old = *p;
-		} while (old);
-		shared = 1;
-	}
-
-	if (new->flags & SA_SAMPLE_RANDOM)
-		rand_initialize_irq(irq);
-
-	local_save_flags(flags);
-	local_irq_disable();
-	*p = new;
-
-	if (!shared) {
-		/* if the irq wasn't registred before, enter it into the vector table
-		   and unmask it physically 
-		*/
-		arch_setup_irq(irq);
-		unmask_irq(irq);
-	}
-	
-	local_irq_restore(flags);
-	return 0;
-}
-
-/* this function is called by a driver to register an irq handler
-   Valid flags:
-   SA_INTERRUPT -> it's a fast interrupt, handler called with irq disabled and
-                   no signal checking etc is performed upon exit
-   SA_SHIRQ -> the interrupt can be shared between different handlers, the handler
-                is required to check if the irq was "aimed" at it explicitely
-   SA_RANDOM -> the interrupt will add to the random generators entropy
-*/
-
-int request_irq(unsigned int irq, 
-		irqreturn_t (*handler)(int, void *, struct pt_regs *),
-		unsigned long irqflags, 
-		const char * devname,
-		void *dev_id)
-{
-	int retval;
-	struct irqaction * action;
-
-	if(!handler)
-		return -EINVAL;
-
-	/* allocate and fill in a handler structure and setup the irq */
-
-	action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
-	if (!action)
-		return -ENOMEM;
-
-	action->handler = handler;
-	action->flags = irqflags;
-	cpus_clear(action->mask);
-	action->name = devname;
-	action->next = NULL;
-	action->dev_id = dev_id;
-
-	retval = setup_irq(irq, action);
-
-	if (retval)
-		kfree(action);
-	return retval;
-}
-
-EXPORT_SYMBOL(request_irq);
-		
-void free_irq(unsigned int irq, void *dev_id)
-{
-	struct irqaction * action, **p;
-	unsigned long flags;
-
-	if (irq >= NR_IRQS) {
-		printk("Trying to free IRQ%d\n",irq);
-		return;
+	unsigned long sp;
+	irq_enter();
+	sp = rdsp();
+	if (unlikely((sp & (PAGE_SIZE - 1)) < (PAGE_SIZE/8))) {
+		printk("do_IRQ: stack overflow: %lX\n", sp);
+		show_stack(NULL, (unsigned long *)sp);
 	}
-	for (p = irq - FIRST_IRQ + irq_action; (action = *p) != NULL; p = &action->next) {
-		if (action->dev_id != dev_id)
-			continue;
-
-		/* Found it - now free it */
-		local_save_flags(flags);
-		local_irq_disable();
-		*p = action->next;
-		if (!irq_action[irq - FIRST_IRQ]) {
-			mask_irq(irq);
-			arch_free_irq(irq);
-		}
-		local_irq_restore(flags);
-		kfree(action);
-		return;
-	}
-	printk("Trying to free free IRQ%d\n",irq);
+	__do_IRQ(irq, regs);
+        irq_exit();
 }
 
-EXPORT_SYMBOL(free_irq);
-
 void weird_irq(void)
 {
 	local_irq_disable();
@@ -288,10 +112,3 @@ void weird_irq(void)
 	while(1);
 }
 
-#if defined(CONFIG_PROC_FS) && defined(CONFIG_SYSCTL)
-/* Used by other archs to show/control IRQ steering during SMP */
-void __init
-init_irq_proc(void)
-{
-}
-#endif
diff --git a/arch/cris/kernel/module.c b/arch/cris/kernel/module.c
index f1d3e784f30..11b867df861 100644
--- a/arch/cris/kernel/module.c
+++ b/arch/cris/kernel/module.c
@@ -32,7 +32,7 @@ void *module_alloc(unsigned long size)
 {
 	if (size == 0)
 		return NULL;
-	return vmalloc(size);
+	return vmalloc_exec(size);
 }
 
 
@@ -59,26 +59,8 @@ int apply_relocate(Elf32_Shdr *sechdrs,
 		   unsigned int relsec,
 		   struct module *me)
 {
-	unsigned int i;
-	Elf32_Rel *rel = (void *)sechdrs[relsec].sh_addr;
-	Elf32_Sym *sym;
-	uint32_t *location;
-
-	DEBUGP("Applying relocate section %u to %u\n", relsec,
-	       sechdrs[relsec].sh_info);
-	for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
-		/* This is where to make the change */
-		location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_offset
-			+ rel[i].r_offset;
-		/* This is the symbol it is referring to.  Note that all
-		   undefined symbols have been resolved.  */
-		sym = (Elf32_Sym *)sechdrs[symindex].sh_addr
-			+ ELF32_R_SYM(rel[i].r_info);
-
-                /* We add the value into the location given */
-                *location += sym->st_value;
-	}
-	return 0;
+	printk(KERN_ERR "module %s: REL relocation unsupported\n", me->name);
+	return -ENOEXEC;
 }
 
 int apply_relocate_add(Elf32_Shdr *sechdrs,
@@ -90,7 +72,7 @@ int apply_relocate_add(Elf32_Shdr *sechdrs,
   	unsigned int i;
 	Elf32_Rela *rela = (void *)sechdrs[relsec].sh_addr;
 
-	DEBUGP ("Applying relocate section %u to %u\n", relsec,
+	DEBUGP ("Applying add relocate section %u to %u\n", relsec,
 		sechdrs[relsec].sh_info);
 
 	for (i = 0; i < sechdrs[relsec].sh_size / sizeof (*rela); i++) {
@@ -103,7 +85,18 @@ int apply_relocate_add(Elf32_Shdr *sechdrs,
 		Elf32_Sym *sym
 			= ((Elf32_Sym *)sechdrs[symindex].sh_addr
 			   + ELF32_R_SYM (rela[i].r_info));
-		*loc = sym->st_value + rela[i].r_addend;
+		switch (ELF32_R_TYPE(rela[i].r_info)) {
+		case R_CRIS_32:
+			*loc = sym->st_value + rela[i].r_addend;
+			break;
+		case R_CRIS_32_PCREL:
+			*loc = sym->st_value - (unsigned)loc + rela[i].r_addend - 4;
+			 break;
+		default:
+			printk(KERN_ERR "module %s: Unknown relocation: %u\n",
+			       me->name, ELF32_R_TYPE(rela[i].r_info));
+			return -ENOEXEC;
+		}
 	}
 
 	return 0;
diff --git a/arch/cris/kernel/process.c b/arch/cris/kernel/process.c
index a5ad2b67585..949a0e40e03 100644
--- a/arch/cris/kernel/process.c
+++ b/arch/cris/kernel/process.c
@@ -1,4 +1,4 @@
-/* $Id: process.c,v 1.17 2004/04/05 13:53:48 starvik Exp $
+/* $Id: process.c,v 1.21 2005/03/04 08:16:17 starvik Exp $
  * 
  *  linux/arch/cris/kernel/process.c
  *
@@ -8,6 +8,18 @@
  *  Authors:   Bjorn Wesen (bjornw@axis.com)
  *
  *  $Log: process.c,v $
+ *  Revision 1.21  2005/03/04 08:16:17  starvik
+ *  Merge of Linux 2.6.11.
+ *
+ *  Revision 1.20  2005/01/18 05:57:22  starvik
+ *  Renamed hlt_counter to cris_hlt_counter and made it global.
+ *
+ *  Revision 1.19  2004/10/19 13:07:43  starvik
+ *  Merge of Linux 2.6.9
+ *
+ *  Revision 1.18  2004/08/16 12:37:23  starvik
+ *  Merge of Linux 2.6.8
+ *
  *  Revision 1.17  2004/04/05 13:53:48  starvik
  *  Merge of Linux 2.6.5
  *
@@ -161,18 +173,18 @@ EXPORT_SYMBOL(init_task);
  * region by enable_hlt/disable_hlt.
  */
 
-static int hlt_counter=0;
+int cris_hlt_counter=0;
 
 void disable_hlt(void)
 {
-	hlt_counter++;
+	cris_hlt_counter++;
 }
 
 EXPORT_SYMBOL(disable_hlt);
 
 void enable_hlt(void)
 {
-	hlt_counter--;
+	cris_hlt_counter--;
 }
 
 EXPORT_SYMBOL(enable_hlt);
@@ -195,16 +207,19 @@ void cpu_idle (void)
 	/* endless idle loop with no priority at all */
 	while (1) {
 		while (!need_resched()) {
-			void (*idle)(void) = pm_idle;
-
+			void (*idle)(void);
+			/*
+			 * Mark this as an RCU critical section so that
+			 * synchronize_kernel() in the unload path waits
+			 * for our completion.
+			 */
+			idle = pm_idle;
 			if (!idle)
 				idle = default_idle;
-
 			idle();
 		}
 		schedule();
 	}
-
 }
 
 void hard_reset_now (void);
diff --git a/arch/cris/kernel/profile.c b/arch/cris/kernel/profile.c
new file mode 100644
index 00000000000..69c52189f04
--- /dev/null
+++ b/arch/cris/kernel/profile.c
@@ -0,0 +1,73 @@
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/proc_fs.h>
+#include <linux/types.h>
+#include <asm/ptrace.h>
+#include <asm/uaccess.h>
+
+#define SAMPLE_BUFFER_SIZE 8192
+
+static char* sample_buffer;
+static char* sample_buffer_pos;
+static int prof_running = 0;
+
+void
+cris_profile_sample(struct pt_regs* regs)
+{
+  if (!prof_running)
+    return;
+  if (user_mode(regs))
+    *(unsigned int*)sample_buffer_pos = current->pid;
+  else
+    *(unsigned int*)sample_buffer_pos = 0;
+  *(unsigned int*)(sample_buffer_pos + 4) = instruction_pointer(regs);
+  sample_buffer_pos += 8;
+  if (sample_buffer_pos == sample_buffer + SAMPLE_BUFFER_SIZE)
+    sample_buffer_pos = sample_buffer;
+}
+
+static ssize_t
+read_cris_profile(struct file *file, char __user *buf, size_t count, loff_t *ppos)
+{
+  unsigned long p = *ppos;
+  if (p > SAMPLE_BUFFER_SIZE)
+    return 0;
+  if (p + count > SAMPLE_BUFFER_SIZE)
+    count = SAMPLE_BUFFER_SIZE - p;
+  if (copy_to_user(buf, sample_buffer + p,count))
+		return -EFAULT;
+  memset(sample_buffer + p, 0, count);
+  *ppos += count;
+  return count;
+}
+
+static ssize_t
+write_cris_profile(struct file *file, const char __user *buf,
+              size_t count, loff_t *ppos)
+{
+  sample_buffer_pos = sample_buffer;
+  memset(sample_buffer, 0, SAMPLE_BUFFER_SIZE);
+}
+
+static struct file_operations cris_proc_profile_operations = {
+	.read		= read_cris_profile,
+	.write		= write_cris_profile,
+};
+
+static int
+__init init_cris_profile(void)
+{
+  struct proc_dir_entry *entry;
+  sample_buffer = (char*)kmalloc(SAMPLE_BUFFER_SIZE, GFP_KERNEL);
+  sample_buffer_pos = sample_buffer;
+  entry = create_proc_entry("system_profile", S_IWUSR | S_IRUGO, NULL);
+  if (entry) {
+    entry->proc_fops = &cris_proc_profile_operations;
+    entry->size = SAMPLE_BUFFER_SIZE;
+  }
+  prof_running = 1;
+  return 0;
+}
+
+__initcall(init_cris_profile);
diff --git a/arch/cris/kernel/ptrace.c b/arch/cris/kernel/ptrace.c
index e85a2fdd9ac..2b6363cbe98 100644
--- a/arch/cris/kernel/ptrace.c
+++ b/arch/cris/kernel/ptrace.c
@@ -8,6 +8,12 @@
  * Authors:   Bjorn Wesen
  *
  * $Log: ptrace.c,v $
+ * Revision 1.10  2004/09/22 11:50:01  orjanf
+ * * Moved get_reg/put_reg to arch-specific files.
+ * * Added functions to access debug registers (CRISv32).
+ * * Added support for PTRACE_SINGLESTEP (CRISv32).
+ * * Added S flag to CCS_MASK (CRISv32).
+ *
  * Revision 1.9  2003/07/04 12:56:11  tobiasa
  * Moved arch-specific code to arch-specific files.
  *
@@ -72,37 +78,6 @@
 #include <asm/system.h>
 #include <asm/processor.h>
 
-/*
- * Get contents of register REGNO in task TASK.
- */
-inline long get_reg(struct task_struct *task, unsigned int regno)
-{
-	/* USP is a special case, it's not in the pt_regs struct but
-	 * in the tasks thread struct
-	 */
-
-	if (regno == PT_USP)
-		return task->thread.usp;
-	else if (regno < PT_MAX)
-		return ((unsigned long *)user_regs(task->thread_info))[regno];
-	else
-		return 0;
-}
-
-/*
- * Write contents of register REGNO in task TASK.
- */
-inline int put_reg(struct task_struct *task, unsigned int regno,
-			  unsigned long data)
-{
-	if (regno == PT_USP)
-		task->thread.usp = data;
-	else if (regno < PT_MAX)
-		((unsigned long *)user_regs(task->thread_info))[regno] = data;
-	else
-		return -1;
-	return 0;
-}
 
 /* notification of userspace execution resumption
  * - triggered by current->work.notify_resume
diff --git a/arch/cris/kernel/setup.c b/arch/cris/kernel/setup.c
index 6ec2671078b..d11206e467a 100644
--- a/arch/cris/kernel/setup.c
+++ b/arch/cris/kernel/setup.c
@@ -17,6 +17,7 @@
 #include <asm/pgtable.h>
 #include <linux/seq_file.h>
 #include <linux/tty.h>
+#include <linux/utsname.h>
 
 #include <asm/setup.h>
 
@@ -29,7 +30,7 @@ struct screen_info screen_info;
 extern int root_mountflags;
 extern char _etext, _edata, _end;
 
-static char command_line[COMMAND_LINE_SIZE] = { 0, };
+char cris_command_line[COMMAND_LINE_SIZE] = { 0, };
 
 extern const unsigned long text_start, edata; /* set by the linker script */
 extern unsigned long dram_start, dram_end;
@@ -147,34 +148,35 @@ setup_arch(char **cmdline_p)
 
 	paging_init();
 
-	/* We don't use a command line yet, so just re-initialize it without
-	   saving anything that might be there.  */
-
-	*cmdline_p = command_line;
+	*cmdline_p = cris_command_line;
 
 #ifdef CONFIG_ETRAX_CMDLINE
-	strlcpy(command_line, CONFIG_ETRAX_CMDLINE, COMMAND_LINE_SIZE);
-	command_line[COMMAND_LINE_SIZE - 1] = '\0';
+        if (!strcmp(cris_command_line, "")) {
+		strlcpy(cris_command_line, CONFIG_ETRAX_CMDLINE, COMMAND_LINE_SIZE);
+		cris_command_line[COMMAND_LINE_SIZE - 1] = '\0';
+	}
+#endif
 
 	/* Save command line for future references. */
-	memcpy(saved_command_line, command_line, COMMAND_LINE_SIZE);
+	memcpy(saved_command_line, cris_command_line, COMMAND_LINE_SIZE);
 	saved_command_line[COMMAND_LINE_SIZE - 1] = '\0';
-#endif
 
 	/* give credit for the CRIS port */
 	show_etrax_copyright();
+
+	/* Setup utsname */
+	strcpy(system_utsname.machine, cris_machine_name);
 }
 
 static void *c_start(struct seq_file *m, loff_t *pos)
 {
-	/* We only got one CPU... */
-	return *pos < 1 ? (void *)1 : NULL;
+	return *pos < NR_CPUS ? (void *)(int)(*pos + 1): NULL;
 }
 
 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 {
 	++*pos;
-	return NULL;
+	return c_start(m, pos);
 }
 
 static void c_stop(struct seq_file *m, void *v)
diff --git a/arch/cris/kernel/time.c b/arch/cris/kernel/time.c
index 6c28b0e7f7b..fa2d4323da2 100644
--- a/arch/cris/kernel/time.c
+++ b/arch/cris/kernel/time.c
@@ -1,4 +1,4 @@
-/* $Id: time.c,v 1.14 2004/06/01 05:38:11 starvik Exp $
+/* $Id: time.c,v 1.18 2005/03/04 08:16:17 starvik Exp $
  *
  *  linux/arch/cris/kernel/time.c
  *
@@ -30,6 +30,7 @@
 #include <linux/bcd.h>
 #include <linux/timex.h>
 #include <linux/init.h>
+#include <linux/profile.h>
 
 u64 jiffies_64 = INITIAL_JIFFIES;
 
@@ -214,6 +215,21 @@ update_xtime_from_cmos(void)
 	}
 }
 
+extern void cris_profile_sample(struct pt_regs* regs);
+
+void
+cris_do_profile(struct pt_regs* regs)
+{
+
+#if CONFIG_SYSTEM_PROFILER
+        cris_profile_sample(regs);
+#endif
+
+#if CONFIG_PROFILING
+        profile_tick(CPU_PROFILING, regs);
+#endif
+}
+
 /*
  * Scheduler clock - returns current time in nanosec units.
  */
diff --git a/arch/cris/kernel/traps.c b/arch/cris/kernel/traps.c
index d4dfa050e3a..520d92205fe 100644
--- a/arch/cris/kernel/traps.c
+++ b/arch/cris/kernel/traps.c
@@ -1,4 +1,4 @@
-/* $Id: traps.c,v 1.9 2004/05/11 12:28:26 starvik Exp $
+/* $Id: traps.c,v 1.11 2005/01/24 16:03:19 orjanf Exp $
  *
  *  linux/arch/cris/traps.c
  *
@@ -20,13 +20,15 @@
 
 static int kstack_depth_to_print = 24;
 
+extern int raw_printk(const char *fmt, ...);
+
 void show_trace(unsigned long * stack)
 {
 	unsigned long addr, module_start, module_end;
 	extern char _stext, _etext;
 	int i;
 
-        printk("\nCall Trace: ");
+        raw_printk("\nCall Trace: ");
 
         i = 1;
         module_start = VMALLOC_START;
@@ -37,7 +39,7 @@ void show_trace(unsigned long * stack)
 			/* This message matches "failing address" marked
 			   s390 in ksymoops, so lines containing it will
 			   not be filtered out by ksymoops.  */
-			printk ("Failing address 0x%lx\n", (unsigned long)stack);
+			raw_printk ("Failing address 0x%lx\n", (unsigned long)stack);
 			break;
 		}
 		stack++;
@@ -54,8 +56,8 @@ void show_trace(unsigned long * stack)
                      (addr <= (unsigned long) &_etext)) ||
                     ((addr >= module_start) && (addr <= module_end))) {
                         if (i && ((i % 8) == 0))
-                                printk("\n       ");
-                        printk("[<%08lx>] ", addr);
+                                raw_printk("\n       ");
+                        raw_printk("[<%08lx>] ", addr);
                         i++;
                 }
         }
@@ -96,25 +98,59 @@ show_stack(struct task_struct *task, unsigned long *sp)
 
         stack = sp;
 
-	printk("\nStack from %08lx:\n       ", (unsigned long)stack);
+	raw_printk("\nStack from %08lx:\n       ", (unsigned long)stack);
         for(i = 0; i < kstack_depth_to_print; i++) {
                 if (((long) stack & (THREAD_SIZE-1)) == 0)
                         break;
                 if (i && ((i % 8) == 0))
-                        printk("\n       ");
+                        raw_printk("\n       ");
 		if (__get_user (addr, stack)) {
 			/* This message matches "failing address" marked
 			   s390 in ksymoops, so lines containing it will
 			   not be filtered out by ksymoops.  */
-			printk ("Failing address 0x%lx\n", (unsigned long)stack);
+			raw_printk ("Failing address 0x%lx\n", (unsigned long)stack);
 			break;
 		}
 		stack++;
-		printk("%08lx ", addr);
+		raw_printk("%08lx ", addr);
         }
 	show_trace(sp);
 }
 
+static void (*nmi_handler)(struct pt_regs*);
+extern void arch_enable_nmi(void);
+
+void set_nmi_handler(void (*handler)(struct pt_regs*))
+{
+  nmi_handler = handler;
+  arch_enable_nmi();
+}
+
+void handle_nmi(struct pt_regs* regs)
+{
+  if (nmi_handler)
+    nmi_handler(regs);
+}
+
+#ifdef CONFIG_DEBUG_NMI_OOPS
+void oops_nmi_handler(struct pt_regs* regs)
+{
+  stop_watchdog();
+  raw_printk("NMI!\n");
+  show_registers(regs);
+}
+
+static int
+__init oops_nmi_register(void)
+{
+  set_nmi_handler(oops_nmi_handler);
+  return 0;
+}
+
+__initcall(oops_nmi_register);
+
+#endif
+
 #if 0
 /* displays a short stack trace */
 
@@ -123,9 +159,9 @@ show_stack()
 {
 	unsigned long *sp = (unsigned long *)rdusp();
 	int i;
-	printk("Stack dump [0x%08lx]:\n", (unsigned long)sp);
+	raw_printk("Stack dump [0x%08lx]:\n", (unsigned long)sp);
 	for(i = 0; i < 16; i++)
-		printk("sp + %d: 0x%08lx\n", i*4, sp[i]);
+		raw_printk("sp + %d: 0x%08lx\n", i*4, sp[i]);
 	return 0;
 }
 #endif
@@ -142,3 +178,9 @@ trap_init(void)
 {
 	/* Nothing needs to be done */
 }
+
+void spinning_cpu(void* addr)
+{
+  raw_printk("CPU %d spinning on %X\n", smp_processor_id(), addr);
+  dump_stack();
+}
diff --git a/arch/cris/mm/fault.c b/arch/cris/mm/fault.c
index 03254b9eded..934c51078cc 100644
--- a/arch/cris/mm/fault.c
+++ b/arch/cris/mm/fault.c
@@ -6,6 +6,38 @@
  *  Authors:  Bjorn Wesen 
  * 
  *  $Log: fault.c,v $
+ *  Revision 1.20  2005/03/04 08:16:18  starvik
+ *  Merge of Linux 2.6.11.
+ *
+ *  Revision 1.19  2005/01/14 10:07:59  starvik
+ *  Fixed warning.
+ *
+ *  Revision 1.18  2005/01/12 08:10:14  starvik
+ *  Readded the change of frametype when handling kernel page fault fixup
+ *  for v10. This is necessary to avoid that the CPU remakes the faulting
+ *  access.
+ *
+ *  Revision 1.17  2005/01/11 13:53:05  starvik
+ *  Use raw_printk.
+ *
+ *  Revision 1.16  2004/12/17 11:39:41  starvik
+ *  SMP support.
+ *
+ *  Revision 1.15  2004/11/23 18:36:18  starvik
+ *  Stack is now non-executable.
+ *  Signal handler trampolines are placed in a reserved page mapped into all
+ *  processes.
+ *
+ *  Revision 1.14  2004/11/23 07:10:21  starvik
+ *  Moved find_fixup_code to generic code.
+ *
+ *  Revision 1.13  2004/11/23 07:00:54  starvik
+ *  Actually use the execute permission bit in the MMU. This makes it possible
+ *  to prevent e.g. attacks where executable code is put on the stack.
+ *
+ *  Revision 1.12  2004/09/29 06:16:04  starvik
+ *  Use instruction_pointer
+ *
  *  Revision 1.11  2004/05/14 07:58:05  starvik
  *  Merge of changes from 2.4
  *
@@ -103,6 +135,7 @@
 
 extern int find_fixup_code(struct pt_regs *);
 extern void die_if_kernel(const char *, struct pt_regs *, long);
+extern int raw_printk(const char *fmt, ...);
 
 /* debug of low-level TLB reload */
 #undef DEBUG
@@ -118,7 +151,8 @@ extern void die_if_kernel(const char *, struct pt_regs *, long);
 
 /* current active page directory */
 
-volatile pgd_t *current_pgd;
+volatile DEFINE_PER_CPU(pgd_t *,current_pgd);
+unsigned long cris_signal_return_page;
 
 /*
  * This routine handles page faults.  It determines the address,
@@ -146,8 +180,9 @@ do_page_fault(unsigned long address, struct pt_regs *regs,
 	struct vm_area_struct * vma;
 	siginfo_t info;
 
-        D(printk("Page fault for %X at %X, prot %d write %d\n",
-                 address, regs->erp, protection, writeaccess));
+        D(printk("Page fault for %lX on %X at %lX, prot %d write %d\n",
+                 address, smp_processor_id(), instruction_pointer(regs),
+                 protection, writeaccess));
 
 	tsk = current;
 
@@ -175,8 +210,19 @@ do_page_fault(unsigned long address, struct pt_regs *regs,
 	    !user_mode(regs))
 		goto vmalloc_fault;
 
+	/* When stack execution is not allowed we store the signal
+	 * trampolines in the reserved cris_signal_return_page.
+	 * Handle this in the exact same way as vmalloc (we know
+	 * that the mapping is there and is valid so no need to
+	 * call handle_mm_fault).
+	 */
+	if (cris_signal_return_page &&
+	    address == cris_signal_return_page &&
+	    !protection && user_mode(regs))
+		goto vmalloc_fault;
+
 	/* we can and should enable interrupts at this point */
-	sti();
+	local_irq_enable();
 
 	mm = tsk->mm;
 	info.si_code = SEGV_MAPERR;
@@ -220,7 +266,10 @@ do_page_fault(unsigned long address, struct pt_regs *regs,
 
 	/* first do some preliminary protection checks */
 
-	if (writeaccess) {
+	if (writeaccess == 2){
+		if (!(vma->vm_flags & VM_EXEC))
+			goto bad_area;
+	} else if (writeaccess == 1) {
 		if (!(vma->vm_flags & VM_WRITE))
 			goto bad_area;
 	} else {
@@ -234,14 +283,14 @@ do_page_fault(unsigned long address, struct pt_regs *regs,
 	 * the fault.
 	 */
 
-	switch (handle_mm_fault(mm, vma, address, writeaccess)) {
-	case 1:
+	switch (handle_mm_fault(mm, vma, address, writeaccess & 1)) {
+	case VM_FAULT_MINOR:
 		tsk->min_flt++;
 		break;
-	case 2:
+	case VM_FAULT_MAJOR:
 		tsk->maj_flt++;
 		break;
-	case 0:
+	case VM_FAULT_SIGBUS:
 		goto do_sigbus;
 	default:
 		goto out_of_memory;
@@ -292,10 +341,10 @@ do_page_fault(unsigned long address, struct pt_regs *regs,
 	 */
 
 	if ((unsigned long) (address) < PAGE_SIZE)
-		printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference");
+		raw_printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference");
 	else
-		printk(KERN_ALERT "Unable to handle kernel access");
-	printk(" at virtual address %08lx\n",address);
+		raw_printk(KERN_ALERT "Unable to handle kernel access");
+	raw_printk(" at virtual address %08lx\n",address);
 
 	die_if_kernel("Oops", regs, (writeaccess << 1) | protection);
 
@@ -346,10 +395,11 @@ vmalloc_fault:
 
 		int offset = pgd_index(address);
 		pgd_t *pgd, *pgd_k;
+		pud_t *pud, *pud_k;
 		pmd_t *pmd, *pmd_k;
 		pte_t *pte_k;
 
-		pgd = (pgd_t *)current_pgd + offset;
+		pgd = (pgd_t *)per_cpu(current_pgd, smp_processor_id()) + offset;
 		pgd_k = init_mm.pgd + offset;
 
 		/* Since we're two-level, we don't need to do both
@@ -364,8 +414,13 @@ vmalloc_fault:
 		 * it exists.
 		 */
 
-		pmd = pmd_offset(pgd, address);
-		pmd_k = pmd_offset(pgd_k, address);
+		pud = pud_offset(pgd, address);
+		pud_k = pud_offset(pgd_k, address);
+		if (!pud_present(*pud_k))
+			goto no_context;
+
+		pmd = pmd_offset(pud, address);
+		pmd_k = pmd_offset(pud_k, address);
 
 		if (!pmd_present(*pmd_k))
 			goto bad_area_nosemaphore;
@@ -385,3 +440,19 @@ vmalloc_fault:
 		return;
 	}
 }
+
+/* Find fixup code. */
+int
+find_fixup_code(struct pt_regs *regs)
+{
+	const struct exception_table_entry *fixup;
+
+	if ((fixup = search_exception_tables(instruction_pointer(regs))) != 0) {
+		/* Adjust the instruction pointer in the stackframe. */
+		instruction_pointer(regs) = fixup->fixup;
+		arch_fixup(regs);
+		return 1;
+	}
+
+	return 0;
+}
diff --git a/arch/cris/mm/ioremap.c b/arch/cris/mm/ioremap.c
index 6b9130bfb6c..ebba11e270f 100644
--- a/arch/cris/mm/ioremap.c
+++ b/arch/cris/mm/ioremap.c
@@ -14,9 +14,10 @@
 #include <asm/pgalloc.h>
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
+#include <asm/arch/memmap.h>
 
 extern inline void remap_area_pte(pte_t * pte, unsigned long address, unsigned long size,
-	unsigned long phys_addr, unsigned long flags)
+	unsigned long phys_addr, pgprot_t prot)
 {
 	unsigned long end;
 
@@ -31,9 +32,7 @@ extern inline void remap_area_pte(pte_t * pte, unsigned long address, unsigned l
 			printk("remap_area_pte: page already exists\n");
 			BUG();
 		}
-		set_pte(pte, mk_pte_phys(phys_addr, __pgprot(_PAGE_PRESENT | __READABLE | 
-							     __WRITEABLE | _PAGE_GLOBAL |
-							     _PAGE_KERNEL | flags)));
+		set_pte(pte, mk_pte_phys(phys_addr, prot));
 		address += PAGE_SIZE;
 		phys_addr += PAGE_SIZE;
 		pte++;
@@ -41,7 +40,7 @@ extern inline void remap_area_pte(pte_t * pte, unsigned long address, unsigned l
 }
 
 static inline int remap_area_pmd(pmd_t * pmd, unsigned long address, unsigned long size,
-	unsigned long phys_addr, unsigned long flags)
+	unsigned long phys_addr, pgprot_t prot)
 {
 	unsigned long end;
 
@@ -56,7 +55,7 @@ static inline int remap_area_pmd(pmd_t * pmd, unsigned long address, unsigned lo
 		pte_t * pte = pte_alloc_kernel(&init_mm, pmd, address);
 		if (!pte)
 			return -ENOMEM;
-		remap_area_pte(pte, address, end - address, address + phys_addr, flags);
+		remap_area_pte(pte, address, end - address, address + phys_addr, prot);
 		address = (address + PMD_SIZE) & PMD_MASK;
 		pmd++;
 	} while (address && (address < end));
@@ -64,7 +63,7 @@ static inline int remap_area_pmd(pmd_t * pmd, unsigned long address, unsigned lo
 }
 
 static int remap_area_pages(unsigned long address, unsigned long phys_addr,
-				 unsigned long size, unsigned long flags)
+				 unsigned long size, pgprot_t prot)
 {
 	int error;
 	pgd_t * dir;
@@ -77,13 +76,19 @@ static int remap_area_pages(unsigned long address, unsigned long phys_addr,
 		BUG();
 	spin_lock(&init_mm.page_table_lock);
 	do {
+		pud_t *pud;
 		pmd_t *pmd;
-		pmd = pmd_alloc(&init_mm, dir, address);
+
 		error = -ENOMEM;
+		pud = pud_alloc(&init_mm, dir, address);
+		if (!pud)
+			break;
+		pmd = pmd_alloc(&init_mm, pud, address);
+
 		if (!pmd)
 			break;
 		if (remap_area_pmd(pmd, address, end - address,
-				   phys_addr + address, flags))
+				   phys_addr + address, prot))
 			break;
 		error = 0;
 		address = (address + PGDIR_SIZE) & PGDIR_MASK;
@@ -107,9 +112,9 @@ static int remap_area_pages(unsigned long address, unsigned long phys_addr,
  * have to convert them into an offset in a page-aligned mapping, but the
  * caller shouldn't need to know that small detail.
  */
-void * __ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags)
+void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot)
 {
-	void * addr;
+	void __iomem * addr;
 	struct vm_struct * area;
 	unsigned long offset, last_addr;
 
@@ -131,15 +136,36 @@ void * __ioremap(unsigned long phys_addr, unsigned long size, unsigned long flag
 	area = get_vm_area(size, VM_IOREMAP);
 	if (!area)
 		return NULL;
-	addr = area->addr;
-	if (remap_area_pages((unsigned long) addr, phys_addr, size, flags)) {
-		vfree(addr);
+	addr = (void __iomem *)area->addr;
+	if (remap_area_pages((unsigned long) addr, phys_addr, size, prot)) {
+		vfree((void __force *)addr);
 		return NULL;
 	}
-	return (void *) (offset + (char *)addr);
+	return (void __iomem *) (offset + (char __iomem *)addr);
+}
+
+void __iomem * __ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags)
+{
+	return __ioremap_prot(phys_addr, size,
+		              __pgprot(_PAGE_PRESENT | __READABLE |
+				       __WRITEABLE | _PAGE_GLOBAL |
+				       _PAGE_KERNEL | flags));
+}
+
+/**
+ * ioremap_nocache     -   map bus memory into CPU space
+ * @offset:    bus address of the memory
+ * @size:      size of the resource to map
+ *
+ * Must be freed with iounmap.
+ */
+
+void __iomem *ioremap_nocache (unsigned long phys_addr, unsigned long size)
+{
+        return __ioremap(phys_addr | MEM_NON_CACHEABLE, size, 0);
 }
 
-void iounmap(void *addr)
+void iounmap(volatile void __iomem *addr)
 {
 	if (addr > high_memory)
 		return vfree((void *) (PAGE_MASK & (unsigned long) addr));
diff --git a/arch/cris/mm/tlb.c b/arch/cris/mm/tlb.c
index 23eca5ad738..0df390a656c 100644
--- a/arch/cris/mm/tlb.c
+++ b/arch/cris/mm/tlb.c
@@ -29,18 +29,6 @@
 struct mm_struct *page_id_map[NUM_PAGEID];
 static int map_replace_ptr = 1;  /* which page_id_map entry to replace next */
 
-/*
- * Initialize the context related info for a new mm_struct
- * instance.
- */
-
-int
-init_new_context(struct task_struct *tsk, struct mm_struct *mm)
-{
-	mm->context = NO_CONTEXT;
-	return 0;
-}
-
 /* the following functions are similar to those used in the PPC port */
 
 static inline void
@@ -60,12 +48,12 @@ alloc_context(struct mm_struct *mm)
 		 */
 		flush_tlb_mm(old_mm);
 
-		old_mm->context = NO_CONTEXT;
+		old_mm->context.page_id = NO_CONTEXT;
 	}
 
 	/* insert it into the page_id_map */
 
-	mm->context = map_replace_ptr;
+	mm->context.page_id = map_replace_ptr;
 	page_id_map[map_replace_ptr] = mm;
 
 	map_replace_ptr++;
@@ -81,7 +69,7 @@ alloc_context(struct mm_struct *mm)
 void
 get_mmu_context(struct mm_struct *mm)
 {
-	if(mm->context == NO_CONTEXT)
+	if(mm->context.page_id == NO_CONTEXT)
 		alloc_context(mm);
 }
 
@@ -96,11 +84,10 @@ get_mmu_context(struct mm_struct *mm)
 void
 destroy_context(struct mm_struct *mm)
 {
-	if(mm->context != NO_CONTEXT) {
-		D(printk("destroy_context %d (%p)\n", mm->context, mm));
+	if(mm->context.page_id != NO_CONTEXT) {
+		D(printk("destroy_context %d (%p)\n", mm->context.page_id, mm));
 		flush_tlb_mm(mm);  /* TODO this might be redundant ? */
-		page_id_map[mm->context] = NULL;
-		/* mm->context = NO_CONTEXT; redundant.. mm will be freed */
+		page_id_map[mm->context.page_id] = NULL;
 	}
 }
 
diff --git a/arch/frv/mm/fault.c b/arch/frv/mm/fault.c
index 41d02ac4823..8b3eb50c510 100644
--- a/arch/frv/mm/fault.c
+++ b/arch/frv/mm/fault.c
@@ -163,13 +163,13 @@ asmlinkage void do_page_fault(int datammu, unsigned long esr0, unsigned long ear
 	 * the fault.
 	 */
 	switch (handle_mm_fault(mm, vma, ear0, write)) {
-	case 1:
+	case VM_FAULT_MINOR:
 		current->min_flt++;
 		break;
-	case 2:
+	case VM_FAULT_MAJOR:
 		current->maj_flt++;
 		break;
-	case 0:
+	case VM_FAULT_SIGBUS:
 		goto do_sigbus;
 	default:
 		goto out_of_memory;
diff --git a/arch/i386/Kconfig b/arch/i386/Kconfig
index a801d9d4860..619d843ba23 100644
--- a/arch/i386/Kconfig
+++ b/arch/i386/Kconfig
@@ -454,8 +454,9 @@ config HPET_TIMER
 	  Choose N to continue using the legacy 8254 timer.
 
 config HPET_EMULATE_RTC
-	bool "Provide RTC interrupt"
+	bool
 	depends on HPET_TIMER && RTC=y
+	default y
 
 config SMP
 	bool "Symmetric multi-processing support"
diff --git a/arch/i386/Kconfig.debug b/arch/i386/Kconfig.debug
index bfb2064f710..5228c40a6fb 100644
--- a/arch/i386/Kconfig.debug
+++ b/arch/i386/Kconfig.debug
@@ -18,6 +18,9 @@ config EARLY_PRINTK
 config DEBUG_STACKOVERFLOW
 	bool "Check for stack overflows"
 	depends on DEBUG_KERNEL
+	help
+	  This option will cause messages to be printed if free stack space
+	  drops below a certain limit.
 
 config KPROBES
 	bool "Kprobes"
diff --git a/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c
index 963e17aa205..60a9e54dd20 100644
--- a/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c
+++ b/arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c
@@ -442,6 +442,13 @@ acpi_cpufreq_cpu_init (
 			(u32) data->acpi_data.states[i].transition_latency);
 
 	cpufreq_frequency_table_get_attr(data->freq_table, policy->cpu);
+	
+	/*
+	 * the first call to ->target() should result in us actually
+	 * writing something to the appropriate registers.
+	 */
+	data->resume = 1;
+	
 	return (result);
 
  err_freqfree:
diff --git a/arch/i386/kernel/cpu/cpufreq/powernow-k8.c b/arch/i386/kernel/cpu/cpufreq/powernow-k8.c
index 10cc096c0ad..ab6e0611303 100644
--- a/arch/i386/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/i386/kernel/cpu/cpufreq/powernow-k8.c
@@ -1,5 +1,5 @@
 /*
- *   (c) 2003, 2004 Advanced Micro Devices, Inc.
+ *   (c) 2003, 2004, 2005 Advanced Micro Devices, Inc.
  *  Your use of this code is subject to the terms and conditions of the
  *  GNU general public license version 2. See "COPYING" or
  *  http://www.gnu.org/licenses/gpl.html
@@ -44,7 +44,7 @@
 
 #define PFX "powernow-k8: "
 #define BFX PFX "BIOS error: "
-#define VERSION "version 1.40.2"
+#define VERSION "version 1.50.3"
 #include "powernow-k8.h"
 
 /* serialize freq changes  */
@@ -110,14 +110,13 @@ static int query_current_values_with_pending_wait(struct powernow_k8_data *data)
 	u32 lo, hi;
 	u32 i = 0;
 
-	lo = MSR_S_LO_CHANGE_PENDING;
-	while (lo & MSR_S_LO_CHANGE_PENDING) {
+	do {
 		if (i++ > 0x1000000) {
 			printk(KERN_ERR PFX "detected change pending stuck\n");
 			return 1;
 		}
 		rdmsr(MSR_FIDVID_STATUS, lo, hi);
-	}
+	} while (lo & MSR_S_LO_CHANGE_PENDING);
 
 	data->currvid = hi & MSR_S_HI_CURRENT_VID;
 	data->currfid = lo & MSR_S_LO_CURRENT_FID;
@@ -232,7 +231,7 @@ static int write_new_vid(struct powernow_k8_data *data, u32 vid)
 /*
  * Reduce the vid by the max of step or reqvid.
  * Decreasing vid codes represent increasing voltages:
- * vid of 0 is 1.550V, vid of 0x1e is 0.800V, vid of 0x1f is off.
+ * vid of 0 is 1.550V, vid of 0x1e is 0.800V, vid of VID_OFF is off.
  */
 static int decrease_vid_code_by_step(struct powernow_k8_data *data, u32 reqvid, u32 step)
 {
@@ -467,7 +466,7 @@ static int check_supported_cpu(unsigned int cpu)
 	eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
 	if (((eax & CPUID_USE_XFAM_XMOD) != CPUID_USE_XFAM_XMOD) ||
 	    ((eax & CPUID_XFAM) != CPUID_XFAM_K8) ||
-	    ((eax & CPUID_XMOD) > CPUID_XMOD_REV_E)) {
+	    ((eax & CPUID_XMOD) > CPUID_XMOD_REV_F)) {
 		printk(KERN_INFO PFX "Processor cpuid %x not supported\n", eax);
 		goto out;
 	}
@@ -696,6 +695,7 @@ static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned
 
 	data->irt = (data->acpi_data.states[index].control >> IRT_SHIFT) & IRT_MASK;
 	data->rvo = (data->acpi_data.states[index].control >> RVO_SHIFT) & RVO_MASK;
+	data->exttype = (data->acpi_data.states[index].control >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK;
 	data->plllock = (data->acpi_data.states[index].control >> PLL_L_SHIFT) & PLL_L_MASK;
 	data->vidmvs = 1 << ((data->acpi_data.states[index].control >> MVS_SHIFT) & MVS_MASK);
 	data->vstable = (data->acpi_data.states[index].control >> VST_SHIFT) & VST_MASK;
@@ -735,8 +735,16 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data)
 	}
 
 	for (i = 0; i < data->acpi_data.state_count; i++) {
-		u32 fid = data->acpi_data.states[i].control & FID_MASK;
-		u32 vid = (data->acpi_data.states[i].control >> VID_SHIFT) & VID_MASK;
+		u32 fid;
+		u32 vid;
+
+		if (data->exttype) {
+			fid = data->acpi_data.states[i].status & FID_MASK;
+			vid = (data->acpi_data.states[i].status >> VID_SHIFT) & VID_MASK;
+		} else {
+			fid = data->acpi_data.states[i].control & FID_MASK;
+			vid = (data->acpi_data.states[i].control >> VID_SHIFT) & VID_MASK;
+		}
 
 		dprintk("   %d : fid 0x%x, vid 0x%x\n", i, fid, vid);
 
@@ -753,7 +761,7 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data)
 		}
 
 		/* verify voltage is OK - BIOSs are using "off" to indicate invalid */
-		if (vid == 0x1f) {
+		if (vid == VID_OFF) {
 			dprintk("invalid vid %u, ignoring\n", vid);
 			powernow_table[i].frequency = CPUFREQ_ENTRY_INVALID;
 			continue;
@@ -930,15 +938,6 @@ static int powernowk8_target(struct cpufreq_policy *pol, unsigned targfreq, unsi
 
 	down(&fidvid_sem);
 
-	for_each_cpu_mask(i, cpu_core_map[pol->cpu]) {
-		/* make sure the sibling is initialized */
-		if (!powernow_data[i]) {
-                        ret = 0;
-                        up(&fidvid_sem);
-                        goto err_out;
-                }
-	}
-
 	powernow_k8_acpi_pst_values(data, newstate);
 
 	if (transition_frequency(data, newstate)) {
@@ -978,7 +977,7 @@ static int __init powernowk8_cpu_init(struct cpufreq_policy *pol)
 {
 	struct powernow_k8_data *data;
 	cpumask_t oldmask = CPU_MASK_ALL;
-	int rc;
+	int rc, i;
 
 	if (!check_supported_cpu(pol->cpu))
 		return -ENODEV;
@@ -1064,7 +1063,9 @@ static int __init powernowk8_cpu_init(struct cpufreq_policy *pol)
 	printk("cpu_init done, current fid 0x%x, vid 0x%x\n",
 	       data->currfid, data->currvid);
 
-	powernow_data[pol->cpu] = data;
+	for_each_cpu_mask(i, cpu_core_map[pol->cpu]) {
+		powernow_data[i] = data;
+	}
 
 	return 0;
 
diff --git a/arch/i386/kernel/cpu/cpufreq/powernow-k8.h b/arch/i386/kernel/cpu/cpufreq/powernow-k8.h
index 9ed5bf221cb..b1e85bb3639 100644
--- a/arch/i386/kernel/cpu/cpufreq/powernow-k8.h
+++ b/arch/i386/kernel/cpu/cpufreq/powernow-k8.h
@@ -1,5 +1,5 @@
 /*
- *  (c) 2003, 2004 Advanced Micro Devices, Inc.
+ *  (c) 2003, 2004, 2005 Advanced Micro Devices, Inc.
  *  Your use of this code is subject to the terms and conditions of the
  *  GNU general public license version 2. See "COPYING" or
  *  http://www.gnu.org/licenses/gpl.html
@@ -19,6 +19,7 @@ struct powernow_k8_data {
 	u32 vidmvs;  /* usable value calculated from mvs */
 	u32 vstable; /* voltage stabilization time, units 20 us */
 	u32 plllock; /* pll lock time, units 1 us */
+        u32 exttype; /* extended interface = 1 */
 
 	/* keep track of the current fid / vid */
 	u32 currvid, currfid;
@@ -41,7 +42,7 @@ struct powernow_k8_data {
 #define CPUID_XFAM			0x0ff00000	/* extended family */
 #define CPUID_XFAM_K8			0
 #define CPUID_XMOD			0x000f0000	/* extended model */
-#define CPUID_XMOD_REV_E		0x00020000
+#define CPUID_XMOD_REV_F		0x00040000
 #define CPUID_USE_XFAM_XMOD		0x00000f00
 #define CPUID_GET_MAX_CAPABILITIES	0x80000000
 #define CPUID_FREQ_VOLT_CAPABILITIES	0x80000007
@@ -57,25 +58,26 @@ struct powernow_k8_data {
 
 /* Field definitions within the FID VID Low Control MSR : */
 #define MSR_C_LO_INIT_FID_VID     0x00010000
-#define MSR_C_LO_NEW_VID          0x00001f00
-#define MSR_C_LO_NEW_FID          0x0000002f
+#define MSR_C_LO_NEW_VID          0x00003f00
+#define MSR_C_LO_NEW_FID          0x0000003f
 #define MSR_C_LO_VID_SHIFT        8
 
 /* Field definitions within the FID VID High Control MSR : */
-#define MSR_C_HI_STP_GNT_TO       0x000fffff
+#define MSR_C_HI_STP_GNT_TO 	  0x000fffff
 
 /* Field definitions within the FID VID Low Status MSR : */
-#define MSR_S_LO_CHANGE_PENDING   0x80000000	/* cleared when completed */
-#define MSR_S_LO_MAX_RAMP_VID     0x1f000000
+#define MSR_S_LO_CHANGE_PENDING   0x80000000   /* cleared when completed */
+#define MSR_S_LO_MAX_RAMP_VID     0x3f000000
 #define MSR_S_LO_MAX_FID          0x003f0000
 #define MSR_S_LO_START_FID        0x00003f00
 #define MSR_S_LO_CURRENT_FID      0x0000003f
 
 /* Field definitions within the FID VID High Status MSR : */
-#define MSR_S_HI_MAX_WORKING_VID  0x001f0000
-#define MSR_S_HI_START_VID        0x00001f00
-#define MSR_S_HI_CURRENT_VID      0x0000001f
-#define MSR_C_HI_STP_GNT_BENIGN   0x00000001
+#define MSR_S_HI_MIN_WORKING_VID  0x3f000000
+#define MSR_S_HI_MAX_WORKING_VID  0x003f0000
+#define MSR_S_HI_START_VID        0x00003f00
+#define MSR_S_HI_CURRENT_VID      0x0000003f
+#define MSR_C_HI_STP_GNT_BENIGN	  0x00000001
 
 /*
  * There are restrictions frequencies have to follow:
@@ -99,13 +101,15 @@ struct powernow_k8_data {
 #define MIN_FREQ_RESOLUTION  200 /* fids jump by 2 matching freq jumps by 200 */
 
 #define MAX_FID 0x2a	/* Spec only gives FID values as far as 5 GHz */
-#define LEAST_VID 0x1e	/* Lowest (numerically highest) useful vid value */
+#define LEAST_VID 0x3e	/* Lowest (numerically highest) useful vid value */
 
 #define MIN_FREQ 800	/* Min and max freqs, per spec */
 #define MAX_FREQ 5000
 
 #define INVALID_FID_MASK 0xffffffc1  /* not a valid fid if these bits are set */
-#define INVALID_VID_MASK 0xffffffe0  /* not a valid vid if these bits are set */
+#define INVALID_VID_MASK 0xffffffc0  /* not a valid vid if these bits are set */
+
+#define VID_OFF 0x3f
 
 #define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */
 
@@ -121,12 +125,14 @@ struct powernow_k8_data {
                                                                                                     
 #define IRT_SHIFT      30
 #define RVO_SHIFT      28
+#define EXT_TYPE_SHIFT 27
 #define PLL_L_SHIFT    20
 #define MVS_SHIFT      18
 #define VST_SHIFT      11
 #define VID_SHIFT       6
 #define IRT_MASK        3
 #define RVO_MASK        3
+#define EXT_TYPE_MASK   1
 #define PLL_L_MASK   0x7f
 #define MVS_MASK        3
 #define VST_MASK     0x7f
diff --git a/arch/i386/kernel/cpu/intel_cacheinfo.c b/arch/i386/kernel/cpu/intel_cacheinfo.c
index 1d768b26326..6c55b50cf04 100644
--- a/arch/i386/kernel/cpu/intel_cacheinfo.c
+++ b/arch/i386/kernel/cpu/intel_cacheinfo.c
@@ -128,7 +128,7 @@ static int __devinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_le
 	cpuid_count(4, index, &eax, &ebx, &ecx, &edx);
 	cache_eax.full = eax;
 	if (cache_eax.split.type == CACHE_TYPE_NULL)
-		return -1;
+		return -EIO; /* better error ? */
 
 	this_leaf->eax.full = eax;
 	this_leaf->ebx.full = ebx;
@@ -334,6 +334,7 @@ static int __devinit detect_cache_attributes(unsigned int cpu)
 	struct _cpuid4_info	*this_leaf;
 	unsigned long 		j;
 	int 			retval;
+	cpumask_t		oldmask;
 
 	if (num_cache_leaves == 0)
 		return -ENOENT;
@@ -345,19 +346,26 @@ static int __devinit detect_cache_attributes(unsigned int cpu)
 	memset(cpuid4_info[cpu], 0,
 	    sizeof(struct _cpuid4_info) * num_cache_leaves);
 
+	oldmask = current->cpus_allowed;
+	retval = set_cpus_allowed(current, cpumask_of_cpu(cpu));
+	if (retval)
+		goto out;
+
 	/* Do cpuid and store the results */
+	retval = 0;
 	for (j = 0; j < num_cache_leaves; j++) {
 		this_leaf = CPUID4_INFO_IDX(cpu, j);
 		retval = cpuid4_cache_lookup(j, this_leaf);
 		if (unlikely(retval < 0))
-			goto err_out;
+			break;
 		cache_shared_cpu_map_setup(cpu, j);
 	}
-	return 0;
+	set_cpus_allowed(current, oldmask);
 
-err_out:
-	free_cache_attributes(cpu);
-	return -ENOMEM;
+out:
+	if (retval)
+		free_cache_attributes(cpu);
+	return retval;
 }
 
 #ifdef CONFIG_SYSFS
diff --git a/arch/i386/kernel/cpu/transmeta.c b/arch/i386/kernel/cpu/transmeta.c
index f57e5ee9494..fc426380366 100644
--- a/arch/i386/kernel/cpu/transmeta.c
+++ b/arch/i386/kernel/cpu/transmeta.c
@@ -76,6 +76,12 @@ static void __init init_transmeta(struct cpuinfo_x86 *c)
 #define USER686 (X86_FEATURE_TSC|X86_FEATURE_CX8|X86_FEATURE_CMOV)
         if ( c->x86 == 5 && (c->x86_capability[0] & USER686) == USER686 )
 		c->x86 = 6;
+
+#ifdef CONFIG_SYSCTL
+	/* randomize_va_space slows us down enormously;
+	   it probably triggers retranslation of x86->native bytecode */
+	randomize_va_space = 0;
+#endif
 }
 
 static void transmeta_identify(struct cpuinfo_x86 * c)
diff --git a/arch/i386/kernel/machine_kexec.c b/arch/i386/kernel/machine_kexec.c
index 52ed18d8b51..cb699a2aa1f 100644
--- a/arch/i386/kernel/machine_kexec.c
+++ b/arch/i386/kernel/machine_kexec.c
@@ -16,6 +16,7 @@
 #include <asm/io.h>
 #include <asm/apic.h>
 #include <asm/cpufeature.h>
+#include <asm/desc.h>
 
 static inline unsigned long read_cr3(void)
 {
@@ -90,33 +91,32 @@ static void identity_map_page(unsigned long address)
 }
 #endif
 
-
 static void set_idt(void *newidt, __u16 limit)
 {
-	unsigned char curidt[6];
+	struct Xgt_desc_struct curidt;
 
 	/* ia32 supports unaliged loads & stores */
-	(*(__u16 *)(curidt)) = limit;
-	(*(__u32 *)(curidt +2)) = (unsigned long)(newidt);
+	curidt.size    = limit;
+	curidt.address = (unsigned long)newidt;
 
 	__asm__ __volatile__ (
-		"lidt %0\n"
-		: "=m" (curidt)
+		"lidtl %0\n"
+		: : "m" (curidt)
 		);
 };
 
 
 static void set_gdt(void *newgdt, __u16 limit)
 {
-	unsigned char curgdt[6];
+	struct Xgt_desc_struct curgdt;
 
 	/* ia32 supports unaligned loads & stores */
-	(*(__u16 *)(curgdt)) = limit;
-	(*(__u32 *)(curgdt +2)) = (unsigned long)(newgdt);
+	curgdt.size    = limit;
+	curgdt.address = (unsigned long)newgdt;
 
 	__asm__ __volatile__ (
-		"lgdt %0\n"
-		: "=m" (curgdt)
+		"lgdtl %0\n"
+		: : "m" (curgdt)
 		);
 };
 
diff --git a/arch/i386/kernel/mpparse.c b/arch/i386/kernel/mpparse.c
index af917f609c7..ce838abb27d 100644
--- a/arch/i386/kernel/mpparse.c
+++ b/arch/i386/kernel/mpparse.c
@@ -1116,7 +1116,15 @@ int mp_register_gsi (u32 gsi, int edge_level, int active_high_low)
 		 */
 		int irq = gsi;
 		if (gsi < MAX_GSI_NUM) {
-			gsi = pci_irq++;
+			if (gsi > 15)
+				gsi = pci_irq++;
+#ifdef CONFIG_ACPI_BUS
+			/*
+			 * Don't assign IRQ used by ACPI SCI
+			 */
+			if (gsi == acpi_fadt.sci_int)
+				gsi = pci_irq++;
+#endif
 			gsi_to_irq[irq] = gsi;
 		} else {
 			printk(KERN_ERR "GSI %u is too high\n", gsi);
diff --git a/arch/i386/kernel/numaq.c b/arch/i386/kernel/numaq.c
index e51edf0a656..5f5b075f860 100644
--- a/arch/i386/kernel/numaq.c
+++ b/arch/i386/kernel/numaq.c
@@ -31,6 +31,7 @@
 #include <linux/nodemask.h>
 #include <asm/numaq.h>
 #include <asm/topology.h>
+#include <asm/processor.h>
 
 #define	MB_TO_PAGES(addr) ((addr) << (20 - PAGE_SHIFT))
 
@@ -77,3 +78,11 @@ int __init get_memcfg_numaq(void)
 	smp_dump_qct();
 	return 1;
 }
+
+static int __init numaq_dsc_disable(void)
+{
+	printk(KERN_DEBUG "NUMAQ: disabling TSC\n");
+	tsc_disable = 1;
+	return 0;
+}
+core_initcall(numaq_dsc_disable);
diff --git a/arch/i386/kernel/process.c b/arch/i386/kernel/process.c
index d9492058aaf..e3f362e8af5 100644
--- a/arch/i386/kernel/process.c
+++ b/arch/i386/kernel/process.c
@@ -917,6 +917,8 @@ asmlinkage int sys_get_thread_area(struct user_desc __user *u_info)
 	if (idx < GDT_ENTRY_TLS_MIN || idx > GDT_ENTRY_TLS_MAX)
 		return -EINVAL;
 
+	memset(&info, 0, sizeof(info));
+
 	desc = current->thread.tls_array + idx - GDT_ENTRY_TLS_MIN;
 
 	info.entry_number = idx;
diff --git a/arch/i386/kernel/syscall_table.S b/arch/i386/kernel/syscall_table.S
index 468500a7e89..9b21a31d4f4 100644
--- a/arch/i386/kernel/syscall_table.S
+++ b/arch/i386/kernel/syscall_table.S
@@ -251,7 +251,7 @@ ENTRY(sys_call_table)
 	.long sys_io_submit
 	.long sys_io_cancel
 	.long sys_fadvise64	/* 250 */
-	.long sys_set_zone_reclaim
+	.long sys_ni_syscall
 	.long sys_exit_group
 	.long sys_lookup_dcookie
 	.long sys_epoll_create
diff --git a/arch/i386/mach-visws/reboot.c b/arch/i386/mach-visws/reboot.c
index 9e9296676f9..5d73e042ed0 100644
--- a/arch/i386/mach-visws/reboot.c
+++ b/arch/i386/mach-visws/reboot.c
@@ -9,12 +9,15 @@
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
-void machine_restart(char * __unused)
+void machine_shutdown(void)
 {
 #ifdef CONFIG_SMP
 	smp_send_stop();
 #endif
+}
 
+void machine_emergency_restart(void)
+{
 	/*
 	 * Visual Workstations restart after this
 	 * register is poked on the PIIX4
@@ -22,6 +25,12 @@ void machine_restart(char * __unused)
 	outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT);
 }
 
+void machine_restart(char * __unused)
+{
+	machine_shutdown();
+	machine_emergency_restart();
+}
+
 void machine_power_off(void)
 {
 	unsigned short pm_status;
diff --git a/arch/i386/mach-visws/setup.c b/arch/i386/mach-visws/setup.c
index 9f6d2d9b1be..26ada6fc0d7 100644
--- a/arch/i386/mach-visws/setup.c
+++ b/arch/i386/mach-visws/setup.c
@@ -14,6 +14,8 @@
 #include "cobalt.h"
 #include "piix4.h"
 
+int no_broadcast;
+
 char visws_board_type = -1;
 char visws_board_rev = -1;
 
diff --git a/arch/i386/mach-voyager/voyager_basic.c b/arch/i386/mach-voyager/voyager_basic.c
index b3eda46e0fe..c6384061328 100644
--- a/arch/i386/mach-voyager/voyager_basic.c
+++ b/arch/i386/mach-voyager/voyager_basic.c
@@ -252,6 +252,12 @@ kb_wait(void)
 }
 
 void
+machine_shutdown(void)
+{
+	/* Architecture specific shutdown needed before a kexec */
+}
+
+void
 machine_restart(char *cmd)
 {
 	printk("Voyager Warm Restart\n");
@@ -279,6 +285,13 @@ machine_restart(char *cmd)
 }
 
 void
+machine_emergency_restart(void)
+{
+	/*for now, just hook this to a warm restart */
+	machine_restart(NULL);
+}
+
+void
 mca_nmi_hook(void)
 {
 	__u8 dumpval __attribute__((unused)) = inb(0xf823);
diff --git a/arch/i386/mm/discontig.c b/arch/i386/mm/discontig.c
index b358f0702a4..6711ce3f691 100644
--- a/arch/i386/mm/discontig.c
+++ b/arch/i386/mm/discontig.c
@@ -262,6 +262,17 @@ static unsigned long calculate_numa_remap_pages(void)
 		reserve_pages += size;
 		printk("Shrinking node %d from %ld pages to %ld pages\n",
 			nid, node_end_pfn[nid], node_end_pfn[nid] - size);
+
+		if (node_end_pfn[nid] & (PTRS_PER_PTE-1)) {
+			/*
+			 * Align node_end_pfn[] and node_remap_start_pfn[] to
+			 * pmd boundary. remap_numa_kva will barf otherwise.
+			 */
+			printk("Shrinking node %d further by %ld pages for proper alignment\n",
+				nid, node_end_pfn[nid] & (PTRS_PER_PTE-1));
+			size +=  node_end_pfn[nid] & (PTRS_PER_PTE-1);
+		}
+
 		node_end_pfn[nid] -= size;
 		node_remap_start_pfn[nid] = node_end_pfn[nid];
 	}
diff --git a/arch/i386/pci/acpi.c b/arch/i386/pci/acpi.c
index 2db65ec45dc..42913f43feb 100644
--- a/arch/i386/pci/acpi.c
+++ b/arch/i386/pci/acpi.c
@@ -30,6 +30,7 @@ static int __init pci_acpi_init(void)
 	acpi_irq_penalty_init();
 	pcibios_scanned++;
 	pcibios_enable_irq = acpi_pci_irq_enable;
+	pcibios_disable_irq = acpi_pci_irq_disable;
 
 	if (pci_routeirq) {
 		/*
diff --git a/arch/i386/pci/common.c b/arch/i386/pci/common.c
index 70bcd53451f..ade5bc57c34 100644
--- a/arch/i386/pci/common.c
+++ b/arch/i386/pci/common.c
@@ -254,3 +254,9 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
 
 	return pcibios_enable_irq(dev);
 }
+
+void pcibios_disable_device (struct pci_dev *dev)
+{
+	if (pcibios_disable_irq)
+		pcibios_disable_irq(dev);
+}
diff --git a/arch/i386/pci/irq.c b/arch/i386/pci/irq.c
index 766b104ac1a..86348b68fda 100644
--- a/arch/i386/pci/irq.c
+++ b/arch/i386/pci/irq.c
@@ -56,6 +56,7 @@ struct irq_router_handler {
 };
 
 int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL;
+void (*pcibios_disable_irq)(struct pci_dev *dev) = NULL;
 
 /*
  *  Check passed address for the PCI IRQ Routing Table signature
@@ -550,6 +551,13 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route
 static __init int via_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
 {
 	/* FIXME: We should move some of the quirk fixup stuff here */
+
+	if (router->device == PCI_DEVICE_ID_VIA_82C686 &&
+			device == PCI_DEVICE_ID_VIA_82C586_0) {
+		/* Asus k7m bios wrongly reports 82C686A as 586-compatible */
+		device = PCI_DEVICE_ID_VIA_82C686;
+	}
+
 	switch(device)
 	{
 		case PCI_DEVICE_ID_VIA_82C586_0:
diff --git a/arch/i386/pci/pci.h b/arch/i386/pci/pci.h
index a80f0f55ff5..127d53ad16b 100644
--- a/arch/i386/pci/pci.h
+++ b/arch/i386/pci/pci.h
@@ -73,3 +73,4 @@ extern int pcibios_scanned;
 extern spinlock_t pci_config_lock;
 
 extern int (*pcibios_enable_irq)(struct pci_dev *dev);
+extern void (*pcibios_disable_irq)(struct pci_dev *dev);
diff --git a/arch/i386/pci/visws.c b/arch/i386/pci/visws.c
index 314c933b6b8..6c17433fdf7 100644
--- a/arch/i386/pci/visws.c
+++ b/arch/i386/pci/visws.c
@@ -18,8 +18,10 @@
 extern struct pci_raw_ops pci_direct_conf1;
 
 static int pci_visws_enable_irq(struct pci_dev *dev) { return 0; }
+static void pci_visws_disable_irq(struct pci_dev *dev) { }
 
 int (*pcibios_enable_irq)(struct pci_dev *dev) = &pci_visws_enable_irq;
+void (*pcibios_disable_irq)(struct pci_dev *dev) = &pci_visws_disable_irq;
 
 void __init pcibios_penalize_isa_irq(int irq, int active) {}
 
diff --git a/arch/ia64/kernel/entry.S b/arch/ia64/kernel/entry.S
index bb9a506deb7..9be53e1ea40 100644
--- a/arch/ia64/kernel/entry.S
+++ b/arch/ia64/kernel/entry.S
@@ -1573,9 +1573,9 @@ sys_call_table:
 	data8 sys_keyctl
 	data8 sys_ioprio_set
 	data8 sys_ioprio_get			// 1275
-	data8 sys_set_zone_reclaim
-	data8 sys_ni_syscall
-	data8 sys_ni_syscall
 	data8 sys_ni_syscall
+	data8 sys_inotify_init
+	data8 sys_inotify_add_watch
+	data8 sys_inotify_rm_watch
 
 	.org sys_call_table + 8*NR_syscalls	// guard against failures to increase NR_syscalls
diff --git a/arch/ia64/kernel/unwind.c b/arch/ia64/kernel/unwind.c
index 2776a074c6f..3288be47bc7 100644
--- a/arch/ia64/kernel/unwind.c
+++ b/arch/ia64/kernel/unwind.c
@@ -362,7 +362,7 @@ unw_access_gr (struct unw_frame_info *info, int regnum, unsigned long *val, char
 			if (info->pri_unat_loc)
 				nat_addr = info->pri_unat_loc;
 			else
-				nat_addr = &info->sw->ar_unat;
+				nat_addr = &info->sw->caller_unat;
 			nat_mask = (1UL << ((long) addr & 0x1f8)/8);
 		}
 	} else {
@@ -524,7 +524,7 @@ unw_access_ar (struct unw_frame_info *info, int regnum, unsigned long *val, int
 	      case UNW_AR_UNAT:
 		addr = info->unat_loc;
 		if (!addr)
-			addr = &info->sw->ar_unat;
+			addr = &info->sw->caller_unat;
 		break;
 
 	      case UNW_AR_LC:
@@ -1775,7 +1775,7 @@ run_script (struct unw_script *script, struct unw_frame_info *state)
 
 		      case UNW_INSN_SETNAT_MEMSTK:
 			if (!state->pri_unat_loc)
-				state->pri_unat_loc = &state->sw->ar_unat;
+				state->pri_unat_loc = &state->sw->caller_unat;
 			/* register off. is a multiple of 8, so the least 3 bits (type) are 0 */
 			s[dst+1] = ((unsigned long) state->pri_unat_loc - s[dst]) | UNW_NAT_MEMSTK;
 			break;
@@ -2243,11 +2243,11 @@ unw_init (void)
 	if (8*sizeof(unw_hash_index_t) < UNW_LOG_HASH_SIZE)
 		unw_hash_index_t_is_too_narrow();
 
-	unw.sw_off[unw.preg_index[UNW_REG_PRI_UNAT_GR]] = SW(AR_UNAT);
+	unw.sw_off[unw.preg_index[UNW_REG_PRI_UNAT_GR]] = SW(CALLER_UNAT);
 	unw.sw_off[unw.preg_index[UNW_REG_BSPSTORE]] = SW(AR_BSPSTORE);
-	unw.sw_off[unw.preg_index[UNW_REG_PFS]] = SW(AR_UNAT);
+	unw.sw_off[unw.preg_index[UNW_REG_PFS]] = SW(AR_PFS);
 	unw.sw_off[unw.preg_index[UNW_REG_RP]] = SW(B0);
-	unw.sw_off[unw.preg_index[UNW_REG_UNAT]] = SW(AR_UNAT);
+	unw.sw_off[unw.preg_index[UNW_REG_UNAT]] = SW(CALLER_UNAT);
 	unw.sw_off[unw.preg_index[UNW_REG_PR]] = SW(PR);
 	unw.sw_off[unw.preg_index[UNW_REG_LC]] = SW(AR_LC);
 	unw.sw_off[unw.preg_index[UNW_REG_FPSR]] = SW(AR_FPSR);
diff --git a/arch/m32r/Kconfig.debug b/arch/m32r/Kconfig.debug
index 36788c2c310..31039723804 100644
--- a/arch/m32r/Kconfig.debug
+++ b/arch/m32r/Kconfig.debug
@@ -5,6 +5,9 @@ source "lib/Kconfig.debug"
 config DEBUG_STACKOVERFLOW
 	bool "Check for stack overflows"
 	depends on DEBUG_KERNEL
+	help
+	  This option will cause messages to be printed if free stack space
+	  drops below a certain limit.
 
 config DEBUG_STACK_USAGE
 	bool "Stack utilization instrumentation"
diff --git a/arch/m32r/kernel/time.c b/arch/m32r/kernel/time.c
index 3c4707280a5..8a2b77bc574 100644
--- a/arch/m32r/kernel/time.c
+++ b/arch/m32r/kernel/time.c
@@ -205,8 +205,7 @@ static long last_rtc_update = 0;
  * timer_interrupt() needs to keep up the real-time clock,
  * as well as call the "do_timer()" routine every clocktick
  */
-static inline void
-do_timer_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 {
 #ifndef CONFIG_SMP
 	profile_tick(CPU_PROFILING, regs);
@@ -221,6 +220,7 @@ do_timer_interrupt(int irq, void *dev_id, struct pt_regs * regs)
 	 * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
 	 * called as close as possible to 500 ms before the new second starts.
 	 */
+	write_seqlock(&xtime_lock);
 	if ((time_status & STA_UNSYNC) == 0
 		&& xtime.tv_sec > last_rtc_update + 660
 		&& (xtime.tv_nsec / 1000) >= 500000 - ((unsigned)TICK_SIZE) / 2
@@ -231,6 +231,7 @@ do_timer_interrupt(int irq, void *dev_id, struct pt_regs * regs)
 		else	/* do it again in 60 s */
 			last_rtc_update = xtime.tv_sec - 600;
 	}
+	write_sequnlock(&xtime_lock);
 	/* As we return to user mode fire off the other CPU schedulers..
 	   this is basically because we don't yet share IRQ's around.
 	   This message is rigged to be safe on the 386 - basically it's
@@ -238,14 +239,8 @@ do_timer_interrupt(int irq, void *dev_id, struct pt_regs * regs)
 
 #ifdef CONFIG_SMP
 	smp_local_timer_interrupt(regs);
+	smp_send_timer();
 #endif
-}
-
-irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
-{
-	write_seqlock(&xtime_lock);
-	do_timer_interrupt(irq, NULL, regs);
-	write_sequnlock(&xtime_lock);
 
 	return IRQ_HANDLED;
 }
diff --git a/arch/m68k/mm/fault.c b/arch/m68k/mm/fault.c
index ac48b6d2aff..aec15270d33 100644
--- a/arch/m68k/mm/fault.c
+++ b/arch/m68k/mm/fault.c
@@ -160,13 +160,13 @@ good_area:
 	printk("handle_mm_fault returns %d\n",fault);
 #endif
 	switch (fault) {
-	case 1:
+	case VM_FAULT_MINOR:
 		current->min_flt++;
 		break;
-	case 2:
+	case VM_FAULT_MAJOR:
 		current->maj_flt++;
 		break;
-	case 0:
+	case VM_FAULT_SIGBUS:
 		goto bus_err;
 	default:
 		goto out_of_memory;
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b578239146b..898de2df1fc 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1088,41 +1088,6 @@ config ARC32
 	depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP22 || SGI_IP32
 	default y
 
-config FB
-	bool
-	depends on MIPS_MAGNUM_4000 || OLIVETTI_M700
-	default y
-	---help---
-	  The frame buffer device provides an abstraction for the graphics
-	  hardware. It represents the frame buffer of some video hardware and
-	  allows application software to access the graphics hardware through
-	  a well-defined interface, so the software doesn't need to know
-	  anything about the low-level (hardware register) stuff.
-
-	  Frame buffer devices work identically across the different
-	  architectures supported by Linux and make the implementation of
-	  application programs easier and more portable; at this point, an X
-	  server exists which uses the frame buffer device exclusively.
-	  On several non-X86 architectures, the frame buffer device is the
-	  only way to use the graphics hardware.
-
-	  The device is accessed through special device nodes, usually located
-	  in the /dev directory, i.e. /dev/fb*.
-
-	  You need an utility program called fbset to make full use of frame
-	  buffer devices. Please read <file:Documentation/fb/framebuffer.txt>
-	  and the Framebuffer-HOWTO at <http://www.tldp.org/docs.html#howto>
-	  for more information.
-
-	  Say Y here and to the driver for your graphics board below if you
-	  are compiling a kernel for a non-x86 architecture.
-
-	  If you are compiling for the x86 architecture, you can say Y if you
-	  want to play with it, but it is not essential. Please note that
-	  running graphical applications that directly touch the hardware
-	  (e.g. an accelerated X server) and that are not frame buffer
-	  device-aware may cause unexpected results. If unsure, say N.
-
 config HAVE_STD_PC_SERIAL_PORT
 	bool
 
diff --git a/arch/mips/kernel/irixsig.c b/arch/mips/kernel/irixsig.c
index 3f956f809fa..40244782a8e 100644
--- a/arch/mips/kernel/irixsig.c
+++ b/arch/mips/kernel/irixsig.c
@@ -178,7 +178,7 @@ asmlinkage int do_irix_signal(sigset_t *oldset, struct pt_regs *regs)
 	if (!user_mode(regs))
 		return 1;
 
-	if (try_to_freeze(0))
+	if (try_to_freeze())
 		goto no_signal;
 
 	if (!oldset)
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 1f3b19124c0..c1a69cf232f 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -774,7 +774,7 @@ int do_signal32(sigset_t *oldset, struct pt_regs *regs)
 	if (!user_mode(regs))
 		return 1;
 
-	if (try_to_freeze(0))
+	if (try_to_freeze())
 		goto no_signal;
 
 	if (!oldset)
diff --git a/arch/mips/vr41xx/common/Makefile b/arch/mips/vr41xx/common/Makefile
index 92c11e9bbb3..fa98ef3855b 100644
--- a/arch/mips/vr41xx/common/Makefile
+++ b/arch/mips/vr41xx/common/Makefile
@@ -2,7 +2,7 @@
 # Makefile for common code of the NEC VR4100 series.
 #
 
-obj-y				+= bcu.o cmu.o giu.o icu.o init.o int-handler.o pmu.o
+obj-y				+= bcu.o cmu.o icu.o init.o int-handler.o pmu.o
 obj-$(CONFIG_VRC4173)		+= vrc4173.o
 
 EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/vr41xx/common/giu.c b/arch/mips/vr41xx/common/giu.c
deleted file mode 100644
index 9c6b21a79e8..00000000000
--- a/arch/mips/vr41xx/common/giu.c
+++ /dev/null
@@ -1,455 +0,0 @@
-/*
- *  giu.c, General-purpose I/O Unit Interrupt routines for NEC VR4100 series.
- *
- *  Copyright (C) 2002 MontaVista Software Inc.
- *    Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
- *  Copyright (C) 2003-2004  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
- *  Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/*
- * Changes:
- *  MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
- *  - New creation, NEC VR4111, VR4121, VR4122 and VR4131 are supported.
- *
- *  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
- *  - Added support for NEC VR4133.
- *  - Removed board_irq_init.
- */
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/smp.h>
-#include <linux/types.h>
-
-#include <asm/cpu.h>
-#include <asm/io.h>
-#include <asm/vr41xx/vr41xx.h>
-
-#define GIUIOSELL_TYPE1	KSEG1ADDR(0x0b000100)
-#define GIUIOSELL_TYPE2	KSEG1ADDR(0x0f000140)
-
-#define GIUIOSELL	0x00
-#define GIUIOSELH	0x02
-#define GIUINTSTATL	0x08
-#define GIUINTSTATH	0x0a
-#define GIUINTENL	0x0c
-#define GIUINTENH	0x0e
-#define GIUINTTYPL	0x10
-#define GIUINTTYPH	0x12
-#define GIUINTALSELL	0x14
-#define GIUINTALSELH	0x16
-#define GIUINTHTSELL	0x18
-#define GIUINTHTSELH	0x1a
-#define GIUFEDGEINHL	0x20
-#define GIUFEDGEINHH	0x22
-#define GIUREDGEINHL	0x24
-#define GIUREDGEINHH	0x26
-
-static uint32_t giu_base;
-
-static struct irqaction giu_cascade = {
-	.handler	= no_action,
-	.mask		= CPU_MASK_NONE,
-	.name		= "cascade",
-};
-
-#define read_giuint(offset)		readw(giu_base + (offset))
-#define write_giuint(val, offset)	writew((val), giu_base + (offset))
-
-#define GIUINT_HIGH_OFFSET	16
-
-static inline uint16_t set_giuint(uint8_t offset, uint16_t set)
-{
-	uint16_t res;
-
-	res = read_giuint(offset);
-	res |= set;
-	write_giuint(res, offset);
-
-	return res;
-}
-
-static inline uint16_t clear_giuint(uint8_t offset, uint16_t clear)
-{
-	uint16_t res;
-
-	res = read_giuint(offset);
-	res &= ~clear;
-	write_giuint(res, offset);
-
-	return res;
-}
-
-static unsigned int startup_giuint_low_irq(unsigned int irq)
-{
-	unsigned int pin;
-
-	pin = GIU_IRQ_TO_PIN(irq);
-	write_giuint((uint16_t)1 << pin, GIUINTSTATL);
-	set_giuint(GIUINTENL, (uint16_t)1 << pin);
-
-	return 0;
-}
-
-static void shutdown_giuint_low_irq(unsigned int irq)
-{
-	clear_giuint(GIUINTENL, (uint16_t)1 << GIU_IRQ_TO_PIN(irq));
-}
-
-static void enable_giuint_low_irq(unsigned int irq)
-{
-	set_giuint(GIUINTENL, (uint16_t)1 << GIU_IRQ_TO_PIN(irq));
-}
-
-#define disable_giuint_low_irq	shutdown_giuint_low_irq
-
-static void ack_giuint_low_irq(unsigned int irq)
-{
-	unsigned int pin;
-
-	pin = GIU_IRQ_TO_PIN(irq);
-	clear_giuint(GIUINTENL, (uint16_t)1 << pin);
-	write_giuint((uint16_t)1 << pin, GIUINTSTATL);
-}
-
-static void end_giuint_low_irq(unsigned int irq)
-{
-	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-		set_giuint(GIUINTENL, (uint16_t)1 << GIU_IRQ_TO_PIN(irq));
-}
-
-static struct hw_interrupt_type giuint_low_irq_type = {
-	.typename	= "GIUINTL",
-	.startup	= startup_giuint_low_irq,
-	.shutdown	= shutdown_giuint_low_irq,
-	.enable		= enable_giuint_low_irq,
-	.disable	= disable_giuint_low_irq,
-	.ack		= ack_giuint_low_irq,
-	.end		= end_giuint_low_irq,
-};
-
-static unsigned int startup_giuint_high_irq(unsigned int irq)
-{
-	unsigned int pin;
-
-	pin = GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET);
-	write_giuint((uint16_t)1 << pin, GIUINTSTATH);
-	set_giuint(GIUINTENH, (uint16_t)1 << pin);
-
-	return 0;
-}
-
-static void shutdown_giuint_high_irq(unsigned int irq)
-{
-	clear_giuint(GIUINTENH, (uint16_t)1 << GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET));
-}
-
-static void enable_giuint_high_irq(unsigned int irq)
-{
-	set_giuint(GIUINTENH, (uint16_t)1 << GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET));
-}
-
-#define disable_giuint_high_irq	shutdown_giuint_high_irq
-
-static void ack_giuint_high_irq(unsigned int irq)
-{
-	unsigned int pin;
-
-	pin = GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET);
-	clear_giuint(GIUINTENH, (uint16_t)1 << pin);
-	write_giuint((uint16_t)1 << pin, GIUINTSTATH);
-}
-
-static void end_giuint_high_irq(unsigned int irq)
-{
-	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-		set_giuint(GIUINTENH, (uint16_t)1 << GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET));
-}
-
-static struct hw_interrupt_type giuint_high_irq_type = {
-	.typename	= "GIUINTH",
-	.startup	= startup_giuint_high_irq,
-	.shutdown	= shutdown_giuint_high_irq,
-	.enable		= enable_giuint_high_irq,
-	.disable	= disable_giuint_high_irq,
-	.ack		= ack_giuint_high_irq,
-	.end		= end_giuint_high_irq,
-};
-
-void __init init_vr41xx_giuint_irq(void)
-{
-	int i;
-
-	for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
-		if (i < (GIU_IRQ_BASE + GIUINT_HIGH_OFFSET))
-			irq_desc[i].handler = &giuint_low_irq_type;
-		else
-			irq_desc[i].handler = &giuint_high_irq_type;
-	}
-
-	setup_irq(GIUINT_CASCADE_IRQ, &giu_cascade);
-}
-
-void vr41xx_set_irq_trigger(int pin, int trigger, int hold)
-{
-	uint16_t mask;
-
-	if (pin < GIUINT_HIGH_OFFSET) {
-		mask = (uint16_t)1 << pin;
-		if (trigger != TRIGGER_LEVEL) {
-        		set_giuint(GIUINTTYPL, mask);
-			if (hold == SIGNAL_HOLD)
-				set_giuint(GIUINTHTSELL, mask);
-			else
-				clear_giuint(GIUINTHTSELL, mask);
-			if (current_cpu_data.cputype == CPU_VR4133) {
-				switch (trigger) {
-				case TRIGGER_EDGE_FALLING:
-					set_giuint(GIUFEDGEINHL, mask);
-					clear_giuint(GIUREDGEINHL, mask);
-					break;
-				case TRIGGER_EDGE_RISING:
-					clear_giuint(GIUFEDGEINHL, mask);
-					set_giuint(GIUREDGEINHL, mask);
-					break;
-				default:
-					set_giuint(GIUFEDGEINHL, mask);
-					set_giuint(GIUREDGEINHL, mask);
-					break;
-				}
-			}
-		} else {
-			clear_giuint(GIUINTTYPL, mask);
-			clear_giuint(GIUINTHTSELL, mask);
-		}
-		write_giuint(mask, GIUINTSTATL);
-	} else {
-		mask = (uint16_t)1 << (pin - GIUINT_HIGH_OFFSET);
-		if (trigger != TRIGGER_LEVEL) {
-			set_giuint(GIUINTTYPH, mask);
-			if (hold == SIGNAL_HOLD)
-				set_giuint(GIUINTHTSELH, mask);
-			else
-				clear_giuint(GIUINTHTSELH, mask);
-			if (current_cpu_data.cputype == CPU_VR4133) {
-				switch (trigger) {
-				case TRIGGER_EDGE_FALLING:
-					set_giuint(GIUFEDGEINHH, mask);
-					clear_giuint(GIUREDGEINHH, mask);
-					break;
-				case TRIGGER_EDGE_RISING:
-					clear_giuint(GIUFEDGEINHH, mask);
-					set_giuint(GIUREDGEINHH, mask);
-					break;
-				default:
-					set_giuint(GIUFEDGEINHH, mask);
-					set_giuint(GIUREDGEINHH, mask);
-					break;
-				}
-			}
-		} else {
-			clear_giuint(GIUINTTYPH, mask);
-			clear_giuint(GIUINTHTSELH, mask);
-		}
-		write_giuint(mask, GIUINTSTATH);
-	}
-}
-
-EXPORT_SYMBOL(vr41xx_set_irq_trigger);
-
-void vr41xx_set_irq_level(int pin, int level)
-{
-	uint16_t mask;
-
-	if (pin < GIUINT_HIGH_OFFSET) {
-		mask = (uint16_t)1 << pin;
-		if (level == LEVEL_HIGH)
-			set_giuint(GIUINTALSELL, mask);
-		else
-			clear_giuint(GIUINTALSELL, mask);
-		write_giuint(mask, GIUINTSTATL);
-	} else {
-		mask = (uint16_t)1 << (pin - GIUINT_HIGH_OFFSET);
-		if (level == LEVEL_HIGH)
-			set_giuint(GIUINTALSELH, mask);
-		else
-			clear_giuint(GIUINTALSELH, mask);
-		write_giuint(mask, GIUINTSTATH);
-	}
-}
-
-EXPORT_SYMBOL(vr41xx_set_irq_level);
-
-#define GIUINT_NR_IRQS		32
-
-enum {
-	GIUINT_NO_CASCADE,
-	GIUINT_CASCADE
-};
-
-struct vr41xx_giuint_cascade {
-	unsigned int flag;
-	int (*get_irq_number)(int irq);
-};
-
-static struct vr41xx_giuint_cascade giuint_cascade[GIUINT_NR_IRQS];
-
-static int no_irq_number(int irq)
-{
-	return -EINVAL;
-}
-
-int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq))
-{
-	unsigned int pin;
-	int retval;
-
-	if (irq < GIU_IRQ(0) || irq > GIU_IRQ(31))
-		return -EINVAL;
-
-	if(!get_irq_number)
-		return -EINVAL;
-
-	pin = GIU_IRQ_TO_PIN(irq);
-	giuint_cascade[pin].flag = GIUINT_CASCADE;
-	giuint_cascade[pin].get_irq_number = get_irq_number;
-
-	retval = setup_irq(irq, &giu_cascade);
-	if (retval != 0) {
-		giuint_cascade[pin].flag = GIUINT_NO_CASCADE;
-		giuint_cascade[pin].get_irq_number = no_irq_number;
-	}
-
-	return retval;
-}
-
-EXPORT_SYMBOL(vr41xx_cascade_irq);
-
-static inline int get_irq_pin_number(void)
-{
-	uint16_t pendl, pendh, maskl, maskh;
-	int i;
-
-	pendl = read_giuint(GIUINTSTATL);
-	pendh = read_giuint(GIUINTSTATH);
-	maskl = read_giuint(GIUINTENL);
-	maskh = read_giuint(GIUINTENH);
-
-	maskl &= pendl;
-	maskh &= pendh;
-
-	if (maskl) {
-		for (i = 0; i < 16; i++) {
-			if (maskl & ((uint16_t)1 << i))
-				return i;
-		}
-	} else if (maskh) {
-		for (i = 0; i < 16; i++) {
-			if (maskh & ((uint16_t)1 << i))
-				return i + GIUINT_HIGH_OFFSET;
-		}
-	}
-
-	printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
-	       maskl, pendl, maskh, pendh);
-
-	atomic_inc(&irq_err_count);
-
-	return -1;
-}
-
-static inline void ack_giuint_irq(int pin)
-{
-	if (pin < GIUINT_HIGH_OFFSET) {
-		clear_giuint(GIUINTENL, (uint16_t)1 << pin);
-		write_giuint((uint16_t)1 << pin, GIUINTSTATL);
-	} else {
-		pin -= GIUINT_HIGH_OFFSET;
-		clear_giuint(GIUINTENH, (uint16_t)1 << pin);
-		write_giuint((uint16_t)1 << pin, GIUINTSTATH);
-	}
-}
-
-static inline void end_giuint_irq(int pin)
-{
-	if (pin < GIUINT_HIGH_OFFSET)
-		set_giuint(GIUINTENL, (uint16_t)1 << pin);
-	else
-		set_giuint(GIUINTENH, (uint16_t)1 << (pin - GIUINT_HIGH_OFFSET));
-}
-
-void giuint_irq_dispatch(struct pt_regs *regs)
-{
-	struct vr41xx_giuint_cascade *cascade;
-	unsigned int giuint_irq;
-	int pin;
-
-	pin = get_irq_pin_number();
-	if (pin < 0)
-		return;
-
-	disable_irq(GIUINT_CASCADE_IRQ);
-
-	cascade = &giuint_cascade[pin];
-	giuint_irq = GIU_IRQ(pin);
-	if (cascade->flag == GIUINT_CASCADE) {
-		int irq = cascade->get_irq_number(giuint_irq);
-		ack_giuint_irq(pin);
-		if (irq >= 0)
-			do_IRQ(irq, regs);
-		end_giuint_irq(pin);
-	} else {
-		do_IRQ(giuint_irq, regs);
-	}
-
-	enable_irq(GIUINT_CASCADE_IRQ);
-}
-
-static int __init vr41xx_giu_init(void)
-{
-	int i;
-
-	switch (current_cpu_data.cputype) {
-	case CPU_VR4111:
-	case CPU_VR4121:
-		giu_base = GIUIOSELL_TYPE1;
-		break;
-	case CPU_VR4122:
-	case CPU_VR4131:
-	case CPU_VR4133:
-		giu_base = GIUIOSELL_TYPE2;
-		break;
-	default:
-		printk(KERN_ERR "GIU: Unexpected CPU of NEC VR4100 series\n");
-		return -EINVAL;
-	}
-
-	for (i = 0; i < GIUINT_NR_IRQS; i++) {
-		if (i < GIUINT_HIGH_OFFSET)
-			clear_giuint(GIUINTENL, (uint16_t)1 << i);
-		else
-			clear_giuint(GIUINTENH, (uint16_t)1 << (i - GIUINT_HIGH_OFFSET));
-		giuint_cascade[i].flag = GIUINT_NO_CASCADE;
-		giuint_cascade[i].get_irq_number = no_irq_number;
-	}
-
-	return 0;
-}
-
-early_initcall(vr41xx_giu_init);
diff --git a/arch/parisc/kernel/pci.c b/arch/parisc/kernel/pci.c
index 3cb08a4a513..e6a891a0cad 100644
--- a/arch/parisc/kernel/pci.c
+++ b/arch/parisc/kernel/pci.c
@@ -255,8 +255,26 @@ void __devinit pcibios_resource_to_bus(struct pci_dev *dev,
 	pcibios_link_hba_resources(&hba->lmmio_space, bus->resource[1]);
 }
 
+void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+			      struct pci_bus_region *region)
+{
+	struct pci_bus *bus = dev->bus;
+	struct pci_hba_data *hba = HBA_DATA(bus->bridge->platform_data);
+
+	if (res->flags & IORESOURCE_MEM) {
+		res->start = PCI_HOST_ADDR(hba, region->start);
+		res->end = PCI_HOST_ADDR(hba, region->end);
+	}
+
+	if (res->flags & IORESOURCE_IO) {
+		res->start = region->start;
+		res->end = region->end;
+	}
+}
+
 #ifdef CONFIG_HOTPLUG
 EXPORT_SYMBOL(pcibios_resource_to_bus);
+EXPORT_SYMBOL(pcibios_bus_to_resource);
 #endif
 
 /*
diff --git a/arch/parisc/mm/fault.c b/arch/parisc/mm/fault.c
index eaa701479f5..0ad945d4c0a 100644
--- a/arch/parisc/mm/fault.c
+++ b/arch/parisc/mm/fault.c
@@ -178,17 +178,17 @@ good_area:
 	 */
 
 	switch (handle_mm_fault(mm, vma, address, (acc_type & VM_WRITE) != 0)) {
-	      case 1:
+	      case VM_FAULT_MINOR:
 		++current->min_flt;
 		break;
-	      case 2:
+	      case VM_FAULT_MAJOR:
 		++current->maj_flt;
 		break;
-	      case 0:
+	      case VM_FAULT_SIGBUS:
 		/*
-		 * We ran out of memory, or some other thing happened
-		 * to us that made us unable to handle the page fault
-		 * gracefully.
+		 * We hit a hared mapping outside of the file, or some
+		 * other thing happened to us that made us unable to
+		 * handle the page fault gracefully.
 		 */
 		goto bad_area;
 	      default:
diff --git a/arch/ppc/8xx_io/Kconfig b/arch/ppc/8xx_io/Kconfig
index 9e2227ec3b3..57dacf97853 100644
--- a/arch/ppc/8xx_io/Kconfig
+++ b/arch/ppc/8xx_io/Kconfig
@@ -69,9 +69,9 @@ config FEC_QS6612
 	
 config ENET_BIG_BUFFERS
 	bool "Use Big CPM Ethernet Buffers"
-	depends on NET_ETHERNET
+	depends on SCC_ENET || FEC_ENET
 	help
-	  Allocate large buffers for MPC8xx Etherenet.  Increases throughput
+	  Allocate large buffers for MPC8xx Ethernet. Increases throughput
 	  and decreases the likelihood of dropped packets, but costs memory.
 
 config HTDMSOUND
diff --git a/arch/ppc/8xx_io/commproc.c b/arch/ppc/8xx_io/commproc.c
index 0cc2e7a9cb1..11726e2a4ec 100644
--- a/arch/ppc/8xx_io/commproc.c
+++ b/arch/ppc/8xx_io/commproc.c
@@ -39,8 +39,6 @@
 #include <asm/tlbflush.h>
 #include <asm/rheap.h>
 
-extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep);
-
 static void m8xx_cpm_dpinit(void);
 static	uint	host_buffer;	/* One page of host buffer */
 static	uint	host_end;	/* end + 1 */
@@ -108,14 +106,11 @@ struct hw_interrupt_type cpm_pic = {
 	.end		= cpm_eoi,
 };
 
-extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
-
 void
-m8xx_cpm_reset(uint bootpage)
+m8xx_cpm_reset(void)
 {
 	volatile immap_t	 *imp;
 	volatile cpm8xx_t	*commproc;
-	pte_t *pte;
 
 	imp = (immap_t *)IMAP_ADDR;
 	commproc = (cpm8xx_t *)&imp->im_cpm;
@@ -143,17 +138,6 @@ m8xx_cpm_reset(uint bootpage)
 	/* Reclaim the DP memory for our use. */
 	m8xx_cpm_dpinit();
 
-	/* get the PTE for the bootpage */
-	if (!get_pteptr(&init_mm, bootpage, &pte))
-	       panic("get_pteptr failed\n");
-																							
-	/* and make it uncachable */
-	pte_val(*pte) |= _PAGE_NO_CACHE;
-	_tlbie(bootpage);
-
-	host_buffer = bootpage;
-	host_end = host_buffer + PAGE_SIZE;
-
 	/* Tell everyone where the comm processor resides.
 	*/
 	cpmp = (cpm8xx_t *)commproc;
@@ -384,8 +368,6 @@ static rh_info_t cpm_dpmem_info;
 
 void m8xx_cpm_dpinit(void)
 {
-	cpm8xx_t *cp = &((immap_t *)IMAP_ADDR)->im_cpm;
-
 	spin_lock_init(&cpm_dpmem_lock);
 
 	/* Initialize the info header */
diff --git a/arch/ppc/8xx_io/fec.c b/arch/ppc/8xx_io/fec.c
index 0730392dcc2..62f68d6181c 100644
--- a/arch/ppc/8xx_io/fec.c
+++ b/arch/ppc/8xx_io/fec.c
@@ -173,7 +173,7 @@ struct fec_enet_private {
 	uint	phy_status;
 	uint	phy_speed;
 	phy_info_t	*phy;
-	struct tq_struct phy_task;
+	struct work_struct phy_task;
 
 	uint	sequence_done;
 
@@ -199,7 +199,8 @@ static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
 #ifdef	CONFIG_USE_MDIO
 static void fec_enet_mii(struct net_device *dev);
 #endif	/* CONFIG_USE_MDIO */
-static void fec_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs);
+static irqreturn_t fec_enet_interrupt(int irq, void * dev_id,
+		       					struct pt_regs * regs);
 #ifdef CONFIG_FEC_PACKETHOOK
 static void  fec_enet_tx(struct net_device *dev, __u32 regval);
 static void  fec_enet_rx(struct net_device *dev, __u32 regval);
@@ -471,7 +472,7 @@ fec_timeout(struct net_device *dev)
 /* The interrupt handler.
  * This is called from the MPC core interrupt.
  */
-static	void
+static	irqreturn_t
 fec_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
 {
 	struct	net_device *dev = dev_id;
@@ -525,6 +526,7 @@ printk("%s[%d] %s: unexpected FEC_ENET_MII event\n", __FILE__,__LINE__,__FUNCTIO
 		}
 
 	}
+	return IRQ_RETVAL(IRQ_HANDLED);
 }
 
 
@@ -1263,8 +1265,9 @@ static void mii_display_status(struct net_device *dev)
 	printk(".\n");
 }
 
-static void mii_display_config(struct net_device *dev)
+static void mii_display_config(void *priv)
 {
+	struct net_device *dev = (struct net_device *)priv;
 	struct fec_enet_private *fep = dev->priv;
 	volatile uint *s = &(fep->phy_status);
 
@@ -1294,8 +1297,9 @@ static void mii_display_config(struct net_device *dev)
 	fep->sequence_done = 1;
 }
 
-static void mii_relink(struct net_device *dev)
+static void mii_relink(void *priv)
 {
+	struct net_device *dev = (struct net_device *)priv;
 	struct fec_enet_private *fep = dev->priv;
 	int duplex;
 
@@ -1323,18 +1327,16 @@ static void mii_queue_relink(uint mii_reg, struct net_device *dev)
 {
 	struct fec_enet_private *fep = dev->priv;
 
-	fep->phy_task.routine = (void *)mii_relink;
-	fep->phy_task.data = dev;
-	schedule_task(&fep->phy_task);
+	INIT_WORK(&fep->phy_task, mii_relink, (void *)dev);
+	schedule_work(&fep->phy_task);
 }
 
 static void mii_queue_config(uint mii_reg, struct net_device *dev)
 {
 	struct fec_enet_private *fep = dev->priv;
 
-	fep->phy_task.routine = (void *)mii_display_config;
-	fep->phy_task.data = dev;
-	schedule_task(&fep->phy_task);
+	INIT_WORK(&fep->phy_task, mii_display_config, (void *)dev);
+	schedule_work(&fep->phy_task);
 }
 
 
@@ -1403,11 +1405,11 @@ mii_discover_phy(uint mii_reg, struct net_device *dev)
 
 /* This interrupt occurs when the PHY detects a link change.
 */
-static void
+static
 #ifdef CONFIG_RPXCLASSIC
-mii_link_interrupt(void *dev_id)
+void mii_link_interrupt(void *dev_id)
 #else
-mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs)
+irqreturn_t mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs)
 #endif
 {
 #ifdef	CONFIG_USE_MDIO
@@ -1440,6 +1442,9 @@ mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs)
 printk("%s[%d] %s: unexpected Link interrupt\n", __FILE__,__LINE__,__FUNCTION__);
 #endif	/* CONFIG_USE_MDIO */
 
+#ifndef CONFIG_RPXCLASSIC
+	return IRQ_RETVAL(IRQ_HANDLED);
+#endif	/* CONFIG_RPXCLASSIC */
 }
 
 static int
@@ -1575,7 +1580,7 @@ static int __init fec_enet_init(void)
 	struct fec_enet_private *fep;
 	int i, j, k, err;
 	unsigned char	*eap, *iap, *ba;
-	unsigned long	mem_addr;
+	dma_addr_t	mem_addr;
 	volatile	cbd_t	*bdp;
 	cbd_t		*cbd_base;
 	volatile	immap_t	*immap;
@@ -1640,7 +1645,8 @@ static int __init fec_enet_init(void)
 		printk("FEC initialization failed.\n");
 		return 1;
 	}
-	cbd_base = (cbd_t *)consistent_alloc(GFP_KERNEL, PAGE_SIZE, &mem_addr);
+	cbd_base = (cbd_t *)dma_alloc_coherent(dev->class_dev.dev, PAGE_SIZE,
+					       &mem_addr, GFP_KERNEL);
 
 	/* Set receive and transmit descriptor base.
 	*/
@@ -1657,7 +1663,10 @@ static int __init fec_enet_init(void)
 
 		/* Allocate a page.
 		*/
-		ba = (unsigned char *)consistent_alloc(GFP_KERNEL, PAGE_SIZE, &mem_addr);
+		ba = (unsigned char *)dma_alloc_coherent(dev->class_dev.dev,
+							 PAGE_SIZE,
+							 &mem_addr,
+							 GFP_KERNEL);
 		/* BUG: no check for failure */
 
 		/* Initialize the BD for every fragment in the page.
diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig
index b833cbcd77f..f6db3b385fe 100644
--- a/arch/ppc/Kconfig
+++ b/arch/ppc/Kconfig
@@ -85,7 +85,6 @@ config POWER4
 	bool "POWER4 and 970 (G5)"
 
 config 8xx
-	depends on BROKEN
 	bool "8xx"
 
 config E200
@@ -559,6 +558,7 @@ config PPC_MULTIPLATFORM
 
 config APUS
 	bool "Amiga-APUS"
+	depends on BROKEN
 	help
 	  Select APUS if configuring for a PowerUP Amiga.
 	  More information is available at:
@@ -648,6 +648,7 @@ config PAL4
 
 config GEMINI
 	bool "Synergy-Gemini"
+	depends on BROKEN
 	help
 	  Select Gemini if configuring for a Synergy Microsystems' Gemini
 	  series Single Board Computer.  More information is available at:
@@ -878,6 +879,13 @@ config MPC10X_STORE_GATHERING
 	bool "Enable MPC10x store gathering"
 	depends on MPC10X_BRIDGE
 
+config SANDPOINT_ENABLE_UART1
+	bool "Enable DUART mode on Sandpoint"
+	depends on SANDPOINT
+	help
+	  If this option is enabled then the MPC824x processor will run
+	  in DUART mode instead of UART mode.
+
 config CPC710_DATA_GATHERING
 	bool "Enable CPC710 data gathering"
 	depends on K2
@@ -935,19 +943,11 @@ config NR_CPUS
 	depends on SMP
 	default "4"
 
-config PREEMPT
-	bool "Preemptible Kernel"
-	help
-	  This option reduces the latency of the kernel when reacting to
-	  real-time or interactive events by allowing a low priority process to
-	  be preempted even if it is in kernel mode executing a system call.
-
-	  Say Y here if you are building a kernel for a desktop, embedded
-	  or real-time system.  Say N if you are unsure.
-
 config HIGHMEM
 	bool "High memory support"
 
+source kernel/Kconfig.hz
+source kernel/Kconfig.preempt
 source "mm/Kconfig"
 
 source "fs/Kconfig.binfmt"
diff --git a/arch/ppc/boot/simple/Makefile b/arch/ppc/boot/simple/Makefile
index 991b4cbb83c..d4dc4fa7964 100644
--- a/arch/ppc/boot/simple/Makefile
+++ b/arch/ppc/boot/simple/Makefile
@@ -61,6 +61,12 @@ zimageinitrd-$(CONFIG_IBM_OPENBIOS)	:= zImage.initrd-TREE
          end-$(CONFIG_EMBEDDEDBOOT)	:= embedded
         misc-$(CONFIG_EMBEDDEDBOOT)	:= misc-embedded.o
 
+      zimage-$(CONFIG_BAMBOO)		:= zImage-TREE
+zimageinitrd-$(CONFIG_BAMBOO)		:= zImage.initrd-TREE
+         end-$(CONFIG_BAMBOO)		:= bamboo
+  entrypoint-$(CONFIG_BAMBOO)		:= 0x01000000
+     extra.o-$(CONFIG_BAMBOO)		:= pibs.o
+
       zimage-$(CONFIG_EBONY)		:= zImage-TREE
 zimageinitrd-$(CONFIG_EBONY)		:= zImage.initrd-TREE
          end-$(CONFIG_EBONY)		:= ebony
diff --git a/arch/ppc/boot/simple/pibs.c b/arch/ppc/boot/simple/pibs.c
index 1348740e503..67222d57c34 100644
--- a/arch/ppc/boot/simple/pibs.c
+++ b/arch/ppc/boot/simple/pibs.c
@@ -91,9 +91,11 @@ load_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
 
 	mac64 = simple_strtoull((char *)PIBS_MAC_BASE, 0, 16);
 	memcpy(hold_residual->bi_enetaddr, (char *)&mac64+2, 6);
-#ifdef CONFIG_440GX
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP)
 	mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET), 0, 16);
 	memcpy(hold_residual->bi_enet1addr, (char *)&mac64+2, 6);
+#endif
+#ifdef CONFIG_440GX
 	mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*2), 0, 16);
 	memcpy(hold_residual->bi_enet2addr, (char *)&mac64+2, 6);
 	mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*3), 0, 16);
diff --git a/arch/ppc/configs/bamboo_defconfig b/arch/ppc/configs/bamboo_defconfig
new file mode 100644
index 00000000000..0ba4e70d50b
--- /dev/null
+++ b/arch/ppc/configs/bamboo_defconfig
@@ -0,0 +1,943 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.12
+# Tue Jun 28 15:24:25 2005
+#
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_HAVE_DEC_LOCK=y
+CONFIG_PPC=y
+CONFIG_PPC32=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_KOBJECT_UEVENT=y
+# CONFIG_IKCONFIG is not set
+CONFIG_EMBEDDED=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Processor
+#
+# CONFIG_6xx is not set
+# CONFIG_40x is not set
+CONFIG_44x=y
+# CONFIG_POWER3 is not set
+# CONFIG_POWER4 is not set
+# CONFIG_8xx is not set
+# CONFIG_E200 is not set
+# CONFIG_E500 is not set
+CONFIG_PPC_FPU=y
+CONFIG_BOOKE=y
+CONFIG_PTE_64BIT=y
+CONFIG_PHYS_64BIT=y
+# CONFIG_MATH_EMULATION is not set
+# CONFIG_KEXEC is not set
+# CONFIG_CPU_FREQ is not set
+CONFIG_4xx=y
+
+#
+# IBM 4xx options
+#
+CONFIG_BAMBOO=y
+# CONFIG_EBONY is not set
+# CONFIG_LUAN is not set
+# CONFIG_OCOTEA is not set
+CONFIG_440EP=y
+CONFIG_440=y
+CONFIG_IBM440EP_ERR42=y
+CONFIG_IBM_OCP=y
+# CONFIG_PPC4xx_DMA is not set
+CONFIG_PPC_GEN550=y
+# CONFIG_PM is not set
+CONFIG_NOT_COHERENT_CACHE=y
+
+#
+# Platform options
+#
+# CONFIG_PC_KEYBOARD is not set
+# CONFIG_SMP is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="ip=on"
+CONFIG_SECCOMP=y
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PCI_LEGACY_PROC is not set
+# CONFIG_PCI_NAMES is not set
+# CONFIG_PCI_DEBUG is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0x80000000
+CONFIG_CONSISTENT_START=0xff100000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_BOOT_LOAD=0x01000000
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_LBD is not set
+# CONFIG_CDROM_PKTCDVD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=y
+CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_IDEPCI_SHARE_IRQ is not set
+# CONFIG_BLK_DEV_OFFBOARD is not set
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_SL82C105 is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
+# CONFIG_IDEDMA_PCI_AUTO is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+CONFIG_BLK_DEV_CMD64X=y
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_IDE_ARM is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_IVB is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+# CONFIG_BLK_DEV_SD is not set
+CONFIG_CHR_DEV_ST=y
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transport Attributes
+#
+CONFIG_SCSI_SPI_ATTRS=y
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+CONFIG_SCSI_SYM53C8XX_2=y
+CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
+CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
+CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
+# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_FC is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+CONFIG_SCSI_QLA2XXX=y
+# CONFIG_SCSI_QLA21XX is not set
+# CONFIG_SCSI_QLA22XX is not set
+# CONFIG_SCSI_QLA2300 is not set
+# CONFIG_SCSI_QLA2322 is not set
+# CONFIG_SCSI_QLA6312 is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+# CONFIG_FUSION_SPI is not set
+# CONFIG_FUSION_FC is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Macintosh device drivers
+#
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_IP_TCPDIAG=y
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+
+#
+# IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_CONNTRACK_MARK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_IBM_EMAC=y
+# CONFIG_IBM_EMAC_ERRMSG is not set
+CONFIG_IBM_EMAC_RXB=64
+CONFIG_IBM_EMAC_TXB=8
+CONFIG_IBM_EMAC_FGAP=8
+CONFIG_IBM_EMAC_SKBRES=0
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+CONFIG_EEPRO100=y
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+CONFIG_NATSEMI=y
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+CONFIG_E1000=y
+# CONFIG_E1000_NAPI is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PCIPS2 is not set
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_BLUETOOTH_TTY is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
+#
+# CONFIG_USB_STORAGE is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+# CONFIG_USB_AIPTEK is not set
+# CONFIG_USB_WACOM is not set
+# CONFIG_USB_ACECAD is not set
+# CONFIG_USB_KBTAB is not set
+# CONFIG_USB_POWERMATE is not set
+# CONFIG_USB_MTOUCH is not set
+# CONFIG_USB_ITMTOUCH is not set
+# CONFIG_USB_EGALAX is not set
+# CONFIG_USB_XPAD is not set
+# CONFIG_USB_ATI_REMOTE is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB Multimedia devices
+#
+# CONFIG_USB_DABUSB is not set
+
+#
+# Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+CONFIG_USB_PEGASUS=y
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGETKIT is not set
+# CONFIG_USB_PHIDGETSERVO is not set
+# CONFIG_USB_IDMOUSE is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# SN Devices
+#
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+
+#
+# XFS support
+#
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+# CONFIG_DEVPTS_FS_XATTR is not set
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_FS is not set
+# CONFIG_KGDB is not set
+# CONFIG_XMON is not set
+CONFIG_BDI_SWITCH=y
+# CONFIG_SERIAL_TEXT_DEBUG is not set
+CONFIG_PPC_OCP=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
diff --git a/arch/ppc/configs/common_defconfig b/arch/ppc/configs/common_defconfig
index 95ead3f1b1c..4d33bee23a8 100644
--- a/arch/ppc/configs/common_defconfig
+++ b/arch/ppc/configs/common_defconfig
@@ -1,15 +1,17 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.10-rc2
-# Thu Nov 18 08:22:35 2004
+# Linux kernel version: 2.6.13-rc3
+# Wed Jul 13 13:34:24 2005
 #
 CONFIG_MMU=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_HAVE_DEC_LOCK=y
 CONFIG_PPC=y
 CONFIG_PPC32=y
 CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
 
 #
 # Code maturity level options
@@ -17,6 +19,7 @@ CONFIG_GENERIC_NVRAM=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
 
 #
 # General setup
@@ -28,30 +31,33 @@ CONFIG_POSIX_MQUEUE=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 CONFIG_SYSCTL=y
 # CONFIG_AUDIT is not set
-CONFIG_LOG_BUF_SHIFT=14
 CONFIG_HOTPLUG=y
 CONFIG_KOBJECT_UEVENT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 # CONFIG_EMBEDDED is not set
 CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SHMEM=y
 CONFIG_CC_ALIGN_FUNCTIONS=0
 CONFIG_CC_ALIGN_LABELS=0
 CONFIG_CC_ALIGN_LOOPS=0
 CONFIG_CC_ALIGN_JUMPS=0
 # CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
 
 #
 # Loadable module support
 #
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
 CONFIG_OBSOLETE_MODPARM=y
 CONFIG_MODVERSIONS=y
 # CONFIG_MODULE_SRCVERSION_ALL is not set
@@ -66,22 +72,27 @@ CONFIG_6xx=y
 # CONFIG_POWER3 is not set
 # CONFIG_POWER4 is not set
 # CONFIG_8xx is not set
+# CONFIG_E200 is not set
 # CONFIG_E500 is not set
+CONFIG_PPC_FPU=y
 CONFIG_ALTIVEC=y
 CONFIG_TAU=y
 # CONFIG_TAU_INT is not set
 # CONFIG_TAU_AVERAGE is not set
+# CONFIG_KEXEC is not set
 CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
 # CONFIG_CPU_FREQ_DEBUG is not set
-CONFIG_CPU_FREQ_PROC_INTF=y
+CONFIG_CPU_FREQ_STAT=m
+CONFIG_CPU_FREQ_STAT_DETAILS=y
 CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
 # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
 CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_USERSPACE=m
+CONFIG_CPU_FREQ_GOV_ONDEMAND=m
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
 CONFIG_CPU_FREQ_PMAC=y
-CONFIG_CPU_FREQ_TABLE=y
 CONFIG_PPC601_SYNC_FIX=y
 CONFIG_PM=y
 CONFIG_PPC_STD_MMU=y
@@ -91,11 +102,15 @@ CONFIG_PPC_STD_MMU=y
 #
 CONFIG_PPC_MULTIPLATFORM=y
 # CONFIG_APUS is not set
+# CONFIG_KATANA is not set
 # CONFIG_WILLOW is not set
+# CONFIG_CPCI690 is not set
 # CONFIG_PCORE is not set
 # CONFIG_POWERPMC250 is not set
-# CONFIG_EV64260 is not set
+# CONFIG_CHESTNUT is not set
 # CONFIG_SPRUCE is not set
+# CONFIG_HDPU is not set
+# CONFIG_EV64260 is not set
 # CONFIG_LOPEC is not set
 # CONFIG_MCPN765 is not set
 # CONFIG_MVME5100 is not set
@@ -103,6 +118,7 @@ CONFIG_PPC_MULTIPLATFORM=y
 # CONFIG_PRPMC750 is not set
 # CONFIG_PRPMC800 is not set
 # CONFIG_SANDPOINT is not set
+# CONFIG_RADSTONE_PPC7D is not set
 # CONFIG_ADIR is not set
 # CONFIG_K2 is not set
 # CONFIG_PAL4 is not set
@@ -113,22 +129,40 @@ CONFIG_PPC_MULTIPLATFORM=y
 # CONFIG_RPX8260 is not set
 # CONFIG_TQM8260 is not set
 # CONFIG_ADS8272 is not set
+# CONFIG_PQ2FADS is not set
 # CONFIG_LITE5200 is not set
+# CONFIG_MPC834x_SYS is not set
 CONFIG_PPC_CHRP=y
 CONFIG_PPC_PMAC=y
 CONFIG_PPC_PREP=y
 CONFIG_PPC_OF=y
 CONFIG_PPCBUG_NVRAM=y
 # CONFIG_SMP is not set
-# CONFIG_PREEMPT is not set
 # CONFIG_HIGHMEM is not set
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_BINFMT_ELF=y
 CONFIG_BINFMT_MISC=m
 CONFIG_PROC_DEVICETREE=y
 CONFIG_PREP_RESIDUAL=y
 CONFIG_PROC_PREPRESIDUAL=y
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="console=ttyS0,9600 console=tty0 root=/dev/sda2"
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM_DEBUG is not set
+CONFIG_SOFTWARE_SUSPEND=y
+CONFIG_PM_STD_PARTITION=""
+# CONFIG_SECCOMP is not set
+CONFIG_ISA_DMA_API=y
 
 #
 # Bus options
@@ -137,18 +171,24 @@ CONFIG_ISA=y
 CONFIG_GENERIC_ISA_DMA=y
 CONFIG_PCI=y
 CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_LEGACY_PROC=y
-CONFIG_PCI_NAMES=y
+# CONFIG_PCI_LEGACY_PROC is not set
+# CONFIG_PCI_NAMES is not set
+# CONFIG_PCI_DEBUG is not set
 
 #
 # PCCARD (PCMCIA/CardBus) support
 #
-# CONFIG_PCCARD is not set
+CONFIG_PCCARD=m
+# CONFIG_PCMCIA_DEBUG is not set
+# CONFIG_PCMCIA is not set
+CONFIG_CARDBUS=y
 
 #
 # PC-card bridges
 #
+CONFIG_YENTA=m
 CONFIG_PCMCIA_PROBE=y
+CONFIG_PCCARD_NONSTATIC=m
 
 #
 # Advanced setup
@@ -165,6 +205,143 @@ CONFIG_TASK_SIZE=0x80000000
 CONFIG_BOOT_LOAD=0x00800000
 
 #
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_IP_TCPDIAG=y
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+
+#
+# IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_IP_NF_CONNTRACK=m
+# CONFIG_IP_NF_CT_ACCT is not set
+CONFIG_IP_NF_CONNTRACK_MARK=y
+# CONFIG_IP_NF_CT_PROTO_SCTP is not set
+CONFIG_IP_NF_FTP=m
+CONFIG_IP_NF_IRC=m
+CONFIG_IP_NF_TFTP=m
+CONFIG_IP_NF_AMANDA=m
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_LIMIT=m
+CONFIG_IP_NF_MATCH_IPRANGE=m
+CONFIG_IP_NF_MATCH_MAC=m
+CONFIG_IP_NF_MATCH_PKTTYPE=m
+CONFIG_IP_NF_MATCH_MARK=m
+CONFIG_IP_NF_MATCH_MULTIPORT=m
+CONFIG_IP_NF_MATCH_TOS=m
+CONFIG_IP_NF_MATCH_RECENT=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_DSCP=m
+CONFIG_IP_NF_MATCH_AH_ESP=m
+CONFIG_IP_NF_MATCH_LENGTH=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_MATCH_TCPMSS=m
+CONFIG_IP_NF_MATCH_HELPER=m
+CONFIG_IP_NF_MATCH_STATE=m
+CONFIG_IP_NF_MATCH_CONNTRACK=m
+CONFIG_IP_NF_MATCH_OWNER=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_REALM=m
+CONFIG_IP_NF_MATCH_SCTP=m
+CONFIG_IP_NF_MATCH_COMMENT=m
+CONFIG_IP_NF_MATCH_CONNMARK=m
+CONFIG_IP_NF_MATCH_HASHLIMIT=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_TARGET_TCPMSS=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_SAME=m
+CONFIG_IP_NF_NAT_SNMP_BASIC=m
+CONFIG_IP_NF_NAT_IRC=m
+CONFIG_IP_NF_NAT_FTP=m
+CONFIG_IP_NF_NAT_TFTP=m
+CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_TOS=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_DSCP=m
+CONFIG_IP_NF_TARGET_MARK=m
+CONFIG_IP_NF_TARGET_CLASSIFY=m
+CONFIG_IP_NF_TARGET_CONNMARK=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_TARGET_NOTRACK=m
+CONFIG_IP_NF_ARPTABLES=m
+# CONFIG_IP_NF_ARPFILTER is not set
+# CONFIG_IP_NF_ARP_MANGLE is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_CLS_ROUTE=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_RX is not set
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+
+#
 # Device Drivers
 #
 
@@ -173,7 +350,8 @@ CONFIG_BOOT_LOAD=0x00800000
 #
 # CONFIG_STANDALONE is not set
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
+CONFIG_FW_LOADER=m
+# CONFIG_DEBUG_DRIVER is not set
 
 #
 # Memory Technology Devices (MTD)
@@ -183,7 +361,13 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
 #
 # Parallel port support
 #
-# CONFIG_PARPORT is not set
+CONFIG_PARPORT=m
+CONFIG_PARPORT_PC=m
+CONFIG_PARPORT_SERIAL=m
+CONFIG_PARPORT_PC_FIFO=y
+CONFIG_PARPORT_PC_SUPERIO=y
+# CONFIG_PARPORT_GSC is not set
+CONFIG_PARPORT_1284=y
 
 #
 # Plug and Play support
@@ -194,18 +378,21 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
 # Block devices
 #
 CONFIG_BLK_DEV_FD=m
-# CONFIG_MAC_FLOPPY is not set
+CONFIG_MAC_FLOPPY=m
 # CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
 # CONFIG_BLK_CPQ_DA is not set
 # CONFIG_BLK_CPQ_CISS_DA is not set
 # CONFIG_BLK_DEV_DAC960 is not set
 # CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_SX8 is not set
 # CONFIG_BLK_DEV_UB is not set
 CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
@@ -219,6 +406,7 @@ CONFIG_IOSCHED_NOOP=y
 CONFIG_IOSCHED_AS=y
 CONFIG_IOSCHED_DEADLINE=y
 CONFIG_IOSCHED_CFQ=y
+# CONFIG_ATA_OVER_ETH is not set
 
 #
 # ATA/ATAPI/MFM/RLL support
@@ -247,7 +435,7 @@ CONFIG_IDEPCI_SHARE_IRQ=y
 # CONFIG_BLK_DEV_OFFBOARD is not set
 CONFIG_BLK_DEV_GENERIC=y
 # CONFIG_BLK_DEV_OPTI621 is not set
-CONFIG_BLK_DEV_SL82C105=y
+# CONFIG_BLK_DEV_SL82C105 is not set
 CONFIG_BLK_DEV_IDEDMA_PCI=y
 # CONFIG_BLK_DEV_IDEDMA_FORCED is not set
 CONFIG_IDEDMA_PCI_AUTO=y
@@ -264,6 +452,7 @@ CONFIG_BLK_DEV_CMD64X=y
 # CONFIG_BLK_DEV_HPT366 is not set
 # CONFIG_BLK_DEV_SC1200 is not set
 # CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT821X is not set
 # CONFIG_BLK_DEV_NS87415 is not set
 # CONFIG_BLK_DEV_PDC202XX_OLD is not set
 CONFIG_BLK_DEV_PDC202XX_NEW=y
@@ -299,19 +488,21 @@ CONFIG_CHR_DEV_ST=y
 CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
 
 #
 # Some SCSI devices (e.g. CD jukebox) support multiple LUNs
 #
 # CONFIG_SCSI_MULTI_LUN is not set
 CONFIG_SCSI_CONSTANTS=y
-# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_LOGGING=y
 
 #
 # SCSI Transport Attributes
 #
 CONFIG_SCSI_SPI_ATTRS=y
 # CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
 
 #
 # SCSI low-level drivers
@@ -340,7 +531,6 @@ CONFIG_SCSI_AIC7XXX_OLD=m
 # CONFIG_SCSI_DMX3191D is not set
 # CONFIG_SCSI_DTC3280 is not set
 # CONFIG_SCSI_EATA is not set
-# CONFIG_SCSI_EATA_PIO is not set
 # CONFIG_SCSI_FUTURE_DOMAIN is not set
 # CONFIG_SCSI_GDTH is not set
 # CONFIG_SCSI_GENERIC_NCR5380 is not set
@@ -348,6 +538,8 @@ CONFIG_SCSI_AIC7XXX_OLD=m
 # CONFIG_SCSI_IPS is not set
 # CONFIG_SCSI_INITIO is not set
 # CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_PPA is not set
+# CONFIG_SCSI_IMM is not set
 # CONFIG_SCSI_NCR53C406A is not set
 CONFIG_SCSI_SYM53C8XX_2=y
 CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0
@@ -358,17 +550,15 @@ CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
 # CONFIG_SCSI_PAS16 is not set
 # CONFIG_SCSI_PSI240I is not set
 # CONFIG_SCSI_QLOGIC_FAS is not set
-# CONFIG_SCSI_QLOGIC_ISP is not set
 # CONFIG_SCSI_QLOGIC_FC is not set
 # CONFIG_SCSI_QLOGIC_1280 is not set
-# CONFIG_SCSI_QLOGIC_1280_1040 is not set
 CONFIG_SCSI_QLA2XXX=y
 # CONFIG_SCSI_QLA21XX is not set
 # CONFIG_SCSI_QLA22XX is not set
 # CONFIG_SCSI_QLA2300 is not set
 # CONFIG_SCSI_QLA2322 is not set
 # CONFIG_SCSI_QLA6312 is not set
-# CONFIG_SCSI_QLA6322 is not set
+# CONFIG_SCSI_LPFC is not set
 # CONFIG_SCSI_SYM53C416 is not set
 # CONFIG_SCSI_DC395x is not set
 # CONFIG_SCSI_DC390T is not set
@@ -395,11 +585,40 @@ CONFIG_SCSI_MAC53C94=y
 # Fusion MPT device support
 #
 # CONFIG_FUSION is not set
+# CONFIG_FUSION_SPI is not set
+# CONFIG_FUSION_FC is not set
 
 #
 # IEEE 1394 (FireWire) support
 #
-# CONFIG_IEEE1394 is not set
+CONFIG_IEEE1394=m
+
+#
+# Subsystem Options
+#
+# CONFIG_IEEE1394_VERBOSEDEBUG is not set
+CONFIG_IEEE1394_OUI_DB=y
+CONFIG_IEEE1394_EXTRA_CONFIG_ROMS=y
+CONFIG_IEEE1394_CONFIG_ROM_IP1394=y
+# CONFIG_IEEE1394_EXPORT_FULL_API is not set
+
+#
+# Device Drivers
+#
+# CONFIG_IEEE1394_PCILYNX is not set
+CONFIG_IEEE1394_OHCI1394=m
+
+#
+# Protocol Drivers
+#
+CONFIG_IEEE1394_VIDEO1394=m
+CONFIG_IEEE1394_SBP2=m
+# CONFIG_IEEE1394_SBP2_PHYS_DMA is not set
+CONFIG_IEEE1394_ETH1394=m
+CONFIG_IEEE1394_DV1394=m
+CONFIG_IEEE1394_RAWIO=m
+CONFIG_IEEE1394_CMP=m
+CONFIG_IEEE1394_AMDTP=m
 
 #
 # I2O device support
@@ -412,8 +631,8 @@ CONFIG_SCSI_MAC53C94=y
 CONFIG_ADB=y
 CONFIG_ADB_CUDA=y
 CONFIG_ADB_PMU=y
-CONFIG_PMAC_PBOOK=y
 CONFIG_PMAC_APM_EMU=y
+CONFIG_PMAC_MEDIABAY=y
 CONFIG_PMAC_BACKLIGHT=y
 CONFIG_ADB_MACIO=y
 CONFIG_INPUT_ADBHID=y
@@ -423,138 +642,13 @@ CONFIG_THERM_ADT746X=m
 # CONFIG_ANSLCD is not set
 
 #
-# Networking support
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-# CONFIG_NETLINK_DEV is not set
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_IP_TCPDIAG=y
-# CONFIG_IP_TCPDIAG_IPV6 is not set
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# IP: Netfilter Configuration
+# Network device support
 #
-CONFIG_IP_NF_CONNTRACK=m
-# CONFIG_IP_NF_CT_ACCT is not set
-# CONFIG_IP_NF_CONNTRACK_MARK is not set
-# CONFIG_IP_NF_CT_PROTO_SCTP is not set
-CONFIG_IP_NF_FTP=m
-CONFIG_IP_NF_IRC=m
-CONFIG_IP_NF_TFTP=m
-CONFIG_IP_NF_AMANDA=m
-# CONFIG_IP_NF_QUEUE is not set
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_LIMIT=m
-CONFIG_IP_NF_MATCH_IPRANGE=m
-CONFIG_IP_NF_MATCH_MAC=m
-CONFIG_IP_NF_MATCH_PKTTYPE=m
-CONFIG_IP_NF_MATCH_MARK=m
-CONFIG_IP_NF_MATCH_MULTIPORT=m
-CONFIG_IP_NF_MATCH_TOS=m
-CONFIG_IP_NF_MATCH_RECENT=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_DSCP=m
-CONFIG_IP_NF_MATCH_AH_ESP=m
-CONFIG_IP_NF_MATCH_LENGTH=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_MATCH_TCPMSS=m
-CONFIG_IP_NF_MATCH_HELPER=m
-CONFIG_IP_NF_MATCH_STATE=m
-CONFIG_IP_NF_MATCH_CONNTRACK=m
-CONFIG_IP_NF_MATCH_OWNER=m
-# CONFIG_IP_NF_MATCH_ADDRTYPE is not set
-# CONFIG_IP_NF_MATCH_REALM is not set
-# CONFIG_IP_NF_MATCH_SCTP is not set
-# CONFIG_IP_NF_MATCH_COMMENT is not set
-# CONFIG_IP_NF_MATCH_HASHLIMIT is not set
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-# CONFIG_IP_NF_TARGET_LOG is not set
-CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_TARGET_TCPMSS=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_NAT_NEEDED=y
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_SAME=m
-CONFIG_IP_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_NAT_IRC=m
-CONFIG_IP_NF_NAT_FTP=m
-CONFIG_IP_NF_NAT_TFTP=m
-CONFIG_IP_NF_NAT_AMANDA=m
-# CONFIG_IP_NF_MANGLE is not set
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_TARGET_NOTRACK=m
-# CONFIG_IP_NF_ARPTABLES is not set
-CONFIG_IP_NF_COMPAT_IPCHAINS=m
-# CONFIG_IP_NF_COMPAT_IPFWADM is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-# CONFIG_NET_CLS_ROUTE is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
+CONFIG_TUN=m
 
 #
 # ARCnet devices
@@ -588,6 +682,8 @@ CONFIG_TULIP_MMIO=y
 CONFIG_DE4X5=m
 # CONFIG_WINBOND_840 is not set
 # CONFIG_DM9102 is not set
+# CONFIG_PCMCIA_XIRCOM is not set
+# CONFIG_PCMCIA_XIRTULIP is not set
 # CONFIG_AT1700 is not set
 # CONFIG_DEPCA is not set
 # CONFIG_HP100 is not set
@@ -626,9 +722,12 @@ CONFIG_PCNET32=y
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 # CONFIG_R8169 is not set
+# CONFIG_SKGE is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_MV643XX_ETH is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -676,18 +775,19 @@ CONFIG_NET_WIRELESS=y
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
 CONFIG_PPP=y
 CONFIG_PPP_MULTILINK=y
 CONFIG_PPP_FILTER=y
 CONFIG_PPP_ASYNC=y
 # CONFIG_PPP_SYNC_TTY is not set
 CONFIG_PPP_DEFLATE=y
-# CONFIG_PPP_BSDCOMP is not set
-# CONFIG_PPPOE is not set
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPPOE=m
 # CONFIG_SLIP is not set
 # CONFIG_NET_FC is not set
 # CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
+CONFIG_NETCONSOLE=m
 
 #
 # ISDN subsystem
@@ -708,7 +808,7 @@ CONFIG_INPUT=y
 # Userland interfaces
 #
 CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
@@ -717,18 +817,6 @@ CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_EVBUG=m
 
 #
-# Input I/O drivers
-#
-# CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
-CONFIG_SERIO=y
-CONFIG_SERIO_I8042=y
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_SERIO_CT82C710 is not set
-# CONFIG_SERIO_PCIPS2 is not set
-# CONFIG_SERIO_RAW is not set
-
-#
 # Input Device Drivers
 #
 CONFIG_INPUT_KEYBOARD=y
@@ -751,6 +839,18 @@ CONFIG_INPUT_MISC=y
 CONFIG_INPUT_UINPUT=m
 
 #
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_PARKBD is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
 # Character devices
 #
 CONFIG_VT=y
@@ -761,7 +861,8 @@ CONFIG_HW_CONSOLE=y
 #
 # Serial drivers
 #
-CONFIG_SERIAL_8250=m
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_NR_UARTS=4
 # CONFIG_SERIAL_8250_EXTENDED is not set
 
@@ -769,11 +870,16 @@ CONFIG_SERIAL_8250_NR_UARTS=4
 # Non-8250 serial port support
 #
 CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_SERIAL_PMACZILOG=y
-# CONFIG_SERIAL_PMACZILOG_CONSOLE is not set
+CONFIG_SERIAL_PMACZILOG_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_PRINTER is not set
+# CONFIG_PPDEV is not set
+# CONFIG_TIPAR is not set
 
 #
 # IPMI
@@ -794,11 +900,23 @@ CONFIG_GEN_RTC=y
 #
 # Ftape, the floppy tape device driver
 #
-# CONFIG_AGP is not set
-# CONFIG_DRM is not set
+CONFIG_AGP=m
+CONFIG_AGP_UNINORTH=m
+CONFIG_DRM=m
+# CONFIG_DRM_TDFX is not set
+CONFIG_DRM_R128=m
+CONFIG_DRM_RADEON=m
+# CONFIG_DRM_MGA is not set
+# CONFIG_DRM_SIS is not set
+# CONFIG_DRM_VIA is not set
 # CONFIG_RAW_DRIVER is not set
 
 #
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+
+#
 # I2C support
 #
 CONFIG_I2C=y
@@ -823,11 +941,13 @@ CONFIG_I2C_ALGOBIT=y
 CONFIG_I2C_HYDRA=y
 # CONFIG_I2C_I801 is not set
 # CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
 # CONFIG_I2C_ISA is not set
 CONFIG_I2C_KEYWEST=m
+# CONFIG_I2C_MPC is not set
 # CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_PIIX4 is not set
 # CONFIG_I2C_PROSAVAGE is not set
 # CONFIG_I2C_SAVAGE4 is not set
 # CONFIG_SCx200_ACB is not set
@@ -839,43 +959,20 @@ CONFIG_I2C_KEYWEST=m
 # CONFIG_I2C_VIAPRO is not set
 # CONFIG_I2C_VOODOO3 is not set
 # CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_SENSOR is not set
 
 #
-# Hardware Sensors Chip support
-#
-# CONFIG_I2C_SENSOR is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ASB100 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_FSCHER is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_VIA686A is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83627HF is not set
-
-#
-# Other I2C Chip support
+# Miscellaneous I2C Chip support
 #
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_SENSORS_M41T00 is not set
+# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
@@ -887,6 +984,11 @@ CONFIG_I2C_KEYWEST=m
 # CONFIG_W1 is not set
 
 #
+# Hardware Monitoring support
+#
+# CONFIG_HWMON is not set
+
+#
 # Misc devices
 #
 
@@ -904,8 +1006,13 @@ CONFIG_I2C_KEYWEST=m
 # Graphics support
 #
 CONFIG_FB=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_SOFT_CURSOR=y
+CONFIG_FB_MACMODES=y
 CONFIG_FB_MODE_HELPERS=y
-# CONFIG_FB_TILEBLITTING is not set
+CONFIG_FB_TILEBLITTING=y
 # CONFIG_FB_CIRRUS is not set
 # CONFIG_FB_PM2 is not set
 # CONFIG_FB_CYBER2000 is not set
@@ -917,13 +1024,16 @@ CONFIG_FB_CT65550=y
 # CONFIG_FB_ASILIANT is not set
 CONFIG_FB_IMSTT=y
 # CONFIG_FB_VGA16 is not set
-# CONFIG_FB_RIVA is not set
+# CONFIG_FB_NVIDIA is not set
+CONFIG_FB_RIVA=y
+CONFIG_FB_RIVA_I2C=y
+# CONFIG_FB_RIVA_DEBUG is not set
 CONFIG_FB_MATROX=y
 CONFIG_FB_MATROX_MILLENIUM=y
 CONFIG_FB_MATROX_MYSTIQUE=y
-# CONFIG_FB_MATROX_G450 is not set
-# CONFIG_FB_MATROX_G100A is not set
+CONFIG_FB_MATROX_G=y
 CONFIG_FB_MATROX_I2C=y
+CONFIG_FB_MATROX_MAVEN=m
 # CONFIG_FB_MATROX_MULTIHEAD is not set
 # CONFIG_FB_RADEON_OLD is not set
 CONFIG_FB_RADEON=y
@@ -932,8 +1042,8 @@ CONFIG_FB_RADEON_I2C=y
 CONFIG_FB_ATY128=y
 CONFIG_FB_ATY=y
 CONFIG_FB_ATY_CT=y
-# CONFIG_FB_ATY_GENERIC_LCD is not set
-# CONFIG_FB_ATY_XL_INIT is not set
+CONFIG_FB_ATY_GENERIC_LCD=y
+CONFIG_FB_ATY_XL_INIT=y
 CONFIG_FB_ATY_GX=y
 # CONFIG_FB_SAVAGE is not set
 # CONFIG_FB_SIS is not set
@@ -943,6 +1053,7 @@ CONFIG_FB_3DFX=y
 # CONFIG_FB_3DFX_ACCEL is not set
 # CONFIG_FB_VOODOO1 is not set
 # CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
 
 #
@@ -960,9 +1071,10 @@ CONFIG_FONT_8x16=y
 # Logo configuration
 #
 CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
 CONFIG_LOGO_LINUX_CLUT224=y
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
 # Sound
@@ -987,6 +1099,7 @@ CONFIG_SND_PCM_OSS=m
 CONFIG_SND_SEQUENCER_OSS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
+CONFIG_SND_GENERIC_PM=y
 
 #
 # Generic devices
@@ -1002,6 +1115,7 @@ CONFIG_SND_OPL3_LIB=m
 #
 # ISA devices
 #
+CONFIG_SND_CS4231_LIB=m
 # CONFIG_SND_AD1848 is not set
 # CONFIG_SND_CS4231 is not set
 CONFIG_SND_CS4232=m
@@ -1039,6 +1153,8 @@ CONFIG_SND_CS4232=m
 # CONFIG_SND_CS46XX is not set
 # CONFIG_SND_CS4281 is not set
 # CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_CA0106 is not set
 # CONFIG_SND_KORG1212 is not set
 # CONFIG_SND_MIXART is not set
 # CONFIG_SND_NM256 is not set
@@ -1046,6 +1162,7 @@ CONFIG_SND_CS4232=m
 # CONFIG_SND_RME96 is not set
 # CONFIG_SND_RME9652 is not set
 # CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
 # CONFIG_SND_TRIDENT is not set
 # CONFIG_SND_YMFPCI is not set
 # CONFIG_SND_ALS4000 is not set
@@ -1062,7 +1179,9 @@ CONFIG_SND_CS4232=m
 # CONFIG_SND_INTEL8X0M is not set
 # CONFIG_SND_SONICVIBES is not set
 # CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
 # CONFIG_SND_VX222 is not set
+# CONFIG_SND_HDA_INTEL is not set
 
 #
 # ALSA PowerMac devices
@@ -1083,6 +1202,8 @@ CONFIG_SND_USB_AUDIO=m
 #
 # USB support
 #
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
 CONFIG_USB=y
 # CONFIG_USB_DEBUG is not set
 
@@ -1094,15 +1215,19 @@ CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_SUSPEND is not set
 # CONFIG_USB_OTG is not set
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
 
 #
 # USB Host Controller Drivers
 #
-# CONFIG_USB_EHCI_HCD is not set
+CONFIG_USB_EHCI_HCD=m
+CONFIG_USB_EHCI_SPLIT_ISO=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_ISP116X_HCD is not set
 CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_UHCI_HCD=m
+# CONFIG_USB_SL811_HCD is not set
 
 #
 # USB Device Class drivers
@@ -1112,17 +1237,20 @@ CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_MIDI is not set
 CONFIG_USB_ACM=m
 CONFIG_USB_PRINTER=m
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
+#
 CONFIG_USB_STORAGE=m
 # CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_RW_DETECT is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
+CONFIG_USB_STORAGE_DATAFAB=y
 CONFIG_USB_STORAGE_FREECOM=y
-# CONFIG_USB_STORAGE_ISD200 is not set
+CONFIG_USB_STORAGE_ISD200=y
 CONFIG_USB_STORAGE_DPCM=y
-# CONFIG_USB_STORAGE_HP8200e is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
+CONFIG_USB_STORAGE_USBAT=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
 
 #
 # USB Input Devices
@@ -1130,22 +1258,24 @@ CONFIG_USB_STORAGE_DPCM=y
 CONFIG_USB_HID=y
 CONFIG_USB_HIDINPUT=y
 # CONFIG_HID_FF is not set
-# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_HIDDEV=y
 # CONFIG_USB_AIPTEK is not set
 # CONFIG_USB_WACOM is not set
+# CONFIG_USB_ACECAD is not set
 # CONFIG_USB_KBTAB is not set
 # CONFIG_USB_POWERMATE is not set
 # CONFIG_USB_MTOUCH is not set
+# CONFIG_USB_ITMTOUCH is not set
 # CONFIG_USB_EGALAX is not set
 # CONFIG_USB_XPAD is not set
 # CONFIG_USB_ATI_REMOTE is not set
+# CONFIG_USB_KEYSPAN_REMOTE is not set
 
 #
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
-# CONFIG_USB_HPUSBSCSI is not set
 
 #
 # USB Multimedia devices
@@ -1161,22 +1291,27 @@ CONFIG_USB_HIDINPUT=y
 #
 # CONFIG_USB_CATC is not set
 # CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
+CONFIG_USB_PEGASUS=m
 # CONFIG_USB_RTL8150 is not set
 # CONFIG_USB_USBNET is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_MON is not set
 
 #
 # USB port drivers
 #
+# CONFIG_USB_USS720 is not set
 
 #
 # USB Serial Converter support
 #
 CONFIG_USB_SERIAL=m
 # CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_AIRPRIME is not set
 # CONFIG_USB_SERIAL_BELKIN is not set
 # CONFIG_USB_SERIAL_WHITEHEAT is not set
 # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP2101 is not set
 # CONFIG_USB_SERIAL_CYPRESS_M8 is not set
 # CONFIG_USB_SERIAL_EMPEG is not set
 # CONFIG_USB_SERIAL_FTDI_SIO is not set
@@ -1185,28 +1320,32 @@ CONFIG_USB_SERIAL_VISOR=m
 # CONFIG_USB_SERIAL_IR is not set
 # CONFIG_USB_SERIAL_EDGEPORT is not set
 # CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
 # CONFIG_USB_SERIAL_IPW is not set
 # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
 CONFIG_USB_SERIAL_KEYSPAN=m
-# CONFIG_USB_SERIAL_KEYSPAN_MPR is not set
+CONFIG_USB_SERIAL_KEYSPAN_MPR=y
 CONFIG_USB_SERIAL_KEYSPAN_USA28=y
 CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
-# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
 CONFIG_USB_SERIAL_KEYSPAN_USA19=y
 CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
 CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
 CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
 CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
 CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
-# CONFIG_USB_SERIAL_KEYSPAN_USA49WLC is not set
+CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
 # CONFIG_USB_SERIAL_KLSI is not set
 # CONFIG_USB_SERIAL_KOBIL_SCT is not set
 # CONFIG_USB_SERIAL_MCT_U232 is not set
 # CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
 # CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_TI is not set
 # CONFIG_USB_SERIAL_CYBERJACK is not set
 # CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
 # CONFIG_USB_SERIAL_OMNINET is not set
 CONFIG_USB_EZUSB=y
 
@@ -1215,7 +1354,6 @@ CONFIG_USB_EZUSB=y
 #
 # CONFIG_USB_EMI62 is not set
 # CONFIG_USB_EMI26 is not set
-# CONFIG_USB_TIGL is not set
 # CONFIG_USB_AUERSWALD is not set
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
@@ -1224,10 +1362,13 @@ CONFIG_USB_EZUSB=y
 # CONFIG_USB_CYTHERM is not set
 # CONFIG_USB_PHIDGETKIT is not set
 # CONFIG_USB_PHIDGETSERVO is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
 # CONFIG_USB_TEST is not set
 
 #
-# USB ATM/DSL drivers
+# USB DSL modem support
 #
 
 #
@@ -1236,21 +1377,63 @@ CONFIG_USB_EZUSB=y
 # CONFIG_USB_GADGET is not set
 
 #
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# SN Devices
+#
+
+#
 # File systems
 #
 CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_JBD is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_XFS_FS is not set
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+CONFIG_JFS_FS=m
+CONFIG_JFS_POSIX_ACL=y
+CONFIG_JFS_SECURITY=y
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
+CONFIG_FS_POSIX_ACL=y
+
+#
+# XFS support
+#
+CONFIG_XFS_FS=m
+CONFIG_XFS_EXPORT=y
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_QUOTA is not set
+CONFIG_XFS_SECURITY=y
+CONFIG_XFS_POSIX_ACL=y
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
 # CONFIG_QUOTA is not set
 CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
+CONFIG_AUTOFS4_FS=m
 
 #
 # CD-ROM/DVD Filesystems
@@ -1258,7 +1441,8 @@ CONFIG_DNOTIFY=y
 CONFIG_ISO9660_FS=y
 # CONFIG_JOLIET is not set
 # CONFIG_ZISOFS is not set
-# CONFIG_UDF_FS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
 
 #
 # DOS/FAT/NT Filesystems
@@ -1276,12 +1460,11 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-CONFIG_DEVFS_FS=y
-# CONFIG_DEVFS_MOUNT is not set
-# CONFIG_DEVFS_DEBUG is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_DEVPTS_FS_XATTR=y
+CONFIG_DEVPTS_FS_SECURITY=y
 CONFIG_TMPFS=y
-# CONFIG_TMPFS_XATTR is not set
+CONFIG_TMPFS_XATTR=y
+CONFIG_TMPFS_SECURITY=y
 # CONFIG_HUGETLB_PAGE is not set
 CONFIG_RAMFS=y
 
@@ -1295,27 +1478,33 @@ CONFIG_HFSPLUS_FS=m
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
+CONFIG_CRAMFS=m
 # CONFIG_VXFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
+CONFIG_UFS_FS=m
+# CONFIG_UFS_FS_WRITE is not set
 
 #
 # Network File Systems
 #
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
 # CONFIG_NFS_V4 is not set
 # CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=y
+CONFIG_NFSD_V2_ACL=y
 CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
 # CONFIG_NFSD_V4 is not set
 CONFIG_NFSD_TCP=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -1348,46 +1537,46 @@ CONFIG_MSDOS_PARTITION=y
 #
 # Native Language Support
 #
-CONFIG_NLS=y
+CONFIG_NLS=m
 CONFIG_NLS_DEFAULT="iso8859-1"
-# CONFIG_NLS_CODEPAGE_437 is not set
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
 CONFIG_NLS_ISO8859_1=m
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=m
 
 #
 # Library routines
@@ -1406,7 +1595,19 @@ CONFIG_ZLIB_DEFLATE=y
 #
 # Kernel hacking
 #
-# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_XMON is not set
+# CONFIG_BDI_SWITCH is not set
 CONFIG_BOOTX_TEXT=y
 
 #
@@ -1419,3 +1620,7 @@ CONFIG_BOOTX_TEXT=y
 # Cryptographic options
 #
 # CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
diff --git a/arch/ppc/configs/pmac_defconfig b/arch/ppc/configs/pmac_defconfig
index 8eebb045576..a2db8b541c9 100644
--- a/arch/ppc/configs/pmac_defconfig
+++ b/arch/ppc/configs/pmac_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.11-rc4
-# Sun Feb 13 14:56:58 2005
+# Linux kernel version: 2.6.13-rc3
+# Wed Jul 13 14:13:13 2005
 #
 CONFIG_MMU=y
 CONFIG_GENERIC_HARDIRQS=y
@@ -11,6 +11,7 @@ CONFIG_HAVE_DEC_LOCK=y
 CONFIG_PPC=y
 CONFIG_PPC32=y
 CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
 
 #
 # Code maturity level options
@@ -18,6 +19,7 @@ CONFIG_GENERIC_NVRAM=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
 
 #
 # General setup
@@ -28,7 +30,7 @@ CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 CONFIG_SYSCTL=y
-CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_AUDIT is not set
 CONFIG_HOTPLUG=y
 CONFIG_KOBJECT_UEVENT=y
 CONFIG_IKCONFIG=y
@@ -37,15 +39,18 @@ CONFIG_IKCONFIG_PROC=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SHMEM=y
 CONFIG_CC_ALIGN_FUNCTIONS=0
 CONFIG_CC_ALIGN_LABELS=0
 CONFIG_CC_ALIGN_LOOPS=0
 CONFIG_CC_ALIGN_JUMPS=0
 # CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
 
 #
 # Loadable module support
@@ -67,12 +72,16 @@ CONFIG_6xx=y
 # CONFIG_POWER3 is not set
 # CONFIG_POWER4 is not set
 # CONFIG_8xx is not set
+# CONFIG_E200 is not set
 # CONFIG_E500 is not set
+CONFIG_PPC_FPU=y
 CONFIG_ALTIVEC=y
 CONFIG_TAU=y
 # CONFIG_TAU_INT is not set
 # CONFIG_TAU_AVERAGE is not set
+# CONFIG_KEXEC is not set
 CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
 # CONFIG_CPU_FREQ_DEBUG is not set
 CONFIG_CPU_FREQ_STAT=m
 CONFIG_CPU_FREQ_STAT_DETAILS=y
@@ -82,8 +91,8 @@ CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
 CONFIG_CPU_FREQ_GOV_POWERSAVE=m
 CONFIG_CPU_FREQ_GOV_USERSPACE=m
 CONFIG_CPU_FREQ_GOV_ONDEMAND=m
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
 CONFIG_CPU_FREQ_PMAC=y
-CONFIG_CPU_FREQ_TABLE=y
 CONFIG_PPC601_SYNC_FIX=y
 CONFIG_PM=y
 CONFIG_PPC_STD_MMU=y
@@ -100,6 +109,7 @@ CONFIG_PPC_MULTIPLATFORM=y
 # CONFIG_POWERPMC250 is not set
 # CONFIG_CHESTNUT is not set
 # CONFIG_SPRUCE is not set
+# CONFIG_HDPU is not set
 # CONFIG_EV64260 is not set
 # CONFIG_LOPEC is not set
 # CONFIG_MCPN765 is not set
@@ -108,6 +118,7 @@ CONFIG_PPC_MULTIPLATFORM=y
 # CONFIG_PRPMC750 is not set
 # CONFIG_PRPMC800 is not set
 # CONFIG_SANDPOINT is not set
+# CONFIG_RADSTONE_PPC7D is not set
 # CONFIG_ADIR is not set
 # CONFIG_K2 is not set
 # CONFIG_PAL4 is not set
@@ -120,19 +131,37 @@ CONFIG_PPC_MULTIPLATFORM=y
 # CONFIG_ADS8272 is not set
 # CONFIG_PQ2FADS is not set
 # CONFIG_LITE5200 is not set
+# CONFIG_MPC834x_SYS is not set
 CONFIG_PPC_CHRP=y
 CONFIG_PPC_PMAC=y
 CONFIG_PPC_PREP=y
 CONFIG_PPC_OF=y
 CONFIG_PPCBUG_NVRAM=y
 # CONFIG_SMP is not set
-# CONFIG_PREEMPT is not set
 # CONFIG_HIGHMEM is not set
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_BINFMT_ELF=y
 CONFIG_BINFMT_MISC=m
 CONFIG_PROC_DEVICETREE=y
 # CONFIG_PREP_RESIDUAL is not set
 # CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM_DEBUG is not set
+CONFIG_SOFTWARE_SUSPEND=y
+CONFIG_PM_STD_PARTITION=""
+# CONFIG_SECCOMP is not set
+CONFIG_ISA_DMA_API=y
 
 #
 # Bus options
@@ -143,6 +172,7 @@ CONFIG_PCI=y
 CONFIG_PCI_DOMAINS=y
 CONFIG_PCI_LEGACY_PROC=y
 CONFIG_PCI_NAMES=y
+# CONFIG_PCI_DEBUG is not set
 
 #
 # PCCARD (PCMCIA/CardBus) support
@@ -150,6 +180,8 @@ CONFIG_PCI_NAMES=y
 CONFIG_PCCARD=m
 # CONFIG_PCMCIA_DEBUG is not set
 CONFIG_PCMCIA=m
+# CONFIG_PCMCIA_LOAD_CIS is not set
+# CONFIG_PCMCIA_IOCTL is not set
 CONFIG_CARDBUS=y
 
 #
@@ -175,6 +207,194 @@ CONFIG_TASK_SIZE=0xc0000000
 CONFIG_BOOT_LOAD=0x00800000
 
 #
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_IP_TCPDIAG=y
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+
+#
+# IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_IP_NF_CONNTRACK=m
+CONFIG_IP_NF_CT_ACCT=y
+CONFIG_IP_NF_CONNTRACK_MARK=y
+CONFIG_IP_NF_CT_PROTO_SCTP=m
+CONFIG_IP_NF_FTP=m
+CONFIG_IP_NF_IRC=m
+CONFIG_IP_NF_TFTP=m
+CONFIG_IP_NF_AMANDA=m
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_LIMIT=m
+CONFIG_IP_NF_MATCH_IPRANGE=m
+CONFIG_IP_NF_MATCH_MAC=m
+CONFIG_IP_NF_MATCH_PKTTYPE=m
+CONFIG_IP_NF_MATCH_MARK=m
+CONFIG_IP_NF_MATCH_MULTIPORT=m
+CONFIG_IP_NF_MATCH_TOS=m
+CONFIG_IP_NF_MATCH_RECENT=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_DSCP=m
+CONFIG_IP_NF_MATCH_AH_ESP=m
+CONFIG_IP_NF_MATCH_LENGTH=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_MATCH_TCPMSS=m
+CONFIG_IP_NF_MATCH_HELPER=m
+CONFIG_IP_NF_MATCH_STATE=m
+CONFIG_IP_NF_MATCH_CONNTRACK=m
+CONFIG_IP_NF_MATCH_OWNER=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_REALM=m
+CONFIG_IP_NF_MATCH_SCTP=m
+CONFIG_IP_NF_MATCH_COMMENT=m
+CONFIG_IP_NF_MATCH_CONNMARK=m
+CONFIG_IP_NF_MATCH_HASHLIMIT=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_TARGET_TCPMSS=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_SAME=m
+CONFIG_IP_NF_NAT_SNMP_BASIC=m
+CONFIG_IP_NF_NAT_IRC=m
+CONFIG_IP_NF_NAT_FTP=m
+CONFIG_IP_NF_NAT_TFTP=m
+CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_TOS=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_DSCP=m
+CONFIG_IP_NF_TARGET_MARK=m
+CONFIG_IP_NF_TARGET_CLASSIFY=m
+CONFIG_IP_NF_TARGET_CONNMARK=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_TARGET_NOTRACK=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_CLS_ROUTE=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_RX is not set
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_HAMRADIO is not set
+CONFIG_IRDA=m
+
+#
+# IrDA protocols
+#
+CONFIG_IRLAN=m
+CONFIG_IRNET=m
+CONFIG_IRCOMM=m
+# CONFIG_IRDA_ULTRA is not set
+
+#
+# IrDA options
+#
+CONFIG_IRDA_CACHE_LAST_LSAP=y
+CONFIG_IRDA_FAST_RR=y
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+CONFIG_IRTTY_SIR=m
+
+#
+# Dongle support
+#
+# CONFIG_DONGLE is not set
+
+#
+# Old SIR device drivers
+#
+# CONFIG_IRPORT_SIR is not set
+
+#
+# Old Serial dongle support
+#
+
+#
+# FIR device drivers
+#
+# CONFIG_USB_IRDA is not set
+# CONFIG_SIGMATEL_FIR is not set
+# CONFIG_NSC_FIR is not set
+# CONFIG_WINBOND_FIR is not set
+# CONFIG_TOSHIBA_FIR is not set
+# CONFIG_SMC_IRCC_FIR is not set
+# CONFIG_ALI_FIR is not set
+# CONFIG_VLSI_FIR is not set
+# CONFIG_VIA_FIR is not set
+# CONFIG_BT is not set
+
+#
 # Device Drivers
 #
 
@@ -183,7 +403,7 @@ CONFIG_BOOT_LOAD=0x00800000
 #
 # CONFIG_STANDALONE is not set
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
+CONFIG_FW_LOADER=m
 # CONFIG_DEBUG_DRIVER is not set
 
 #
@@ -279,6 +499,7 @@ CONFIG_BLK_DEV_CMD64X=y
 # CONFIG_BLK_DEV_HPT366 is not set
 # CONFIG_BLK_DEV_SC1200 is not set
 # CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT821X is not set
 # CONFIG_BLK_DEV_NS87415 is not set
 # CONFIG_BLK_DEV_PDC202XX_OLD is not set
 CONFIG_BLK_DEV_PDC202XX_NEW=y
@@ -313,6 +534,7 @@ CONFIG_CHR_DEV_ST=y
 CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
 
 #
 # Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -350,7 +572,6 @@ CONFIG_SCSI_AIC7XXX_OLD=m
 # CONFIG_SCSI_BUSLOGIC is not set
 # CONFIG_SCSI_DMX3191D is not set
 # CONFIG_SCSI_EATA is not set
-# CONFIG_SCSI_EATA_PIO is not set
 # CONFIG_SCSI_FUTURE_DOMAIN is not set
 # CONFIG_SCSI_GDTH is not set
 # CONFIG_SCSI_IPS is not set
@@ -362,7 +583,6 @@ CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
 CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
 # CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set
 # CONFIG_SCSI_IPR is not set
-# CONFIG_SCSI_QLOGIC_ISP is not set
 # CONFIG_SCSI_QLOGIC_FC is not set
 # CONFIG_SCSI_QLOGIC_1280 is not set
 CONFIG_SCSI_QLA2XXX=y
@@ -371,6 +591,7 @@ CONFIG_SCSI_QLA2XXX=y
 # CONFIG_SCSI_QLA2300 is not set
 # CONFIG_SCSI_QLA2322 is not set
 # CONFIG_SCSI_QLA6312 is not set
+# CONFIG_SCSI_LPFC is not set
 # CONFIG_SCSI_DC395x is not set
 # CONFIG_SCSI_DC390T is not set
 # CONFIG_SCSI_NSP32 is not set
@@ -398,6 +619,8 @@ CONFIG_SCSI_MAC53C94=y
 # Fusion MPT device support
 #
 # CONFIG_FUSION is not set
+# CONFIG_FUSION_SPI is not set
+# CONFIG_FUSION_FC is not set
 
 #
 # IEEE 1394 (FireWire) support
@@ -411,6 +634,7 @@ CONFIG_IEEE1394=m
 # CONFIG_IEEE1394_OUI_DB is not set
 CONFIG_IEEE1394_EXTRA_CONFIG_ROMS=y
 CONFIG_IEEE1394_CONFIG_ROM_IP1394=y
+# CONFIG_IEEE1394_EXPORT_FULL_API is not set
 
 #
 # Device Drivers
@@ -441,8 +665,8 @@ CONFIG_IEEE1394_AMDTP=m
 CONFIG_ADB=y
 CONFIG_ADB_CUDA=y
 CONFIG_ADB_PMU=y
-CONFIG_PMAC_PBOOK=y
 CONFIG_PMAC_APM_EMU=y
+CONFIG_PMAC_MEDIABAY=y
 CONFIG_PMAC_BACKLIGHT=y
 CONFIG_ADB_MACIO=y
 CONFIG_INPUT_ADBHID=y
@@ -452,192 +676,13 @@ CONFIG_THERM_ADT746X=m
 # CONFIG_ANSLCD is not set
 
 #
-# Networking support
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-# CONFIG_NETLINK_DEV is not set
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_IP_TCPDIAG=y
-# CONFIG_IP_TCPDIAG_IPV6 is not set
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_IP_NF_CONNTRACK=m
-CONFIG_IP_NF_CT_ACCT=y
-CONFIG_IP_NF_CONNTRACK_MARK=y
-CONFIG_IP_NF_CT_PROTO_SCTP=m
-CONFIG_IP_NF_FTP=m
-CONFIG_IP_NF_IRC=m
-CONFIG_IP_NF_TFTP=m
-CONFIG_IP_NF_AMANDA=m
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_LIMIT=m
-CONFIG_IP_NF_MATCH_IPRANGE=m
-CONFIG_IP_NF_MATCH_MAC=m
-CONFIG_IP_NF_MATCH_PKTTYPE=m
-CONFIG_IP_NF_MATCH_MARK=m
-CONFIG_IP_NF_MATCH_MULTIPORT=m
-CONFIG_IP_NF_MATCH_TOS=m
-CONFIG_IP_NF_MATCH_RECENT=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_DSCP=m
-CONFIG_IP_NF_MATCH_AH_ESP=m
-CONFIG_IP_NF_MATCH_LENGTH=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_MATCH_TCPMSS=m
-CONFIG_IP_NF_MATCH_HELPER=m
-CONFIG_IP_NF_MATCH_STATE=m
-CONFIG_IP_NF_MATCH_CONNTRACK=m
-CONFIG_IP_NF_MATCH_OWNER=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_REALM=m
-CONFIG_IP_NF_MATCH_SCTP=m
-CONFIG_IP_NF_MATCH_COMMENT=m
-CONFIG_IP_NF_MATCH_CONNMARK=m
-CONFIG_IP_NF_MATCH_HASHLIMIT=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_TARGET_TCPMSS=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_NAT_NEEDED=y
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_SAME=m
-CONFIG_IP_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_NAT_IRC=m
-CONFIG_IP_NF_NAT_FTP=m
-CONFIG_IP_NF_NAT_TFTP=m
-CONFIG_IP_NF_NAT_AMANDA=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_TOS=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_DSCP=m
-CONFIG_IP_NF_TARGET_MARK=m
-CONFIG_IP_NF_TARGET_CLASSIFY=m
-CONFIG_IP_NF_TARGET_CONNMARK=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_TARGET_NOTRACK=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-CONFIG_NET_CLS_ROUTE=y
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_HAMRADIO is not set
-CONFIG_IRDA=m
-
-#
-# IrDA protocols
-#
-CONFIG_IRLAN=m
-CONFIG_IRNET=m
-CONFIG_IRCOMM=m
-# CONFIG_IRDA_ULTRA is not set
-
-#
-# IrDA options
-#
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRDA_FAST_RR=y
-# CONFIG_IRDA_DEBUG is not set
-
-#
-# Infrared-port device drivers
-#
-
-#
-# SIR device drivers
-#
-CONFIG_IRTTY_SIR=m
-
-#
-# Dongle support
-#
-# CONFIG_DONGLE is not set
-
-#
-# Old SIR device drivers
-#
-# CONFIG_IRPORT_SIR is not set
-
-#
-# Old Serial dongle support
-#
-
-#
-# FIR device drivers
+# Network device support
 #
-# CONFIG_USB_IRDA is not set
-# CONFIG_SIGMATEL_FIR is not set
-# CONFIG_TOSHIBA_FIR is not set
-# CONFIG_VLSI_FIR is not set
-# CONFIG_BT is not set
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
+CONFIG_TUN=m
 
 #
 # ARCnet devices
@@ -691,9 +736,12 @@ CONFIG_PCNET32=y
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 # CONFIG_R8169 is not set
+# CONFIG_SKGE is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_MV643XX_ETH is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -768,7 +816,7 @@ CONFIG_PPPOE=m
 # CONFIG_SLIP is not set
 # CONFIG_NET_FC is not set
 # CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
+CONFIG_NETCONSOLE=m
 
 #
 # ISDN subsystem
@@ -798,14 +846,6 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
 #
-# Input I/O drivers
-#
-# CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
-# CONFIG_SERIO is not set
-# CONFIG_SERIO_I8042 is not set
-
-#
 # Input Device Drivers
 #
 CONFIG_INPUT_KEYBOARD=y
@@ -823,6 +863,12 @@ CONFIG_INPUT_MOUSE=y
 # CONFIG_INPUT_MISC is not set
 
 #
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
 # Character devices
 #
 CONFIG_VT=y
@@ -845,6 +891,7 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_SERIAL_PMACZILOG=y
 CONFIG_SERIAL_PMACZILOG_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
@@ -876,6 +923,7 @@ CONFIG_DRM_R128=m
 CONFIG_DRM_RADEON=m
 # CONFIG_DRM_MGA is not set
 # CONFIG_DRM_SIS is not set
+# CONFIG_DRM_VIA is not set
 
 #
 # PCMCIA character devices
@@ -884,6 +932,11 @@ CONFIG_DRM_RADEON=m
 # CONFIG_RAW_DRIVER is not set
 
 #
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+
+#
 # I2C support
 #
 CONFIG_I2C=y
@@ -907,12 +960,12 @@ CONFIG_I2C_ALGOBIT=y
 # CONFIG_I2C_HYDRA is not set
 # CONFIG_I2C_I801 is not set
 # CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
 # CONFIG_I2C_ISA is not set
 CONFIG_I2C_KEYWEST=m
 # CONFIG_I2C_MPC is not set
 # CONFIG_I2C_NFORCE2 is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_PIIX4 is not set
 # CONFIG_I2C_PROSAVAGE is not set
 # CONFIG_I2C_SAVAGE4 is not set
 # CONFIG_SCx200_ACB is not set
@@ -924,45 +977,20 @@ CONFIG_I2C_KEYWEST=m
 # CONFIG_I2C_VIAPRO is not set
 # CONFIG_I2C_VOODOO3 is not set
 # CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_SENSOR is not set
 
 #
-# Hardware Sensors Chip support
-#
-# CONFIG_I2C_SENSOR is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ASB100 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_FSCHER is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_VIA686A is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83627HF is not set
-
-#
-# Other I2C Chip support
+# Miscellaneous I2C Chip support
 #
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_SENSORS_M41T00 is not set
+# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
@@ -974,6 +1002,11 @@ CONFIG_I2C_KEYWEST=m
 # CONFIG_W1 is not set
 
 #
+# Hardware Monitoring support
+#
+# CONFIG_HWMON is not set
+
+#
 # Misc devices
 #
 
@@ -991,6 +1024,11 @@ CONFIG_I2C_KEYWEST=m
 # Graphics support
 #
 CONFIG_FB=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_SOFT_CURSOR=y
+CONFIG_FB_MACMODES=y
 CONFIG_FB_MODE_HELPERS=y
 CONFIG_FB_TILEBLITTING=y
 # CONFIG_FB_CIRRUS is not set
@@ -1004,6 +1042,7 @@ CONFIG_FB_CT65550=y
 # CONFIG_FB_ASILIANT is not set
 CONFIG_FB_IMSTT=y
 # CONFIG_FB_VGA16 is not set
+# CONFIG_FB_NVIDIA is not set
 # CONFIG_FB_RIVA is not set
 CONFIG_FB_MATROX=y
 CONFIG_FB_MATROX_MILLENIUM=y
@@ -1029,6 +1068,7 @@ CONFIG_FB_3DFX=y
 CONFIG_FB_3DFX_ACCEL=y
 # CONFIG_FB_VOODOO1 is not set
 # CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
 
 #
@@ -1110,6 +1150,7 @@ CONFIG_SND_DUMMY=m
 # CONFIG_SND_RME96 is not set
 # CONFIG_SND_RME9652 is not set
 # CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
 # CONFIG_SND_TRIDENT is not set
 # CONFIG_SND_YMFPCI is not set
 # CONFIG_SND_ALS4000 is not set
@@ -1128,6 +1169,7 @@ CONFIG_SND_DUMMY=m
 # CONFIG_SND_VIA82XX is not set
 # CONFIG_SND_VIA82XX_MODEM is not set
 # CONFIG_SND_VX222 is not set
+# CONFIG_SND_HDA_INTEL is not set
 
 #
 # ALSA PowerMac devices
@@ -1152,6 +1194,8 @@ CONFIG_SND_USB_USX2Y=m
 #
 # USB support
 #
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
 CONFIG_USB=y
 # CONFIG_USB_DEBUG is not set
 
@@ -1163,14 +1207,15 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_DYNAMIC_MINORS=y
 CONFIG_USB_SUSPEND=y
 # CONFIG_USB_OTG is not set
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
 
 #
 # USB Host Controller Drivers
 #
 # CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
 CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_UHCI_HCD is not set
 # CONFIG_USB_SL811_HCD is not set
 
@@ -1197,12 +1242,15 @@ CONFIG_USB_HIDINPUT=y
 CONFIG_USB_HIDDEV=y
 # CONFIG_USB_AIPTEK is not set
 # CONFIG_USB_WACOM is not set
+# CONFIG_USB_ACECAD is not set
 # CONFIG_USB_KBTAB is not set
 # CONFIG_USB_POWERMATE is not set
 # CONFIG_USB_MTOUCH is not set
+# CONFIG_USB_ITMTOUCH is not set
 # CONFIG_USB_EGALAX is not set
 # CONFIG_USB_XPAD is not set
 # CONFIG_USB_ATI_REMOTE is not set
+# CONFIG_USB_KEYSPAN_REMOTE is not set
 
 #
 # USB Imaging devices
@@ -1227,6 +1275,8 @@ CONFIG_USB_HIDDEV=y
 CONFIG_USB_PEGASUS=m
 # CONFIG_USB_RTL8150 is not set
 # CONFIG_USB_USBNET is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_MON is not set
 
 #
 # USB port drivers
@@ -1237,9 +1287,11 @@ CONFIG_USB_PEGASUS=m
 #
 CONFIG_USB_SERIAL=m
 # CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_AIRPRIME is not set
 # CONFIG_USB_SERIAL_BELKIN is not set
 # CONFIG_USB_SERIAL_WHITEHEAT is not set
 # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP2101 is not set
 # CONFIG_USB_SERIAL_CYPRESS_M8 is not set
 # CONFIG_USB_SERIAL_EMPEG is not set
 # CONFIG_USB_SERIAL_FTDI_SIO is not set
@@ -1268,10 +1320,12 @@ CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
 # CONFIG_USB_SERIAL_KOBIL_SCT is not set
 # CONFIG_USB_SERIAL_MCT_U232 is not set
 # CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
 # CONFIG_USB_SERIAL_SAFE is not set
 # CONFIG_USB_SERIAL_TI is not set
 # CONFIG_USB_SERIAL_CYBERJACK is not set
 # CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
 # CONFIG_USB_SERIAL_OMNINET is not set
 CONFIG_USB_EZUSB=y
 
@@ -1289,10 +1343,11 @@ CONFIG_USB_EZUSB=y
 # CONFIG_USB_PHIDGETKIT is not set
 # CONFIG_USB_PHIDGETSERVO is not set
 # CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_LD is not set
 # CONFIG_USB_TEST is not set
 
 #
-# USB ATM/DSL drivers
+# USB DSL modem support
 #
 
 #
@@ -1311,12 +1366,17 @@ CONFIG_USB_EZUSB=y
 # CONFIG_INFINIBAND is not set
 
 #
+# SN Devices
+#
+
+#
 # File systems
 #
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 # CONFIG_EXT2_FS_POSIX_ACL is not set
 # CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_XATTR=y
 # CONFIG_EXT3_FS_POSIX_ACL is not set
@@ -1326,6 +1386,7 @@ CONFIG_JBD=y
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
 
 #
 # XFS support
@@ -1333,6 +1394,7 @@ CONFIG_FS_MBCACHE=y
 # CONFIG_XFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
 # CONFIG_QUOTA is not set
 CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
@@ -1363,7 +1425,6 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
 CONFIG_DEVPTS_FS_XATTR=y
 CONFIG_DEVPTS_FS_SECURITY=y
 CONFIG_TMPFS=y
@@ -1394,15 +1455,20 @@ CONFIG_CRAMFS=m
 #
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
 # CONFIG_NFS_V4 is not set
 # CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=y
+CONFIG_NFSD_V2_ACL=y
 CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
 # CONFIG_NFSD_V4 is not set
 CONFIG_NFSD_TCP=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -1494,8 +1560,10 @@ CONFIG_ZLIB_DEFLATE=y
 #
 # Kernel hacking
 #
+# CONFIG_PRINTK_TIME is not set
 CONFIG_DEBUG_KERNEL=y
 CONFIG_MAGIC_SYSRQ=y
+CONFIG_LOG_BUF_SHIFT=16
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_SPINLOCK is not set
diff --git a/arch/ppc/configs/radstone_ppc7d_defconfig b/arch/ppc/configs/radstone_ppc7d_defconfig
index 7f6467e7794..ca4d1fd0ca0 100644
--- a/arch/ppc/configs/radstone_ppc7d_defconfig
+++ b/arch/ppc/configs/radstone_ppc7d_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.11
-# Tue Mar 15 14:31:19 2005
+# Linux kernel version: 2.6.13-rc3
+# Tue Jul 26 00:02:09 2005
 #
 CONFIG_MMU=y
 CONFIG_GENERIC_HARDIRQS=y
@@ -11,6 +11,7 @@ CONFIG_HAVE_DEC_LOCK=y
 CONFIG_PPC=y
 CONFIG_PPC32=y
 CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
 
 #
 # Code maturity level options
@@ -18,6 +19,7 @@ CONFIG_GENERIC_NVRAM=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
 
 #
 # General setup
@@ -35,6 +37,8 @@ CONFIG_KOBJECT_UEVENT=y
 CONFIG_EMBEDDED=y
 CONFIG_KALLSYMS=y
 CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
@@ -67,9 +71,12 @@ CONFIG_6xx=y
 # CONFIG_POWER3 is not set
 # CONFIG_POWER4 is not set
 # CONFIG_8xx is not set
+# CONFIG_E200 is not set
 # CONFIG_E500 is not set
+CONFIG_PPC_FPU=y
 CONFIG_ALTIVEC=y
 # CONFIG_TAU is not set
+# CONFIG_KEXEC is not set
 # CONFIG_CPU_FREQ is not set
 CONFIG_PPC_GEN550=y
 # CONFIG_PM is not set
@@ -84,21 +91,18 @@ CONFIG_PPC_STD_MMU=y
 # CONFIG_KATANA is not set
 # CONFIG_WILLOW is not set
 # CONFIG_CPCI690 is not set
-# CONFIG_PCORE is not set
 # CONFIG_POWERPMC250 is not set
 # CONFIG_CHESTNUT is not set
 # CONFIG_SPRUCE is not set
+# CONFIG_HDPU is not set
 # CONFIG_EV64260 is not set
 # CONFIG_LOPEC is not set
-# CONFIG_MCPN765 is not set
 # CONFIG_MVME5100 is not set
 # CONFIG_PPLUS is not set
 # CONFIG_PRPMC750 is not set
 # CONFIG_PRPMC800 is not set
 # CONFIG_SANDPOINT is not set
 CONFIG_RADSTONE_PPC7D=y
-# CONFIG_ADIR is not set
-# CONFIG_K2 is not set
 # CONFIG_PAL4 is not set
 # CONFIG_GEMINI is not set
 # CONFIG_EST8260 is not set
@@ -121,10 +125,18 @@ CONFIG_MV64X60_NEW_BASE=0xfef00000
 # CONFIG_SMP is not set
 # CONFIG_PREEMPT is not set
 # CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_BINFMT_ELF=y
 CONFIG_BINFMT_MISC=y
 CONFIG_CMDLINE_BOOL=y
 CONFIG_CMDLINE="console=ttyS0,9600"
+CONFIG_SECCOMP=y
+CONFIG_ISA_DMA_API=y
 
 #
 # Bus options
@@ -155,6 +167,69 @@ CONFIG_TASK_SIZE=0x80000000
 CONFIG_BOOT_LOAD=0x00800000
 
 #
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_IP_TCPDIAG=y
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+CONFIG_BRIDGE=y
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+
+#
 # Device Drivers
 #
 
@@ -203,6 +278,7 @@ CONFIG_MTD_CFI_I1=y
 CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_CFI_I4 is not set
 # CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
 CONFIG_MTD_CFI_INTELEXT=y
 # CONFIG_MTD_CFI_AMDSTD is not set
 # CONFIG_MTD_CFI_STAA is not set
@@ -210,13 +286,13 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
 
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 # CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PLATRAM is not set
 
 #
 # Self-contained MTD device drivers
@@ -299,6 +375,7 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
 
 #
 # Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -331,7 +408,6 @@ CONFIG_SCSI_SPI_ATTRS=y
 # CONFIG_SCSI_BUSLOGIC is not set
 # CONFIG_SCSI_DMX3191D is not set
 # CONFIG_SCSI_EATA is not set
-# CONFIG_SCSI_EATA_PIO is not set
 # CONFIG_SCSI_FUTURE_DOMAIN is not set
 # CONFIG_SCSI_GDTH is not set
 # CONFIG_SCSI_IPS is not set
@@ -343,7 +419,6 @@ CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
 CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
 # CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set
 # CONFIG_SCSI_IPR is not set
-# CONFIG_SCSI_QLOGIC_ISP is not set
 # CONFIG_SCSI_QLOGIC_FC is not set
 # CONFIG_SCSI_QLOGIC_1280 is not set
 CONFIG_SCSI_QLA2XXX=y
@@ -352,6 +427,7 @@ CONFIG_SCSI_QLA2XXX=y
 # CONFIG_SCSI_QLA2300 is not set
 # CONFIG_SCSI_QLA2322 is not set
 # CONFIG_SCSI_QLA6312 is not set
+# CONFIG_SCSI_LPFC is not set
 # CONFIG_SCSI_DC395x is not set
 # CONFIG_SCSI_DC390T is not set
 # CONFIG_SCSI_NSP32 is not set
@@ -366,6 +442,8 @@ CONFIG_SCSI_QLA2XXX=y
 # Fusion MPT device support
 #
 # CONFIG_FUSION is not set
+# CONFIG_FUSION_SPI is not set
+# CONFIG_FUSION_FC is not set
 
 #
 # IEEE 1394 (FireWire) support
@@ -382,71 +460,8 @@ CONFIG_SCSI_QLA2XXX=y
 #
 
 #
-# Networking support
+# Network device support
 #
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-# CONFIG_NETLINK_DEV is not set
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_IP_TCPDIAG=y
-# CONFIG_IP_TCPDIAG_IPV6 is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETFILTER is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-# CONFIG_ATM is not set
-CONFIG_BRIDGE=y
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-# CONFIG_NET_CLS_ROUTE is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
@@ -511,9 +526,11 @@ CONFIG_E100=y
 # CONFIG_YELLOWFIN is not set
 CONFIG_R8169=y
 CONFIG_R8169_NAPI=y
+# CONFIG_SKGE is not set
 CONFIG_SK98LIN=y
 # CONFIG_VIA_VELOCITY is not set
 CONFIG_TIGON3=y
+# CONFIG_BNX2 is not set
 CONFIG_MV643XX_ETH=y
 CONFIG_MV643XX_ETH_0=y
 CONFIG_MV643XX_ETH_1=y
@@ -546,6 +563,8 @@ CONFIG_MV643XX_ETH_1=y
 # CONFIG_NET_FC is not set
 # CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
 
 #
 # ISDN subsystem
@@ -598,7 +617,6 @@ CONFIG_SERIO_SERPORT=y
 CONFIG_SERIO_LIBPS2=y
 # CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
@@ -623,6 +641,7 @@ CONFIG_SERIAL_MPSC=y
 # CONFIG_SERIAL_MPSC_CONSOLE is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
@@ -690,11 +709,11 @@ CONFIG_I2C_CHARDEV=y
 # CONFIG_I2C_AMD8111 is not set
 # CONFIG_I2C_I801 is not set
 # CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
 # CONFIG_I2C_ISA is not set
 # CONFIG_I2C_MPC is not set
 # CONFIG_I2C_NFORCE2 is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_PIIX4 is not set
 # CONFIG_I2C_PROSAVAGE is not set
 # CONFIG_I2C_SAVAGE4 is not set
 # CONFIG_SCx200_ACB is not set
@@ -707,16 +726,41 @@ CONFIG_I2C_CHARDEV=y
 # CONFIG_I2C_VOODOO3 is not set
 # CONFIG_I2C_PCA_ISA is not set
 CONFIG_I2C_MV64XXX=y
+CONFIG_I2C_SENSOR=y
 
 #
-# Hardware Sensors Chip support
+# Miscellaneous I2C Chip support
 #
-CONFIG_I2C_SENSOR=y
+CONFIG_SENSORS_DS1337=y
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_SENSORS_M41T00 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Hardware Monitoring support
+#
+CONFIG_HWMON=y
 # CONFIG_SENSORS_ADM1021 is not set
 # CONFIG_SENSORS_ADM1025 is not set
 # CONFIG_SENSORS_ADM1026 is not set
 # CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
 # CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_FSCHER is not set
 # CONFIG_SENSORS_FSCPOS is not set
@@ -732,33 +776,18 @@ CONFIG_I2C_SENSOR=y
 # CONFIG_SENSORS_LM85 is not set
 # CONFIG_SENSORS_LM87 is not set
 CONFIG_SENSORS_LM90=y
+# CONFIG_SENSORS_LM92 is not set
 # CONFIG_SENSORS_MAX1619 is not set
 # CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
 # CONFIG_SENSORS_SIS5595 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
 # CONFIG_SENSORS_VIA686A is not set
 # CONFIG_SENSORS_W83781D is not set
 # CONFIG_SENSORS_W83L785TS is not set
 # CONFIG_SENSORS_W83627HF is not set
-
-#
-# Other I2C Chip support
-#
-# CONFIG_SENSORS_EEPROM is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_RTC8564 is not set
-# CONFIG_SENSORS_M41T00 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
 
 #
 # Misc devices
@@ -813,14 +842,20 @@ CONFIG_USB_ARCH_HAS_OHCI=y
 # CONFIG_INFINIBAND is not set
 
 #
+# SN Devices
+#
+
+#
 # File systems
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
 # CONFIG_EXT3_FS is not set
 # CONFIG_JBD is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
 
 #
 # XFS support
@@ -828,6 +863,7 @@ CONFIG_EXT2_FS=y
 # CONFIG_XFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
 # CONFIG_QUOTA is not set
 CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
@@ -854,7 +890,6 @@ CONFIG_ISO9660_FS=y
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
 # CONFIG_DEVPTS_FS_XATTR is not set
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_XATTR is not set
@@ -874,8 +909,7 @@ CONFIG_RAMFS=y
 # CONFIG_JFFS_FS is not set
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_DEBUG=0
-# CONFIG_JFFS2_FS_NAND is not set
-# CONFIG_JFFS2_FS_NOR_ECC is not set
+CONFIG_JFFS2_FS_WRITEBUFFER=y
 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
 CONFIG_JFFS2_ZLIB=y
 CONFIG_JFFS2_RTIME=y
@@ -892,12 +926,14 @@ CONFIG_JFFS2_RTIME=y
 #
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
 # CONFIG_NFS_DIRECTIO is not set
 # CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
diff --git a/arch/ppc/configs/sandpoint_defconfig b/arch/ppc/configs/sandpoint_defconfig
index 0f4393a07f8..fb493a67c60 100644
--- a/arch/ppc/configs/sandpoint_defconfig
+++ b/arch/ppc/configs/sandpoint_defconfig
@@ -437,7 +437,7 @@ CONFIG_SOUND_GAMEPORT=y
 #
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_NR_UARTS=4
 # CONFIG_SERIAL_8250_EXTENDED is not set
 
 #
diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c
index 50936cda0af..8a3d74f2531 100644
--- a/arch/ppc/kernel/cputable.c
+++ b/arch/ppc/kernel/cputable.c
@@ -852,6 +852,26 @@ struct cpu_spec	cpu_specs[] = {
 
 #endif /* CONFIG_40x */
 #ifdef CONFIG_44x
+	{
+		.pvr_mask		= 0xf0000fff,
+		.pvr_value		= 0x40000850,
+		.cpu_name		= "440EP Rev. A",
+		.cpu_features		= CPU_FTR_SPLIT_ID_CACHE |
+			CPU_FTR_USE_TB,
+		.cpu_user_features	= COMMON_PPC, /* 440EP has an FPU */
+		.icache_bsize		= 32,
+		.dcache_bsize		= 32,
+	},
+	{
+		.pvr_mask		= 0xf0000fff,
+		.pvr_value		= 0x400008d3,
+		.cpu_name		= "440EP Rev. B",
+		.cpu_features		= CPU_FTR_SPLIT_ID_CACHE |
+			CPU_FTR_USE_TB,
+		.cpu_user_features	= COMMON_PPC, /* 440EP has an FPU */
+		.icache_bsize		= 32,
+		.dcache_bsize		= 32,
+	},
 	{ 	/* 440GP Rev. B */
 		.pvr_mask		= 0xf0000fff,
 		.pvr_value		= 0x40000440,
diff --git a/arch/ppc/kernel/entry.S b/arch/ppc/kernel/entry.S
index d4df68629cc..cb83045e2ed 100644
--- a/arch/ppc/kernel/entry.S
+++ b/arch/ppc/kernel/entry.S
@@ -215,6 +215,7 @@ syscall_dotrace_cont:
 	lwzx	r10,r10,r0	/* Fetch system call handler [ptr] */
 	mtlr	r10
 	addi	r9,r1,STACK_FRAME_OVERHEAD
+	PPC440EP_ERR42
 	blrl			/* Call handler */
 	.globl	ret_from_syscall
 ret_from_syscall:
diff --git a/arch/ppc/kernel/head_44x.S b/arch/ppc/kernel/head_44x.S
index 6c7ae605246..69ff3a9961e 100644
--- a/arch/ppc/kernel/head_44x.S
+++ b/arch/ppc/kernel/head_44x.S
@@ -179,24 +179,26 @@ skpinv:	addi	r4,r4,1				/* Increment */
 4:
 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 	/*
-	 * Add temporary UART mapping for early debug.  This
-	 * mapping must be identical to that used by the early
-	 * bootloader code since the same asm/serial.h parameters
-	 * are used for polled operation.
+	 * Add temporary UART mapping for early debug.
+	 * We can map UART registers wherever we want as long as they don't
+	 * interfere with other system mappings (e.g. with pinned entries).
+	 * For an example of how we handle this - see ocotea.h.       --ebs
 	 */
  	/* pageid fields */
 	lis	r3,UART0_IO_BASE@h
-	ori	r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M
+	ori	r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_4K
 
 	/* xlat fields */
 	lis	r4,UART0_PHYS_IO_BASE@h		/* RPN depends on SoC */
+#ifndef CONFIG_440EP
 	ori	r4,r4,0x0001		/* ERPN is 1 for second 4GB page */
+#endif
 
 	/* attrib fields */
 	li	r5,0
 	ori	r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_I | PPC44x_TLB_G)
 
-        li      r0,1                    /* TLB slot 1 */
+        li      r0,0                    /* TLB slot 0 */
 
 	tlbwe	r3,r0,PPC44x_TLB_PAGEID	/* Load the pageid fields */
 	tlbwe	r4,r0,PPC44x_TLB_XLAT	/* Load the translation fields */
@@ -228,6 +230,16 @@ skpinv:	addi	r4,r4,1				/* Increment */
 	lis	r4,interrupt_base@h	/* IVPR only uses the high 16-bits */
 	mtspr	SPRN_IVPR,r4
 
+#ifdef CONFIG_440EP
+	/* Clear DAPUIB flag in CCR0 (enable APU between CPU and FPU) */
+	mfspr	r2,SPRN_CCR0
+	lis	r3,0xffef
+	ori	r3,r3,0xffff
+	and	r2,r2,r3
+	mtspr	SPRN_CCR0,r2
+	isync
+#endif
+
 	/*
 	 * This is where the main kernel code starts.
 	 */
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 5a7a64e91fc..eb18cadb375 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -288,13 +288,11 @@ SystemCall:
  * For the MPC8xx, this is a software tablewalk to load the instruction
  * TLB.  It is modelled after the example in the Motorola manual.  The task
  * switch loads the M_TWB register with the pointer to the first level table.
- * If we discover there is no second level table (the value is zero), the
- * plan was to load that into the TLB, which causes another fault into the
- * TLB Error interrupt where we can handle such problems.  However, that did
- * not work, so if we discover there is no second level table, we restore
- * registers and branch to the error exception.  We have to use the MD_xxx
- * registers for the tablewalk because the equivalent MI_xxx registers
- * only perform the attribute functions.
+ * If we discover there is no second level table (value is zero) or if there
+ * is an invalid pte, we load that into the TLB, which causes another fault
+ * into the TLB Error interrupt where we can handle such problems.
+ * We have to use the MD_xxx registers for the tablewalk because the
+ * equivalent MI_xxx registers only perform the attribute functions.
  */
 InstructionTLBMiss:
 #ifdef CONFIG_8xx_CPU6
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index 191a8def3bd..ce71b4a0158 100644
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -1145,6 +1145,7 @@ _GLOBAL(kernel_thread)
 	stwu	r0,-16(r1)
 	mtlr	r30		/* fn addr in lr */
 	mr	r3,r31		/* load arg and call fn */
+	PPC440EP_ERR42
 	blrl
 	li	r0,__NR_exit	/* exit if function returns */
 	li	r3,0
@@ -1451,3 +1452,6 @@ _GLOBAL(sys_call_table)
 	.long sys_waitid
 	.long sys_ioprio_set
 	.long sys_ioprio_get
+	.long sys_inotify_init		/* 275 */
+	.long sys_inotify_add_watch
+	.long sys_inotify_rm_watch
diff --git a/arch/ppc/kernel/pci.c b/arch/ppc/kernel/pci.c
index 70cfb6ffd87..7b3586a3bf3 100644
--- a/arch/ppc/kernel/pci.c
+++ b/arch/ppc/kernel/pci.c
@@ -160,6 +160,21 @@ void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 }
 EXPORT_SYMBOL(pcibios_resource_to_bus);
 
+void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+			     struct pci_bus_region *region)
+{
+	unsigned long offset = 0;
+	struct pci_controller *hose = dev->sysdata;
+
+	if (hose && res->flags & IORESOURCE_IO)
+		offset = (unsigned long)hose->io_base_virt - isa_io_base;
+	else if (hose && res->flags & IORESOURCE_MEM)
+		offset = hose->pci_mem_offset;
+	res->start = region->start + offset;
+	res->end = region->end + offset;
+}
+EXPORT_SYMBOL(pcibios_bus_to_resource);
+
 /*
  * We need to avoid collisions with `mirrored' VGA ports
  * and other strange ISA hardware, so we always want the
diff --git a/arch/ppc/kernel/ppc_ksyms.c b/arch/ppc/kernel/ppc_ksyms.c
index d59ad07de8e..e7d40cc6c1b 100644
--- a/arch/ppc/kernel/ppc_ksyms.c
+++ b/arch/ppc/kernel/ppc_ksyms.c
@@ -324,7 +324,7 @@ EXPORT_SYMBOL(__res);
 
 EXPORT_SYMBOL(next_mmu_context);
 EXPORT_SYMBOL(set_context);
-EXPORT_SYMBOL(handle_mm_fault); /* For MOL */
+EXPORT_SYMBOL_GPL(__handle_mm_fault); /* For MOL */
 EXPORT_SYMBOL(disarm_decr);
 #ifdef CONFIG_PPC_STD_MMU
 extern long mol_trampoline;
diff --git a/arch/ppc/mm/init.c b/arch/ppc/mm/init.c
index 6164a2b3473..33ada72c733 100644
--- a/arch/ppc/mm/init.c
+++ b/arch/ppc/mm/init.c
@@ -562,6 +562,9 @@ void flush_dcache_icache_page(struct page *page)
 #ifdef CONFIG_BOOKE
 	__flush_dcache_icache(kmap(page));
 	kunmap(page);
+#elif CONFIG_8xx
+	/* On 8xx there is no need to kmap since highmem is not supported */
+	__flush_dcache_icache(page_address(page)); 
 #else
 	__flush_dcache_icache_phys(page_to_pfn(page) << PAGE_SHIFT);
 #endif
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
index a0612a86455..f7c045764e0 100644
--- a/arch/ppc/platforms/4xx/Kconfig
+++ b/arch/ppc/platforms/4xx/Kconfig
@@ -68,6 +68,11 @@ choice
 	depends on 44x
 	default EBONY
 
+config BAMBOO
+	bool "Bamboo"
+	help
+	  This option enables support for the IBM PPC440EP evaluation board.
+
 config EBONY
 	bool "Ebony"
 	help
@@ -98,6 +103,12 @@ config NP405H
 	depends on ASH
 	default y
 
+config 440EP
+	bool
+	depends on BAMBOO
+	select PPC_FPU
+	default y
+
 config 440GP
 	bool
 	depends on EBONY
@@ -115,7 +126,7 @@ config 440SP
 
 config 440
 	bool
-	depends on 440GP || 440SP
+	depends on 440GP || 440SP || 440EP
 	default y
 
 config 440A
@@ -123,6 +134,11 @@ config 440A
 	depends on 440GX
 	default y
 
+config IBM440EP_ERR42
+	bool
+	depends on 440EP
+	default y
+
 # All 405-based cores up until the 405GPR and 405EP have this errata.
 config IBM405_ERR77
 	bool
@@ -142,7 +158,7 @@ config BOOKE
 
 config IBM_OCP
 	bool
-	depends on ASH || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
+	depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
 	default y
 
 config XILINX_OCP
diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile
index ea470c6adbb..844c3b5066e 100644
--- a/arch/ppc/platforms/4xx/Makefile
+++ b/arch/ppc/platforms/4xx/Makefile
@@ -2,6 +2,7 @@
 # Makefile for the PowerPC 4xx linux kernel.
 
 obj-$(CONFIG_ASH)		+= ash.o
+obj-$(CONFIG_BAMBOO)		+= bamboo.o
 obj-$(CONFIG_CPCI405)		+= cpci405.o
 obj-$(CONFIG_EBONY)		+= ebony.o
 obj-$(CONFIG_EP405)		+= ep405.o
@@ -19,6 +20,7 @@ obj-$(CONFIG_405GP)		+= ibm405gp.o
 obj-$(CONFIG_REDWOOD_5)		+= ibmstb4.o
 obj-$(CONFIG_NP405H)		+= ibmnp405h.o
 obj-$(CONFIG_REDWOOD_6)		+= ibmstbx25.o
+obj-$(CONFIG_440EP)		+= ibm440ep.o
 obj-$(CONFIG_440GP)		+= ibm440gp.o
 obj-$(CONFIG_440GX)		+= ibm440gx.o
 obj-$(CONFIG_440SP)		+= ibm440sp.o
diff --git a/arch/ppc/platforms/4xx/bamboo.c b/arch/ppc/platforms/4xx/bamboo.c
new file mode 100644
index 00000000000..f116787b0b7
--- /dev/null
+++ b/arch/ppc/platforms/4xx/bamboo.c
@@ -0,0 +1,427 @@
+/*
+ * arch/ppc/platforms/4xx/bamboo.c
+ *
+ * Bamboo board specific routines
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ * Copyright 2004 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/types.h>
+#include <linux/major.h>
+#include <linux/blkdev.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/ide.h>
+#include <linux/initrd.h>
+#include <linux/irq.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/ethtool.h>
+
+#include <asm/system.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/ocp.h>
+#include <asm/pci-bridge.h>
+#include <asm/time.h>
+#include <asm/todc.h>
+#include <asm/bootinfo.h>
+#include <asm/ppc4xx_pic.h>
+#include <asm/ppcboot.h>
+
+#include <syslib/gen550.h>
+#include <syslib/ibm440gx_common.h>
+
+/*
+ * This is a horrible kludge, we eventually need to abstract this
+ * generic PHY stuff, so the  standard phy mode defines can be
+ * easily used from arch code.
+ */
+#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
+
+bd_t __res;
+
+static struct ibm44x_clocks clocks __initdata;
+
+/*
+ * Bamboo external IRQ triggering/polarity settings
+ */
+unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: Ethernet transceiver */
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ1: Expansion connector */
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 0 */
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 1 */
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ4: PCI slot 2 */
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ5: PCI slot 3 */
+	(IRQ_SENSE_EDGE  | IRQ_POLARITY_NEGATIVE), /* IRQ6: SMI pushbutton */
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ7: EXT */
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
+	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
+};
+
+static void __init
+bamboo_calibrate_decr(void)
+{
+	unsigned int freq;
+
+	if (mfspr(SPRN_CCR1) & CCR1_TCS)
+		freq = BAMBOO_TMRCLK;
+	else
+		freq = clocks.cpu;
+
+	ibm44x_calibrate_decr(freq);
+
+}
+
+static int
+bamboo_show_cpuinfo(struct seq_file *m)
+{
+	seq_printf(m, "vendor\t\t: IBM\n");
+	seq_printf(m, "machine\t\t: PPC440EP EVB (Bamboo)\n");
+
+	return 0;
+}
+
+static inline int
+bamboo_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+	static char pci_irq_table[][4] =
+	/*
+	 *	PCI IDSEL/INTPIN->INTLINE
+	 * 	   A   B   C   D
+	 */
+	{
+		{ 28, 28, 28, 28 },	/* IDSEL 1 - PCI Slot 0 */
+		{ 27, 27, 27, 27 },	/* IDSEL 2 - PCI Slot 1 */
+		{ 26, 26, 26, 26 },	/* IDSEL 3 - PCI Slot 2 */
+		{ 25, 25, 25, 25 },	/* IDSEL 4 - PCI Slot 3 */
+	};
+
+	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
+	return PCI_IRQ_TABLE_LOOKUP;
+}
+
+static void __init bamboo_set_emacdata(void)
+{
+	unsigned char * selection1_base;
+	struct ocp_def *def;
+	struct ocp_func_emac_data *emacdata;
+	u8 selection1_val;
+	int mode;
+
+	selection1_base = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16);
+	selection1_val = readb(selection1_base);
+	iounmap((void *) selection1_base);
+	if (BAMBOO_SEL_MII(selection1_val))
+		mode = PHY_MODE_MII;
+	else if (BAMBOO_SEL_RMII(selection1_val))
+		mode = PHY_MODE_RMII;
+	else
+		mode = PHY_MODE_SMII;
+
+	/* Set mac_addr and phy mode for each EMAC */
+
+	def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
+	emacdata = def->additions;
+	memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
+	emacdata->phy_mode = mode;
+
+	def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
+	emacdata = def->additions;
+	memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
+	emacdata->phy_mode = mode;
+}
+
+static int
+bamboo_exclude_device(unsigned char bus, unsigned char devfn)
+{
+	return (bus == 0 && devfn == 0);
+}
+
+#define PCI_READW(offset) \
+        (readw((void *)((u32)pci_reg_base+offset)))
+
+#define PCI_WRITEW(value, offset) \
+	(writew(value, (void *)((u32)pci_reg_base+offset)))
+
+#define PCI_WRITEL(value, offset) \
+	(writel(value, (void *)((u32)pci_reg_base+offset)))
+
+static void __init
+bamboo_setup_pci(void)
+{
+	void *pci_reg_base;
+	unsigned long memory_size;
+	memory_size = ppc_md.find_end_of_memory();
+
+	pci_reg_base = ioremap64(BAMBOO_PCIL0_BASE, BAMBOO_PCIL0_SIZE);
+
+	/* Enable PCI I/O, Mem, and Busmaster cycles */
+	PCI_WRITEW(PCI_READW(PCI_COMMAND) |
+		   PCI_COMMAND_MEMORY |
+		   PCI_COMMAND_MASTER, PCI_COMMAND);
+
+	/* Disable region first */
+	PCI_WRITEL(0, BAMBOO_PCIL0_PMM0MA);
+
+	/* PLB starting addr: 0x00000000A0000000 */
+	PCI_WRITEL(BAMBOO_PCI_PHY_MEM_BASE, BAMBOO_PCIL0_PMM0LA);
+
+	/* PCI start addr, 0xA0000000 (PCI Address) */
+	PCI_WRITEL(BAMBOO_PCI_MEM_BASE, BAMBOO_PCIL0_PMM0PCILA);
+	PCI_WRITEL(0, BAMBOO_PCIL0_PMM0PCIHA);
+
+	/* Enable no pre-fetch, enable region */
+	PCI_WRITEL(((0xffffffff -
+		     (BAMBOO_PCI_UPPER_MEM - BAMBOO_PCI_MEM_BASE)) | 0x01),
+		      BAMBOO_PCIL0_PMM0MA);
+
+	/* Disable region one */
+	PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
+	PCI_WRITEL(0, BAMBOO_PCIL0_PMM1LA);
+	PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCILA);
+	PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCIHA);
+	PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
+
+	/* Disable region two */
+	PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
+	PCI_WRITEL(0, BAMBOO_PCIL0_PMM2LA);
+	PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCILA);
+	PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCIHA);
+	PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
+
+	/* Now configure the PCI->PLB windows, we only use PTM1
+	 *
+	 * For Inbound flow, set the window size to all available memory
+	 * This is required because if size is smaller,
+	 * then Eth/PCI DD would fail as PCI card not able to access
+	 * the memory allocated by DD.
+	 */
+
+	PCI_WRITEL(0, BAMBOO_PCIL0_PTM1MS);	/* disabled region 1 */
+	PCI_WRITEL(0, BAMBOO_PCIL0_PTM1LA);	/* begin of address map */
+
+	memory_size = 1 << fls(memory_size - 1);
+
+	/* Size low + Enabled */
+	PCI_WRITEL((0xffffffff - (memory_size - 1)) | 0x1, BAMBOO_PCIL0_PTM1MS);
+
+	eieio();
+	iounmap(pci_reg_base);
+}
+
+static void __init
+bamboo_setup_hose(void)
+{
+	unsigned int bar_response, bar;
+	struct pci_controller *hose;
+
+	bamboo_setup_pci();
+
+	hose = pcibios_alloc_controller();
+
+	if (!hose)
+		return;
+
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	hose->pci_mem_offset = BAMBOO_PCI_MEM_OFFSET;
+
+	pci_init_resource(&hose->io_resource,
+			BAMBOO_PCI_LOWER_IO,
+			BAMBOO_PCI_UPPER_IO,
+			IORESOURCE_IO,
+			"PCI host bridge");
+
+	pci_init_resource(&hose->mem_resources[0],
+			BAMBOO_PCI_LOWER_MEM,
+			BAMBOO_PCI_UPPER_MEM,
+			IORESOURCE_MEM,
+			"PCI host bridge");
+
+	ppc_md.pci_exclude_device = bamboo_exclude_device;
+
+	hose->io_space.start = BAMBOO_PCI_LOWER_IO;
+	hose->io_space.end = BAMBOO_PCI_UPPER_IO;
+	hose->mem_space.start = BAMBOO_PCI_LOWER_MEM;
+	hose->mem_space.end = BAMBOO_PCI_UPPER_MEM;
+	isa_io_base =
+		(unsigned long)ioremap64(BAMBOO_PCI_IO_BASE, BAMBOO_PCI_IO_SIZE);
+	hose->io_base_virt = (void *)isa_io_base;
+
+	setup_indirect_pci(hose,
+			BAMBOO_PCI_CFGA_PLB32,
+			BAMBOO_PCI_CFGD_PLB32);
+	hose->set_cfg_type = 1;
+
+	/* Zero config bars */
+	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
+		early_write_config_dword(hose, hose->first_busno,
+					 PCI_FUNC(hose->first_busno), bar,
+					 0x00000000);
+		early_read_config_dword(hose, hose->first_busno,
+					PCI_FUNC(hose->first_busno), bar,
+					&bar_response);
+	}
+
+	hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
+
+	ppc_md.pci_swizzle = common_swizzle;
+	ppc_md.pci_map_irq = bamboo_map_irq;
+}
+
+TODC_ALLOC();
+
+static void __init
+bamboo_early_serial_map(void)
+{
+	struct uart_port port;
+
+	/* Setup ioremapped serial port access */
+	memset(&port, 0, sizeof(port));
+	port.membase = ioremap64(PPC440EP_UART0_ADDR, 8);
+	port.irq = 0;
+	port.uartclk = clocks.uart0;
+	port.regshift = 0;
+	port.iotype = SERIAL_IO_MEM;
+	port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
+	port.line = 0;
+
+	if (early_serial_setup(&port) != 0) {
+		printk("Early serial init of port 0 failed\n");
+	}
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+	/* Configure debug serial access */
+	gen550_init(0, &port);
+#endif
+
+	port.membase = ioremap64(PPC440EP_UART1_ADDR, 8);
+	port.irq = 1;
+	port.uartclk = clocks.uart1;
+	port.line = 1;
+
+	if (early_serial_setup(&port) != 0) {
+		printk("Early serial init of port 1 failed\n");
+	}
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+	/* Configure debug serial access */
+	gen550_init(1, &port);
+#endif
+
+	port.membase = ioremap64(PPC440EP_UART2_ADDR, 8);
+	port.irq = 3;
+	port.uartclk = clocks.uart2;
+	port.line = 2;
+
+	if (early_serial_setup(&port) != 0) {
+		printk("Early serial init of port 2 failed\n");
+	}
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+	/* Configure debug serial access */
+	gen550_init(2, &port);
+#endif
+
+	port.membase = ioremap64(PPC440EP_UART3_ADDR, 8);
+	port.irq = 4;
+	port.uartclk = clocks.uart3;
+	port.line = 3;
+
+	if (early_serial_setup(&port) != 0) {
+		printk("Early serial init of port 3 failed\n");
+	}
+}
+
+static void __init
+bamboo_setup_arch(void)
+{
+
+	bamboo_set_emacdata();
+
+	ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
+	ocp_sys_info.opb_bus_freq = clocks.opb;
+
+	/* Setup TODC access */
+	TODC_INIT(TODC_TYPE_DS1743,
+			0,
+			0,
+			ioremap64(BAMBOO_RTC_ADDR, BAMBOO_RTC_SIZE),
+			8);
+
+	/* init to some ~sane value until calibrate_delay() runs */
+        loops_per_jiffy = 50000000/HZ;
+
+	/* Setup PCI host bridge */
+	bamboo_setup_hose();
+
+#ifdef CONFIG_BLK_DEV_INITRD
+	if (initrd_start)
+		ROOT_DEV = Root_RAM0;
+	else
+#endif
+#ifdef CONFIG_ROOT_NFS
+		ROOT_DEV = Root_NFS;
+#else
+		ROOT_DEV = Root_HDA1;
+#endif
+
+	bamboo_early_serial_map();
+
+	/* Identify the system */
+	printk("IBM Bamboo port (MontaVista Software, Inc. (source@mvista.com))\n");
+}
+
+void __init platform_init(unsigned long r3, unsigned long r4,
+		unsigned long r5, unsigned long r6, unsigned long r7)
+{
+	parse_bootinfo(find_bootinfo());
+
+	/*
+	 * If we were passed in a board information, copy it into the
+	 * residual data area.
+	 */
+	if (r3)
+		__res = *(bd_t *)(r3 + KERNELBASE);
+
+
+	ibm44x_platform_init();
+
+	ppc_md.setup_arch = bamboo_setup_arch;
+	ppc_md.show_cpuinfo = bamboo_show_cpuinfo;
+	ppc_md.get_irq = NULL;		/* Set in ppc4xx_pic_init() */
+
+	ppc_md.calibrate_decr = bamboo_calibrate_decr;
+	ppc_md.time_init = todc_time_init;
+	ppc_md.set_rtc_time = todc_set_rtc_time;
+	ppc_md.get_rtc_time = todc_get_rtc_time;
+
+	ppc_md.nvram_read_val = todc_direct_read_val;
+	ppc_md.nvram_write_val = todc_direct_write_val;
+#ifdef CONFIG_KGDB
+	ppc_md.early_serial_map = bamboo_early_serial_map;
+#endif
+}
+
diff --git a/arch/ppc/platforms/4xx/bamboo.h b/arch/ppc/platforms/4xx/bamboo.h
new file mode 100644
index 00000000000..63d71450414
--- /dev/null
+++ b/arch/ppc/platforms/4xx/bamboo.h
@@ -0,0 +1,136 @@
+/*
+ * arch/ppc/platforms/bamboo.h
+ *
+ * Bamboo board definitions
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ *
+ * Copyright 2004 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_BAMBOO_H__
+#define __ASM_BAMBOO_H__
+
+#include <linux/config.h>
+#include <platforms/4xx/ibm440ep.h>
+
+/* F/W TLB mapping used in bootloader glue to reset EMAC */
+#define PPC44x_EMAC0_MR0		0x0EF600E00
+
+/* Location of MAC addresses in PIBS image */
+#define PIBS_FLASH_BASE			0xfff00000
+#define PIBS_MAC_BASE			(PIBS_FLASH_BASE+0xc0400)
+#define PIBS_MAC_SIZE			0x200
+#define PIBS_MAC_OFFSET			0x100
+
+/* Default clock rate */
+#define BAMBOO_TMRCLK			25000000
+
+/* RTC/NVRAM location */
+#define BAMBOO_RTC_ADDR			0x080000000ULL
+#define BAMBOO_RTC_SIZE			0x2000
+
+/* FPGA Registers */
+#define BAMBOO_FPGA_ADDR		0x080002000ULL
+
+#define BAMBOO_FPGA_CONFIG2_REG_ADDR	(BAMBOO_FPGA_ADDR + 0x1)
+#define BAMBOO_FULL_DUPLEX_EN(x)	(x & 0x08)
+#define BAMBOO_FORCE_100Mbps(x)		(x & 0x04)
+#define BAMBOO_AUTONEGOTIATE(x)		(x & 0x02)
+
+#define BAMBOO_FPGA_SETTING_REG_ADDR	(BAMBOO_FPGA_ADDR + 0x3)
+#define BAMBOO_BOOT_SMALL_FLASH(x)	(!(x & 0x80))
+#define BAMBOO_LARGE_FLASH_EN(x)	(!(x & 0x40))
+#define BAMBOO_BOOT_NAND_FLASH(x)	(!(x & 0x20))
+
+#define BAMBOO_FPGA_SELECTION1_REG_ADDR (BAMBOO_FPGA_ADDR + 0x4)
+#define BAMBOO_SEL_MII(x)		(x & 0x80)
+#define BAMBOO_SEL_RMII(x)		(x & 0x40)
+#define BAMBOO_SEL_SMII(x)		(x & 0x20)
+
+/* Flash */
+#define BAMBOO_SMALL_FLASH_LOW		0x087f00000ULL
+#define BAMBOO_SMALL_FLASH_HIGH		0x0fff00000ULL
+#define BAMBOO_SMALL_FLASH_SIZE		0x100000
+#define BAMBOO_LARGE_FLASH_LOW		0x087800000ULL
+#define BAMBOO_LARGE_FLASH_HIGH1	0x0ff800000ULL
+#define BAMBOO_LARGE_FLASH_HIGH2	0x0ffc00000ULL
+#define BAMBOO_LARGE_FLASH_SIZE		0x400000
+#define BAMBOO_SRAM_LOW			0x087f00000ULL
+#define BAMBOO_SRAM_HIGH1		0x0fff00000ULL
+#define BAMBOO_SRAM_HIGH2		0x0ff800000ULL
+#define BAMBOO_SRAM_SIZE		0x100000
+#define BAMBOO_NAND_FLASH_REG_ADDR	0x090000000ULL
+#define BAMBOO_NAND_FLASH_REG_SIZE	0x2000
+
+/*
+ * Serial port defines
+ */
+#define RS_TABLE_SIZE			4
+
+#define UART0_IO_BASE			0xEF600300
+#define UART1_IO_BASE			0xEF600400
+#define UART2_IO_BASE			0xEF600500
+#define UART3_IO_BASE			0xEF600600
+
+#define BASE_BAUD			33177600/3/16
+#define UART0_INT			0
+#define UART1_INT			1
+#define UART2_INT			3
+#define UART3_INT			4
+
+#define STD_UART_OP(num)					\
+	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
+		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
+		iomem_base: UART##num##_IO_BASE,		\
+		io_type: SERIAL_IO_MEM},
+
+#define SERIAL_PORT_DFNS	\
+	STD_UART_OP(0)		\
+	STD_UART_OP(1)		\
+	STD_UART_OP(2)		\
+	STD_UART_OP(3)
+
+/* PCI support */
+#define BAMBOO_PCI_CFGA_PLB32		0xeec00000
+#define BAMBOO_PCI_CFGD_PLB32		0xeec00004
+
+#define BAMBOO_PCI_IO_BASE		0x00000000e8000000ULL
+#define BAMBOO_PCI_IO_SIZE		0x00010000
+#define BAMBOO_PCI_MEM_OFFSET		0x00000000
+#define BAMBOO_PCI_PHY_MEM_BASE		0x00000000a0000000ULL
+
+#define BAMBOO_PCI_LOWER_IO		0x00000000
+#define BAMBOO_PCI_UPPER_IO		0x0000ffff
+#define BAMBOO_PCI_LOWER_MEM		0xa0000000
+#define BAMBOO_PCI_UPPER_MEM		0xafffffff
+#define BAMBOO_PCI_MEM_BASE		0xa0000000
+
+#define BAMBOO_PCIL0_BASE		0x00000000ef400000ULL
+#define BAMBOO_PCIL0_SIZE		0x40
+
+#define BAMBOO_PCIL0_PMM0LA		0x000
+#define BAMBOO_PCIL0_PMM0MA		0x004
+#define BAMBOO_PCIL0_PMM0PCILA		0x008
+#define BAMBOO_PCIL0_PMM0PCIHA		0x00C
+#define BAMBOO_PCIL0_PMM1LA		0x010
+#define BAMBOO_PCIL0_PMM1MA		0x014
+#define BAMBOO_PCIL0_PMM1PCILA		0x018
+#define BAMBOO_PCIL0_PMM1PCIHA		0x01C
+#define BAMBOO_PCIL0_PMM2LA		0x020
+#define BAMBOO_PCIL0_PMM2MA		0x024
+#define BAMBOO_PCIL0_PMM2PCILA		0x028
+#define BAMBOO_PCIL0_PMM2PCIHA		0x02C
+#define BAMBOO_PCIL0_PTM1MS		0x030
+#define BAMBOO_PCIL0_PTM1LA		0x034
+#define BAMBOO_PCIL0_PTM2MS		0x038
+#define BAMBOO_PCIL0_PTM2LA		0x03C
+
+#endif                          /* __ASM_BAMBOO_H__ */
+#endif                          /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c
index cd11734ef7c..509e69a095f 100644
--- a/arch/ppc/platforms/4xx/ebony.c
+++ b/arch/ppc/platforms/4xx/ebony.c
@@ -7,7 +7,7 @@
  * Copyright 2002-2005 MontaVista Software Inc.
  *
  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
- * Copyright (c) 2003, 2004 Zultys Technologies
+ * Copyright (c) 2003-2005 Zultys Technologies
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -50,6 +50,7 @@
 #include <asm/bootinfo.h>
 #include <asm/ppc4xx_pic.h>
 #include <asm/ppcboot.h>
+#include <asm/tlbflush.h>
 
 #include <syslib/gen550.h>
 #include <syslib/ibm440gp_common.h>
@@ -248,6 +249,9 @@ ebony_early_serial_map(void)
 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 	/* Configure debug serial access */
 	gen550_init(0, &port);
+
+	/* Purge TLB entry added in head_44x.S for early serial access */
+	_tlbie(UART0_IO_BASE);
 #endif
 
 	port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
diff --git a/arch/ppc/platforms/4xx/ebony.h b/arch/ppc/platforms/4xx/ebony.h
index 47c391c9174..d08faa46a0a 100644
--- a/arch/ppc/platforms/4xx/ebony.h
+++ b/arch/ppc/platforms/4xx/ebony.h
@@ -56,9 +56,18 @@
  * Serial port defines
  */
 
-/* OpenBIOS defined UART mappings, used before early_serial_setup */
+#if defined(__BOOTER__)
+/* OpenBIOS defined UART mappings, used by bootloader shim */
 #define UART0_IO_BASE	0xE0000200
 #define UART1_IO_BASE	0xE0000300
+#else
+/* head_44x.S created UART mapping, used before early_serial_setup.
+ * We cannot use default OpenBIOS UART mappings because they
+ * don't work for configurations with more than 512M RAM.    --ebs
+ */
+#define UART0_IO_BASE	0xF0000200
+#define UART1_IO_BASE	0xF0000300
+#endif
 
 /* external Epson SG-615P */
 #define BASE_BAUD	691200
@@ -66,7 +75,7 @@
 #define STD_UART_OP(num)					\
 	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
 		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: UART##num##_IO_BASE,		\
+		iomem_base: (void*)UART##num##_IO_BASE,		\
 		io_type: SERIAL_IO_MEM},
 
 #define SERIAL_PORT_DFNS	\
diff --git a/arch/ppc/platforms/4xx/ibm440ep.c b/arch/ppc/platforms/4xx/ibm440ep.c
new file mode 100644
index 00000000000..284da01f1ff
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibm440ep.c
@@ -0,0 +1,220 @@
+/*
+ * arch/ppc/platforms/4xx/ibm440ep.c
+ *
+ * PPC440EP I/O descriptions
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ * Copyright 2004 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <platforms/4xx/ibm440ep.h>
+#include <asm/ocp.h>
+#include <asm/ppc4xx_pic.h>
+
+static struct ocp_func_emac_data ibm440ep_emac0_def = {
+	.rgmii_idx	= -1,           /* No RGMII */
+	.rgmii_mux	= -1,           /* No RGMII */
+	.zmii_idx       = 0,            /* ZMII device index */
+	.zmii_mux       = 0,            /* ZMII input of this EMAC */
+	.mal_idx        = 0,            /* MAL device index */
+	.mal_rx_chan    = 0,            /* MAL rx channel number */
+	.mal_tx_chan    = 0,            /* MAL tx channel number */
+	.wol_irq        = 61,		/* WOL interrupt number */
+	.mdio_idx       = -1,           /* No shared MDIO */
+	.tah_idx	= -1,           /* No TAH */
+};
+
+static struct ocp_func_emac_data ibm440ep_emac1_def = {
+	.rgmii_idx	= -1,           /* No RGMII */
+	.rgmii_mux	= -1,           /* No RGMII */
+	.zmii_idx       = 0,            /* ZMII device index */
+	.zmii_mux       = 1,            /* ZMII input of this EMAC */
+	.mal_idx        = 0,            /* MAL device index */
+	.mal_rx_chan    = 1,            /* MAL rx channel number */
+	.mal_tx_chan    = 2,            /* MAL tx channel number */
+	.wol_irq        = 63,  		/* WOL interrupt number */
+	.mdio_idx       = -1,           /* No shared MDIO */
+	.tah_idx	= -1,           /* No TAH */
+};
+OCP_SYSFS_EMAC_DATA()
+
+static struct ocp_func_mal_data ibm440ep_mal0_def = {
+	.num_tx_chans   = 4,  		/* Number of TX channels */
+	.num_rx_chans   = 2,    	/* Number of RX channels */
+	.txeob_irq	= 10,		/* TX End Of Buffer IRQ  */
+	.rxeob_irq	= 11,		/* RX End Of Buffer IRQ  */
+	.txde_irq	= 33,		/* TX Descriptor Error IRQ */
+	.rxde_irq	= 34,		/* RX Descriptor Error IRQ */
+	.serr_irq	= 32,		/* MAL System Error IRQ    */
+};
+OCP_SYSFS_MAL_DATA()
+
+static struct ocp_func_iic_data ibm440ep_iic0_def = {
+	.fast_mode	= 0,		/* Use standad mode (100Khz) */
+};
+
+static struct ocp_func_iic_data ibm440ep_iic1_def = {
+	.fast_mode	= 0,		/* Use standad mode (100Khz) */
+};
+OCP_SYSFS_IIC_DATA()
+
+struct ocp_def core_ocp[] = {
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_OPB,
+	  .index	= 0,
+	  .paddr	= 0x0EF600000ULL,
+	  .irq		= OCP_IRQ_NA,
+	  .pm		= OCP_CPM_NA,
+	},
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_16550,
+	  .index	= 0,
+	  .paddr	= PPC440EP_UART0_ADDR,
+	  .irq		= UART0_INT,
+	  .pm		= IBM_CPM_UART0,
+	},
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_16550,
+	  .index	= 1,
+	  .paddr	= PPC440EP_UART1_ADDR,
+	  .irq		= UART1_INT,
+	  .pm		= IBM_CPM_UART1,
+	},
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_16550,
+	  .index	= 2,
+	  .paddr	= PPC440EP_UART2_ADDR,
+	  .irq		= UART2_INT,
+	  .pm		= IBM_CPM_UART2,
+	},
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_16550,
+	  .index	= 3,
+	  .paddr	= PPC440EP_UART3_ADDR,
+	  .irq		= UART3_INT,
+	  .pm		= IBM_CPM_UART3,
+	},
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_IIC,
+	  .index	= 0,
+	  .paddr	= 0x0EF600700ULL,
+	  .irq		= 2,
+	  .pm		= IBM_CPM_IIC0,
+	  .additions	= &ibm440ep_iic0_def,
+	  .show		= &ocp_show_iic_data
+	},
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_IIC,
+	  .index	= 1,
+	  .paddr	= 0x0EF600800ULL,
+	  .irq		= 7,
+	  .pm		= IBM_CPM_IIC1,
+	  .additions	= &ibm440ep_iic1_def,
+	  .show		= &ocp_show_iic_data
+	},
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_GPIO,
+	  .index	= 0,
+	  .paddr	= 0x0EF600B00ULL,
+	  .irq		= OCP_IRQ_NA,
+	  .pm		= IBM_CPM_GPIO0,
+	},
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_GPIO,
+	  .index	= 1,
+	  .paddr	= 0x0EF600C00ULL,
+	  .irq		= OCP_IRQ_NA,
+	  .pm		= OCP_CPM_NA,
+	},
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_MAL,
+	  .paddr	= OCP_PADDR_NA,
+	  .irq		= OCP_IRQ_NA,
+	  .pm		= OCP_CPM_NA,
+	  .additions	= &ibm440ep_mal0_def,
+	  .show		= &ocp_show_mal_data,
+	},
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_EMAC,
+	  .index	= 0,
+	  .paddr	= 0x0EF600E00ULL,
+	  .irq		= 60,
+	  .pm		= OCP_CPM_NA,
+	  .additions	= &ibm440ep_emac0_def,
+	  .show		= &ocp_show_emac_data,
+	},
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_EMAC,
+	  .index	= 1,
+	  .paddr	= 0x0EF600F00ULL,
+	  .irq		= 62,
+	  .pm		= OCP_CPM_NA,
+	  .additions	= &ibm440ep_emac1_def,
+	  .show		= &ocp_show_emac_data,
+	},
+	{ .vendor	= OCP_VENDOR_IBM,
+	  .function	= OCP_FUNC_ZMII,
+	  .paddr	= 0x0EF600D00ULL,
+	  .irq		= OCP_IRQ_NA,
+	  .pm		= OCP_CPM_NA,
+	},
+	{ .vendor	= OCP_VENDOR_INVALID
+	}
+};
+
+/* Polarity and triggering settings for internal interrupt sources */
+struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
+	{ .polarity	= 0xffbffe03,
+	  .triggering   = 0xfffffe00,
+	  .ext_irq_mask = 0x000001fc,	/* IRQ0 - IRQ6 */
+	},
+	{ .polarity	= 0xffffc6ef,
+	  .triggering	= 0xffffc7ff,
+	  .ext_irq_mask = 0x00003800,	/* IRQ7 - IRQ9 */
+	},
+};
+
+static struct resource usb_gadget_resources[] = {
+	[0] = {
+		.start	= 0x050000100ULL,
+		.end 	= 0x05000017FULL,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= 55,
+		.end	= 55,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static u64 dma_mask = 0xffffffffULL;
+
+static struct platform_device usb_gadget_device = {
+	.name		= "musbhsfc",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(usb_gadget_resources),
+	.resource       = usb_gadget_resources,
+	.dev		= {
+		.dma_mask = &dma_mask,
+		.coherent_dma_mask = 0xffffffffULL,
+	}
+};
+
+static struct platform_device *ibm440ep_devs[] __initdata = {
+	&usb_gadget_device,
+};
+
+static int __init
+ibm440ep_platform_add_devices(void)
+{
+	return platform_add_devices(ibm440ep_devs, ARRAY_SIZE(ibm440ep_devs));
+}
+arch_initcall(ibm440ep_platform_add_devices);
+
diff --git a/arch/ppc/platforms/4xx/ibm440ep.h b/arch/ppc/platforms/4xx/ibm440ep.h
new file mode 100644
index 00000000000..97c80b8e3e1
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ibm440ep.h
@@ -0,0 +1,76 @@
+/*
+ * arch/ppc/platforms/4xx/ibm440ep.h
+ *
+ * PPC440EP definitions
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ *
+ * Copyright 2002 Roland Dreier
+ * Copyright 2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifdef __KERNEL__
+#ifndef __PPC_PLATFORMS_IBM440EP_H
+#define __PPC_PLATFORMS_IBM440EP_H
+
+#include <linux/config.h>
+#include <asm/ibm44x.h>
+
+/* UART */
+#define PPC440EP_UART0_ADDR		0x0EF600300
+#define PPC440EP_UART1_ADDR		0x0EF600400
+#define PPC440EP_UART2_ADDR		0x0EF600500
+#define PPC440EP_UART3_ADDR		0x0EF600600
+#define UART0_INT			0
+#define UART1_INT			1
+#define UART2_INT			3
+#define UART3_INT			4
+
+/* Clock and Power Management */
+#define IBM_CPM_IIC0		0x80000000	/* IIC interface */
+#define IBM_CPM_IIC1		0x40000000	/* IIC interface */
+#define IBM_CPM_PCI		0x20000000	/* PCI bridge */
+#define IBM_CPM_USB1H		0x08000000	/* USB 1.1 Host */
+#define IBM_CPM_FPU		0x04000000	/* floating point unit */
+#define IBM_CPM_CPU		0x02000000	/* processor core */
+#define IBM_CPM_DMA		0x01000000	/* DMA controller */
+#define IBM_CPM_BGO		0x00800000	/* PLB to OPB bus arbiter */
+#define IBM_CPM_BGI		0x00400000	/* OPB to PLB bridge */
+#define IBM_CPM_EBC		0x00200000	/* External Bus Controller */
+#define IBM_CPM_EBM		0x00100000	/* Ext Bus Master Interface */
+#define IBM_CPM_DMC		0x00080000	/* SDRAM peripheral controller */
+#define IBM_CPM_PLB4		0x00040000	/* PLB4 bus arbiter */
+#define IBM_CPM_PLB4x3		0x00020000	/* PLB4 to PLB3 bridge controller */
+#define IBM_CPM_PLB3x4		0x00010000	/* PLB3 to PLB4 bridge controller */
+#define IBM_CPM_PLB3		0x00008000	/* PLB3 bus arbiter */
+#define IBM_CPM_PPM		0x00002000	/* PLB Performance Monitor */
+#define IBM_CPM_UIC1		0x00001000	/* Universal Interrupt Controller */
+#define IBM_CPM_GPIO0		0x00000800	/* General Purpose IO (??) */
+#define IBM_CPM_GPT		0x00000400	/* General Purpose Timers  */
+#define IBM_CPM_UART0		0x00000200	/* serial port 0 */
+#define IBM_CPM_UART1		0x00000100	/* serial port 1 */
+#define IBM_CPM_UIC0		0x00000080	/* Universal Interrupt Controller */
+#define IBM_CPM_TMRCLK		0x00000040	/* CPU timers */
+#define IBM_CPM_EMAC0		0x00000020	/* ethernet port 0 */
+#define IBM_CPM_EMAC1		0x00000010	/* ethernet port 1 */
+#define IBM_CPM_UART2		0x00000008	/* serial port 2 */
+#define IBM_CPM_UART3		0x00000004	/* serial port 3 */
+#define IBM_CPM_USB2D		0x00000002	/* USB 2.0 Device */
+#define IBM_CPM_USB2H		0x00000001	/* USB 2.0 Host */
+
+#define DFLT_IBM4xx_PM		~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
+				| IBM_CPM_EBC | IBM_CPM_BGO | IBM_CPM_FPU \
+				| IBM_CPM_EBM | IBM_CPM_PLB4 | IBM_CPM_3x4 \
+				| IBM_CPM_PLB3 | IBM_CPM_PLB4x3 \
+				| IBM_CPM_EMAC0 | IBM_CPM_TMRCLK \
+				| IBM_CPM_DMA | IBM_CPM_PCI | IBM_CPM_EMAC1)
+
+
+#endif /* __PPC_PLATFORMS_IBM440EP_H */
+#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440sp.c b/arch/ppc/platforms/4xx/ibm440sp.c
index a203efb47ab..fa3e003a0db 100644
--- a/arch/ppc/platforms/4xx/ibm440sp.c
+++ b/arch/ppc/platforms/4xx/ibm440sp.c
@@ -36,8 +36,8 @@ static struct ocp_func_emac_data ibm440sp_emac0_def = {
 OCP_SYSFS_EMAC_DATA()
 
 static struct ocp_func_mal_data ibm440sp_mal0_def = {
-	.num_tx_chans   = 4,    	/* Number of TX channels */
-	.num_rx_chans   = 4,    	/* Number of RX channels */
+	.num_tx_chans   = 1,    	/* Number of TX channels */
+	.num_rx_chans   = 1,    	/* Number of RX channels */
 	.txeob_irq	= 38,		/* TX End Of Buffer IRQ  */
 	.rxeob_irq	= 39,		/* RX End Of Buffer IRQ  */
 	.txde_irq	= 34,		/* TX Descriptor Error IRQ */
diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
index 5f82a6bc704..8fc34a34476 100644
--- a/arch/ppc/platforms/4xx/ocotea.c
+++ b/arch/ppc/platforms/4xx/ocotea.c
@@ -48,6 +48,7 @@
 #include <asm/bootinfo.h>
 #include <asm/ppc4xx_pic.h>
 #include <asm/ppcboot.h>
+#include <asm/tlbflush.h>
 
 #include <syslib/gen550.h>
 #include <syslib/ibm440gx_common.h>
@@ -266,6 +267,9 @@ ocotea_early_serial_map(void)
 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 	/* Configure debug serial access */
 	gen550_init(0, &port);
+
+	/* Purge TLB entry added in head_44x.S for early serial access */
+	_tlbie(UART0_IO_BASE);
 #endif
 
 	port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
diff --git a/arch/ppc/platforms/4xx/ocotea.h b/arch/ppc/platforms/4xx/ocotea.h
index 202dc825119..33251153ac5 100644
--- a/arch/ppc/platforms/4xx/ocotea.h
+++ b/arch/ppc/platforms/4xx/ocotea.h
@@ -55,15 +55,24 @@
  */
 #define RS_TABLE_SIZE	2
 
-/* OpenBIOS defined UART mappings, used before early_serial_setup */
+#if defined(__BOOTER__)
+/* OpenBIOS defined UART mappings, used by bootloader shim */
 #define UART0_IO_BASE	0xE0000200
 #define UART1_IO_BASE	0xE0000300
+#else
+/* head_44x.S created UART mapping, used before early_serial_setup.
+ * We cannot use default OpenBIOS UART mappings because they
+ * don't work for configurations with more than 512M RAM.    --ebs
+ */
+#define UART0_IO_BASE	0xF0000200
+#define UART1_IO_BASE	0xF0000300
+#endif
 
 #define BASE_BAUD	11059200/16
 #define STD_UART_OP(num)					\
 	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
 		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: UART##num##_IO_BASE,		\
+		iomem_base: (void*)UART##num##_IO_BASE,		\
 		io_type: SERIAL_IO_MEM},
 
 #define SERIAL_PORT_DFNS	\
diff --git a/arch/ppc/platforms/85xx/mpc8560_ads.c b/arch/ppc/platforms/85xx/mpc8560_ads.c
index e18380258b6..f2748c88665 100644
--- a/arch/ppc/platforms/85xx/mpc8560_ads.c
+++ b/arch/ppc/platforms/85xx/mpc8560_ads.c
@@ -56,7 +56,6 @@
 #include <syslib/ppc85xx_common.h>
 #include <syslib/ppc85xx_setup.h>
 
-extern void cpm2_reset(void);
 
 /* ************************************************************************
  *
diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
index b52c4317fef..6267b294f70 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
+++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
@@ -49,7 +49,7 @@
 #include <asm/mpc85xx.h>
 #include <asm/irq.h>
 #include <asm/immap_85xx.h>
-#include <asm/immap_cpm2.h>
+#include <asm/cpm2.h>
 #include <asm/ppc_sys.h>
 #include <asm/kgdb.h>
 
diff --git a/arch/ppc/platforms/85xx/stx_gp3.c b/arch/ppc/platforms/85xx/stx_gp3.c
index bb41265cfc8..c99b365d611 100644
--- a/arch/ppc/platforms/85xx/stx_gp3.c
+++ b/arch/ppc/platforms/85xx/stx_gp3.c
@@ -52,14 +52,13 @@
 #include <asm/mpc85xx.h>
 #include <asm/irq.h>
 #include <asm/immap_85xx.h>
-#include <asm/immap_cpm2.h>
+#include <asm/cpm2.h>
 #include <asm/mpc85xx.h>
 #include <asm/ppc_sys.h>
 
 #include <syslib/cpm2_pic.h>
 #include <syslib/ppc85xx_common.h>
 
-extern void cpm2_reset(void);
 
 unsigned char __res[sizeof(bd_t)];
 
diff --git a/arch/ppc/platforms/pmac_setup.c b/arch/ppc/platforms/pmac_setup.c
index 4d324b630f4..b392b9a1598 100644
--- a/arch/ppc/platforms/pmac_setup.c
+++ b/arch/ppc/platforms/pmac_setup.c
@@ -113,7 +113,7 @@ extern int pmac_newworld;
 extern void zs_kgdb_hook(int tty_num);
 static void ohare_init(void);
 #ifdef CONFIG_BOOTX_TEXT
-void pmac_progress(char *s, unsigned short hex);
+static void pmac_progress(char *s, unsigned short hex);
 #endif
 
 sys_ctrler_t sys_ctrler = SYS_CTRLER_UNKNOWN;
@@ -123,7 +123,7 @@ extern struct smp_ops_t psurge_smp_ops;
 extern struct smp_ops_t core99_smp_ops;
 #endif /* CONFIG_SMP */
 
-int __pmac
+static int __pmac
 pmac_show_cpuinfo(struct seq_file *m)
 {
 	struct device_node *np;
@@ -227,7 +227,7 @@ pmac_show_cpuinfo(struct seq_file *m)
 	return 0;
 }
 
-int __openfirmware
+static int __openfirmware
 pmac_show_percpuinfo(struct seq_file *m, int i)
 {
 #ifdef CONFIG_CPU_FREQ_PMAC
@@ -415,7 +415,7 @@ find_ide_boot(void)
 }
 #endif /* CONFIG_BLK_DEV_IDE && CONFIG_BLK_DEV_IDE_PMAC */
 
-void __init
+static void __init
 find_boot_device(void)
 {
 #if defined(CONFIG_BLK_DEV_IDE) && defined(CONFIG_BLK_DEV_IDE_PMAC)
@@ -512,7 +512,7 @@ note_bootable_part(dev_t dev, int part, int goodness)
 	}
 }
 
-void __pmac
+static void __pmac
 pmac_restart(char *cmd)
 {
 #ifdef CONFIG_ADB_CUDA
@@ -537,7 +537,7 @@ pmac_restart(char *cmd)
 	}
 }
 
-void __pmac
+static void __pmac
 pmac_power_off(void)
 {
 #ifdef CONFIG_ADB_CUDA
@@ -562,7 +562,7 @@ pmac_power_off(void)
 	}
 }
 
-void __pmac
+static void __pmac
 pmac_halt(void)
 {
    pmac_power_off();
@@ -700,7 +700,7 @@ pmac_init(unsigned long r3, unsigned long r4, unsigned long r5,
 }
 
 #ifdef CONFIG_BOOTX_TEXT
-void __init
+static void __init
 pmac_progress(char *s, unsigned short hex)
 {
 	if (boot_text_mapped) {
diff --git a/arch/ppc/platforms/prpmc750.c b/arch/ppc/platforms/prpmc750.c
index c894e1ab593..24ae1caafc6 100644
--- a/arch/ppc/platforms/prpmc750.c
+++ b/arch/ppc/platforms/prpmc750.c
@@ -29,6 +29,7 @@
 #include <linux/ide.h>
 #include <linux/root_dev.h>
 #include <linux/slab.h>
+#include <linux/serial_reg.h>
 
 #include <asm/byteorder.h>
 #include <asm/system.h>
diff --git a/arch/ppc/platforms/sandpoint.c b/arch/ppc/platforms/sandpoint.c
index 8b149c2fc54..21e31346b12 100644
--- a/arch/ppc/platforms/sandpoint.c
+++ b/arch/ppc/platforms/sandpoint.c
@@ -311,19 +311,22 @@ sandpoint_setup_arch(void)
 	{
 		bd_t *bp = (bd_t *)__res;
 		struct plat_serial8250_port *pdata;
-		pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_DUART);
 
+		pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART0);
 		if (pdata)
 		{
 			pdata[0].uartclk = bp->bi_busfreq;
-			pdata[0].membase = ioremap(pdata[0].mapbase, 0x100);
+		}
 
-			/* this disables the 2nd serial port on the DUART
-			 * since the sandpoint does not have it connected */
-			pdata[1].uartclk = 0;
-			pdata[1].irq = 0;
-			pdata[1].mapbase = 0;
+#ifdef CONFIG_SANDPOINT_ENABLE_UART1
+		pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART1);
+		if (pdata)
+		{
+			pdata[0].uartclk = bp->bi_busfreq;
 		}
+#else
+		ppc_sys_device_remove(MPC10X_UART1);
+#endif
 	}
 
 	printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n");
diff --git a/arch/ppc/platforms/tqm8260_setup.c b/arch/ppc/platforms/tqm8260_setup.c
index a8880bfc034..3409139330b 100644
--- a/arch/ppc/platforms/tqm8260_setup.c
+++ b/arch/ppc/platforms/tqm8260_setup.c
@@ -16,8 +16,8 @@
 
 #include <linux/init.h>
 
-#include <asm/immap_cpm2.h>
 #include <asm/mpc8260.h>
+#include <asm/cpm2.h>
 #include <asm/machdep.h>
 
 static int
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
index dec5bf4f687..220a65ab0a5 100644
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_PPCBUG_NVRAM)	+= prep_nvram.o
 obj-$(CONFIG_PPC_OCP)		+= ocp.o
 obj-$(CONFIG_IBM_OCP)		+= ibm_ocp.o
 obj-$(CONFIG_44x)		+= ibm44x_common.o
+obj-$(CONFIG_440EP)		+= ibm440gx_common.o
 obj-$(CONFIG_440GP)		+= ibm440gp_common.o
 obj-$(CONFIG_440GX)		+= ibm440gx_common.o
 obj-$(CONFIG_440SP)		+= ibm440gx_common.o ibm440sp_common.o
@@ -44,6 +45,7 @@ obj-$(CONFIG_PPC_CHRP)		+= open_pic.o indirect_pci.o i8259.o
 obj-$(CONFIG_PPC_PREP)		+= open_pic.o indirect_pci.o i8259.o todc_time.o
 obj-$(CONFIG_ADIR)		+= i8259.o indirect_pci.o pci_auto.o \
 					todc_time.o
+obj-$(CONFIG_BAMBOO)		+= indirect_pci.o pci_auto.o todc_time.o
 obj-$(CONFIG_CPCI690)		+= todc_time.o pci_auto.o
 obj-$(CONFIG_EBONY)		+= indirect_pci.o pci_auto.o todc_time.o
 obj-$(CONFIG_EV64260)		+= todc_time.o pci_auto.o
diff --git a/arch/ppc/syslib/cpm2_common.c b/arch/ppc/syslib/cpm2_common.c
index 4c19a4ac716..cbac44b1620 100644
--- a/arch/ppc/syslib/cpm2_common.c
+++ b/arch/ppc/syslib/cpm2_common.c
@@ -27,7 +27,6 @@
 #include <asm/mpc8260.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
-#include <asm/immap_cpm2.h>
 #include <asm/cpm2.h>
 #include <asm/rheap.h>
 
diff --git a/arch/ppc/syslib/ibm440gx_common.c b/arch/ppc/syslib/ibm440gx_common.c
index 4ad85e0e023..d4776af6a3c 100644
--- a/arch/ppc/syslib/ibm440gx_common.c
+++ b/arch/ppc/syslib/ibm440gx_common.c
@@ -34,6 +34,10 @@ void __init ibm440gx_get_clocks(struct ibm44x_clocks* p, unsigned int sys_clk,
 	u32 plld  = CPR_READ(DCRN_CPR_PLLD);
 	u32 uart0 = SDR_READ(DCRN_SDR_UART0);
 	u32 uart1 = SDR_READ(DCRN_SDR_UART1);
+#ifdef CONFIG_440EP
+	u32 uart2 = SDR_READ(DCRN_SDR_UART2);
+	u32 uart3 = SDR_READ(DCRN_SDR_UART3);
+#endif
 
 	/* Dividers */
 	u32 fbdv   = __fix_zero((plld >> 24) & 0x1f, 32);
@@ -96,6 +100,17 @@ bypass:
 		p->uart1 = ser_clk;
 	else
 		p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256);
+#ifdef CONFIG_440EP
+	if (uart2 & 0x00800000)
+		p->uart2 = ser_clk;
+	else
+		p->uart2 = p->plb / __fix_zero(uart2 & 0xff, 256);
+
+	if (uart3 & 0x00800000)
+		p->uart3 = ser_clk;
+	else
+		p->uart3 = p->plb / __fix_zero(uart3 & 0xff, 256);
+#endif
 }
 
 /* Issue L2C diagnostic command */
diff --git a/arch/ppc/syslib/ibm44x_common.h b/arch/ppc/syslib/ibm44x_common.h
index b14eb603ce0..c16b6a5ac6a 100644
--- a/arch/ppc/syslib/ibm44x_common.h
+++ b/arch/ppc/syslib/ibm44x_common.h
@@ -29,6 +29,10 @@ struct ibm44x_clocks {
 	unsigned int ebc;	/* PerClk */
 	unsigned int uart0;
 	unsigned int uart1;
+#ifdef CONFIG_440EP
+	unsigned int uart2;
+	unsigned int uart3;
+#endif
 };
 
 /* common 44x platform init */
diff --git a/arch/ppc/syslib/m8260_setup.c b/arch/ppc/syslib/m8260_setup.c
index fda75d79050..8f80a42dfdb 100644
--- a/arch/ppc/syslib/m8260_setup.c
+++ b/arch/ppc/syslib/m8260_setup.c
@@ -24,7 +24,7 @@
 #include <asm/io.h>
 #include <asm/pgtable.h>
 #include <asm/mpc8260.h>
-#include <asm/immap_cpm2.h>
+#include <asm/cpm2.h>
 #include <asm/machdep.h>
 #include <asm/bootinfo.h>
 #include <asm/time.h>
@@ -33,7 +33,6 @@
 
 unsigned char __res[sizeof(bd_t)];
 
-extern void cpm2_reset(void);
 extern void pq2_find_bridges(void);
 extern void pq2pci_init_irq(void);
 extern void idma_pci9_init(void);
diff --git a/arch/ppc/syslib/m82xx_pci.c b/arch/ppc/syslib/m82xx_pci.c
index 5e7a7edcea7..9db58c587b4 100644
--- a/arch/ppc/syslib/m82xx_pci.c
+++ b/arch/ppc/syslib/m82xx_pci.c
@@ -238,9 +238,9 @@ pq2ads_setup_pci(struct pci_controller *hose)
 	 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
 	 * and local bus for PCI (SIUMCR [LBPC]).
 	 */
-	immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
-				~(SIUMCR_L2PC11 | SIUMCR_LBPC11 | SIUMCR_CS10PC11 | SIUMCR_APPC11) |
-				SIUMCR_BBD | SIUMCR_LBPC01 | SIUMCR_DPPC11 | SIUMCR_APPC10;
+	immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.siu_82xx.sc_siumcr &
+				~(SIUMCR_L2CPC11 | SIUMCR_LBPC11 | SIUMCR_CS10PC11 | SIUMCR_APPC11) |
+				SIUMCR_BBD | SIUMCR_LBPC01 | SIUMCR_DPPC11 | SIUMCR_APPC10);
 #endif
 	/* Enable PCI  */
 	immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
diff --git a/arch/ppc/syslib/m8xx_setup.c b/arch/ppc/syslib/m8xx_setup.c
index c1db2ab1d15..55a381af4e3 100644
--- a/arch/ppc/syslib/m8xx_setup.c
+++ b/arch/ppc/syslib/m8xx_setup.c
@@ -57,7 +57,7 @@ unsigned char __res[sizeof(bd_t)];
 extern void m8xx_ide_init(void);
 
 extern unsigned long find_available_memory(void);
-extern void m8xx_cpm_reset(uint cpm_page);
+extern void m8xx_cpm_reset();
 extern void m8xx_wdt_handler_install(bd_t *bp);
 extern void rpxfb_alloc_pages(void);
 extern void cpm_interrupt_init(void);
@@ -70,13 +70,9 @@ board_init(void)
 void __init
 m8xx_setup_arch(void)
 {
-	int	cpm_page;
-
-	cpm_page = (int) alloc_bootmem_pages(PAGE_SIZE);
-
 	/* Reset the Communication Processor Module.
 	*/
-	m8xx_cpm_reset(cpm_page);
+	m8xx_cpm_reset();
 
 #ifdef CONFIG_FB_RPX
 	rpxfb_alloc_pages();
diff --git a/arch/ppc/syslib/mpc10x_common.c b/arch/ppc/syslib/mpc10x_common.c
index 8fc5f415452..87065e2e4c5 100644
--- a/arch/ppc/syslib/mpc10x_common.c
+++ b/arch/ppc/syslib/mpc10x_common.c
@@ -45,24 +45,29 @@
 #define MPC10X_DMA0_IRQ (EPIC_IRQ_BASE + 1 + NUM_8259_INTERRUPTS)
 #define MPC10X_DMA1_IRQ (EPIC_IRQ_BASE + 2 + NUM_8259_INTERRUPTS)
 #define MPC10X_UART0_IRQ (EPIC_IRQ_BASE + 4 + NUM_8259_INTERRUPTS)
+#define MPC10X_UART1_IRQ (EPIC_IRQ_BASE + 5 + NUM_8259_INTERRUPTS)
 #else
 #define MPC10X_I2C_IRQ -1
 #define MPC10X_DMA0_IRQ -1
 #define MPC10X_DMA1_IRQ -1
 #define MPC10X_UART0_IRQ -1
+#define MPC10X_UART1_IRQ -1
 #endif
 
 static struct fsl_i2c_platform_data mpc10x_i2c_pdata = {
 	.device_flags		= 0,
 };
 
-static struct plat_serial8250_port serial_platform_data[] = {
+static struct plat_serial8250_port serial_plat_uart0[] = {
 	[0] = {
 		.mapbase	= 0x4500,
 		.iotype		= UPIO_MEM,
 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 	},
-	[1] = {
+	{ },
+};
+static struct plat_serial8250_port serial_plat_uart1[] = {
+	[0] = {
 		.mapbase	= 0x4600,
 		.iotype		= UPIO_MEM,
 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
@@ -133,11 +138,17 @@ struct platform_device ppc_sys_platform_devices[] = {
 			},
 		},
 	},
-	[MPC10X_DUART] = {
+	[MPC10X_UART0] = {
 		.name = "serial8250",
 		.id	= 0,
-		.dev.platform_data = serial_platform_data,
+		.dev.platform_data = serial_plat_uart0,
 	},
+	[MPC10X_UART1] = {
+		.name = "serial8250",
+		.id	= 1,
+		.dev.platform_data = serial_plat_uart1,
+	},
+
 };
 
 /* We use the PCI ID to match on */
@@ -147,10 +158,10 @@ struct ppc_sys_spec ppc_sys_specs[] = {
 		.ppc_sys_name 	= "8245",
 		.mask		= 0xFFFFFFFF,
 		.value		= MPC10X_BRIDGE_8245,
-		.num_devices	= 4,
+		.num_devices	= 5,
 		.device_list	= (enum ppc_sys_devices[])
 		{
-			MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, MPC10X_DUART,
+			MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, MPC10X_UART0, MPC10X_UART1,
 		},
 	},
 	{
@@ -180,6 +191,25 @@ struct ppc_sys_spec ppc_sys_specs[] = {
 	},
 };
 
+/*
+ * mach_mpc10x_fixup: This function enables DUART mode if it detects
+ * if it detects two UARTS in the platform device entries.
+ */
+static int __init mach_mpc10x_fixup(struct platform_device *pdev)
+{
+	if (strncmp (pdev->name, "serial8250", 10) == 0 && pdev->id == 1)
+		writeb(readb(serial_plat_uart1[0].membase + 0x11) | 0x1,
+				serial_plat_uart1[0].membase + 0x11);
+	return 0;
+}
+
+static int __init mach_mpc10x_init(void)
+{
+	ppc_sys_device_fixup = mach_mpc10x_fixup;
+	return 0;
+}
+postcore_initcall(mach_mpc10x_init);
+
 /* Set resources to match bridge memory map */
 void __init
 mpc10x_bridge_set_resources(int map, struct pci_controller *hose)
@@ -219,6 +249,7 @@ mpc10x_bridge_set_resources(int map, struct pci_controller *hose)
 				ppc_md.progress("mpc10x:exit1", 0x100);
 	}
 }
+
 /*
  * Do some initialization and put the EUMB registers at the specified address
  * (also map the EPIC registers into virtual space--OpenPIC_Addr will be set).
@@ -411,11 +442,13 @@ mpc10x_bridge_init(struct pci_controller *hose,
 	ppc_sys_platform_devices[MPC10X_DMA1].resource[1].start = MPC10X_DMA1_IRQ;
 	ppc_sys_platform_devices[MPC10X_DMA1].resource[1].end = MPC10X_DMA1_IRQ;
 
-	serial_platform_data[0].mapbase += phys_eumb_base;
-	serial_platform_data[0].irq = MPC10X_UART0_IRQ;
+	serial_plat_uart0[0].mapbase += phys_eumb_base;
+	serial_plat_uart0[0].irq = MPC10X_UART0_IRQ;
+	serial_plat_uart0[0].membase = ioremap(serial_plat_uart0[0].mapbase, 0x100);
 
-	serial_platform_data[1].mapbase += phys_eumb_base;
-	serial_platform_data[1].irq = MPC10X_UART0_IRQ + 1;
+	serial_plat_uart1[0].mapbase += phys_eumb_base;
+	serial_plat_uart1[0].irq = MPC10X_UART1_IRQ;
+	serial_plat_uart1[0].membase = ioremap(serial_plat_uart1[0].mapbase, 0x100);
 
 	/*
 	 * 8240 erratum 26, 8241/8245 erratum 29, 107 erratum 23: speculative
diff --git a/arch/ppc/syslib/mpc83xx_devices.c b/arch/ppc/syslib/mpc83xx_devices.c
index 75c8e9834ae..5aaf0e58e1f 100644
--- a/arch/ppc/syslib/mpc83xx_devices.c
+++ b/arch/ppc/syslib/mpc83xx_devices.c
@@ -191,8 +191,8 @@ struct platform_device ppc_sys_platform_devices[] = {
 		.num_resources	 = 2,
 		.resource = (struct resource[]) {
 			{
-				.start	= 0x22000,
-				.end	= 0x22fff,
+				.start	= 0x23000,
+				.end	= 0x23fff,
 				.flags	= IORESOURCE_MEM,
 			},
 			{
@@ -208,8 +208,8 @@ struct platform_device ppc_sys_platform_devices[] = {
 		.num_resources	 = 2,
 		.resource = (struct resource[]) {
 			{
-				.start	= 0x23000,
-				.end	= 0x23fff,
+				.start	= 0x22000,
+				.end	= 0x22fff,
 				.flags	= IORESOURCE_MEM,
 			},
 			{
diff --git a/arch/ppc/syslib/ppc85xx_setup.c b/arch/ppc/syslib/ppc85xx_setup.c
index ca95d79a704..b7242f1bd93 100644
--- a/arch/ppc/syslib/ppc85xx_setup.c
+++ b/arch/ppc/syslib/ppc85xx_setup.c
@@ -233,14 +233,14 @@ mpc85xx_setup_pci2(struct pci_controller *hose)
 	pci->powbar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
 	/* Enable, Mem R/W */
 	pci->powar1 = 0x80044000 |
-	   (__ilog2(MPC85XX_PCI1_UPPER_MEM - MPC85XX_PCI1_LOWER_MEM + 1) - 1);
+	   (__ilog2(MPC85XX_PCI2_UPPER_MEM - MPC85XX_PCI2_LOWER_MEM + 1) - 1);
 
 	/* Setup outboud IO windows @ MPC85XX_PCI2_IO_BASE */
 	pci->potar2 = 0x00000000;
 	pci->potear2 = 0x00000000;
 	pci->powbar2 = (MPC85XX_PCI2_IO_BASE >> 12) & 0x000fffff;
 	/* Enable, IO R/W */
-	pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI1_IO_SIZE) - 1);
+	pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI2_IO_SIZE) - 1);
 
 	/* Setup 2G inbound Memory Window @ 0 */
 	pci->pitar1 = 0x00000000;
diff --git a/arch/ppc64/Kconfig b/arch/ppc64/Kconfig
index fdd8afba715..2ce87836c67 100644
--- a/arch/ppc64/Kconfig
+++ b/arch/ppc64/Kconfig
@@ -288,6 +288,7 @@ config SCHED_SMT
 	  overhead in some places. If unsure say N here.
 
 source "kernel/Kconfig.preempt"
+source kernel/Kconfig.hz
 
 config EEH
 	bool "PCI Extended Error Handling (EEH)" if EMBEDDED
diff --git a/arch/ppc64/boot/zlib.c b/arch/ppc64/boot/zlib.c
index 9d5e4e9832d..78837e884b8 100644
--- a/arch/ppc64/boot/zlib.c
+++ b/arch/ppc64/boot/zlib.c
@@ -1307,7 +1307,7 @@ local int huft_build(
   {
     *t = (inflate_huft *)Z_NULL;
     *m = 0;
-    return Z_OK;
+    return Z_DATA_ERROR;
   }
 
 
@@ -1351,6 +1351,7 @@ local int huft_build(
     if ((j = *p++) != 0)
       v[x[j]++] = i;
   } while (++i < n);
+  n = x[g];			/* set n to length of v */
 
 
   /* Generate the Huffman codes and for each, make the table entries */
diff --git a/arch/ppc64/configs/bpa_defconfig b/arch/ppc64/configs/bpa_defconfig
new file mode 100644
index 00000000000..46c5da41c3a
--- /dev/null
+++ b/arch/ppc64/configs/bpa_defconfig
@@ -0,0 +1,987 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.13-rc6
+# Mon Aug  8 14:12:19 2005
+#
+CONFIG_64BIT=y
+CONFIG_MMU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_HAVE_DEC_LOCK=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_COMPAT=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_FORCE_MAX_ZONEORDER=13
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_HOTPLUG=y
+CONFIG_KOBJECT_UEVENT=y
+# CONFIG_IKCONFIG is not set
+# CONFIG_CPUSETS is not set
+# CONFIG_EMBEDDED is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_SYSVIPC_COMPAT=y
+
+#
+# Platform support
+#
+# CONFIG_PPC_ISERIES is not set
+CONFIG_PPC_MULTIPLATFORM=y
+# CONFIG_PPC_PSERIES is not set
+CONFIG_PPC_BPA=y
+# CONFIG_PPC_PMAC is not set
+# CONFIG_PPC_MAPLE is not set
+CONFIG_PPC=y
+CONFIG_PPC64=y
+CONFIG_PPC_OF=y
+CONFIG_BPA_IIC=y
+CONFIG_ALTIVEC=y
+CONFIG_KEXEC=y
+# CONFIG_U3_DART is not set
+# CONFIG_BOOTX_TEXT is not set
+# CONFIG_POWER4_ONLY is not set
+# CONFIG_IOMMU_VMERGE is not set
+CONFIG_SMP=y
+CONFIG_NR_CPUS=4
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_NUMA is not set
+CONFIG_SCHED_SMT=y
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_PREEMPT_BKL=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_PPC_RTAS=y
+CONFIG_RTAS_PROC=y
+CONFIG_RTAS_FLASH=y
+CONFIG_SECCOMP=y
+CONFIG_ISA_DMA_API=y
+
+#
+# General setup
+#
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_PCI_LEGACY_PROC=y
+CONFIG_PCI_NAMES=y
+# CONFIG_PCI_DEBUG is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PCI Hotplug Support
+#
+# CONFIG_HOTPLUG_PCI is not set
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=y
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+CONFIG_INET_TUNNEL=y
+CONFIG_IP_TCPDIAG=y
+CONFIG_IP_TCPDIAG_IPV6=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+
+#
+# IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_PRIVACY is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_IPV6_TUNNEL=m
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_IP_NF_CONNTRACK=y
+# CONFIG_IP_NF_CT_ACCT is not set
+# CONFIG_IP_NF_CONNTRACK_MARK is not set
+CONFIG_IP_NF_CT_PROTO_SCTP=y
+CONFIG_IP_NF_FTP=m
+CONFIG_IP_NF_IRC=m
+CONFIG_IP_NF_TFTP=m
+CONFIG_IP_NF_AMANDA=m
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_LIMIT=m
+CONFIG_IP_NF_MATCH_IPRANGE=m
+CONFIG_IP_NF_MATCH_MAC=m
+CONFIG_IP_NF_MATCH_PKTTYPE=m
+CONFIG_IP_NF_MATCH_MARK=m
+CONFIG_IP_NF_MATCH_MULTIPORT=m
+CONFIG_IP_NF_MATCH_TOS=m
+CONFIG_IP_NF_MATCH_RECENT=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_DSCP=m
+CONFIG_IP_NF_MATCH_AH_ESP=m
+CONFIG_IP_NF_MATCH_LENGTH=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_MATCH_TCPMSS=m
+CONFIG_IP_NF_MATCH_HELPER=m
+CONFIG_IP_NF_MATCH_STATE=m
+CONFIG_IP_NF_MATCH_CONNTRACK=m
+CONFIG_IP_NF_MATCH_OWNER=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_REALM=m
+CONFIG_IP_NF_MATCH_SCTP=m
+CONFIG_IP_NF_MATCH_COMMENT=m
+CONFIG_IP_NF_MATCH_HASHLIMIT=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_TARGET_TCPMSS=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_SAME=m
+CONFIG_IP_NF_NAT_SNMP_BASIC=m
+CONFIG_IP_NF_NAT_IRC=m
+CONFIG_IP_NF_NAT_FTP=m
+CONFIG_IP_NF_NAT_TFTP=m
+CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_TOS=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_DSCP=m
+CONFIG_IP_NF_TARGET_MARK=m
+CONFIG_IP_NF_TARGET_CLASSIFY=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_TARGET_NOTRACK=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IP6_NF_IPTABLES is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_CLS_ROUTE=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=y
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=131072
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CDROM_PKTCDVD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=y
+CONFIG_IDEDISK_MULTI_MODE=y
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=y
+CONFIG_BLK_DEV_IDEPCI=y
+CONFIG_IDEPCI_SHARE_IRQ=y
+# CONFIG_BLK_DEV_OFFBOARD is not set
+CONFIG_BLK_DEV_GENERIC=y
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_SL82C105 is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
+CONFIG_IDEDMA_PCI_AUTO=y
+# CONFIG_IDEDMA_ONLYDISK is not set
+CONFIG_BLK_DEV_AEC62XX=y
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+CONFIG_BLK_DEV_SIIMAGE=y
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_IDE_ARM is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_IVB is not set
+CONFIG_IDEDMA_AUTO=y
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Macintosh device drivers
+#
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_PCI is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+CONFIG_E1000=m
+# CONFIG_E1000_NAPI is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+CONFIG_SKGE=m
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_MV643XX_ETH is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_PCIPS2 is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_ROCKETPORT is not set
+# CONFIG_CYCLADES is not set
+# CONFIG_MOXA_SMARTIO is not set
+# CONFIG_ISI is not set
+# CONFIG_SYNCLINK is not set
+# CONFIG_SYNCLINKMP is not set
+# CONFIG_N_HDLC is not set
+# CONFIG_SPECIALIX is not set
+# CONFIG_SX is not set
+# CONFIG_STALDRV is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_WATCHDOG_RTAS=y
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+# CONFIG_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_HANGCHECK_TIMER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+# CONFIG_I2C_CHARDEV is not set
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_ISA is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_SENSOR is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Hardware Monitoring support
+#
+# CONFIG_HWMON is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB is not set
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# SN Devices
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+
+#
+# XFS support
+#
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+# CONFIG_DEVPTS_FS_XATTR is not set
+CONFIG_TMPFS=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_TMPFS_SECURITY is not set
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+CONFIG_NFSD=m
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+# CONFIG_NFSD_V4 is not set
+CONFIG_NFSD_TCP=y
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_ACL_SUPPORT=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=m
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_LOG_BUF_SHIFT=15
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_INFO is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_KPROBES is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUGGER=y
+# CONFIG_XMON is not set
+# CONFIG_PPCDBG is not set
+CONFIG_IRQSTACKS=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=m
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Hardware crypto devices
+#
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
diff --git a/arch/ppc64/configs/g5_defconfig b/arch/ppc64/configs/g5_defconfig
index 1eb33398648..ab567741e80 100644
--- a/arch/ppc64/configs/g5_defconfig
+++ b/arch/ppc64/configs/g5_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc6
-# Tue Jun 14 16:59:20 2005
+# Linux kernel version: 2.6.13-rc6
+# Mon Aug  8 14:16:59 2005
 #
 CONFIG_64BIT=y
 CONFIG_MMU=y
@@ -73,12 +73,15 @@ CONFIG_SYSVIPC_COMPAT=y
 # CONFIG_PPC_ISERIES is not set
 CONFIG_PPC_MULTIPLATFORM=y
 # CONFIG_PPC_PSERIES is not set
+# CONFIG_PPC_BPA is not set
 CONFIG_PPC_PMAC=y
 # CONFIG_PPC_MAPLE is not set
 CONFIG_PPC=y
 CONFIG_PPC64=y
 CONFIG_PPC_OF=y
+CONFIG_MPIC=y
 CONFIG_ALTIVEC=y
+CONFIG_KEXEC=y
 CONFIG_U3_DART=y
 CONFIG_PPC_PMAC64=y
 CONFIG_BOOTX_TEXT=y
@@ -86,8 +89,24 @@ CONFIG_POWER4_ONLY=y
 CONFIG_IOMMU_VMERGE=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_NUMA is not set
 # CONFIG_SCHED_SMT is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
+# CONFIG_PREEMPT_BKL is not set
+CONFIG_HZ_100=y
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=100
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_SECCOMP=y
 CONFIG_ISA_DMA_API=y
@@ -117,6 +136,142 @@ CONFIG_PROC_DEVICETREE=y
 # CONFIG_CMDLINE_BOOL is not set
 
 #
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+CONFIG_NET_KEY=m
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=y
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_TUNNEL=y
+CONFIG_IP_TCPDIAG=m
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+
+#
+# IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_IP_NF_CONNTRACK=m
+CONFIG_IP_NF_CT_ACCT=y
+CONFIG_IP_NF_CONNTRACK_MARK=y
+CONFIG_IP_NF_CT_PROTO_SCTP=m
+CONFIG_IP_NF_FTP=m
+CONFIG_IP_NF_IRC=m
+CONFIG_IP_NF_TFTP=m
+CONFIG_IP_NF_AMANDA=m
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_LIMIT=m
+CONFIG_IP_NF_MATCH_IPRANGE=m
+CONFIG_IP_NF_MATCH_MAC=m
+CONFIG_IP_NF_MATCH_PKTTYPE=m
+CONFIG_IP_NF_MATCH_MARK=m
+CONFIG_IP_NF_MATCH_MULTIPORT=m
+CONFIG_IP_NF_MATCH_TOS=m
+CONFIG_IP_NF_MATCH_RECENT=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_DSCP=m
+CONFIG_IP_NF_MATCH_AH_ESP=m
+CONFIG_IP_NF_MATCH_LENGTH=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_MATCH_TCPMSS=m
+CONFIG_IP_NF_MATCH_HELPER=m
+CONFIG_IP_NF_MATCH_STATE=m
+CONFIG_IP_NF_MATCH_CONNTRACK=m
+CONFIG_IP_NF_MATCH_OWNER=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_REALM=m
+CONFIG_IP_NF_MATCH_SCTP=m
+CONFIG_IP_NF_MATCH_COMMENT=m
+CONFIG_IP_NF_MATCH_CONNMARK=m
+CONFIG_IP_NF_MATCH_HASHLIMIT=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_TARGET_TCPMSS=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_SAME=m
+CONFIG_IP_NF_NAT_SNMP_BASIC=m
+CONFIG_IP_NF_NAT_IRC=m
+CONFIG_IP_NF_NAT_FTP=m
+CONFIG_IP_NF_NAT_TFTP=m
+CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_TOS=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_DSCP=m
+CONFIG_IP_NF_TARGET_MARK=m
+CONFIG_IP_NF_TARGET_CLASSIFY=m
+CONFIG_IP_NF_TARGET_CONNMARK=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_TARGET_NOTRACK=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_CLS_ROUTE=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+
+#
 # Device Drivers
 #
 
@@ -218,6 +373,7 @@ CONFIG_IDEDMA_PCI_AUTO=y
 # CONFIG_BLK_DEV_HPT366 is not set
 # CONFIG_BLK_DEV_SC1200 is not set
 # CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT821X is not set
 # CONFIG_BLK_DEV_NS87415 is not set
 # CONFIG_BLK_DEV_PDC202XX_OLD is not set
 # CONFIG_BLK_DEV_PDC202XX_NEW is not set
@@ -251,6 +407,7 @@ CONFIG_CHR_DEV_ST=y
 CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
 
 #
 # Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -309,6 +466,7 @@ CONFIG_SCSI_QLA2XXX=y
 # CONFIG_SCSI_QLA2300 is not set
 # CONFIG_SCSI_QLA2322 is not set
 # CONFIG_SCSI_QLA6312 is not set
+# CONFIG_SCSI_QLA24XX is not set
 # CONFIG_SCSI_LPFC is not set
 # CONFIG_SCSI_DC395x is not set
 # CONFIG_SCSI_DC390T is not set
@@ -338,6 +496,8 @@ CONFIG_DM_ZERO=m
 # Fusion MPT device support
 #
 # CONFIG_FUSION is not set
+# CONFIG_FUSION_SPI is not set
+# CONFIG_FUSION_FC is not set
 
 #
 # IEEE 1394 (FireWire) support
@@ -351,6 +511,7 @@ CONFIG_IEEE1394=y
 CONFIG_IEEE1394_OUI_DB=y
 CONFIG_IEEE1394_EXTRA_CONFIG_ROMS=y
 CONFIG_IEEE1394_CONFIG_ROM_IP1394=y
+# CONFIG_IEEE1394_EXPORT_FULL_API is not set
 
 #
 # Device Drivers
@@ -377,152 +538,14 @@ CONFIG_IEEE1394_RAWIO=y
 #
 # Macintosh device drivers
 #
-CONFIG_ADB=y
 CONFIG_ADB_PMU=y
 CONFIG_PMAC_SMU=y
-# CONFIG_PMAC_PBOOK is not set
 # CONFIG_PMAC_BACKLIGHT is not set
-# CONFIG_INPUT_ADBHID is not set
 CONFIG_THERM_PM72=y
 
 #
-# Networking support
-#
-CONFIG_NET=y
-
-#
-# Networking options
+# Network device support
 #
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_NET_KEY=m
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_PNP is not set
-CONFIG_NET_IPIP=y
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-CONFIG_SYN_COOKIES=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_TUNNEL=y
-CONFIG_IP_TCPDIAG=m
-# CONFIG_IP_TCPDIAG_IPV6 is not set
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_IP_NF_CONNTRACK=m
-CONFIG_IP_NF_CT_ACCT=y
-CONFIG_IP_NF_CONNTRACK_MARK=y
-CONFIG_IP_NF_CT_PROTO_SCTP=m
-CONFIG_IP_NF_FTP=m
-CONFIG_IP_NF_IRC=m
-CONFIG_IP_NF_TFTP=m
-CONFIG_IP_NF_AMANDA=m
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_LIMIT=m
-CONFIG_IP_NF_MATCH_IPRANGE=m
-CONFIG_IP_NF_MATCH_MAC=m
-CONFIG_IP_NF_MATCH_PKTTYPE=m
-CONFIG_IP_NF_MATCH_MARK=m
-CONFIG_IP_NF_MATCH_MULTIPORT=m
-CONFIG_IP_NF_MATCH_TOS=m
-CONFIG_IP_NF_MATCH_RECENT=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_DSCP=m
-CONFIG_IP_NF_MATCH_AH_ESP=m
-CONFIG_IP_NF_MATCH_LENGTH=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_MATCH_TCPMSS=m
-CONFIG_IP_NF_MATCH_HELPER=m
-CONFIG_IP_NF_MATCH_STATE=m
-CONFIG_IP_NF_MATCH_CONNTRACK=m
-CONFIG_IP_NF_MATCH_OWNER=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_REALM=m
-CONFIG_IP_NF_MATCH_SCTP=m
-CONFIG_IP_NF_MATCH_COMMENT=m
-CONFIG_IP_NF_MATCH_CONNMARK=m
-CONFIG_IP_NF_MATCH_HASHLIMIT=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_TARGET_TCPMSS=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_NAT_NEEDED=y
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_SAME=m
-CONFIG_IP_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_NAT_IRC=m
-CONFIG_IP_NF_NAT_FTP=m
-CONFIG_IP_NF_NAT_TFTP=m
-CONFIG_IP_NF_NAT_AMANDA=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_TOS=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_DSCP=m
-CONFIG_IP_NF_TARGET_MARK=m
-CONFIG_IP_NF_TARGET_CLASSIFY=m
-CONFIG_IP_NF_TARGET_CONNMARK=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_TARGET_NOTRACK=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-CONFIG_LLC=y
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-CONFIG_NET_CLS_ROUTE=y
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
 CONFIG_BONDING=m
@@ -562,6 +585,7 @@ CONFIG_E1000=y
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 # CONFIG_R8169 is not set
+# CONFIG_SKGE is not set
 # CONFIG_SK98LIN is not set
 CONFIG_TIGON3=m
 # CONFIG_BNX2 is not set
@@ -604,6 +628,8 @@ CONFIG_PPPOE=m
 # CONFIG_NET_FC is not set
 # CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
 
 #
 # ISDN subsystem
@@ -691,7 +717,6 @@ CONFIG_LEGACY_PTY_COUNT=256
 #
 # CONFIG_WATCHDOG is not set
 # CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
@@ -750,50 +775,19 @@ CONFIG_I2C_KEYWEST=y
 # CONFIG_I2C_VIAPRO is not set
 # CONFIG_I2C_VOODOO3 is not set
 # CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_SENSOR is not set
 
 #
-# Hardware Sensors Chip support
-#
-# CONFIG_I2C_SENSOR is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ASB100 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_FSCHER is not set
-# CONFIG_SENSORS_FSCPOS is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_SIS5595 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_VIA686A is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83627HF is not set
-
-#
-# Other I2C Chip support
+# Miscellaneous I2C Chip support
 #
 # CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
@@ -805,6 +799,11 @@ CONFIG_I2C_KEYWEST=y
 # CONFIG_W1 is not set
 
 #
+# Hardware Monitoring support
+#
+# CONFIG_HWMON is not set
+
+#
 # Misc devices
 #
 
@@ -911,6 +910,7 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_EHCI_HCD=y
 # CONFIG_USB_EHCI_SPLIT_ISO is not set
 # CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+# CONFIG_USB_ISP116X_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
@@ -950,12 +950,15 @@ CONFIG_THRUSTMASTER_FF=y
 CONFIG_USB_HIDDEV=y
 # CONFIG_USB_AIPTEK is not set
 # CONFIG_USB_WACOM is not set
+# CONFIG_USB_ACECAD is not set
 # CONFIG_USB_KBTAB is not set
 # CONFIG_USB_POWERMATE is not set
 # CONFIG_USB_MTOUCH is not set
+# CONFIG_USB_ITMTOUCH is not set
 # CONFIG_USB_EGALAX is not set
 # CONFIG_USB_XPAD is not set
 # CONFIG_USB_ATI_REMOTE is not set
+# CONFIG_USB_KEYSPAN_REMOTE is not set
 
 #
 # USB Imaging devices
@@ -1071,10 +1074,11 @@ CONFIG_USB_EZUSB=y
 # CONFIG_USB_PHIDGETSERVO is not set
 # CONFIG_USB_IDMOUSE is not set
 # CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
 # CONFIG_USB_TEST is not set
 
 #
-# USB ATM/DSL drivers
+# USB DSL modem support
 #
 
 #
@@ -1093,12 +1097,18 @@ CONFIG_USB_EZUSB=y
 # CONFIG_INFINIBAND is not set
 
 #
+# SN Devices
+#
+
+#
 # File systems
 #
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
 CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
 CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_XATTR=y
 CONFIG_EXT3_FS_POSIX_ACL=y
@@ -1126,6 +1136,7 @@ CONFIG_XFS_SECURITY=y
 CONFIG_XFS_POSIX_ACL=y
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
 # CONFIG_QUOTA is not set
 CONFIG_DNOTIFY=y
 CONFIG_AUTOFS_FS=m
@@ -1157,7 +1168,6 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
 CONFIG_DEVPTS_FS_XATTR=y
 # CONFIG_DEVPTS_FS_SECURITY is not set
 CONFIG_TMPFS=y
@@ -1189,15 +1199,20 @@ CONFIG_CRAMFS=y
 #
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 # CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=y
+CONFIG_NFSD_V2_ACL=y
 CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
 CONFIG_NFSD_V4=y
 CONFIG_NFSD_TCP=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
 CONFIG_RPCSEC_GSS_KRB5=y
diff --git a/arch/ppc64/configs/iSeries_defconfig b/arch/ppc64/configs/iSeries_defconfig
index f6a2b99afd6..394ba18b58c 100644
--- a/arch/ppc64/configs/iSeries_defconfig
+++ b/arch/ppc64/configs/iSeries_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc6
-# Tue Jun 14 17:01:28 2005
+# Linux kernel version: 2.6.13-rc6
+# Mon Aug  8 14:17:02 2005
 #
 CONFIG_64BIT=y
 CONFIG_MMU=y
@@ -80,8 +80,24 @@ CONFIG_IBMVIO=y
 CONFIG_IOMMU_VMERGE=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=32
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_NUMA is not set
 # CONFIG_SCHED_SMT is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
+# CONFIG_PREEMPT_BKL is not set
+CONFIG_HZ_100=y
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=100
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_MSCHUNKS=y
 CONFIG_LPARCFG=y
@@ -110,6 +126,142 @@ CONFIG_PCI_NAMES=y
 # CONFIG_HOTPLUG_PCI is not set
 
 #
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+CONFIG_NET_KEY=m
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=y
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_TUNNEL=y
+CONFIG_IP_TCPDIAG=m
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+
+#
+# IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_IP_NF_CONNTRACK=m
+CONFIG_IP_NF_CT_ACCT=y
+CONFIG_IP_NF_CONNTRACK_MARK=y
+CONFIG_IP_NF_CT_PROTO_SCTP=m
+CONFIG_IP_NF_FTP=m
+CONFIG_IP_NF_IRC=m
+CONFIG_IP_NF_TFTP=m
+CONFIG_IP_NF_AMANDA=m
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_LIMIT=m
+CONFIG_IP_NF_MATCH_IPRANGE=m
+CONFIG_IP_NF_MATCH_MAC=m
+CONFIG_IP_NF_MATCH_PKTTYPE=m
+CONFIG_IP_NF_MATCH_MARK=m
+CONFIG_IP_NF_MATCH_MULTIPORT=m
+CONFIG_IP_NF_MATCH_TOS=m
+CONFIG_IP_NF_MATCH_RECENT=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_DSCP=m
+CONFIG_IP_NF_MATCH_AH_ESP=m
+CONFIG_IP_NF_MATCH_LENGTH=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_MATCH_TCPMSS=m
+CONFIG_IP_NF_MATCH_HELPER=m
+CONFIG_IP_NF_MATCH_STATE=m
+CONFIG_IP_NF_MATCH_CONNTRACK=m
+CONFIG_IP_NF_MATCH_OWNER=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_REALM=m
+CONFIG_IP_NF_MATCH_SCTP=m
+CONFIG_IP_NF_MATCH_COMMENT=m
+CONFIG_IP_NF_MATCH_CONNMARK=m
+CONFIG_IP_NF_MATCH_HASHLIMIT=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_TARGET_TCPMSS=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_SAME=m
+CONFIG_IP_NF_NAT_SNMP_BASIC=m
+CONFIG_IP_NF_NAT_IRC=m
+CONFIG_IP_NF_NAT_FTP=m
+CONFIG_IP_NF_NAT_TFTP=m
+CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_TOS=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_DSCP=m
+CONFIG_IP_NF_TARGET_MARK=m
+CONFIG_IP_NF_TARGET_CLASSIFY=m
+CONFIG_IP_NF_TARGET_CONNMARK=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_TARGET_NOTRACK=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_CLS_ROUTE=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+
+#
 # Device Drivers
 #
 
@@ -184,6 +336,7 @@ CONFIG_CHR_DEV_ST=y
 CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
 
 #
 # Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -231,6 +384,7 @@ CONFIG_SCSI_QLA2XXX=y
 # CONFIG_SCSI_QLA2300 is not set
 # CONFIG_SCSI_QLA2322 is not set
 # CONFIG_SCSI_QLA6312 is not set
+# CONFIG_SCSI_QLA24XX is not set
 # CONFIG_SCSI_LPFC is not set
 # CONFIG_SCSI_DC395x is not set
 # CONFIG_SCSI_DC390T is not set
@@ -260,6 +414,8 @@ CONFIG_DM_ZERO=m
 # Fusion MPT device support
 #
 # CONFIG_FUSION is not set
+# CONFIG_FUSION_SPI is not set
+# CONFIG_FUSION_FC is not set
 
 #
 # IEEE 1394 (FireWire) support
@@ -276,145 +432,8 @@ CONFIG_DM_ZERO=m
 #
 
 #
-# Networking support
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_NET_KEY=m
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_PNP is not set
-CONFIG_NET_IPIP=y
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-CONFIG_SYN_COOKIES=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_TUNNEL=y
-CONFIG_IP_TCPDIAG=m
-# CONFIG_IP_TCPDIAG_IPV6 is not set
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
+# Network device support
 #
-# IP: Netfilter Configuration
-#
-CONFIG_IP_NF_CONNTRACK=m
-CONFIG_IP_NF_CT_ACCT=y
-CONFIG_IP_NF_CONNTRACK_MARK=y
-CONFIG_IP_NF_CT_PROTO_SCTP=m
-CONFIG_IP_NF_FTP=m
-CONFIG_IP_NF_IRC=m
-CONFIG_IP_NF_TFTP=m
-CONFIG_IP_NF_AMANDA=m
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_LIMIT=m
-CONFIG_IP_NF_MATCH_IPRANGE=m
-CONFIG_IP_NF_MATCH_MAC=m
-CONFIG_IP_NF_MATCH_PKTTYPE=m
-CONFIG_IP_NF_MATCH_MARK=m
-CONFIG_IP_NF_MATCH_MULTIPORT=m
-CONFIG_IP_NF_MATCH_TOS=m
-CONFIG_IP_NF_MATCH_RECENT=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_DSCP=m
-CONFIG_IP_NF_MATCH_AH_ESP=m
-CONFIG_IP_NF_MATCH_LENGTH=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_MATCH_TCPMSS=m
-CONFIG_IP_NF_MATCH_HELPER=m
-CONFIG_IP_NF_MATCH_STATE=m
-CONFIG_IP_NF_MATCH_CONNTRACK=m
-CONFIG_IP_NF_MATCH_OWNER=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_REALM=m
-CONFIG_IP_NF_MATCH_SCTP=m
-CONFIG_IP_NF_MATCH_COMMENT=m
-CONFIG_IP_NF_MATCH_CONNMARK=m
-CONFIG_IP_NF_MATCH_HASHLIMIT=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_TARGET_TCPMSS=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_NAT_NEEDED=y
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_SAME=m
-CONFIG_IP_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_NAT_IRC=m
-CONFIG_IP_NF_NAT_FTP=m
-CONFIG_IP_NF_NAT_TFTP=m
-CONFIG_IP_NF_NAT_AMANDA=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_TOS=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_DSCP=m
-CONFIG_IP_NF_TARGET_MARK=m
-CONFIG_IP_NF_TARGET_CLASSIFY=m
-CONFIG_IP_NF_TARGET_CONNMARK=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_TARGET_NOTRACK=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-CONFIG_LLC=y
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-CONFIG_NET_CLS_ROUTE=y
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-CONFIG_NETPOLL=y
-CONFIG_NETPOLL_RX=y
-CONFIG_NETPOLL_TRAP=y
-CONFIG_NET_POLL_CONTROLLER=y
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
 CONFIG_BONDING=m
@@ -471,6 +490,7 @@ CONFIG_E1000=m
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 # CONFIG_R8169 is not set
+# CONFIG_SKGE is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
@@ -514,6 +534,10 @@ CONFIG_PPPOE=m
 # CONFIG_NET_FC is not set
 # CONFIG_SHAPER is not set
 CONFIG_NETCONSOLE=y
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_RX=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
 
 #
 # ISDN subsystem
@@ -587,7 +611,6 @@ CONFIG_LEGACY_PTY_COUNT=256
 #
 # CONFIG_WATCHDOG is not set
 # CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
@@ -610,6 +633,7 @@ CONFIG_MAX_RAW_DEVS=256
 # I2C support
 #
 # CONFIG_I2C is not set
+# CONFIG_I2C_SENSOR is not set
 
 #
 # Dallas's 1-wire bus
@@ -617,6 +641,11 @@ CONFIG_MAX_RAW_DEVS=256
 # CONFIG_W1 is not set
 
 #
+# Hardware Monitoring support
+#
+# CONFIG_HWMON is not set
+
+#
 # Misc devices
 #
 
@@ -663,12 +692,18 @@ CONFIG_USB_ARCH_HAS_OHCI=y
 # CONFIG_INFINIBAND is not set
 
 #
+# SN Devices
+#
+
+#
 # File systems
 #
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
 CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
 CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_XATTR=y
 CONFIG_EXT3_FS_POSIX_ACL=y
@@ -700,6 +735,7 @@ CONFIG_XFS_SECURITY=y
 CONFIG_XFS_POSIX_ACL=y
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
 # CONFIG_QUOTA is not set
 CONFIG_DNOTIFY=y
 CONFIG_AUTOFS_FS=m
@@ -731,7 +767,6 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
 CONFIG_DEVPTS_FS_XATTR=y
 CONFIG_DEVPTS_FS_SECURITY=y
 CONFIG_TMPFS=y
@@ -763,15 +798,20 @@ CONFIG_CRAMFS=y
 #
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 # CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=m
+CONFIG_NFSD_V2_ACL=y
 CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
 CONFIG_NFSD_V4=y
 CONFIG_NFSD_TCP=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
 CONFIG_RPCSEC_GSS_KRB5=y
diff --git a/arch/ppc64/configs/maple_defconfig b/arch/ppc64/configs/maple_defconfig
index 8051b0f47b6..2033fe663db 100644
--- a/arch/ppc64/configs/maple_defconfig
+++ b/arch/ppc64/configs/maple_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc6
-# Tue Jun 14 17:12:48 2005
+# Linux kernel version: 2.6.13-rc6
+# Mon Aug  8 14:17:04 2005
 #
 CONFIG_64BIT=y
 CONFIG_MMU=y
@@ -73,12 +73,15 @@ CONFIG_SYSVIPC_COMPAT=y
 # CONFIG_PPC_ISERIES is not set
 CONFIG_PPC_MULTIPLATFORM=y
 # CONFIG_PPC_PSERIES is not set
+# CONFIG_PPC_BPA is not set
 # CONFIG_PPC_PMAC is not set
 CONFIG_PPC_MAPLE=y
 CONFIG_PPC=y
 CONFIG_PPC64=y
 CONFIG_PPC_OF=y
+CONFIG_MPIC=y
 # CONFIG_ALTIVEC is not set
+CONFIG_KEXEC=y
 CONFIG_U3_DART=y
 CONFIG_MPIC_BROKEN_U3=y
 CONFIG_BOOTX_TEXT=y
@@ -86,8 +89,24 @@ CONFIG_POWER4_ONLY=y
 CONFIG_IOMMU_VMERGE=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_NUMA is not set
 # CONFIG_SCHED_SMT is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
+# CONFIG_PREEMPT_BKL is not set
+CONFIG_HZ_100=y
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=100
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_SECCOMP=y
 CONFIG_ISA_DMA_API=y
@@ -116,6 +135,69 @@ CONFIG_PROC_DEVICETREE=y
 # CONFIG_CMDLINE_BOOL is not set
 
 #
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_IP_TCPDIAG=y
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+
+#
 # Device Drivers
 #
 
@@ -213,6 +295,7 @@ CONFIG_BLK_DEV_AMD74XX=y
 # CONFIG_BLK_DEV_HPT366 is not set
 # CONFIG_BLK_DEV_SC1200 is not set
 # CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT821X is not set
 # CONFIG_BLK_DEV_NS87415 is not set
 # CONFIG_BLK_DEV_PDC202XX_OLD is not set
 # CONFIG_BLK_DEV_PDC202XX_NEW is not set
@@ -240,6 +323,7 @@ CONFIG_IDEDMA_AUTO=y
 #
 # Fusion MPT device support
 #
+# CONFIG_FUSION is not set
 
 #
 # IEEE 1394 (FireWire) support
@@ -256,70 +340,8 @@ CONFIG_IDEDMA_AUTO=y
 #
 
 #
-# Networking support
-#
-CONFIG_NET=y
-
-#
-# Networking options
+# Network device support
 #
-CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IP_PNP_BOOTP is not set
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_IP_TCPDIAG=y
-# CONFIG_IP_TCPDIAG_IPV6 is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETFILTER is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-# CONFIG_NET_CLS_ROUTE is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
@@ -376,6 +398,7 @@ CONFIG_E1000=y
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 # CONFIG_R8169 is not set
+# CONFIG_SKGE is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
@@ -408,6 +431,8 @@ CONFIG_E1000=y
 # CONFIG_SLIP is not set
 # CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
 
 #
 # ISDN subsystem
@@ -487,7 +512,6 @@ CONFIG_LEGACY_PTY_COUNT=256
 #
 # CONFIG_WATCHDOG is not set
 # CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
@@ -543,50 +567,19 @@ CONFIG_I2C_AMD8111=y
 # CONFIG_I2C_VIAPRO is not set
 # CONFIG_I2C_VOODOO3 is not set
 # CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_SENSOR is not set
 
 #
-# Hardware Sensors Chip support
-#
-# CONFIG_I2C_SENSOR is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ASB100 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_FSCHER is not set
-# CONFIG_SENSORS_FSCPOS is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_SIS5595 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_VIA686A is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83627HF is not set
-
-#
-# Other I2C Chip support
+# Miscellaneous I2C Chip support
 #
 # CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
@@ -598,6 +591,11 @@ CONFIG_I2C_AMD8111=y
 # CONFIG_W1 is not set
 
 #
+# Hardware Monitoring support
+#
+# CONFIG_HWMON is not set
+
+#
 # Misc devices
 #
 
@@ -649,6 +647,7 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_SPLIT_ISO=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_ISP116X_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
@@ -676,12 +675,15 @@ CONFIG_USB_HIDINPUT=y
 # CONFIG_USB_HIDDEV is not set
 # CONFIG_USB_AIPTEK is not set
 # CONFIG_USB_WACOM is not set
+# CONFIG_USB_ACECAD is not set
 # CONFIG_USB_KBTAB is not set
 # CONFIG_USB_POWERMATE is not set
 # CONFIG_USB_MTOUCH is not set
+# CONFIG_USB_ITMTOUCH is not set
 # CONFIG_USB_EGALAX is not set
 # CONFIG_USB_XPAD is not set
 # CONFIG_USB_ATI_REMOTE is not set
+# CONFIG_USB_KEYSPAN_REMOTE is not set
 
 #
 # USB Imaging devices
@@ -772,10 +774,11 @@ CONFIG_USB_EZUSB=y
 # CONFIG_USB_PHIDGETSERVO is not set
 # CONFIG_USB_IDMOUSE is not set
 # CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
 # CONFIG_USB_TEST is not set
 
 #
-# USB ATM/DSL drivers
+# USB DSL modem support
 #
 
 #
@@ -794,16 +797,23 @@ CONFIG_USB_EZUSB=y
 # CONFIG_INFINIBAND is not set
 
 #
+# SN Devices
+#
+
+#
 # File systems
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
 CONFIG_JBD=y
 # CONFIG_JBD_DEBUG is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
 
 #
 # XFS support
@@ -811,6 +821,7 @@ CONFIG_JBD=y
 # CONFIG_XFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
 # CONFIG_QUOTA is not set
 CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
@@ -838,7 +849,6 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
 CONFIG_DEVPTS_FS_XATTR=y
 # CONFIG_DEVPTS_FS_SECURITY is not set
 CONFIG_TMPFS=y
@@ -870,12 +880,15 @@ CONFIG_CRAMFS=y
 #
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 # CONFIG_NFS_DIRECTIO is not set
 # CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
 CONFIG_RPCSEC_GSS_KRB5=y
diff --git a/arch/ppc64/configs/pSeries_defconfig b/arch/ppc64/configs/pSeries_defconfig
index d0db8b5966c..297fd522948 100644
--- a/arch/ppc64/configs/pSeries_defconfig
+++ b/arch/ppc64/configs/pSeries_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc6
-# Tue Jun 14 17:13:47 2005
+# Linux kernel version: 2.6.13-rc6
+# Mon Aug  8 14:17:07 2005
 #
 CONFIG_64BIT=y
 CONFIG_MMU=y
@@ -74,13 +74,17 @@ CONFIG_SYSVIPC_COMPAT=y
 # CONFIG_PPC_ISERIES is not set
 CONFIG_PPC_MULTIPLATFORM=y
 CONFIG_PPC_PSERIES=y
+# CONFIG_PPC_BPA is not set
 # CONFIG_PPC_PMAC is not set
 # CONFIG_PPC_MAPLE is not set
 CONFIG_PPC=y
 CONFIG_PPC64=y
 CONFIG_PPC_OF=y
+CONFIG_XICS=y
+CONFIG_MPIC=y
 CONFIG_ALTIVEC=y
 CONFIG_PPC_SPLPAR=y
+CONFIG_KEXEC=y
 CONFIG_IBMVIO=y
 # CONFIG_U3_DART is not set
 # CONFIG_BOOTX_TEXT is not set
@@ -88,10 +92,30 @@ CONFIG_IBMVIO=y
 CONFIG_IOMMU_VMERGE=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=128
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
 CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
+CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM_MANUAL=y
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_NEED_MULTIPLE_NODES=y
+CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y
+CONFIG_NODES_SPAN_OTHER_NODES=y
 CONFIG_NUMA=y
 CONFIG_SCHED_SMT=y
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
+# CONFIG_PREEMPT_BKL is not set
+CONFIG_HZ_100=y
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=100
 CONFIG_EEH=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_PPC_RTAS=y
@@ -132,6 +156,142 @@ CONFIG_PROC_DEVICETREE=y
 # CONFIG_CMDLINE_BOOL is not set
 
 #
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+CONFIG_NET_KEY=m
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=y
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_TUNNEL=y
+CONFIG_IP_TCPDIAG=m
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+
+#
+# IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_IP_NF_CONNTRACK=m
+CONFIG_IP_NF_CT_ACCT=y
+CONFIG_IP_NF_CONNTRACK_MARK=y
+CONFIG_IP_NF_CT_PROTO_SCTP=m
+CONFIG_IP_NF_FTP=m
+CONFIG_IP_NF_IRC=m
+CONFIG_IP_NF_TFTP=m
+CONFIG_IP_NF_AMANDA=m
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_LIMIT=m
+CONFIG_IP_NF_MATCH_IPRANGE=m
+CONFIG_IP_NF_MATCH_MAC=m
+CONFIG_IP_NF_MATCH_PKTTYPE=m
+CONFIG_IP_NF_MATCH_MARK=m
+CONFIG_IP_NF_MATCH_MULTIPORT=m
+CONFIG_IP_NF_MATCH_TOS=m
+CONFIG_IP_NF_MATCH_RECENT=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_DSCP=m
+CONFIG_IP_NF_MATCH_AH_ESP=m
+CONFIG_IP_NF_MATCH_LENGTH=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_MATCH_TCPMSS=m
+CONFIG_IP_NF_MATCH_HELPER=m
+CONFIG_IP_NF_MATCH_STATE=m
+CONFIG_IP_NF_MATCH_CONNTRACK=m
+CONFIG_IP_NF_MATCH_OWNER=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_REALM=m
+CONFIG_IP_NF_MATCH_SCTP=m
+CONFIG_IP_NF_MATCH_COMMENT=m
+CONFIG_IP_NF_MATCH_CONNMARK=m
+CONFIG_IP_NF_MATCH_HASHLIMIT=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_TARGET_TCPMSS=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_SAME=m
+CONFIG_IP_NF_NAT_SNMP_BASIC=m
+CONFIG_IP_NF_NAT_IRC=m
+CONFIG_IP_NF_NAT_FTP=m
+CONFIG_IP_NF_NAT_TFTP=m
+CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_TOS=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_DSCP=m
+CONFIG_IP_NF_TARGET_MARK=m
+CONFIG_IP_NF_TARGET_CLASSIFY=m
+CONFIG_IP_NF_TARGET_CONNMARK=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_TARGET_NOTRACK=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_CLS_ROUTE=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+
+#
 # Device Drivers
 #
 
@@ -238,6 +398,7 @@ CONFIG_BLK_DEV_AMD74XX=y
 # CONFIG_BLK_DEV_HPT366 is not set
 # CONFIG_BLK_DEV_SC1200 is not set
 # CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT821X is not set
 # CONFIG_BLK_DEV_NS87415 is not set
 # CONFIG_BLK_DEV_PDC202XX_OLD is not set
 # CONFIG_BLK_DEV_PDC202XX_NEW is not set
@@ -267,6 +428,7 @@ CONFIG_CHR_DEV_ST=y
 CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
 
 #
 # Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -322,6 +484,7 @@ CONFIG_SCSI_QLA22XX=m
 CONFIG_SCSI_QLA2300=m
 CONFIG_SCSI_QLA2322=m
 CONFIG_SCSI_QLA6312=m
+CONFIG_SCSI_QLA24XX=m
 CONFIG_SCSI_LPFC=m
 # CONFIG_SCSI_DC395x is not set
 # CONFIG_SCSI_DC390T is not set
@@ -352,6 +515,8 @@ CONFIG_DM_MULTIPATH_EMC=m
 # Fusion MPT device support
 #
 # CONFIG_FUSION is not set
+# CONFIG_FUSION_SPI is not set
+# CONFIG_FUSION_FC is not set
 
 #
 # IEEE 1394 (FireWire) support
@@ -368,145 +533,8 @@ CONFIG_DM_MULTIPATH_EMC=m
 #
 
 #
-# Networking support
+# Network device support
 #
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_NET_KEY=m
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_PNP is not set
-CONFIG_NET_IPIP=y
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-CONFIG_SYN_COOKIES=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_TUNNEL=y
-CONFIG_IP_TCPDIAG=m
-# CONFIG_IP_TCPDIAG_IPV6 is not set
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_IP_NF_CONNTRACK=m
-CONFIG_IP_NF_CT_ACCT=y
-CONFIG_IP_NF_CONNTRACK_MARK=y
-CONFIG_IP_NF_CT_PROTO_SCTP=m
-CONFIG_IP_NF_FTP=m
-CONFIG_IP_NF_IRC=m
-CONFIG_IP_NF_TFTP=m
-CONFIG_IP_NF_AMANDA=m
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_LIMIT=m
-CONFIG_IP_NF_MATCH_IPRANGE=m
-CONFIG_IP_NF_MATCH_MAC=m
-CONFIG_IP_NF_MATCH_PKTTYPE=m
-CONFIG_IP_NF_MATCH_MARK=m
-CONFIG_IP_NF_MATCH_MULTIPORT=m
-CONFIG_IP_NF_MATCH_TOS=m
-CONFIG_IP_NF_MATCH_RECENT=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_DSCP=m
-CONFIG_IP_NF_MATCH_AH_ESP=m
-CONFIG_IP_NF_MATCH_LENGTH=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_MATCH_TCPMSS=m
-CONFIG_IP_NF_MATCH_HELPER=m
-CONFIG_IP_NF_MATCH_STATE=m
-CONFIG_IP_NF_MATCH_CONNTRACK=m
-CONFIG_IP_NF_MATCH_OWNER=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_REALM=m
-CONFIG_IP_NF_MATCH_SCTP=m
-CONFIG_IP_NF_MATCH_COMMENT=m
-CONFIG_IP_NF_MATCH_CONNMARK=m
-CONFIG_IP_NF_MATCH_HASHLIMIT=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_TARGET_TCPMSS=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_NAT_NEEDED=y
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_SAME=m
-CONFIG_IP_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_NAT_IRC=m
-CONFIG_IP_NF_NAT_FTP=m
-CONFIG_IP_NF_NAT_TFTP=m
-CONFIG_IP_NF_NAT_AMANDA=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_TOS=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_DSCP=m
-CONFIG_IP_NF_TARGET_MARK=m
-CONFIG_IP_NF_TARGET_CLASSIFY=m
-CONFIG_IP_NF_TARGET_CONNMARK=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_TARGET_NOTRACK=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-CONFIG_LLC=y
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-CONFIG_NET_CLS_ROUTE=y
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-CONFIG_NETPOLL=y
-CONFIG_NETPOLL_RX=y
-CONFIG_NETPOLL_TRAP=y
-CONFIG_NET_POLL_CONTROLLER=y
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
 CONFIG_BONDING=m
@@ -566,6 +594,7 @@ CONFIG_E1000=y
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 # CONFIG_R8169 is not set
+# CONFIG_SKGE is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 CONFIG_TIGON3=y
@@ -613,6 +642,10 @@ CONFIG_PPPOE=m
 # CONFIG_NET_FC is not set
 # CONFIG_SHAPER is not set
 CONFIG_NETCONSOLE=y
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_RX=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
 
 #
 # ISDN subsystem
@@ -714,7 +747,6 @@ CONFIG_HVCS=m
 #
 # CONFIG_WATCHDOG is not set
 # CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
@@ -772,50 +804,19 @@ CONFIG_I2C_ALGOBIT=y
 # CONFIG_I2C_VIAPRO is not set
 # CONFIG_I2C_VOODOO3 is not set
 # CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_SENSOR is not set
 
 #
-# Hardware Sensors Chip support
-#
-# CONFIG_I2C_SENSOR is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ASB100 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_FSCHER is not set
-# CONFIG_SENSORS_FSCPOS is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_SIS5595 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_VIA686A is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83627HF is not set
-
-#
-# Other I2C Chip support
+# Miscellaneous I2C Chip support
 #
 # CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
@@ -827,6 +828,11 @@ CONFIG_I2C_ALGOBIT=y
 # CONFIG_W1 is not set
 
 #
+# Hardware Monitoring support
+#
+# CONFIG_HWMON is not set
+
+#
 # Misc devices
 #
 
@@ -933,6 +939,7 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_EHCI_HCD=y
 # CONFIG_USB_EHCI_SPLIT_ISO is not set
 # CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+# CONFIG_USB_ISP116X_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
@@ -969,12 +976,15 @@ CONFIG_USB_HIDINPUT=y
 CONFIG_USB_HIDDEV=y
 # CONFIG_USB_AIPTEK is not set
 # CONFIG_USB_WACOM is not set
+# CONFIG_USB_ACECAD is not set
 # CONFIG_USB_KBTAB is not set
 # CONFIG_USB_POWERMATE is not set
 # CONFIG_USB_MTOUCH is not set
+# CONFIG_USB_ITMTOUCH is not set
 # CONFIG_USB_EGALAX is not set
 # CONFIG_USB_XPAD is not set
 # CONFIG_USB_ATI_REMOTE is not set
+# CONFIG_USB_KEYSPAN_REMOTE is not set
 
 #
 # USB Imaging devices
@@ -1026,10 +1036,11 @@ CONFIG_USB_MON=y
 # CONFIG_USB_PHIDGETSERVO is not set
 # CONFIG_USB_IDMOUSE is not set
 # CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
 # CONFIG_USB_TEST is not set
 
 #
-# USB ATM/DSL drivers
+# USB DSL modem support
 #
 
 #
@@ -1046,18 +1057,25 @@ CONFIG_USB_MON=y
 # InfiniBand support
 #
 CONFIG_INFINIBAND=m
+CONFIG_INFINIBAND_USER_VERBS=m
 CONFIG_INFINIBAND_MTHCA=m
 # CONFIG_INFINIBAND_MTHCA_DEBUG is not set
 CONFIG_INFINIBAND_IPOIB=m
 # CONFIG_INFINIBAND_IPOIB_DEBUG is not set
 
 #
+# SN Devices
+#
+
+#
 # File systems
 #
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
 CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
 CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_XATTR=y
 CONFIG_EXT3_FS_POSIX_ACL=y
@@ -1089,6 +1107,7 @@ CONFIG_XFS_SECURITY=y
 CONFIG_XFS_POSIX_ACL=y
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
 # CONFIG_QUOTA is not set
 CONFIG_DNOTIFY=y
 CONFIG_AUTOFS_FS=m
@@ -1120,7 +1139,6 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
 CONFIG_DEVPTS_FS_XATTR=y
 CONFIG_DEVPTS_FS_SECURITY=y
 CONFIG_TMPFS=y
@@ -1152,15 +1170,20 @@ CONFIG_CRAMFS=y
 #
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 # CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=y
+CONFIG_NFSD_V2_ACL=y
 CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
 CONFIG_NFSD_V4=y
 CONFIG_NFSD_TCP=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
 CONFIG_RPCSEC_GSS_KRB5=y
diff --git a/arch/ppc64/defconfig b/arch/ppc64/defconfig
index b8e2066dde7..c361e7727b7 100644
--- a/arch/ppc64/defconfig
+++ b/arch/ppc64/defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc5-git9
-# Sun Jun  5 09:26:47 2005
+# Linux kernel version: 2.6.13-rc6
+# Mon Aug  8 14:16:54 2005
 #
 CONFIG_64BIT=y
 CONFIG_MMU=y
@@ -73,13 +73,18 @@ CONFIG_SYSVIPC_COMPAT=y
 # CONFIG_PPC_ISERIES is not set
 CONFIG_PPC_MULTIPLATFORM=y
 CONFIG_PPC_PSERIES=y
+CONFIG_PPC_BPA=y
 CONFIG_PPC_PMAC=y
 CONFIG_PPC_MAPLE=y
 CONFIG_PPC=y
 CONFIG_PPC64=y
 CONFIG_PPC_OF=y
+CONFIG_XICS=y
+CONFIG_MPIC=y
+CONFIG_BPA_IIC=y
 CONFIG_ALTIVEC=y
 CONFIG_PPC_SPLPAR=y
+CONFIG_KEXEC=y
 CONFIG_IBMVIO=y
 CONFIG_U3_DART=y
 CONFIG_MPIC_BROKEN_U3=y
@@ -89,10 +94,30 @@ CONFIG_BOOTX_TEXT=y
 CONFIG_IOMMU_VMERGE=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=32
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
 CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
+CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM_MANUAL=y
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_NEED_MULTIPLE_NODES=y
+CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y
+CONFIG_NODES_SPAN_OTHER_NODES=y
 # CONFIG_NUMA is not set
 # CONFIG_SCHED_SMT is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
+# CONFIG_PREEMPT_BKL is not set
+CONFIG_HZ_100=y
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=100
 CONFIG_EEH=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_PPC_RTAS=y
@@ -133,6 +158,142 @@ CONFIG_PROC_DEVICETREE=y
 # CONFIG_CMDLINE_BOOL is not set
 
 #
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+CONFIG_NET_KEY=m
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=y
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_TUNNEL=y
+# CONFIG_IP_TCPDIAG is not set
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+
+#
+# IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_IP_NF_CONNTRACK=m
+CONFIG_IP_NF_CT_ACCT=y
+CONFIG_IP_NF_CONNTRACK_MARK=y
+CONFIG_IP_NF_CT_PROTO_SCTP=m
+CONFIG_IP_NF_FTP=m
+CONFIG_IP_NF_IRC=m
+CONFIG_IP_NF_TFTP=m
+CONFIG_IP_NF_AMANDA=m
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_LIMIT=m
+CONFIG_IP_NF_MATCH_IPRANGE=m
+CONFIG_IP_NF_MATCH_MAC=m
+CONFIG_IP_NF_MATCH_PKTTYPE=m
+CONFIG_IP_NF_MATCH_MARK=m
+CONFIG_IP_NF_MATCH_MULTIPORT=m
+CONFIG_IP_NF_MATCH_TOS=m
+CONFIG_IP_NF_MATCH_RECENT=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_DSCP=m
+CONFIG_IP_NF_MATCH_AH_ESP=m
+CONFIG_IP_NF_MATCH_LENGTH=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_MATCH_TCPMSS=m
+CONFIG_IP_NF_MATCH_HELPER=m
+CONFIG_IP_NF_MATCH_STATE=m
+CONFIG_IP_NF_MATCH_CONNTRACK=m
+CONFIG_IP_NF_MATCH_OWNER=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_REALM=m
+CONFIG_IP_NF_MATCH_SCTP=m
+CONFIG_IP_NF_MATCH_COMMENT=m
+CONFIG_IP_NF_MATCH_CONNMARK=m
+CONFIG_IP_NF_MATCH_HASHLIMIT=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_TARGET_TCPMSS=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_SAME=m
+CONFIG_IP_NF_NAT_SNMP_BASIC=m
+CONFIG_IP_NF_NAT_IRC=m
+CONFIG_IP_NF_NAT_FTP=m
+CONFIG_IP_NF_NAT_TFTP=m
+CONFIG_IP_NF_NAT_AMANDA=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_TOS=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_DSCP=m
+CONFIG_IP_NF_TARGET_MARK=m
+CONFIG_IP_NF_TARGET_CLASSIFY=m
+CONFIG_IP_NF_TARGET_CONNMARK=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_TARGET_NOTRACK=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_CLS_ROUTE=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+
+#
 # Device Drivers
 #
 
@@ -239,6 +400,7 @@ CONFIG_BLK_DEV_AMD74XX=y
 # CONFIG_BLK_DEV_HPT366 is not set
 # CONFIG_BLK_DEV_SC1200 is not set
 # CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT821X is not set
 # CONFIG_BLK_DEV_NS87415 is not set
 # CONFIG_BLK_DEV_PDC202XX_OLD is not set
 # CONFIG_BLK_DEV_PDC202XX_NEW is not set
@@ -272,6 +434,7 @@ CONFIG_CHR_DEV_ST=y
 CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
 
 #
 # Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -339,6 +502,7 @@ CONFIG_SCSI_QLA22XX=m
 CONFIG_SCSI_QLA2300=m
 CONFIG_SCSI_QLA2322=m
 CONFIG_SCSI_QLA6312=m
+CONFIG_SCSI_QLA24XX=m
 CONFIG_SCSI_LPFC=m
 # CONFIG_SCSI_DC395x is not set
 # CONFIG_SCSI_DC390T is not set
@@ -369,6 +533,8 @@ CONFIG_DM_MULTIPATH_EMC=m
 # Fusion MPT device support
 #
 # CONFIG_FUSION is not set
+# CONFIG_FUSION_SPI is not set
+# CONFIG_FUSION_FC is not set
 
 #
 # IEEE 1394 (FireWire) support
@@ -382,6 +548,7 @@ CONFIG_IEEE1394=y
 # CONFIG_IEEE1394_OUI_DB is not set
 CONFIG_IEEE1394_EXTRA_CONFIG_ROMS=y
 CONFIG_IEEE1394_CONFIG_ROM_IP1394=y
+# CONFIG_IEEE1394_EXPORT_FULL_API is not set
 
 #
 # Device Drivers
@@ -409,154 +576,14 @@ CONFIG_IEEE1394_AMDTP=m
 #
 # Macintosh device drivers
 #
-CONFIG_ADB=y
 CONFIG_ADB_PMU=y
 CONFIG_PMAC_SMU=y
-# CONFIG_PMAC_PBOOK is not set
 # CONFIG_PMAC_BACKLIGHT is not set
-# CONFIG_INPUT_ADBHID is not set
 CONFIG_THERM_PM72=y
 
 #
-# Networking support
+# Network device support
 #
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_NET_KEY=m
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_PNP is not set
-CONFIG_NET_IPIP=y
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-CONFIG_SYN_COOKIES=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_TUNNEL=y
-# CONFIG_IP_TCPDIAG is not set
-# CONFIG_IP_TCPDIAG_IPV6 is not set
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_IP_NF_CONNTRACK=m
-CONFIG_IP_NF_CT_ACCT=y
-CONFIG_IP_NF_CONNTRACK_MARK=y
-CONFIG_IP_NF_CT_PROTO_SCTP=m
-CONFIG_IP_NF_FTP=m
-CONFIG_IP_NF_IRC=m
-CONFIG_IP_NF_TFTP=m
-CONFIG_IP_NF_AMANDA=m
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_LIMIT=m
-CONFIG_IP_NF_MATCH_IPRANGE=m
-CONFIG_IP_NF_MATCH_MAC=m
-CONFIG_IP_NF_MATCH_PKTTYPE=m
-CONFIG_IP_NF_MATCH_MARK=m
-CONFIG_IP_NF_MATCH_MULTIPORT=m
-CONFIG_IP_NF_MATCH_TOS=m
-CONFIG_IP_NF_MATCH_RECENT=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_DSCP=m
-CONFIG_IP_NF_MATCH_AH_ESP=m
-CONFIG_IP_NF_MATCH_LENGTH=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_MATCH_TCPMSS=m
-CONFIG_IP_NF_MATCH_HELPER=m
-CONFIG_IP_NF_MATCH_STATE=m
-CONFIG_IP_NF_MATCH_CONNTRACK=m
-CONFIG_IP_NF_MATCH_OWNER=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_REALM=m
-CONFIG_IP_NF_MATCH_SCTP=m
-CONFIG_IP_NF_MATCH_COMMENT=m
-CONFIG_IP_NF_MATCH_CONNMARK=m
-CONFIG_IP_NF_MATCH_HASHLIMIT=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_TARGET_TCPMSS=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_NAT_NEEDED=y
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_SAME=m
-CONFIG_IP_NF_NAT_SNMP_BASIC=m
-CONFIG_IP_NF_NAT_IRC=m
-CONFIG_IP_NF_NAT_FTP=m
-CONFIG_IP_NF_NAT_TFTP=m
-CONFIG_IP_NF_NAT_AMANDA=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_TOS=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_DSCP=m
-CONFIG_IP_NF_TARGET_MARK=m
-CONFIG_IP_NF_TARGET_CLASSIFY=m
-CONFIG_IP_NF_TARGET_CONNMARK=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_TARGET_NOTRACK=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-CONFIG_LLC=y
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-CONFIG_NET_CLS_ROUTE=y
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-CONFIG_NETPOLL=y
-CONFIG_NETPOLL_RX=y
-CONFIG_NETPOLL_TRAP=y
-CONFIG_NET_POLL_CONTROLLER=y
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
 CONFIG_BONDING=m
@@ -616,6 +643,7 @@ CONFIG_E1000=y
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 # CONFIG_R8169 is not set
+# CONFIG_SKGE is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 CONFIG_TIGON3=y
@@ -661,6 +689,10 @@ CONFIG_PPPOE=m
 # CONFIG_NET_FC is not set
 # CONFIG_SHAPER is not set
 CONFIG_NETCONSOLE=y
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_RX=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
 
 #
 # ISDN subsystem
@@ -764,7 +796,6 @@ CONFIG_HVCS=m
 #
 # CONFIG_WATCHDOG is not set
 # CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
@@ -823,50 +854,19 @@ CONFIG_I2C_KEYWEST=y
 # CONFIG_I2C_VIAPRO is not set
 # CONFIG_I2C_VOODOO3 is not set
 # CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_SENSOR is not set
 
 #
-# Hardware Sensors Chip support
-#
-# CONFIG_I2C_SENSOR is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ASB100 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_FSCHER is not set
-# CONFIG_SENSORS_FSCPOS is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_SIS5595 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_VIA686A is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83627HF is not set
-
-#
-# Other I2C Chip support
+# Miscellaneous I2C Chip support
 #
 # CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
@@ -878,6 +878,11 @@ CONFIG_I2C_KEYWEST=y
 # CONFIG_W1 is not set
 
 #
+# Hardware Monitoring support
+#
+# CONFIG_HWMON is not set
+
+#
 # Misc devices
 #
 
@@ -988,6 +993,7 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_EHCI_HCD=y
 # CONFIG_USB_EHCI_SPLIT_ISO is not set
 # CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+# CONFIG_USB_ISP116X_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
@@ -1024,12 +1030,15 @@ CONFIG_USB_HIDINPUT=y
 CONFIG_USB_HIDDEV=y
 # CONFIG_USB_AIPTEK is not set
 # CONFIG_USB_WACOM is not set
+# CONFIG_USB_ACECAD is not set
 # CONFIG_USB_KBTAB is not set
 # CONFIG_USB_POWERMATE is not set
 # CONFIG_USB_MTOUCH is not set
+# CONFIG_USB_ITMTOUCH is not set
 # CONFIG_USB_EGALAX is not set
 # CONFIG_USB_XPAD is not set
 # CONFIG_USB_ATI_REMOTE is not set
+# CONFIG_USB_KEYSPAN_REMOTE is not set
 
 #
 # USB Imaging devices
@@ -1081,10 +1090,11 @@ CONFIG_USB_PEGASUS=y
 # CONFIG_USB_PHIDGETSERVO is not set
 # CONFIG_USB_IDMOUSE is not set
 # CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
 # CONFIG_USB_TEST is not set
 
 #
-# USB ATM/DSL drivers
+# USB DSL modem support
 #
 
 #
@@ -1101,18 +1111,25 @@ CONFIG_USB_PEGASUS=y
 # InfiniBand support
 #
 CONFIG_INFINIBAND=m
+CONFIG_INFINIBAND_USER_VERBS=m
 CONFIG_INFINIBAND_MTHCA=m
 # CONFIG_INFINIBAND_MTHCA_DEBUG is not set
 CONFIG_INFINIBAND_IPOIB=m
 # CONFIG_INFINIBAND_IPOIB_DEBUG is not set
 
 #
+# SN Devices
+#
+
+#
 # File systems
 #
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
 CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
 CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_XATTR=y
 CONFIG_EXT3_FS_POSIX_ACL=y
@@ -1144,6 +1161,7 @@ CONFIG_XFS_SECURITY=y
 CONFIG_XFS_POSIX_ACL=y
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
 # CONFIG_QUOTA is not set
 CONFIG_DNOTIFY=y
 CONFIG_AUTOFS_FS=y
@@ -1174,7 +1192,6 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
 CONFIG_DEVPTS_FS_XATTR=y
 CONFIG_DEVPTS_FS_SECURITY=y
 CONFIG_TMPFS=y
@@ -1206,15 +1223,20 @@ CONFIG_CRAMFS=y
 #
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 # CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=m
+CONFIG_NFSD_V2_ACL=y
 CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
 CONFIG_NFSD_V4=y
 CONFIG_NFSD_TCP=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=m
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
 CONFIG_RPCSEC_GSS_KRB5=y
diff --git a/arch/ppc64/kernel/LparData.c b/arch/ppc64/kernel/LparData.c
index 6ffcf67dd50..76cfd1449d5 100644
--- a/arch/ppc64/kernel/LparData.c
+++ b/arch/ppc64/kernel/LparData.c
@@ -33,17 +33,36 @@
  * the hypervisor and Linux.  
  */
 
+/*
+ * WARNING - magic here
+ *
+ * Ok, this is a horrid hack below, but marginally better than the
+ * alternatives.  What we really want is just to initialize
+ * hvReleaseData in C as in the #if 0 section here.  However, gcc
+ * refuses to believe that (u32)&x is a constant expression, so will
+ * not allow the xMsNucDataOffset field to be properly initialized.
+ * So, we declare hvReleaseData in inline asm instead.  We use inline
+ * asm, rather than a .S file, because the assembler won't generate
+ * the necessary relocation for the LparMap either, unless that symbol
+ * is declared in the same source file.  Finally, we put the asm in a
+ * dummy, attribute-used function, instead of at file scope, because
+ * file scope asms don't allow contraints.  We want to use the "i"
+ * constraints to put sizeof() and offsetof() expressions in there,
+ * because including asm/offsets.h in C code then stringifying causes
+ * all manner of warnings.
+ */
+#if 0
 struct HvReleaseData hvReleaseData = {
 	.xDesc = 0xc8a5d9c4,	/* "HvRD" ebcdic */
 	.xSize = sizeof(struct HvReleaseData),
 	.xVpdAreasPtrOffset = offsetof(struct naca_struct, xItVpdAreas),
 	.xSlicNacaAddr = &naca,		/* 64-bit Naca address */
-	.xMsNucDataOffset = 0x4800,	/* offset of LparMap within loadarea (see head.S) */
-	.xTagsMode = 1,			/* tags inactive       */
-	.xAddressSize = 0,		/* 64 bit              */
-	.xNoSharedProcs = 0,		/* shared processors   */
-	.xNoHMT = 0,			/* HMT allowed         */
-	.xRsvd2 = 6,			/* TEMP: This allows non-GA driver */
+	.xMsNucDataOffset = (u32)((unsigned long)&xLparMap - KERNELBASE),
+	.xFlags = HVREL_TAGSINACTIVE	/* tags inactive       */
+					/* 64 bit              */
+					/* shared processors   */
+					/* HMT allowed         */
+		  | 6,			/* TEMP: This allows non-GA driver */
 	.xVrmIndex = 4,			/* We are v5r2m0               */
 	.xMinSupportedPlicVrmIndex = 3,		/* v5r1m0 */
 	.xMinCompatablePlicVrmIndex = 3,	/* v5r1m0 */
@@ -51,6 +70,63 @@ struct HvReleaseData hvReleaseData = {
 		0xa7, 0x40, 0xf2, 0x4b,
 		0xf4, 0x4b, 0xf6, 0xf4 },
 };
+#endif
+
+
+extern struct HvReleaseData hvReleaseData;
+
+static void __attribute_used__ hvReleaseData_wrapper(void)
+{
+	/* This doesn't appear to need any alignment (even 4 byte) */
+	asm volatile (
+		"	lparMapPhys = xLparMap - %3\n"
+		"	.data\n"
+		"	.globl	hvReleaseData\n"
+		"hvReleaseData:\n"
+		"	.long	0xc8a5d9c4\n"	/* xDesc */
+						/* "HvRD" in ebcdic */
+		"	.short	%0\n"		/* xSize */
+		"	.short	%1\n"		/* xVpdAreasPtrOffset */
+		"	.llong	naca\n"		/* xSlicNacaAddr */
+		"	.long	lparMapPhys\n"	/* xMsNucDataOffset */
+		"	.long	0\n"		/* xRsvd1 */
+		"	.short	%2\n"		/* xFlags */
+		"	.short	4\n"	/* xVrmIndex  - v5r2m0 */
+		"	.short	3\n"	/* xMinSupportedPlicVrmIndex - v5r1m0 */
+		"	.short	3\n"	/* xMinCompatablePlicVrmIndex - v5r1m0 */
+		"	.long	0xd38995a4\n"	/* xVrmName */
+		"	.long	0xa740f24b\n"	/*   "Linux 2.4.64" ebcdic */
+		"	.long	0xf44bf6f4\n"
+		"	. = hvReleaseData + %0\n"
+		"	.previous\n"
+		: : "i"(sizeof(hvReleaseData)),
+		"i"(offsetof(struct naca_struct, xItVpdAreas)),
+		"i"(HVREL_TAGSINACTIVE /* tags inactive, 64 bit, */
+				       /* shared processors, HMT allowed */
+		    | 6), /* TEMP: This allows non-GA drivers */
+		"i"(KERNELBASE)
+		);
+}
+
+struct LparMap __attribute__((aligned (16))) xLparMap = {
+	.xNumberEsids = HvEsidsToMap,
+	.xNumberRanges = HvRangesToMap,
+	.xSegmentTableOffs = STAB0_PAGE,
+
+	.xEsids = {
+		{ .xKernelEsid = GET_ESID(KERNELBASE),
+		  .xKernelVsid = KERNEL_VSID(KERNELBASE), },
+		{ .xKernelEsid = GET_ESID(VMALLOCBASE),
+		  .xKernelVsid = KERNEL_VSID(VMALLOCBASE), },
+	},
+
+	.xRanges = {
+		{ .xPages = HvPagesToMap,
+		  .xOffset = 0,
+		  .xVPN = KERNEL_VSID(KERNELBASE) << (SID_SHIFT - PAGE_SHIFT),
+		},
+	},
+};
 
 extern void system_reset_iSeries(void);
 extern void machine_check_iSeries(void);
diff --git a/arch/ppc64/kernel/head.S b/arch/ppc64/kernel/head.S
index 93ebcac0d5a..784f56d4684 100644
--- a/arch/ppc64/kernel/head.S
+++ b/arch/ppc64/kernel/head.S
@@ -522,36 +522,9 @@ __end_interrupts:
 #ifdef CONFIG_PPC_ISERIES
 	.globl naca
 naca:
-	.llong itVpdAreas
-
-	/*
-	 * The iSeries LPAR map is at this fixed address
-	 * so that the HvReleaseData structure can address
-	 * it with a 32-bit offset.
-	 *
-	 * The VSID values below are dependent on the
-	 * VSID generation algorithm.  See include/asm/mmu_context.h.
-	 */
-
-	. = 0x4800
-
-	.llong	2		/* # ESIDs to be mapped by hypervisor	 */
-	.llong	1		/* # memory ranges to be mapped by hypervisor */
-	.llong	STAB0_PAGE	/* Page # of segment table within load area	*/
-	.llong	0		/* Reserved */
-	.llong	0		/* Reserved */
-	.llong	0		/* Reserved */
-	.llong	0		/* Reserved */
-	.llong	0		/* Reserved */
-	.llong	(KERNELBASE>>SID_SHIFT)
-	.llong	0x408f92c94	/* KERNELBASE VSID */
-	/* We have to list the bolted VMALLOC segment here, too, so that it
-	 * will be restored on shared processor switch */
-	.llong	(VMALLOCBASE>>SID_SHIFT)
-	.llong	0xf09b89af5	/* VMALLOCBASE VSID */
-	.llong	8192		/* # pages to map (32 MB) */
-	.llong	0		/* Offset from start of loadarea to start of map */
-	.llong	0x408f92c940000	/* VPN of first page to map */
+	.llong	itVpdAreas
+	.llong	0		/* xRamDisk */
+	.llong	0		/* xRamDiskSize */
 
 	. = 0x6100
 
@@ -2098,7 +2071,7 @@ _GLOBAL(hmt_start_secondary)
 	blr
 #endif
 
-#if defined(CONFIG_SMP) && !defined(CONFIG_PPC_ISERIES)
+#if defined(CONFIG_KEXEC) || (defined(CONFIG_SMP) && !defined(CONFIG_PPC_ISERIES))
 _GLOBAL(smp_release_cpus)
 	/* All secondary cpus are spinning on a common
 	 * spinloop, release them all now so they can start
@@ -2131,13 +2104,6 @@ empty_zero_page:
 swapper_pg_dir:
 	.space	4096
 
-#ifdef CONFIG_SMP
-/* 1 page segment table per cpu (max 48, cpu0 allocated at STAB0_PHYS_ADDR) */
-	.globl	stab_array
-stab_array:
-	.space	4096 * 48
-#endif
-	
 /*
  * This space gets a copy of optional info passed to us by the bootstrap
  * Used to pass parameters into the kernel like root=/dev/sda1, etc.
diff --git a/arch/ppc64/kernel/machine_kexec.c b/arch/ppc64/kernel/machine_kexec.c
index fdb2fc649d7..4775f12a013 100644
--- a/arch/ppc64/kernel/machine_kexec.c
+++ b/arch/ppc64/kernel/machine_kexec.c
@@ -185,7 +185,7 @@ void kexec_copy_flush(struct kimage *image)
 void kexec_smp_down(void *arg)
 {
 	if (ppc_md.cpu_irq_down)
-		ppc_md.cpu_irq_down();
+		ppc_md.cpu_irq_down(1);
 
 	local_irq_disable();
 	kexec_smp_wait();
@@ -232,7 +232,7 @@ static void kexec_prepare_cpus(void)
 
 	/* after we tell the others to go down */
 	if (ppc_md.cpu_irq_down)
-		ppc_md.cpu_irq_down();
+		ppc_md.cpu_irq_down(0);
 
 	put_cpu();
 
@@ -243,15 +243,19 @@ static void kexec_prepare_cpus(void)
 
 static void kexec_prepare_cpus(void)
 {
+	extern void smp_release_cpus(void);
 	/*
 	 * move the secondarys to us so that we can copy
 	 * the new kernel 0-0x100 safely
 	 *
 	 * do this if kexec in setup.c ?
+	 *
+	 * We need to release the cpus if we are ever going from an
+	 * UP to an SMP kernel.
 	 */
-	smp_relase_cpus();
+	smp_release_cpus();
 	if (ppc_md.cpu_irq_down)
-		ppc_md.cpu_irq_down();
+		ppc_md.cpu_irq_down(0);
 	local_irq_disable();
 }
 
diff --git a/arch/ppc64/kernel/misc.S b/arch/ppc64/kernel/misc.S
index 59f4f997381..a05b50b738e 100644
--- a/arch/ppc64/kernel/misc.S
+++ b/arch/ppc64/kernel/misc.S
@@ -1129,6 +1129,9 @@ _GLOBAL(sys_call_table32)
 	.llong .compat_sys_waitid
 	.llong .sys32_ioprio_set
 	.llong .sys32_ioprio_get
+	.llong .sys_inotify_init	/* 275 */
+	.llong .sys_inotify_add_watch
+	.llong .sys_inotify_rm_watch
 
 	.balign 8
 _GLOBAL(sys_call_table)
@@ -1407,3 +1410,6 @@ _GLOBAL(sys_call_table)
 	.llong .sys_waitid
 	.llong .sys_ioprio_set
 	.llong .sys_ioprio_get
+	.llong .sys_inotify_init	/* 275 */
+	.llong .sys_inotify_add_watch
+	.llong .sys_inotify_rm_watch
diff --git a/arch/ppc64/kernel/mpic.c b/arch/ppc64/kernel/mpic.c
index e8fbab1df37..cc262a05ddb 100644
--- a/arch/ppc64/kernel/mpic.c
+++ b/arch/ppc64/kernel/mpic.c
@@ -794,10 +794,10 @@ void mpic_setup_this_cpu(void)
 
 /*
  * XXX: someone who knows mpic should check this.
- * do we need to eoi the ipi here (see xics comments)?
+ * do we need to eoi the ipi including for kexec cpu here (see xics comments)?
  * or can we reset the mpic in the new kernel?
  */
-void mpic_teardown_this_cpu(void)
+void mpic_teardown_this_cpu(int secondary)
 {
 	struct mpic *mpic = mpic_primary;
 	unsigned long flags;
diff --git a/arch/ppc64/kernel/mpic.h b/arch/ppc64/kernel/mpic.h
index 99fbbc9a084..ca78a7f1052 100644
--- a/arch/ppc64/kernel/mpic.h
+++ b/arch/ppc64/kernel/mpic.h
@@ -256,7 +256,7 @@ extern unsigned int mpic_irq_get_priority(unsigned int irq);
 extern void mpic_setup_this_cpu(void);
 
 /* Clean up for kexec (or cpu offline or ...) */
-extern void mpic_teardown_this_cpu(void);
+extern void mpic_teardown_this_cpu(int secondary);
 
 /* Request IPIs on primary mpic */
 extern void mpic_request_ipis(void);
diff --git a/arch/ppc64/kernel/pci.c b/arch/ppc64/kernel/pci.c
index ae6f579d3fa..d0d55c7908e 100644
--- a/arch/ppc64/kernel/pci.c
+++ b/arch/ppc64/kernel/pci.c
@@ -108,8 +108,28 @@ void  pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region
 	region->end = res->end - offset;
 }
 
+void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+			      struct pci_bus_region *region)
+{
+	unsigned long offset = 0;
+	struct pci_controller *hose = pci_bus_to_host(dev->bus);
+
+	if (!hose)
+		return;
+
+	if (res->flags & IORESOURCE_IO)
+	        offset = (unsigned long)hose->io_base_virt - pci_io_base;
+
+	if (res->flags & IORESOURCE_MEM)
+		offset = hose->pci_mem_offset;
+
+	res->start = region->start + offset;
+	res->end = region->end + offset;
+}
+
 #ifdef CONFIG_HOTPLUG
 EXPORT_SYMBOL(pcibios_resource_to_bus);
+EXPORT_SYMBOL(pcibios_bus_to_resource);
 #endif
 
 /*
diff --git a/arch/ppc64/kernel/pmac_setup.c b/arch/ppc64/kernel/pmac_setup.c
index 3013cdb5f93..e40877fa67c 100644
--- a/arch/ppc64/kernel/pmac_setup.c
+++ b/arch/ppc64/kernel/pmac_setup.c
@@ -97,7 +97,7 @@ EXPORT_SYMBOL(smu_cmdbuf_abs);
 
 extern void udbg_init_scc(struct device_node *np);
 
-void __pmac pmac_show_cpuinfo(struct seq_file *m)
+static void __pmac pmac_show_cpuinfo(struct seq_file *m)
 {
 	struct device_node *np;
 	char *pp;
@@ -144,7 +144,7 @@ void __pmac pmac_show_cpuinfo(struct seq_file *m)
 }
 
 
-void __init pmac_setup_arch(void)
+static void __init pmac_setup_arch(void)
 {
 	/* init to some ~sane value until calibrate_delay() runs */
 	loops_per_jiffy = 50000000;
@@ -230,7 +230,7 @@ void __pmac note_bootable_part(dev_t dev, int part, int goodness)
 	}
 }
 
-void __pmac pmac_restart(char *cmd)
+static void __pmac pmac_restart(char *cmd)
 {
 	switch(sys_ctrler) {
 #ifdef CONFIG_ADB_PMU
@@ -249,7 +249,7 @@ void __pmac pmac_restart(char *cmd)
 	}
 }
 
-void __pmac pmac_power_off(void)
+static void __pmac pmac_power_off(void)
 {
 	switch(sys_ctrler) {
 #ifdef CONFIG_ADB_PMU
@@ -267,7 +267,7 @@ void __pmac pmac_power_off(void)
 	}
 }
 
-void __pmac pmac_halt(void)
+static void __pmac pmac_halt(void)
 {
 	pmac_power_off();
 }
@@ -327,7 +327,7 @@ static void __init init_boot_display(void)
 /* 
  * Early initialization.
  */
-void __init pmac_init_early(void)
+static void __init pmac_init_early(void)
 {
 	DBG(" -> pmac_init_early\n");
 
diff --git a/arch/ppc64/kernel/prom.c b/arch/ppc64/kernel/prom.c
index 47727a6f734..5aca01ddd81 100644
--- a/arch/ppc64/kernel/prom.c
+++ b/arch/ppc64/kernel/prom.c
@@ -916,6 +916,7 @@ static int __init early_init_dt_scan_cpus(unsigned long node,
 		}
 	}
 
+#ifdef CONFIG_ALTIVEC
 	/* Check if we have a VMX and eventually update CPU features */
 	prop = (u32 *)get_flat_dt_prop(node, "ibm,vmx", NULL);
 	if (prop && (*prop) > 0) {
@@ -929,6 +930,7 @@ static int __init early_init_dt_scan_cpus(unsigned long node,
 		cur_cpu_spec->cpu_features |= CPU_FTR_ALTIVEC;
 		cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_ALTIVEC;
 	}
+#endif /* CONFIG_ALTIVEC */
 
 	/*
 	 * Check for an SMT capable CPU and set the CPU feature. We do
diff --git a/arch/ppc64/kernel/setup.c b/arch/ppc64/kernel/setup.c
index e80f10c8982..687e8559520 100644
--- a/arch/ppc64/kernel/setup.c
+++ b/arch/ppc64/kernel/setup.c
@@ -1068,6 +1068,8 @@ void __init setup_arch(char **cmdline_p)
 	irqstack_early_init();
 	emergency_stack_init();
 
+	stabs_alloc();
+
 	/* set up the bootmem stuff with available memory */
 	do_init_bootmem();
 	sparse_init();
diff --git a/arch/ppc64/kernel/smp.c b/arch/ppc64/kernel/smp.c
index 2fcddfcb594..793b562da65 100644
--- a/arch/ppc64/kernel/smp.c
+++ b/arch/ppc64/kernel/smp.c
@@ -65,8 +65,6 @@ struct smp_ops_t *smp_ops;
 
 static volatile unsigned int cpu_callin_map[NR_CPUS];
 
-extern unsigned char stab_array[];
-
 void smp_call_function_interrupt(void);
 
 int smt_enabled_at_boot = 1;
@@ -492,19 +490,6 @@ int __devinit __cpu_up(unsigned int cpu)
 
 	paca[cpu].default_decr = tb_ticks_per_jiffy;
 
-	if (!cpu_has_feature(CPU_FTR_SLB)) {
-		void *tmp;
-
-		/* maximum of 48 CPUs on machines with a segment table */
-		if (cpu >= 48)
-			BUG();
-
-		tmp = &stab_array[PAGE_SIZE * cpu];
-		memset(tmp, 0, PAGE_SIZE); 
-		paca[cpu].stab_addr = (unsigned long)tmp;
-		paca[cpu].stab_real = virt_to_abs(tmp);
-	}
-
 	/* Make sure callin-map entry is 0 (can be leftover a CPU
 	 * hotplug
 	 */
diff --git a/arch/ppc64/kernel/udbg.c b/arch/ppc64/kernel/udbg.c
index d4ccd6f1ef4..c0da45540f0 100644
--- a/arch/ppc64/kernel/udbg.c
+++ b/arch/ppc64/kernel/udbg.c
@@ -141,7 +141,7 @@ void udbg_init_scc(struct device_node *np)
 
 #endif /* CONFIG_PPC_PMAC */
 
-#if CONFIG_PPC_PMAC
+#ifdef CONFIG_PPC_PMAC
 static void udbg_real_putc(unsigned char c)
 {
 	while ((real_readb(sccc) & SCC_TXRDY) == 0)
diff --git a/arch/ppc64/kernel/xics.c b/arch/ppc64/kernel/xics.c
index 677c4450984..d9dc6f28d05 100644
--- a/arch/ppc64/kernel/xics.c
+++ b/arch/ppc64/kernel/xics.c
@@ -647,29 +647,30 @@ static void xics_set_affinity(unsigned int virq, cpumask_t cpumask)
 	}
 }
 
-void xics_teardown_cpu(void)
+void xics_teardown_cpu(int secondary)
 {
 	int cpu = smp_processor_id();
-	int status;
 
 	ops->cppr_info(cpu, 0x00);
 	iosync();
 
 	/*
-	 * we need to EOI the IPI if we got here from kexec down IPI
-	 *
-	 * xics doesn't care if we duplicate an EOI as long as we
-	 * don't EOI and raise priority.
-	 *
-	 * probably need to check all the other interrupts too
-	 * should we be flagging idle loop instead?
-	 * or creating some task to be scheduled?
+	 * Some machines need to have at least one cpu in the GIQ,
+	 * so leave the master cpu in the group.
 	 */
-	ops->xirr_info_set(cpu, XICS_IPI);
-
-	status = rtas_set_indicator(GLOBAL_INTERRUPT_QUEUE,
-		(1UL << interrupt_server_size) - 1 - default_distrib_server, 0);
-	WARN_ON(status != 0);
+	if (secondary) {
+		/*
+		 * we need to EOI the IPI if we got here from kexec down IPI
+		 *
+		 * probably need to check all the other interrupts too
+		 * should we be flagging idle loop instead?
+		 * or creating some task to be scheduled?
+		 */
+		ops->xirr_info_set(cpu, XICS_IPI);
+		rtas_set_indicator(GLOBAL_INTERRUPT_QUEUE,
+			(1UL << interrupt_server_size) - 1 -
+			default_distrib_server, 0);
+	}
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
diff --git a/arch/ppc64/mm/numa.c b/arch/ppc64/mm/numa.c
index cafd91aef28..0b191f2de01 100644
--- a/arch/ppc64/mm/numa.c
+++ b/arch/ppc64/mm/numa.c
@@ -647,7 +647,12 @@ void __init do_init_bootmem(void)
 new_range:
 			mem_start = read_n_cells(addr_cells, &memcell_buf);
 			mem_size = read_n_cells(size_cells, &memcell_buf);
-			numa_domain = numa_enabled ? of_node_numa_domain(memory) : 0;
+			if (numa_enabled) {
+				numa_domain = of_node_numa_domain(memory);
+				if (numa_domain  >= MAX_NUMNODES)
+					numa_domain = 0;
+			} else
+				numa_domain =  0;
 
 			if (numa_domain != nid)
 				continue;
diff --git a/arch/ppc64/mm/stab.c b/arch/ppc64/mm/stab.c
index df4bbe14153..1b83f002bf2 100644
--- a/arch/ppc64/mm/stab.c
+++ b/arch/ppc64/mm/stab.c
@@ -18,6 +18,8 @@
 #include <asm/mmu_context.h>
 #include <asm/paca.h>
 #include <asm/cputable.h>
+#include <asm/lmb.h>
+#include <asm/abs_addr.h>
 
 struct stab_entry {
 	unsigned long esid_data;
@@ -224,6 +226,39 @@ void switch_stab(struct task_struct *tsk, struct mm_struct *mm)
 extern void slb_initialize(void);
 
 /*
+ * Allocate segment tables for secondary CPUs.  These must all go in
+ * the first (bolted) segment, so that do_stab_bolted won't get a
+ * recursive segment miss on the segment table itself.
+ */
+void stabs_alloc(void)
+{
+	int cpu;
+
+	if (cpu_has_feature(CPU_FTR_SLB))
+		return;
+
+	for_each_cpu(cpu) {
+		unsigned long newstab;
+
+		if (cpu == 0)
+			continue; /* stab for CPU 0 is statically allocated */
+
+		newstab = lmb_alloc_base(PAGE_SIZE, PAGE_SIZE, 1<<SID_SHIFT);
+		if (! newstab)
+			panic("Unable to allocate segment table for CPU %d.\n",
+			      cpu);
+
+		newstab += KERNELBASE;
+
+		memset((void *)newstab, 0, PAGE_SIZE);
+
+		paca[cpu].stab_addr = newstab;
+		paca[cpu].stab_real = virt_to_abs(newstab);
+		printk(KERN_DEBUG "Segment table for CPU %d at 0x%lx virtual, 0x%lx absolute\n", cpu, paca[cpu].stab_addr, paca[cpu].stab_real);
+	}
+}
+
+/*
  * Build an entry for the base kernel segment and put it into
  * the segment table or SLB.  All other segment table or SLB
  * entries are faulted in.
diff --git a/arch/ppc64/xmon/xmon.c b/arch/ppc64/xmon/xmon.c
index 7f6e13a4b71..05539439e6b 100644
--- a/arch/ppc64/xmon/xmon.c
+++ b/arch/ppc64/xmon/xmon.c
@@ -329,13 +329,16 @@ int xmon_core(struct pt_regs *regs, int fromipi)
 		printf("cpu 0x%x: Exception %lx %s in xmon, "
 		       "returning to main loop\n",
 		       cpu, regs->trap, getvecname(TRAP(regs)));
+		release_output_lock();
 		longjmp(xmon_fault_jmp[cpu], 1);
 	}
 
 	if (setjmp(recurse_jmp) != 0) {
 		if (!in_xmon || !xmon_gate) {
+			get_output_lock();
 			printf("xmon: WARNING: bad recursive fault "
 			       "on cpu 0x%x\n", cpu);
+			release_output_lock();
 			goto waiting;
 		}
 		secondary = !(xmon_taken && cpu == xmon_owner);
diff --git a/arch/s390/appldata/appldata_base.c b/arch/s390/appldata/appldata_base.c
index c067435bae4..c9f2f60cfa5 100644
--- a/arch/s390/appldata/appldata_base.c
+++ b/arch/s390/appldata/appldata_base.c
@@ -232,7 +232,11 @@ static int appldata_diag(char record_nr, u16 function, unsigned long buffer,
 	ry = -1;
 	asm volatile(
 			"diag %1,%0,0xDC\n\t"
-			: "=d" (ry) : "d" (&(appldata_parameter_list)) : "cc");
+			: "=d" (ry)
+			: "d" (&appldata_parameter_list),
+			  "m" (appldata_parameter_list),
+			  "m" (appldata_product_id)
+			: "cc");
 	return (int) ry;
 }
 /************************ timer, work, DIAG <END> ****************************/
diff --git a/arch/s390/defconfig b/arch/s390/defconfig
index 89850b2c27e..0865251a3f4 100644
--- a/arch/s390/defconfig
+++ b/arch/s390/defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc3
-# Fri Apr 22 15:30:58 2005
+# Linux kernel version: 2.6.13-rc4
+# Fri Jul 29 14:49:30 2005
 #
 CONFIG_MMU=y
 CONFIG_RWSEM_XCHGADD_ALGORITHM=y
@@ -23,10 +23,11 @@ CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
-# CONFIG_POSIX_MQUEUE is not set
+CONFIG_POSIX_MQUEUE=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 CONFIG_SYSCTL=y
-# CONFIG_AUDIT is not set
+CONFIG_AUDIT=y
+# CONFIG_AUDITSYSCALL is not set
 CONFIG_HOTPLUG=y
 CONFIG_KOBJECT_UEVENT=y
 CONFIG_IKCONFIG=y
@@ -36,6 +37,8 @@ CONFIG_IKCONFIG_PROC=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
@@ -51,9 +54,10 @@ CONFIG_BASE_SMALL=0
 # Loadable module support
 #
 CONFIG_MODULES=y
-# CONFIG_MODULE_UNLOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
 CONFIG_OBSOLETE_MODPARM=y
-# CONFIG_MODVERSIONS is not set
+CONFIG_MODVERSIONS=y
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
 CONFIG_STOP_MACHINE=y
@@ -81,8 +85,15 @@ CONFIG_MARCH_G5=y
 # CONFIG_MARCH_Z990 is not set
 CONFIG_PACK_STACK=y
 # CONFIG_SMALL_STACK is not set
-# CONFIG_CHECK_STACK is not set
+CONFIG_CHECK_STACK=y
+CONFIG_STACK_GUARD=256
 # CONFIG_WARN_STACK is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
 
 #
 # I/O subsystem configuration
@@ -95,7 +106,7 @@ CONFIG_QDIO=y
 #
 # Misc
 #
-# CONFIG_PREEMPT is not set
+CONFIG_PREEMPT=y
 CONFIG_IPL=y
 # CONFIG_IPL_TAPE is not set
 CONFIG_IPL_VM=y
@@ -105,9 +116,110 @@ CONFIG_BINFMT_MISC=m
 CONFIG_PFAULT=y
 # CONFIG_SHARED_KERNEL is not set
 # CONFIG_CMM is not set
-# CONFIG_VIRT_TIMER is not set
+CONFIG_VIRT_TIMER=y
+CONFIG_VIRT_CPU_ACCOUNTING=y
+# CONFIG_APPLDATA_BASE is not set
 CONFIG_NO_IDLE_HZ=y
 CONFIG_NO_IDLE_HZ_INIT=y
+# CONFIG_KEXEC is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_IP_TCPDIAG=y
+CONFIG_IP_TCPDIAG_IPV6=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+CONFIG_IPV6=y
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_CLK_JIFFIES=y
+# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set
+# CONFIG_NET_SCH_CLK_CPU is not set
+CONFIG_NET_SCH_CBQ=m
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_INGRESS is not set
+CONFIG_NET_QOS=y
+CONFIG_NET_ESTIMATOR=y
+CONFIG_NET_CLS=y
+# CONFIG_NET_CLS_BASIC is not set
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+# CONFIG_CLS_U32_PERF is not set
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_CLS_POLICE=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
 # CONFIG_PCMCIA is not set
 
 #
@@ -133,6 +245,7 @@ CONFIG_CHR_DEV_ST=y
 CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
 CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
 
 #
 # Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -205,7 +318,13 @@ CONFIG_MD_RAID5=m
 # CONFIG_MD_RAID6 is not set
 CONFIG_MD_MULTIPATH=m
 # CONFIG_MD_FAULTY is not set
-# CONFIG_BLK_DEV_DM is not set
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_CRYPT=y
+CONFIG_DM_SNAPSHOT=y
+CONFIG_DM_MIRROR=y
+CONFIG_DM_ZERO=y
+CONFIG_DM_MULTIPATH=y
+# CONFIG_DM_MULTIPATH_EMC is not set
 
 #
 # Character device drivers
@@ -231,7 +350,8 @@ CONFIG_CCW_CONSOLE=y
 CONFIG_SCLP=y
 CONFIG_SCLP_TTY=y
 CONFIG_SCLP_CONSOLE=y
-# CONFIG_SCLP_VT220_TTY is not set
+CONFIG_SCLP_VT220_TTY=y
+CONFIG_SCLP_VT220_CONSOLE=y
 CONFIG_SCLP_CPI=m
 CONFIG_S390_TAPE=m
 
@@ -255,105 +375,8 @@ CONFIG_S390_TAPE_34XX=m
 CONFIG_Z90CRYPT=m
 
 #
-# Networking support
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_IP_TCPDIAG=y
-CONFIG_IP_TCPDIAG_IPV6=y
-CONFIG_IPV6=y
-# CONFIG_IPV6_PRIVACY is not set
-# CONFIG_INET6_AH is not set
-# CONFIG_INET6_ESP is not set
-# CONFIG_INET6_IPCOMP is not set
-# CONFIG_INET6_TUNNEL is not set
-# CONFIG_IPV6_TUNNEL is not set
-# CONFIG_NETFILTER is not set
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_CLK_JIFFIES=y
-# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set
-# CONFIG_NET_SCH_CLK_CPU is not set
-CONFIG_NET_SCH_CBQ=m
-# CONFIG_NET_SCH_HTB is not set
-# CONFIG_NET_SCH_HFSC is not set
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-# CONFIG_NET_SCH_NETEM is not set
-# CONFIG_NET_SCH_INGRESS is not set
-CONFIG_NET_QOS=y
-CONFIG_NET_ESTIMATOR=y
-CONFIG_NET_CLS=y
-# CONFIG_NET_CLS_BASIC is not set
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_ROUTE=y
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-# CONFIG_CLS_U32_PERF is not set
-# CONFIG_NET_CLS_IND is not set
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-# CONFIG_NET_EMATCH is not set
-# CONFIG_NET_CLS_ACT is not set
-CONFIG_NET_CLS_POLICE=y
-
-#
-# Network testing
+# Network device support
 #
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
 CONFIG_BONDING=m
@@ -411,12 +434,15 @@ CONFIG_CCWGROUP=y
 # CONFIG_SLIP is not set
 # CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
 
 #
 # File systems
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_XATTR=y
 # CONFIG_EXT3_FS_POSIX_ACL is not set
@@ -426,6 +452,7 @@ CONFIG_JBD=y
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
 
 #
 # XFS support
@@ -433,6 +460,7 @@ CONFIG_FS_MBCACHE=y
 # CONFIG_XFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
 # CONFIG_QUOTA is not set
 CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
@@ -457,7 +485,6 @@ CONFIG_DNOTIFY=y
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
 # CONFIG_DEVPTS_FS_XATTR is not set
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_XATTR is not set
@@ -486,15 +513,18 @@ CONFIG_RAMFS=y
 #
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
 # CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=y
 CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
 # CONFIG_NFSD_V4 is not set
 CONFIG_NFSD_TCP=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -544,11 +574,12 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_LOG_BUF_SHIFT=17
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_KOBJECT is not set
 # CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_FS is not set
+CONFIG_DEBUG_FS=y
 
 #
 # Security options
diff --git a/arch/s390/kernel/compat_wrapper.S b/arch/s390/kernel/compat_wrapper.S
index 799a98eac92..23fe94e5868 100644
--- a/arch/s390/kernel/compat_wrapper.S
+++ b/arch/s390/kernel/compat_wrapper.S
@@ -1449,3 +1449,29 @@ compat_sys_kexec_load_wrapper:
 	llgtr	%r4,%r4			# struct kexec_segment *
 	llgfr	%r5,%r5			# unsigned long
 	jg	compat_sys_kexec_load
+
+	.globl	sys_ioprio_set_wrapper
+sys_ioprio_set_wrapper:
+	lgfr	%r2,%r2			# int
+	lgfr	%r3,%r3			# int
+	lgfr	%r4,%r4			# int
+	jg	sys_ioprio_set
+
+	.globl	sys_ioprio_get_wrapper
+sys_ioprio_get_wrapper:
+	lgfr	%r2,%r2			# int
+	lgfr	%r3,%r3			# int
+	jg	sys_ioprio_get
+
+	.globl	sys_inotify_add_watch_wrapper
+sys_inotify_add_watch_wrapper:
+	lgfr	%r2,%r2			# int
+	llgtr	%r3,%r3			# const char *
+	llgfr	%r4,%r4			# u32
+	jg	sys_inotify_add_watch
+
+	.globl	sys_inotify_rm_watch_wrapper
+sys_inotify_rm_watch_wrapper:
+	lgfr	%r2,%r2			# int
+	llgfr	%r3,%r3			# u32
+	jg	sys_inotify_rm_watch
diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S
index 5b262b5d869..1a271b16cb5 100644
--- a/arch/s390/kernel/entry.S
+++ b/arch/s390/kernel/entry.S
@@ -690,9 +690,9 @@ mcck_int_handler:
 	bo	BASED(0f)
 	spt	__LC_LAST_UPDATE_TIMER	# revalidate cpu timer
 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
-	mvc	__LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
-	mvc	__LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
-	mvc	__LC_LAST_UPDATE_TIMER(8),__LC_EXIT_TIMER
+	mvc	__LC_ASYNC_ENTER_TIMER(8),__LC_LAST_UPDATE_TIMER
+	mvc	__LC_SYNC_ENTER_TIMER(8),__LC_LAST_UPDATE_TIMER
+	mvc	__LC_EXIT_TIMER(8),__LC_LAST_UPDATE_TIMER
 0:	tm	__LC_MCCK_CODE+2,0x08   # mwp of old psw valid?
 	bno	BASED(mcck_no_vtime)	# no -> skip cleanup critical
 	tm	__LC_MCK_OLD_PSW+1,0x01 # interrupting from user ?
diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S
index 57ca75d0ad7..d9f22915008 100644
--- a/arch/s390/kernel/entry64.S
+++ b/arch/s390/kernel/entry64.S
@@ -727,9 +727,9 @@ mcck_int_handler:
 	jo	0f
 	spt	__LC_LAST_UPDATE_TIMER
 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
-	mvc	__LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
-	mvc	__LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
-	mvc	__LC_LAST_UPDATE_TIMER(8),__LC_EXIT_TIMER
+	mvc	__LC_ASYNC_ENTER_TIMER(8),__LC_LAST_UPDATE_TIMER
+	mvc	__LC_SYNC_ENTER_TIMER(8),__LC_LAST_UPDATE_TIMER
+	mvc	__LC_EXIT_TIMER(8),__LC_LAST_UPDATE_TIMER
 0:	tm	__LC_MCCK_CODE+2,0x08	# mwp of old psw valid?
 	jno	mcck_no_vtime		# no -> no timer update
 	tm      __LC_MCK_OLD_PSW+1,0x01 # interrupting from user ?
diff --git a/arch/s390/kernel/head.S b/arch/s390/kernel/head.S
index fc8bf5e285f..2710e66fefb 100644
--- a/arch/s390/kernel/head.S
+++ b/arch/s390/kernel/head.S
@@ -346,6 +346,13 @@ iplstart:
         la    %r2,.Lreset              
         lhi   %r3,26
 	diag  %r2,%r3,8
+	la    %r5,.Lirb
+	stsch 0(%r5)			       # check if irq is pending
+	tm    30(%r5),0x0f		       # by verifying if any of the
+	bnz   .Lwaitforirq		       # activity or status control
+	tm    31(%r5),0xff		       # bits is set in the schib
+	bz    .Lnoreset
+.Lwaitforirq:
 	mvc   0x78(8),.Lrdrnewpsw              # set up IO interrupt psw
 .Lwaitrdrirq:
 	lpsw  .Lrdrwaitpsw
@@ -535,8 +542,13 @@ startup:basr  %r13,0                     # get base
 	lhi   %r1,0
 	icm   %r1,3,.Lscpincr1-PARMAREA(%r4) # use this one if != 0
 	jnz   .Lscnd
-	l     %r1,.Lscpincr2-PARMAREA+4(%r4) # otherwise use this one
+	lhi   %r1,0x800			# otherwise report 2GB
 .Lscnd:
+	lhi   %r3,0x800			# limit reported memory size to 2GB
+	cr    %r1,%r3
+	jl    .Lno2gb
+	lr    %r1,%r3
+.Lno2gb:
 	xr    %r3,%r3			# same logic
 	ic    %r3,.Lscpa1-PARMAREA(%r4)
 	chi   %r3,0x00
@@ -765,7 +777,7 @@ _stext:	basr  %r13,0                    # get base
 
 # check control registers
         stctl  %c0,%c15,0(%r15)
-	oi     2(%r15),0x20             # enable sigp external interrupts
+	oi     2(%r15),0x40             # enable sigp emergency signal
 	oi     0(%r15),0x10             # switch on low address protection
         lctl   %c0,%c15,0(%r15)
 
diff --git a/arch/s390/kernel/head64.S b/arch/s390/kernel/head64.S
index f525c0c2125..9a8263a153c 100644
--- a/arch/s390/kernel/head64.S
+++ b/arch/s390/kernel/head64.S
@@ -345,6 +345,13 @@ iplstart:
         la    %r2,.Lreset              
         lhi   %r3,26
 	diag  %r2,%r3,8
+	la    %r5,.Lirb
+	stsch 0(%r5)			       # check if irq is pending
+	tm    30(%r5),0x0f		       # by verifying if any of the
+	bnz   .Lwaitforirq		       # activity or status control
+	tm    31(%r5),0xff		       # bits is set in the schib
+	bz    .Lnoreset
+.Lwaitforirq:
 	mvc   0x78(8),.Lrdrnewpsw	       # set up IO interrupt psw
 .Lwaitrdrirq:
 	lpsw  .Lrdrwaitpsw
@@ -658,10 +665,8 @@ startup:basr  %r13,0                     # get base
 #
 	la     %r1,0f-.LPG1(%r13)	# set program check address
 	stg    %r1,__LC_PGM_NEW_PSW+8
-	mvc    __LC_DIAG44_OPCODE(8),.Lnop-.LPG1(%r13)
 	diag   0,0,0x44			# test diag 0x44
 	oi     7(%r12),32		# set diag44 flag
-	mvc    __LC_DIAG44_OPCODE(8),.Ldiag44-.LPG1(%r13)
 0:	
 
 #
@@ -702,7 +707,6 @@ startup:basr  %r13,0                     # get base
 .L4malign:.quad 0xffffffffffc00000
 .Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8
 .Lnop:	.long  0x07000700
-.Ldiag44:.long 0x83000044
 
 	.org PARMAREA-64
 .Lduct:	.long 0,0,0,0,0,0,0,0
@@ -765,7 +769,7 @@ _stext:	basr  %r13,0                    # get base
 
 # check control registers
         stctg  %c0,%c15,0(%r15)
-	oi     6(%r15),0x20             # enable sigp external interrupts
+	oi     6(%r15),0x40             # enable sigp emergency signal
 	oi     4(%r15),0x10             # switch on low address proctection
         lctlg  %c0,%c15,0(%r15)
 
diff --git a/arch/s390/kernel/machine_kexec.c b/arch/s390/kernel/machine_kexec.c
index 2721c3a32b8..5aa71b05b8a 100644
--- a/arch/s390/kernel/machine_kexec.c
+++ b/arch/s390/kernel/machine_kexec.c
@@ -70,6 +70,8 @@ machine_kexec(struct kimage *image)
 	for (;;);
 }
 
+extern void pfault_fini(void);
+
 static void
 kexec_halt_all_cpus(void *kernel_image)
 {
@@ -78,6 +80,11 @@ kexec_halt_all_cpus(void *kernel_image)
 	struct kimage *image;
 	relocate_kernel_t data_mover;
 
+#ifdef CONFIG_PFAULT
+	if (MACHINE_IS_VM)
+		pfault_fini();
+#endif
+
 	if (atomic_compare_and_swap(-1, smp_processor_id(), &cpuid))
 		signal_processor(smp_processor_id(), sigp_stop);
 
diff --git a/arch/s390/kernel/relocate_kernel.S b/arch/s390/kernel/relocate_kernel.S
index d5e4a62fbb7..2a25ec7147f 100644
--- a/arch/s390/kernel/relocate_kernel.S
+++ b/arch/s390/kernel/relocate_kernel.S
@@ -4,6 +4,7 @@
  * (C) Copyright IBM Corp. 2005
  *
  * Author(s): Rolf Adelsberger <adelsberger@de.ibm.com>
+ *	      Heiko Carstens <heiko.carstens@de.ibm.com>
  *
  */
 
@@ -25,8 +26,31 @@
 	relocate_kernel:
 		basr	%r13,0		#base address
 	.base:
-		spx	zero64-.base(%r13)	#absolute addressing mode
 		stnsm	sys_msk-.base(%r13),0xf8	#disable DAT and IRQ (external)
+		spx	zero64-.base(%r13)	#absolute addressing mode
+		stctl	%c0,%c15,ctlregs-.base(%r13)
+		stm	%r0,%r15,gprregs-.base(%r13)
+		la	%r1,load_psw-.base(%r13)
+		mvc     0(8,%r0),0(%r1)
+		la	%r0,.back-.base(%r13)
+		st	%r0,4(%r0)
+		oi	4(%r0),0x80
+		mvc	0x68(8,%r0),0(%r1)
+		la	%r0,.back_pgm-.base(%r13)
+		st	%r0,0x6c(%r0)
+		oi	0x6c(%r0),0x80
+		lhi	%r0,0
+		diag	%r0,%r0,0x308
+	.back:
+		basr	%r13,0
+	.back_base:
+		oi	have_diag308-.back_base(%r13),0x01
+		lctl	%c0,%c15,ctlregs-.back_base(%r13)
+		lm	%r0,%r15,gprregs-.back_base(%r13)
+		j	.start_reloc
+	.back_pgm:
+		lm	%r0,%r15,gprregs-.base(%r13)
+	.start_reloc:
 		lhi	%r10,-1		#preparing the mask
 		sll	%r10,12		#shift it such that it becomes 0xf000
 	.top:
@@ -63,6 +87,10 @@
 		o	%r3,4(%r4)	#or load address into psw
 		st	%r3,4(%r4)
 		mvc	0(8,%r0),0(%r4)	#copy psw to absolute address 0
+		tm	have_diag308-.base(%r13),0x01
+		jno	.no_diag308
+		diag	%r0,%r0,0x308
+	.no_diag308:
 		sr	%r1,%r1		#clear %r1
 		sr	%r2,%r2		#clear %r2
 		sigp	%r1,%r2,0x12	#set cpuid to zero
@@ -75,6 +103,17 @@
 		.long	0x00080000,0x80000000
 	sys_msk:
 		.quad	0
+	ctlregs:
+		.rept	16
+		.long	0
+		.endr
+	gprregs:
+		.rept	16
+		.long	0
+		.endr
+	have_diag308:
+		.byte	0
+		.align	8
 	relocate_kernel_end:
 	.globl	relocate_kernel_len
 	relocate_kernel_len:
diff --git a/arch/s390/kernel/relocate_kernel64.S b/arch/s390/kernel/relocate_kernel64.S
index 96290cc4eb3..8cdb86e8911 100644
--- a/arch/s390/kernel/relocate_kernel64.S
+++ b/arch/s390/kernel/relocate_kernel64.S
@@ -4,6 +4,7 @@
  * (C) Copyright IBM Corp. 2005
  *
  * Author(s): Rolf Adelsberger <adelsberger@de.ibm.com>
+ *	      Heiko Carstens <heiko.carstens@de.ibm.com>
  *
  */
 
@@ -26,8 +27,34 @@
 	relocate_kernel:
 		basr	%r13,0		#base address
 	.base:
+		stnsm	sys_msk-.base(%r13),0xf8	#disable DAT and IRQs
 		spx	zero64-.base(%r13)	#absolute addressing mode
-		stnsm	sys_msk-.base(%r13),0xf8	#disable DAT and IRQ (external)
+		stctg	%c0,%c15,ctlregs-.base(%r13)
+		stmg	%r0,%r15,gprregs-.base(%r13)
+		lghi	%r0,3
+		sllg	%r0,%r0,31
+		stg	%r0,0x1d0(%r0)
+		la	%r0,.back_pgm-.base(%r13)
+		stg	%r0,0x1d8(%r0)
+		la	%r1,load_psw-.base(%r13)
+		mvc     0(8,%r0),0(%r1)
+		la	%r0,.back-.base(%r13)
+		st	%r0,4(%r0)
+		oi	4(%r0),0x80
+		lghi	%r0,0
+		diag	%r0,%r0,0x308
+	.back:
+		lhi	%r1,1		#mode 1 = esame
+		sigp	%r1,%r0,0x12	#switch to esame mode
+		sam64			#switch to 64 bit addressing mode
+		basr	%r13,0
+	.back_base:
+		oi	have_diag308-.back_base(%r13),0x01
+		lctlg	%c0,%c15,ctlregs-.back_base(%r13)
+		lmg	%r0,%r15,gprregs-.back_base(%r13)
+		j	.top
+	.back_pgm:
+		lmg	%r0,%r15,gprregs-.base(%r13)
 	.top:
 		lghi	%r7,4096	#load PAGE_SIZE in r7
 		lghi	%r9,4096	#load PAGE_SIZE in r9
@@ -62,6 +89,10 @@
 		o	%r3,4(%r4)	#or load address into psw
 		st	%r3,4(%r4)
 		mvc     0(8,%r0),0(%r4)	#copy psw to absolute address 0
+		tm	have_diag308-.base(%r13),0x01
+		jno	.no_diag308
+		diag	%r0,%r0,0x308
+	.no_diag308:
 		sam31			#31 bit mode
 		sr      %r1,%r1		#erase register r1
 		sr      %r2,%r2		#erase register r2
@@ -75,8 +106,18 @@
 		.long	0x00080000,0x80000000
 	sys_msk:
 		.quad	0
+	ctlregs:
+		.rept	16
+		.quad	0
+		.endr
+	gprregs:
+		.rept	16
+		.quad	0
+		.endr
+	have_diag308:
+		.byte	0
+		.align	8
 	relocate_kernel_end:
 	.globl	relocate_kernel_len
 	relocate_kernel_len:
 		.quad	relocate_kernel_end - relocate_kernel
-
diff --git a/arch/s390/kernel/s390_ext.c b/arch/s390/kernel/s390_ext.c
index 3bdd38ec71d..207bc511a6e 100644
--- a/arch/s390/kernel/s390_ext.c
+++ b/arch/s390/kernel/s390_ext.c
@@ -19,7 +19,6 @@
 #include <asm/irq.h>
 
 /*
- * Simple hash strategy: index = code & 0xff;
  * ext_int_hash[index] is the start of the list for all external interrupts
  * that hash to this index. With the current set of external interrupts 
  * (0x1202 external call, 0x1004 cpu timer, 0x2401 hwc console, 0x4000
@@ -27,6 +26,11 @@
  */
 ext_int_info_t *ext_int_hash[256] = { 0, };
 
+static inline int ext_hash(__u16 code)
+{
+	return (code + (code >> 9)) & 0xff;
+}
+
 int register_external_interrupt(__u16 code, ext_int_handler_t handler)
 {
         ext_int_info_t *p;
@@ -37,7 +41,7 @@ int register_external_interrupt(__u16 code, ext_int_handler_t handler)
                 return -ENOMEM;
         p->code = code;
         p->handler = handler;
-        index = code & 0xff;
+	index = ext_hash(code);
         p->next = ext_int_hash[index];
         ext_int_hash[index] = p;
         return 0;
@@ -52,7 +56,7 @@ int register_early_external_interrupt(__u16 code, ext_int_handler_t handler,
                 return -EINVAL;
         p->code = code;
         p->handler = handler;
-        index = code & 0xff;
+	index = ext_hash(code);
         p->next = ext_int_hash[index];
         ext_int_hash[index] = p;
         return 0;
@@ -63,7 +67,7 @@ int unregister_external_interrupt(__u16 code, ext_int_handler_t handler)
         ext_int_info_t *p, *q;
         int index;
 
-        index = code & 0xff;
+	index = ext_hash(code);
         q = NULL;
         p = ext_int_hash[index];
         while (p != NULL) {
@@ -90,7 +94,7 @@ int unregister_early_external_interrupt(__u16 code, ext_int_handler_t handler,
 
 	if (p == NULL || p->code != code || p->handler != handler)
 		return -EINVAL;
-	index = code & 0xff;
+	index = ext_hash(code);
 	q = ext_int_hash[index];
 	if (p != q) {
 		while (q != NULL) {
@@ -120,7 +124,7 @@ void do_extint(struct pt_regs *regs, unsigned short code)
 		 */
 		account_ticks(regs);
 	kstat_cpu(smp_processor_id()).irqs[EXTERNAL_INTERRUPT]++;
-        index = code & 0xff;
+        index = ext_hash(code);
 	for (p = ext_int_hash[index]; p; p = p->next) {
 		if (likely(p->code == code)) {
 			if (likely(p->handler))
diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
index a12183989a7..5ba5a5485da 100644
--- a/arch/s390/kernel/setup.c
+++ b/arch/s390/kernel/setup.c
@@ -431,12 +431,6 @@ setup_lowcore(void)
 		ctl_set_bit(14, 29);
 	}
 #endif
-#ifdef CONFIG_ARCH_S390X
-	if (MACHINE_HAS_DIAG44)
-		lc->diag44_opcode = 0x83000044;
-	else
-		lc->diag44_opcode = 0x07000700;
-#endif /* CONFIG_ARCH_S390X */
 	set_prefix((u32)(unsigned long) lc);
 }
 
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
index 642572a8e33..85222fee436 100644
--- a/arch/s390/kernel/smp.c
+++ b/arch/s390/kernel/smp.c
@@ -375,7 +375,7 @@ static void smp_ext_bitcall(int cpu, ec_bit_sig sig)
          * Set signaling bit in lowcore of target cpu and kick it
          */
 	set_bit(sig, (unsigned long *) &lowcore_ptr[cpu]->ext_call_fast);
-	while(signal_processor(cpu, sigp_external_call) == sigp_busy)
+	while(signal_processor(cpu, sigp_emergency_signal) == sigp_busy)
 		udelay(10);
 }
 
@@ -394,7 +394,7 @@ static void smp_ext_bitcall_others(ec_bit_sig sig)
                  * Set signaling bit in lowcore of target cpu and kick it
                  */
 		set_bit(sig, (unsigned long *) &lowcore_ptr[cpu]->ext_call_fast);
-		while (signal_processor(cpu, sigp_external_call) == sigp_busy)
+		while (signal_processor(cpu, sigp_emergency_signal) == sigp_busy)
 			udelay(10);
         }
 }
@@ -537,7 +537,8 @@ int __devinit start_secondary(void *cpuvoid)
 #endif
 #ifdef CONFIG_PFAULT
 	/* Enable pfault pseudo page faults on this cpu. */
-	pfault_init();
+	if (MACHINE_IS_VM)
+		pfault_init();
 #endif
 	/* Mark this cpu as online */
 	cpu_set(smp_processor_id(), cpu_online_map);
@@ -690,7 +691,8 @@ __cpu_disable(void)
 
 #ifdef CONFIG_PFAULT
 	/* Disable pfault pseudo page faults on this cpu. */
-	pfault_fini();
+	if (MACHINE_IS_VM)
+		pfault_fini();
 #endif
 
 	/* disable all external interrupts */
@@ -751,9 +753,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 	unsigned int cpu;
         int i;
 
-        /* request the 0x1202 external interrupt */
-        if (register_external_interrupt(0x1202, do_ext_call_interrupt) != 0)
-                panic("Couldn't request external interrupt 0x1202");
+        /* request the 0x1201 emergency signal external interrupt */
+        if (register_external_interrupt(0x1201, do_ext_call_interrupt) != 0)
+                panic("Couldn't request external interrupt 0x1201");
         smp_check_cpus(max_cpus);
         memset(lowcore_ptr,0,sizeof(lowcore_ptr));  
         /*
diff --git a/arch/s390/kernel/syscalls.S b/arch/s390/kernel/syscalls.S
index a8668afb5f8..426d7cafdab 100644
--- a/arch/s390/kernel/syscalls.S
+++ b/arch/s390/kernel/syscalls.S
@@ -290,3 +290,8 @@ SYSCALL(sys_add_key,sys_add_key,compat_sys_add_key_wrapper)
 SYSCALL(sys_request_key,sys_request_key,compat_sys_request_key_wrapper)
 SYSCALL(sys_keyctl,sys_keyctl,compat_sys_keyctl)		/* 280 */
 SYSCALL(sys_waitid,sys_waitid,compat_sys_waitid_wrapper)
+SYSCALL(sys_ioprio_set,sys_ioprio_set,sys_ioprio_set_wrapper)
+SYSCALL(sys_ioprio_get,sys_ioprio_get,sys_ioprio_get_wrapper)
+SYSCALL(sys_inotify_init,sys_inotify_init,sys_inotify_init)
+SYSCALL(sys_inotify_add_watch,sys_inotify_add_watch,sys_inotify_add_watch_wrapper)
+SYSCALL(sys_inotify_rm_watch,sys_inotify_rm_watch,sys_inotify_rm_watch_wrapper)
diff --git a/arch/s390/kernel/traps.c b/arch/s390/kernel/traps.c
index bc7b7be7acb..6b8703ec2ae 100644
--- a/arch/s390/kernel/traps.c
+++ b/arch/s390/kernel/traps.c
@@ -29,6 +29,7 @@
 #include <linux/delay.h>
 #include <linux/module.h>
 #include <linux/kallsyms.h>
+#include <linux/reboot.h>
 
 #include <asm/system.h>
 #include <asm/uaccess.h>
@@ -675,6 +676,19 @@ asmlinkage void kernel_stack_overflow(struct pt_regs * regs)
 	panic("Corrupt kernel stack, can't continue.");
 }
 
+#ifndef CONFIG_ARCH_S390X
+static int
+pagex_reboot_event(struct notifier_block *this, unsigned long event, void *ptr)
+{
+	if (MACHINE_IS_VM)
+		cpcmd("SET PAGEX OFF", NULL, 0, NULL);
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block pagex_reboot_notifier = {
+	.notifier_call = &pagex_reboot_event,
+};
+#endif
 
 /* init is done in lowcore.S and head.S */
 
@@ -735,6 +749,7 @@ void __init trap_init(void)
 						    &ext_int_pfault);
 #endif
 #ifndef CONFIG_ARCH_S390X
+		register_reboot_notifier(&pagex_reboot_notifier);
 		cpcmd("SET PAGEX ON", NULL, 0, NULL);
 #endif
 	}
diff --git a/arch/s390/lib/Makefile b/arch/s390/lib/Makefile
index a8758b1d20a..b701efa1f00 100644
--- a/arch/s390/lib/Makefile
+++ b/arch/s390/lib/Makefile
@@ -5,5 +5,5 @@
 EXTRA_AFLAGS := -traditional
 
 lib-y += delay.o string.o
-lib-$(CONFIG_ARCH_S390_31) += uaccess.o
-lib-$(CONFIG_ARCH_S390X) += uaccess64.o
+lib-$(CONFIG_ARCH_S390_31) += uaccess.o spinlock.o
+lib-$(CONFIG_ARCH_S390X) += uaccess64.o spinlock.o
diff --git a/arch/s390/lib/spinlock.c b/arch/s390/lib/spinlock.c
new file mode 100644
index 00000000000..888b5596c19
--- /dev/null
+++ b/arch/s390/lib/spinlock.c
@@ -0,0 +1,133 @@
+/*
+ *  arch/s390/lib/spinlock.c
+ *    Out of line spinlock code.
+ *
+ *  S390 version
+ *    Copyright (C) 2004 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
+ */
+
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/init.h>
+#include <asm/io.h>
+
+atomic_t spin_retry_counter;
+int spin_retry = 1000;
+
+/**
+ * spin_retry= parameter
+ */
+static int __init spin_retry_setup(char *str)
+{
+	spin_retry = simple_strtoul(str, &str, 0);
+	return 1;
+}
+__setup("spin_retry=", spin_retry_setup);
+
+static inline void
+_diag44(void)
+{
+#ifdef __s390x__
+	if (MACHINE_HAS_DIAG44)
+#endif
+		asm volatile("diag 0,0,0x44");
+}
+
+void
+_raw_spin_lock_wait(spinlock_t *lp, unsigned int pc)
+{
+	int count = spin_retry;
+
+	while (1) {
+		if (count-- <= 0) {
+			_diag44();
+			count = spin_retry;
+		}
+		atomic_inc(&spin_retry_counter);
+		if (_raw_compare_and_swap(&lp->lock, 0, pc) == 0)
+			return;
+	}
+}
+EXPORT_SYMBOL(_raw_spin_lock_wait);
+
+int
+_raw_spin_trylock_retry(spinlock_t *lp, unsigned int pc)
+{
+	int count = spin_retry;
+
+	while (count-- > 0) {
+		atomic_inc(&spin_retry_counter);
+		if (_raw_compare_and_swap(&lp->lock, 0, pc) == 0)
+			return 1;
+	}
+	return 0;
+}
+EXPORT_SYMBOL(_raw_spin_trylock_retry);
+
+void
+_raw_read_lock_wait(rwlock_t *rw)
+{
+	unsigned int old;
+	int count = spin_retry;
+
+	while (1) {
+		if (count-- <= 0) {
+			_diag44();
+			count = spin_retry;
+		}
+		atomic_inc(&spin_retry_counter);
+		old = rw->lock & 0x7fffffffU;
+		if (_raw_compare_and_swap(&rw->lock, old, old + 1) == old)
+			return;
+	}
+}
+EXPORT_SYMBOL(_raw_read_lock_wait);
+
+int
+_raw_read_trylock_retry(rwlock_t *rw)
+{
+	unsigned int old;
+	int count = spin_retry;
+
+	while (count-- > 0) {
+		atomic_inc(&spin_retry_counter);
+		old = rw->lock & 0x7fffffffU;
+		if (_raw_compare_and_swap(&rw->lock, old, old + 1) == old)
+			return 1;
+	}
+	return 0;
+}
+EXPORT_SYMBOL(_raw_read_trylock_retry);
+
+void
+_raw_write_lock_wait(rwlock_t *rw)
+{
+	int count = spin_retry;
+
+	while (1) {
+		if (count-- <= 0) {
+			_diag44();
+			count = spin_retry;
+		}
+		atomic_inc(&spin_retry_counter);
+		if (_raw_compare_and_swap(&rw->lock, 0, 0x80000000) == 0)
+			return;
+	}
+}
+EXPORT_SYMBOL(_raw_write_lock_wait);
+
+int
+_raw_write_trylock_retry(rwlock_t *rw)
+{
+	int count = spin_retry;
+
+	while (count-- > 0) {
+		atomic_inc(&spin_retry_counter);
+		if (_raw_compare_and_swap(&rw->lock, 0, 0x80000000) == 0)
+			return 1;
+	}
+	return 0;
+}
+EXPORT_SYMBOL(_raw_write_trylock_retry);
diff --git a/arch/sh/kernel/signal.c b/arch/sh/kernel/signal.c
index 06f1b47eded..8022243f017 100644
--- a/arch/sh/kernel/signal.c
+++ b/arch/sh/kernel/signal.c
@@ -579,7 +579,7 @@ int do_signal(struct pt_regs *regs, sigset_t *oldset)
 	if (!user_mode(regs))
 		return 1;
 
-	if (try_to_freeze(0))
+	if (try_to_freeze())
 		goto no_signal;
 
 	if (!oldset)
diff --git a/arch/sh64/kernel/signal.c b/arch/sh64/kernel/signal.c
index 45ad1026dde..c6a14a87c59 100644
--- a/arch/sh64/kernel/signal.c
+++ b/arch/sh64/kernel/signal.c
@@ -697,7 +697,7 @@ int do_signal(struct pt_regs *regs, sigset_t *oldset)
 	if (!user_mode(regs))
 		return 1;
 
-	if (try_to_freeze(0))
+	if (try_to_freeze())
 		goto no_signal;
 
 	if (!oldset)
diff --git a/arch/sh64/mm/fault.c b/arch/sh64/mm/fault.c
index a24932881db..f08d0eaf649 100644
--- a/arch/sh64/mm/fault.c
+++ b/arch/sh64/mm/fault.c
@@ -223,13 +223,13 @@ good_area:
 	 */
 survive:
 	switch (handle_mm_fault(mm, vma, address, writeaccess)) {
-	case 1:
+	case VM_FAULT_MINOR:
 		tsk->min_flt++;
 		break;
-	case 2:
+	case VM_FAULT_MAJOR:
 		tsk->maj_flt++;
 		break;
-	case 0:
+	case VM_FAULT_SIGBUS:
 		goto do_sigbus;
 	default:
 		goto out_of_memory;
diff --git a/arch/sparc/kernel/systbls.S b/arch/sparc/kernel/systbls.S
index 025f4516e65..e457a40838f 100644
--- a/arch/sparc/kernel/systbls.S
+++ b/arch/sparc/kernel/systbls.S
@@ -48,8 +48,8 @@ sys_call_table:
 /*135*/	.long sys_nis_syscall, sys_mkdir, sys_rmdir, sys_utimes, sys_stat64
 /*140*/	.long sys_sendfile64, sys_nis_syscall, sys_futex, sys_gettid, sys_getrlimit
 /*145*/	.long sys_setrlimit, sys_pivot_root, sys_prctl, sys_pciconfig_read, sys_pciconfig_write
-/*150*/	.long sys_nis_syscall, sys_nis_syscall, sys_nis_syscall, sys_poll, sys_getdents64
-/*155*/	.long sys_fcntl64, sys_ni_syscall, sys_statfs, sys_fstatfs, sys_oldumount
+/*150*/	.long sys_nis_syscall, sys_inotify_init, sys_inotify_add_watch, sys_poll, sys_getdents64
+/*155*/	.long sys_fcntl64, sys_inotify_rm_watch, sys_statfs, sys_fstatfs, sys_oldumount
 /*160*/	.long sys_sched_setaffinity, sys_sched_getaffinity, sys_getdomainname, sys_setdomainname, sys_nis_syscall
 /*165*/	.long sys_quotactl, sys_set_tid_address, sys_mount, sys_ustat, sys_setxattr
 /*170*/	.long sys_lsetxattr, sys_fsetxattr, sys_getxattr, sys_lgetxattr, sys_getdents
diff --git a/arch/sparc64/kernel/systbls.S b/arch/sparc64/kernel/systbls.S
index bceb91a8a2b..53eaf2345fe 100644
--- a/arch/sparc64/kernel/systbls.S
+++ b/arch/sparc64/kernel/systbls.S
@@ -50,8 +50,8 @@ sys_call_table32:
 	.word sys_nis_syscall, sys32_mkdir, sys_rmdir, sys32_utimes, compat_sys_stat64
 /*140*/	.word sys32_sendfile64, sys_nis_syscall, sys32_futex, sys_gettid, compat_sys_getrlimit
 	.word compat_sys_setrlimit, sys_pivot_root, sys32_prctl, sys_pciconfig_read, sys_pciconfig_write
-/*150*/	.word sys_nis_syscall, sys_nis_syscall, sys_nis_syscall, sys_poll, sys_getdents64
-	.word compat_sys_fcntl64, sys_ni_syscall, compat_sys_statfs, compat_sys_fstatfs, sys_oldumount
+/*150*/	.word sys_nis_syscall, sys_inotify_init, sys_inotify_add_watch, sys_poll, sys_getdents64
+	.word compat_sys_fcntl64, sys_inotify_rm_watch, compat_sys_statfs, compat_sys_fstatfs, sys_oldumount
 /*160*/	.word compat_sys_sched_setaffinity, compat_sys_sched_getaffinity, sys32_getdomainname, sys32_setdomainname, sys_nis_syscall
 	.word sys_quotactl, sys_set_tid_address, compat_sys_mount, sys_ustat, sys32_setxattr
 /*170*/	.word sys32_lsetxattr, sys32_fsetxattr, sys_getxattr, sys_lgetxattr, compat_sys_getdents
@@ -116,8 +116,8 @@ sys_call_table:
 	.word sys_socketpair, sys_mkdir, sys_rmdir, sys_utimes, sys_stat64
 /*140*/	.word sys_sendfile64, sys_getpeername, sys_futex, sys_gettid, sys_getrlimit
 	.word sys_setrlimit, sys_pivot_root, sys_prctl, sys_pciconfig_read, sys_pciconfig_write
-/*150*/	.word sys_getsockname, sys_nis_syscall, sys_nis_syscall, sys_poll, sys_getdents64
-	.word sys_nis_syscall, sys_ni_syscall, sys_statfs, sys_fstatfs, sys_oldumount
+/*150*/	.word sys_getsockname, sys_inotify_init, sys_inotify_add_watch, sys_poll, sys_getdents64
+	.word sys_nis_syscall, sys_inotify_rm_watch, sys_statfs, sys_fstatfs, sys_oldumount
 /*160*/	.word sys_sched_setaffinity, sys_sched_getaffinity, sys_getdomainname, sys_setdomainname, sys_utrap_install
 	.word sys_quotactl, sys_set_tid_address, sys_mount, sys_ustat, sys_setxattr
 /*170*/	.word sys_lsetxattr, sys_fsetxattr, sys_getxattr, sys_lgetxattr, sys_getdents
diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
index 8fc413cb6ac..3fbaf342a45 100644
--- a/arch/sparc64/mm/init.c
+++ b/arch/sparc64/mm/init.c
@@ -121,15 +121,24 @@ __inline__ void flush_dcache_page_impl(struct page *page)
 }
 
 #define PG_dcache_dirty		PG_arch_1
+#define PG_dcache_cpu_shift	24
+#define PG_dcache_cpu_mask	(256 - 1)
+
+#if NR_CPUS > 256
+#error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
+#endif
 
 #define dcache_dirty_cpu(page) \
-	(((page)->flags >> 24) & (NR_CPUS - 1UL))
+	(((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
 
 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
 {
 	unsigned long mask = this_cpu;
-	unsigned long non_cpu_bits = ~((NR_CPUS - 1UL) << 24UL);
-	mask = (mask << 24) | (1UL << PG_dcache_dirty);
+	unsigned long non_cpu_bits;
+
+	non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
+	mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
+
 	__asm__ __volatile__("1:\n\t"
 			     "ldx	[%2], %%g7\n\t"
 			     "and	%%g7, %1, %%g1\n\t"
@@ -151,7 +160,7 @@ static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long c
 	__asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 			     "1:\n\t"
 			     "ldx	[%2], %%g7\n\t"
-			     "srlx	%%g7, 24, %%g1\n\t"
+			     "srlx	%%g7, %4, %%g1\n\t"
 			     "and	%%g1, %3, %%g1\n\t"
 			     "cmp	%%g1, %0\n\t"
 			     "bne,pn	%%icc, 2f\n\t"
@@ -164,7 +173,8 @@ static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long c
 			     "2:"
 			     : /* no outputs */
 			     : "r" (cpu), "r" (mask), "r" (&page->flags),
-			       "i" (NR_CPUS - 1UL)
+			       "i" (PG_dcache_cpu_mask),
+			       "i" (PG_dcache_cpu_shift)
 			     : "g1", "g7");
 }
 
@@ -180,7 +190,8 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t p
 	if (pfn_valid(pfn) &&
 	    (page = pfn_to_page(pfn), page_mapping(page)) &&
 	    ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
-		int cpu = ((pg_flags >> 24) & (NR_CPUS - 1UL));
+		int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
+			   PG_dcache_cpu_mask);
 		int this_cpu = get_cpu();
 
 		/* This is just to optimize away some function calls
diff --git a/arch/um/Makefile b/arch/um/Makefile
index eb4ac403bd9..f5a83a72aa7 100644
--- a/arch/um/Makefile
+++ b/arch/um/Makefile
@@ -245,7 +245,7 @@ $(ARCH_DIR)/util: scripts_basic $(SYS_DIR)/sc.h $(ARCH_DIR)/kernel-offsets.h FOR
 $(ARCH_DIR)/kernel/skas/util: scripts_basic $(ARCH_DIR)/user-offsets.h FORCE
 	$(Q)$(MAKE) $(build)=$@
 
-$(ARCH_DIR)/os-$(OS)/util: scripts_basic FORCE
+$(ARCH_DIR)/os-$(OS)/util: scripts_basic $(ARCH_DIR)/user-offsets.h FORCE
 	$(Q)$(MAKE) $(build)=$@
 
 export SUBARCH USER_CFLAGS OS
diff --git a/arch/um/Makefile-i386 b/arch/um/Makefile-i386
index 93d0818fa81..a777e57dbf8 100644
--- a/arch/um/Makefile-i386
+++ b/arch/um/Makefile-i386
@@ -33,6 +33,7 @@ ifneq ($(CONFIG_GPROF),y)
 ARCH_CFLAGS += -DUM_FASTCALL
 endif
 
+SYS_UTIL_DIR	:= $(ARCH_DIR)/sys-i386/util
 SYS_HEADERS	:= $(SYS_DIR)/sc.h $(SYS_DIR)/thread.h
 
 prepare: $(SYS_HEADERS)
diff --git a/arch/um/drivers/Makefile b/arch/um/drivers/Makefile
index d6c31a95b88..de17d4c6e02 100644
--- a/arch/um/drivers/Makefile
+++ b/arch/um/drivers/Makefile
@@ -19,6 +19,8 @@ harddog-objs := harddog_kern.o harddog_user.o
 
 LDFLAGS_pcap.o := -r $(shell $(CC) $(CFLAGS) -print-file-name=libpcap.a)
 
+targets := pcap_kern.o pcap_user.o
+
 $(obj)/pcap.o: $(obj)/pcap_kern.o $(obj)/pcap_user.o
 	$(LD) -r -dp -o $@ $^ $(LDFLAGS) $(LDFLAGS_pcap.o)
 #XXX: The call below does not work because the flags are added before the
@@ -26,7 +28,7 @@ $(obj)/pcap.o: $(obj)/pcap_kern.o $(obj)/pcap_user.o
 #$(call if_changed,ld)
 
 # When the above is fixed, don't forget to add this too!
-#targets := $(obj)/pcap.o
+#targets += $(obj)/pcap.o
 
 obj-y := stdio_console.o fd.o chan_kern.o chan_user.o line.o
 obj-$(CONFIG_SSL) += ssl.o
diff --git a/arch/um/drivers/cow.h b/arch/um/drivers/cow.h
index 4fcbe8b1b77..4fcf3a8d13f 100644
--- a/arch/um/drivers/cow.h
+++ b/arch/um/drivers/cow.h
@@ -3,10 +3,10 @@
 
 #include <asm/types.h>
 
-#if __BYTE_ORDER == __BIG_ENDIAN
+#if defined(__BIG_ENDIAN)
 # define ntohll(x) (x)
 # define htonll(x) (x)
-#elif __BYTE_ORDER == __LITTLE_ENDIAN
+#elif defined(__LITTLE_ENDIAN)
 # define ntohll(x)  bswap_64(x)
 # define htonll(x)  bswap_64(x)
 #else
diff --git a/arch/um/drivers/hostaudio_kern.c b/arch/um/drivers/hostaudio_kern.c
index d5742783e19..59602b81b24 100644
--- a/arch/um/drivers/hostaudio_kern.c
+++ b/arch/um/drivers/hostaudio_kern.c
@@ -57,10 +57,10 @@ __uml_setup("mixer=", set_mixer, "mixer=<mixer device>\n" MIXER_HELP);
 
 #else /*MODULE*/
 
-MODULE_PARM(dsp, "s");
+module_param(dsp, charp, 0644);
 MODULE_PARM_DESC(dsp, DSP_HELP);
 
-MODULE_PARM(mixer, "s");
+module_param(mixer, charp, 0644);
 MODULE_PARM_DESC(mixer, MIXER_HELP);
 
 #endif
diff --git a/arch/um/drivers/mconsole_kern.c b/arch/um/drivers/mconsole_kern.c
index 404de41a4f6..c190c241419 100644
--- a/arch/um/drivers/mconsole_kern.c
+++ b/arch/um/drivers/mconsole_kern.c
@@ -557,7 +557,7 @@ static int create_proc_mconsole(void)
 
 	ent = create_proc_entry("mconsole", S_IFREG | 0200, NULL);
 	if(ent == NULL){
-		printk("create_proc_mconsole : create_proc_entry failed\n");
+		printk(KERN_INFO "create_proc_mconsole : create_proc_entry failed\n");
 		return(0);
 	}
 
diff --git a/arch/um/kernel/exitcode.c b/arch/um/kernel/exitcode.c
index 0ea87f24b36..d21ebad666b 100644
--- a/arch/um/kernel/exitcode.c
+++ b/arch/um/kernel/exitcode.c
@@ -48,7 +48,7 @@ static int make_proc_exitcode(void)
 
 	ent = create_proc_entry("exitcode", 0600, &proc_root);
 	if(ent == NULL){
-		printk("make_proc_exitcode : Failed to register "
+		printk(KERN_WARNING "make_proc_exitcode : Failed to register "
 		       "/proc/exitcode\n");
 		return(0);
 	}
diff --git a/arch/um/kernel/helper.c b/arch/um/kernel/helper.c
index 13b1f5c2f7e..f83e1e8e239 100644
--- a/arch/um/kernel/helper.c
+++ b/arch/um/kernel/helper.c
@@ -13,6 +13,7 @@
 #include "user.h"
 #include "kern_util.h"
 #include "user_util.h"
+#include "helper.h"
 #include "os.h"
 
 struct helper_data {
@@ -149,7 +150,7 @@ int run_helper_thread(int (*proc)(void *), void *arg, unsigned int flags,
 	return(pid);
 }
 
-int helper_wait(int pid, int block)
+int helper_wait(int pid)
 {
 	int ret;
 
@@ -160,14 +161,3 @@ int helper_wait(int pid, int block)
 	}
 	return(ret);
 }
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff --git a/arch/um/kernel/process.c b/arch/um/kernel/process.c
index c45a60e9c92..67acd92c532 100644
--- a/arch/um/kernel/process.c
+++ b/arch/um/kernel/process.c
@@ -131,7 +131,7 @@ int start_fork_tramp(void *thread_arg, unsigned long temp_stack,
 	return(arg.pid);
 }
 
-static int ptrace_child(void)
+static int ptrace_child(void *arg)
 {
 	int ret;
 	int pid = os_getpid(), ppid = getppid();
@@ -160,16 +160,20 @@ static int ptrace_child(void)
 	_exit(ret);
 }
 
-static int start_ptraced_child(void)
+static int start_ptraced_child(void **stack_out)
 {
+	void *stack;
+	unsigned long sp;
 	int pid, n, status;
 	
-	pid = fork();
-	if(pid == 0)
-		ptrace_child();
-
+	stack = mmap(NULL, PAGE_SIZE, PROT_READ | PROT_WRITE | PROT_EXEC,
+		     MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+	if(stack == MAP_FAILED)
+		panic("check_ptrace : mmap failed, errno = %d", errno);
+	sp = (unsigned long) stack + PAGE_SIZE - sizeof(void *);
+	pid = clone(ptrace_child, (void *) sp, SIGCHLD, NULL);
 	if(pid < 0)
-		panic("check_ptrace : fork failed, errno = %d", errno);
+		panic("check_ptrace : clone failed, errno = %d", errno);
 	CATCH_EINTR(n = waitpid(pid, &status, WUNTRACED));
 	if(n < 0)
 		panic("check_ptrace : wait failed, errno = %d", errno);
@@ -177,6 +181,7 @@ static int start_ptraced_child(void)
 		panic("check_ptrace : expected SIGSTOP, got status = %d",
 		      status);
 
+	*stack_out = stack;
 	return(pid);
 }
 
@@ -184,12 +189,12 @@ static int start_ptraced_child(void)
  * just avoid using sysemu, not panic, but only if SYSEMU features are broken.
  * So only for SYSEMU features we test mustpanic, while normal host features
  * must work anyway!*/
-static int stop_ptraced_child(int pid, int exitcode, int mustexit)
+static int stop_ptraced_child(int pid, void *stack, int exitcode, int mustpanic)
 {
 	int status, n, ret = 0;
 
 	if(ptrace(PTRACE_CONT, pid, 0, 0) < 0)
-		panic("stop_ptraced_child : ptrace failed, errno = %d", errno);
+		panic("check_ptrace : ptrace failed, errno = %d", errno);
 	CATCH_EINTR(n = waitpid(pid, &status, 0));
 	if(!WIFEXITED(status) || (WEXITSTATUS(status) != exitcode)) {
 		int exit_with = WEXITSTATUS(status);
@@ -200,24 +205,40 @@ static int stop_ptraced_child(int pid, int exitcode, int mustexit)
 		printk("check_ptrace : child exited with exitcode %d, while "
 		      "expecting %d; status 0x%x", exit_with,
 		      exitcode, status);
-		if (mustexit)
+		if (mustpanic)
 			panic("\n");
 		else
 			printk("\n");
 		ret = -1;
 	}
 
+	if(munmap(stack, PAGE_SIZE) < 0)
+		panic("check_ptrace : munmap failed, errno = %d", errno);
 	return ret;
 }
 
 static int force_sysemu_disabled = 0;
 
+int ptrace_faultinfo = 1;
+int proc_mm = 1;
+
+static int __init skas0_cmd_param(char *str, int* add)
+{
+	ptrace_faultinfo = proc_mm = 0;
+	return 0;
+}
+
 static int __init nosysemu_cmd_param(char *str, int* add)
 {
 	force_sysemu_disabled = 1;
 	return 0;
 }
 
+__uml_setup("skas0", skas0_cmd_param,
+		"skas0\n"
+		"    Disables SKAS3 usage, so that SKAS0 is used, unless you \n"
+		"    specify mode=tt.\n\n");
+
 __uml_setup("nosysemu", nosysemu_cmd_param,
 		"nosysemu\n"
 		"    Turns off syscall emulation patch for ptrace (SYSEMU) on.\n"
@@ -228,11 +249,12 @@ __uml_setup("nosysemu", nosysemu_cmd_param,
 
 static void __init check_sysemu(void)
 {
+	void *stack;
 	int pid, syscall, n, status, count=0;
 
 	printk("Checking syscall emulation patch for ptrace...");
 	sysemu_supported = 0;
-	pid = start_ptraced_child();
+	pid = start_ptraced_child(&stack);
 
 	if(ptrace(PTRACE_SYSEMU, pid, 0, 0) < 0)
 		goto fail;
@@ -250,7 +272,7 @@ static void __init check_sysemu(void)
 		panic("check_sysemu : failed to modify system "
 		      "call return, errno = %d", errno);
 
-	if (stop_ptraced_child(pid, 0, 0) < 0)
+	if (stop_ptraced_child(pid, stack, 0, 0) < 0)
 		goto fail_stopped;
 
 	sysemu_supported = 1;
@@ -258,7 +280,7 @@ static void __init check_sysemu(void)
 	set_using_sysemu(!force_sysemu_disabled);
 
 	printk("Checking advanced syscall emulation patch for ptrace...");
-	pid = start_ptraced_child();
+	pid = start_ptraced_child(&stack);
 	while(1){
 		count++;
 		if(ptrace(PTRACE_SYSEMU_SINGLESTEP, pid, 0, 0) < 0)
@@ -283,7 +305,7 @@ static void __init check_sysemu(void)
 			break;
 		}
 	}
-	if (stop_ptraced_child(pid, 0, 0) < 0)
+	if (stop_ptraced_child(pid, stack, 0, 0) < 0)
 		goto fail_stopped;
 
 	sysemu_supported = 2;
@@ -294,17 +316,18 @@ static void __init check_sysemu(void)
 	return;
 
 fail:
-	stop_ptraced_child(pid, 1, 0);
+	stop_ptraced_child(pid, stack, 1, 0);
 fail_stopped:
 	printk("missing\n");
 }
 
 void __init check_ptrace(void)
 {
+	void *stack;
 	int pid, syscall, n, status;
 
 	printk("Checking that ptrace can change system call numbers...");
-	pid = start_ptraced_child();
+	pid = start_ptraced_child(&stack);
 
 	if (ptrace(PTRACE_OLDSETOPTIONS, pid, 0, (void *)PTRACE_O_TRACESYSGOOD) < 0)
 		panic("check_ptrace: PTRACE_SETOPTIONS failed, errno = %d", errno);
@@ -331,7 +354,7 @@ void __init check_ptrace(void)
 			break;
 		}
 	}
-	stop_ptraced_child(pid, 0, 1);
+	stop_ptraced_child(pid, stack, 0, 1);
 	printk("OK\n");
 	check_sysemu();
 }
@@ -359,22 +382,22 @@ void forward_pending_sigio(int target)
 		kill(target, SIGIO);
 }
 
-int ptrace_faultinfo = 0;
-int proc_mm = 1;
-
 extern void *__syscall_stub_start, __syscall_stub_end;
 
 #ifdef UML_CONFIG_MODE_SKAS
+
 static inline void check_skas3_ptrace_support(void)
 {
 	struct ptrace_faultinfo fi;
+	void *stack;
 	int pid, n;
 
 	printf("Checking for the skas3 patch in the host...");
-	pid = start_ptraced_child();
+	pid = start_ptraced_child(&stack);
 
 	n = ptrace(PTRACE_FAULTINFO, pid, 0, &fi);
 	if (n < 0) {
+		ptrace_faultinfo = 0;
 		if(errno == EIO)
 			printf("not found\n");
 		else {
@@ -382,12 +405,14 @@ static inline void check_skas3_ptrace_support(void)
 		}
 	}
 	else {
-		ptrace_faultinfo = 1;
-		printf("found\n");
+		if (!ptrace_faultinfo)
+			printf("found but disabled on command line\n");
+		else
+			printf("found\n");
 	}
 
 	init_registers(pid);
-	stop_ptraced_child(pid, 1, 1);
+	stop_ptraced_child(pid, stack, 1, 1);
 }
 
 int can_do_skas(void)
@@ -396,13 +421,13 @@ int can_do_skas(void)
 	if (os_access("/proc/mm", OS_ACC_W_OK) < 0) {
 		proc_mm = 0;
 		printf("not found\n");
-		goto out;
-	}
-	else {
-		printf("found\n");
+	} else {
+		if (!proc_mm)
+			printf("found but disabled on command line\n");
+		else
+			printf("found\n");
 	}
 
-out:
 	check_skas3_ptrace_support();
 	return 1;
 }
diff --git a/arch/um/kernel/process_kern.c b/arch/um/kernel/process_kern.c
index d4036ed680b..c23d8a08d0f 100644
--- a/arch/um/kernel/process_kern.c
+++ b/arch/um/kernel/process_kern.c
@@ -412,7 +412,7 @@ int __init make_proc_sysemu(void)
 
 	if (ent == NULL)
 	{
-		printk("Failed to register /proc/sysemu\n");
+		printk(KERN_WARNING "Failed to register /proc/sysemu\n");
 		return(0);
 	}
 
diff --git a/arch/um/kernel/skas/process.c b/arch/um/kernel/skas/process.c
index ba671dab887..6dd9e5bf18e 100644
--- a/arch/um/kernel/skas/process.c
+++ b/arch/um/kernel/skas/process.c
@@ -64,7 +64,7 @@ void wait_stub_done(int pid, int sig, char * fname)
                 (WSTOPSIG(status) == SIGVTALRM));
 
         if((n < 0) || !WIFSTOPPED(status) ||
-           (WSTOPSIG(status) != SIGUSR1 && WSTOPSIG(status != SIGTRAP))){
+           (WSTOPSIG(status) != SIGUSR1 && WSTOPSIG(status) != SIGTRAP)){
                 panic("%s : failed to wait for SIGUSR1/SIGTRAP, "
                       "pid = %d, n = %d, errno = %d, status = 0x%x\n",
                       fname, pid, n, errno, status);
diff --git a/arch/um/kernel/skas/syscall_user.c b/arch/um/kernel/skas/syscall_user.c
index 2828e6e3772..6b066497014 100644
--- a/arch/um/kernel/skas/syscall_user.c
+++ b/arch/um/kernel/skas/syscall_user.c
@@ -15,7 +15,7 @@
 void handle_syscall(union uml_pt_regs *regs)
 {
 	long result;
-#if UML_CONFIG_SYSCALL_DEBUG
+#ifdef UML_CONFIG_SYSCALL_DEBUG
   	int index;
 
   	index = record_syscall_start(UPT_SYSCALL_NR(regs));
@@ -27,7 +27,7 @@ void handle_syscall(union uml_pt_regs *regs)
 	REGS_SET_SYSCALL_RETURN(regs->skas.regs, result);
 
 	syscall_trace(regs, 1);
-#if UML_CONFIG_SYSCALL_DEBUG
+#ifdef UML_CONFIG_SYSCALL_DEBUG
   	record_syscall_end(index, result);
 #endif
 }
diff --git a/arch/um/kernel/skas/trap_user.c b/arch/um/kernel/skas/trap_user.c
index 0dee1d95c80..9950a6716fe 100644
--- a/arch/um/kernel/skas/trap_user.c
+++ b/arch/um/kernel/skas/trap_user.c
@@ -58,7 +58,6 @@ void user_signal(int sig, union uml_pt_regs *regs, int pid)
         int segv = ((sig == SIGFPE) || (sig == SIGSEGV) || (sig == SIGBUS) ||
                     (sig == SIGILL) || (sig == SIGTRAP));
 
-	regs->skas.is_user = 1;
 	if (segv)
 		get_skas_faultinfo(pid, &regs->skas.faultinfo);
 	info = &sig_info[sig];
diff --git a/arch/um/kernel/time_kern.c b/arch/um/kernel/time_kern.c
index a8b4ef601f5..4e08f7545d6 100644
--- a/arch/um/kernel/time_kern.c
+++ b/arch/um/kernel/time_kern.c
@@ -137,7 +137,10 @@ long um_stime(int __user *tptr)
 void timer_handler(int sig, union uml_pt_regs *regs)
 {
 	local_irq_disable();
-	update_process_times(CHOOSE_MODE(user_context(UPT_SP(regs)), (regs)->skas.is_user));
+	irq_enter();
+	update_process_times(CHOOSE_MODE(user_context(UPT_SP(regs)),
+					 (regs)->skas.is_user));
+	irq_exit();
 	local_irq_enable();
 	if(current_thread->cpu == 0)
 		timer_irq(regs);
diff --git a/arch/um/kernel/um_arch.c b/arch/um/kernel/um_arch.c
index 8736d098f0e..ca2bb6f09a7 100644
--- a/arch/um/kernel/um_arch.c
+++ b/arch/um/kernel/um_arch.c
@@ -38,6 +38,9 @@
 #include "choose-mode.h"
 #include "mode_kern.h"
 #include "mode.h"
+#ifdef UML_CONFIG_MODE_SKAS
+#include "skas.h"
+#endif
 
 #define DEFAULT_COMMAND_LINE "root=98:0"
 
@@ -318,6 +321,7 @@ int linux_main(int argc, char **argv)
 	unsigned long avail, diff;
 	unsigned long virtmem_size, max_physmem;
 	unsigned int i, add;
+	char * mode;
 
 	for (i = 1; i < argc; i++){
 		if((i == 1) && (argv[i][0] == ' ')) continue;
@@ -338,6 +342,21 @@ int linux_main(int argc, char **argv)
 		exit(1);
 	}
 #endif
+
+#ifndef CONFIG_MODE_SKAS
+	mode = "TT";
+#else
+	/* Show to the user the result of selection */
+	if (mode_tt)
+		mode = "TT";
+	else if (proc_mm && ptrace_faultinfo)
+		mode = "SKAS3";
+	else
+		mode = "SKAS0";
+#endif
+
+	printf("UML running in %s mode\n", mode);
+
 	uml_start = CHOOSE_MODE_PROC(set_task_sizes_tt, set_task_sizes_skas, 0,
 				     &host_task_size, &task_size);
 
diff --git a/arch/um/os-Linux/elf_aux.c b/arch/um/os-Linux/elf_aux.c
index f0d6060e3e5..9416e1c2992 100644
--- a/arch/um/os-Linux/elf_aux.c
+++ b/arch/um/os-Linux/elf_aux.c
@@ -9,8 +9,10 @@
  */
 #include <elf.h>
 #include <stddef.h>
+#include <asm/elf.h>
 #include "init.h"
 #include "elf_user.h"
+#include "mem_user.h"
 
 #if ELF_CLASS == ELFCLASS32
 typedef Elf32_auxv_t elf_auxv_t;
@@ -40,6 +42,9 @@ __init void scan_elf_aux( char **envp)
 				break;
 			case AT_SYSINFO_EHDR:
 				vsyscall_ehdr = auxv->a_un.a_val;
+				/* See if the page is under TASK_SIZE */
+				if (vsyscall_ehdr < (unsigned long) envp)
+					vsyscall_ehdr = 0;
 				break;
 			case AT_HWCAP:
 				elf_aux_hwcap = auxv->a_un.a_val;
diff --git a/arch/um/os-Linux/user_syms.c b/arch/um/os-Linux/user_syms.c
index 75d7af9ae1d..56d3f870926 100644
--- a/arch/um/os-Linux/user_syms.c
+++ b/arch/um/os-Linux/user_syms.c
@@ -83,6 +83,9 @@ EXPORT_SYMBOL_PROTO(statfs64);
 
 EXPORT_SYMBOL_PROTO(getuid);
 
+EXPORT_SYMBOL_PROTO(fsync);
+EXPORT_SYMBOL_PROTO(fdatasync);
+
 /*
  * Overrides for Emacs so that we follow Linus's tabbing style.
  * Emacs will notice this stuff at the end of the file and automatically
diff --git a/arch/um/sys-i386/stub_segv.c b/arch/um/sys-i386/stub_segv.c
index b251442ad0b..68aeabe3a65 100644
--- a/arch/um/sys-i386/stub_segv.c
+++ b/arch/um/sys-i386/stub_segv.c
@@ -21,10 +21,10 @@ stub_segv_handler(int sig)
 	__asm__("movl %0, %%eax ; int $0x80": : "g" (__NR_getpid));
 	__asm__("movl %%eax, %%ebx ; movl %0, %%eax ; movl %1, %%ecx ;"
 		"int $0x80": : "g" (__NR_kill), "g" (SIGUSR1));
-	/* Pop the frame pointer and return address since we need to leave
+	/* Load pointer to sigcontext into esp, since we need to leave
 	 * the stack in its original form when we do the sigreturn here, by
 	 * hand.
 	 */
-	__asm__("popl %%eax ; popl %%eax ; popl %%eax ; movl %0, %%eax ; "
-		"int $0x80" : : "g" (__NR_sigreturn));
+	__asm__("mov %0,%%esp ; movl %1, %%eax ; "
+		"int $0x80" : : "a" (sc), "g" (__NR_sigreturn));
 }
diff --git a/arch/v850/Makefile b/arch/v850/Makefile
index 6edaed4a310..bf38ca0ad78 100644
--- a/arch/v850/Makefile
+++ b/arch/v850/Makefile
@@ -1,8 +1,8 @@
 #
 # arch/v850/Makefile
 #
-#  Copyright (C) 2001,02,03  NEC Corporation
-#  Copyright (C) 2001,02,03  Miles Bader <miles@gnu.org>
+#  Copyright (C) 2001,02,03,05  NEC Corporation
+#  Copyright (C) 2001,02,03,05  Miles Bader <miles@gnu.org>
 #
 # This file is included by the global makefile so that you can add your own
 # architecture-specific flags and dependencies. Remember to do have actions
@@ -22,6 +22,9 @@ CFLAGS += -ffixed-r16 -mno-prolog-function
 CFLAGS += -fno-builtin
 CFLAGS += -D__linux__ -DUTS_SYSNAME=\"uClinux\"
 
+# By default, build a kernel that runs on the gdb v850 simulator.
+KBUILD_DEFCONFIG := sim_defconfig
+
 # This prevents the linker from consolidating the .gnu.linkonce.this_module
 # section into .text (which the v850 default linker script for -r does for
 # some reason)
diff --git a/arch/v850/README b/arch/v850/README
index 01b98e290d4..12f7f7a665e 100644
--- a/arch/v850/README
+++ b/arch/v850/README
@@ -1,31 +1,43 @@
 This port to the NEC V850E processor supports the following platforms:
 
-   + The gdb v850e simulator (CONFIG_V850E_SIM).
-
-   + The Midas labs RTE-V850E/MA1-CB and RTE-V850E/NB85E-CB evaluation boards
-     (CONFIG_RTE_CB_MA1 and CONFIG_RTE_CB_NB85E).  This support has only been
-     tested when running with the Multi-debugger monitor ROM (for the Green
-     Hills Multi debugger).  The optional NEC Solution Gear RTE-MOTHER-A
-     motherboard is also supported, which allows PCI boards to be used
-     (CONFIG_RTE_MB_A_PCI).
-
-   + The Midas labs RTE-V850E/ME2-CB evaluation board (CONFIG_RTE_CB_ME2).
-     This has only been tested using a kernel downloaded via an ICE connection
-     using the Multi debugger.  Support for the RTE-MOTHER-A is present, but
-     hasn't been tested (unlike the other Midas labs cpu boards, the
-     RTE-V850E/ME2-CB includes an ethernet adaptor).
-
-   + The NEC AS85EP1 V850E evaluation chip/board (CONFIG_V850E_AS85EP1).
-
-   + The NEC `Anna' (board/chip) implementation of the V850E2 processor
-     (CONFIG_V850E2_ANNA).
-
-   + The sim85e2c and sim85e2s simulators, which are verilog simulations of
-     the V850E2 NA85E2C/NA85E2S cpu cores (CONFIG_V850E2_SIM85E2C and
-     CONFIG_V850E2_SIM85E2S).
-
-   + A FPGA implementation of the V850E2 NA85E2C cpu core
-     (CONFIG_V850E2_FPGA85E2C).
+   "sim"
+	The gdb v850e simulator (CONFIG_V850E_SIM).
+
+   "rte-ma1-cb"
+	The Midas labs RTE-V850E/MA1-CB and RTE-V850E/NB85E-CB evaluation
+	boards (CONFIG_RTE_CB_MA1 and CONFIG_RTE_CB_NB85E).  This support
+	has only been tested when running with the Multi-debugger monitor
+	ROM (for the Green Hills Multi debugger).  The optional NEC
+	Solution Gear RTE-MOTHER-A motherboard is also supported, which
+	allows PCI boards to be used (CONFIG_RTE_MB_A_PCI).
+
+   "rte-me2-cb"
+	The Midas labs RTE-V850E/ME2-CB evaluation board (CONFIG_RTE_CB_ME2).
+     	This has only been tested using a kernel downloaded via an ICE
+     	connection using the Multi debugger.  Support for the RTE-MOTHER-A is
+     	present, but hasn't been tested (unlike the other Midas labs cpu
+     	boards, the RTE-V850E/ME2-CB includes an ethernet adaptor).
+
+   "as85ep1"
+	The NEC AS85EP1 V850E evaluation chip/board (CONFIG_V850E_AS85EP1).
+
+   "anna"
+	The NEC `Anna' (board/chip) implementation of the V850E2 processor
+	(CONFIG_V850E2_ANNA).
+
+   "sim85e2c", "sim85e2s"
+   	The sim85e2c and sim85e2s simulators, which are verilog simulations
+	of the V850E2 NA85E2C/NA85E2S cpu cores (CONFIG_V850E2_SIM85E2C and
+	CONFIG_V850E2_SIM85E2S).
+
+   "fpga85e2c"
+	A FPGA implementation of the V850E2 NA85E2C cpu core
+	(CONFIG_V850E2_FPGA85E2C).
+
+To get a default kernel configuration for a particular platform, you can
+use a <platform>_defconfig make target (e.g., "make rte-me2-cb_defconfig");
+to see which default configurations are possible, look in the directory
+"arch/v850/configs".
 
 Porting to anything with a V850E/MA1 or MA2 processor should be simple.
 See the file <asm-v850/machdep.h> and the files it includes for an example of
diff --git a/arch/v850/configs/rte-ma1-cb_defconfig b/arch/v850/configs/rte-ma1-cb_defconfig
new file mode 100644
index 00000000000..1b5ca3c3a65
--- /dev/null
+++ b/arch/v850/configs/rte-ma1-cb_defconfig
@@ -0,0 +1,605 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.12-uc0
+# Thu Jul 21 11:08:27 2005
+#
+# CONFIG_MMU is not set
+# CONFIG_UID16 is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+# CONFIG_ISA is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+CONFIG_V850=y
+
+#
+# Processor type and features
+#
+# CONFIG_V850E_SIM is not set
+CONFIG_RTE_CB_MA1=y
+# CONFIG_RTE_CB_NB85E is not set
+# CONFIG_RTE_CB_ME2 is not set
+# CONFIG_V850E_AS85EP1 is not set
+# CONFIG_V850E2_SIM85E2C is not set
+# CONFIG_V850E2_SIM85E2S is not set
+# CONFIG_V850E2_FPGA85E2C is not set
+# CONFIG_V850E2_ANNA is not set
+CONFIG_V850E=y
+CONFIG_V850E_MA1=y
+CONFIG_RTE_CB=y
+CONFIG_RTE_CB_MULTI=y
+CONFIG_RTE_CB_MULTI_DBTRAP=y
+# CONFIG_RTE_CB_MA1_KSRAM is not set
+CONFIG_RTE_MB_A_PCI=y
+CONFIG_RTE_GBUS_INT=y
+CONFIG_PCI=y
+CONFIG_V850E_INTC=y
+CONFIG_V850E_TIMER_D=y
+# CONFIG_V850E_CACHE is not set
+# CONFIG_V850E2_CACHE is not set
+CONFIG_NO_CACHE=y
+CONFIG_ZERO_BSS=y
+# CONFIG_V850E_HIGHRES_TIMER is not set
+# CONFIG_RESET_GUARD is not set
+CONFIG_LARGE_ALLOCS=y
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+# CONFIG_AUDIT is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_KOBJECT_UEVENT=y
+# CONFIG_IKCONFIG is not set
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_BASE_FULL is not set
+# CONFIG_FUTEX is not set
+# CONFIG_EPOLL is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_BASE_SMALL=1
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
+#
+# CONFIG_PCI_LEGACY_PROC is not set
+# CONFIG_PCI_NAMES is not set
+# CONFIG_PCI_DEBUG is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PCI Hotplug Support
+#
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_FLAT=y
+# CONFIG_BINFMT_ZFLAT is not set
+# CONFIG_BINFMT_SHARED_FLAT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_PARTITIONS is not set
+
+#
+# User Modules And Translation Layers
+#
+# CONFIG_MTD_CHAR is not set
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+CONFIG_MTD_SLRAM=y
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_RAM is not set
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CDROM_PKTCDVD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# Disk device support
+#
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_UNIX is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_IP_TCPDIAG is not set
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_NE2000 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_DGRS is not set
+CONFIG_EEPRO100=y
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_V850E_UART=y
+CONFIG_V850E_UART_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_UNIX98_PTYS is not set
+# CONFIG_LEGACY_PTYS is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+
+#
+# XFS support
+#
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_SUNRPC=y
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB is not set
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_FS is not set
+# CONFIG_NO_KERNEL_MSG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC32 is not set
+# CONFIG_LIBCRC32C is not set
diff --git a/arch/v850/configs/rte-me2-cb_defconfig b/arch/v850/configs/rte-me2-cb_defconfig
new file mode 100644
index 00000000000..44becc06540
--- /dev/null
+++ b/arch/v850/configs/rte-me2-cb_defconfig
@@ -0,0 +1,453 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.12-uc0
+# Thu Jul 21 11:30:08 2005
+#
+# CONFIG_MMU is not set
+# CONFIG_UID16 is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+# CONFIG_ISA is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+CONFIG_V850=y
+
+#
+# Processor type and features
+#
+# CONFIG_V850E_SIM is not set
+# CONFIG_RTE_CB_MA1 is not set
+# CONFIG_RTE_CB_NB85E is not set
+CONFIG_RTE_CB_ME2=y
+# CONFIG_V850E_AS85EP1 is not set
+# CONFIG_V850E2_SIM85E2C is not set
+# CONFIG_V850E2_SIM85E2S is not set
+# CONFIG_V850E2_FPGA85E2C is not set
+# CONFIG_V850E2_ANNA is not set
+CONFIG_V850E=y
+CONFIG_V850E_ME2=y
+CONFIG_RTE_CB=y
+# CONFIG_RTE_MB_A_PCI is not set
+# CONFIG_PCI is not set
+CONFIG_V850E_INTC=y
+CONFIG_V850E_TIMER_D=y
+CONFIG_V850E_CACHE=y
+# CONFIG_V850E2_CACHE is not set
+# CONFIG_NO_CACHE is not set
+# CONFIG_ROM_KERNEL is not set
+CONFIG_ZERO_BSS=y
+# CONFIG_V850E_HIGHRES_TIMER is not set
+# CONFIG_RESET_GUARD is not set
+CONFIG_LARGE_ALLOCS=y
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+# CONFIG_AUDIT is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_BASE_FULL is not set
+# CONFIG_FUTEX is not set
+# CONFIG_EPOLL is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_BASE_SMALL=1
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
+#
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PCI Hotplug Support
+#
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_FLAT=y
+# CONFIG_BINFMT_ZFLAT is not set
+# CONFIG_BINFMT_SHARED_FLAT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_PARTITIONS is not set
+
+#
+# User Modules And Translation Layers
+#
+# CONFIG_MTD_CHAR is not set
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_SLRAM=y
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_RAM is not set
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CDROM_PKTCDVD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+
+#
+# Disk device support
+#
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# Networking support
+#
+# CONFIG_NET is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_V850E_UART is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_UNIX98_PTYS is not set
+# CONFIG_LEGACY_PTYS is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+
+#
+# XFS support
+#
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB_ARCH_HAS_HCD is not set
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_FS is not set
+# CONFIG_NO_KERNEL_MSG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC32 is not set
+# CONFIG_LIBCRC32C is not set
diff --git a/arch/v850/configs/sim_defconfig b/arch/v850/configs/sim_defconfig
new file mode 100644
index 00000000000..d73f5f9d838
--- /dev/null
+++ b/arch/v850/configs/sim_defconfig
@@ -0,0 +1,442 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.12-uc0
+# Thu Jul 21 11:29:27 2005
+#
+# CONFIG_MMU is not set
+# CONFIG_UID16 is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+# CONFIG_ISA is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+CONFIG_V850=y
+
+#
+# Processor type and features
+#
+CONFIG_V850E_SIM=y
+# CONFIG_RTE_CB_MA1 is not set
+# CONFIG_RTE_CB_NB85E is not set
+# CONFIG_RTE_CB_ME2 is not set
+# CONFIG_V850E_AS85EP1 is not set
+# CONFIG_V850E2_SIM85E2C is not set
+# CONFIG_V850E2_SIM85E2S is not set
+# CONFIG_V850E2_FPGA85E2C is not set
+# CONFIG_V850E2_ANNA is not set
+CONFIG_V850E=y
+# CONFIG_PCI is not set
+# CONFIG_V850E_INTC is not set
+# CONFIG_V850E_TIMER_D is not set
+# CONFIG_V850E_CACHE is not set
+# CONFIG_V850E2_CACHE is not set
+CONFIG_NO_CACHE=y
+CONFIG_ZERO_BSS=y
+# CONFIG_RESET_GUARD is not set
+CONFIG_LARGE_ALLOCS=y
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+# CONFIG_AUDIT is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_BASE_FULL is not set
+# CONFIG_FUTEX is not set
+# CONFIG_EPOLL is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_BASE_SMALL=1
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
+#
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PCI Hotplug Support
+#
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_FLAT=y
+# CONFIG_BINFMT_ZFLAT is not set
+# CONFIG_BINFMT_SHARED_FLAT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+# CONFIG_MTD_PARTITIONS is not set
+
+#
+# User Modules And Translation Layers
+#
+# CONFIG_MTD_CHAR is not set
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_SLRAM=y
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+
+#
+# NAND Flash Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_RAM is not set
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CDROM_PKTCDVD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+
+#
+# Disk device support
+#
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# I2O device support
+#
+
+#
+# Networking support
+#
+# CONFIG_NET is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_UNIX98_PTYS is not set
+# CONFIG_LEGACY_PTYS is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+
+#
+# XFS support
+#
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB_ARCH_HAS_HCD is not set
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_FS is not set
+# CONFIG_NO_KERNEL_MSG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC32 is not set
+# CONFIG_LIBCRC32C is not set
diff --git a/arch/v850/kernel/rte_mb_a_pci.c b/arch/v850/kernel/rte_mb_a_pci.c
index 074b50abc89..ffbb6d073bf 100644
--- a/arch/v850/kernel/rte_mb_a_pci.c
+++ b/arch/v850/kernel/rte_mb_a_pci.c
@@ -1,8 +1,8 @@
 /*
  * arch/v850/kernel/mb_a_pci.c -- PCI support for Midas lab RTE-MOTHER-A board
  *
- *  Copyright (C) 2001,02,03  NEC Electronics Corporation
- *  Copyright (C) 2001,02,03  Miles Bader <miles@gnu.org>
+ *  Copyright (C) 2001,02,03,05  NEC Electronics Corporation
+ *  Copyright (C) 2001,02,03,05  Miles Bader <miles@gnu.org>
  *
  * This file is subject to the terms and conditions of the GNU General
  * Public License.  See the file COPYING in the main directory of this
@@ -743,15 +743,17 @@ pci_unmap_sg (struct pci_dev *pdev, struct scatterlist *sg, int sg_len,int dir)
    for a scatter-gather list, same rules and usage.  */
 
 void
-pci_dma_sync_sg_for_cpu (struct pci_dev *dev, struct scatterlist *sg, int sg_len,
-		 int dir)
+pci_dma_sync_sg_for_cpu (struct pci_dev *dev,
+			 struct scatterlist *sg, int sg_len,
+			 int dir)
 {
 	BUG ();
 }
 
 void
-pci_dma_sync_sg_for_device (struct pci_dev *dev, struct scatterlist *sg, int sg_len,
-		 int dir)
+pci_dma_sync_sg_for_device (struct pci_dev *dev,
+			    struct scatterlist *sg, int sg_len,
+			    int dir)
 {
 	BUG ();
 }
@@ -786,6 +788,27 @@ pci_free_consistent (struct pci_dev *pdev, size_t size, void *cpu_addr,
 }
 
 
+/* iomap/iomap */
+
+void __iomem *pci_iomap (struct pci_dev *dev, int bar, unsigned long max)
+{
+	unsigned long start = pci_resource_start (dev, bar);
+	unsigned long len = pci_resource_len (dev, bar);
+
+	if (!start || len == 0)
+		return 0;
+
+	/* None of the ioremap functions actually do anything, other than
+	   re-casting their argument, so don't bother differentiating them.  */
+	return ioremap (start, len);
+}
+
+void pci_iounmap (struct pci_dev *dev, void __iomem *addr)
+{
+	/* nothing */
+}
+
+
 /* symbol exports (for modules) */
 
 EXPORT_SYMBOL (pci_map_single);
@@ -794,3 +817,5 @@ EXPORT_SYMBOL (pci_alloc_consistent);
 EXPORT_SYMBOL (pci_free_consistent);
 EXPORT_SYMBOL (pci_dma_sync_single_for_cpu);
 EXPORT_SYMBOL (pci_dma_sync_single_for_device);
+EXPORT_SYMBOL (pci_iomap);
+EXPORT_SYMBOL (pci_iounmap);
diff --git a/arch/v850/kernel/vmlinux.lds.S b/arch/v850/kernel/vmlinux.lds.S
index c366a8b326e..5be05f47109 100644
--- a/arch/v850/kernel/vmlinux.lds.S
+++ b/arch/v850/kernel/vmlinux.lds.S
@@ -12,6 +12,7 @@
  */
 
 #include <linux/config.h>
+
 #define VMLINUX_SYMBOL(_sym_) _##_sym_
 #include <asm-generic/vmlinux.lds.h>
 
@@ -42,6 +43,19 @@
 			*(.rodata) *(.rodata.*)				      \
 			*(__vermagic)		/* Kernel version magic */    \
 			*(.rodata1)					      \
+		/* PCI quirks */					      \
+		___start_pci_fixups_early = . ;				      \
+			*(.pci_fixup_early)				      \
+		___end_pci_fixups_early = . ;				      \
+		___start_pci_fixups_header = . ;			      \
+			*(.pci_fixup_header)				      \
+		___end_pci_fixups_header = . ;				      \
+		___start_pci_fixups_final = . ;				      \
+			*(.pci_fixup_final)				      \
+		___end_pci_fixups_final = . ;				      \
+		___start_pci_fixups_enable = . ;			      \
+			*(.pci_fixup_enable)				      \
+		___end_pci_fixups_enable = . ;				      \
 		/* Kernel symbol table: Normal symbols */		      \
 		___start___ksymtab = .;					      \
 			*(__ksymtab)					      \
diff --git a/arch/x86_64/Kconfig b/arch/x86_64/Kconfig
index 4b8326177c5..660a03a89e6 100644
--- a/arch/x86_64/Kconfig
+++ b/arch/x86_64/Kconfig
@@ -329,12 +329,15 @@ config HPET_EMULATE_RTC
 
 config GART_IOMMU
 	bool "IOMMU support"
+	default y
 	depends on PCI
 	help
-	  Support the K8 IOMMU. Needed to run systems with more than 4GB of memory
+	  Support the IOMMU. Needed to run systems with more than 3GB of memory
 	  properly with 32-bit PCI devices that do not support DAC (Double Address
 	  Cycle). The IOMMU can be turned off at runtime with the iommu=off parameter.
 	  Normally the kernel will take the right choice by itself.
+	  This option includes a driver for the AMD Opteron/Athlon64 IOMMU
+	  and a software emulation used on some other systems.
 	  If unsure, say Y.
 
 # need this always enabled with GART_IOMMU for the VIA workaround
diff --git a/arch/x86_64/Makefile b/arch/x86_64/Makefile
index 42891569767..4c6ed96d5f7 100644
--- a/arch/x86_64/Makefile
+++ b/arch/x86_64/Makefile
@@ -21,18 +21,6 @@
 #
 # $Id: Makefile,v 1.31 2002/03/22 15:56:07 ak Exp $
 
-#
-# early bootup linking needs 32bit. You can either use real 32bit tools
-# here or 64bit tools in 32bit mode.
-#
-IA32_CC := $(CC) $(CPPFLAGS) -m32 -O2 -fomit-frame-pointer
-IA32_LD := $(LD) -m elf_i386
-IA32_AS := $(CC) $(AFLAGS) -m32 -Wa,--32 -traditional -c
-IA32_OBJCOPY := $(CROSS_COMPILE)objcopy
-IA32_CPP := $(CROSS_COMPILE)gcc -m32 -E
-export IA32_CC IA32_LD IA32_AS IA32_OBJCOPY IA32_CPP
-
-
 LDFLAGS		:= -m elf_x86_64
 OBJCOPYFLAGS	:= -O binary -R .note -R .comment -S
 LDFLAGS_vmlinux :=
diff --git a/arch/x86_64/crypto/aes.c b/arch/x86_64/crypto/aes.c
index 2b5c4010ce3..acfdaa28791 100644
--- a/arch/x86_64/crypto/aes.c
+++ b/arch/x86_64/crypto/aes.c
@@ -322,3 +322,4 @@ module_exit(aes_fini);
 
 MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm");
 MODULE_LICENSE("GPL");
+MODULE_ALIAS("aes");
diff --git a/arch/x86_64/defconfig b/arch/x86_64/defconfig
index 569595b74c7..776f3c866b7 100644
--- a/arch/x86_64/defconfig
+++ b/arch/x86_64/defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc4
-# Fri May 13 06:39:11 2005
+# Linux kernel version: 2.6.13-rc3
+# Fri Jul 22 16:47:31 2005
 #
 CONFIG_X86_64=y
 CONFIG_64BIT=y
@@ -84,14 +84,27 @@ CONFIG_X86_IO_APIC=y
 CONFIG_X86_LOCAL_APIC=y
 CONFIG_MTRR=y
 CONFIG_SMP=y
-# CONFIG_PREEMPT is not set
 CONFIG_SCHED_SMT=y
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_PREEMPT_BKL=y
 CONFIG_K8_NUMA=y
 # CONFIG_NUMA_EMU is not set
-CONFIG_DISCONTIGMEM=y
+CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
 CONFIG_NUMA=y
+CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM_MANUAL=y
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_DISCONTIGMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_NEED_MULTIPLE_NODES=y
+CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y
 CONFIG_HAVE_DEC_LOCK=y
-CONFIG_NR_CPUS=8
+CONFIG_NR_CPUS=32
 CONFIG_HPET_TIMER=y
 CONFIG_X86_PM_TIMER=y
 CONFIG_HPET_EMULATE_RTC=y
@@ -99,7 +112,13 @@ CONFIG_GART_IOMMU=y
 CONFIG_SWIOTLB=y
 CONFIG_X86_MCE=y
 CONFIG_X86_MCE_INTEL=y
+CONFIG_PHYSICAL_START=0x100000
+# CONFIG_KEXEC is not set
 CONFIG_SECCOMP=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_ISA_DMA_API=y
@@ -118,12 +137,11 @@ CONFIG_PM_STD_PARTITION=""
 CONFIG_ACPI=y
 CONFIG_ACPI_BOOT=y
 CONFIG_ACPI_INTERPRETER=y
-CONFIG_ACPI_SLEEP=y
-CONFIG_ACPI_SLEEP_PROC_FS=y
 CONFIG_ACPI_AC=y
 CONFIG_ACPI_BATTERY=y
 CONFIG_ACPI_BUTTON=y
 # CONFIG_ACPI_VIDEO is not set
+CONFIG_ACPI_HOTKEY=m
 CONFIG_ACPI_FAN=y
 CONFIG_ACPI_PROCESSOR=y
 CONFIG_ACPI_THERMAL=y
@@ -154,6 +172,7 @@ CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
 # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
 CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
 
 #
 # CPUFreq processor drivers
@@ -204,6 +223,76 @@ CONFIG_SYSVIPC_COMPAT=y
 CONFIG_UID16=y
 
 #
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_IP_TCPDIAG=y
+CONFIG_IP_TCPDIAG_IPV6=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+CONFIG_IPV6=y
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_NETFILTER is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_RX is not set
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+
+#
 # Device Drivers
 #
 
@@ -308,6 +397,7 @@ CONFIG_BLK_DEV_AMD74XX=y
 # CONFIG_BLK_DEV_HPT366 is not set
 # CONFIG_BLK_DEV_SC1200 is not set
 CONFIG_BLK_DEV_PIIX=y
+# CONFIG_BLK_DEV_IT821X is not set
 # CONFIG_BLK_DEV_NS87415 is not set
 # CONFIG_BLK_DEV_PDC202XX_OLD is not set
 CONFIG_BLK_DEV_PDC202XX_NEW=y
@@ -338,6 +428,7 @@ CONFIG_BLK_DEV_SD=y
 # CONFIG_CHR_DEV_OSST is not set
 # CONFIG_BLK_DEV_SR is not set
 # CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
 
 #
 # Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -372,7 +463,6 @@ CONFIG_AIC79XX_DEBUG_MASK=0
 # CONFIG_MEGARAID_NEWGEN is not set
 # CONFIG_MEGARAID_LEGACY is not set
 CONFIG_SCSI_SATA=y
-# CONFIG_SCSI_SATA_AHCI is not set
 # CONFIG_SCSI_SATA_SVW is not set
 CONFIG_SCSI_ATA_PIIX=y
 # CONFIG_SCSI_SATA_NV is not set
@@ -410,14 +500,21 @@ CONFIG_SCSI_QLA2XXX=y
 #
 # Multi-device support (RAID and LVM)
 #
-# CONFIG_MD is not set
+CONFIG_MD=y
+# CONFIG_BLK_DEV_MD is not set
+CONFIG_BLK_DEV_DM=y
+# CONFIG_DM_CRYPT is not set
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
 
 #
 # Fusion MPT device support
 #
-CONFIG_FUSION=y
-CONFIG_FUSION_MAX_SGE=40
-# CONFIG_FUSION_CTL is not set
+# CONFIG_FUSION is not set
+# CONFIG_FUSION_SPI is not set
+# CONFIG_FUSION_FC is not set
 
 #
 # IEEE 1394 (FireWire) support
@@ -430,75 +527,8 @@ CONFIG_FUSION_MAX_SGE=40
 # CONFIG_I2O is not set
 
 #
-# Networking support
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_IP_TCPDIAG=y
-CONFIG_IP_TCPDIAG_IPV6=y
-CONFIG_IPV6=y
-# CONFIG_IPV6_PRIVACY is not set
-# CONFIG_INET6_AH is not set
-# CONFIG_INET6_ESP is not set
-# CONFIG_INET6_IPCOMP is not set
-# CONFIG_INET6_TUNNEL is not set
-# CONFIG_IPV6_TUNNEL is not set
-# CONFIG_NETFILTER is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
+# Network device support
 #
-# CONFIG_IP_SCTP is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-# CONFIG_NET_CLS_ROUTE is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-CONFIG_NETPOLL=y
-# CONFIG_NETPOLL_RX is not set
-# CONFIG_NETPOLL_TRAP is not set
-CONFIG_NET_POLL_CONTROLLER=y
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
@@ -517,7 +547,9 @@ CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 # CONFIG_HAPPYMEAL is not set
 # CONFIG_SUNGEM is not set
-# CONFIG_NET_VENDOR_3COM is not set
+CONFIG_NET_VENDOR_3COM=y
+CONFIG_VORTEX=y
+# CONFIG_TYPHOON is not set
 
 #
 # Tulip family network device support
@@ -532,7 +564,7 @@ CONFIG_NET_PCI=y
 CONFIG_FORCEDETH=y
 # CONFIG_DGRS is not set
 # CONFIG_EEPRO100 is not set
-# CONFIG_E100 is not set
+CONFIG_E100=y
 # CONFIG_FEALNX is not set
 # CONFIG_NATSEMI is not set
 # CONFIG_NE2K_PCI is not set
@@ -553,14 +585,15 @@ CONFIG_8139TOO=y
 # CONFIG_ACENIC is not set
 # CONFIG_DL2K is not set
 CONFIG_E1000=y
-# CONFIG_E1000_NAPI is not set
 # CONFIG_NS83820 is not set
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 # CONFIG_R8169 is not set
+# CONFIG_SKGE is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_VIA_VELOCITY is not set
 CONFIG_TIGON3=y
+# CONFIG_BNX2 is not set
 
 #
 # Ethernet (10000 Mbit)
@@ -647,7 +680,6 @@ CONFIG_SERIO_I8042=y
 CONFIG_SERIO_LIBPS2=y
 # CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
 
 #
 # Character devices
@@ -716,6 +748,7 @@ CONFIG_MAX_RAW_DEVS=256
 # I2C support
 #
 # CONFIG_I2C is not set
+# CONFIG_I2C_SENSOR is not set
 
 #
 # Dallas's 1-wire bus
@@ -723,6 +756,12 @@ CONFIG_MAX_RAW_DEVS=256
 # CONFIG_W1 is not set
 
 #
+# Hardware Monitoring support
+#
+CONFIG_HWMON=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
 # Misc devices
 #
 # CONFIG_IBM_ASM is not set
@@ -808,6 +847,7 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_EHCI_HCD=y
 # CONFIG_USB_EHCI_SPLIT_ISO is not set
 # CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+# CONFIG_USB_ISP116X_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
@@ -846,12 +886,15 @@ CONFIG_USB_HIDINPUT=y
 # CONFIG_USB_HIDDEV is not set
 # CONFIG_USB_AIPTEK is not set
 # CONFIG_USB_WACOM is not set
+# CONFIG_USB_ACECAD is not set
 # CONFIG_USB_KBTAB is not set
 # CONFIG_USB_POWERMATE is not set
 # CONFIG_USB_MTOUCH is not set
+# CONFIG_USB_ITMTOUCH is not set
 # CONFIG_USB_EGALAX is not set
 # CONFIG_USB_XPAD is not set
 # CONFIG_USB_ATI_REMOTE is not set
+# CONFIG_USB_KEYSPAN_REMOTE is not set
 
 #
 # USB Imaging devices
@@ -902,10 +945,11 @@ CONFIG_USB_MON=y
 # CONFIG_USB_PHIDGETSERVO is not set
 # CONFIG_USB_IDMOUSE is not set
 # CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
 # CONFIG_USB_TEST is not set
 
 #
-# USB ATM/DSL drivers
+# USB DSL modem support
 #
 
 #
@@ -924,6 +968,10 @@ CONFIG_USB_MON=y
 # CONFIG_INFINIBAND is not set
 
 #
+# SN Devices
+#
+
+#
 # Firmware Drivers
 #
 # CONFIG_EDD is not set
@@ -935,6 +983,7 @@ CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
 # CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_XATTR=y
 CONFIG_EXT3_FS_POSIX_ACL=y
@@ -957,6 +1006,7 @@ CONFIG_FS_POSIX_ACL=y
 # CONFIG_XFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
 # CONFIG_QUOTA is not set
 CONFIG_DNOTIFY=y
 CONFIG_AUTOFS_FS=y
@@ -986,7 +1036,6 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
 # CONFIG_DEVPTS_FS_XATTR is not set
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_XATTR is not set
@@ -1016,15 +1065,18 @@ CONFIG_RAMFS=y
 #
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
 # CONFIG_NFS_DIRECTIO is not set
 CONFIG_NFSD=y
 CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
 # CONFIG_NFSD_V4 is not set
 CONFIG_NFSD_TCP=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
diff --git a/arch/x86_64/ia32/Makefile b/arch/x86_64/ia32/Makefile
index a12b19da4b5..f76217d8f57 100644
--- a/arch/x86_64/ia32/Makefile
+++ b/arch/x86_64/ia32/Makefile
@@ -4,14 +4,14 @@
 
 obj-$(CONFIG_IA32_EMULATION) := ia32entry.o sys_ia32.o ia32_ioctl.o \
 	ia32_signal.o tls32.o \
-	ia32_binfmt.o fpu32.o ptrace32.o syscall32.o
+	ia32_binfmt.o fpu32.o ptrace32.o syscall32.o syscall32_syscall.o
 
 sysv-$(CONFIG_SYSVIPC) := ipc32.o
 obj-$(CONFIG_IA32_EMULATION) += $(sysv-y)
 
 obj-$(CONFIG_IA32_AOUT) += ia32_aout.o
 
-$(obj)/syscall32.o: $(src)/syscall32.c \
+$(obj)/syscall32_syscall.o: \
 	$(foreach F,sysenter syscall,$(obj)/vsyscall-$F.so)
 
 # Teach kbuild about targets
diff --git a/arch/x86_64/ia32/ia32_aout.c b/arch/x86_64/ia32/ia32_aout.c
index c12edf5d97f..3e6780fa018 100644
--- a/arch/x86_64/ia32/ia32_aout.c
+++ b/arch/x86_64/ia32/ia32_aout.c
@@ -42,7 +42,7 @@ extern int ia32_setup_arg_pages(struct linux_binprm *bprm,
 static int load_aout_binary(struct linux_binprm *, struct pt_regs * regs);
 static int load_aout_library(struct file*);
 
-#if CORE_DUMP
+#ifdef CORE_DUMP
 static int aout_core_dump(long signr, struct pt_regs * regs, struct file *file);
 
 /*
@@ -103,7 +103,7 @@ static struct linux_binfmt aout_format = {
 	.module		= THIS_MODULE,
 	.load_binary	= load_aout_binary,
 	.load_shlib	= load_aout_library,
-#if CORE_DUMP
+#ifdef CORE_DUMP
 	.core_dump	= aout_core_dump,
 #endif
 	.min_coredump	= PAGE_SIZE
@@ -120,7 +120,7 @@ static void set_brk(unsigned long start, unsigned long end)
 	up_write(&current->mm->mmap_sem);
 }
 
-#if CORE_DUMP
+#ifdef CORE_DUMP
 /*
  * These are the only things you should do on a core-file: use only these
  * macros to write out all the necessary info.
diff --git a/arch/x86_64/ia32/ptrace32.c b/arch/x86_64/ia32/ptrace32.c
index b98b6d2462f..2a925e2af39 100644
--- a/arch/x86_64/ia32/ptrace32.c
+++ b/arch/x86_64/ia32/ptrace32.c
@@ -43,11 +43,11 @@ static int putreg32(struct task_struct *child, unsigned regno, u32 val)
 	switch (regno) {
 	case offsetof(struct user32, regs.fs):
 		if (val && (val & 3) != 3) return -EIO; 
-		child->thread.fs = val & 0xffff; 
+		child->thread.fsindex = val & 0xffff;
 		break;
 	case offsetof(struct user32, regs.gs):
 		if (val && (val & 3) != 3) return -EIO; 
-		child->thread.gs = val & 0xffff;
+		child->thread.gsindex = val & 0xffff;
 		break;
 	case offsetof(struct user32, regs.ds):
 		if (val && (val & 3) != 3) return -EIO; 
@@ -138,10 +138,10 @@ static int getreg32(struct task_struct *child, unsigned regno, u32 *val)
 
 	switch (regno) {
 	case offsetof(struct user32, regs.fs):
-	        *val = child->thread.fs; 
+	        *val = child->thread.fsindex;
 		break;
 	case offsetof(struct user32, regs.gs):
-		*val = child->thread.gs;
+		*val = child->thread.gsindex;
 		break;
 	case offsetof(struct user32, regs.ds):
 		*val = child->thread.ds;
diff --git a/arch/x86_64/ia32/syscall32.c b/arch/x86_64/ia32/syscall32.c
index 816a3b89f13..adbc5f8089e 100644
--- a/arch/x86_64/ia32/syscall32.c
+++ b/arch/x86_64/ia32/syscall32.c
@@ -14,16 +14,6 @@
 #include <asm/tlbflush.h>
 #include <asm/ia32_unistd.h>
 
-/* 32bit VDSOs mapped into user space. */ 
-asm(".section \".init.data\",\"aw\"\n"
-    "syscall32_syscall:\n"
-    ".incbin \"arch/x86_64/ia32/vsyscall-syscall.so\"\n"
-    "syscall32_syscall_end:\n"
-    "syscall32_sysenter:\n"
-    ".incbin \"arch/x86_64/ia32/vsyscall-sysenter.so\"\n"
-    "syscall32_sysenter_end:\n"
-    ".previous");
-
 extern unsigned char syscall32_syscall[], syscall32_syscall_end[];
 extern unsigned char syscall32_sysenter[], syscall32_sysenter_end[];
 extern int sysctl_vsyscall32;
diff --git a/arch/x86_64/ia32/syscall32_syscall.S b/arch/x86_64/ia32/syscall32_syscall.S
new file mode 100644
index 00000000000..8f8271bdf13
--- /dev/null
+++ b/arch/x86_64/ia32/syscall32_syscall.S
@@ -0,0 +1,17 @@
+/* 32bit VDSOs mapped into user space. */
+
+	.section ".init.data","aw"
+
+	.globl syscall32_syscall
+	.globl syscall32_syscall_end
+
+syscall32_syscall:
+	.incbin "arch/x86_64/ia32/vsyscall-syscall.so"
+syscall32_syscall_end:
+
+	.globl syscall32_sysenter
+	.globl syscall32_sysenter_end
+
+syscall32_sysenter:
+	.incbin "arch/x86_64/ia32/vsyscall-sysenter.so"
+syscall32_sysenter_end:
diff --git a/arch/x86_64/kernel/entry.S b/arch/x86_64/kernel/entry.S
index 28817490fdc..096d470e280 100644
--- a/arch/x86_64/kernel/entry.S
+++ b/arch/x86_64/kernel/entry.S
@@ -76,7 +76,7 @@
 
 	.macro FAKE_STACK_FRAME child_rip
 	/* push in order ss, rsp, eflags, cs, rip */
-	xorq %rax, %rax
+	xorl %eax, %eax
 	pushq %rax /* ss */
 	CFI_ADJUST_CFA_OFFSET	8
 	pushq %rax /* rsp */
@@ -423,7 +423,7 @@ ENTRY(stub_rt_sigreturn)
 	testl $3,CS(%rdi)
 	je 1f
 	swapgs	
-1:	addl $1,%gs:pda_irqcount	# RED-PEN should check preempt count
+1:	incl	%gs:pda_irqcount	# RED-PEN should check preempt count
 	movq %gs:pda_irqstackptr,%rax
 	cmoveq %rax,%rsp							
 	pushq %rdi			# save old stack	
@@ -436,7 +436,7 @@ ENTRY(common_interrupt)
 ret_from_intr:		
 	popq  %rdi
 	cli	
-	subl $1,%gs:pda_irqcount
+	decl %gs:pda_irqcount
 #ifdef CONFIG_DEBUG_INFO
 	movq RBP(%rdi),%rbp
 #endif
@@ -494,7 +494,7 @@ retint_signal:
 	sti
 	SAVE_REST
 	movq $-1,ORIG_RAX(%rsp) 			
-	xorq %rsi,%rsi		# oldset
+	xorl %esi,%esi		# oldset
 	movq %rsp,%rdi		# &pt_regs
 	call do_notify_resume
 	RESTORE_REST
@@ -752,7 +752,7 @@ child_rip:
 	movq %rsi, %rdi
 	call *%rax
 	# exit
-	xorq %rdi, %rdi
+	xorl %edi, %edi
 	call do_exit
 
 /*
@@ -918,3 +918,15 @@ ENTRY(machine_check)
 ENTRY(call_debug)
        zeroentry do_call_debug
 
+ENTRY(call_softirq)
+	movq %gs:pda_irqstackptr,%rax
+	pushq %r15
+	movq %rsp,%r15
+	incl %gs:pda_irqcount
+	cmove %rax,%rsp
+	call __do_softirq
+	movq %r15,%rsp
+	decl %gs:pda_irqcount
+	popq %r15
+	ret
+
diff --git a/arch/x86_64/kernel/genapic.c b/arch/x86_64/kernel/genapic.c
index 69b9c25a8fc..30c843a5efd 100644
--- a/arch/x86_64/kernel/genapic.c
+++ b/arch/x86_64/kernel/genapic.c
@@ -31,6 +31,7 @@ u8 x86_cpu_to_log_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
 
 extern struct genapic apic_cluster;
 extern struct genapic apic_flat;
+extern struct genapic apic_physflat;
 
 struct genapic *genapic = &apic_flat;
 
@@ -44,12 +45,7 @@ void __init clustered_apic_check(void)
 	u8 clusters, max_cluster;
 	u8 id;
 	u8 cluster_cnt[NUM_APIC_CLUSTERS];
-
-	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
-		/* AMD always uses flat mode right now */
-		genapic = &apic_flat;
-		goto print;
-	}
+	int num_cpus = 0;
 
 #if defined(CONFIG_ACPI_BUS)
 	/*
@@ -64,15 +60,34 @@ void __init clustered_apic_check(void)
 #endif
 
 	memset(cluster_cnt, 0, sizeof(cluster_cnt));
-
 	for (i = 0; i < NR_CPUS; i++) {
 		id = bios_cpu_apicid[i];
-		if (id != BAD_APICID)
-			cluster_cnt[APIC_CLUSTERID(id)]++;
+		if (id == BAD_APICID)
+			continue;
+		num_cpus++;
+		cluster_cnt[APIC_CLUSTERID(id)]++;
 	}
 
+	/* Don't use clustered mode on AMD platforms. */
+ 	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
+		genapic = &apic_physflat;
+#ifndef CONFIG_CPU_HOTPLUG
+		/* In the CPU hotplug case we cannot use broadcast mode
+		   because that opens a race when a CPU is removed.
+		   Stay at physflat mode in this case.
+		   It is bad to do this unconditionally though. Once
+		   we have ACPI platform support for CPU hotplug
+		   we should detect hotplug capablity from ACPI tables and
+		   only do this when really needed. -AK */
+		if (num_cpus <= 8)
+			genapic = &apic_flat;
+#endif
+ 		goto print;
+ 	}
+
 	clusters = 0;
 	max_cluster = 0;
+
 	for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
 		if (cluster_cnt[i] > 0) {
 			++clusters;
diff --git a/arch/x86_64/kernel/genapic_flat.c b/arch/x86_64/kernel/genapic_flat.c
index 28284696508..adc96282a9e 100644
--- a/arch/x86_64/kernel/genapic_flat.c
+++ b/arch/x86_64/kernel/genapic_flat.c
@@ -2,13 +2,11 @@
  * Copyright 2004 James Cleverdon, IBM.
  * Subject to the GNU Public License, v.2
  *
- * Flat APIC subarch code.  Maximum 8 CPUs, logical delivery.
+ * Flat APIC subarch code.
  *
  * Hacked for x86-64 by James Cleverdon from i386 architecture code by
  * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
  * James Cleverdon.
- * Ashok Raj <ashok.raj@intel.com>
- * 	Removed IPI broadcast shortcut to support CPU hotplug
  */
 #include <linux/config.h>
 #include <linux/threads.h>
@@ -20,47 +18,6 @@
 #include <asm/smp.h>
 #include <asm/ipi.h>
 
-/*
- * The following permit choosing broadcast IPI shortcut v.s sending IPI only
- * to online cpus via the send_IPI_mask varient.
- * The mask version is my preferred option, since it eliminates a lot of
- * other extra code that would need to be written to cleanup intrs sent
- * to a CPU while offline.
- *
- * Sending broadcast introduces lots of trouble in CPU hotplug situations.
- * These IPI's are delivered to cpu's irrespective of their offline status
- * and could pickup stale intr data when these CPUS are turned online.
- *
- * Not using broadcast is a cleaner approach IMO, but Andi Kleen disagrees with
- * the idea of not using broadcast IPI's anymore. Hence the run time check
- * is introduced, on his request so we can choose an alternate mechanism.
- *
- * Initial wacky performance tests that collect cycle counts show
- * no increase in using mask v.s broadcast version. In fact they seem
- * identical in terms of cycle counts.
- *
- * if we need to use broadcast, we need to do the following.
- *
- * cli;
- * hold call_lock;
- * clear any pending IPI, just ack and clear all pending intr
- * set cpu_online_map;
- * release call_lock;
- * sti;
- *
- * The complicated dummy irq processing shown above is not required if
- * we didnt sent IPI's to wrong CPU's in the first place.
- *
- * - Ashok Raj <ashok.raj@intel.com>
- */
-#ifdef CONFIG_HOTPLUG_CPU
-#define DEFAULT_SEND_IPI	(1)
-#else
-#define DEFAULT_SEND_IPI	(0)
-#endif
-
-static int no_broadcast=DEFAULT_SEND_IPI;
-
 static cpumask_t flat_target_cpus(void)
 {
 	return cpu_online_map;
@@ -119,37 +76,15 @@ static void flat_send_IPI_mask(cpumask_t cpumask, int vector)
 	local_irq_restore(flags);
 }
 
-static inline void __local_flat_send_IPI_allbutself(int vector)
-{
-	if (no_broadcast) {
-		cpumask_t mask = cpu_online_map;
-		int this_cpu = get_cpu();
-
-		cpu_clear(this_cpu, mask);
-		flat_send_IPI_mask(mask, vector);
-		put_cpu();
-	}
-	else
-		__send_IPI_shortcut(APIC_DEST_ALLBUT, vector, APIC_DEST_LOGICAL);
-}
-
-static inline void __local_flat_send_IPI_all(int vector)
-{
-	if (no_broadcast)
-		flat_send_IPI_mask(cpu_online_map, vector);
-	else
-		__send_IPI_shortcut(APIC_DEST_ALLINC, vector, APIC_DEST_LOGICAL);
-}
-
 static void flat_send_IPI_allbutself(int vector)
 {
 	if (((num_online_cpus()) - 1) >= 1)
-		__local_flat_send_IPI_allbutself(vector);
+		__send_IPI_shortcut(APIC_DEST_ALLBUT, vector,APIC_DEST_LOGICAL);
 }
 
 static void flat_send_IPI_all(int vector)
 {
-	__local_flat_send_IPI_all(vector);
+	__send_IPI_shortcut(APIC_DEST_ALLINC, vector, APIC_DEST_LOGICAL);
 }
 
 static int flat_apic_id_registered(void)
@@ -170,16 +105,6 @@ static unsigned int phys_pkg_id(int index_msb)
 	return ((ebx >> 24) & 0xFF) >> index_msb;
 }
 
-static __init int no_ipi_broadcast(char *str)
-{
-	get_option(&str, &no_broadcast);
-	printk ("Using %s mode\n", no_broadcast ? "No IPI Broadcast" :
-											"IPI Broadcast");
-	return 1;
-}
-
-__setup("no_ipi_broadcast", no_ipi_broadcast);
-
 struct genapic apic_flat =  {
 	.name = "flat",
 	.int_delivery_mode = dest_LowestPrio,
@@ -195,11 +120,62 @@ struct genapic apic_flat =  {
 	.phys_pkg_id = phys_pkg_id,
 };
 
-static int __init print_ipi_mode(void)
+/*
+ * Physflat mode is used when there are more than 8 CPUs on a AMD system.
+ * We cannot use logical delivery in this case because the mask
+ * overflows, so use physical mode.
+ */
+
+static cpumask_t physflat_target_cpus(void)
+{
+	return cpumask_of_cpu(0);
+}
+
+static void physflat_send_IPI_mask(cpumask_t cpumask, int vector)
+{
+	send_IPI_mask_sequence(cpumask, vector);
+}
+
+static void physflat_send_IPI_allbutself(int vector)
+{
+	cpumask_t allbutme = cpu_online_map;
+	int me = get_cpu();
+	cpu_clear(me, allbutme);
+	physflat_send_IPI_mask(allbutme, vector);
+	put_cpu();
+}
+
+static void physflat_send_IPI_all(int vector)
 {
-	printk ("Using IPI %s mode\n", no_broadcast ? "No-Shortcut" :
-											"Shortcut");
-	return 0;
+	physflat_send_IPI_mask(cpu_online_map, vector);
 }
 
-late_initcall(print_ipi_mode);
+static unsigned int physflat_cpu_mask_to_apicid(cpumask_t cpumask)
+{
+	int cpu;
+
+	/*
+	 * We're using fixed IRQ delivery, can only return one phys APIC ID.
+	 * May as well be the first.
+	 */
+	cpu = first_cpu(cpumask);
+	if ((unsigned)cpu < NR_CPUS)
+		return x86_cpu_to_apicid[cpu];
+	else
+		return BAD_APICID;
+}
+
+struct genapic apic_physflat =  {
+	.name = "physical flat",
+	.int_delivery_mode = dest_LowestPrio,
+	.int_dest_mode = (APIC_DEST_PHYSICAL != 0),
+	.int_delivery_dest = APIC_DEST_PHYSICAL | APIC_DM_LOWEST,
+	.target_cpus = physflat_target_cpus,
+	.apic_id_registered = flat_apic_id_registered,
+	.init_apic_ldr = flat_init_apic_ldr,/*not needed, but shouldn't hurt*/
+	.send_IPI_all = physflat_send_IPI_all,
+	.send_IPI_allbutself = physflat_send_IPI_allbutself,
+	.send_IPI_mask = physflat_send_IPI_mask,
+	.cpu_mask_to_apicid = physflat_cpu_mask_to_apicid,
+	.phys_pkg_id = phys_pkg_id,
+};
diff --git a/arch/x86_64/kernel/head.S b/arch/x86_64/kernel/head.S
index 8d765aa77a2..98ff5eb32b9 100644
--- a/arch/x86_64/kernel/head.S
+++ b/arch/x86_64/kernel/head.S
@@ -137,14 +137,14 @@ startup_64:
 	wrmsr
 
 	/* Setup cr0 */
-	xorq	%rax, %rax
-	btsq	$31, %rax			/* Enable paging */
-	btsq	$0, %rax			/* Enable protected mode */
-	btsq	$1, %rax			/* Enable MP */
-	btsq	$4, %rax			/* Enable ET */
-	btsq	$5, %rax			/* Enable NE */
-	btsq	$16, %rax			/* Enable WP */
-	btsq	$18, %rax			/* Enable AM */
+#define CR0_PM				1		/* protected mode */
+#define CR0_MP				(1<<1)
+#define CR0_ET				(1<<4)
+#define CR0_NE				(1<<5)
+#define CR0_WP				(1<<16)
+#define CR0_AM				(1<<18)
+#define CR0_PAGING 			(1<<31)
+	movl $CR0_PM|CR0_MP|CR0_ET|CR0_NE|CR0_WP|CR0_AM|CR0_PAGING,%eax
 	/* Make changes effective */
 	movq	%rax, %cr0
 
diff --git a/arch/x86_64/kernel/irq.c b/arch/x86_64/kernel/irq.c
index cc3fb85f514..849a20aec7c 100644
--- a/arch/x86_64/kernel/irq.c
+++ b/arch/x86_64/kernel/irq.c
@@ -135,3 +135,22 @@ void fixup_irqs(cpumask_t map)
 	local_irq_disable();
 }
 #endif
+
+extern void call_softirq(void);
+
+asmlinkage void do_softirq(void)
+{
+ 	__u32 pending;
+ 	unsigned long flags;
+
+ 	if (in_interrupt())
+ 		return;
+
+ 	local_irq_save(flags);
+ 	pending = local_softirq_pending();
+ 	/* Switch to interrupt stack */
+ 	if (pending)
+		call_softirq();
+ 	local_irq_restore(flags);
+}
+EXPORT_SYMBOL(do_softirq);
diff --git a/arch/x86_64/kernel/machine_kexec.c b/arch/x86_64/kernel/machine_kexec.c
index 60d1eff4156..89fab51e20f 100644
--- a/arch/x86_64/kernel/machine_kexec.c
+++ b/arch/x86_64/kernel/machine_kexec.c
@@ -8,43 +8,26 @@
 
 #include <linux/mm.h>
 #include <linux/kexec.h>
-#include <linux/delay.h>
 #include <linux/string.h>
 #include <linux/reboot.h>
-#include <asm/pda.h>
 #include <asm/pgtable.h>
-#include <asm/pgalloc.h>
 #include <asm/tlbflush.h>
 #include <asm/mmu_context.h>
 #include <asm/io.h>
-#include <asm/apic.h>
-#include <asm/cpufeature.h>
-#include <asm/hw_irq.h>
-
-#define LEVEL0_SIZE (1UL << 12UL)
-#define LEVEL1_SIZE (1UL << 21UL)
-#define LEVEL2_SIZE (1UL << 30UL)
-#define LEVEL3_SIZE (1UL << 39UL)
-#define LEVEL4_SIZE (1UL << 48UL)
-
-#define L0_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
-#define L1_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE)
-#define L2_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
-#define L3_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
-
-static void init_level2_page(u64 *level2p, unsigned long addr)
+
+static void init_level2_page(pmd_t *level2p, unsigned long addr)
 {
 	unsigned long end_addr;
 
 	addr &= PAGE_MASK;
-	end_addr = addr + LEVEL2_SIZE;
+	end_addr = addr + PUD_SIZE;
 	while (addr < end_addr) {
-		*(level2p++) = addr | L1_ATTR;
-		addr += LEVEL1_SIZE;
+		set_pmd(level2p++, __pmd(addr | __PAGE_KERNEL_LARGE_EXEC));
+		addr += PMD_SIZE;
 	}
 }
 
-static int init_level3_page(struct kimage *image, u64 *level3p,
+static int init_level3_page(struct kimage *image, pud_t *level3p,
 				unsigned long addr, unsigned long last_addr)
 {
 	unsigned long end_addr;
@@ -52,32 +35,32 @@ static int init_level3_page(struct kimage *image, u64 *level3p,
 
 	result = 0;
 	addr &= PAGE_MASK;
-	end_addr = addr + LEVEL3_SIZE;
+	end_addr = addr + PGDIR_SIZE;
 	while ((addr < last_addr) && (addr < end_addr)) {
 		struct page *page;
-		u64 *level2p;
+		pmd_t *level2p;
 
 		page = kimage_alloc_control_pages(image, 0);
 		if (!page) {
 			result = -ENOMEM;
 			goto out;
 		}
-		level2p = (u64 *)page_address(page);
+		level2p = (pmd_t *)page_address(page);
 		init_level2_page(level2p, addr);
-		*(level3p++) = __pa(level2p) | L2_ATTR;
-		addr += LEVEL2_SIZE;
+		set_pud(level3p++, __pud(__pa(level2p) | _KERNPG_TABLE));
+		addr += PUD_SIZE;
 	}
 	/* clear the unused entries */
 	while (addr < end_addr) {
-		*(level3p++) = 0;
-		addr += LEVEL2_SIZE;
+		pud_clear(level3p++);
+		addr += PUD_SIZE;
 	}
 out:
 	return result;
 }
 
 
-static int init_level4_page(struct kimage *image, u64 *level4p,
+static int init_level4_page(struct kimage *image, pgd_t *level4p,
 				unsigned long addr, unsigned long last_addr)
 {
 	unsigned long end_addr;
@@ -85,28 +68,28 @@ static int init_level4_page(struct kimage *image, u64 *level4p,
 
 	result = 0;
 	addr &= PAGE_MASK;
-	end_addr = addr + LEVEL4_SIZE;
+	end_addr = addr + (PTRS_PER_PGD * PGDIR_SIZE);
 	while ((addr < last_addr) && (addr < end_addr)) {
 		struct page *page;
-		u64 *level3p;
+		pud_t *level3p;
 
 		page = kimage_alloc_control_pages(image, 0);
 		if (!page) {
 			result = -ENOMEM;
 			goto out;
 		}
-		level3p = (u64 *)page_address(page);
+		level3p = (pud_t *)page_address(page);
 		result = init_level3_page(image, level3p, addr, last_addr);
 		if (result) {
 			goto out;
 		}
-		*(level4p++) = __pa(level3p) | L3_ATTR;
-		addr += LEVEL3_SIZE;
+		set_pgd(level4p++, __pgd(__pa(level3p) | _KERNPG_TABLE));
+		addr += PGDIR_SIZE;
 	}
 	/* clear the unused entries */
 	while (addr < end_addr) {
-		*(level4p++) = 0;
-		addr += LEVEL3_SIZE;
+		pgd_clear(level4p++);
+		addr += PGDIR_SIZE;
 	}
 out:
 	return result;
@@ -115,52 +98,50 @@ out:
 
 static int init_pgtable(struct kimage *image, unsigned long start_pgtable)
 {
-	u64 *level4p;
-	level4p = (u64 *)__va(start_pgtable);
+	pgd_t *level4p;
+	level4p = (pgd_t *)__va(start_pgtable);
  	return init_level4_page(image, level4p, 0, end_pfn << PAGE_SHIFT);
 }
 
 static void set_idt(void *newidt, u16 limit)
 {
-	unsigned char curidt[10];
+	struct desc_ptr curidt;
 
 	/* x86-64 supports unaliged loads & stores */
-	(*(u16 *)(curidt)) = limit;
-	(*(u64 *)(curidt +2)) = (unsigned long)(newidt);
+	curidt.size    = limit;
+	curidt.address = (unsigned long)newidt;
 
 	__asm__ __volatile__ (
-		"lidt %0\n"
-		: "=m" (curidt)
+		"lidtq %0\n"
+		: : "m" (curidt)
 		);
 };
 
 
 static void set_gdt(void *newgdt, u16 limit)
 {
-	unsigned char curgdt[10];
+	struct desc_ptr curgdt;
 
 	/* x86-64 supports unaligned loads & stores */
-	(*(u16 *)(curgdt)) = limit;
-	(*(u64 *)(curgdt +2)) = (unsigned long)(newgdt);
+	curgdt.size    = limit;
+	curgdt.address = (unsigned long)newgdt;
 
 	__asm__ __volatile__ (
-		"lgdt %0\n"
-		: "=m" (curgdt)
+		"lgdtq %0\n"
+		: : "m" (curgdt)
 		);
 };
 
 static void load_segments(void)
 {
 	__asm__ __volatile__ (
-		"\tmovl $"STR(__KERNEL_DS)",%eax\n"
-		"\tmovl %eax,%ds\n"
-		"\tmovl %eax,%es\n"
-		"\tmovl %eax,%ss\n"
-		"\tmovl %eax,%fs\n"
-		"\tmovl %eax,%gs\n"
+		"\tmovl %0,%%ds\n"
+		"\tmovl %0,%%es\n"
+		"\tmovl %0,%%ss\n"
+		"\tmovl %0,%%fs\n"
+		"\tmovl %0,%%gs\n"
+		: : "a" (__KERNEL_DS)
 		);
-#undef STR
-#undef __STR
 }
 
 typedef NORET_TYPE void (*relocate_new_kernel_t)(unsigned long indirection_page,
@@ -178,7 +159,7 @@ int machine_kexec_prepare(struct kimage *image)
 
 	/* Calculate the offsets */
 	start_pgtable = page_to_pfn(image->control_code_page) << PAGE_SHIFT;
-	control_code_buffer = start_pgtable + 4096UL;
+	control_code_buffer = start_pgtable + PAGE_SIZE;
 
 	/* Setup the identity mapped 64bit page table */
 	result = init_pgtable(image, start_pgtable);
@@ -214,7 +195,7 @@ NORET_TYPE void machine_kexec(struct kimage *image)
 	/* Calculate the offsets */
 	page_list = image->head;
 	start_pgtable = page_to_pfn(image->control_code_page) << PAGE_SHIFT;
-	control_code_buffer = start_pgtable + 4096UL;
+	control_code_buffer = start_pgtable + PAGE_SIZE;
 
 	/* Set the low half of the page table to my identity mapped
 	 * page table for kexec.  Leave the high half pointing at the
diff --git a/arch/x86_64/kernel/mce.c b/arch/x86_64/kernel/mce.c
index 21e70625a49..8aa56736cde 100644
--- a/arch/x86_64/kernel/mce.c
+++ b/arch/x86_64/kernel/mce.c
@@ -15,6 +15,8 @@
 #include <linux/sysdev.h>
 #include <linux/miscdevice.h>
 #include <linux/fs.h>
+#include <linux/cpu.h>
+#include <linux/percpu.h>
 #include <asm/processor.h> 
 #include <asm/msr.h>
 #include <asm/mce.h>
@@ -34,6 +36,7 @@ static unsigned long bank[NR_BANKS] = { [0 ... NR_BANKS-1] = ~0UL };
 static unsigned long console_logged;
 static int notify_user;
 static int rip_msr;
+static int mce_bootlog;
 
 /*
  * Lockless MCE logging infrastructure.
@@ -195,10 +198,11 @@ void do_machine_check(struct pt_regs * regs, long error_code)
 			rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr);
 
 		mce_get_rip(&m, regs);
-		if (error_code != -1)
+		if (error_code >= 0)
 			rdtscll(m.tsc);
 		wrmsrl(MSR_IA32_MC0_STATUS + i*4, 0);
-		mce_log(&m);
+		if (error_code != -2)
+			mce_log(&m);
 
 		/* Did this bank cause the exception? */
 		/* Assume that the bank with uncorrectable errors did it,
@@ -313,7 +317,7 @@ static void mce_init(void *dummy)
 
 	/* Log the machine checks left over from the previous reset.
 	   This also clears all registers */
-	do_machine_check(NULL, -1);
+	do_machine_check(NULL, mce_bootlog ? -1 : -2);
 
 	set_in_cr4(X86_CR4_MCE);
 
@@ -474,11 +478,17 @@ static int __init mcheck_disable(char *str)
 }
 
 /* mce=off disables machine check. Note you can reenable it later
-   using sysfs */
+   using sysfs.
+   mce=bootlog Log MCEs from before booting. Disabled by default to work
+   around buggy BIOS that leave bogus MCEs.  */
 static int __init mcheck_enable(char *str)
 {
+	if (*str == '=')
+		str++;
 	if (!strcmp(str, "off"))
 		mce_dont_init = 1;
+	else if (!strcmp(str, "bootlog"))
+		mce_bootlog = 1;
 	else
 		printk("mce= argument %s ignored. Please use /sys", str); 
 	return 0;
@@ -514,10 +524,7 @@ static struct sysdev_class mce_sysclass = {
 	set_kset_name("machinecheck"),
 };
 
-static struct sys_device device_mce = {
-	.id	= 0,
-	.cls	= &mce_sysclass,
-};
+static DEFINE_PER_CPU(struct sys_device, device_mce);
 
 /* Why are there no generic functions for this? */
 #define ACCESSOR(name, var, start) \
@@ -542,27 +549,83 @@ ACCESSOR(bank4ctl,bank[4],mce_restart())
 ACCESSOR(tolerant,tolerant,)
 ACCESSOR(check_interval,check_interval,mce_restart())
 
-static __cpuinit int mce_init_device(void)
+/* Per cpu sysdev init.  All of the cpus still share the same ctl bank */
+static __cpuinit int mce_create_device(unsigned int cpu)
 {
 	int err;
+	if (!mce_available(&cpu_data[cpu]))
+		return -EIO;
+
+	per_cpu(device_mce,cpu).id = cpu;
+	per_cpu(device_mce,cpu).cls = &mce_sysclass;
+
+	err = sysdev_register(&per_cpu(device_mce,cpu));
+
+	if (!err) {
+		sysdev_create_file(&per_cpu(device_mce,cpu), &attr_bank0ctl);
+		sysdev_create_file(&per_cpu(device_mce,cpu), &attr_bank1ctl);
+		sysdev_create_file(&per_cpu(device_mce,cpu), &attr_bank2ctl);
+		sysdev_create_file(&per_cpu(device_mce,cpu), &attr_bank3ctl);
+		sysdev_create_file(&per_cpu(device_mce,cpu), &attr_bank4ctl);
+		sysdev_create_file(&per_cpu(device_mce,cpu), &attr_tolerant);
+		sysdev_create_file(&per_cpu(device_mce,cpu), &attr_check_interval);
+	}
+	return err;
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+static __cpuinit void mce_remove_device(unsigned int cpu)
+{
+	sysdev_remove_file(&per_cpu(device_mce,cpu), &attr_bank0ctl);
+	sysdev_remove_file(&per_cpu(device_mce,cpu), &attr_bank1ctl);
+	sysdev_remove_file(&per_cpu(device_mce,cpu), &attr_bank2ctl);
+	sysdev_remove_file(&per_cpu(device_mce,cpu), &attr_bank3ctl);
+	sysdev_remove_file(&per_cpu(device_mce,cpu), &attr_bank4ctl);
+	sysdev_remove_file(&per_cpu(device_mce,cpu), &attr_tolerant);
+	sysdev_remove_file(&per_cpu(device_mce,cpu), &attr_check_interval);
+	sysdev_unregister(&per_cpu(device_mce,cpu));
+}
+#endif
+
+/* Get notified when a cpu comes on/off. Be hotplug friendly. */
+static __cpuinit int
+mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
+{
+	unsigned int cpu = (unsigned long)hcpu;
+
+	switch (action) {
+	case CPU_ONLINE:
+		mce_create_device(cpu);
+		break;
+#ifdef CONFIG_HOTPLUG_CPU
+	case CPU_DEAD:
+		mce_remove_device(cpu);
+		break;
+#endif
+	}
+	return NOTIFY_OK;
+}
+
+static struct notifier_block mce_cpu_notifier = {
+	.notifier_call = mce_cpu_callback,
+};
+
+static __init int mce_init_device(void)
+{
+	int err;
+	int i = 0;
+
 	if (!mce_available(&boot_cpu_data))
 		return -EIO;
 	err = sysdev_class_register(&mce_sysclass);
-	if (!err)
-		err = sysdev_register(&device_mce);
-	if (!err) { 
-		/* could create per CPU objects, but it is not worth it. */
-		sysdev_create_file(&device_mce, &attr_bank0ctl); 
-		sysdev_create_file(&device_mce, &attr_bank1ctl); 
-		sysdev_create_file(&device_mce, &attr_bank2ctl); 
-		sysdev_create_file(&device_mce, &attr_bank3ctl); 
-		sysdev_create_file(&device_mce, &attr_bank4ctl); 
-		sysdev_create_file(&device_mce, &attr_tolerant); 
-		sysdev_create_file(&device_mce, &attr_check_interval);
-	} 
-	
+
+	for_each_online_cpu(i) {
+		mce_create_device(i);
+	}
+
+	register_cpu_notifier(&mce_cpu_notifier);
 	misc_register(&mce_log_device);
 	return err;
-
 }
+
 device_initcall(mce_init_device);
diff --git a/arch/x86_64/kernel/mpparse.c b/arch/x86_64/kernel/mpparse.c
index 9c5aa2a790c..79c362d03e2 100644
--- a/arch/x86_64/kernel/mpparse.c
+++ b/arch/x86_64/kernel/mpparse.c
@@ -109,7 +109,7 @@ static int __init mpf_checksum(unsigned char *mp, int len)
 
 static void __init MP_processor_info (struct mpc_config_processor *m)
 {
-	int ver;
+	int ver, cpu;
 	static int found_bsp=0;
 
 	if (!(m->mpc_cpuflag & CPU_ENABLED))
@@ -131,7 +131,7 @@ static void __init MP_processor_info (struct mpc_config_processor *m)
 		return;
 	}
 
-	num_processors++;
+	cpu = num_processors++;
 
 	if (m->mpc_apicid > MAX_APICS) {
 		printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
@@ -155,13 +155,18 @@ static void __init MP_processor_info (struct mpc_config_processor *m)
  		 * in same order as logical cpu numbers. Hence the first
  		 * entry is BSP, and so on.
  		 */
+		cpu = 0;
+
  		bios_cpu_apicid[0] = m->mpc_apicid;
  		x86_cpu_to_apicid[0] = m->mpc_apicid;
  		found_bsp = 1;
- 	} else {
- 		bios_cpu_apicid[num_processors - found_bsp] = m->mpc_apicid;
- 		x86_cpu_to_apicid[num_processors - found_bsp] = m->mpc_apicid;
- 	}
+ 	} else
+		cpu = num_processors - found_bsp;
+	bios_cpu_apicid[cpu] = m->mpc_apicid;
+	x86_cpu_to_apicid[cpu] = m->mpc_apicid;
+
+	cpu_set(cpu, cpu_possible_map);
+	cpu_set(cpu, cpu_present_map);
 }
 
 static void __init MP_bus_info (struct mpc_config_bus *m)
@@ -965,8 +970,21 @@ int mp_register_gsi(u32 gsi, int edge_level, int active_high_low)
 		 * due to unused I/O APIC pins.
 		 */
 		int irq = gsi;
-		gsi = pci_irq++;
-		gsi_to_irq[irq] = gsi;
+		if (gsi < MAX_GSI_NUM) {
+			if (gsi > 15)
+				gsi = pci_irq++;
+#ifdef CONFIG_ACPI_BUS
+			/*
+			 * Don't assign IRQ used by ACPI SCI
+			 */
+			if (gsi == acpi_fadt.sci_int)
+				gsi = pci_irq++;
+#endif
+			gsi_to_irq[irq] = gsi;
+		} else {
+			printk(KERN_ERR "GSI %u is too high\n", gsi);
+			return gsi;
+		}
 	}
 
 	io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c
index 5fd03225058..116a491e296 100644
--- a/arch/x86_64/kernel/setup.c
+++ b/arch/x86_64/kernel/setup.c
@@ -645,15 +645,15 @@ void __init setup_arch(char **cmdline_p)
 		}
 	}
 #endif
-
-	sparse_init();
-
 #ifdef CONFIG_KEXEC
 	if (crashk_res.start != crashk_res.end) {
 		reserve_bootmem(crashk_res.start,
 			crashk_res.end - crashk_res.start + 1);
 	}
 #endif
+
+	sparse_init();
+
 	paging_init();
 
 	check_ioapic();
@@ -765,8 +765,6 @@ static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
 	int cpu = smp_processor_id();
 	int node = 0;
 	unsigned bits;
-	if (c->x86_num_cores == 1)
-		return;
 
 	bits = 0;
 	while ((1 << bits) < c->x86_num_cores)
@@ -1081,8 +1079,7 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
 	else
 		mtrr_ap_init();
 #ifdef CONFIG_NUMA
-	if (c != &boot_cpu_data)
-		numa_add_cpu(c - cpu_data);
+	numa_add_cpu(smp_processor_id());
 #endif
 }
  
diff --git a/arch/x86_64/kernel/setup64.c b/arch/x86_64/kernel/setup64.c
index f2b9c6bc999..34082c1cc41 100644
--- a/arch/x86_64/kernel/setup64.c
+++ b/arch/x86_64/kernel/setup64.c
@@ -12,6 +12,7 @@
 #include <linux/string.h>
 #include <linux/bootmem.h>
 #include <linux/bitops.h>
+#include <linux/module.h>
 #include <asm/bootsetup.h>
 #include <asm/pda.h>
 #include <asm/pgtable.h>
@@ -22,10 +23,8 @@
 #include <asm/smp.h>
 #include <asm/i387.h>
 #include <asm/percpu.h>
-#include <asm/mtrr.h>
 #include <asm/proto.h>
-#include <asm/mman.h>
-#include <asm/numa.h>
+#include <asm/sections.h>
 
 char x86_boot_params[BOOT_PARAM_SIZE] __initdata = {0,};
 
@@ -33,11 +32,6 @@ cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
 
 struct x8664_pda cpu_pda[NR_CPUS] __cacheline_aligned; 
 
-extern struct task_struct init_task;
-
-extern unsigned char __per_cpu_start[], __per_cpu_end[]; 
-
-extern struct desc_ptr cpu_gdt_descr[];
 struct desc_ptr idt_descr = { 256 * 16, (unsigned long) idt_table }; 
 
 char boot_cpu_stack[IRQSTACKSIZE] __attribute__((section(".bss.page_aligned")));
@@ -101,7 +95,7 @@ void __init setup_per_cpu_areas(void)
 #endif
 
 	for (i = 0; i < NR_CPUS; i++) { 
-		unsigned char *ptr;
+		char *ptr;
 
 		if (!NODE_DATA(cpu_to_node(i))) {
 			printk("cpu with no node %d, num_online_nodes %d\n",
@@ -190,11 +184,7 @@ void __cpuinit check_efer(void)
  */
 void __cpuinit cpu_init (void)
 {
-#ifdef CONFIG_SMP
 	int cpu = stack_smp_processor_id();
-#else
-	int cpu = smp_processor_id();
-#endif
 	struct tss_struct *t = &per_cpu(init_tss, cpu);
 	unsigned long v; 
 	char *estacks = NULL; 
@@ -214,7 +204,7 @@ void __cpuinit cpu_init (void)
 
 	printk("Initializing CPU#%d\n", cpu);
 
-		clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
+	clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
 
 	/*
 	 * Initialize the per-CPU GDT with the boot GDT,
diff --git a/arch/x86_64/kernel/smp.c b/arch/x86_64/kernel/smp.c
index ccae392886a..e5958220d6b 100644
--- a/arch/x86_64/kernel/smp.c
+++ b/arch/x86_64/kernel/smp.c
@@ -129,10 +129,9 @@ asmlinkage void smp_invalidate_interrupt (void)
 		} else
 			leave_mm(cpu);
 	}
+out:
 	ack_APIC_irq();
 	cpu_clear(cpu, flush_cpumask);
-
-out:
 	put_cpu_no_resched();
 }
 
@@ -294,6 +293,69 @@ void unlock_ipi_call_lock(void)
 }
 
 /*
+ * this function sends a 'generic call function' IPI to one other CPU
+ * in the system.
+ */
+static void __smp_call_function_single (int cpu, void (*func) (void *info), void *info,
+				int nonatomic, int wait)
+{
+	struct call_data_struct data;
+	int cpus = 1;
+
+	data.func = func;
+	data.info = info;
+	atomic_set(&data.started, 0);
+	data.wait = wait;
+	if (wait)
+		atomic_set(&data.finished, 0);
+
+	call_data = &data;
+	wmb();
+	/* Send a message to all other CPUs and wait for them to respond */
+	send_IPI_mask(cpumask_of_cpu(cpu), CALL_FUNCTION_VECTOR);
+
+	/* Wait for response */
+	while (atomic_read(&data.started) != cpus)
+		cpu_relax();
+
+	if (!wait)
+		return;
+
+	while (atomic_read(&data.finished) != cpus)
+		cpu_relax();
+}
+
+/*
+ * smp_call_function_single - Run a function on another CPU
+ * @func: The function to run. This must be fast and non-blocking.
+ * @info: An arbitrary pointer to pass to the function.
+ * @nonatomic: Currently unused.
+ * @wait: If true, wait until function has completed on other CPUs.
+ *
+ * Retrurns 0 on success, else a negative status code.
+ *
+ * Does not return until the remote CPU is nearly ready to execute <func>
+ * or is or has executed.
+ */
+
+int smp_call_function_single (int cpu, void (*func) (void *info), void *info,
+	int nonatomic, int wait)
+{
+	/* prevent preemption and reschedule on another processor */
+	int me = get_cpu();
+	if (cpu == me) {
+		WARN_ON(1);
+		put_cpu();
+		return -EBUSY;
+	}
+	spin_lock_bh(&call_lock);
+	__smp_call_function_single(cpu, func, info, nonatomic, wait);
+	spin_unlock_bh(&call_lock);
+	put_cpu();
+	return 0;
+}
+
+/*
  * this function sends a 'generic call function' IPI to all other CPUs
  * in the system.
  */
diff --git a/arch/x86_64/kernel/smpboot.c b/arch/x86_64/kernel/smpboot.c
index b969ee12872..6e4807d64d4 100644
--- a/arch/x86_64/kernel/smpboot.c
+++ b/arch/x86_64/kernel/smpboot.c
@@ -113,24 +113,6 @@ struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
 #define set_idle_for_cpu(x,p)   (idle_thread_array[(x)] = (p))
 
 /*
- * cpu_possible_map should be static, it cannot change as cpu's
- * are onlined, or offlined. The reason is per-cpu data-structures
- * are allocated by some modules at init time, and dont expect to
- * do this dynamically on cpu arrival/departure.
- * cpu_present_map on the other hand can change dynamically.
- * In case when cpu_hotplug is not compiled, then we resort to current
- * behaviour, which is cpu_possible == cpu_present.
- * If cpu-hotplug is supported, then we need to preallocate for all
- * those NR_CPUS, hence cpu_possible_map represents entire NR_CPUS range.
- * - Ashok Raj
- */
-#ifdef CONFIG_HOTPLUG_CPU
-#define fixup_cpu_possible_map(x)	cpu_set((x), cpu_possible_map)
-#else
-#define fixup_cpu_possible_map(x)
-#endif
-
-/*
  * Currently trivial. Write the real->protected mode
  * bootstrap into the page concerned. The caller
  * has made sure it's suitably aligned.
@@ -229,9 +211,6 @@ static __cpuinit void sync_master(void *arg)
 {
 	unsigned long flags, i;
 
-	if (smp_processor_id() != boot_cpu_id)
-		return;
-
 	go[MASTER] = 0;
 
 	local_irq_save(flags);
@@ -280,12 +259,12 @@ get_delta(long *rt, long *master)
 	return tcenter - best_tm;
 }
 
-static __cpuinit void sync_tsc(void)
+static __cpuinit void sync_tsc(unsigned int master)
 {
 	int i, done = 0;
 	long delta, adj, adjust_latency = 0;
 	unsigned long flags, rt, master_time_stamp, bound;
-#if DEBUG_TSC_SYNC
+#ifdef DEBUG_TSC_SYNC
 	static struct syncdebug {
 		long rt;	/* roundtrip time */
 		long master;	/* master's timestamp */
@@ -294,9 +273,17 @@ static __cpuinit void sync_tsc(void)
 	} t[NUM_ROUNDS] __cpuinitdata;
 #endif
 
+	printk(KERN_INFO "CPU %d: Syncing TSC to CPU %u.\n",
+		smp_processor_id(), master);
+
 	go[MASTER] = 1;
 
-	smp_call_function(sync_master, NULL, 1, 0);
+	/* It is dangerous to broadcast IPI as cpus are coming up,
+	 * as they may not be ready to accept them.  So since
+	 * we only need to send the ipi to the boot cpu direct
+	 * the message, and avoid the race.
+	 */
+	smp_call_function_single(master, sync_master, NULL, 1, 0);
 
 	while (go[MASTER])	/* wait for master to be ready */
 		no_cpu_relax();
@@ -321,7 +308,7 @@ static __cpuinit void sync_tsc(void)
 				rdtscll(t);
 				wrmsrl(MSR_IA32_TSC, t + adj);
 			}
-#if DEBUG_TSC_SYNC
+#ifdef DEBUG_TSC_SYNC
 			t[i].rt = rt;
 			t[i].master = master_time_stamp;
 			t[i].diff = delta;
@@ -331,7 +318,7 @@ static __cpuinit void sync_tsc(void)
 	}
 	spin_unlock_irqrestore(&tsc_sync_lock, flags);
 
-#if DEBUG_TSC_SYNC
+#ifdef DEBUG_TSC_SYNC
 	for (i = 0; i < NUM_ROUNDS; ++i)
 		printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
 		       t[i].rt, t[i].master, t[i].diff, t[i].lat);
@@ -340,16 +327,14 @@ static __cpuinit void sync_tsc(void)
 	printk(KERN_INFO
 	       "CPU %d: synchronized TSC with CPU %u (last diff %ld cycles, "
 	       "maxerr %lu cycles)\n",
-	       smp_processor_id(), boot_cpu_id, delta, rt);
+	       smp_processor_id(), master, delta, rt);
 }
 
 static void __cpuinit tsc_sync_wait(void)
 {
 	if (notscsync || !cpu_has_tsc)
 		return;
-	printk(KERN_INFO "CPU %d: Syncing TSC to CPU %u.\n", smp_processor_id(),
-			boot_cpu_id);
-	sync_tsc();
+	sync_tsc(boot_cpu_id);
 }
 
 static __init int notscsync_setup(char *s)
@@ -537,7 +522,7 @@ void __cpuinit start_secondary(void)
 extern volatile unsigned long init_rsp;
 extern void (*initial_code)(void);
 
-#if APIC_DEBUG
+#ifdef APIC_DEBUG
 static void inquire_remote_apic(int apicid)
 {
 	unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
@@ -773,8 +758,9 @@ do_rest:
 	initial_code = start_secondary;
 	clear_ti_thread_flag(c_idle.idle->thread_info, TIF_FORK);
 
-	printk(KERN_INFO "Booting processor %d/%d rip %lx rsp %lx\n", cpu, apicid,
-	       start_rip, init_rsp);
+	printk(KERN_INFO "Booting processor %d/%d APIC 0x%x\n", cpu,
+		cpus_weight(cpu_present_map),
+		apicid);
 
 	/*
 	 * This grunge runs the startup process for
@@ -841,7 +827,7 @@ do_rest:
 			else
 				/* trampoline code not run */
 				printk("Not responding.\n");
-#if APIC_DEBUG
+#ifdef APIC_DEBUG
 			inquire_remote_apic(apicid);
 #endif
 		}
@@ -924,6 +910,27 @@ static __init void enforce_max_cpus(unsigned max_cpus)
 	}
 }
 
+#ifdef CONFIG_HOTPLUG_CPU
+/*
+ * cpu_possible_map should be static, it cannot change as cpu's
+ * are onlined, or offlined. The reason is per-cpu data-structures
+ * are allocated by some modules at init time, and dont expect to
+ * do this dynamically on cpu arrival/departure.
+ * cpu_present_map on the other hand can change dynamically.
+ * In case when cpu_hotplug is not compiled, then we resort to current
+ * behaviour, which is cpu_possible == cpu_present.
+ * If cpu-hotplug is supported, then we need to preallocate for all
+ * those NR_CPUS, hence cpu_possible_map represents entire NR_CPUS range.
+ * - Ashok Raj
+ */
+static void prefill_possible_map(void)
+{
+	int i;
+	for (i = 0; i < NR_CPUS; i++)
+		cpu_set(i, cpu_possible_map);
+}
+#endif
+
 /*
  * Various sanity checks.
  */
@@ -987,25 +994,15 @@ static int __init smp_sanity_check(unsigned max_cpus)
  */
 void __init smp_prepare_cpus(unsigned int max_cpus)
 {
-	int i;
-
 	nmi_watchdog_default();
 	current_cpu_data = boot_cpu_data;
 	current_thread_info()->cpu = 0;  /* needed? */
 
 	enforce_max_cpus(max_cpus);
 
-	/*
-	 * Fill in cpu_present_mask
-	 */
-	for (i = 0; i < NR_CPUS; i++) {
-		int apicid = cpu_present_to_apicid(i);
-		if (physid_isset(apicid, phys_cpu_present_map)) {
-			cpu_set(i, cpu_present_map);
-			cpu_set(i, cpu_possible_map);
-		}
-		fixup_cpu_possible_map(i);
-	}
+#ifdef CONFIG_HOTPLUG_CPU
+	prefill_possible_map();
+#endif
 
 	if (smp_sanity_check(max_cpus) < 0) {
 		printk(KERN_INFO "SMP disabled\n");
@@ -1189,8 +1186,7 @@ void __cpu_die(unsigned int cpu)
 			printk ("CPU %d is now offline\n", cpu);
 			return;
 		}
-		current->state = TASK_UNINTERRUPTIBLE;
-		schedule_timeout(HZ/10);
+		msleep(100);
 	}
  	printk(KERN_ERR "CPU %u didn't die...\n", cpu);
 }
diff --git a/arch/x86_64/kernel/traps.c b/arch/x86_64/kernel/traps.c
index 10273663000..6ead433a388 100644
--- a/arch/x86_64/kernel/traps.c
+++ b/arch/x86_64/kernel/traps.c
@@ -594,9 +594,6 @@ asmlinkage void default_do_nmi(struct pt_regs *regs)
 	if (!cpu)
 		reason = get_nmi_reason();
 
-	if (!cpu_online(cpu))
-		return;
-
 	if (!(reason & 0xc0)) {
 		if (notify_die(DIE_NMI_IPI, "nmi_ipi", regs, reason, 0, SIGINT)
 								== NOTIFY_STOP)
diff --git a/arch/x86_64/lib/csum-copy.S b/arch/x86_64/lib/csum-copy.S
index 01808ec3783..72fd55ee896 100644
--- a/arch/x86_64/lib/csum-copy.S
+++ b/arch/x86_64/lib/csum-copy.S
@@ -188,8 +188,8 @@ csum_partial_copy_generic:
 	source
 	movw (%rdi),%bx
 	adcl %ebx,%eax
-	dest
 	decl %ecx
+	dest
 	movw %bx,(%rsi)
 	leaq 2(%rdi),%rdi
 	leaq 2(%rsi),%rsi
diff --git a/arch/x86_64/lib/delay.c b/arch/x86_64/lib/delay.c
index 33a873a3c22..841bd738a18 100644
--- a/arch/x86_64/lib/delay.c
+++ b/arch/x86_64/lib/delay.c
@@ -18,8 +18,6 @@
 #include <asm/smp.h>
 #endif
 
-int x86_udelay_tsc = 0;		/* Delay via TSC */
-
 int read_current_timer(unsigned long *timer_value)
 {
 	rdtscll(*timer_value);
diff --git a/arch/x86_64/mm/fault.c b/arch/x86_64/mm/fault.c
index 2f187986f94..493819e543a 100644
--- a/arch/x86_64/mm/fault.c
+++ b/arch/x86_64/mm/fault.c
@@ -23,7 +23,6 @@
 #include <linux/vt_kern.h>		/* For unblank_screen() */
 #include <linux/compiler.h>
 #include <linux/module.h>
-#include <linux/kprobes.h>
 
 #include <asm/system.h>
 #include <asm/uaccess.h>
@@ -440,13 +439,13 @@ good_area:
 	 * the fault.
 	 */
 	switch (handle_mm_fault(mm, vma, address, write)) {
-	case 1:
+	case VM_FAULT_MINOR:
 		tsk->min_flt++;
 		break;
-	case 2:
+	case VM_FAULT_MAJOR:
 		tsk->maj_flt++;
 		break;
-	case 0:
+	case VM_FAULT_SIGBUS:
 		goto do_sigbus;
 	default:
 		goto out_of_memory;
diff --git a/arch/x86_64/mm/numa.c b/arch/x86_64/mm/numa.c
index ac61c186eb0..70cb2904a90 100644
--- a/arch/x86_64/mm/numa.c
+++ b/arch/x86_64/mm/numa.c
@@ -36,34 +36,36 @@ int numa_off __initdata;
 int __init compute_hash_shift(struct node *nodes, int numnodes)
 {
 	int i; 
-	int shift = 24;
-	u64 addr;
+	int shift = 20;
+	unsigned long addr,maxend=0;
 	
-	/* When in doubt use brute force. */
-	while (shift < 48) { 
-		memset(memnodemap,0xff,sizeof(*memnodemap) * NODEMAPSIZE); 
-		for (i = 0; i < numnodes; i++) {
-			if (nodes[i].start == nodes[i].end) 
-				continue;
-			for (addr = nodes[i].start; 
-			     addr < nodes[i].end; 
-			     addr += (1UL << shift)) {
-				if (memnodemap[addr >> shift] != 0xff && 
-				    memnodemap[addr >> shift] != i) { 
-					printk(KERN_INFO 
-					    "node %d shift %d addr %Lx conflict %d\n", 
-					       i, shift, addr, memnodemap[addr>>shift]);
-					goto next; 
-				} 
-				memnodemap[addr >> shift] = i; 
+	for (i = 0; i < numnodes; i++)
+		if ((nodes[i].start != nodes[i].end) && (nodes[i].end > maxend))
+				maxend = nodes[i].end;
+
+	while ((1UL << shift) <  (maxend / NODEMAPSIZE))
+		shift++;
+
+	printk (KERN_DEBUG"Using %d for the hash shift. Max adder is %lx \n",
+			shift,maxend);
+	memset(memnodemap,0xff,sizeof(*memnodemap) * NODEMAPSIZE);
+	for (i = 0; i < numnodes; i++) {
+		if (nodes[i].start == nodes[i].end)
+			continue;
+		for (addr = nodes[i].start;
+		     addr < nodes[i].end;
+		     addr += (1UL << shift)) {
+			if (memnodemap[addr >> shift] != 0xff) {
+				printk(KERN_INFO
+	"Your memory is not aligned you need to rebuild your kernel "
+	"with a bigger NODEMAPSIZE shift=%d adder=%lu\n",
+					shift,addr);
+				return -1;
 			} 
+			memnodemap[addr >> shift] = i;
 		} 
-		return shift; 
-	next:
-		shift++; 
 	} 
-	memset(memnodemap,0,sizeof(*memnodemap) * NODEMAPSIZE); 
-	return -1; 
+	return shift;
 }
 
 #ifdef CONFIG_SPARSEMEM
diff --git a/arch/x86_64/mm/srat.c b/arch/x86_64/mm/srat.c
index 5d01b31472e..8e3d097a9dd 100644
--- a/arch/x86_64/mm/srat.c
+++ b/arch/x86_64/mm/srat.c
@@ -20,6 +20,9 @@
 
 static struct acpi_table_slit *acpi_slit;
 
+/* Internal processor count */
+static unsigned int __initdata num_processors = 0;
+
 static nodemask_t nodes_parsed __initdata;
 static nodemask_t nodes_found __initdata;
 static struct node nodes[MAX_NUMNODES] __initdata;
@@ -101,16 +104,18 @@ acpi_numa_processor_affinity_init(struct acpi_table_processor_affinity *pa)
 		bad_srat();
 		return;
 	}
-	if (pa->apic_id >= NR_CPUS) {
-		printk(KERN_ERR "SRAT: lapic %u too large.\n",
-		       pa->apic_id);
+	if (num_processors >= NR_CPUS) {
+		printk(KERN_ERR "SRAT: Processor #%d (lapic %u) INVALID. (Max ID: %d).\n",
+			num_processors, pa->apic_id, NR_CPUS);
 		bad_srat();
 		return;
 	}
-	cpu_to_node[pa->apic_id] = node;
+	cpu_to_node[num_processors] = node;
 	acpi_numa = 1;
-	printk(KERN_INFO "SRAT: PXM %u -> APIC %u -> Node %u\n",
-	       pxm, pa->apic_id, node);
+	printk(KERN_INFO "SRAT: PXM %u -> APIC %u -> CPU %u -> Node %u\n",
+	       pxm, pa->apic_id, num_processors, node);
+
+	num_processors++;
 }
 
 /* Callback for parsing of the Proximity Domain <-> Memory Area mappings */
@@ -124,7 +129,6 @@ acpi_numa_memory_affinity_init(struct acpi_table_memory_affinity *ma)
 
 	if (srat_disabled() || ma->flags.enabled == 0)
 		return;
-	/* hotplug bit is ignored for now */
 	pxm = ma->proximity_domain;
 	node = setup_node(pxm);
 	if (node < 0) {
@@ -134,6 +138,10 @@ acpi_numa_memory_affinity_init(struct acpi_table_memory_affinity *ma)
 	}
 	start = ma->base_addr_lo | ((u64)ma->base_addr_hi << 32);
 	end = start + (ma->length_lo | ((u64)ma->length_hi << 32));
+	/* It is fine to add this area to the nodes data it will be used later*/
+	if (ma->flags.hot_pluggable == 1)
+		printk(KERN_INFO "SRAT: hot plug zone found %lx - %lx \n",
+				start, end);
 	i = conflicting_nodes(start, end);
 	if (i >= 0) {
 		printk(KERN_ERR
diff --git a/arch/x86_64/pci/k8-bus.c b/arch/x86_64/pci/k8-bus.c
index 7e7d0c2a002..c2c38b57993 100644
--- a/arch/x86_64/pci/k8-bus.c
+++ b/arch/x86_64/pci/k8-bus.c
@@ -29,7 +29,7 @@ __init static int
 fill_mp_bus_to_cpumask(void)
 {
 	struct pci_dev *nb_dev = NULL;
-	int i, j, printed;
+	int i, j;
 	u32 ldtbus, nid;
 	static int lbnr[3] = {
 		LDT_BUS_NUMBER_REGISTER_0,
diff --git a/crypto/aes.c b/crypto/aes.c
index d0dd7c3c527..5df92888ef5 100644
--- a/crypto/aes.c
+++ b/crypto/aes.c
@@ -67,7 +67,7 @@
 /*
  * #define byte(x, nr) ((unsigned char)((x) >> (nr*8))) 
  */
-inline static u8
+static inline u8
 byte(const u32 x, const unsigned n)
 {
 	return x >> (n << 3);
diff --git a/drivers/acorn/block/fd1772.c b/drivers/acorn/block/fd1772.c
index 3cd2e968e96..c0a37d98b4f 100644
--- a/drivers/acorn/block/fd1772.c
+++ b/drivers/acorn/block/fd1772.c
@@ -1283,8 +1283,7 @@ static void do_fd_request(request_queue_t* q)
 	if (fdc_busy) return;
 	save_flags(flags);
 	cli();
-	while (fdc_busy)
-		sleep_on(&fdc_wait);
+	wait_event(fdc_wait, !fdc_busy);
 	fdc_busy = 1;
 	ENABLE_IRQ();
 	restore_flags(flags);
diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
index 986410e7b48..ba13896cae4 100644
--- a/drivers/acpi/Kconfig
+++ b/drivers/acpi/Kconfig
@@ -133,9 +133,10 @@ config ACPI_HOTKEY
 	depends on ACPI_INTERPRETER
 	depends on EXPERIMENTAL
 	depends on !IA64_SGI_SN
-	default m
+	default n
 	help
-	ACPI generic hotkey
+	  Experimental consolidated hotkey driver.
+	  If you are unsure, say N.
 
 config ACPI_FAN
 	tristate "Fan"
diff --git a/drivers/acpi/button.c b/drivers/acpi/button.c
index 0f45d45f05a..8162fd0c21a 100644
--- a/drivers/acpi/button.c
+++ b/drivers/acpi/button.c
@@ -26,6 +26,9 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/init.h>
+#include <linux/types.h>
+#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
 #include <acpi/acpi_bus.h>
 #include <acpi/acpi_drivers.h>
 
@@ -33,6 +36,9 @@
 #define ACPI_BUTTON_COMPONENT		0x00080000
 #define ACPI_BUTTON_DRIVER_NAME		"ACPI Button Driver"
 #define ACPI_BUTTON_CLASS		"button"
+#define ACPI_BUTTON_FILE_INFO		"info"
+#define ACPI_BUTTON_FILE_STATE		"state"
+#define ACPI_BUTTON_TYPE_UNKNOWN	0x00
 #define ACPI_BUTTON_NOTIFY_STATUS	0x80
 
 #define ACPI_BUTTON_SUBCLASS_POWER	"power"
@@ -64,6 +70,8 @@ MODULE_LICENSE("GPL");
 
 static int acpi_button_add (struct acpi_device *device);
 static int acpi_button_remove (struct acpi_device *device, int type);
+static int acpi_button_info_open_fs(struct inode *inode, struct file *file);
+static int acpi_button_state_open_fs(struct inode *inode, struct file *file);
 
 static struct acpi_driver acpi_button_driver = {
 	.name =		ACPI_BUTTON_DRIVER_NAME,
@@ -82,6 +90,179 @@ struct acpi_button {
 	unsigned long		pushed;
 };
 
+static struct file_operations acpi_button_info_fops = {
+	.open		= acpi_button_info_open_fs,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static struct file_operations acpi_button_state_fops = {
+	.open		= acpi_button_state_open_fs,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+/* --------------------------------------------------------------------------
+                              FS Interface (/proc)
+   -------------------------------------------------------------------------- */
+
+static struct proc_dir_entry	*acpi_button_dir;
+
+static int acpi_button_info_seq_show(struct seq_file *seq, void *offset)
+{
+	struct acpi_button	*button = (struct acpi_button *) seq->private;
+
+	ACPI_FUNCTION_TRACE("acpi_button_info_seq_show");
+
+	if (!button || !button->device)
+		return_VALUE(0);
+
+	seq_printf(seq, "type:                    %s\n", 
+		acpi_device_name(button->device));
+
+	return_VALUE(0);
+}
+
+static int acpi_button_info_open_fs(struct inode *inode, struct file *file)
+{
+	return single_open(file, acpi_button_info_seq_show, PDE(inode)->data);
+}
+	
+static int acpi_button_state_seq_show(struct seq_file *seq, void *offset)
+{
+	struct acpi_button	*button = (struct acpi_button *) seq->private;
+	acpi_status		status;
+	unsigned long		state;
+
+	ACPI_FUNCTION_TRACE("acpi_button_state_seq_show");
+
+	if (!button || !button->device)
+		return_VALUE(0);
+
+	status = acpi_evaluate_integer(button->handle,"_LID",NULL,&state);
+	if (ACPI_FAILURE(status)) {
+		seq_printf(seq, "state:      unsupported\n");
+	}
+	else{
+		seq_printf(seq, "state:      %s\n", (state ? "open" : "closed")); 
+	}
+
+	return_VALUE(0);
+}
+
+static int acpi_button_state_open_fs(struct inode *inode, struct file *file)
+{
+	return single_open(file, acpi_button_state_seq_show, PDE(inode)->data);
+}
+
+static struct proc_dir_entry *acpi_power_dir;
+static struct proc_dir_entry *acpi_sleep_dir;
+static struct proc_dir_entry *acpi_lid_dir;
+
+static int
+acpi_button_add_fs (
+	struct acpi_device	*device)
+{
+	struct proc_dir_entry	*entry = NULL;
+	struct acpi_button	*button = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_button_add_fs");
+
+	if (!device || !acpi_driver_data(device))
+		return_VALUE(-EINVAL);
+
+	button = acpi_driver_data(device);
+
+	switch (button->type) {
+	case ACPI_BUTTON_TYPE_POWER:
+	case ACPI_BUTTON_TYPE_POWERF:
+		if (!acpi_power_dir)
+			acpi_power_dir = proc_mkdir(ACPI_BUTTON_SUBCLASS_POWER, 
+				acpi_button_dir);
+		entry = acpi_power_dir;
+		break;
+	case ACPI_BUTTON_TYPE_SLEEP:
+	case ACPI_BUTTON_TYPE_SLEEPF:
+		if (!acpi_sleep_dir)
+			acpi_sleep_dir = proc_mkdir(ACPI_BUTTON_SUBCLASS_SLEEP, 
+				acpi_button_dir);
+		entry = acpi_sleep_dir;
+		break;
+	case ACPI_BUTTON_TYPE_LID:
+		if (!acpi_lid_dir)
+			acpi_lid_dir = proc_mkdir(ACPI_BUTTON_SUBCLASS_LID, 
+				acpi_button_dir);
+		entry = acpi_lid_dir;
+		break;
+	}
+
+	if (!entry)
+		return_VALUE(-ENODEV);
+	entry->owner = THIS_MODULE;
+
+	acpi_device_dir(device) = proc_mkdir(acpi_device_bid(device), entry);
+	if (!acpi_device_dir(device))
+		return_VALUE(-ENODEV);
+	acpi_device_dir(device)->owner = THIS_MODULE;
+
+	/* 'info' [R] */
+	entry = create_proc_entry(ACPI_BUTTON_FILE_INFO,
+		S_IRUGO, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_BUTTON_FILE_INFO));
+	else {
+		entry->proc_fops = &acpi_button_info_fops;
+		entry->data = acpi_driver_data(device);
+		entry->owner = THIS_MODULE;
+	}
+
+	/* show lid state [R] */
+	if (button->type == ACPI_BUTTON_TYPE_LID) {
+		entry = create_proc_entry(ACPI_BUTTON_FILE_STATE,
+			S_IRUGO, acpi_device_dir(device));
+		if (!entry)
+			ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+				"Unable to create '%s' fs entry\n",
+				ACPI_BUTTON_FILE_INFO));
+		else {
+			entry->proc_fops = &acpi_button_state_fops;
+			entry->data = acpi_driver_data(device);
+			entry->owner = THIS_MODULE;
+		}
+	}
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_button_remove_fs (
+	struct acpi_device	*device)
+{
+	struct acpi_button	*button = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_button_remove_fs");
+
+	button = acpi_driver_data(device);
+	if (acpi_device_dir(device)) {
+		if (button->type == ACPI_BUTTON_TYPE_LID)
+			remove_proc_entry(ACPI_BUTTON_FILE_STATE,
+					     acpi_device_dir(device));
+		remove_proc_entry(ACPI_BUTTON_FILE_INFO,
+				     acpi_device_dir(device));
+
+		remove_proc_entry(acpi_device_bid(device),
+				     acpi_device_dir(device)->parent);
+		acpi_device_dir(device) = NULL;
+	}
+
+	return_VALUE(0);
+}
+
+
 /* --------------------------------------------------------------------------
                                 Driver Interface
    -------------------------------------------------------------------------- */
@@ -121,7 +302,8 @@ acpi_button_notify_fixed (
 	
 	ACPI_FUNCTION_TRACE("acpi_button_notify_fixed");
 
-	BUG_ON(!button);
+	if (!button)
+		return_ACPI_STATUS(AE_BAD_PARAMETER);
 
 	acpi_button_notify(button->handle, ACPI_BUTTON_NOTIFY_STATUS, button);
 
@@ -197,6 +379,10 @@ acpi_button_add (
 		goto end;
 	}
 
+	result = acpi_button_add_fs(device);
+	if (result)
+		goto end;
+
 	switch (button->type) {
 	case ACPI_BUTTON_TYPE_POWERF:
 		status = acpi_install_fixed_event_handler (
@@ -240,6 +426,7 @@ acpi_button_add (
 
 end:
 	if (result) {
+		acpi_button_remove_fs(device);
 		kfree(button);
 	}
 
@@ -280,6 +467,8 @@ acpi_button_remove (struct acpi_device *device, int type)
 		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
 			"Error removing notify handler\n"));
 
+	acpi_button_remove_fs(device);	
+
 	kfree(button);
 
 	return_VALUE(0);
@@ -293,14 +482,20 @@ acpi_button_init (void)
 
 	ACPI_FUNCTION_TRACE("acpi_button_init");
 
+	acpi_button_dir = proc_mkdir(ACPI_BUTTON_CLASS, acpi_root_dir);
+	if (!acpi_button_dir)
+		return_VALUE(-ENODEV);
+	acpi_button_dir->owner = THIS_MODULE;
 	result = acpi_bus_register_driver(&acpi_button_driver);
 	if (result < 0) {
+		remove_proc_entry(ACPI_BUTTON_CLASS, acpi_root_dir);
 		return_VALUE(-ENODEV);
 	}
 
 	return_VALUE(0);
 }
 
+
 static void __exit
 acpi_button_exit (void)
 {
@@ -308,8 +503,17 @@ acpi_button_exit (void)
 
 	acpi_bus_unregister_driver(&acpi_button_driver);
 
+	if (acpi_power_dir) 
+		remove_proc_entry(ACPI_BUTTON_SUBCLASS_POWER, acpi_button_dir);
+	if (acpi_sleep_dir)
+		remove_proc_entry(ACPI_BUTTON_SUBCLASS_SLEEP, acpi_button_dir);
+	if (acpi_lid_dir)
+		remove_proc_entry(ACPI_BUTTON_SUBCLASS_LID, acpi_button_dir);
+	remove_proc_entry(ACPI_BUTTON_CLASS, acpi_root_dir);
+
 	return_VOID;
 }
 
+
 module_init(acpi_button_init);
 module_exit(acpi_button_exit);
diff --git a/drivers/acpi/dispatcher/dswload.c b/drivers/acpi/dispatcher/dswload.c
index 1ac197ccfc8..d1162001842 100644
--- a/drivers/acpi/dispatcher/dswload.c
+++ b/drivers/acpi/dispatcher/dswload.c
@@ -491,12 +491,6 @@ acpi_ds_load2_begin_op (
 		if ((!(walk_state->op_info->flags & AML_NSOPCODE) &&
 			  (walk_state->opcode != AML_INT_NAMEPATH_OP)) ||
 			(!(walk_state->op_info->flags & AML_NAMED))) {
-			if ((walk_state->op_info->class == AML_CLASS_EXECUTE) ||
-				(walk_state->op_info->class == AML_CLASS_CONTROL)) {
-				ACPI_REPORT_WARNING ((
-					"Encountered executable code at module level, [%s]\n",
-					acpi_ps_get_opcode_name (walk_state->opcode)));
-			}
 			return_ACPI_STATUS (AE_OK);
 		}
 
diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c
index fca4140a50a..1ac5731d45e 100644
--- a/drivers/acpi/ec.c
+++ b/drivers/acpi/ec.c
@@ -59,76 +59,186 @@ ACPI_MODULE_NAME		("acpi_ec")
 #define ACPI_EC_DELAY		50	/* Wait 50ms max. during EC ops */
 #define ACPI_EC_UDELAY_GLK	1000	/* Wait 1ms max. to get global lock */
 
+#define ACPI_EC_UDELAY         100     /* Poll @ 100us increments */
+#define ACPI_EC_UDELAY_COUNT   1000    /* Wait 10ms max. during EC ops */
+
 #define ACPI_EC_COMMAND_READ	0x80
 #define ACPI_EC_COMMAND_WRITE	0x81
 #define ACPI_EC_BURST_ENABLE	0x82
 #define ACPI_EC_BURST_DISABLE	0x83
 #define ACPI_EC_COMMAND_QUERY	0x84
 
-static int acpi_ec_add (struct acpi_device *device);
+#define EC_POLLING		0xFF
+#define EC_BURST		0x00
+
+
 static int acpi_ec_remove (struct acpi_device *device, int type);
 static int acpi_ec_start (struct acpi_device *device);
 static int acpi_ec_stop (struct acpi_device *device, int type);
+static int acpi_ec_burst_add ( struct acpi_device *device);
+static int acpi_ec_polling_add ( struct acpi_device	*device);
 
 static struct acpi_driver acpi_ec_driver = {
 	.name =		ACPI_EC_DRIVER_NAME,
 	.class =	ACPI_EC_CLASS,
 	.ids =		ACPI_EC_HID,
 	.ops =		{
-				.add =		acpi_ec_add,
+				.add =		acpi_ec_polling_add,
 				.remove =	acpi_ec_remove,
 				.start =	acpi_ec_start,
 				.stop =		acpi_ec_stop,
 			},
 };
-
-struct acpi_ec {
-	acpi_handle			handle;
-	unsigned long			uid;
-	unsigned long			gpe_bit;
-	struct acpi_generic_address	status_addr;
-	struct acpi_generic_address	command_addr;
-	struct acpi_generic_address	data_addr;
-	unsigned long			global_lock;
-	unsigned int			expect_event;
-	atomic_t			leaving_burst; /* 0 : No, 1 : Yes, 2: abort*/
-	atomic_t			pending_gpe;
-	struct semaphore		sem;
-	wait_queue_head_t		wait;
+union acpi_ec {
+	struct {
+		u32				mode;
+		acpi_handle			handle;
+		unsigned long			uid;
+		unsigned long			gpe_bit;
+		struct acpi_generic_address	status_addr;
+		struct acpi_generic_address	command_addr;
+		struct acpi_generic_address	data_addr;
+		unsigned long			global_lock;
+	} common;
+
+	struct {
+		u32				mode;
+		acpi_handle			handle;
+		unsigned long			uid;
+		unsigned long			gpe_bit;
+		struct acpi_generic_address	status_addr;
+		struct acpi_generic_address	command_addr;
+		struct acpi_generic_address	data_addr;
+		unsigned long			global_lock;
+		unsigned int			expect_event;
+		atomic_t			leaving_burst; /* 0 : No, 1 : Yes, 2: abort*/
+		atomic_t			pending_gpe;
+		struct semaphore		sem;
+		wait_queue_head_t		wait;
+	}burst;
+
+	struct {
+		u32				mode;
+		acpi_handle			handle;
+		unsigned long			uid;
+		unsigned long			gpe_bit;
+		struct acpi_generic_address	status_addr;
+		struct acpi_generic_address	command_addr;
+		struct acpi_generic_address	data_addr;
+		unsigned long			global_lock;
+       		spinlock_t                      lock;
+	}polling;
 };
 
+static int acpi_ec_polling_wait ( union acpi_ec *ec, u8 event); 
+static int acpi_ec_burst_wait(union acpi_ec *ec, unsigned int event);
+static int acpi_ec_polling_read ( union acpi_ec *ec, u8 address, u32 *data);
+static int acpi_ec_burst_read( union acpi_ec *ec, u8 address, u32 *data);
+static int acpi_ec_polling_write ( union acpi_ec *ec, u8 address, u8 data);
+static int acpi_ec_burst_write ( union acpi_ec *ec, u8 address, u8 data);
+static int acpi_ec_polling_query ( union acpi_ec *ec, u32 *data);
+static int acpi_ec_burst_query ( union acpi_ec *ec, u32 *data);
+static void acpi_ec_gpe_polling_query ( void *ec_cxt);
+static void acpi_ec_gpe_burst_query ( void *ec_cxt);
+static u32 acpi_ec_gpe_polling_handler ( void *data);
+static u32 acpi_ec_gpe_burst_handler ( void *data);
+static acpi_status __init
+acpi_fake_ecdt_polling_callback (
+	acpi_handle	handle,
+	u32		Level,
+	void		*context,
+	void		**retval);
+
+static acpi_status __init
+acpi_fake_ecdt_burst_callback (
+	acpi_handle	handle,
+	u32		Level,
+	void		*context,
+	void		**retval);
+
+static int __init
+acpi_ec_polling_get_real_ecdt(void);
+static int __init
+acpi_ec_burst_get_real_ecdt(void);
 /* If we find an EC via the ECDT, we need to keep a ptr to its context */
-static struct acpi_ec	*ec_ecdt;
+static union acpi_ec	*ec_ecdt;
 
 /* External interfaces use first EC only, so remember */
 static struct acpi_device *first_ec;
+static int acpi_ec_polling_mode = EC_POLLING;
 
 /* --------------------------------------------------------------------------
                              Transaction Management
    -------------------------------------------------------------------------- */
 
-static inline u32 acpi_ec_read_status(struct acpi_ec *ec)
+static inline u32 acpi_ec_read_status(union acpi_ec *ec)
 {
 	u32	status = 0;
 
-	acpi_hw_low_level_read(8, &status, &ec->status_addr);
+	acpi_hw_low_level_read(8, &status, &ec->common.status_addr);
 	return status;
 }
 
-static int acpi_ec_wait(struct acpi_ec *ec, unsigned int event)
+static int
+acpi_ec_wait (
+	union acpi_ec		*ec,
+	u8			event)
+{
+	if (acpi_ec_polling_mode) 
+		return acpi_ec_polling_wait (ec, event);
+	else
+		return acpi_ec_burst_wait (ec, event);
+}
+
+static int
+acpi_ec_polling_wait (
+	union acpi_ec		*ec,
+	u8			event)
+{
+	u32			acpi_ec_status = 0;
+	u32			i = ACPI_EC_UDELAY_COUNT;
+
+	if (!ec)
+		return -EINVAL;
+
+	/* Poll the EC status register waiting for the event to occur. */
+	switch (event) {
+	case ACPI_EC_EVENT_OBF:
+		do {
+			acpi_hw_low_level_read(8, &acpi_ec_status, &ec->common.status_addr);
+			if (acpi_ec_status & ACPI_EC_FLAG_OBF)
+				return 0;
+			udelay(ACPI_EC_UDELAY);
+		} while (--i>0);
+		break;
+	case ACPI_EC_EVENT_IBE:
+		do {
+			acpi_hw_low_level_read(8, &acpi_ec_status, &ec->common.status_addr);
+			if (!(acpi_ec_status & ACPI_EC_FLAG_IBF))
+				return 0;
+			udelay(ACPI_EC_UDELAY);
+		} while (--i>0);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return -ETIME;
+}
+static int acpi_ec_burst_wait(union acpi_ec *ec, unsigned int event)
 {
 	int	result = 0;
 
 	ACPI_FUNCTION_TRACE("acpi_ec_wait");
 
-	ec->expect_event = event;
+	ec->burst.expect_event = event;
 	smp_mb();
 
-	result = wait_event_interruptible_timeout(ec->wait,
-					!ec->expect_event,
+	result = wait_event_interruptible_timeout(ec->burst.wait,
+					!ec->burst.expect_event,
 					msecs_to_jiffies(ACPI_EC_DELAY));
 	
-	ec->expect_event = 0;
+	ec->burst.expect_event = 0;
 	smp_mb();
 
 	if (result < 0){
@@ -160,7 +270,7 @@ static int acpi_ec_wait(struct acpi_ec *ec, unsigned int event)
 
 static int
 acpi_ec_enter_burst_mode (
-	struct acpi_ec		*ec)
+	union acpi_ec		*ec)
 {
 	u32			tmp = 0;
 	int			status = 0;
@@ -170,43 +280,43 @@ acpi_ec_enter_burst_mode (
 	status = acpi_ec_read_status(ec);
 	if (status != -EINVAL &&
 		!(status & ACPI_EC_FLAG_BURST)){
-		acpi_hw_low_level_write(8, ACPI_EC_BURST_ENABLE, &ec->command_addr);
+		acpi_hw_low_level_write(8, ACPI_EC_BURST_ENABLE, &ec->common.command_addr);
 		status = acpi_ec_wait(ec, ACPI_EC_EVENT_OBF);
 		if (status){
-			acpi_enable_gpe(NULL, ec->gpe_bit, ACPI_NOT_ISR);
+			acpi_enable_gpe(NULL, ec->common.gpe_bit, ACPI_NOT_ISR);
 			return_VALUE(-EINVAL);
 		}
-		acpi_hw_low_level_read(8, &tmp, &ec->data_addr);
-		acpi_enable_gpe(NULL, ec->gpe_bit, ACPI_NOT_ISR);
+		acpi_hw_low_level_read(8, &tmp, &ec->common.data_addr);
+		acpi_enable_gpe(NULL, ec->common.gpe_bit, ACPI_NOT_ISR);
 		if(tmp != 0x90 ) {/* Burst ACK byte*/
 			return_VALUE(-EINVAL);
 		}
 	}
 
-	atomic_set(&ec->leaving_burst , 0);
+	atomic_set(&ec->burst.leaving_burst , 0);
 	return_VALUE(0);
 }
 
 static int
 acpi_ec_leave_burst_mode (
-	struct acpi_ec		*ec)
+	union acpi_ec		*ec)
 {
 	int			status =0;
 
 	ACPI_FUNCTION_TRACE("acpi_ec_leave_burst_mode");
 
-	atomic_set(&ec->leaving_burst , 1);
+	atomic_set(&ec->burst.leaving_burst , 1);
 	status = acpi_ec_read_status(ec);
 	if (status != -EINVAL &&
 		(status & ACPI_EC_FLAG_BURST)){
-		acpi_hw_low_level_write(8, ACPI_EC_BURST_DISABLE, &ec->command_addr);
+		acpi_hw_low_level_write(8, ACPI_EC_BURST_DISABLE, &ec->common.command_addr);
 		status = acpi_ec_wait(ec, ACPI_EC_FLAG_IBF);
 		if (status){
-			acpi_enable_gpe(NULL, ec->gpe_bit, ACPI_NOT_ISR);
+			acpi_enable_gpe(NULL, ec->common.gpe_bit, ACPI_NOT_ISR);
 			ACPI_DEBUG_PRINT((ACPI_DB_ERROR,"------->wait fail\n"));
 			return_VALUE(-EINVAL);
 		}
-		acpi_enable_gpe(NULL, ec->gpe_bit, ACPI_NOT_ISR);
+		acpi_enable_gpe(NULL, ec->common.gpe_bit, ACPI_NOT_ISR);
 		status = acpi_ec_read_status(ec);
 	}
 
@@ -215,7 +325,131 @@ acpi_ec_leave_burst_mode (
 
 static int
 acpi_ec_read (
-	struct acpi_ec		*ec,
+	union acpi_ec		*ec,
+	u8			address,
+	u32			*data)
+{
+	if (acpi_ec_polling_mode) 
+		return acpi_ec_polling_read(ec, address, data);
+	else
+		return acpi_ec_burst_read(ec, address, data);
+}
+static int
+acpi_ec_write (
+	union acpi_ec		*ec,
+	u8			address,
+	u8			data)
+{
+	if (acpi_ec_polling_mode) 
+		return acpi_ec_polling_write(ec, address, data);
+	else
+		return acpi_ec_burst_write(ec, address, data);
+}
+static int
+acpi_ec_polling_read (
+	union acpi_ec		*ec,
+	u8			address,
+	u32			*data)
+{
+	acpi_status		status = AE_OK;
+	int			result = 0;
+	unsigned long		flags = 0;
+	u32			glk = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_ec_read");
+
+	if (!ec || !data)
+		return_VALUE(-EINVAL);
+
+	*data = 0;
+
+	if (ec->common.global_lock) {
+		status = acpi_acquire_global_lock(ACPI_EC_UDELAY_GLK, &glk);
+		if (ACPI_FAILURE(status))
+			return_VALUE(-ENODEV);
+	}
+
+	spin_lock_irqsave(&ec->polling.lock, flags);
+
+	acpi_hw_low_level_write(8, ACPI_EC_COMMAND_READ, &ec->common.command_addr);
+	result = acpi_ec_wait(ec, ACPI_EC_EVENT_IBE);
+	if (result)
+		goto end;
+
+	acpi_hw_low_level_write(8, address, &ec->common.data_addr);
+	result = acpi_ec_wait(ec, ACPI_EC_EVENT_OBF);
+	if (result)
+		goto end;
+
+	acpi_hw_low_level_read(8, data, &ec->common.data_addr);
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Read [%02x] from address [%02x]\n",
+		*data, address));
+	
+end:
+	spin_unlock_irqrestore(&ec->polling.lock, flags);
+
+	if (ec->common.global_lock)
+		acpi_release_global_lock(glk);
+
+	return_VALUE(result);
+}
+
+
+static int
+acpi_ec_polling_write (
+	union acpi_ec		*ec,
+	u8			address,
+	u8			data)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	unsigned long		flags = 0;
+	u32			glk = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_ec_write");
+
+	if (!ec)
+		return_VALUE(-EINVAL);
+
+	if (ec->common.global_lock) {
+		status = acpi_acquire_global_lock(ACPI_EC_UDELAY_GLK, &glk);
+		if (ACPI_FAILURE(status))
+			return_VALUE(-ENODEV);
+	}
+
+	spin_lock_irqsave(&ec->polling.lock, flags);
+
+	acpi_hw_low_level_write(8, ACPI_EC_COMMAND_WRITE, &ec->common.command_addr);
+	result = acpi_ec_wait(ec, ACPI_EC_EVENT_IBE);
+	if (result)
+		goto end;
+
+	acpi_hw_low_level_write(8, address, &ec->common.data_addr);
+	result = acpi_ec_wait(ec, ACPI_EC_EVENT_IBE);
+	if (result)
+		goto end;
+
+	acpi_hw_low_level_write(8, data, &ec->common.data_addr);
+	result = acpi_ec_wait(ec, ACPI_EC_EVENT_IBE);
+	if (result)
+		goto end;
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Wrote [%02x] to address [%02x]\n",
+		data, address));
+
+end:
+	spin_unlock_irqrestore(&ec->polling.lock, flags);
+
+	if (ec->common.global_lock)
+		acpi_release_global_lock(glk);
+
+	return_VALUE(result);
+}
+
+static int
+acpi_ec_burst_read (
+	union acpi_ec		*ec,
 	u8			address,
 	u32			*data)
 {
@@ -230,51 +464,51 @@ acpi_ec_read (
 retry:
 	*data = 0;
 
-	if (ec->global_lock) {
+	if (ec->common.global_lock) {
 		status = acpi_acquire_global_lock(ACPI_EC_UDELAY_GLK, &glk);
 		if (ACPI_FAILURE(status))
 			return_VALUE(-ENODEV);
 	}
 
 	WARN_ON(in_interrupt());
-	down(&ec->sem);
+	down(&ec->burst.sem);
 
 	if(acpi_ec_enter_burst_mode(ec))
 		goto end;
 
-	acpi_hw_low_level_write(8, ACPI_EC_COMMAND_READ, &ec->command_addr);
+	acpi_hw_low_level_write(8, ACPI_EC_COMMAND_READ, &ec->common.command_addr);
 	status = acpi_ec_wait(ec, ACPI_EC_EVENT_IBE);
-	acpi_enable_gpe(NULL, ec->gpe_bit, ACPI_NOT_ISR);
+	acpi_enable_gpe(NULL, ec->common.gpe_bit, ACPI_NOT_ISR);
 	if (status) {
 		goto end;
 	}
 
-	acpi_hw_low_level_write(8, address, &ec->data_addr);
+	acpi_hw_low_level_write(8, address, &ec->common.data_addr);
 	status= acpi_ec_wait(ec, ACPI_EC_EVENT_OBF);
 	if (status){
-		acpi_enable_gpe(NULL, ec->gpe_bit, ACPI_NOT_ISR);
+		acpi_enable_gpe(NULL, ec->common.gpe_bit, ACPI_NOT_ISR);
 		goto end;
 	}
 
-	acpi_hw_low_level_read(8, data, &ec->data_addr);
-	acpi_enable_gpe(NULL, ec->gpe_bit, ACPI_NOT_ISR);
+	acpi_hw_low_level_read(8, data, &ec->common.data_addr);
+	acpi_enable_gpe(NULL, ec->common.gpe_bit, ACPI_NOT_ISR);
 
 	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Read [%02x] from address [%02x]\n",
 		*data, address));
 	
 end:
 	acpi_ec_leave_burst_mode(ec);
-	up(&ec->sem);
+	up(&ec->burst.sem);
 
-	if (ec->global_lock)
+	if (ec->common.global_lock)
 		acpi_release_global_lock(glk);
 
-	if(atomic_read(&ec->leaving_burst) == 2){
+	if(atomic_read(&ec->burst.leaving_burst) == 2){
 		ACPI_DEBUG_PRINT((ACPI_DB_INFO,"aborted, retry ...\n"));
-		while(atomic_read(&ec->pending_gpe)){
+		while(atomic_read(&ec->burst.pending_gpe)){
 			msleep(1);	
 		}
-		acpi_enable_gpe(NULL, ec->gpe_bit, ACPI_NOT_ISR);
+		acpi_enable_gpe(NULL, ec->common.gpe_bit, ACPI_NOT_ISR);
 		goto retry;
 	}
 
@@ -283,8 +517,8 @@ end:
 
 
 static int
-acpi_ec_write (
-	struct acpi_ec		*ec,
+acpi_ec_burst_write (
+	union acpi_ec		*ec,
 	u8			address,
 	u8			data)
 {
@@ -297,14 +531,14 @@ acpi_ec_write (
 	if (!ec)
 		return_VALUE(-EINVAL);
 retry:
-	if (ec->global_lock) {
+	if (ec->common.global_lock) {
 		status = acpi_acquire_global_lock(ACPI_EC_UDELAY_GLK, &glk);
 		if (ACPI_FAILURE(status))
 			return_VALUE(-ENODEV);
 	}
 
 	WARN_ON(in_interrupt());
-	down(&ec->sem);
+	down(&ec->burst.sem);
 
 	if(acpi_ec_enter_burst_mode(ec))
 		goto end;
@@ -312,33 +546,33 @@ retry:
 	status = acpi_ec_read_status(ec);
 	if (status != -EINVAL &&
 		!(status & ACPI_EC_FLAG_BURST)){
-		acpi_hw_low_level_write(8, ACPI_EC_BURST_ENABLE, &ec->command_addr);
+		acpi_hw_low_level_write(8, ACPI_EC_BURST_ENABLE, &ec->common.command_addr);
 		status = acpi_ec_wait(ec, ACPI_EC_EVENT_OBF);
 		if (status)
 			goto end;
-		acpi_hw_low_level_read(8, &tmp, &ec->data_addr);
+		acpi_hw_low_level_read(8, &tmp, &ec->common.data_addr);
 		if(tmp != 0x90 ) /* Burst ACK byte*/
 			goto end;
 	}
 	/*Now we are in burst mode*/
 
-	acpi_hw_low_level_write(8, ACPI_EC_COMMAND_WRITE, &ec->command_addr);
+	acpi_hw_low_level_write(8, ACPI_EC_COMMAND_WRITE, &ec->common.command_addr);
 	status = acpi_ec_wait(ec, ACPI_EC_EVENT_IBE);
-	acpi_enable_gpe(NULL, ec->gpe_bit, ACPI_NOT_ISR);
+	acpi_enable_gpe(NULL, ec->common.gpe_bit, ACPI_NOT_ISR);
 	if (status){
 		goto end;
 	}
 
-	acpi_hw_low_level_write(8, address, &ec->data_addr);
+	acpi_hw_low_level_write(8, address, &ec->common.data_addr);
 	status = acpi_ec_wait(ec, ACPI_EC_EVENT_IBE);
 	if (status){
-		acpi_enable_gpe(NULL, ec->gpe_bit, ACPI_NOT_ISR);
+		acpi_enable_gpe(NULL, ec->common.gpe_bit, ACPI_NOT_ISR);
 		goto end;
 	}
 
-	acpi_hw_low_level_write(8, data, &ec->data_addr);
+	acpi_hw_low_level_write(8, data, &ec->common.data_addr);
 	status = acpi_ec_wait(ec, ACPI_EC_EVENT_IBE);
-	acpi_enable_gpe(NULL, ec->gpe_bit, ACPI_NOT_ISR);
+	acpi_enable_gpe(NULL, ec->common.gpe_bit, ACPI_NOT_ISR);
 	if (status)
 		goto end;
 
@@ -347,17 +581,17 @@ retry:
 
 end:
 	acpi_ec_leave_burst_mode(ec);
-	up(&ec->sem);
+	up(&ec->burst.sem);
 
-	if (ec->global_lock)
+	if (ec->common.global_lock)
 		acpi_release_global_lock(glk);
 
-	if(atomic_read(&ec->leaving_burst) == 2){
+	if(atomic_read(&ec->burst.leaving_burst) == 2){
 		ACPI_DEBUG_PRINT((ACPI_DB_INFO,"aborted, retry ...\n"));
-		while(atomic_read(&ec->pending_gpe)){
+		while(atomic_read(&ec->burst.pending_gpe)){
 			msleep(1);	
 		}
-		acpi_enable_gpe(NULL, ec->gpe_bit, ACPI_NOT_ISR);
+		acpi_enable_gpe(NULL, ec->common.gpe_bit, ACPI_NOT_ISR);
 		goto retry;
 	}
 
@@ -370,7 +604,7 @@ end:
 int
 ec_read(u8 addr, u8 *val)
 {
-	struct acpi_ec *ec;
+	union acpi_ec *ec;
 	int err;
 	u32 temp_data;
 
@@ -393,7 +627,7 @@ EXPORT_SYMBOL(ec_read);
 int
 ec_write(u8 addr, u8 val)
 {
-	struct acpi_ec *ec;
+	union acpi_ec *ec;
 	int err;
 
 	if (!first_ec)
@@ -407,10 +641,66 @@ ec_write(u8 addr, u8 val)
 }
 EXPORT_SYMBOL(ec_write);
 
-
 static int
 acpi_ec_query (
-	struct acpi_ec		*ec,
+	union acpi_ec		*ec,
+	u32			*data)
+{
+	if (acpi_ec_polling_mode) 
+		return acpi_ec_polling_query(ec, data);
+	else
+		return acpi_ec_burst_query(ec, data);
+}
+static int
+acpi_ec_polling_query (
+	union acpi_ec		*ec,
+	u32			*data)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	unsigned long		flags = 0;
+	u32			glk = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_ec_query");
+
+	if (!ec || !data)
+		return_VALUE(-EINVAL);
+
+	*data = 0;
+
+	if (ec->common.global_lock) {
+		status = acpi_acquire_global_lock(ACPI_EC_UDELAY_GLK, &glk);
+		if (ACPI_FAILURE(status))
+			return_VALUE(-ENODEV);
+	}
+
+	/*
+	 * Query the EC to find out which _Qxx method we need to evaluate.
+	 * Note that successful completion of the query causes the ACPI_EC_SCI
+	 * bit to be cleared (and thus clearing the interrupt source).
+	 */
+	spin_lock_irqsave(&ec->polling.lock, flags);
+
+	acpi_hw_low_level_write(8, ACPI_EC_COMMAND_QUERY, &ec->common.command_addr);
+	result = acpi_ec_wait(ec, ACPI_EC_EVENT_OBF);
+	if (result)
+		goto end;
+
+	acpi_hw_low_level_read(8, data, &ec->common.data_addr);
+	if (!*data)
+		result = -ENODATA;
+
+end:
+	spin_unlock_irqrestore(&ec->polling.lock, flags);
+
+	if (ec->common.global_lock)
+		acpi_release_global_lock(glk);
+
+	return_VALUE(result);
+}
+static int
+acpi_ec_burst_query (
+	union acpi_ec		*ec,
 	u32			*data)
 {
 	int			status = 0;
@@ -422,13 +712,13 @@ acpi_ec_query (
 		return_VALUE(-EINVAL);
 	*data = 0;
 
-	if (ec->global_lock) {
+	if (ec->common.global_lock) {
 		status = acpi_acquire_global_lock(ACPI_EC_UDELAY_GLK, &glk);
 		if (ACPI_FAILURE(status))
 			return_VALUE(-ENODEV);
 	}
 
-	down(&ec->sem);
+	down(&ec->burst.sem);
 	if(acpi_ec_enter_burst_mode(ec))
 		goto end;
 	/*
@@ -436,28 +726,28 @@ acpi_ec_query (
 	 * Note that successful completion of the query causes the ACPI_EC_SCI
 	 * bit to be cleared (and thus clearing the interrupt source).
 	 */
-	acpi_hw_low_level_write(8, ACPI_EC_COMMAND_QUERY, &ec->command_addr);
+	acpi_hw_low_level_write(8, ACPI_EC_COMMAND_QUERY, &ec->common.command_addr);
 	status = acpi_ec_wait(ec, ACPI_EC_EVENT_OBF);
 	if (status){
-		acpi_enable_gpe(NULL, ec->gpe_bit, ACPI_NOT_ISR);
+		acpi_enable_gpe(NULL, ec->common.gpe_bit, ACPI_NOT_ISR);
 		goto end;
 	}
 
-	acpi_hw_low_level_read(8, data, &ec->data_addr);
-	acpi_enable_gpe(NULL, ec->gpe_bit, ACPI_NOT_ISR);
+	acpi_hw_low_level_read(8, data, &ec->common.data_addr);
+	acpi_enable_gpe(NULL, ec->common.gpe_bit, ACPI_NOT_ISR);
 	if (!*data)
 		status = -ENODATA;
 
 end:
 	acpi_ec_leave_burst_mode(ec);
-	up(&ec->sem);
+	up(&ec->burst.sem);
 
-	if (ec->global_lock)
+	if (ec->common.global_lock)
 		acpi_release_global_lock(glk);
 
-	if(atomic_read(&ec->leaving_burst) == 2){
+	if(atomic_read(&ec->burst.leaving_burst) == 2){
 		ACPI_DEBUG_PRINT((ACPI_DB_INFO,"aborted, retry ...\n"));
-		acpi_enable_gpe(NULL, ec->gpe_bit, ACPI_NOT_ISR);
+		acpi_enable_gpe(NULL, ec->common.gpe_bit, ACPI_NOT_ISR);
 		status = -ENODATA;
 	}
 	return_VALUE(status);
@@ -468,7 +758,7 @@ end:
                                 Event Management
    -------------------------------------------------------------------------- */
 
-struct acpi_ec_query_data {
+union acpi_ec_query_data {
 	acpi_handle		handle;
 	u8			data;
 };
@@ -477,7 +767,59 @@ static void
 acpi_ec_gpe_query (
 	void			*ec_cxt)
 {
-	struct acpi_ec		*ec = (struct acpi_ec *) ec_cxt;
+	if (acpi_ec_polling_mode) 
+		acpi_ec_gpe_polling_query(ec_cxt);
+	else
+		acpi_ec_gpe_burst_query(ec_cxt);
+}
+
+static void
+acpi_ec_gpe_polling_query (
+	void			*ec_cxt)
+{
+	union acpi_ec		*ec = (union acpi_ec *) ec_cxt;
+	u32			value = 0;
+	unsigned long		flags = 0;
+	static char		object_name[5] = {'_','Q','0','0','\0'};
+	const char		hex[] = {'0','1','2','3','4','5','6','7',
+				         '8','9','A','B','C','D','E','F'};
+
+	ACPI_FUNCTION_TRACE("acpi_ec_gpe_query");
+
+	if (!ec_cxt)
+		goto end;
+
+	spin_lock_irqsave(&ec->polling.lock, flags);
+	acpi_hw_low_level_read(8, &value, &ec->common.command_addr);
+	spin_unlock_irqrestore(&ec->polling.lock, flags);
+
+	/* TBD: Implement asynch events!
+	 * NOTE: All we care about are EC-SCI's.  Other EC events are
+	 * handled via polling (yuck!).  This is because some systems
+	 * treat EC-SCIs as level (versus EDGE!) triggered, preventing
+	 *  a purely interrupt-driven approach (grumble, grumble).
+	 */
+	if (!(value & ACPI_EC_FLAG_SCI))
+		goto end;
+
+	if (acpi_ec_query(ec, &value))
+		goto end;
+
+	object_name[2] = hex[((value >> 4) & 0x0F)];
+	object_name[3] = hex[(value & 0x0F)];
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Evaluating %s\n", object_name));
+
+	acpi_evaluate_object(ec->common.handle, object_name, NULL, NULL);
+
+end:	
+	acpi_enable_gpe(NULL, ec->common.gpe_bit, ACPI_NOT_ISR);
+}
+static void
+acpi_ec_gpe_burst_query (
+	void			*ec_cxt)
+{
+	union acpi_ec		*ec = (union acpi_ec *) ec_cxt;
 	u32			value;
 	int			result = -ENODATA;
 	static char		object_name[5] = {'_','Q','0','0','\0'};
@@ -497,9 +839,9 @@ acpi_ec_gpe_query (
 
 	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Evaluating %s\n", object_name));
 
-	acpi_evaluate_object(ec->handle, object_name, NULL, NULL);
+	acpi_evaluate_object(ec->common.handle, object_name, NULL, NULL);
 end:	
-	atomic_dec(&ec->pending_gpe);
+	atomic_dec(&ec->burst.pending_gpe);
 	return;
 }
 
@@ -507,48 +849,77 @@ static u32
 acpi_ec_gpe_handler (
 	void			*data)
 {
+	if (acpi_ec_polling_mode) 
+		return acpi_ec_gpe_polling_handler(data);
+	else
+		return acpi_ec_gpe_burst_handler(data);	
+}
+static u32
+acpi_ec_gpe_polling_handler (
+	void			*data)
+{
+	acpi_status		status = AE_OK;
+	union acpi_ec		*ec = (union acpi_ec *) data;
+
+	if (!ec)
+		return ACPI_INTERRUPT_NOT_HANDLED;
+
+	acpi_disable_gpe(NULL, ec->common.gpe_bit, ACPI_ISR);
+
+	status = acpi_os_queue_for_execution(OSD_PRIORITY_GPE,
+		acpi_ec_gpe_query, ec);
+
+	if (status == AE_OK)
+		return ACPI_INTERRUPT_HANDLED;
+	else
+		return ACPI_INTERRUPT_NOT_HANDLED;
+}
+static u32
+acpi_ec_gpe_burst_handler (
+	void			*data)
+{
 	acpi_status		status = AE_OK;
 	u32			value;
-	struct acpi_ec		*ec = (struct acpi_ec *) data;
+	union acpi_ec		*ec = (union acpi_ec *) data;
 
 	if (!ec)
 		return ACPI_INTERRUPT_NOT_HANDLED;
 
-	acpi_disable_gpe(NULL, ec->gpe_bit, ACPI_ISR);
+	acpi_disable_gpe(NULL, ec->common.gpe_bit, ACPI_ISR);
 
 	value = acpi_ec_read_status(ec);
 
 	if((value & ACPI_EC_FLAG_IBF) &&
 		!(value & ACPI_EC_FLAG_BURST) &&
-			(atomic_read(&ec->leaving_burst) == 0)) { 
+			(atomic_read(&ec->burst.leaving_burst) == 0)) { 
 	/*
 	 * the embedded controller disables 
 	 * burst mode for any reason other 
 	 * than the burst disable command
 	 * to process critical event.
 	 */
-		atomic_set(&ec->leaving_burst , 2); /* block current pending transaction
+		atomic_set(&ec->burst.leaving_burst , 2); /* block current pending transaction
 					and retry */
-		wake_up(&ec->wait);
+		wake_up(&ec->burst.wait);
 	}else {
-		if ((ec->expect_event == ACPI_EC_EVENT_OBF &&
+		if ((ec->burst.expect_event == ACPI_EC_EVENT_OBF &&
 				(value & ACPI_EC_FLAG_OBF)) ||
-	    			(ec->expect_event == ACPI_EC_EVENT_IBE &&
+	    			(ec->burst.expect_event == ACPI_EC_EVENT_IBE &&
 				!(value & ACPI_EC_FLAG_IBF))) {
-			ec->expect_event = 0;
-			wake_up(&ec->wait);
+			ec->burst.expect_event = 0;
+			wake_up(&ec->burst.wait);
 			return ACPI_INTERRUPT_HANDLED;
 		}
 	}
 
 	if (value & ACPI_EC_FLAG_SCI){
-		atomic_add(1, &ec->pending_gpe) ;
+		atomic_add(1, &ec->burst.pending_gpe) ;
 		status = acpi_os_queue_for_execution(OSD_PRIORITY_GPE,
 						acpi_ec_gpe_query, ec);
 		return status == AE_OK ?
 		ACPI_INTERRUPT_HANDLED : ACPI_INTERRUPT_NOT_HANDLED;
 	} 
-	acpi_enable_gpe(NULL, ec->gpe_bit, ACPI_ISR);
+	acpi_enable_gpe(NULL, ec->common.gpe_bit, ACPI_ISR);
 	return status == AE_OK ?
 		ACPI_INTERRUPT_HANDLED : ACPI_INTERRUPT_NOT_HANDLED;
 }
@@ -585,7 +956,7 @@ acpi_ec_space_handler (
 	void			*region_context)
 {
 	int			result = 0;
-	struct acpi_ec		*ec = NULL;
+	union acpi_ec		*ec = NULL;
 	u64			temp = *value;
 	acpi_integer		f_v = 0;
 	int 			i = 0;
@@ -600,7 +971,7 @@ acpi_ec_space_handler (
 		return_VALUE(AE_BAD_PARAMETER);
 	}
 
-	ec = (struct acpi_ec *) handler_context;
+	ec = (union acpi_ec *) handler_context;
 
 next_byte:
 	switch (function) {
@@ -661,7 +1032,7 @@ static struct proc_dir_entry	*acpi_ec_dir;
 static int
 acpi_ec_read_info (struct seq_file *seq, void *offset)
 {
-	struct acpi_ec		*ec = (struct acpi_ec *) seq->private;
+	union acpi_ec		*ec = (union acpi_ec *) seq->private;
 
 	ACPI_FUNCTION_TRACE("acpi_ec_read_info");
 
@@ -669,12 +1040,12 @@ acpi_ec_read_info (struct seq_file *seq, void *offset)
 		goto end;
 
 	seq_printf(seq, "gpe bit:                 0x%02x\n",
-		(u32) ec->gpe_bit);
+		(u32) ec->common.gpe_bit);
 	seq_printf(seq, "ports:                   0x%02x, 0x%02x\n",
-		(u32) ec->status_addr.address, (u32) ec->data_addr.address);
+		(u32) ec->common.status_addr.address, (u32) ec->common.data_addr.address);
 	seq_printf(seq, "use global lock:         %s\n",
-		ec->global_lock?"yes":"no");
-	acpi_enable_gpe(NULL, ec->gpe_bit, ACPI_NOT_ISR);
+		ec->common.global_lock?"yes":"no");
+	acpi_enable_gpe(NULL, ec->common.gpe_bit, ACPI_NOT_ISR);
 
 end:
 	return_VALUE(0);
@@ -697,7 +1068,7 @@ static int
 acpi_ec_add_fs (
 	struct acpi_device	*device)
 {
-	struct proc_dir_entry	*entry;
+	struct proc_dir_entry	*entry = NULL;
 
 	ACPI_FUNCTION_TRACE("acpi_ec_add_fs");
 
@@ -744,13 +1115,14 @@ acpi_ec_remove_fs (
                                Driver Interface
    -------------------------------------------------------------------------- */
 
+
 static int
-acpi_ec_add (
+acpi_ec_polling_add (
 	struct acpi_device	*device)
 {
-	int			result;
-	acpi_status		status;
-	struct acpi_ec		*ec;
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	union acpi_ec		*ec = NULL;
 	unsigned long		uid;
 
 	ACPI_FUNCTION_TRACE("acpi_ec_add");
@@ -758,39 +1130,107 @@ acpi_ec_add (
 	if (!device)
 		return_VALUE(-EINVAL);
 
-	ec = kmalloc(sizeof(struct acpi_ec), GFP_KERNEL);
+	ec = kmalloc(sizeof(union acpi_ec), GFP_KERNEL);
 	if (!ec)
 		return_VALUE(-ENOMEM);
-	memset(ec, 0, sizeof(struct acpi_ec));
-
-	ec->handle = device->handle;
-	ec->uid = -1;
- 	atomic_set(&ec->pending_gpe, 0);
- 	atomic_set(&ec->leaving_burst , 1);
- 	init_MUTEX(&ec->sem);
- 	init_waitqueue_head(&ec->wait);
+	memset(ec, 0, sizeof(union acpi_ec));
+
+	ec->common.handle = device->handle;
+	ec->common.uid = -1;
+	spin_lock_init(&ec->polling.lock);
 	strcpy(acpi_device_name(device), ACPI_EC_DEVICE_NAME);
 	strcpy(acpi_device_class(device), ACPI_EC_CLASS);
 	acpi_driver_data(device) = ec;
 
 	/* Use the global lock for all EC transactions? */
-	acpi_evaluate_integer(ec->handle, "_GLK", NULL, &ec->global_lock);
+	acpi_evaluate_integer(ec->common.handle, "_GLK", NULL, &ec->common.global_lock);
 
 	/* If our UID matches the UID for the ECDT-enumerated EC,
 	   we now have the *real* EC info, so kill the makeshift one.*/
-	acpi_evaluate_integer(ec->handle, "_UID", NULL, &uid);
-	if (ec_ecdt && ec_ecdt->uid == uid) {
+	acpi_evaluate_integer(ec->common.handle, "_UID", NULL, &uid);
+	if (ec_ecdt && ec_ecdt->common.uid == uid) {
 		acpi_remove_address_space_handler(ACPI_ROOT_OBJECT,
 			ACPI_ADR_SPACE_EC, &acpi_ec_space_handler);
+	
+		acpi_remove_gpe_handler(NULL, ec_ecdt->common.gpe_bit, &acpi_ec_gpe_handler);
+
+		kfree(ec_ecdt);
+	}
+
+	/* Get GPE bit assignment (EC events). */
+	/* TODO: Add support for _GPE returning a package */
+	status = acpi_evaluate_integer(ec->common.handle, "_GPE", NULL, &ec->common.gpe_bit);
+	if (ACPI_FAILURE(status)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Error obtaining GPE bit assignment\n"));
+		result = -ENODEV;
+		goto end;
+	}
 
-		acpi_remove_gpe_handler(NULL, ec_ecdt->gpe_bit, &acpi_ec_gpe_handler);
+	result = acpi_ec_add_fs(device);
+	if (result)
+		goto end;
+
+	printk(KERN_INFO PREFIX "%s [%s] (gpe %d)\n",
+		acpi_device_name(device), acpi_device_bid(device),
+		(u32) ec->common.gpe_bit);
+
+	if (!first_ec)
+		first_ec = device;
+
+end:
+	if (result)
+		kfree(ec);
+
+	return_VALUE(result);
+}
+static int
+acpi_ec_burst_add (
+	struct acpi_device	*device)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	union acpi_ec		*ec = NULL;
+	unsigned long		uid;
+
+	ACPI_FUNCTION_TRACE("acpi_ec_add");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	ec = kmalloc(sizeof(union acpi_ec), GFP_KERNEL);
+	if (!ec)
+		return_VALUE(-ENOMEM);
+	memset(ec, 0, sizeof(union acpi_ec));
+
+	ec->common.handle = device->handle;
+	ec->common.uid = -1;
+ 	atomic_set(&ec->burst.pending_gpe, 0);
+ 	atomic_set(&ec->burst.leaving_burst , 1);
+ 	init_MUTEX(&ec->burst.sem);
+ 	init_waitqueue_head(&ec->burst.wait);
+	strcpy(acpi_device_name(device), ACPI_EC_DEVICE_NAME);
+	strcpy(acpi_device_class(device), ACPI_EC_CLASS);
+	acpi_driver_data(device) = ec;
+
+	/* Use the global lock for all EC transactions? */
+	acpi_evaluate_integer(ec->common.handle, "_GLK", NULL, &ec->common.global_lock);
+
+	/* If our UID matches the UID for the ECDT-enumerated EC,
+	   we now have the *real* EC info, so kill the makeshift one.*/
+	acpi_evaluate_integer(ec->common.handle, "_UID", NULL, &uid);
+	if (ec_ecdt && ec_ecdt->common.uid == uid) {
+		acpi_remove_address_space_handler(ACPI_ROOT_OBJECT,
+			ACPI_ADR_SPACE_EC, &acpi_ec_space_handler);
+
+		acpi_remove_gpe_handler(NULL, ec_ecdt->common.gpe_bit, &acpi_ec_gpe_handler);
 
 		kfree(ec_ecdt);
 	}
 
 	/* Get GPE bit assignment (EC events). */
 	/* TODO: Add support for _GPE returning a package */
-	status = acpi_evaluate_integer(ec->handle, "_GPE", NULL, &ec->gpe_bit);
+	status = acpi_evaluate_integer(ec->common.handle, "_GPE", NULL, &ec->common.gpe_bit);
 	if (ACPI_FAILURE(status)) {
 		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
 			"Error obtaining GPE bit assignment\n"));
@@ -804,7 +1244,7 @@ acpi_ec_add (
 
 	printk(KERN_INFO PREFIX "%s [%s] (gpe %d)\n",
 		acpi_device_name(device), acpi_device_bid(device),
-		(u32) ec->gpe_bit);
+		(u32) ec->common.gpe_bit);
 
 	if (!first_ec)
 		first_ec = device;
@@ -822,7 +1262,7 @@ acpi_ec_remove (
 	struct acpi_device	*device,
 	int			type)
 {
-	struct acpi_ec		*ec;
+	union acpi_ec		*ec = NULL;
 
 	ACPI_FUNCTION_TRACE("acpi_ec_remove");
 
@@ -844,7 +1284,7 @@ acpi_ec_io_ports (
 	struct acpi_resource	*resource,
 	void			*context)
 {
-	struct acpi_ec		*ec = (struct acpi_ec *) context;
+	union acpi_ec		*ec = (union acpi_ec *) context;
 	struct acpi_generic_address *addr;
 
 	if (resource->id != ACPI_RSTYPE_IO) {
@@ -856,10 +1296,10 @@ acpi_ec_io_ports (
 	 * the second address region returned is the status/command
 	 * port.
 	 */
-	if (ec->data_addr.register_bit_width == 0) {
-		addr = &ec->data_addr;
-	} else if (ec->command_addr.register_bit_width == 0) {
-		addr = &ec->command_addr;
+	if (ec->common.data_addr.register_bit_width == 0) {
+		addr = &ec->common.data_addr;
+	} else if (ec->common.command_addr.register_bit_width == 0) {
+		addr = &ec->common.command_addr;
 	} else {
 		return AE_CTRL_TERMINATE;
 	}
@@ -877,8 +1317,8 @@ static int
 acpi_ec_start (
 	struct acpi_device	*device)
 {
-	acpi_status		status;
-	struct acpi_ec		*ec;
+	acpi_status		status = AE_OK;
+	union acpi_ec		*ec = NULL;
 
 	ACPI_FUNCTION_TRACE("acpi_ec_start");
 
@@ -893,35 +1333,36 @@ acpi_ec_start (
 	/*
 	 * Get I/O port addresses. Convert to GAS format.
 	 */
-	status = acpi_walk_resources(ec->handle, METHOD_NAME__CRS,
+	status = acpi_walk_resources(ec->common.handle, METHOD_NAME__CRS,
 		acpi_ec_io_ports, ec);
-	if (ACPI_FAILURE(status) || ec->command_addr.register_bit_width == 0) {
+	if (ACPI_FAILURE(status) || ec->common.command_addr.register_bit_width == 0) {
 		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Error getting I/O port addresses"));
 		return_VALUE(-ENODEV);
 	}
 
-	ec->status_addr = ec->command_addr;
+	ec->common.status_addr = ec->common.command_addr;
 
 	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "gpe=0x%02x, ports=0x%2x,0x%2x\n",
-		(u32) ec->gpe_bit, (u32) ec->command_addr.address,
-		(u32) ec->data_addr.address));
+		(u32) ec->common.gpe_bit, (u32) ec->common.command_addr.address,
+		(u32) ec->common.data_addr.address));
+
 
 	/*
 	 * Install GPE handler
 	 */
-	status = acpi_install_gpe_handler(NULL, ec->gpe_bit,
+	status = acpi_install_gpe_handler(NULL, ec->common.gpe_bit,
 		ACPI_GPE_EDGE_TRIGGERED, &acpi_ec_gpe_handler, ec);
 	if (ACPI_FAILURE(status)) {
 		return_VALUE(-ENODEV);
 	}
-	acpi_set_gpe_type (NULL, ec->gpe_bit, ACPI_GPE_TYPE_RUNTIME);
-	acpi_enable_gpe (NULL, ec->gpe_bit, ACPI_NOT_ISR);
+	acpi_set_gpe_type (NULL, ec->common.gpe_bit, ACPI_GPE_TYPE_RUNTIME);
+	acpi_enable_gpe (NULL, ec->common.gpe_bit, ACPI_NOT_ISR);
 
-	status = acpi_install_address_space_handler (ec->handle,
+	status = acpi_install_address_space_handler (ec->common.handle,
 			ACPI_ADR_SPACE_EC, &acpi_ec_space_handler,
 			&acpi_ec_space_setup, ec);
 	if (ACPI_FAILURE(status)) {
-		acpi_remove_gpe_handler(NULL, ec->gpe_bit, &acpi_ec_gpe_handler);
+		acpi_remove_gpe_handler(NULL, ec->common.gpe_bit, &acpi_ec_gpe_handler);
 		return_VALUE(-ENODEV);
 	}
 
@@ -934,8 +1375,8 @@ acpi_ec_stop (
 	struct acpi_device	*device,
 	int			type)
 {
-	acpi_status		status;
-	struct acpi_ec		*ec;
+	acpi_status		status = AE_OK;
+	union acpi_ec		*ec = NULL;
 
 	ACPI_FUNCTION_TRACE("acpi_ec_stop");
 
@@ -944,12 +1385,12 @@ acpi_ec_stop (
 
 	ec = acpi_driver_data(device);
 
-	status = acpi_remove_address_space_handler(ec->handle,
+	status = acpi_remove_address_space_handler(ec->common.handle,
 		ACPI_ADR_SPACE_EC, &acpi_ec_space_handler);
 	if (ACPI_FAILURE(status))
 		return_VALUE(-ENODEV);
 
-	status = acpi_remove_gpe_handler(NULL, ec->gpe_bit, &acpi_ec_gpe_handler);
+	status = acpi_remove_gpe_handler(NULL, ec->common.gpe_bit, &acpi_ec_gpe_handler);
 	if (ACPI_FAILURE(status))
 		return_VALUE(-ENODEV);
 
@@ -963,26 +1404,76 @@ acpi_fake_ecdt_callback (
 	void		*context,
 	void		**retval)
 {
+
+	if (acpi_ec_polling_mode)
+		return acpi_fake_ecdt_polling_callback(handle,
+			Level, context, retval);
+	else
+		return acpi_fake_ecdt_burst_callback(handle,
+			Level, context, retval);
+}
+
+static acpi_status __init
+acpi_fake_ecdt_polling_callback (
+	acpi_handle	handle,
+	u32		Level,
+	void		*context,
+	void		**retval)
+{
 	acpi_status	status;
 
 	status = acpi_walk_resources(handle, METHOD_NAME__CRS,
 		acpi_ec_io_ports, ec_ecdt);
 	if (ACPI_FAILURE(status))
 		return status;
-	ec_ecdt->status_addr = ec_ecdt->command_addr;
+	ec_ecdt->common.status_addr = ec_ecdt->common.command_addr;
 
-	ec_ecdt->uid = -1;
-	acpi_evaluate_integer(handle, "_UID", NULL, &ec_ecdt->uid);
+	ec_ecdt->common.uid = -1;
+	acpi_evaluate_integer(handle, "_UID", NULL, &ec_ecdt->common.uid);
 
-	status = acpi_evaluate_integer(handle, "_GPE", NULL, &ec_ecdt->gpe_bit);
+	status = acpi_evaluate_integer(handle, "_GPE", NULL, &ec_ecdt->common.gpe_bit);
 	if (ACPI_FAILURE(status))
 		return status;
-	ec_ecdt->global_lock = TRUE;
-	ec_ecdt->handle = handle;
+	spin_lock_init(&ec_ecdt->polling.lock);
+	ec_ecdt->common.global_lock = TRUE;
+	ec_ecdt->common.handle = handle;
 
 	printk(KERN_INFO PREFIX  "GPE=0x%02x, ports=0x%2x, 0x%2x\n",
-		(u32) ec_ecdt->gpe_bit, (u32) ec_ecdt->command_addr.address,
-		(u32) ec_ecdt->data_addr.address);
+		(u32) ec_ecdt->common.gpe_bit, (u32) ec_ecdt->common.command_addr.address,
+		(u32) ec_ecdt->common.data_addr.address);
+
+	return AE_CTRL_TERMINATE;
+}
+
+static acpi_status __init
+acpi_fake_ecdt_burst_callback (
+	acpi_handle	handle,
+	u32		Level,
+	void		*context,
+	void		**retval)
+{
+	acpi_status	status;
+
+	init_MUTEX(&ec_ecdt->burst.sem);
+	init_waitqueue_head(&ec_ecdt->burst.wait);
+	status = acpi_walk_resources(handle, METHOD_NAME__CRS,
+		acpi_ec_io_ports, ec_ecdt);
+	if (ACPI_FAILURE(status))
+		return status;
+	ec_ecdt->common.status_addr = ec_ecdt->common.command_addr;
+
+	ec_ecdt->common.uid = -1;
+	acpi_evaluate_integer(handle, "_UID", NULL, &ec_ecdt->common.uid);
+
+	status = acpi_evaluate_integer(handle, "_GPE", NULL, &ec_ecdt->common.gpe_bit);
+	if (ACPI_FAILURE(status))
+		return status;
+	ec_ecdt->common.global_lock = TRUE;
+	ec_ecdt->common.handle = handle;
+
+	printk(KERN_INFO PREFIX  "GPE=0x%02x, ports=0x%2x, 0x%2x\n",
+		(u32) ec_ecdt->common.gpe_bit, (u32) ec_ecdt->common.command_addr.address,
+		(u32) ec_ecdt->common.data_addr.address);
 
 	return AE_CTRL_TERMINATE;
 }
@@ -1005,12 +1496,12 @@ acpi_ec_fake_ecdt(void)
 
 	printk(KERN_INFO PREFIX "Try to make an fake ECDT\n");
 
-	ec_ecdt = kmalloc(sizeof(struct acpi_ec), GFP_KERNEL);
+	ec_ecdt = kmalloc(sizeof(union acpi_ec), GFP_KERNEL);
 	if (!ec_ecdt) {
 		ret = -ENOMEM;
 		goto error;
 	}
-	memset(ec_ecdt, 0, sizeof(struct acpi_ec));
+	memset(ec_ecdt, 0, sizeof(union acpi_ec));
 
 	status = acpi_get_devices (ACPI_EC_HID,
 				acpi_fake_ecdt_callback,
@@ -1031,6 +1522,60 @@ error:
 static int __init
 acpi_ec_get_real_ecdt(void)
 {
+	if (acpi_ec_polling_mode)
+		return acpi_ec_polling_get_real_ecdt();
+	else
+		return acpi_ec_burst_get_real_ecdt();
+}
+
+static int __init
+acpi_ec_polling_get_real_ecdt(void)
+{
+	acpi_status		status;
+	struct acpi_table_ecdt 	*ecdt_ptr;
+
+	status = acpi_get_firmware_table("ECDT", 1, ACPI_LOGICAL_ADDRESSING, 
+		(struct acpi_table_header **) &ecdt_ptr);
+	if (ACPI_FAILURE(status))
+		return -ENODEV;
+
+	printk(KERN_INFO PREFIX "Found ECDT\n");
+
+	/*
+	 * Generate a temporary ec context to use until the namespace is scanned
+	 */
+	ec_ecdt = kmalloc(sizeof(union acpi_ec), GFP_KERNEL);
+	if (!ec_ecdt)
+		return -ENOMEM;
+	memset(ec_ecdt, 0, sizeof(union acpi_ec));
+
+	ec_ecdt->common.command_addr = ecdt_ptr->ec_control;
+	ec_ecdt->common.status_addr = ecdt_ptr->ec_control;
+	ec_ecdt->common.data_addr = ecdt_ptr->ec_data;
+	ec_ecdt->common.gpe_bit = ecdt_ptr->gpe_bit;
+	spin_lock_init(&ec_ecdt->polling.lock);
+	/* use the GL just to be safe */
+	ec_ecdt->common.global_lock = TRUE;
+	ec_ecdt->common.uid = ecdt_ptr->uid;
+
+	status = acpi_get_handle(NULL, ecdt_ptr->ec_id, &ec_ecdt->common.handle);
+	if (ACPI_FAILURE(status)) {
+		goto error;
+	}
+
+	return 0;
+error:
+	printk(KERN_ERR PREFIX "Could not use ECDT\n");
+	kfree(ec_ecdt);
+	ec_ecdt = NULL;
+
+	return -ENODEV;
+}
+
+
+static int __init
+acpi_ec_burst_get_real_ecdt(void)
+{
 	acpi_status		status;
 	struct acpi_table_ecdt 	*ecdt_ptr;
 
@@ -1044,22 +1589,22 @@ acpi_ec_get_real_ecdt(void)
 	/*
 	 * Generate a temporary ec context to use until the namespace is scanned
 	 */
-	ec_ecdt = kmalloc(sizeof(struct acpi_ec), GFP_KERNEL);
+	ec_ecdt = kmalloc(sizeof(union acpi_ec), GFP_KERNEL);
 	if (!ec_ecdt)
 		return -ENOMEM;
-	memset(ec_ecdt, 0, sizeof(struct acpi_ec));
-
- 	init_MUTEX(&ec_ecdt->sem);
- 	init_waitqueue_head(&ec_ecdt->wait);
-	ec_ecdt->command_addr = ecdt_ptr->ec_control;
-	ec_ecdt->status_addr = ecdt_ptr->ec_control;
-	ec_ecdt->data_addr = ecdt_ptr->ec_data;
-	ec_ecdt->gpe_bit = ecdt_ptr->gpe_bit;
+	memset(ec_ecdt, 0, sizeof(union acpi_ec));
+
+ 	init_MUTEX(&ec_ecdt->burst.sem);
+ 	init_waitqueue_head(&ec_ecdt->burst.wait);
+	ec_ecdt->common.command_addr = ecdt_ptr->ec_control;
+	ec_ecdt->common.status_addr = ecdt_ptr->ec_control;
+	ec_ecdt->common.data_addr = ecdt_ptr->ec_data;
+	ec_ecdt->common.gpe_bit = ecdt_ptr->gpe_bit;
 	/* use the GL just to be safe */
-	ec_ecdt->global_lock = TRUE;
-	ec_ecdt->uid = ecdt_ptr->uid;
+	ec_ecdt->common.global_lock = TRUE;
+	ec_ecdt->common.uid = ecdt_ptr->uid;
 
-	status = acpi_get_handle(NULL, ecdt_ptr->ec_id, &ec_ecdt->handle);
+	status = acpi_get_handle(NULL, ecdt_ptr->ec_id, &ec_ecdt->common.handle);
 	if (ACPI_FAILURE(status)) {
 		goto error;
 	}
@@ -1092,20 +1637,20 @@ acpi_ec_ecdt_probe (void)
 	/*
 	 * Install GPE handler
 	 */
-	status = acpi_install_gpe_handler(NULL, ec_ecdt->gpe_bit,
+	status = acpi_install_gpe_handler(NULL, ec_ecdt->common.gpe_bit,
 		ACPI_GPE_EDGE_TRIGGERED, &acpi_ec_gpe_handler,
 		ec_ecdt);
 	if (ACPI_FAILURE(status)) {
 		goto error;
 	}
-	acpi_set_gpe_type (NULL, ec_ecdt->gpe_bit, ACPI_GPE_TYPE_RUNTIME);
-	acpi_enable_gpe (NULL, ec_ecdt->gpe_bit, ACPI_NOT_ISR);
+	acpi_set_gpe_type (NULL, ec_ecdt->common.gpe_bit, ACPI_GPE_TYPE_RUNTIME);
+	acpi_enable_gpe (NULL, ec_ecdt->common.gpe_bit, ACPI_NOT_ISR);
 
 	status = acpi_install_address_space_handler (ACPI_ROOT_OBJECT,
 			ACPI_ADR_SPACE_EC, &acpi_ec_space_handler,
 			&acpi_ec_space_setup, ec_ecdt);
 	if (ACPI_FAILURE(status)) {
-		acpi_remove_gpe_handler(NULL, ec_ecdt->gpe_bit,
+		acpi_remove_gpe_handler(NULL, ec_ecdt->common.gpe_bit,
 			&acpi_ec_gpe_handler);
 		goto error;
 	}
@@ -1123,7 +1668,7 @@ error:
 
 static int __init acpi_ec_init (void)
 {
-	int			result;
+	int			result = 0;
 
 	ACPI_FUNCTION_TRACE("acpi_ec_init");
 
@@ -1166,4 +1711,24 @@ static int __init acpi_fake_ecdt_setup(char *str)
 	acpi_fake_ecdt_enabled = 1;
 	return 0;
 }
+
 __setup("acpi_fake_ecdt", acpi_fake_ecdt_setup);
+static int __init acpi_ec_set_polling_mode(char *str)
+{
+	int burst;
+
+	if (!get_option(&str, &burst))
+		return 0;
+
+	if (burst) {
+		acpi_ec_polling_mode = EC_BURST;
+		acpi_ec_driver.ops.add = acpi_ec_burst_add;
+	} else {
+		acpi_ec_polling_mode = EC_POLLING;
+		acpi_ec_driver.ops.add = acpi_ec_polling_add;
+	}
+	printk(KERN_INFO PREFIX "EC %s mode.\n",
+		burst ? "burst": "polling");
+	return 0;
+}
+__setup("ec_burst=", acpi_ec_set_polling_mode);
diff --git a/drivers/acpi/hotkey.c b/drivers/acpi/hotkey.c
index babdf762ead..1f76a40bade 100644
--- a/drivers/acpi/hotkey.c
+++ b/drivers/acpi/hotkey.c
@@ -1,5 +1,5 @@
-/* 
- *  hotkey.c - ACPI Hotkey Driver ($Revision:$)
+/*
+ *  hotkey.c - ACPI Hotkey Driver ($Revision: 0.2 $)
  *
  *  Copyright (C) 2004 Luming Yu <luming.yu@intel.com>
  *
@@ -51,17 +51,18 @@
 #define ACPI_HOTKEY_POLLING 0x2
 #define ACPI_UNDEFINED_EVENT    0xf
 
-#define MAX_CONFIG_RECORD_LEN   80
-#define MAX_NAME_PATH_LEN   80
-#define MAX_CALL_PARM       80
+#define RESULT_STR_LEN	    80
 
-#define IS_EVENT(e)       0xff	/* ((e) & 0x40000000)  */
-#define IS_POLL(e)      0xff	/* (~((e) & 0x40000000))  */
+#define ACTION_METHOD	0
+#define POLL_METHOD	1
 
+#define IS_EVENT(e)       	((e) <= 10000 && (e) >0)
+#define IS_POLL(e)      	((e) > 10000)
+#define IS_OTHERS(e)		((e)<=0 || (e)>=20000)
 #define _COMPONENT              ACPI_HOTKEY_COMPONENT
 ACPI_MODULE_NAME("acpi_hotkey")
 
-    MODULE_AUTHOR("luming.yu@intel.com");
+MODULE_AUTHOR("luming.yu@intel.com");
 MODULE_DESCRIPTION(ACPI_HOTK_NAME);
 MODULE_LICENSE("GPL");
 
@@ -114,7 +115,7 @@ struct acpi_event_hotkey {
 	char *action_method;	/* action method */
 };
 
-/* 
+/*
  * There are two ways to poll status
  * 1. directy call read_xxx method, without any arguments passed in
  * 2. call write_xxx method, with arguments passed in, you need
@@ -131,7 +132,7 @@ struct acpi_polling_hotkey {
 	char *poll_method;	/* poll method */
 	acpi_handle action_handle;	/* acpi handle attached action method */
 	char *action_method;	/* action method */
-	void *poll_result;	/* polling_result */
+	union acpi_object *poll_result;	/* polling_result */
 	struct proc_dir_entry *proc;
 };
 
@@ -162,20 +163,25 @@ static struct acpi_driver hotkey_driver = {
 		},
 };
 
+static void free_hotkey_device(union acpi_hotkey *key);
+static void free_hotkey_buffer(union acpi_hotkey *key);
+static void free_poll_hotkey_buffer(union acpi_hotkey *key);
 static int hotkey_open_config(struct inode *inode, struct file *file);
+static int hotkey_poll_open_config(struct inode *inode, struct file *file);
 static ssize_t hotkey_write_config(struct file *file,
 				   const char __user * buffer,
 				   size_t count, loff_t * data);
-static ssize_t hotkey_write_poll_config(struct file *file,
-					const char __user * buffer,
-					size_t count, loff_t * data);
 static int hotkey_info_open_fs(struct inode *inode, struct file *file);
 static int hotkey_action_open_fs(struct inode *inode, struct file *file);
 static ssize_t hotkey_execute_aml_method(struct file *file,
 					 const char __user * buffer,
 					 size_t count, loff_t * data);
 static int hotkey_config_seq_show(struct seq_file *seq, void *offset);
+static int hotkey_poll_config_seq_show(struct seq_file *seq, void *offset);
 static int hotkey_polling_open_fs(struct inode *inode, struct file *file);
+static union acpi_hotkey *get_hotkey_by_event(struct
+			      acpi_hotkey_list
+			      *hotkey_list, int event);
 
 /* event based config */
 static struct file_operations hotkey_config_fops = {
@@ -188,9 +194,9 @@ static struct file_operations hotkey_config_fops = {
 
 /* polling based config */
 static struct file_operations hotkey_poll_config_fops = {
-	.open = hotkey_open_config,
+	.open = hotkey_poll_open_config,
 	.read = seq_read,
-	.write = hotkey_write_poll_config,
+	.write = hotkey_write_config,
 	.llseek = seq_lseek,
 	.release = single_release,
 };
@@ -227,7 +233,7 @@ static int hotkey_info_seq_show(struct seq_file *seq, void *offset)
 {
 	ACPI_FUNCTION_TRACE("hotkey_info_seq_show");
 
-	seq_printf(seq, "Hotkey generic driver ver: %s", HOTKEY_ACPI_VERSION);
+	seq_printf(seq, "Hotkey generic driver ver: %s\n", HOTKEY_ACPI_VERSION);
 
 	return_VALUE(0);
 }
@@ -239,27 +245,35 @@ static int hotkey_info_open_fs(struct inode *inode, struct file *file)
 
 static char *format_result(union acpi_object *object)
 {
-	char *buf = (char *)kmalloc(sizeof(union acpi_object), GFP_KERNEL);
-
-	memset(buf, 0, sizeof(union acpi_object));
+	char *buf = NULL;
+	
+	buf = (char *)kmalloc(RESULT_STR_LEN, GFP_KERNEL);
+	if (buf)
+		memset(buf, 0, RESULT_STR_LEN);
+	else
+		goto do_fail;
 
 	/* Now, just support integer type */
 	if (object->type == ACPI_TYPE_INTEGER)
-		sprintf(buf, "%d", (u32) object->integer.value);
-
-	return buf;
+		sprintf(buf, "%d\n", (u32) object->integer.value);
+do_fail:
+	return (buf);
 }
 
 static int hotkey_polling_seq_show(struct seq_file *seq, void *offset)
 {
 	struct acpi_polling_hotkey *poll_hotkey =
 	    (struct acpi_polling_hotkey *)seq->private;
+	char *buf;
 
 	ACPI_FUNCTION_TRACE("hotkey_polling_seq_show");
 
-	if (poll_hotkey->poll_result)
-		seq_printf(seq, "%s", format_result(poll_hotkey->poll_result));
-
+	if (poll_hotkey->poll_result){
+		buf = format_result(poll_hotkey->poll_result);
+		if(buf)
+			seq_printf(seq, "%s", buf);
+		kfree(buf);
+	}
 	return_VALUE(0);
 }
 
@@ -276,19 +290,19 @@ static int hotkey_action_open_fs(struct inode *inode, struct file *file)
 /* Mapping external hotkey number to standardized hotkey event num */
 static int hotkey_get_internal_event(int event, struct acpi_hotkey_list *list)
 {
-	struct list_head *entries, *next;
-	int val = 0;
+	struct list_head *entries;
+	int val = -1;
 
 	ACPI_FUNCTION_TRACE("hotkey_get_internal_event");
 
-	list_for_each_safe(entries, next, list->entries) {
+	list_for_each(entries, list->entries) {
 		union acpi_hotkey *key =
 		    container_of(entries, union acpi_hotkey, entries);
 		if (key->link.hotkey_type == ACPI_HOTKEY_EVENT
-		    && key->event_hotkey.external_hotkey_num == event)
+		    && key->event_hotkey.external_hotkey_num == event){
 			val = key->link.hotkey_standard_num;
-		else
-			val = -1;
+			break;
+		}
 	}
 
 	return_VALUE(val);
@@ -306,7 +320,7 @@ acpi_hotkey_notify_handler(acpi_handle handle, u32 event, void *data)
 		return_VOID;
 
 	internal_event = hotkey_get_internal_event(event, &global_hotkey_list);
-	acpi_bus_generate_event(device, event, 0);
+	acpi_bus_generate_event(device, internal_event, 0);
 
 	return_VOID;
 }
@@ -329,13 +343,17 @@ static int auto_hotkey_remove(struct acpi_device *device, int type)
 static int create_polling_proc(union acpi_hotkey *device)
 {
 	struct proc_dir_entry *proc;
+	char  proc_name[80];
 	mode_t mode;
 
 	ACPI_FUNCTION_TRACE("create_polling_proc");
 	mode = S_IFREG | S_IRUGO | S_IWUGO;
 
-	proc = create_proc_entry(device->poll_hotkey.action_method,
-				 mode, hotkey_proc_dir);
+	sprintf(proc_name, "%d", device->link.hotkey_standard_num);
+	/*
+	strcat(proc_name, device->poll_hotkey.poll_method);
+	*/
+	proc = create_proc_entry(proc_name, mode, hotkey_proc_dir);
 
 	if (!proc) {
 		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
@@ -353,23 +371,6 @@ static int create_polling_proc(union acpi_hotkey *device)
 	return_VALUE(0);
 }
 
-static int is_valid_acpi_path(const char *pathname)
-{
-	acpi_handle handle;
-	acpi_status status;
-	ACPI_FUNCTION_TRACE("is_valid_acpi_path");
-
-	status = acpi_get_handle(NULL, (char *)pathname, &handle);
-	return_VALUE(!ACPI_FAILURE(status));
-}
-
-static int is_valid_hotkey(union acpi_hotkey *device)
-{
-	ACPI_FUNCTION_TRACE("is_valid_hotkey");
-	/* Implement valid check */
-	return_VALUE(1);
-}
-
 static int hotkey_add(union acpi_hotkey *device)
 {
 	int status = 0;
@@ -378,15 +379,11 @@ static int hotkey_add(union acpi_hotkey *device)
 	ACPI_FUNCTION_TRACE("hotkey_add");
 
 	if (device->link.hotkey_type == ACPI_HOTKEY_EVENT) {
-		status =
-		    acpi_bus_get_device(device->event_hotkey.bus_handle, &dev);
-		if (status)
-			return_VALUE(status);
-
+		acpi_bus_get_device(device->event_hotkey.bus_handle, &dev);
 		status = acpi_install_notify_handler(dev->handle,
-						     ACPI_SYSTEM_NOTIFY,
+						     ACPI_DEVICE_NOTIFY,
 						     acpi_hotkey_notify_handler,
-						     device);
+						     dev);
 	} else			/* Add polling hotkey */
 		create_polling_proc(device);
 
@@ -409,84 +406,143 @@ static int hotkey_remove(union acpi_hotkey *device)
 		if (key->link.hotkey_standard_num ==
 		    device->link.hotkey_standard_num) {
 			list_del(&key->link.entries);
-			remove_proc_entry(key->poll_hotkey.action_method,
-					  hotkey_proc_dir);
+			free_hotkey_device(key);
 			global_hotkey_list.count--;
 			break;
 		}
 	}
+	kfree(device);
 	return_VALUE(0);
 }
 
-static void hotkey_update(union acpi_hotkey *key)
+static int  hotkey_update(union acpi_hotkey *key)
 {
-	struct list_head *entries, *next;
+	struct list_head *entries;
 
 	ACPI_FUNCTION_TRACE("hotkey_update");
 
-	list_for_each_safe(entries, next, global_hotkey_list.entries) {
-		union acpi_hotkey *key =
+	list_for_each(entries, global_hotkey_list.entries) {
+		union acpi_hotkey *tmp=
 		    container_of(entries, union acpi_hotkey, entries);
-		if (key->link.hotkey_standard_num ==
+		if (tmp->link.hotkey_standard_num ==
 		    key->link.hotkey_standard_num) {
-			key->event_hotkey.bus_handle =
-			    key->event_hotkey.bus_handle;
-			key->event_hotkey.external_hotkey_num =
-			    key->event_hotkey.external_hotkey_num;
-			key->event_hotkey.action_handle =
-			    key->event_hotkey.action_handle;
-			key->event_hotkey.action_method =
-			    key->event_hotkey.action_method;
+			if (key->link.hotkey_type == ACPI_HOTKEY_EVENT) {
+				free_hotkey_buffer(tmp);
+				tmp->event_hotkey.bus_handle =
+			    		key->event_hotkey.bus_handle;
+				tmp->event_hotkey.external_hotkey_num =
+			    		key->event_hotkey.external_hotkey_num;
+				tmp->event_hotkey.action_handle =
+			    		key->event_hotkey.action_handle;
+				tmp->event_hotkey.action_method =
+			    		key->event_hotkey.action_method;
+				kfree(key);
+			} else {
+				/*
+				char  proc_name[80];
+
+				sprintf(proc_name, "%d", tmp->link.hotkey_standard_num);
+				strcat(proc_name, tmp->poll_hotkey.poll_method);
+				remove_proc_entry(proc_name,hotkey_proc_dir);
+				*/
+				free_poll_hotkey_buffer(tmp);
+				tmp->poll_hotkey.poll_handle =
+					key->poll_hotkey.poll_handle;
+				tmp->poll_hotkey.poll_method =
+					key->poll_hotkey.poll_method;
+				tmp->poll_hotkey.action_handle =
+					key->poll_hotkey.action_handle;
+				tmp->poll_hotkey.action_method =
+					key->poll_hotkey.action_method;
+				tmp->poll_hotkey.poll_result =
+					key->poll_hotkey.poll_result;
+				/*
+				create_polling_proc(tmp);
+				*/
+				kfree(key);
+			}
+			return_VALUE(0);
 			break;
 		}
 	}
 
-	return_VOID;
+	return_VALUE(-ENODEV);
 }
 
 static void free_hotkey_device(union acpi_hotkey *key)
 {
 	struct acpi_device *dev;
-	int status;
 
 	ACPI_FUNCTION_TRACE("free_hotkey_device");
 
 	if (key->link.hotkey_type == ACPI_HOTKEY_EVENT) {
-		status =
-		    acpi_bus_get_device(key->event_hotkey.bus_handle, &dev);
+		acpi_bus_get_device(key->event_hotkey.bus_handle, &dev);
 		if (dev->handle)
 			acpi_remove_notify_handler(dev->handle,
-						   ACPI_SYSTEM_NOTIFY,
+						   ACPI_DEVICE_NOTIFY,
 						   acpi_hotkey_notify_handler);
-	} else
-		remove_proc_entry(key->poll_hotkey.action_method,
-				  hotkey_proc_dir);
+		free_hotkey_buffer(key);
+	} else {
+		char  proc_name[80];
+
+		sprintf(proc_name, "%d", key->link.hotkey_standard_num);
+		/*
+		strcat(proc_name, key->poll_hotkey.poll_method);
+		*/
+		remove_proc_entry(proc_name,hotkey_proc_dir);
+		free_poll_hotkey_buffer(key);
+	}
 	kfree(key);
 	return_VOID;
 }
 
+static void
+free_hotkey_buffer(union acpi_hotkey *key)
+{
+	kfree(key->event_hotkey.action_method);
+}
+
+static void
+free_poll_hotkey_buffer(union acpi_hotkey *key)
+{
+	kfree(key->poll_hotkey.action_method);
+	kfree(key->poll_hotkey.poll_method);
+	kfree(key->poll_hotkey.poll_result);
+}
 static int
 init_hotkey_device(union acpi_hotkey *key, char *bus_str, char *action_str,
 		   char *method, int std_num, int external_num)
 {
+	acpi_handle	tmp_handle;
+	acpi_status status = AE_OK;
+
 	ACPI_FUNCTION_TRACE("init_hotkey_device");
 
+	if(std_num < 0 || IS_POLL(std_num) || !key )
+		goto do_fail;
+
+	if(!bus_str || !action_str || !method)
+		goto do_fail;
+
 	key->link.hotkey_type = ACPI_HOTKEY_EVENT;
 	key->link.hotkey_standard_num = std_num;
 	key->event_hotkey.flag = 0;
-	if (is_valid_acpi_path(bus_str))
-		acpi_get_handle((acpi_handle) 0,
-				bus_str, &(key->event_hotkey.bus_handle));
-	else
-		return_VALUE(-ENODEV);
-	key->event_hotkey.external_hotkey_num = external_num;
-	if (is_valid_acpi_path(action_str))
-		acpi_get_handle((acpi_handle) 0,
-				action_str, &(key->event_hotkey.action_handle));
-	key->event_hotkey.action_method = kmalloc(sizeof(method), GFP_KERNEL);
-	strcpy(key->event_hotkey.action_method, method);
+	key->event_hotkey.action_method = method;
 
-	return_VALUE(!is_valid_hotkey(key));
+	status = acpi_get_handle(NULL,bus_str, &(key->event_hotkey.bus_handle));
+	if(ACPI_FAILURE(status))
+		goto do_fail;
+	key->event_hotkey.external_hotkey_num = external_num;
+	status = acpi_get_handle(NULL,action_str, &(key->event_hotkey.action_handle));
+	if(ACPI_FAILURE(status))
+		goto do_fail;
+	status = acpi_get_handle(key->event_hotkey.action_handle,
+				method, &tmp_handle);
+	if (ACPI_FAILURE(status))
+		goto do_fail;
+	return_VALUE(AE_OK);
+do_fail:
+	return_VALUE(-ENODEV);
 }
 
 static int
@@ -495,34 +551,46 @@ init_poll_hotkey_device(union acpi_hotkey *key,
 			char *poll_method,
 			char *action_str, char *action_method, int std_num)
 {
+	acpi_status status = AE_OK;
+	acpi_handle	tmp_handle;
+
 	ACPI_FUNCTION_TRACE("init_poll_hotkey_device");
 
+	if(std_num < 0 || IS_EVENT(std_num) || !key)
+		goto do_fail;
+
+	if(!poll_str || !poll_method || !action_str || !action_method)
+		goto do_fail;
+
 	key->link.hotkey_type = ACPI_HOTKEY_POLLING;
 	key->link.hotkey_standard_num = std_num;
 	key->poll_hotkey.flag = 0;
-	if (is_valid_acpi_path(poll_str))
-		acpi_get_handle((acpi_handle) 0,
-				poll_str, &(key->poll_hotkey.poll_handle));
-	else
-		return_VALUE(-ENODEV);
 	key->poll_hotkey.poll_method = poll_method;
-	if (is_valid_acpi_path(action_str))
-		acpi_get_handle((acpi_handle) 0,
-				action_str, &(key->poll_hotkey.action_handle));
-	key->poll_hotkey.action_method =
-	    kmalloc(sizeof(action_method), GFP_KERNEL);
-	strcpy(key->poll_hotkey.action_method, action_method);
+	key->poll_hotkey.action_method = action_method;
+
+	status = acpi_get_handle(NULL,poll_str, &(key->poll_hotkey.poll_handle));
+	if(ACPI_FAILURE(status))
+		goto do_fail;
+	status = acpi_get_handle(key->poll_hotkey.poll_handle,
+				poll_method, &tmp_handle);
+        if (ACPI_FAILURE(status))
+       		goto do_fail;
+	status = acpi_get_handle(NULL,action_str, &(key->poll_hotkey.action_handle));
+	if (ACPI_FAILURE(status))
+		goto do_fail;
+	status = acpi_get_handle(key->poll_hotkey.action_handle,
+				action_method, &tmp_handle);
+	if (ACPI_FAILURE(status))
+		goto do_fail;
 	key->poll_hotkey.poll_result =
 	    (union acpi_object *)kmalloc(sizeof(union acpi_object), GFP_KERNEL);
-	return_VALUE(is_valid_hotkey(key));
+	if(!key->poll_hotkey.poll_result)
+		goto do_fail;
+	return_VALUE(AE_OK);
+do_fail:
+	return_VALUE(-ENODEV);
 }
 
-static int check_hotkey_valid(union acpi_hotkey *key,
-			      struct acpi_hotkey_list *list)
-{
-	ACPI_FUNCTION_TRACE("check_hotkey_valid");
-	return_VALUE(0);
-}
 
 static int hotkey_open_config(struct inode *inode, struct file *file)
 {
@@ -531,10 +599,17 @@ static int hotkey_open_config(struct inode *inode, struct file *file)
 		     (file, hotkey_config_seq_show, PDE(inode)->data));
 }
 
+static int hotkey_poll_open_config(struct inode *inode, struct file *file)
+{
+	ACPI_FUNCTION_TRACE("hotkey_poll_open_config");
+	return_VALUE(single_open
+		     (file, hotkey_poll_config_seq_show, PDE(inode)->data));
+}
+
 static int hotkey_config_seq_show(struct seq_file *seq, void *offset)
 {
 	struct acpi_hotkey_list *hotkey_list = &global_hotkey_list;
-	struct list_head *entries, *next;
+	struct list_head *entries;
 	char bus_name[ACPI_PATHNAME_MAX] = { 0 };
 	char action_name[ACPI_PATHNAME_MAX] = { 0 };
 	struct acpi_buffer bus = { ACPI_PATHNAME_MAX, bus_name };
@@ -542,10 +617,7 @@ static int hotkey_config_seq_show(struct seq_file *seq, void *offset)
 
 	ACPI_FUNCTION_TRACE(("hotkey_config_seq_show"));
 
-	if (!hotkey_list)
-		goto end;
-
-	list_for_each_safe(entries, next, hotkey_list->entries) {
+	list_for_each(entries, hotkey_list->entries) {
 		union acpi_hotkey *key =
 		    container_of(entries, union acpi_hotkey, entries);
 		if (key->link.hotkey_type == ACPI_HOTKEY_EVENT) {
@@ -553,18 +625,37 @@ static int hotkey_config_seq_show(struct seq_file *seq, void *offset)
 				      ACPI_NAME_TYPE_MAX, &bus);
 			acpi_get_name(key->event_hotkey.action_handle,
 				      ACPI_NAME_TYPE_MAX, &act);
-			seq_printf(seq, "%s:%s:%s:%d:%d", bus_name,
+			seq_printf(seq, "%s:%s:%s:%d:%d\n", bus_name,
 				   action_name,
 				   key->event_hotkey.action_method,
 				   key->link.hotkey_standard_num,
 				   key->event_hotkey.external_hotkey_num);
-		} /* ACPI_HOTKEY_POLLING */
-		else {
+		}
+	}
+	seq_puts(seq, "\n");
+	return_VALUE(0);
+}
+
+static int hotkey_poll_config_seq_show(struct seq_file *seq, void *offset)
+{
+	struct acpi_hotkey_list *hotkey_list = &global_hotkey_list;
+	struct list_head *entries;
+	char bus_name[ACPI_PATHNAME_MAX] = { 0 };
+	char action_name[ACPI_PATHNAME_MAX] = { 0 };
+	struct acpi_buffer bus = { ACPI_PATHNAME_MAX, bus_name };
+	struct acpi_buffer act = { ACPI_PATHNAME_MAX, action_name };
+
+	ACPI_FUNCTION_TRACE(("hotkey_config_seq_show"));
+
+	list_for_each(entries, hotkey_list->entries) {
+		union acpi_hotkey *key =
+		    container_of(entries, union acpi_hotkey, entries);
+		if (key->link.hotkey_type == ACPI_HOTKEY_POLLING) {
 			acpi_get_name(key->poll_hotkey.poll_handle,
 				      ACPI_NAME_TYPE_MAX, &bus);
 			acpi_get_name(key->poll_hotkey.action_handle,
 				      ACPI_NAME_TYPE_MAX, &act);
-			seq_printf(seq, "%s:%s:%s:%s:%d", bus_name,
+			seq_printf(seq, "%s:%s:%s:%s:%d\n", bus_name,
 				   key->poll_hotkey.poll_method,
 				   action_name,
 				   key->poll_hotkey.action_method,
@@ -572,49 +663,83 @@ static int hotkey_config_seq_show(struct seq_file *seq, void *offset)
 		}
 	}
 	seq_puts(seq, "\n");
-      end:
 	return_VALUE(0);
 }
 
 static int
 get_parms(char *config_record,
 	  int *cmd,
-	  char *bus_handle,
-	  char *bus_method,
-	  char *action_handle,
-	  char *method, int *internal_event_num, int *external_event_num)
+	  char **bus_handle,
+	  char **bus_method,
+	  char **action_handle,
+	  char **method, int *internal_event_num, int *external_event_num)
 {
-	char *tmp, *tmp1;
+	char *tmp, *tmp1, count;
 	ACPI_FUNCTION_TRACE(("get_parms"));
 
 	sscanf(config_record, "%d", cmd);
 
+	if(*cmd == 1){
+		if(sscanf(config_record, "%d:%d", cmd, internal_event_num)!=2)
+			goto do_fail;
+		else
+			return (6);
+	}
 	tmp = strchr(config_record, ':');
+	if (!tmp)
+		goto do_fail;
 	tmp++;
 	tmp1 = strchr(tmp, ':');
-	strncpy(bus_handle, tmp, tmp1 - tmp);
-	bus_handle[tmp1 - tmp] = 0;
+	if (!tmp1)
+		goto do_fail;
+
+	count = tmp1 - tmp;
+	*bus_handle = (char *) kmalloc(count+1, GFP_KERNEL);
+	if(!*bus_handle)
+		goto do_fail;
+	strncpy(*bus_handle, tmp, count);
+	*(*bus_handle + count) = 0;
 
 	tmp = tmp1;
 	tmp++;
 	tmp1 = strchr(tmp, ':');
-	strncpy(bus_method, tmp, tmp1 - tmp);
-	bus_method[tmp1 - tmp] = 0;
+	if (!tmp1)
+		goto do_fail;
+	count = tmp1 - tmp;
+	*bus_method = (char *) kmalloc(count+1, GFP_KERNEL);
+	if(!*bus_method)
+		goto do_fail;
+	strncpy(*bus_method, tmp, count);
+	*(*bus_method + count) = 0;
 
 	tmp = tmp1;
 	tmp++;
 	tmp1 = strchr(tmp, ':');
-	strncpy(action_handle, tmp, tmp1 - tmp);
-	action_handle[tmp1 - tmp] = 0;
+	if (!tmp1)
+		goto do_fail;
+	count = tmp1 - tmp;
+	*action_handle = (char *) kmalloc(count+1, GFP_KERNEL);
+	strncpy(*action_handle, tmp, count);
+	*(*action_handle + count) = 0;
 
 	tmp = tmp1;
 	tmp++;
 	tmp1 = strchr(tmp, ':');
-	strncpy(method, tmp, tmp1 - tmp);
-	method[tmp1 - tmp] = 0;
+	if (!tmp1)
+		goto do_fail;
+	count = tmp1 - tmp;
+	*method = (char *) kmalloc(count+1, GFP_KERNEL);
+	if(!*method)
+		goto do_fail;
+	strncpy(*method, tmp, count);
+	*(*method + count) = 0;
+
+	if(sscanf(tmp1 + 1, "%d:%d", internal_event_num, external_event_num)<=0)
+		goto do_fail;
 
-	sscanf(tmp1 + 1, "%d:%d", internal_event_num, external_event_num);
 	return_VALUE(6);
+do_fail:
+	return_VALUE(-1);
 }
 
 /*  count is length for one input record */
@@ -622,135 +747,117 @@ static ssize_t hotkey_write_config(struct file *file,
 				   const char __user * buffer,
 				   size_t count, loff_t * data)
 {
-	struct acpi_hotkey_list *hotkey_list = &global_hotkey_list;
-	char config_record[MAX_CONFIG_RECORD_LEN];
-	char bus_handle[MAX_NAME_PATH_LEN];
-	char bus_method[MAX_NAME_PATH_LEN];
-	char action_handle[MAX_NAME_PATH_LEN];
-	char method[20];
+	char *config_record = NULL;
+	char *bus_handle = NULL;
+	char *bus_method = NULL;
+	char *action_handle = NULL;
+	char *method = NULL;
 	int cmd, internal_event_num, external_event_num;
 	int ret = 0;
 	union acpi_hotkey *key = NULL;
 
 	ACPI_FUNCTION_TRACE(("hotkey_write_config"));
 
-	if (!hotkey_list || count > MAX_CONFIG_RECORD_LEN) {
-		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid arguments\n"));
-		return_VALUE(-EINVAL);
-	}
+	config_record = (char *) kmalloc(count+1, GFP_KERNEL);
+	if(!config_record)
+		return_VALUE(-ENOMEM);
 
 	if (copy_from_user(config_record, buffer, count)) {
+		kfree(config_record);
 		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid data \n"));
 		return_VALUE(-EINVAL);
 	}
-	config_record[count] = '\0';
+	config_record[count] = 0;
 
 	ret = get_parms(config_record,
 			&cmd,
-			bus_handle,
-			bus_method,
-			action_handle,
-			method, &internal_event_num, &external_event_num);
+			&bus_handle,
+			&bus_method,
+			&action_handle,
+			&method, &internal_event_num, &external_event_num);
+
+	kfree(config_record);
+	if(IS_OTHERS(internal_event_num))
+		goto do_fail;
 	if (ret != 6) {
+do_fail:	
+		kfree(bus_handle);
+		kfree(bus_method);
+		kfree(action_handle);
+		kfree(method);
 		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
 				  "Invalid data format ret=%d\n", ret));
 		return_VALUE(-EINVAL);
 	}
 
 	key = kmalloc(sizeof(union acpi_hotkey), GFP_KERNEL);
-	ret = init_hotkey_device(key, bus_handle, action_handle, method,
+	if(!key)
+		goto do_fail;
+	memset(key, 0, sizeof(union acpi_hotkey));
+	if(cmd == 1) {
+		union acpi_hotkey *tmp = NULL;
+		tmp = get_hotkey_by_event(&global_hotkey_list,
+				internal_event_num);
+		if(!tmp)
+			ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid key"));
+		else
+			memcpy(key, tmp, sizeof(union acpi_hotkey));
+		goto cont_cmd;
+	}
+	if (IS_EVENT(internal_event_num)) {
+		kfree(bus_method);
+		ret = init_hotkey_device(key, bus_handle, action_handle, method,
 				 internal_event_num, external_event_num);
-
-	if (ret || check_hotkey_valid(key, hotkey_list)) {
+	} else
+		ret = init_poll_hotkey_device(key, bus_handle, bus_method,
+				      action_handle, method,
+				      internal_event_num);
+	if (ret) {
+		kfree(bus_handle);
+		kfree(action_handle);
+		if(IS_EVENT(internal_event_num))
+			free_hotkey_buffer(key);
+		else
+			free_poll_hotkey_buffer(key);
 		kfree(key);
 		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid hotkey \n"));
 		return_VALUE(-EINVAL);
 	}
-	switch (cmd) {
-	case 0:
-		hotkey_add(key);
-		break;
-	case 1:
-		hotkey_remove(key);
-		free_hotkey_device(key);
-		break;
-	case 2:
-		hotkey_update(key);
-		break;
-	default:
-		break;
-	}
-	return_VALUE(count);
-}
-
-/*  count is length for one input record */
-static ssize_t hotkey_write_poll_config(struct file *file,
-					const char __user * buffer,
-					size_t count, loff_t * data)
-{
-	struct seq_file *m = (struct seq_file *)file->private_data;
-	struct acpi_hotkey_list *hotkey_list =
-	    (struct acpi_hotkey_list *)m->private;
-
-	char config_record[MAX_CONFIG_RECORD_LEN];
-	char polling_handle[MAX_NAME_PATH_LEN];
-	char action_handle[MAX_NAME_PATH_LEN];
-	char poll_method[20], action_method[20];
-	int ret, internal_event_num, cmd, external_event_num;
-	union acpi_hotkey *key = NULL;
-
-	ACPI_FUNCTION_TRACE("hotkey_write_poll_config");
-
-	if (!hotkey_list || count > MAX_CONFIG_RECORD_LEN) {
-		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid arguments\n"));
-		return_VALUE(-EINVAL);
-	}
-
-	if (copy_from_user(config_record, buffer, count)) {
-		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid data \n"));
-		return_VALUE(-EINVAL);
-	}
-	config_record[count] = '\0';
 
-	ret = get_parms(config_record,
-			&cmd,
-			polling_handle,
-			poll_method,
-			action_handle,
-			action_method,
-			&internal_event_num, &external_event_num);
-
-	if (ret != 6) {
-		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid data format\n"));
-		return_VALUE(-EINVAL);
-	}
+cont_cmd:
+	kfree(bus_handle);
+	kfree(action_handle);
 
-	key = kmalloc(sizeof(union acpi_hotkey), GFP_KERNEL);
-	ret = init_poll_hotkey_device(key, polling_handle, poll_method,
-				      action_handle, action_method,
-				      internal_event_num);
-	if (ret || check_hotkey_valid(key, hotkey_list)) {
-		kfree(key);
-		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid hotkey \n"));
-		return_VALUE(-EINVAL);
-	}
 	switch (cmd) {
 	case 0:
-		hotkey_add(key);
+		if(get_hotkey_by_event(&global_hotkey_list,key->link.hotkey_standard_num))
+			goto fail_out;
+		else
+			hotkey_add(key);
 		break;
 	case 1:
 		hotkey_remove(key);
 		break;
 	case 2:
-		hotkey_update(key);
+		if(hotkey_update(key))
+			goto fail_out;
 		break;
 	default:
+		goto fail_out;
 		break;
 	}
 	return_VALUE(count);
+fail_out:
+	if(IS_EVENT(internal_event_num))
+		free_hotkey_buffer(key);
+	else
+		free_poll_hotkey_buffer(key);
+	kfree(key);
+	ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "invalid key\n"));
+	return_VALUE(-EINVAL);
 }
 
-/*  
+/*
  * This function evaluates an ACPI method, given an int as parameter, the
  * method is searched within the scope of the handle, can be NULL. The output
  * of the method is written is output, which can also be NULL
@@ -775,7 +882,7 @@ static int write_acpi_int(acpi_handle handle, const char *method, int val,
 	return_VALUE(status == AE_OK);
 }
 
-static int read_acpi_int(acpi_handle handle, const char *method, int *val)
+static int read_acpi_int(acpi_handle handle, const char *method, union acpi_object *val)
 {
 	struct acpi_buffer output;
 	union acpi_object out_obj;
@@ -786,62 +893,32 @@ static int read_acpi_int(acpi_handle handle, const char *method, int *val)
 	output.pointer = &out_obj;
 
 	status = acpi_evaluate_object(handle, (char *)method, NULL, &output);
-	*val = out_obj.integer.value;
+	if(val){
+		val->integer.value = out_obj.integer.value;
+		val->type = out_obj.type;
+	} else
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "null val pointer"));
 	return_VALUE((status == AE_OK)
 		     && (out_obj.type == ACPI_TYPE_INTEGER));
 }
 
-static acpi_handle
-get_handle_from_hotkeylist(struct acpi_hotkey_list *hotkey_list, int event_num)
+static union acpi_hotkey *get_hotkey_by_event(struct
+			      acpi_hotkey_list
+			      *hotkey_list, int event)
 {
-	struct list_head *entries, *next;
-
-	list_for_each_safe(entries, next, hotkey_list->entries) {
-		union acpi_hotkey *key =
-		    container_of(entries, union acpi_hotkey, entries);
-		if (key->link.hotkey_type == ACPI_HOTKEY_EVENT
-		    && key->link.hotkey_standard_num == event_num) {
-			return (key->event_hotkey.action_handle);
-		}
-	}
-	return (NULL);
-}
-
-static
-char *get_method_from_hotkeylist(struct acpi_hotkey_list *hotkey_list,
-				 int event_num)
-{
-	struct list_head *entries, *next;
-
-	list_for_each_safe(entries, next, hotkey_list->entries) {
-		union acpi_hotkey *key =
-		    container_of(entries, union acpi_hotkey, entries);
-
-		if (key->link.hotkey_type == ACPI_HOTKEY_EVENT &&
-		    key->link.hotkey_standard_num == event_num)
-			return (key->event_hotkey.action_method);
-	}
-	return (NULL);
-}
-
-static struct acpi_polling_hotkey *get_hotkey_by_event(struct
-						       acpi_hotkey_list
-						       *hotkey_list, int event)
-{
-	struct list_head *entries, *next;
+	struct list_head *entries;
 
-	list_for_each_safe(entries, next, hotkey_list->entries) {
+	list_for_each(entries, hotkey_list->entries) {
 		union acpi_hotkey *key =
 		    container_of(entries, union acpi_hotkey, entries);
-		if (key->link.hotkey_type == ACPI_HOTKEY_POLLING
-		    && key->link.hotkey_standard_num == event) {
-			return (&key->poll_hotkey);
+		if (key->link.hotkey_standard_num == event) {
+			return(key);
 		}
 	}
-	return (NULL);
+	return(NULL);
 }
 
-/*  
+/*
  * user call AML method interface:
  * Call convention:
  * echo "event_num: arg type : value"
@@ -854,48 +931,56 @@ static ssize_t hotkey_execute_aml_method(struct file *file,
 					 size_t count, loff_t * data)
 {
 	struct acpi_hotkey_list *hotkey_list = &global_hotkey_list;
-	char arg[MAX_CALL_PARM];
-	int event, type, value;
-
-	char *method;
-	acpi_handle handle;
+	char *arg;
+	int event,method_type,type, value;
+	union acpi_hotkey *key;
 
 	ACPI_FUNCTION_TRACE("hotkey_execte_aml_method");
 
-	if (!hotkey_list || count > MAX_CALL_PARM) {
-		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid argument 1"));
-		return_VALUE(-EINVAL);
-	}
+	arg = (char *) kmalloc(count+1, GFP_KERNEL);
+	if(!arg)
+		return_VALUE(-ENOMEM);
+	arg[count]=0;
 
 	if (copy_from_user(arg, buffer, count)) {
+		kfree(arg);
 		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid argument 2"));
 		return_VALUE(-EINVAL);
 	}
 
-	arg[count] = '\0';
-
-	if (sscanf(arg, "%d:%d:%d", &event, &type, &value) != 3) {
+	if (sscanf(arg, "%d:%d:%d:%d", &event, &method_type, &type, &value) != 4) {
+		kfree(arg);
 		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid argument 3"));
 		return_VALUE(-EINVAL);
 	}
-
+	kfree(arg);
 	if (type == ACPI_TYPE_INTEGER) {
-		handle = get_handle_from_hotkeylist(hotkey_list, event);
-		method = (char *)get_method_from_hotkeylist(hotkey_list, event);
+		key = get_hotkey_by_event(hotkey_list, event);
+		if(!key)
+			goto do_fail;
 		if (IS_EVENT(event))
-			write_acpi_int(handle, method, value, NULL);
+			write_acpi_int(key->event_hotkey.action_handle,
+					key->event_hotkey.action_method, value, NULL);
 		else if (IS_POLL(event)) {
-			struct acpi_polling_hotkey *key;
-			key = (struct acpi_polling_hotkey *)
-			    get_hotkey_by_event(hotkey_list, event);
-			read_acpi_int(handle, method, key->poll_result);
+			if ( method_type == POLL_METHOD )
+				read_acpi_int(key->poll_hotkey.poll_handle,
+					key->poll_hotkey.poll_method,
+					key->poll_hotkey.poll_result);
+			else if ( method_type == ACTION_METHOD )
+				write_acpi_int(key->poll_hotkey.action_handle,
+					key->poll_hotkey.action_method, value, NULL);
+			else
+				goto do_fail;
+
 		}
 	} else {
 		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Not supported"));
 		return_VALUE(-EINVAL);
 	}
-
 	return_VALUE(count);
+do_fail:
+	return_VALUE(-EINVAL);
+
 }
 
 static int __init hotkey_init(void)
@@ -928,7 +1013,7 @@ static int __init hotkey_init(void)
 		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
 				  "Hotkey: Unable to create %s entry\n",
 				  HOTKEY_EV_CONFIG));
-		return (-ENODEV);
+		goto do_fail1;
 	} else {
 		hotkey_config->proc_fops = &hotkey_config_fops;
 		hotkey_config->data = &global_hotkey_list;
@@ -943,7 +1028,8 @@ static int __init hotkey_init(void)
 		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
 				  "Hotkey: Unable to create %s entry\n",
 				  HOTKEY_EV_CONFIG));
-		return (-ENODEV);
+
+		goto do_fail2;
 	} else {
 		hotkey_poll_config->proc_fops = &hotkey_poll_config_fops;
 		hotkey_poll_config->data = &global_hotkey_list;
@@ -957,7 +1043,7 @@ static int __init hotkey_init(void)
 		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
 				  "Hotkey: Unable to create %s entry\n",
 				  HOTKEY_ACTION));
-		return (-ENODEV);
+		goto do_fail3;
 	} else {
 		hotkey_action->proc_fops = &hotkey_action_fops;
 		hotkey_action->owner = THIS_MODULE;
@@ -970,7 +1056,7 @@ static int __init hotkey_init(void)
 		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
 				  "Hotkey: Unable to create %s entry\n",
 				  HOTKEY_INFO));
-		return (-ENODEV);
+		goto do_fail4;
 	} else {
 		hotkey_info->proc_fops = &hotkey_info_fops;
 		hotkey_info->owner = THIS_MODULE;
@@ -979,23 +1065,33 @@ static int __init hotkey_init(void)
 	}
 
 	result = acpi_bus_register_driver(&hotkey_driver);
-	if (result < 0) {
-		remove_proc_entry(HOTKEY_PROC, acpi_root_dir);
-		return (-ENODEV);
-	}
+	if (result < 0)
+		goto do_fail5;
 	global_hotkey_list.count = 0;
 	global_hotkey_list.entries = &hotkey_entries;
 
 	INIT_LIST_HEAD(&hotkey_entries);
 
 	return (0);
+
+do_fail5:
+	remove_proc_entry(HOTKEY_INFO, hotkey_proc_dir);
+do_fail4:
+	remove_proc_entry(HOTKEY_ACTION, hotkey_proc_dir);
+do_fail3:
+	remove_proc_entry(HOTKEY_PL_CONFIG, hotkey_proc_dir);
+do_fail2:
+	remove_proc_entry(HOTKEY_EV_CONFIG, hotkey_proc_dir);
+do_fail1:
+	remove_proc_entry(HOTKEY_PROC, acpi_root_dir);
+	return (-ENODEV);
 }
 
 static void __exit hotkey_exit(void)
 {
 	struct list_head *entries, *next;
 
-	ACPI_FUNCTION_TRACE("hotkey_remove");
+	ACPI_FUNCTION_TRACE("hotkey_exit");
 
 	list_for_each_safe(entries, next, global_hotkey_list.entries) {
 		union acpi_hotkey *key =
diff --git a/drivers/acpi/motherboard.c b/drivers/acpi/motherboard.c
index 61ea70742d4..2934475d67d 100644
--- a/drivers/acpi/motherboard.c
+++ b/drivers/acpi/motherboard.c
@@ -43,7 +43,7 @@ ACPI_MODULE_NAME		("acpi_motherboard")
  */
 #define IS_RESERVED_ADDR(base, len) \
 	(((len) > 0) && ((base) > 0) && ((base) + (len) < IO_SPACE_LIMIT) \
-	&& ((base) + (len) > PCIBIOS_MIN_IO))
+	&& ((base) + (len) > 0x1000))
 
 /*
  * Clearing the flag (IORESOURCE_BUSY) allows drivers to use
diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c
index bdd9f37f810..7289da3c4db 100644
--- a/drivers/acpi/osl.c
+++ b/drivers/acpi/osl.c
@@ -145,10 +145,14 @@ acpi_os_vprintf(const char *fmt, va_list args)
 #endif
 }
 
+extern int acpi_in_resume;
 void *
 acpi_os_allocate(acpi_size size)
 {
-	return kmalloc(size, GFP_KERNEL);
+	if (acpi_in_resume)
+		return kmalloc(size, GFP_ATOMIC);
+	else
+		return kmalloc(size, GFP_KERNEL);
 }
 
 void
diff --git a/drivers/acpi/pci_irq.c b/drivers/acpi/pci_irq.c
index d1f42b97282..bb973d2109a 100644
--- a/drivers/acpi/pci_irq.c
+++ b/drivers/acpi/pci_irq.c
@@ -269,7 +269,51 @@ acpi_pci_irq_del_prt (int segment, int bus)
 /* --------------------------------------------------------------------------
                           PCI Interrupt Routing Support
    -------------------------------------------------------------------------- */
+typedef int (*irq_lookup_func)(struct acpi_prt_entry *, int *, int *, char **);
 
+static int
+acpi_pci_allocate_irq(struct acpi_prt_entry *entry,
+	int	*edge_level,
+	int	*active_high_low,
+	char	**link)
+{
+	int	irq;
+
+	ACPI_FUNCTION_TRACE("acpi_pci_allocate_irq");
+
+	if (entry->link.handle) {
+		irq = acpi_pci_link_allocate_irq(entry->link.handle,
+			entry->link.index, edge_level, active_high_low, link);
+		if (irq < 0) {
+			ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Invalid IRQ link routing entry\n"));
+			return_VALUE(-1);
+		}
+	} else {
+		irq = entry->link.index;
+		*edge_level = ACPI_LEVEL_SENSITIVE;
+		*active_high_low = ACPI_ACTIVE_LOW;
+	}
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found IRQ %d\n", irq));
+	return_VALUE(irq);
+}
+
+static int
+acpi_pci_free_irq(struct acpi_prt_entry *entry,
+	int	*edge_level,
+	int	*active_high_low,
+	char	**link)
+{
+	int	irq;
+
+	ACPI_FUNCTION_TRACE("acpi_pci_free_irq");
+	if (entry->link.handle) {
+		irq = acpi_pci_link_free_irq(entry->link.handle);
+	} else {
+		irq = entry->link.index;
+	}
+	return_VALUE(irq);
+}
 /*
  * acpi_pci_irq_lookup
  * success: return IRQ >= 0
@@ -282,12 +326,13 @@ acpi_pci_irq_lookup (
 	int			pin,
 	int			*edge_level,
 	int			*active_high_low,
-	char			**link)
+	char			**link,
+	irq_lookup_func		func)
 {
 	struct acpi_prt_entry	*entry = NULL;
 	int segment = pci_domain_nr(bus);
 	int bus_nr = bus->number;
-	int irq;
+	int ret;
 
 	ACPI_FUNCTION_TRACE("acpi_pci_irq_lookup");
 
@@ -301,22 +346,8 @@ acpi_pci_irq_lookup (
 		return_VALUE(-1);
 	}
 	
-	if (entry->link.handle) {
-		irq = acpi_pci_link_get_irq(entry->link.handle,
-			entry->link.index, edge_level, active_high_low, link);
-		if (irq < 0) {
-			ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Invalid IRQ link routing entry\n"));
-			return_VALUE(-1);
-		}
-	} else {
-		irq = entry->link.index;
-		*edge_level = ACPI_LEVEL_SENSITIVE;
-		*active_high_low = ACPI_ACTIVE_LOW;
-	}
-
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found IRQ %d\n", irq));
-
-	return_VALUE(irq);
+	ret = func(entry, edge_level, active_high_low, link);
+	return_VALUE(ret);
 }
 
 /*
@@ -330,7 +361,8 @@ acpi_pci_irq_derive (
 	int			pin,
 	int			*edge_level,
 	int			*active_high_low,
-	char			**link)
+	char			**link,
+	irq_lookup_func		func)
 {
 	struct pci_dev		*bridge = dev;
 	int			irq = -1;
@@ -363,7 +395,7 @@ acpi_pci_irq_derive (
 		}
 
 		irq = acpi_pci_irq_lookup(bridge->bus, PCI_SLOT(bridge->devfn),
-			pin, edge_level, active_high_low, link);
+			pin, edge_level, active_high_low, link, func);
 	}
 
 	if (irq < 0) {
@@ -415,7 +447,7 @@ acpi_pci_irq_enable (
 	 * values override any BIOS-assigned IRQs set during boot.
 	 */
  	irq = acpi_pci_irq_lookup(dev->bus, PCI_SLOT(dev->devfn), pin,
-		&edge_level, &active_high_low, &link);
+		&edge_level, &active_high_low, &link, acpi_pci_allocate_irq);
 
 	/*
 	 * If no PRT entry was found, we'll try to derive an IRQ from the
@@ -423,7 +455,7 @@ acpi_pci_irq_enable (
 	 */
 	if (irq < 0)
  		irq = acpi_pci_irq_derive(dev, pin, &edge_level,
-			&active_high_low, &link);
+			&active_high_low, &link, acpi_pci_allocate_irq);
  
 	/*
 	 * No IRQ known to the ACPI subsystem - maybe the BIOS / 
@@ -462,7 +494,9 @@ acpi_pci_irq_enable (
 EXPORT_SYMBOL(acpi_pci_irq_enable);
 
 
-#ifdef CONFIG_ACPI_DEALLOCATE_IRQ
+/* FIXME: implement x86/x86_64 version */
+void __attribute__((weak)) acpi_unregister_gsi(u32 i) {}
+
 void
 acpi_pci_irq_disable (
 	struct pci_dev		*dev)
@@ -489,14 +523,14 @@ acpi_pci_irq_disable (
 	 * First we check the PCI IRQ routing table (PRT) for an IRQ.
 	 */
  	gsi = acpi_pci_irq_lookup(dev->bus, PCI_SLOT(dev->devfn), pin,
-				  &edge_level, &active_high_low, NULL);
+			&edge_level, &active_high_low, NULL, acpi_pci_free_irq);
 	/*
 	 * If no PRT entry was found, we'll try to derive an IRQ from the
 	 * device's parent bridge.
 	 */
 	if (gsi < 0)
  		gsi = acpi_pci_irq_derive(dev, pin,
-					  &edge_level, &active_high_low, NULL);
+			&edge_level, &active_high_low, NULL, acpi_pci_free_irq);
 	if (gsi < 0)
 		return_VOID;
 
@@ -512,4 +546,3 @@ acpi_pci_irq_disable (
 
 	return_VOID;
 }
-#endif /* CONFIG_ACPI_DEALLOCATE_IRQ */
diff --git a/drivers/acpi/pci_link.c b/drivers/acpi/pci_link.c
index 6ad0e77df9b..834c2ceff1a 100644
--- a/drivers/acpi/pci_link.c
+++ b/drivers/acpi/pci_link.c
@@ -68,6 +68,10 @@ static struct acpi_driver acpi_pci_link_driver = {
 			},
 };
 
+/*
+ * If a link is initialized, we never change its active and initialized
+ * later even the link is disable. Instead, we just repick the active irq
+ */
 struct acpi_pci_link_irq {
 	u8			active;			/* Current IRQ */
 	u8			edge_level;		/* All IRQs */
@@ -76,8 +80,7 @@ struct acpi_pci_link_irq {
 	u8			possible_count;
 	u8			possible[ACPI_PCI_LINK_MAX_POSSIBLE];
 	u8			initialized:1;
-	u8			suspend_resume:1;
-	u8			reserved:6;
+	u8			reserved:7;
 };
 
 struct acpi_pci_link {
@@ -85,12 +88,14 @@ struct acpi_pci_link {
 	struct acpi_device	*device;
 	acpi_handle		handle;
 	struct acpi_pci_link_irq irq;
+	int			refcnt;
 };
 
 static struct {
 	int			count;
 	struct list_head	entries;
 }				acpi_link;
+DECLARE_MUTEX(acpi_link_lock);
 
 
 /* --------------------------------------------------------------------------
@@ -532,12 +537,12 @@ static int acpi_pci_link_allocate(
 
 	ACPI_FUNCTION_TRACE("acpi_pci_link_allocate");
 
-	if (link->irq.suspend_resume) {
-		acpi_pci_link_set(link, link->irq.active);
-		link->irq.suspend_resume = 0;
-	}
-	if (link->irq.initialized)
+	if (link->irq.initialized) {
+		if (link->refcnt == 0)
+			/* This means the link is disabled but initialized */
+			acpi_pci_link_set(link, link->irq.active);
 		return_VALUE(0);
+	}
 
 	/*
 	 * search for active IRQ in list of possible IRQs.
@@ -596,13 +601,13 @@ static int acpi_pci_link_allocate(
 }
 
 /*
- * acpi_pci_link_get_irq
+ * acpi_pci_link_allocate_irq
  * success: return IRQ >= 0
  * failure: return -1
  */
 
 int
-acpi_pci_link_get_irq (
+acpi_pci_link_allocate_irq (
 	acpi_handle		handle,
 	int			index,
 	int			*edge_level,
@@ -613,7 +618,7 @@ acpi_pci_link_get_irq (
 	struct acpi_device	*device = NULL;
 	struct acpi_pci_link	*link = NULL;
 
-	ACPI_FUNCTION_TRACE("acpi_pci_link_get_irq");
+	ACPI_FUNCTION_TRACE("acpi_pci_link_allocate_irq");
 
 	result = acpi_bus_get_device(handle, &device);
 	if (result) {
@@ -633,21 +638,81 @@ acpi_pci_link_get_irq (
 		return_VALUE(-1);
 	}
 
-	if (acpi_pci_link_allocate(link))
+	down(&acpi_link_lock);
+	if (acpi_pci_link_allocate(link)) {
+		up(&acpi_link_lock);
 		return_VALUE(-1);
+	}
 	   
 	if (!link->irq.active) {
+		up(&acpi_link_lock);
 		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Link active IRQ is 0!\n"));
 		return_VALUE(-1);
 	}
+	link->refcnt ++;
+	up(&acpi_link_lock);
 
 	if (edge_level) *edge_level = link->irq.edge_level;
 	if (active_high_low) *active_high_low = link->irq.active_high_low;
 	if (name) *name = acpi_device_bid(link->device);
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+		"Link %s is referenced\n", acpi_device_bid(link->device)));
 	return_VALUE(link->irq.active);
 }
 
+/*
+ * We don't change link's irq information here.  After it is reenabled, we
+ * continue use the info
+ */
+int
+acpi_pci_link_free_irq(acpi_handle handle)
+{
+	struct acpi_device	*device = NULL;
+	struct acpi_pci_link	*link = NULL;
+	acpi_status		result;
+
+	ACPI_FUNCTION_TRACE("acpi_pci_link_free_irq");
+
+	result = acpi_bus_get_device(handle, &device);
+	if (result) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid link device\n"));
+		return_VALUE(-1);
+	}
+
+	link = (struct acpi_pci_link *) acpi_driver_data(device);
+	if (!link) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid link context\n"));
+		return_VALUE(-1);
+	}
+
+	down(&acpi_link_lock);
+	if (!link->irq.initialized) {
+		up(&acpi_link_lock);
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Link isn't initialized\n"));
+		return_VALUE(-1);
+	}
 
+#ifdef	FUTURE_USE
+	/*
+	 * The Link reference count allows us to _DISable an unused link
+	 * and suspend time, and set it again  on resume.
+	 * However, 2.6.12 still has irq_router.resume
+	 * which blindly restores the link state.
+	 * So we disable the reference count method
+	 * to prevent duplicate acpi_pci_link_set()
+	 * which would harm some systems
+	 */
+	link->refcnt --;
+#endif
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+		"Link %s is dereferenced\n", acpi_device_bid(link->device)));
+
+	if (link->refcnt == 0) {
+		acpi_ut_evaluate_object(link->handle, "_DIS", 0, NULL);
+	}
+	up(&acpi_link_lock);
+	return_VALUE(link->irq.active);
+}
 /* --------------------------------------------------------------------------
                                  Driver Interface
    -------------------------------------------------------------------------- */
@@ -677,6 +742,7 @@ acpi_pci_link_add (
 	strcpy(acpi_device_class(device), ACPI_PCI_LINK_CLASS);
 	acpi_driver_data(device) = link;
 
+	down(&acpi_link_lock);
 	result = acpi_pci_link_get_possible(link);
 	if (result)
 		goto end;
@@ -712,6 +778,7 @@ acpi_pci_link_add (
 end:
 	/* disable all links -- to be activated on use */
 	acpi_ut_evaluate_object(link->handle, "_DIS", 0, NULL);
+	up(&acpi_link_lock);
 
 	if (result)
 		kfree(link);
@@ -720,24 +787,42 @@ end:
 }
 
 static int
-irqrouter_suspend(
-	struct sys_device *dev,
-	u32	state)
+acpi_pci_link_resume(
+	struct acpi_pci_link *link)
+{
+	ACPI_FUNCTION_TRACE("acpi_pci_link_resume");
+
+	if (link->refcnt && link->irq.active && link->irq.initialized)
+		return_VALUE(acpi_pci_link_set(link, link->irq.active));
+	else
+		return_VALUE(0);
+}
+
+/*
+ * FIXME: this is a workaround to avoid nasty warning.  It will be removed
+ * after every device calls pci_disable_device in .resume.
+ */
+int acpi_in_resume;
+static int
+irqrouter_resume(
+	struct sys_device *dev)
 {
 	struct list_head        *node = NULL;
 	struct acpi_pci_link    *link = NULL;
 
-	ACPI_FUNCTION_TRACE("irqrouter_suspend");
+	ACPI_FUNCTION_TRACE("irqrouter_resume");
 
+	acpi_in_resume = 1;
 	list_for_each(node, &acpi_link.entries) {
 		link = list_entry(node, struct acpi_pci_link, node);
 		if (!link) {
-			ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid link context\n"));
+			ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+				"Invalid link context\n"));
 			continue;
 		}
-		if (link->irq.active && link->irq.initialized)
-			link->irq.suspend_resume = 1;
+		acpi_pci_link_resume(link);
 	}
+	acpi_in_resume = 0;
 	return_VALUE(0);
 }
 
@@ -756,8 +841,9 @@ acpi_pci_link_remove (
 
 	link = (struct acpi_pci_link *) acpi_driver_data(device);
 
-	/* TBD: Acquire/release lock */
+	down(&acpi_link_lock);
 	list_del(&link->node);
+	up(&acpi_link_lock);
 
 	kfree(link);
 
@@ -849,9 +935,10 @@ int __init acpi_irq_balance_set(char *str)
 __setup("acpi_irq_balance", acpi_irq_balance_set);
 
 
+/* FIXME: we will remove this interface after all drivers call pci_disable_device */
 static struct sysdev_class irqrouter_sysdev_class = {
         set_kset_name("irqrouter"),
-        .suspend = irqrouter_suspend,
+        .resume = irqrouter_resume,
 };
 
 
diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
index 893b074e3d1..2c04740c654 100644
--- a/drivers/acpi/processor_idle.c
+++ b/drivers/acpi/processor_idle.c
@@ -81,30 +81,32 @@ module_param(bm_history, uint, 0644);
  *
  * To skip this limit, boot/load with a large max_cstate limit.
  */
-static int no_c2c3(struct dmi_system_id *id)
+static int set_max_cstate(struct dmi_system_id *id)
 {
 	if (max_cstate > ACPI_PROCESSOR_MAX_POWER)
 		return 0;
 
-	printk(KERN_NOTICE PREFIX "%s detected - C2,C3 disabled."
+	printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate."
 		" Override with \"processor.max_cstate=%d\"\n", id->ident,
-	       ACPI_PROCESSOR_MAX_POWER + 1);
+		(long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1);
 
-	max_cstate = 1;
+	max_cstate = (long)id->driver_data;
 
 	return 0;
 }
 
 
-
-
 static struct dmi_system_id __initdata processor_power_dmi_table[] = {
-	{ no_c2c3, "IBM ThinkPad R40e", {
+	{ set_max_cstate, "IBM ThinkPad R40e", {
 	  DMI_MATCH(DMI_BIOS_VENDOR,"IBM"),
-	  DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW") }},
-	{ no_c2c3, "Medion 41700", {
+	  DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW") }, (void*)1},
+	{ set_max_cstate, "Medion 41700", {
+	  DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"),
+	  DMI_MATCH(DMI_BIOS_VERSION,"R01-A1J") }, (void*)1},
+	{ set_max_cstate, "Clevo 5600D", {
 	  DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"),
-	  DMI_MATCH(DMI_BIOS_VERSION,"R01-A1J") }},
+	  DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307") },
+	  (void*)2},
 	{},
 };
 
@@ -549,7 +551,8 @@ static int acpi_processor_get_power_info_default_c1 (struct acpi_processor *pr)
 	ACPI_FUNCTION_TRACE("acpi_processor_get_power_info_default_c1");
 
 	for (i = 0; i < ACPI_PROCESSOR_MAX_POWER; i++)
-		memset(pr->power.states, 0, sizeof(struct acpi_processor_cx));
+		memset(&(pr->power.states[i]), 0, 
+		       sizeof(struct acpi_processor_cx));
 
 	/* if info is obtained from pblk/fadt, type equals state */
 	pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1;
@@ -580,7 +583,8 @@ static int acpi_processor_get_power_info_cst (struct acpi_processor *pr)
 
 	pr->power.count = 0;
 	for (i = 0; i < ACPI_PROCESSOR_MAX_POWER; i++)
-		memset(pr->power.states, 0, sizeof(struct acpi_processor_cx));
+		memset(&(pr->power.states[i]), 0, 
+		       sizeof(struct acpi_processor_cx));
 
 	status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer);
 	if (ACPI_FAILURE(status)) {
@@ -763,7 +767,6 @@ static void acpi_processor_power_verify_c3(
 	}
 
 	if (pr->flags.bm_check) {
-		printk("Disabling BM access before entering C3\n");
 		/* bus mastering control is necessary */
 		if (!pr->flags.bm_control) {
 			ACPI_DEBUG_PRINT((ACPI_DB_INFO,
@@ -771,7 +774,6 @@ static void acpi_processor_power_verify_c3(
 			return_VOID;
 		}
 	} else {
-		printk("Invalidating cache before entering C3\n");
 		/*
 		 * WBINVD should be set in fadt, for C3 state to be
 		 * supported on when bm_check is not required.
@@ -842,7 +844,7 @@ static int acpi_processor_get_power_info (
 	result = acpi_processor_get_power_info_cst(pr);
 	if ((result) || (acpi_processor_power_verify(pr) < 2)) {
 		result = acpi_processor_get_power_info_fadt(pr);
-		if (result)
+		if ((result) || (acpi_processor_power_verify(pr) < 2))
 			result = acpi_processor_get_power_info_default_c1(pr);
 	}
 
diff --git a/drivers/block/as-iosched.c b/drivers/block/as-iosched.c
index 91aeb678135..95c0a3690b0 100644
--- a/drivers/block/as-iosched.c
+++ b/drivers/block/as-iosched.c
@@ -1935,23 +1935,15 @@ struct as_fs_entry {
 static ssize_t
 as_var_show(unsigned int var, char *page)
 {
-	var = (var * 1000) / HZ;
 	return sprintf(page, "%d\n", var);
 }
 
 static ssize_t
 as_var_store(unsigned long *var, const char *page, size_t count)
 {
-	unsigned long tmp;
 	char *p = (char *) page;
 
-	tmp = simple_strtoul(p, &p, 10);
-	if (tmp != 0) {
-		tmp = (tmp * HZ) / 1000;
-		if (tmp == 0)
-			tmp = 1;
-	}
-	*var = tmp;
+	*var = simple_strtoul(p, &p, 10);
 	return count;
 }
 
diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c
index 3e9fb6e4a52..418b1469d75 100644
--- a/drivers/block/cciss.c
+++ b/drivers/block/cciss.c
@@ -1135,7 +1135,7 @@ static int revalidate_allvol(ctlr_info_t *host)
 		/* this is for the online array utilities */
 		if (!drv->heads && i)
 			continue;
-		blk_queue_hardsect_size(host->queue, drv->block_size);
+		blk_queue_hardsect_size(drv->queue, drv->block_size);
 		set_capacity(disk, drv->nr_blocks);
 		add_disk(disk);
 	}
@@ -1691,7 +1691,7 @@ static int cciss_revalidate(struct gendisk *disk)
 	cciss_read_capacity(h->ctlr, logvol, size_buff, 1, &total_size, &block_size);
 	cciss_geometry_inquiry(h->ctlr, logvol, 1, total_size, block_size, inq_buff, drv);
 
-	blk_queue_hardsect_size(h->queue, drv->block_size);
+	blk_queue_hardsect_size(drv->queue, drv->block_size);
 	set_capacity(disk, drv->nr_blocks);
 
 	kfree(size_buff);
@@ -2248,12 +2248,12 @@ static irqreturn_t do_cciss_intr(int irq, void *dev_id, struct pt_regs *regs)
  	 * them up.  We will also keep track of the next queue to run so
  	 * that every queue gets a chance to be started first.
  	*/
- 	for (j=0; j < NWD; j++){
- 		int curr_queue = (start_queue + j) % NWD;
+	for (j=0; j < h->highest_lun + 1; j++){
+		int curr_queue = (start_queue + j) % (h->highest_lun + 1);
  		/* make sure the disk has been added and the drive is real
  		 * because this can be called from the middle of init_one.
  		*/
- 		if(!(h->gendisk[curr_queue]->queue) ||
+		if(!(h->drv[curr_queue].queue) ||
 		 		   !(h->drv[curr_queue].heads))
  			continue;
  		blk_start_queue(h->gendisk[curr_queue]->queue);
@@ -2264,14 +2264,14 @@ static irqreturn_t do_cciss_intr(int irq, void *dev_id, struct pt_regs *regs)
  		if ((find_first_zero_bit(h->cmd_pool_bits, NR_CMDS)) == NR_CMDS)
  		{
  			if (curr_queue == start_queue){
- 				h->next_to_run = (start_queue + 1) % NWD;
+				h->next_to_run = (start_queue + 1) % (h->highest_lun + 1);
  				goto cleanup;
  			} else {
  				h->next_to_run = curr_queue;
  				goto cleanup;
  	}
  		} else {
- 			curr_queue = (curr_queue + 1) % NWD;
+			curr_queue = (curr_queue + 1) % (h->highest_lun + 1);
  		}
  	}
 
@@ -2279,7 +2279,6 @@ cleanup:
 	spin_unlock_irqrestore(CCISS_LOCK(h->ctlr), flags);
 	return IRQ_HANDLED;
 }
-
 /* 
  *  We cannot read the structure directly, for portablity we must use 
  *   the io functions.
@@ -2789,13 +2788,6 @@ static int __devinit cciss_init_one(struct pci_dev *pdev,
 	}
 
 	spin_lock_init(&hba[i]->lock);
-	q = blk_init_queue(do_cciss_request, &hba[i]->lock);
-	if (!q)
-		goto clean4;
-
-	q->backing_dev_info.ra_pages = READ_AHEAD;
-	hba[i]->queue = q;
-	q->queuedata = hba[i];
 
 	/* Initialize the pdev driver private data. 
 		have it point to hba[i].  */
@@ -2817,6 +2809,20 @@ static int __devinit cciss_init_one(struct pci_dev *pdev,
 
 	cciss_procinit(i);
 
+	for(j=0; j < NWD; j++) { /* mfm */
+		drive_info_struct *drv = &(hba[i]->drv[j]);
+		struct gendisk *disk = hba[i]->gendisk[j];
+
+		q = blk_init_queue(do_cciss_request, &hba[i]->lock);
+		if (!q) {
+			printk(KERN_ERR
+			   "cciss:  unable to allocate queue for disk %d\n",
+			   j);
+			break;
+		}
+		drv->queue = q;
+
+		q->backing_dev_info.ra_pages = READ_AHEAD;
 	blk_queue_bounce_limit(q, hba[i]->pdev->dma_mask);
 
 	/* This is a hardware imposed limit. */
@@ -2827,26 +2833,23 @@ static int __devinit cciss_init_one(struct pci_dev *pdev,
 
 	blk_queue_max_sectors(q, 512);
 
-
-	for(j=0; j<NWD; j++) {
-		drive_info_struct *drv = &(hba[i]->drv[j]);
-		struct gendisk *disk = hba[i]->gendisk[j];
-
+		q->queuedata = hba[i];
 		sprintf(disk->disk_name, "cciss/c%dd%d", i, j);
 		sprintf(disk->devfs_name, "cciss/host%d/target%d", i, j);
 		disk->major = hba[i]->major;
 		disk->first_minor = j << NWD_SHIFT;
 		disk->fops = &cciss_fops;
-		disk->queue = hba[i]->queue;
+		disk->queue = q;
 		disk->private_data = drv;
 		/* we must register the controller even if no disks exist */
 		/* this is for the online array utilities */
 		if(!drv->heads && j)
 			continue;
-		blk_queue_hardsect_size(hba[i]->queue, drv->block_size);
+		blk_queue_hardsect_size(q, drv->block_size);
 		set_capacity(disk, drv->nr_blocks);
 		add_disk(disk);
 	}
+
 	return(1);
 
 clean4:
@@ -2912,10 +2915,10 @@ static void __devexit cciss_remove_one (struct pci_dev *pdev)
 	for (j = 0; j < NWD; j++) {
 		struct gendisk *disk = hba[i]->gendisk[j];
 		if (disk->flags & GENHD_FL_UP)
+			blk_cleanup_queue(disk->queue);
 			del_gendisk(disk);
 	}
 
-	blk_cleanup_queue(hba[i]->queue);
 	pci_free_consistent(hba[i]->pdev, NR_CMDS * sizeof(CommandList_struct),
 			    hba[i]->cmd_pool, hba[i]->cmd_pool_dhandle);
 	pci_free_consistent(hba[i]->pdev, NR_CMDS * sizeof( ErrorInfo_struct),
diff --git a/drivers/block/cciss.h b/drivers/block/cciss.h
index 8fb19206edd..566587d0a50 100644
--- a/drivers/block/cciss.h
+++ b/drivers/block/cciss.h
@@ -29,6 +29,7 @@ typedef struct _drive_info_struct
 {
  	__u32   LunID;	
 	int 	usage_count;
+	struct request_queue *queue;
 	sector_t nr_blocks;
 	int	block_size;
 	int 	heads;
@@ -72,7 +73,6 @@ struct ctlr_info
 	unsigned int maxQsinceinit;
 	unsigned int maxSG;
 	spinlock_t lock;
-	struct request_queue *queue;
 
 	//* pointers to command and error info pool */ 
 	CommandList_struct 	*cmd_pool;
@@ -260,7 +260,7 @@ struct board_type {
 	struct access_method *access;
 };
 
-#define CCISS_LOCK(i)	(hba[i]->queue->queue_lock)
+#define CCISS_LOCK(i)	(&hba[i]->lock)
 
 #endif /* CCISS_H */
 
diff --git a/drivers/block/cfq-iosched.c b/drivers/block/cfq-iosched.c
index de5746e38af..2435a7c99b2 100644
--- a/drivers/block/cfq-iosched.c
+++ b/drivers/block/cfq-iosched.c
@@ -1281,6 +1281,7 @@ dispatch:
 			 */
 			if (!cfq_crq_in_driver(crq) &&
 			    !cfq_cfqq_idle_window(cfqq) &&
+			    !blk_barrier_rq(rq) &&
 			    cfqd->rq_in_driver >= cfqd->cfq_max_depth)
 				return NULL;
 
diff --git a/drivers/block/ll_rw_blk.c b/drivers/block/ll_rw_blk.c
index 692a5fced76..3c818544475 100644
--- a/drivers/block/ll_rw_blk.c
+++ b/drivers/block/ll_rw_blk.c
@@ -719,7 +719,7 @@ struct request *blk_queue_find_tag(request_queue_t *q, int tag)
 {
 	struct blk_queue_tag *bqt = q->queue_tags;
 
-	if (unlikely(bqt == NULL || tag >= bqt->max_depth))
+	if (unlikely(bqt == NULL || tag >= bqt->real_max_depth))
 		return NULL;
 
 	return bqt->tag_index[tag];
@@ -798,6 +798,7 @@ init_tag_map(request_queue_t *q, struct blk_queue_tag *tags, int depth)
 
 	memset(tag_index, 0, depth * sizeof(struct request *));
 	memset(tag_map, 0, nr_ulongs * sizeof(unsigned long));
+	tags->real_max_depth = depth;
 	tags->max_depth = depth;
 	tags->tag_index = tag_index;
 	tags->tag_map = tag_map;
@@ -872,11 +873,22 @@ int blk_queue_resize_tags(request_queue_t *q, int new_depth)
 		return -ENXIO;
 
 	/*
+	 * if we already have large enough real_max_depth.  just
+	 * adjust max_depth.  *NOTE* as requests with tag value
+	 * between new_depth and real_max_depth can be in-flight, tag
+	 * map can not be shrunk blindly here.
+	 */
+	if (new_depth <= bqt->real_max_depth) {
+		bqt->max_depth = new_depth;
+		return 0;
+	}
+
+	/*
 	 * save the old state info, so we can copy it back
 	 */
 	tag_index = bqt->tag_index;
 	tag_map = bqt->tag_map;
-	max_depth = bqt->max_depth;
+	max_depth = bqt->real_max_depth;
 
 	if (init_tag_map(q, bqt, new_depth))
 		return -ENOMEM;
@@ -913,7 +925,7 @@ void blk_queue_end_tag(request_queue_t *q, struct request *rq)
 
 	BUG_ON(tag == -1);
 
-	if (unlikely(tag >= bqt->max_depth))
+	if (unlikely(tag >= bqt->real_max_depth))
 		/*
 		 * This can happen after tag depth has been reduced.
 		 * FIXME: how about a warning or info message here?
diff --git a/drivers/block/sx8.c b/drivers/block/sx8.c
index 9db0a9e3e59..d57007b92f7 100644
--- a/drivers/block/sx8.c
+++ b/drivers/block/sx8.c
@@ -1582,7 +1582,7 @@ static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
 	if (rc)
 		goto err_out;
 
-#if IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */
+#ifdef IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */
 	rc = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
 	if (!rc) {
 		rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
@@ -1601,7 +1601,7 @@ static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
 			goto err_out_regions;
 		}
 		pci_dac = 0;
-#if IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */
+#ifdef IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */
 	}
 #endif
 
diff --git a/drivers/block/ub.c b/drivers/block/ub.c
index 685f061e69b..a026567f5d1 100644
--- a/drivers/block/ub.c
+++ b/drivers/block/ub.c
@@ -23,6 +23,7 @@
  *  -- Exterminate P3 printks
  *  -- Resove XXX's
  *  -- Redo "benh's retries", perhaps have spin-up code to handle them. V:D=?
+ *  -- CLEAR, CLR2STS, CLRRS seem to be ripe for refactoring.
  */
 #include <linux/kernel.h>
 #include <linux/module.h>
@@ -38,6 +39,73 @@
 #define UB_MAJOR 180
 
 /*
+ * The command state machine is the key model for understanding of this driver.
+ *
+ * The general rule is that all transitions are done towards the bottom
+ * of the diagram, thus preventing any loops.
+ *
+ * An exception to that is how the STAT state is handled. A counter allows it
+ * to be re-entered along the path marked with [C].
+ *
+ *       +--------+
+ *       ! INIT   !
+ *       +--------+
+ *           !
+ *        ub_scsi_cmd_start fails ->--------------------------------------\
+ *           !                                                            !
+ *           V                                                            !
+ *       +--------+                                                       !
+ *       ! CMD    !                                                       !
+ *       +--------+                                                       !
+ *           !                                            +--------+      !
+ *         was -EPIPE -->-------------------------------->! CLEAR  !      !
+ *           !                                            +--------+      !
+ *           !                                                !           !
+ *         was error -->------------------------------------- ! --------->\
+ *           !                                                !           !
+ *  /--<-- cmd->dir == NONE ?                                 !           !
+ *  !        !                                                !           !
+ *  !        V                                                !           !
+ *  !    +--------+                                           !           !
+ *  !    ! DATA   !                                           !           !
+ *  !    +--------+                                           !           !
+ *  !        !                           +---------+          !           !
+ *  !      was -EPIPE -->--------------->! CLR2STS !          !           !
+ *  !        !                           +---------+          !           !
+ *  !        !                                !               !           !
+ *  !        !                              was error -->---- ! --------->\
+ *  !      was error -->--------------------- ! ------------- ! --------->\
+ *  !        !                                !               !           !
+ *  !        V                                !               !           !
+ *  \--->+--------+                           !               !           !
+ *       ! STAT   !<--------------------------/               !           !
+ *  /--->+--------+                                           !           !
+ *  !        !                                                !           !
+ * [C]     was -EPIPE -->-----------\                         !           !
+ *  !        !                      !                         !           !
+ *  +<---- len == 0                 !                         !           !
+ *  !        !                      !                         !           !
+ *  !      was error -->--------------------------------------!---------->\
+ *  !        !                      !                         !           !
+ *  +<---- bad CSW                  !                         !           !
+ *  +<---- bad tag                  !                         !           !
+ *  !        !                      V                         !           !
+ *  !        !                 +--------+                     !           !
+ *  !        !                 ! CLRRS  !                     !           !
+ *  !        !                 +--------+                     !           !
+ *  !        !                      !                         !           !
+ *  \------- ! --------------------[C]--------\               !           !
+ *           !                                !               !           !
+ *         cmd->error---\                +--------+           !           !
+ *           !          +--------------->! SENSE  !<----------/           !
+ *         STAT_FAIL----/                +--------+                       !
+ *           !                                !                           V
+ *           !                                V                      +--------+
+ *           \--------------------------------\--------------------->! DONE   !
+ *                                                                   +--------+
+ */
+
+/*
  * Definitions which have to be scattered once we understand the layout better.
  */
 
@@ -91,8 +159,6 @@ struct bulk_cs_wrap {
 
 #define US_BULK_CS_WRAP_LEN	13
 #define US_BULK_CS_SIGN		0x53425355	/* spells out 'USBS' */
-/* This is for Olympus Camedia digital cameras */
-#define US_BULK_CS_OLYMPUS_SIGN	0x55425355	/* spells out 'USBU' */
 #define US_BULK_STAT_OK		0
 #define US_BULK_STAT_FAIL	1
 #define US_BULK_STAT_PHASE	2
@@ -135,6 +201,7 @@ enum ub_scsi_cmd_state {
 	UB_CMDST_CLR2STS,		/* Clearing before requesting status */
 	UB_CMDST_STAT,			/* Status phase */
 	UB_CMDST_CLEAR,			/* Clearing a stall (halt, actually) */
+	UB_CMDST_CLRRS,			/* Clearing before retrying status */
 	UB_CMDST_SENSE,			/* Sending Request Sense */
 	UB_CMDST_DONE			/* Final state */
 };
@@ -146,6 +213,7 @@ static char *ub_scsi_cmd_stname[] = {
 	"c2s",
 	"sts",
 	"clr",
+	"crs",
 	"Sen",
 	"fin"
 };
@@ -316,6 +384,7 @@ struct ub_dev {
 	struct urb work_urb;
 	struct timer_list work_timer;
 	int last_pipe;			/* What might need clearing */
+	__le32 signature;		/* Learned signature */
 	struct bulk_cb_wrap work_bcb;
 	struct bulk_cs_wrap work_bcs;
 	struct usb_ctrlrequest work_cr;
@@ -339,8 +408,9 @@ static void ub_scsi_action(unsigned long _dev);
 static void ub_scsi_dispatch(struct ub_dev *sc);
 static void ub_scsi_urb_compl(struct ub_dev *sc, struct ub_scsi_cmd *cmd);
 static void ub_state_done(struct ub_dev *sc, struct ub_scsi_cmd *cmd, int rc);
-static void __ub_state_stat(struct ub_dev *sc, struct ub_scsi_cmd *cmd);
+static int __ub_state_stat(struct ub_dev *sc, struct ub_scsi_cmd *cmd);
 static void ub_state_stat(struct ub_dev *sc, struct ub_scsi_cmd *cmd);
+static void ub_state_stat_counted(struct ub_dev *sc, struct ub_scsi_cmd *cmd);
 static void ub_state_sense(struct ub_dev *sc, struct ub_scsi_cmd *cmd);
 static int ub_submit_clear_stall(struct ub_dev *sc, struct ub_scsi_cmd *cmd,
     int stalled_pipe);
@@ -1085,6 +1155,28 @@ static void ub_scsi_urb_compl(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
 
 		ub_state_stat(sc, cmd);
 
+	} else if (cmd->state == UB_CMDST_CLRRS) {
+		if (urb->status == -EPIPE) {
+			/*
+			 * STALL while clearning STALL.
+			 * The control pipe clears itself - nothing to do.
+			 * XXX Might try to reset the device here and retry.
+			 */
+			printk(KERN_NOTICE "%s: stall on control pipe\n",
+			    sc->name);
+			goto Bad_End;
+		}
+
+		/*
+		 * We ignore the result for the halt clear.
+		 */
+
+		/* reset the endpoint toggle */
+		usb_settoggle(sc->dev, usb_pipeendpoint(sc->last_pipe),
+			usb_pipeout(sc->last_pipe), 0);
+
+		ub_state_stat_counted(sc, cmd);
+
 	} else if (cmd->state == UB_CMDST_CMD) {
 		if (urb->status == -EPIPE) {
 			rc = ub_submit_clear_stall(sc, cmd, sc->last_pipe);
@@ -1190,52 +1282,57 @@ static void ub_scsi_urb_compl(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
 				 */
 				goto Bad_End;
 			}
-			cmd->state = UB_CMDST_CLEAR;
+
+			/*
+			 * Having a stall when getting CSW is an error, so
+			 * make sure uppper levels are not oblivious to it.
+			 */
+			cmd->error = -EIO;		/* A cheap trick... */
+
+			cmd->state = UB_CMDST_CLRRS;
 			ub_cmdtr_state(sc, cmd);
 			return;
 		}
+		if (urb->status == -EOVERFLOW) {
+			/*
+			 * XXX We are screwed here. Retrying is pointless,
+			 * because the pipelined data will not get in until
+			 * we read with a big enough buffer. We must reset XXX.
+			 */
+			goto Bad_End;
+		}
 		if (urb->status != 0)
 			goto Bad_End;
 
 		if (urb->actual_length == 0) {
-			/*
-			 * Some broken devices add unnecessary zero-length
-			 * packets to the end of their data transfers.
-			 * Such packets show up as 0-length CSWs. If we
-			 * encounter such a thing, try to read the CSW again.
-			 */
-			if (++cmd->stat_count >= 4) {
-				printk(KERN_NOTICE "%s: unable to get CSW\n",
-				    sc->name);
-				goto Bad_End;
-			}
-			__ub_state_stat(sc, cmd);
+			ub_state_stat_counted(sc, cmd);
 			return;
 		}
 
 		/*
 		 * Check the returned Bulk protocol status.
+		 * The status block has to be validated first.
 		 */
 
 		bcs = &sc->work_bcs;
-		rc = le32_to_cpu(bcs->Residue);
-		if (rc != cmd->len - cmd->act_len) {
+
+		if (sc->signature == cpu_to_le32(0)) {
 			/*
-			 * It is all right to transfer less, the caller has
-			 * to check. But it's not all right if the device
-			 * counts disagree with our counts.
+			 * This is the first reply, so do not perform the check.
+			 * Instead, remember the signature the device uses
+			 * for future checks. But do not allow a nul.
 			 */
-			/* P3 */ printk("%s: resid %d len %d act %d\n",
-			    sc->name, rc, cmd->len, cmd->act_len);
-			goto Bad_End;
-		}
-
-#if 0
-		if (bcs->Signature != cpu_to_le32(US_BULK_CS_SIGN) &&
-		    bcs->Signature != cpu_to_le32(US_BULK_CS_OLYMPUS_SIGN)) {
-			/* Windows ignores signatures, so do we. */
+			sc->signature = bcs->Signature;
+			if (sc->signature == cpu_to_le32(0)) {
+				ub_state_stat_counted(sc, cmd);
+				return;
+			}
+		} else {
+			if (bcs->Signature != sc->signature) {
+				ub_state_stat_counted(sc, cmd);
+				return;
+			}
 		}
-#endif
 
 		if (bcs->Tag != cmd->tag) {
 			/*
@@ -1245,16 +1342,22 @@ static void ub_scsi_urb_compl(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
 			 * commands and reply at commands we timed out before.
 			 * Without flushing these replies we loop forever.
 			 */
-			if (++cmd->stat_count >= 4) {
-				printk(KERN_NOTICE "%s: "
-				    "tag mismatch orig 0x%x reply 0x%x\n",
-				    sc->name, cmd->tag, bcs->Tag);
-				goto Bad_End;
-			}
-			__ub_state_stat(sc, cmd);
+			ub_state_stat_counted(sc, cmd);
 			return;
 		}
 
+		rc = le32_to_cpu(bcs->Residue);
+		if (rc != cmd->len - cmd->act_len) {
+			/*
+			 * It is all right to transfer less, the caller has
+			 * to check. But it's not all right if the device
+			 * counts disagree with our counts.
+			 */
+			/* P3 */ printk("%s: resid %d len %d act %d\n",
+			    sc->name, rc, cmd->len, cmd->act_len);
+			goto Bad_End;
+		}
+
 		switch (bcs->Status) {
 		case US_BULK_STAT_OK:
 			break;
@@ -1272,6 +1375,10 @@ static void ub_scsi_urb_compl(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
 		}
 
 		/* Not zeroing error to preserve a babble indicator */
+		if (cmd->error != 0) {
+			ub_state_sense(sc, cmd);
+			return;
+		}
 		cmd->state = UB_CMDST_DONE;
 		ub_cmdtr_state(sc, cmd);
 		ub_cmdq_pop(sc);
@@ -1310,7 +1417,7 @@ static void ub_state_done(struct ub_dev *sc, struct ub_scsi_cmd *cmd, int rc)
  * Factorization helper for the command state machine:
  * Submit a CSW read.
  */
-static void __ub_state_stat(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
+static int __ub_state_stat(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
 {
 	int rc;
 
@@ -1328,11 +1435,12 @@ static void __ub_state_stat(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
 		/* XXX Clear stalls */
 		ub_complete(&sc->work_done);
 		ub_state_done(sc, cmd, rc);
-		return;
+		return -1;
 	}
 
 	sc->work_timer.expires = jiffies + UB_STAT_TIMEOUT;
 	add_timer(&sc->work_timer);
+	return 0;
 }
 
 /*
@@ -1341,7 +1449,9 @@ static void __ub_state_stat(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
  */
 static void ub_state_stat(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
 {
-	__ub_state_stat(sc, cmd);
+
+	if (__ub_state_stat(sc, cmd) != 0)
+		return;
 
 	cmd->stat_count = 0;
 	cmd->state = UB_CMDST_STAT;
@@ -1350,6 +1460,25 @@ static void ub_state_stat(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
 
 /*
  * Factorization helper for the command state machine:
+ * Submit a CSW read and go to STAT state with counter (along [C] path).
+ */
+static void ub_state_stat_counted(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
+{
+
+	if (++cmd->stat_count >= 4) {
+		ub_state_sense(sc, cmd);
+		return;
+	}
+
+	if (__ub_state_stat(sc, cmd) != 0)
+		return;
+
+	cmd->state = UB_CMDST_STAT;
+	ub_cmdtr_state(sc, cmd);
+}
+
+/*
+ * Factorization helper for the command state machine:
  * Submit a REQUEST SENSE and go to SENSE state.
  */
 static void ub_state_sense(struct ub_dev *sc, struct ub_scsi_cmd *cmd)
diff --git a/drivers/bluetooth/bpa10x.c b/drivers/bluetooth/bpa10x.c
index 2771c861f18..f696da6f417 100644
--- a/drivers/bluetooth/bpa10x.c
+++ b/drivers/bluetooth/bpa10x.c
@@ -367,11 +367,8 @@ static inline void bpa10x_free_urb(struct urb *urb)
 	if (!urb)
 		return;
 
-	if (urb->setup_packet)
-		kfree(urb->setup_packet);
-
-	if (urb->transfer_buffer)
-		kfree(urb->transfer_buffer);
+	kfree(urb->setup_packet);
+	kfree(urb->transfer_buffer);
 
 	usb_free_urb(urb);
 }
diff --git a/drivers/bluetooth/hci_bcsp.c b/drivers/bluetooth/hci_bcsp.c
index c0ed213fc85..858fddb046d 100644
--- a/drivers/bluetooth/hci_bcsp.c
+++ b/drivers/bluetooth/hci_bcsp.c
@@ -58,8 +58,6 @@
 #ifndef CONFIG_BT_HCIUART_DEBUG
 #undef  BT_DBG
 #define BT_DBG( A... )
-#undef  BT_DMP
-#define BT_DMP( A... )
 #endif
 
 static int hciextn = 1;
diff --git a/drivers/bluetooth/hci_h4.c b/drivers/bluetooth/hci_h4.c
index ade94a57bb1..533323b60e6 100644
--- a/drivers/bluetooth/hci_h4.c
+++ b/drivers/bluetooth/hci_h4.c
@@ -57,8 +57,6 @@
 #ifndef CONFIG_BT_HCIUART_DEBUG
 #undef  BT_DBG
 #define BT_DBG( A... )
-#undef  BT_DMP
-#define BT_DMP( A... )
 #endif
 
 /* Initialize protocol */
@@ -125,7 +123,6 @@ static inline int h4_check_data_len(struct h4_struct *h4, int len)
 
 	BT_DBG("len %d room %d", len, room);
 	if (!len) {
-		BT_DMP(h4->rx_skb->data, h4->rx_skb->len);
 		hci_recv_frame(h4->rx_skb);
 	} else if (len > room) {
 		BT_ERR("Data length is too large");
@@ -169,8 +166,6 @@ static int h4_recv(struct hci_uart *hu, void *data, int count)
 			case H4_W4_DATA:
 				BT_DBG("Complete data");
 
-				BT_DMP(h4->rx_skb->data, h4->rx_skb->len);
-
 				hci_recv_frame(h4->rx_skb);
 
 				h4->rx_state = H4_W4_PACKET_TYPE;
diff --git a/drivers/bluetooth/hci_ldisc.c b/drivers/bluetooth/hci_ldisc.c
index f766bc22c6b..90be2eae52e 100644
--- a/drivers/bluetooth/hci_ldisc.c
+++ b/drivers/bluetooth/hci_ldisc.c
@@ -57,8 +57,6 @@
 #ifndef CONFIG_BT_HCIUART_DEBUG
 #undef  BT_DBG
 #define BT_DBG( A... )
-#undef  BT_DMP
-#define BT_DMP( A... )
 #endif
 
 static int reset = 0;
diff --git a/drivers/bluetooth/hci_usb.c b/drivers/bluetooth/hci_usb.c
index b120ecf7b8c..657719b8254 100644
--- a/drivers/bluetooth/hci_usb.c
+++ b/drivers/bluetooth/hci_usb.c
@@ -57,8 +57,6 @@
 #ifndef CONFIG_BT_HCIUSB_DEBUG
 #undef  BT_DBG
 #define BT_DBG(D...)
-#undef  BT_DMP
-#define BT_DMP(D...)
 #endif
 
 #ifndef CONFIG_BT_HCIUSB_ZERO_PACKET
@@ -110,6 +108,9 @@ static struct usb_device_id blacklist_ids[] = {
 	/* Microsoft Wireless Transceiver for Bluetooth 2.0 */
 	{ USB_DEVICE(0x045e, 0x009c), .driver_info = HCI_RESET },
 
+	/* Kensington Bluetooth USB adapter */
+	{ USB_DEVICE(0x047d, 0x105d), .driver_info = HCI_RESET },
+
 	/* ISSC Bluetooth Adapter v3.1 */
 	{ USB_DEVICE(0x1131, 0x1001), .driver_info = HCI_RESET },
 
@@ -387,10 +388,8 @@ static void hci_usb_unlink_urbs(struct hci_usb *husb)
 			urb = &_urb->urb;
 			BT_DBG("%s freeing _urb %p type %d urb %p",
 					husb->hdev->name, _urb, _urb->type, urb);
-			if (urb->setup_packet)
-				kfree(urb->setup_packet);
-			if (urb->transfer_buffer)
-				kfree(urb->transfer_buffer);
+			kfree(urb->setup_packet);
+			kfree(urb->transfer_buffer);
 			_urb_free(_urb);
 		}
 
diff --git a/drivers/cdrom/isp16.c b/drivers/cdrom/isp16.c
index 8e68d858ce6..db0fd9a240e 100644
--- a/drivers/cdrom/isp16.c
+++ b/drivers/cdrom/isp16.c
@@ -18,7 +18,7 @@
  *
  *     19 June 2004     -- check_region() converted to request_region()
  *                         and return statement cleanups.
- *                         Jesper Juhl <juhl-lkml@dif.dk>
+ *                          - Jesper Juhl
  *
  *    Detect cdrom interface on ISP16 sound card.
  *    Configure cdrom interface.
diff --git a/drivers/cdrom/mcdx.c b/drivers/cdrom/mcdx.c
index 07bbd24e3c1..b89420e6d70 100644
--- a/drivers/cdrom/mcdx.c
+++ b/drivers/cdrom/mcdx.c
@@ -51,7 +51,7 @@
  */
 
 
-#if RCS
+#ifdef RCS
 static const char *mcdx_c_version
     = "$Id: mcdx.c,v 1.21 1997/01/26 07:12:59 davem Exp $";
 #endif
@@ -706,7 +706,7 @@ static int mcdx_open(struct cdrom_device_info *cdi, int purpose)
 		xtrace(OPENCLOSE, "open() init irq generation\n");
 		if (-1 == mcdx_config(stuffp, 1))
 			return -EIO;
-#if FALLBACK
+#ifdef FALLBACK
 		/* Set the read speed */
 		xwarn("AAA %x AAA\n", stuffp->readcmd);
 		if (stuffp->readerrs)
@@ -1216,7 +1216,7 @@ static int __init mcdx_init_drive(int drive)
 	}
 
 
-#if WE_KNOW_WHY
+#ifdef WE_KNOW_WHY
 	/* irq 11 -> channel register */
 	outb(0x50, stuffp->wreg_chn);
 #endif
@@ -1294,7 +1294,7 @@ static int mcdx_transfer(struct s_drive_stuff *stuffp,
 
 	ans = mcdx_xfer(stuffp, p, sector, nr_sectors);
 	return ans;
-#if FALLBACK
+#ifdef FALLBACK
 	if (-1 == ans)
 		stuffp->readerrs++;
 	else
diff --git a/drivers/cdrom/optcd.c b/drivers/cdrom/optcd.c
index 7e69c54568b..351a01dd503 100644
--- a/drivers/cdrom/optcd.c
+++ b/drivers/cdrom/optcd.c
@@ -245,7 +245,7 @@ module_param(optcd_port, short, 0);
 
 
 /* Busy wait until FLAG goes low. Return 0 on timeout. */
-inline static int flag_low(int flag, unsigned long timeout)
+static inline int flag_low(int flag, unsigned long timeout)
 {
 	int flag_high;
 	unsigned long count = 0;
@@ -381,7 +381,7 @@ static int send_seek_params(struct cdrom_msf *params)
 
 /* Wait for command execution status. Choice between busy waiting
    and sleeping. Return value <0 indicates timeout. */
-inline static int get_exec_status(int busy_waiting)
+static inline int get_exec_status(int busy_waiting)
 {
 	unsigned char exec_status;
 
@@ -398,7 +398,7 @@ inline static int get_exec_status(int busy_waiting)
 
 /* Wait busy for extra byte of data that a command returns.
    Return value <0 indicates timeout. */
-inline static int get_data(int short_timeout)
+static inline int get_data(int short_timeout)
 {
 	unsigned char data;
 
@@ -441,14 +441,14 @@ static int reset_drive(void)
 /* Facilities for asynchronous operation */
 
 /* Read status/data availability flags FL_STEN and FL_DTEN */
-inline static int stdt_flags(void)
+static inline int stdt_flags(void)
 {
 	return inb(STATUS_PORT) & FL_STDT;
 }
 
 
 /* Fetch status that has previously been waited for. <0 means not available */
-inline static int fetch_status(void)
+static inline int fetch_status(void)
 {
 	unsigned char status;
 
@@ -462,7 +462,7 @@ inline static int fetch_status(void)
 
 
 /* Fetch data that has previously been waited for. */
-inline static void fetch_data(char *buf, int n)
+static inline void fetch_data(char *buf, int n)
 {
 	insb(DATA_PORT, buf, n);
 	DEBUG((DEBUG_DRIVE_IF, "fetched 0x%x bytes", n));
@@ -470,7 +470,7 @@ inline static void fetch_data(char *buf, int n)
 
 
 /* Flush status and data fifos */
-inline static void flush_data(void)
+static inline void flush_data(void)
 {
 	while ((inb(STATUS_PORT) & FL_STDT) != FL_STDT)
 		inb(DATA_PORT);
@@ -482,7 +482,7 @@ inline static void flush_data(void)
 
 /* Send a simple command and wait for response. Command codes < COMFETCH
    are quick response commands */
-inline static int exec_cmd(int cmd)
+static inline int exec_cmd(int cmd)
 {
 	int ack = send_cmd(cmd);
 	if (ack < 0)
@@ -493,7 +493,7 @@ inline static int exec_cmd(int cmd)
 
 /* Send a command with parameters. Don't wait for the response,
  * which consists of data blocks read from the CD. */
-inline static int exec_read_cmd(int cmd, struct cdrom_msf *params)
+static inline int exec_read_cmd(int cmd, struct cdrom_msf *params)
 {
 	int ack = send_cmd(cmd);
 	if (ack < 0)
@@ -503,7 +503,7 @@ inline static int exec_read_cmd(int cmd, struct cdrom_msf *params)
 
 
 /* Send a seek command with parameters and wait for response */
-inline static int exec_seek_cmd(int cmd, struct cdrom_msf *params)
+static inline int exec_seek_cmd(int cmd, struct cdrom_msf *params)
 {
 	int ack = send_cmd(cmd);
 	if (ack < 0)
@@ -516,7 +516,7 @@ inline static int exec_seek_cmd(int cmd, struct cdrom_msf *params)
 
 
 /* Send a command with parameters and wait for response */
-inline static int exec_long_cmd(int cmd, struct cdrom_msf *params)
+static inline int exec_long_cmd(int cmd, struct cdrom_msf *params)
 {
 	int ack = exec_read_cmd(cmd, params);
 	if (ack < 0)
@@ -528,7 +528,7 @@ inline static int exec_long_cmd(int cmd, struct cdrom_msf *params)
 
 
 /* Binary to BCD (2 digits) */
-inline static void single_bin2bcd(u_char *p)
+static inline void single_bin2bcd(u_char *p)
 {
 	DEBUG((DEBUG_CONV, "bin2bcd %02d", *p));
 	*p = (*p % 10) | ((*p / 10) << 4);
@@ -565,7 +565,7 @@ static void lba2msf(int lba, struct cdrom_msf *msf)
 
 
 /* Two BCD digits to binary */
-inline static u_char bcd2bin(u_char bcd)
+static inline u_char bcd2bin(u_char bcd)
 {
 	DEBUG((DEBUG_CONV, "bcd2bin %x%02x", bcd));
 	return (bcd >> 4) * 10 + (bcd & 0x0f);
@@ -988,7 +988,7 @@ static char buf[CD_FRAMESIZE * N_BUFS];
 static volatile int buf_bn[N_BUFS], next_bn;
 static volatile int buf_in = 0, buf_out = NOBUF;
 
-inline static void opt_invalidate_buffers(void)
+static inline void opt_invalidate_buffers(void)
 {
 	int i;
 
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 43d0cb19ef6..4f27e551929 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -735,7 +735,7 @@ config SGI_IP27_RTC
 
 config GEN_RTC
 	tristate "Generic /dev/rtc emulation"
-	depends on RTC!=y && !IA64 && !ARM
+	depends on RTC!=y && !IA64 && !ARM && !PPC64
 	---help---
 	  If you say Y here and create a character special file /dev/rtc with
 	  major number 10 and minor number 135 using mknod ("man mknod"), you
diff --git a/drivers/char/agp/agp.h b/drivers/char/agp/agp.h
index c1fe013c64f..b4af87c6f9c 100644
--- a/drivers/char/agp/agp.h
+++ b/drivers/char/agp/agp.h
@@ -143,6 +143,7 @@ struct agp_bridge_data {
 	char major_version;
 	char minor_version;
 	struct list_head list;
+	u32 apbase_config;
 };
 
 #define KB(x)	((x) * 1024)
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index 51266d6b4d7..1f7d415f432 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -1047,9 +1047,15 @@ static int intel_845_configure(void)
 	/* aperture size */
 	pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
 
-	/* address to map to */
-	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
-	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+	if (agp_bridge->apbase_config != 0) {
+		pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
+				       agp_bridge->apbase_config);
+	} else {
+		/* address to map to */
+		pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
+		agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+		agp_bridge->apbase_config = temp;
+	}
 
 	/* attbase - aperture base */
 	pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
diff --git a/drivers/char/drm/via_dma.c b/drivers/char/drm/via_dma.c
index 82f83945162..4f60f7f4193 100644
--- a/drivers/char/drm/via_dma.c
+++ b/drivers/char/drm/via_dma.c
@@ -231,7 +231,7 @@ int via_dma_init(DRM_IOCTL_ARGS)
 	drm_via_dma_init_t init;
 	int retcode = 0;
 
-	DRM_COPY_FROM_USER_IOCTL(init, (drm_via_dma_init_t *) data,
+	DRM_COPY_FROM_USER_IOCTL(init, (drm_via_dma_init_t __user *) data,
 				 sizeof(init));
 
 	switch (init.func) {
@@ -343,7 +343,7 @@ int via_cmdbuffer(DRM_IOCTL_ARGS)
 
 	LOCK_TEST_WITH_RETURN( dev, filp );
 
-	DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t *) data,
+	DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data,
 				 sizeof(cmdbuf));
 
 	DRM_DEBUG("via cmdbuffer, buf %p size %lu\n", cmdbuf.buf, cmdbuf.size);
@@ -386,7 +386,7 @@ int via_pci_cmdbuffer(DRM_IOCTL_ARGS)
 
 	LOCK_TEST_WITH_RETURN( dev, filp );
 
-	DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t *) data,
+	DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data,
 				 sizeof(cmdbuf));
 
 	DRM_DEBUG("via_pci_cmdbuffer, buf %p size %lu\n", cmdbuf.buf,
@@ -701,7 +701,7 @@ via_cmdbuf_size(DRM_IOCTL_ARGS)
 		return DRM_ERR(EFAULT);
 	}
 
-	DRM_COPY_FROM_USER_IOCTL(d_siz, (drm_via_cmdbuf_size_t *) data,
+	DRM_COPY_FROM_USER_IOCTL(d_siz, (drm_via_cmdbuf_size_t __user *) data,
 				 sizeof(d_siz));
 
 
@@ -735,7 +735,7 @@ via_cmdbuf_size(DRM_IOCTL_ARGS)
 	}
 	d_siz.size = tmp_size;
 
-	DRM_COPY_TO_USER_IOCTL((drm_via_cmdbuf_size_t *) data, d_siz,
+	DRM_COPY_TO_USER_IOCTL((drm_via_cmdbuf_size_t __user *) data, d_siz,
 			       sizeof(d_siz));
 	return ret;
 }
diff --git a/drivers/char/drm/via_drm.h b/drivers/char/drm/via_drm.h
index 4588c9bd181..be346bb0a26 100644
--- a/drivers/char/drm/via_drm.h
+++ b/drivers/char/drm/via_drm.h
@@ -158,7 +158,7 @@ typedef struct _drm_via_dma_init {
 } drm_via_dma_init_t;
 
 typedef struct _drm_via_cmdbuffer {
-	char *buf;
+	char __user *buf;
 	unsigned long size;
 } drm_via_cmdbuffer_t;
 
diff --git a/drivers/char/drm/via_ds.c b/drivers/char/drm/via_ds.c
index daf3df75a20..5c71e089246 100644
--- a/drivers/char/drm/via_ds.c
+++ b/drivers/char/drm/via_ds.c
@@ -133,7 +133,7 @@ memHeap_t *via_mmInit(int ofs, int size)
 	PMemBlock blocks;
 
 	if (size <= 0)
-		return 0;
+		return NULL;
 
 	blocks = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock), DRM_MEM_DRIVER);
 
@@ -143,7 +143,7 @@ memHeap_t *via_mmInit(int ofs, int size)
 		blocks->free = 1;
 		return (memHeap_t *) blocks;
 	} else
-		return 0;
+		return NULL;
 }
 
 static TMemBlock *SliceBlock(TMemBlock * p,
diff --git a/drivers/char/drm/via_ds.h b/drivers/char/drm/via_ds.h
index be9c7f9f1ae..d2bb9f37ca3 100644
--- a/drivers/char/drm/via_ds.h
+++ b/drivers/char/drm/via_ds.h
@@ -61,8 +61,8 @@ struct mem_block_t {
 	struct mem_block_t *heap;
 	int ofs, size;
 	int align;
-	int free:1;
-	int reserved:1;
+	unsigned int free:1;
+	unsigned int reserved:1;
 };
 typedef struct mem_block_t TMemBlock;
 typedef struct mem_block_t *PMemBlock;
diff --git a/drivers/char/drm/via_map.c b/drivers/char/drm/via_map.c
index 0be829b6ec6..bb171139e73 100644
--- a/drivers/char/drm/via_map.c
+++ b/drivers/char/drm/via_map.c
@@ -95,7 +95,8 @@ int via_map_init(DRM_IOCTL_ARGS)
 
 	DRM_DEBUG("%s\n", __FUNCTION__);
 
-	DRM_COPY_FROM_USER_IOCTL(init, (drm_via_init_t *) data, sizeof(init));
+	DRM_COPY_FROM_USER_IOCTL(init, (drm_via_init_t __user *) data,
+				 sizeof(init));
 
 	switch (init.func) {
 	case VIA_INIT_MAP:
diff --git a/drivers/char/drm/via_mm.c b/drivers/char/drm/via_mm.c
index c22712f44d4..13921f3c0ec 100644
--- a/drivers/char/drm/via_mm.c
+++ b/drivers/char/drm/via_mm.c
@@ -76,7 +76,8 @@ int via_agp_init(DRM_IOCTL_ARGS)
 {
 	drm_via_agp_t agp;
 
-	DRM_COPY_FROM_USER_IOCTL(agp, (drm_via_agp_t *) data, sizeof(agp));
+	DRM_COPY_FROM_USER_IOCTL(agp, (drm_via_agp_t __user *) data,
+				 sizeof(agp));
 
 	AgpHeap = via_mmInit(agp.offset, agp.size);
 
@@ -92,7 +93,7 @@ int via_fb_init(DRM_IOCTL_ARGS)
 {
 	drm_via_fb_t fb;
 
-	DRM_COPY_FROM_USER_IOCTL(fb, (drm_via_fb_t *) data, sizeof(fb));
+	DRM_COPY_FROM_USER_IOCTL(fb, (drm_via_fb_t __user *) data, sizeof(fb));
 
 	FBHeap = via_mmInit(fb.offset, fb.size);
 
@@ -193,19 +194,20 @@ int via_mem_alloc(DRM_IOCTL_ARGS)
 {
 	drm_via_mem_t mem;
 
-	DRM_COPY_FROM_USER_IOCTL(mem, (drm_via_mem_t *) data, sizeof(mem));
+	DRM_COPY_FROM_USER_IOCTL(mem, (drm_via_mem_t __user *) data,
+				 sizeof(mem));
 
 	switch (mem.type) {
 	case VIDEO:
 		if (via_fb_alloc(&mem) < 0)
 			return -EFAULT;
-		DRM_COPY_TO_USER_IOCTL((drm_via_mem_t *) data, mem,
+		DRM_COPY_TO_USER_IOCTL((drm_via_mem_t __user *) data, mem,
 				       sizeof(mem));
 		return 0;
 	case AGP:
 		if (via_agp_alloc(&mem) < 0)
 			return -EFAULT;
-		DRM_COPY_TO_USER_IOCTL((drm_via_mem_t *) data, mem,
+		DRM_COPY_TO_USER_IOCTL((drm_via_mem_t __user *) data, mem,
 				       sizeof(mem));
 		return 0;
 	}
@@ -289,7 +291,8 @@ int via_mem_free(DRM_IOCTL_ARGS)
 {
 	drm_via_mem_t mem;
 
-	DRM_COPY_FROM_USER_IOCTL(mem, (drm_via_mem_t *) data, sizeof(mem));
+	DRM_COPY_FROM_USER_IOCTL(mem, (drm_via_mem_t __user *) data,
+				 sizeof(mem));
 
 	switch (mem.type) {
 
diff --git a/drivers/char/drm/via_video.c b/drivers/char/drm/via_video.c
index 37a61c67b29..1e2d444587b 100644
--- a/drivers/char/drm/via_video.c
+++ b/drivers/char/drm/via_video.c
@@ -76,7 +76,8 @@ via_decoder_futex(DRM_IOCTL_ARGS)
 
 	DRM_DEBUG("%s\n", __FUNCTION__);
 
-	DRM_COPY_FROM_USER_IOCTL(fx, (drm_via_futex_t *) data, sizeof(fx));
+	DRM_COPY_FROM_USER_IOCTL(fx, (drm_via_futex_t __user *) data,
+				 sizeof(fx));
 
 	if (fx.lock > VIA_NR_XVMC_LOCKS)
 		return -EFAULT;
diff --git a/drivers/char/ipmi/ipmi_si_intf.c b/drivers/char/ipmi/ipmi_si_intf.c
index 298574e1606..a44b97304e9 100644
--- a/drivers/char/ipmi/ipmi_si_intf.c
+++ b/drivers/char/ipmi/ipmi_si_intf.c
@@ -1726,7 +1726,7 @@ static int dmi_table(u32 base, int len, int num)
 	return status;
 }
 
-inline static int dmi_checksum(u8 *buf)
+static inline int dmi_checksum(u8 *buf)
 {
 	u8   sum=0;
 	int  a;
diff --git a/drivers/char/ipmi/ipmi_watchdog.c b/drivers/char/ipmi/ipmi_watchdog.c
index fcd1c02a32c..d35a953961c 100644
--- a/drivers/char/ipmi/ipmi_watchdog.c
+++ b/drivers/char/ipmi/ipmi_watchdog.c
@@ -131,11 +131,7 @@
 #define	WDIOC_GET_PRETIMEOUT     _IOW(WATCHDOG_IOCTL_BASE, 22, int)
 #endif
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout;
-#endif
+static int nowayout = WATCHDOG_NOWAYOUT;
 
 static ipmi_user_t watchdog_user = NULL;
 
diff --git a/drivers/char/keyboard.c b/drivers/char/keyboard.c
index 7b19e02f112..523fd3c8bba 100644
--- a/drivers/char/keyboard.c
+++ b/drivers/char/keyboard.c
@@ -198,10 +198,10 @@ int setkeycode(unsigned int scancode, unsigned int keycode)
 
 	if (scancode >= dev->keycodemax)
 		return -EINVAL;
-	if (keycode > KEY_MAX)
-		return -EINVAL;
 	if (keycode < 0 || keycode > KEY_MAX)
 		return -EINVAL;
+	if (keycode >> (dev->keycodesize * 8))
+		return -EINVAL;
 
 	oldkey = SET_INPUT_KEYCODE(dev, scancode, keycode);
 
diff --git a/drivers/char/rio/rioboot.c b/drivers/char/rio/rioboot.c
index a8be11dfcba..34cbb13aad4 100644
--- a/drivers/char/rio/rioboot.c
+++ b/drivers/char/rio/rioboot.c
@@ -902,7 +902,7 @@ static int RIOBootComplete( struct rio_info *p, struct Host *HostP, uint Rup, st
 	       (HostP->Mapping[entry].RtaUniqueNum==RtaUniq))
 	    {
 	        HostP->Mapping[entry].Flags |= RTA_BOOTED|RTA_NEWBOOT;
-#if NEED_TO_FIX
+#ifdef NEED_TO_FIX
 		RIO_SV_BROADCAST(HostP->svFlags[entry]);
 #endif
 		if ( (sysport=HostP->Mapping[entry].SysPort) != NO_PORT )
@@ -918,7 +918,7 @@ static int RIOBootComplete( struct rio_info *p, struct Host *HostP, uint Rup, st
 		   {
 			entry2 = HostP->Mapping[entry].ID2 - 1;
 			HostP->Mapping[entry2].Flags |= RTA_BOOTED|RTA_NEWBOOT;
-#if NEED_TO_FIX
+#ifdef NEED_TO_FIX
 			RIO_SV_BROADCAST(HostP->svFlags[entry2]);
 #endif
 			sysport = HostP->Mapping[entry2].SysPort;
@@ -1143,7 +1143,7 @@ static int RIOBootComplete( struct rio_info *p, struct Host *HostP, uint Rup, st
 		    CCOPY( MapP->Name, HostP->Mapping[entry].Name, MAX_NAME_LEN );
 		    HostP->Mapping[entry].Flags =
 		     SLOT_IN_USE | RTA_BOOTED | RTA_NEWBOOT;
-#if NEED_TO_FIX
+#ifdef NEED_TO_FIX
 		    RIO_SV_BROADCAST(HostP->svFlags[entry]);
 #endif
 		    RIOReMapPorts( p, HostP, &HostP->Mapping[entry] );
@@ -1159,7 +1159,7 @@ static int RIOBootComplete( struct rio_info *p, struct Host *HostP, uint Rup, st
    "This RTA has a tentative entry on another host - delete that entry (1)\n");
 		    HostP->Mapping[entry].Flags =
 		     SLOT_TENTATIVE | RTA_BOOTED | RTA_NEWBOOT;
-#if NEED_TO_FIX
+#ifdef NEED_TO_FIX
 		    RIO_SV_BROADCAST(HostP->svFlags[entry]);
 #endif
 		}
@@ -1169,7 +1169,7 @@ static int RIOBootComplete( struct rio_info *p, struct Host *HostP, uint Rup, st
 		    {
 			HostP->Mapping[entry2].Flags = SLOT_IN_USE |
 			 RTA_BOOTED | RTA_NEWBOOT | RTA16_SECOND_SLOT;
-#if NEED_TO_FIX
+#ifdef NEED_TO_FIX
 			RIO_SV_BROADCAST(HostP->svFlags[entry2]);
 #endif
 			HostP->Mapping[entry2].SysPort = MapP2->SysPort;
@@ -1188,7 +1188,7 @@ static int RIOBootComplete( struct rio_info *p, struct Host *HostP, uint Rup, st
 		    else
 			HostP->Mapping[entry2].Flags = SLOT_TENTATIVE |
 			 RTA_BOOTED | RTA_NEWBOOT | RTA16_SECOND_SLOT;
-#if NEED_TO_FIX
+#ifdef NEED_TO_FIX
 			RIO_SV_BROADCAST(HostP->svFlags[entry2]);
 #endif
 		    bzero( (caddr_t)MapP2, sizeof(struct Map) );
diff --git a/drivers/char/rio/rioroute.c b/drivers/char/rio/rioroute.c
index 106b31f48a2..e9564c9fb37 100644
--- a/drivers/char/rio/rioroute.c
+++ b/drivers/char/rio/rioroute.c
@@ -1023,7 +1023,7 @@ RIOFreeDisconnected(struct rio_info *p, struct Host *HostP, int unit)
     if (link < LINKS_PER_UNIT)
 	    return 1;
 
-#if NEED_TO_FIX_THIS
+#ifdef NEED_TO_FIX_THIS
     /* Ok so all the links are disconnected. But we may have only just
     ** made this slot tentative and not yet received a topology update.
     ** Lets check how long ago we made it tentative.
diff --git a/drivers/char/rio/riotable.c b/drivers/char/rio/riotable.c
index 8fb26ad2aa1..e45bc275907 100644
--- a/drivers/char/rio/riotable.c
+++ b/drivers/char/rio/riotable.c
@@ -771,7 +771,7 @@ int RIOAssignRta( struct rio_info *p, struct Map *MapP )
 	    if ((MapP->Flags & RTA16_SECOND_SLOT) == 0)
 	      CCOPY( MapP->Name, HostMapP->Name, MAX_NAME_LEN );
 	    HostMapP->Flags = SLOT_IN_USE | RTA_BOOTED;
-#if NEED_TO_FIX
+#ifdef NEED_TO_FIX
 	    RIO_SV_BROADCAST(p->RIOHosts[host].svFlags[MapP->ID-1]);
 #endif
 	    if (MapP->Flags & RTA16_SECOND_SLOT)
diff --git a/drivers/char/rtc.c b/drivers/char/rtc.c
index d8f9e94ae47..cd4fe8b1709 100644
--- a/drivers/char/rtc.c
+++ b/drivers/char/rtc.c
@@ -1209,6 +1209,7 @@ static int rtc_proc_open(struct inode *inode, struct file *file)
 
 void rtc_get_rtc_time(struct rtc_time *rtc_tm)
 {
+	unsigned long uip_watchdog = jiffies;
 	unsigned char ctrl;
 #ifdef CONFIG_MACH_DECSTATION
 	unsigned int real_year;
@@ -1224,8 +1225,10 @@ void rtc_get_rtc_time(struct rtc_time *rtc_tm)
 	 * Once the read clears, read the RTC time (again via ioctl). Easy.
 	 */
 
-	if (rtc_is_updating() != 0)
-		msleep(20);
+	while (rtc_is_updating() != 0 && jiffies - uip_watchdog < 2*HZ/100) {
+		barrier();
+		cpu_relax();
+	}
 
 	/*
 	 * Only the values that we read from the RTC are set. We leave
diff --git a/drivers/char/sonypi.c b/drivers/char/sonypi.c
index fd042060809..cefbe985e55 100644
--- a/drivers/char/sonypi.c
+++ b/drivers/char/sonypi.c
@@ -439,6 +439,11 @@ static struct {
 	{ 0, 0 },
 };
 
+struct sonypi_keypress {
+	struct input_dev *dev;
+	int key;
+};
+
 static struct sonypi_device {
 	struct pci_dev *dev;
 	struct platform_device *pdev;
@@ -710,22 +715,61 @@ static void sonypi_setbluetoothpower(u8 state)
 
 static void input_keyrelease(void *data)
 {
-	struct input_dev *input_dev;
-	int key;
-
-	while (1) {
-		if (kfifo_get(sonypi_device.input_fifo,
-			      (unsigned char *)&input_dev,
-			      sizeof(input_dev)) != sizeof(input_dev))
-			return;
-		if (kfifo_get(sonypi_device.input_fifo,
-			      (unsigned char *)&key,
-			      sizeof(key)) != sizeof(key))
-			return;
+	struct sonypi_keypress kp;
 
+	while (kfifo_get(sonypi_device.input_fifo, (unsigned char *)&kp,
+			 sizeof(kp)) == sizeof(kp)) {
 		msleep(10);
-		input_report_key(input_dev, key, 0);
-		input_sync(input_dev);
+		input_report_key(kp.dev, kp.key, 0);
+		input_sync(kp.dev);
+	}
+}
+
+static void sonypi_report_input_event(u8 event)
+{
+	struct input_dev *jog_dev = &sonypi_device.input_jog_dev;
+	struct input_dev *key_dev = &sonypi_device.input_key_dev;
+	struct sonypi_keypress kp = { NULL };
+	int i;
+
+	switch (event) {
+	case SONYPI_EVENT_JOGDIAL_UP:
+	case SONYPI_EVENT_JOGDIAL_UP_PRESSED:
+		input_report_rel(jog_dev, REL_WHEEL, 1);
+		input_sync(jog_dev);
+		break;
+
+	case SONYPI_EVENT_JOGDIAL_DOWN:
+	case SONYPI_EVENT_JOGDIAL_DOWN_PRESSED:
+		input_report_rel(jog_dev, REL_WHEEL, -1);
+		input_sync(jog_dev);
+		break;
+
+	case SONYPI_EVENT_JOGDIAL_PRESSED:
+		kp.key = BTN_MIDDLE;
+		kp.dev = jog_dev;
+		break;
+
+	case SONYPI_EVENT_FNKEY_RELEASED:
+		/* Nothing, not all VAIOs generate this event */
+		break;
+
+	default:
+		for (i = 0; sonypi_inputkeys[i].sonypiev; i++)
+			if (event == sonypi_inputkeys[i].sonypiev) {
+				kp.dev = key_dev;
+				kp.key = sonypi_inputkeys[i].inputev;
+				break;
+			}
+		break;
+	}
+
+	if (kp.dev) {
+		input_report_key(kp.dev, kp.key, 1);
+		input_sync(kp.dev);
+		kfifo_put(sonypi_device.input_fifo,
+			  (unsigned char *)&kp, sizeof(kp));
+		schedule_work(&sonypi_device.input_work);
 	}
 }
 
@@ -768,51 +812,8 @@ found:
 		printk(KERN_INFO
 		       "sonypi: event port1=0x%02x,port2=0x%02x\n", v1, v2);
 
-	if (useinput) {
-		struct input_dev *input_jog_dev = &sonypi_device.input_jog_dev;
-		struct input_dev *input_key_dev = &sonypi_device.input_key_dev;
-		switch (event) {
-		case SONYPI_EVENT_JOGDIAL_UP:
-		case SONYPI_EVENT_JOGDIAL_UP_PRESSED:
-			input_report_rel(input_jog_dev, REL_WHEEL, 1);
-			break;
-		case SONYPI_EVENT_JOGDIAL_DOWN:
-		case SONYPI_EVENT_JOGDIAL_DOWN_PRESSED:
-			input_report_rel(input_jog_dev, REL_WHEEL, -1);
-			break;
-		case SONYPI_EVENT_JOGDIAL_PRESSED: {
-			int key = BTN_MIDDLE;
-			input_report_key(input_jog_dev, key, 1);
-			kfifo_put(sonypi_device.input_fifo,
-				  (unsigned char *)&input_jog_dev,
-				  sizeof(input_jog_dev));
-			kfifo_put(sonypi_device.input_fifo,
-				  (unsigned char *)&key, sizeof(key));
-			break;
-		}
-		case SONYPI_EVENT_FNKEY_RELEASED:
-			/* Nothing, not all VAIOs generate this event */
-			break;
-		}
-		input_sync(input_jog_dev);
-
-		for (i = 0; sonypi_inputkeys[i].sonypiev; i++) {
-			int key;
-
-			if (event != sonypi_inputkeys[i].sonypiev)
-				continue;
-
-			key = sonypi_inputkeys[i].inputev;
-			input_report_key(input_key_dev, key, 1);
-			kfifo_put(sonypi_device.input_fifo,
-				  (unsigned char *)&input_key_dev,
-				  sizeof(input_key_dev));
-			kfifo_put(sonypi_device.input_fifo,
-				  (unsigned char *)&key, sizeof(key));
-		}
-		input_sync(input_key_dev);
-		schedule_work(&sonypi_device.input_work);
-	}
+	if (useinput)
+		sonypi_report_input_event(event);
 
 	kfifo_put(sonypi_device.fifo, (unsigned char *)&event, sizeof(event));
 	kill_fasync(&sonypi_device.fifo_async, SIGIO, POLL_IN);
@@ -1227,14 +1228,7 @@ static int __devinit sonypi_probe(void)
 		sonypi_device.input_jog_dev.keybit[LONG(BTN_MOUSE)] =
 			BIT(BTN_MIDDLE);
 		sonypi_device.input_jog_dev.relbit[0] = BIT(REL_WHEEL);
-		sonypi_device.input_jog_dev.name =
-			kmalloc(sizeof(SONYPI_JOG_INPUTNAME), GFP_KERNEL);
-		if (!sonypi_device.input_jog_dev.name) {
-			printk(KERN_ERR "sonypi: kmalloc failed\n");
-			ret = -ENOMEM;
-			goto out_inkmallocinput1;
-		}
-		sprintf(sonypi_device.input_jog_dev.name, SONYPI_JOG_INPUTNAME);
+		sonypi_device.input_jog_dev.name = SONYPI_JOG_INPUTNAME;
 		sonypi_device.input_jog_dev.id.bustype = BUS_ISA;
 		sonypi_device.input_jog_dev.id.vendor = PCI_VENDOR_ID_SONY;
 
@@ -1248,14 +1242,7 @@ static int __devinit sonypi_probe(void)
 			if (sonypi_inputkeys[i].inputev)
 				set_bit(sonypi_inputkeys[i].inputev,
 					sonypi_device.input_key_dev.keybit);
-		sonypi_device.input_key_dev.name =
-			kmalloc(sizeof(SONYPI_KEY_INPUTNAME), GFP_KERNEL);
-		if (!sonypi_device.input_key_dev.name) {
-			printk(KERN_ERR "sonypi: kmalloc failed\n");
-			ret = -ENOMEM;
-			goto out_inkmallocinput2;
-		}
-		sprintf(sonypi_device.input_key_dev.name, SONYPI_KEY_INPUTNAME);
+		sonypi_device.input_key_dev.name = SONYPI_KEY_INPUTNAME;
 		sonypi_device.input_key_dev.id.bustype = BUS_ISA;
 		sonypi_device.input_key_dev.id.vendor = PCI_VENDOR_ID_SONY;
 
@@ -1313,11 +1300,7 @@ out_platformdev:
 	kfifo_free(sonypi_device.input_fifo);
 out_infifo:
 	input_unregister_device(&sonypi_device.input_key_dev);
-	kfree(sonypi_device.input_key_dev.name);
-out_inkmallocinput2:
 	input_unregister_device(&sonypi_device.input_jog_dev);
-	kfree(sonypi_device.input_jog_dev.name);
-out_inkmallocinput1:
 	free_irq(sonypi_device.irq, sonypi_irq);
 out_reqirq:
 	release_region(sonypi_device.ioport1, sonypi_device.region_size);
@@ -1337,13 +1320,14 @@ static void __devexit sonypi_remove(void)
 {
 	sonypi_disable();
 
+	synchronize_sched();  /* Allow sonypi interrupt to complete. */
+	flush_scheduled_work();
+
 	platform_device_unregister(sonypi_device.pdev);
 
 	if (useinput) {
 		input_unregister_device(&sonypi_device.input_key_dev);
-		kfree(sonypi_device.input_key_dev.name);
 		input_unregister_device(&sonypi_device.input_jog_dev);
-		kfree(sonypi_device.input_jog_dev.name);
 		kfifo_free(sonypi_device.input_fifo);
 	}
 
diff --git a/drivers/char/tpm/Kconfig b/drivers/char/tpm/Kconfig
index 7a969778915..79e9832ef1f 100644
--- a/drivers/char/tpm/Kconfig
+++ b/drivers/char/tpm/Kconfig
@@ -17,6 +17,8 @@ config TCG_TPM
 	  obtained at: <http://sourceforge.net/projects/trousers>.  To 
 	  compile this driver as a module, choose M here; the module 
 	  will be called tpm. If unsure, say N.
+	  Note: For more TPM drivers enable CONFIG_PNP, CONFIG_ACPI_BUS
+	  and CONFIG_PNPACPI.
 
 config TCG_NSC
 	tristate "National Semiconductor TPM Interface"
@@ -35,5 +37,17 @@ config TCG_ATMEL
 	  will be accessible from within Linux.  To compile this driver 
 	  as a module, choose M here; the module will be called tpm_atmel.
 
+config TCG_INFINEON
+	tristate "Infineon Technologies TPM Interface"
+	depends on TCG_TPM && PNPACPI
+	---help---
+	  If you have a TPM security chip from Infineon Technologies
+	  (either SLD 9630 TT 1.1 or SLB 9635 TT 1.2) say Yes and it
+	  will be accessible from within Linux.
+	  To compile this driver as a module, choose M here; the module
+	  will be called tpm_infineon.
+	  Further information on this driver and the supported hardware
+	  can be found at http://www.prosec.rub.de/tpm
+
 endmenu
 
diff --git a/drivers/char/tpm/Makefile b/drivers/char/tpm/Makefile
index 736d3df266f..2392e404e8d 100644
--- a/drivers/char/tpm/Makefile
+++ b/drivers/char/tpm/Makefile
@@ -4,4 +4,4 @@
 obj-$(CONFIG_TCG_TPM) += tpm.o
 obj-$(CONFIG_TCG_NSC) += tpm_nsc.o
 obj-$(CONFIG_TCG_ATMEL) += tpm_atmel.o
-
+obj-$(CONFIG_TCG_INFINEON) += tpm_infineon.o
diff --git a/drivers/char/tpm/tpm_infineon.c b/drivers/char/tpm/tpm_infineon.c
new file mode 100644
index 00000000000..dc8c540391f
--- /dev/null
+++ b/drivers/char/tpm/tpm_infineon.c
@@ -0,0 +1,533 @@
+/*
+ * Description:
+ * Device Driver for the Infineon Technologies
+ * SLD 9630 TT 1.1 and SLB 9635 TT 1.2 Trusted Platform Module
+ * Specifications at www.trustedcomputinggroup.org
+ *
+ * Copyright (C) 2005, Marcel Selhorst <selhorst@crypto.rub.de>
+ * Applied Data Security Group, Ruhr-University Bochum, Germany
+ * Project-Homepage: http://www.prosec.rub.de/tpm
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation, version 2 of the
+ * License.
+ */
+
+#include <acpi/acpi_bus.h>
+#include <linux/pnp.h>
+#include "tpm.h"
+
+/* Infineon specific definitions */
+/* maximum number of WTX-packages */
+#define	TPM_MAX_WTX_PACKAGES 	50
+/* msleep-Time for WTX-packages */
+#define	TPM_WTX_MSLEEP_TIME 	20
+/* msleep-Time --> Interval to check status register */
+#define	TPM_MSLEEP_TIME 	3
+/* gives number of max. msleep()-calls before throwing timeout */
+#define	TPM_MAX_TRIES		5000
+#define	TPM_INFINEON_DEV_VEN_VALUE	0x15D1
+
+/* These values will be filled after ACPI-call */
+static int TPM_INF_DATA = 0;
+static int TPM_INF_ADDR = 0;
+
+/* TPM header definitions */
+enum infineon_tpm_header {
+	TPM_VL_VER = 0x01,
+	TPM_VL_CHANNEL_CONTROL = 0x07,
+	TPM_VL_CHANNEL_PERSONALISATION = 0x0A,
+	TPM_VL_CHANNEL_TPM = 0x0B,
+	TPM_VL_CONTROL = 0x00,
+	TPM_INF_NAK = 0x15,
+	TPM_CTRL_WTX = 0x10,
+	TPM_CTRL_WTX_ABORT = 0x18,
+	TPM_CTRL_WTX_ABORT_ACK = 0x18,
+	TPM_CTRL_ERROR = 0x20,
+	TPM_CTRL_CHAININGACK = 0x40,
+	TPM_CTRL_CHAINING = 0x80,
+	TPM_CTRL_DATA = 0x04,
+	TPM_CTRL_DATA_CHA = 0x84,
+	TPM_CTRL_DATA_CHA_ACK = 0xC4
+};
+
+enum infineon_tpm_register {
+	WRFIFO = 0x00,
+	RDFIFO = 0x01,
+	STAT = 0x02,
+	CMD = 0x03
+};
+
+enum infineon_tpm_command_bits {
+	CMD_DIS = 0x00,
+	CMD_LP = 0x01,
+	CMD_RES = 0x02,
+	CMD_IRQC = 0x06
+};
+
+enum infineon_tpm_status_bits {
+	STAT_XFE = 0x00,
+	STAT_LPA = 0x01,
+	STAT_FOK = 0x02,
+	STAT_TOK = 0x03,
+	STAT_IRQA = 0x06,
+	STAT_RDA = 0x07
+};
+
+/* some outgoing values */
+enum infineon_tpm_values {
+	CHIP_ID1 = 0x20,
+	CHIP_ID2 = 0x21,
+	TPM_DAR = 0x30,
+	RESET_LP_IRQC_DISABLE = 0x41,
+	ENABLE_REGISTER_PAIR = 0x55,
+	IOLIMH = 0x60,
+	IOLIML = 0x61,
+	DISABLE_REGISTER_PAIR = 0xAA,
+	IDVENL = 0xF1,
+	IDVENH = 0xF2,
+	IDPDL = 0xF3,
+	IDPDH = 0xF4
+};
+
+static int number_of_wtx;
+
+static int empty_fifo(struct tpm_chip *chip, int clear_wrfifo)
+{
+	int status;
+	int check = 0;
+	int i;
+
+	if (clear_wrfifo) {
+		for (i = 0; i < 4096; i++) {
+			status = inb(chip->vendor->base + WRFIFO);
+			if (status == 0xff) {
+				if (check == 5)
+					break;
+				else
+					check++;
+			}
+		}
+	}
+	/* Note: The values which are currently in the FIFO of the TPM
+	   are thrown away since there is no usage for them. Usually,
+	   this has nothing to say, since the TPM will give its answer
+	   immediately or will be aborted anyway, so the data here is
+	   usually garbage and useless.
+	   We have to clean this, because the next communication with
+	   the TPM would be rubbish, if there is still some old data
+	   in the Read FIFO.
+	 */
+	i = 0;
+	do {
+		status = inb(chip->vendor->base + RDFIFO);
+		status = inb(chip->vendor->base + STAT);
+		i++;
+		if (i == TPM_MAX_TRIES)
+			return -EIO;
+	} while ((status & (1 << STAT_RDA)) != 0);
+	return 0;
+}
+
+static int wait(struct tpm_chip *chip, int wait_for_bit)
+{
+	int status;
+	int i;
+	for (i = 0; i < TPM_MAX_TRIES; i++) {
+		status = inb(chip->vendor->base + STAT);
+		/* check the status-register if wait_for_bit is set */
+		if (status & 1 << wait_for_bit)
+			break;
+		msleep(TPM_MSLEEP_TIME);
+	}
+	if (i == TPM_MAX_TRIES) {	/* timeout occurs */
+		if (wait_for_bit == STAT_XFE)
+			dev_err(&chip->pci_dev->dev,
+				"Timeout in wait(STAT_XFE)\n");
+		if (wait_for_bit == STAT_RDA)
+			dev_err(&chip->pci_dev->dev,
+				"Timeout in wait(STAT_RDA)\n");
+		return -EIO;
+	}
+	return 0;
+};
+
+static void wait_and_send(struct tpm_chip *chip, u8 sendbyte)
+{
+	wait(chip, STAT_XFE);
+	outb(sendbyte, chip->vendor->base + WRFIFO);
+}
+
+    /* Note: WTX means Waiting-Time-Extension. Whenever the TPM needs more
+       calculation time, it sends a WTX-package, which has to be acknowledged
+       or aborted. This usually occurs if you are hammering the TPM with key
+       creation. Set the maximum number of WTX-packages in the definitions
+       above, if the number is reached, the waiting-time will be denied
+       and the TPM command has to be resend.
+     */
+
+static void tpm_wtx(struct tpm_chip *chip)
+{
+	number_of_wtx++;
+	dev_info(&chip->pci_dev->dev, "Granting WTX (%02d / %02d)\n",
+		 number_of_wtx, TPM_MAX_WTX_PACKAGES);
+	wait_and_send(chip, TPM_VL_VER);
+	wait_and_send(chip, TPM_CTRL_WTX);
+	wait_and_send(chip, 0x00);
+	wait_and_send(chip, 0x00);
+	msleep(TPM_WTX_MSLEEP_TIME);
+}
+
+static void tpm_wtx_abort(struct tpm_chip *chip)
+{
+	dev_info(&chip->pci_dev->dev, "Aborting WTX\n");
+	wait_and_send(chip, TPM_VL_VER);
+	wait_and_send(chip, TPM_CTRL_WTX_ABORT);
+	wait_and_send(chip, 0x00);
+	wait_and_send(chip, 0x00);
+	number_of_wtx = 0;
+	msleep(TPM_WTX_MSLEEP_TIME);
+}
+
+static int tpm_inf_recv(struct tpm_chip *chip, u8 * buf, size_t count)
+{
+	int i;
+	int ret;
+	u32 size = 0;
+
+recv_begin:
+	/* start receiving header */
+	for (i = 0; i < 4; i++) {
+		ret = wait(chip, STAT_RDA);
+		if (ret)
+			return -EIO;
+		buf[i] = inb(chip->vendor->base + RDFIFO);
+	}
+
+	if (buf[0] != TPM_VL_VER) {
+		dev_err(&chip->pci_dev->dev,
+			"Wrong transport protocol implementation!\n");
+		return -EIO;
+	}
+
+	if (buf[1] == TPM_CTRL_DATA) {
+		/* size of the data received */
+		size = ((buf[2] << 8) | buf[3]);
+
+		for (i = 0; i < size; i++) {
+			wait(chip, STAT_RDA);
+			buf[i] = inb(chip->vendor->base + RDFIFO);
+		}
+
+		if ((size == 0x6D00) && (buf[1] == 0x80)) {
+			dev_err(&chip->pci_dev->dev,
+				"Error handling on vendor layer!\n");
+			return -EIO;
+		}
+
+		for (i = 0; i < size; i++)
+			buf[i] = buf[i + 6];
+
+		size = size - 6;
+		return size;
+	}
+
+	if (buf[1] == TPM_CTRL_WTX) {
+		dev_info(&chip->pci_dev->dev, "WTX-package received\n");
+		if (number_of_wtx < TPM_MAX_WTX_PACKAGES) {
+			tpm_wtx(chip);
+			goto recv_begin;
+		} else {
+			tpm_wtx_abort(chip);
+			goto recv_begin;
+		}
+	}
+
+	if (buf[1] == TPM_CTRL_WTX_ABORT_ACK) {
+		dev_info(&chip->pci_dev->dev, "WTX-abort acknowledged\n");
+		return size;
+	}
+
+	if (buf[1] == TPM_CTRL_ERROR) {
+		dev_err(&chip->pci_dev->dev, "ERROR-package received:\n");
+		if (buf[4] == TPM_INF_NAK)
+			dev_err(&chip->pci_dev->dev,
+				"-> Negative acknowledgement"
+				" - retransmit command!\n");
+		return -EIO;
+	}
+	return -EIO;
+}
+
+static int tpm_inf_send(struct tpm_chip *chip, u8 * buf, size_t count)
+{
+	int i;
+	int ret;
+	u8 count_high, count_low, count_4, count_3, count_2, count_1;
+
+	/* Disabling Reset, LP and IRQC */
+	outb(RESET_LP_IRQC_DISABLE, chip->vendor->base + CMD);
+
+	ret = empty_fifo(chip, 1);
+	if (ret) {
+		dev_err(&chip->pci_dev->dev, "Timeout while clearing FIFO\n");
+		return -EIO;
+	}
+
+	ret = wait(chip, STAT_XFE);
+	if (ret)
+		return -EIO;
+
+	count_4 = (count & 0xff000000) >> 24;
+	count_3 = (count & 0x00ff0000) >> 16;
+	count_2 = (count & 0x0000ff00) >> 8;
+	count_1 = (count & 0x000000ff);
+	count_high = ((count + 6) & 0xffffff00) >> 8;
+	count_low = ((count + 6) & 0x000000ff);
+
+	/* Sending Header */
+	wait_and_send(chip, TPM_VL_VER);
+	wait_and_send(chip, TPM_CTRL_DATA);
+	wait_and_send(chip, count_high);
+	wait_and_send(chip, count_low);
+
+	/* Sending Data Header */
+	wait_and_send(chip, TPM_VL_VER);
+	wait_and_send(chip, TPM_VL_CHANNEL_TPM);
+	wait_and_send(chip, count_4);
+	wait_and_send(chip, count_3);
+	wait_and_send(chip, count_2);
+	wait_and_send(chip, count_1);
+
+	/* Sending Data */
+	for (i = 0; i < count; i++) {
+		wait_and_send(chip, buf[i]);
+	}
+	return count;
+}
+
+static void tpm_inf_cancel(struct tpm_chip *chip)
+{
+	/*
+	   Since we are using the legacy mode to communicate
+	   with the TPM, we have no cancel functions, but have
+	   a workaround for interrupting the TPM through WTX.
+	 */
+}
+
+static DEVICE_ATTR(pubek, S_IRUGO, tpm_show_pubek, NULL);
+static DEVICE_ATTR(pcrs, S_IRUGO, tpm_show_pcrs, NULL);
+static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps, NULL);
+static DEVICE_ATTR(cancel, S_IWUSR | S_IWGRP, NULL, tpm_store_cancel);
+
+static struct attribute *inf_attrs[] = {
+	&dev_attr_pubek.attr,
+	&dev_attr_pcrs.attr,
+	&dev_attr_caps.attr,
+	&dev_attr_cancel.attr,
+	NULL,
+};
+
+static struct attribute_group inf_attr_grp = {.attrs = inf_attrs };
+
+static struct file_operations inf_ops = {
+	.owner = THIS_MODULE,
+	.llseek = no_llseek,
+	.open = tpm_open,
+	.read = tpm_read,
+	.write = tpm_write,
+	.release = tpm_release,
+};
+
+static struct tpm_vendor_specific tpm_inf = {
+	.recv = tpm_inf_recv,
+	.send = tpm_inf_send,
+	.cancel = tpm_inf_cancel,
+	.req_complete_mask = 0,
+	.req_complete_val = 0,
+	.attr_group = &inf_attr_grp,
+	.miscdev = {.fops = &inf_ops,},
+};
+
+static const struct pnp_device_id tpm_pnp_tbl[] = {
+	/* Infineon TPMs */
+	{"IFX0101", 0},
+	{"IFX0102", 0},
+	{"", 0}
+};
+
+static int __devinit tpm_inf_acpi_probe(struct pnp_dev *dev,
+					const struct pnp_device_id *dev_id)
+{
+	TPM_INF_ADDR = (pnp_port_start(dev, 0) & 0xff);
+	TPM_INF_DATA = ((TPM_INF_ADDR + 1) & 0xff);
+	tpm_inf.base = pnp_port_start(dev, 1);
+	dev_info(&dev->dev, "Found %s with ID %s\n",
+		 dev->name, dev_id->id);
+	if (!((tpm_inf.base >> 8) & 0xff))
+		tpm_inf.base = 0;
+	return 0;
+}
+
+static struct pnp_driver tpm_inf_pnp = {
+	.name = "tpm_inf_pnp",
+	.id_table = tpm_pnp_tbl,
+	.probe = tpm_inf_acpi_probe,
+};
+
+static int __devinit tpm_inf_probe(struct pci_dev *pci_dev,
+				   const struct pci_device_id *pci_id)
+{
+	int rc = 0;
+	u8 iol, ioh;
+	int vendorid[2];
+	int version[2];
+	int productid[2];
+	char chipname[20];
+
+	if (pci_enable_device(pci_dev))
+		return -EIO;
+
+	dev_info(&pci_dev->dev, "LPC-bus found at 0x%x\n", pci_id->device);
+
+	/* read IO-ports from ACPI */
+	pnp_register_driver(&tpm_inf_pnp);
+	pnp_unregister_driver(&tpm_inf_pnp);
+
+	/* Make sure, we have received valid config ports */
+	if (!TPM_INF_ADDR) {
+		pci_disable_device(pci_dev);
+		return -EIO;
+	}
+
+	/* query chip for its vendor, its version number a.s.o. */
+	outb(ENABLE_REGISTER_PAIR, TPM_INF_ADDR);
+	outb(IDVENL, TPM_INF_ADDR);
+	vendorid[1] = inb(TPM_INF_DATA);
+	outb(IDVENH, TPM_INF_ADDR);
+	vendorid[0] = inb(TPM_INF_DATA);
+	outb(IDPDL, TPM_INF_ADDR);
+	productid[1] = inb(TPM_INF_DATA);
+	outb(IDPDH, TPM_INF_ADDR);
+	productid[0] = inb(TPM_INF_DATA);
+	outb(CHIP_ID1, TPM_INF_ADDR);
+	version[1] = inb(TPM_INF_DATA);
+	outb(CHIP_ID2, TPM_INF_ADDR);
+	version[0] = inb(TPM_INF_DATA);
+
+	switch ((productid[0] << 8) | productid[1]) {
+	case 6:
+		sprintf(chipname, " (SLD 9630 TT 1.1)");
+		break;
+	case 11:
+		sprintf(chipname, " (SLB 9635 TT 1.2)");
+		break;
+	default:
+		sprintf(chipname, " (unknown chip)");
+		break;
+	}
+	chipname[19] = 0;
+
+	if ((vendorid[0] << 8 | vendorid[1]) == (TPM_INFINEON_DEV_VEN_VALUE)) {
+
+		if (tpm_inf.base == 0) {
+			dev_err(&pci_dev->dev, "No IO-ports found!\n");
+			pci_disable_device(pci_dev);
+			return -EIO;
+		}
+		/* configure TPM with IO-ports */
+		outb(IOLIMH, TPM_INF_ADDR);
+		outb(((tpm_inf.base >> 8) & 0xff), TPM_INF_DATA);
+		outb(IOLIML, TPM_INF_ADDR);
+		outb((tpm_inf.base & 0xff), TPM_INF_DATA);
+
+		/* control if IO-ports are set correctly */
+		outb(IOLIMH, TPM_INF_ADDR);
+		ioh = inb(TPM_INF_DATA);
+		outb(IOLIML, TPM_INF_ADDR);
+		iol = inb(TPM_INF_DATA);
+
+		if ((ioh << 8 | iol) != tpm_inf.base) {
+			dev_err(&pci_dev->dev,
+				"Could not set IO-ports to %04x\n",
+				tpm_inf.base);
+			pci_disable_device(pci_dev);
+			return -EIO;
+		}
+
+		/* activate register */
+		outb(TPM_DAR, TPM_INF_ADDR);
+		outb(0x01, TPM_INF_DATA);
+		outb(DISABLE_REGISTER_PAIR, TPM_INF_ADDR);
+
+		/* disable RESET, LP and IRQC */
+		outb(RESET_LP_IRQC_DISABLE, tpm_inf.base + CMD);
+
+		/* Finally, we're done, print some infos */
+		dev_info(&pci_dev->dev, "TPM found: "
+			 "config base 0x%x, "
+			 "io base 0x%x, "
+			 "chip version %02x%02x, "
+			 "vendor id %x%x (Infineon), "
+			 "product id %02x%02x"
+			 "%s\n",
+			 TPM_INF_ADDR,
+			 tpm_inf.base,
+			 version[0], version[1],
+			 vendorid[0], vendorid[1],
+			 productid[0], productid[1], chipname);
+
+		rc = tpm_register_hardware(pci_dev, &tpm_inf);
+		if (rc < 0) {
+			pci_disable_device(pci_dev);
+			return -ENODEV;
+		}
+		return 0;
+	} else {
+		dev_info(&pci_dev->dev, "No Infineon TPM found!\n");
+		pci_disable_device(pci_dev);
+		return -ENODEV;
+	}
+}
+
+static struct pci_device_id tpm_pci_tbl[] __devinitdata = {
+	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0)},
+	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12)},
+	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0)},
+	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12)},
+	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0)},
+	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0)},
+	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1)},
+	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_2)},
+	{0,}
+};
+
+MODULE_DEVICE_TABLE(pci, tpm_pci_tbl);
+
+static struct pci_driver inf_pci_driver = {
+	.name = "tpm_inf",
+	.id_table = tpm_pci_tbl,
+	.probe = tpm_inf_probe,
+	.remove = __devexit_p(tpm_remove),
+	.suspend = tpm_pm_suspend,
+	.resume = tpm_pm_resume,
+};
+
+static int __init init_inf(void)
+{
+	return pci_register_driver(&inf_pci_driver);
+}
+
+static void __exit cleanup_inf(void)
+{
+	pci_unregister_driver(&inf_pci_driver);
+}
+
+module_init(init_inf);
+module_exit(cleanup_inf);
+
+MODULE_AUTHOR("Marcel Selhorst <selhorst@crypto.rub.de>");
+MODULE_DESCRIPTION("Driver for Infineon TPM SLD 9630 TT 1.1 / SLB 9635 TT 1.2");
+MODULE_VERSION("1.5");
+MODULE_LICENSE("GPL");
diff --git a/drivers/char/watchdog/acquirewdt.c b/drivers/char/watchdog/acquirewdt.c
index 8f302121741..7289f4af93d 100644
--- a/drivers/char/watchdog/acquirewdt.c
+++ b/drivers/char/watchdog/acquirewdt.c
@@ -82,12 +82,7 @@ static int wdt_start = 0x443;
 module_param(wdt_start, int, 0);
 MODULE_PARM_DESC(wdt_start, "Acquire WDT 'start' io port (default 0x443)");
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/advantechwdt.c b/drivers/char/watchdog/advantechwdt.c
index ea73c8379bd..194a3fd36b9 100644
--- a/drivers/char/watchdog/advantechwdt.c
+++ b/drivers/char/watchdog/advantechwdt.c
@@ -73,12 +73,7 @@ static int timeout = WATCHDOG_TIMEOUT;	/* in seconds */
 module_param(timeout, int, 0);
 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. 1<= timeout <=63, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ".");
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/alim1535_wdt.c b/drivers/char/watchdog/alim1535_wdt.c
index 35dcbf8be7d..8338ca300e2 100644
--- a/drivers/char/watchdog/alim1535_wdt.c
+++ b/drivers/char/watchdog/alim1535_wdt.c
@@ -38,12 +38,7 @@ static int timeout = WATCHDOG_TIMEOUT;
 module_param(timeout, int, 0);
 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. (0<timeout<18000, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
@@ -317,7 +312,7 @@ static int ali_notify_sys(struct notifier_block *this, unsigned long code, void
  */
 
 static struct pci_device_id ali_pci_tbl[] = {
-	{ PCI_VENDOR_ID_AL, 1535, PCI_ANY_ID, PCI_ANY_ID,},
+	{ PCI_VENDOR_ID_AL, 0x1535, PCI_ANY_ID, PCI_ANY_ID,},
 	{ 0, },
 };
 MODULE_DEVICE_TABLE(pci, ali_pci_tbl);
diff --git a/drivers/char/watchdog/alim7101_wdt.c b/drivers/char/watchdog/alim7101_wdt.c
index 90c091d9e0f..c05ac188a4d 100644
--- a/drivers/char/watchdog/alim7101_wdt.c
+++ b/drivers/char/watchdog/alim7101_wdt.c
@@ -75,12 +75,7 @@ static unsigned long wdt_is_open;
 static char wdt_expect_close;
 static struct pci_dev *alim7101_pmu;
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/eurotechwdt.c b/drivers/char/watchdog/eurotechwdt.c
index 2a29a511df7..25c2f257561 100644
--- a/drivers/char/watchdog/eurotechwdt.c
+++ b/drivers/char/watchdog/eurotechwdt.c
@@ -72,12 +72,7 @@ static char *ev = "int";
 
 #define WDT_TIMEOUT		60                /* 1 minute */
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/i8xx_tco.c b/drivers/char/watchdog/i8xx_tco.c
index 5d07ee59679..f975dab1ddf 100644
--- a/drivers/char/watchdog/i8xx_tco.c
+++ b/drivers/char/watchdog/i8xx_tco.c
@@ -105,12 +105,7 @@ static int heartbeat = WATCHDOG_HEARTBEAT;  /* in seconds */
 module_param(heartbeat, int, 0);
 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2<heartbeat<39, default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/ib700wdt.c b/drivers/char/watchdog/ib700wdt.c
index d974f16e84d..cf60329eec8 100644
--- a/drivers/char/watchdog/ib700wdt.c
+++ b/drivers/char/watchdog/ib700wdt.c
@@ -117,12 +117,7 @@ static int wd_times[] = {
 
 static int wd_margin = WD_TIMO;
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/indydog.c b/drivers/char/watchdog/indydog.c
index 6af2c799b57..b4b94daba67 100644
--- a/drivers/char/watchdog/indydog.c
+++ b/drivers/char/watchdog/indydog.c
@@ -29,14 +29,9 @@
 #define PFX "indydog: "
 static int indydog_alive;
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
 #define WATCHDOG_TIMEOUT 30		/* 30 sec default timeout */
 
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/ixp2000_wdt.c b/drivers/char/watchdog/ixp2000_wdt.c
index 4b039516cc8..e7640bc4904 100644
--- a/drivers/char/watchdog/ixp2000_wdt.c
+++ b/drivers/char/watchdog/ixp2000_wdt.c
@@ -30,11 +30,7 @@
 #include <asm/hardware.h>
 #include <asm/uaccess.h>
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
+static int nowayout = WATCHDOG_NOWAYOUT;
 static unsigned int heartbeat = 60;	/* (secs) Default is 1 minute */
 static unsigned long wdt_status;
 
diff --git a/drivers/char/watchdog/ixp4xx_wdt.c b/drivers/char/watchdog/ixp4xx_wdt.c
index 83df369113a..8d916afbf4f 100644
--- a/drivers/char/watchdog/ixp4xx_wdt.c
+++ b/drivers/char/watchdog/ixp4xx_wdt.c
@@ -27,11 +27,7 @@
 #include <asm/hardware.h>
 #include <asm/uaccess.h>
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
+static int nowayout = WATCHDOG_NOWAYOUT;
 static int heartbeat = 60;	/* (secs) Default is 1 minute */
 static unsigned long wdt_status;
 static unsigned long boot_status;
diff --git a/drivers/char/watchdog/machzwd.c b/drivers/char/watchdog/machzwd.c
index 9da395fa779..a9a20aad61e 100644
--- a/drivers/char/watchdog/machzwd.c
+++ b/drivers/char/watchdog/machzwd.c
@@ -94,12 +94,7 @@ MODULE_DESCRIPTION("MachZ ZF-Logic Watchdog driver");
 MODULE_LICENSE("GPL");
 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/mixcomwd.c b/drivers/char/watchdog/mixcomwd.c
index 3143e4a0753..c9b301dccec 100644
--- a/drivers/char/watchdog/mixcomwd.c
+++ b/drivers/char/watchdog/mixcomwd.c
@@ -62,12 +62,7 @@ static int mixcomwd_timer_alive;
 static struct timer_list mixcomwd_timer = TIMER_INITIALIZER(NULL, 0, 0);
 static char expect_close;
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/pcwd.c b/drivers/char/watchdog/pcwd.c
index 6ebce3f2ef9..427ad51b7a3 100644
--- a/drivers/char/watchdog/pcwd.c
+++ b/drivers/char/watchdog/pcwd.c
@@ -146,12 +146,7 @@ static int heartbeat = WATCHDOG_HEARTBEAT;
 module_param(heartbeat, int, 0);
 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2<=heartbeat<=7200, default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/pcwd_pci.c b/drivers/char/watchdog/pcwd_pci.c
index 8ce06662732..2b13afb09c5 100644
--- a/drivers/char/watchdog/pcwd_pci.c
+++ b/drivers/char/watchdog/pcwd_pci.c
@@ -103,12 +103,7 @@ static int heartbeat = WATCHDOG_HEARTBEAT;
 module_param(heartbeat, int, 0);
 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (0<heartbeat<65536, default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/pcwd_usb.c b/drivers/char/watchdog/pcwd_usb.c
index 1127201d73b..092e9b13375 100644
--- a/drivers/char/watchdog/pcwd_usb.c
+++ b/drivers/char/watchdog/pcwd_usb.c
@@ -79,12 +79,7 @@ static int heartbeat = WATCHDOG_HEARTBEAT;
 module_param(heartbeat, int, 0);
 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (0<heartbeat<65536, default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/s3c2410_wdt.c b/drivers/char/watchdog/s3c2410_wdt.c
index 1699d2c28ce..f85ac898a49 100644
--- a/drivers/char/watchdog/s3c2410_wdt.c
+++ b/drivers/char/watchdog/s3c2410_wdt.c
@@ -62,12 +62,7 @@
 #define CONFIG_S3C2410_WATCHDOG_ATBOOT		(0)
 #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME	(15)
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 static int tmr_margin	= CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME;
 static int tmr_atboot	= CONFIG_S3C2410_WATCHDOG_ATBOOT;
 static int soft_noboot	= 0;
diff --git a/drivers/char/watchdog/sa1100_wdt.c b/drivers/char/watchdog/sa1100_wdt.c
index 34e8f7b15e3..fb88b4041dc 100644
--- a/drivers/char/watchdog/sa1100_wdt.c
+++ b/drivers/char/watchdog/sa1100_wdt.c
@@ -36,17 +36,10 @@
 #include <asm/uaccess.h>
 
 #define OSCR_FREQ		CLOCK_TICK_RATE
-#define SA1100_CLOSE_MAGIC	(0x5afc4453)
 
 static unsigned long sa1100wdt_users;
-static int expect_close;
 static int pre_margin;
 static int boot_status;
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
 
 /*
  *	Allow only one person to hold it open
@@ -66,55 +59,33 @@ static int sa1100dog_open(struct inode *inode, struct file *file)
 }
 
 /*
- *	Shut off the timer.
- * 	Lock it in if it's a module and we defined ...NOWAYOUT
- *	Oddly, the watchdog can only be enabled, but we can turn off
- *	the interrupt, which appears to prevent the watchdog timing out.
+ * The watchdog cannot be disabled.
+ *
+ * Previous comments suggested that turning off the interrupt by
+ * clearing OIER[E3] would prevent the watchdog timing out but this
+ * does not appear to be true (at least on the PXA255).
  */
 static int sa1100dog_release(struct inode *inode, struct file *file)
 {
-	OSMR3 = OSCR + pre_margin;
-
-	if (expect_close == SA1100_CLOSE_MAGIC) {
-		OIER &= ~OIER_E3;
-	} else {
-		printk(KERN_CRIT "WATCHDOG: WDT device closed unexpectedly.  WDT will not stop!\n");
-	}
+	printk(KERN_CRIT "WATCHDOG: Device closed - timer will not stop\n");
 
 	clear_bit(1, &sa1100wdt_users);
-	expect_close = 0;
 
 	return 0;
 }
 
 static ssize_t sa1100dog_write(struct file *file, const char *data, size_t len, loff_t *ppos)
 {
-	if (len) {
-		if (!nowayout) {
-			size_t i;
-
-			expect_close = 0;
-
-			for (i = 0; i != len; i++) {
-				char c;
-
-				if (get_user(c, data + i))
-					return -EFAULT;
-				if (c == 'V')
-					expect_close = SA1100_CLOSE_MAGIC;
-			}
-		}
+	if (len)
 		/* Refresh OSMR3 timer. */
 		OSMR3 = OSCR + pre_margin;
-	}
 
 	return len;
 }
 
 static struct watchdog_info ident = {
-	.options	= WDIOF_CARDRESET | WDIOF_MAGICCLOSE |
-			  WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
-	.identity	= "SA1100 Watchdog",
+	.options	= WDIOF_CARDRESET | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
+	.identity	= "SA1100/PXA255 Watchdog",
 };
 
 static int sa1100dog_ioctl(struct inode *inode, struct file *file,
@@ -176,7 +147,7 @@ static struct file_operations sa1100dog_fops =
 static struct miscdevice sa1100dog_miscdev =
 {
 	.minor		= WATCHDOG_MINOR,
-	.name		= "SA1100/PXA2xx watchdog",
+	.name		= "watchdog",
 	.fops		= &sa1100dog_fops,
 };
 
@@ -198,7 +169,6 @@ static int __init sa1100dog_init(void)
 	if (ret == 0)
 		printk("SA1100/PXA2xx Watchdog Timer: timer margin %d sec\n",
 		       margin);
-
 	return ret;
 }
 
@@ -216,8 +186,5 @@ MODULE_DESCRIPTION("SA1100/PXA2xx Watchdog");
 module_param(margin, int, 0);
 MODULE_PARM_DESC(margin, "Watchdog margin in seconds (default 60s)");
 
-module_param(nowayout, int, 0);
-MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
-
 MODULE_LICENSE("GPL");
 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
diff --git a/drivers/char/watchdog/sbc60xxwdt.c b/drivers/char/watchdog/sbc60xxwdt.c
index d7de9880605..ed0bd55fbfc 100644
--- a/drivers/char/watchdog/sbc60xxwdt.c
+++ b/drivers/char/watchdog/sbc60xxwdt.c
@@ -98,12 +98,7 @@ static int timeout = WATCHDOG_TIMEOUT;	/* in seconds, will be multiplied by HZ t
 module_param(timeout, int, 0);
 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. (1<=timeout<=3600, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/sc1200wdt.c b/drivers/char/watchdog/sc1200wdt.c
index 24401e84729..515ce757204 100644
--- a/drivers/char/watchdog/sc1200wdt.c
+++ b/drivers/char/watchdog/sc1200wdt.c
@@ -91,12 +91,7 @@ MODULE_PARM_DESC(io, "io port");
 module_param(timeout, int, 0);
 MODULE_PARM_DESC(timeout, "range is 0-255 minutes, default is 1");
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/sc520_wdt.c b/drivers/char/watchdog/sc520_wdt.c
index f6d143e1900..72501be79b0 100644
--- a/drivers/char/watchdog/sc520_wdt.c
+++ b/drivers/char/watchdog/sc520_wdt.c
@@ -94,12 +94,7 @@ static int timeout = WATCHDOG_TIMEOUT;	/* in seconds, will be multiplied by HZ t
 module_param(timeout, int, 0);
 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. (1<=timeout<=3600, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/scx200_wdt.c b/drivers/char/watchdog/scx200_wdt.c
index b569670e4ed..c4568569f3a 100644
--- a/drivers/char/watchdog/scx200_wdt.c
+++ b/drivers/char/watchdog/scx200_wdt.c
@@ -39,15 +39,11 @@ MODULE_DESCRIPTION("NatSemi SCx200 Watchdog Driver");
 MODULE_LICENSE("GPL");
 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
 
-#ifndef CONFIG_WATCHDOG_NOWAYOUT
-#define CONFIG_WATCHDOG_NOWAYOUT 0
-#endif
-
 static int margin = 60;		/* in seconds */
 module_param(margin, int, 0);
 MODULE_PARM_DESC(margin, "Watchdog margin in seconds");
 
-static int nowayout = CONFIG_WATCHDOG_NOWAYOUT;
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close");
 
diff --git a/drivers/char/watchdog/shwdt.c b/drivers/char/watchdog/shwdt.c
index 3bc9272a474..1f4cab55b2e 100644
--- a/drivers/char/watchdog/shwdt.c
+++ b/drivers/char/watchdog/shwdt.c
@@ -75,11 +75,7 @@ static unsigned long next_heartbeat;
 #define WATCHDOG_HEARTBEAT 30			/* 30 sec default heartbeat */
 static int heartbeat = WATCHDOG_HEARTBEAT;	/* in seconds */
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
+static int nowayout = WATCHDOG_NOWAYOUT;
 
 /**
  * 	sh_wdt_start - Start the Watchdog
diff --git a/drivers/char/watchdog/softdog.c b/drivers/char/watchdog/softdog.c
index 98c7578740e..4d7ed931f5c 100644
--- a/drivers/char/watchdog/softdog.c
+++ b/drivers/char/watchdog/softdog.c
@@ -56,12 +56,7 @@ static int soft_margin = TIMER_MARGIN;	/* in seconds */
 module_param(soft_margin, int, 0);
 MODULE_PARM_DESC(soft_margin, "Watchdog soft_margin in seconds. (0<soft_margin<65536, default=" __MODULE_STRING(TIMER_MARGIN) ")");
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/w83627hf_wdt.c b/drivers/char/watchdog/w83627hf_wdt.c
index 813c97038f8..465e0fd0423 100644
--- a/drivers/char/watchdog/w83627hf_wdt.c
+++ b/drivers/char/watchdog/w83627hf_wdt.c
@@ -54,12 +54,7 @@ static int timeout = WATCHDOG_TIMEOUT;	/* in seconds */
 module_param(timeout, int, 0);
 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. 1<= timeout <=63, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ".");
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/w83877f_wdt.c b/drivers/char/watchdog/w83877f_wdt.c
index bccbd4d6ac2..52a8bd0a598 100644
--- a/drivers/char/watchdog/w83877f_wdt.c
+++ b/drivers/char/watchdog/w83877f_wdt.c
@@ -85,12 +85,7 @@ module_param(timeout, int, 0);
 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. (1<=timeout<=3600, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
 
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/wafer5823wdt.c b/drivers/char/watchdog/wafer5823wdt.c
index abb0bea45c0..7cf6c9bbf48 100644
--- a/drivers/char/watchdog/wafer5823wdt.c
+++ b/drivers/char/watchdog/wafer5823wdt.c
@@ -63,12 +63,7 @@ static int timeout = WD_TIMO;  /* in seconds */
 module_param(timeout, int, 0);
 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. 1<= timeout <=255, default=" __MODULE_STRING(WD_TIMO) ".");
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/wdt.c b/drivers/char/watchdog/wdt.c
index 1210ca0c425..ec7e401228e 100644
--- a/drivers/char/watchdog/wdt.c
+++ b/drivers/char/watchdog/wdt.c
@@ -63,12 +63,7 @@ static int wd_heartbeat;
 module_param(heartbeat, int, 0);
 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (0<heartbeat<65536, default=" __MODULE_STRING(WD_TIMO) ")");
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/wdt977.c b/drivers/char/watchdog/wdt977.c
index 072e9b21475..44d49dfacbb 100644
--- a/drivers/char/watchdog/wdt977.c
+++ b/drivers/char/watchdog/wdt977.c
@@ -53,12 +53,7 @@ MODULE_PARM_DESC(timeout,"Watchdog timeout in seconds (60..15300), default=" __M
 module_param(testmode, int, 0);
 MODULE_PARM_DESC(testmode,"Watchdog testmode (1 = no reboot), default=0");
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/char/watchdog/wdt_pci.c b/drivers/char/watchdog/wdt_pci.c
index c80cb77b92f..4b3311993d4 100644
--- a/drivers/char/watchdog/wdt_pci.c
+++ b/drivers/char/watchdog/wdt_pci.c
@@ -89,12 +89,7 @@ static int wd_heartbeat;
 module_param(heartbeat, int, 0);
 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (0<heartbeat<65536, default=" __MODULE_STRING(WD_TIMO) ")");
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int nowayout = 1;
-#else
-static int nowayout = 0;
-#endif
-
+static int nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
 
diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
index 7a7859dd0d9..10b01498238 100644
--- a/drivers/cpufreq/cpufreq.c
+++ b/drivers/cpufreq/cpufreq.c
@@ -1130,7 +1130,7 @@ int cpufreq_driver_target(struct cpufreq_policy *policy,
 			  unsigned int target_freq,
 			  unsigned int relation)
 {
-	unsigned int ret;
+	int ret;
 
 	policy = cpufreq_cpu_get(policy->cpu);
 	if (!policy)
@@ -1151,7 +1151,7 @@ EXPORT_SYMBOL_GPL(cpufreq_driver_target);
 
 static int __cpufreq_governor(struct cpufreq_policy *policy, unsigned int event)
 {
-	int ret = -EINVAL;
+	int ret;
 
 	if (!try_module_get(policy->governor->owner))
 		return -EINVAL;
diff --git a/drivers/fc4/fc.c b/drivers/fc4/fc.c
index 5d961f5e0ca..e4710d1d1f9 100644
--- a/drivers/fc4/fc.c
+++ b/drivers/fc4/fc.c
@@ -1004,8 +1004,8 @@ int fcp_scsi_dev_reset(Scsi_Cmnd *SCpnt)
 		return FAILED;
 	}
 	fc->rst_pkt->eh_state = SCSI_STATE_UNUSED;
-	return SUCCESS;
 #endif
+	return SUCCESS;
 }
 
 static int __fcp_scsi_host_reset(Scsi_Cmnd *SCpnt)
diff --git a/drivers/firmware/pcdp.c b/drivers/firmware/pcdp.c
index 53c95c0bbf4..ae1fb45dbb4 100644
--- a/drivers/firmware/pcdp.c
+++ b/drivers/firmware/pcdp.c
@@ -25,14 +25,22 @@ setup_serial_console(struct pcdp_uart *uart)
 #ifdef CONFIG_SERIAL_8250_CONSOLE
 	int mmio;
 	static char options[64], *p = options;
+	char parity;
 
 	mmio = (uart->addr.address_space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY);
 	p += sprintf(p, "console=uart,%s,0x%lx",
 		mmio ? "mmio" : "io", uart->addr.address);
-	if (uart->baud)
+	if (uart->baud) {
 		p += sprintf(p, ",%lu", uart->baud);
-	if (uart->bits)
-		p += sprintf(p, "n%d", uart->bits);
+		if (uart->bits) {
+			switch (uart->parity) {
+			    case 0x2: parity = 'e'; break;
+			    case 0x3: parity = 'o'; break;
+			    default:  parity = 'n';
+			}
+			p += sprintf(p, "%c%d", parity, uart->bits);
+		}
+	}
 
 	return early_serial_console_init(options);
 #else
diff --git a/drivers/hwmon/adm1026.c b/drivers/hwmon/adm1026.c
index 3c85fe150cd..4fa17c76eea 100644
--- a/drivers/hwmon/adm1026.c
+++ b/drivers/hwmon/adm1026.c
@@ -393,7 +393,7 @@ void adm1026_init_client(struct i2c_client *client)
 
 	value = data->config3;
 	if (data->config3 & CFG3_GPIO16_ENABLE) {
-		dev_dbg(&client->dev, "GPIO16 enabled.  THERM"
+		dev_dbg(&client->dev, "GPIO16 enabled.  THERM "
 			"pin disabled.\n");
 	} else {
 		dev_dbg(&client->dev, "THERM pin enabled.  "
diff --git a/drivers/hwmon/atxp1.c b/drivers/hwmon/atxp1.c
index 0bcf82b4c07..fca3fc1cef7 100644
--- a/drivers/hwmon/atxp1.c
+++ b/drivers/hwmon/atxp1.c
@@ -21,6 +21,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/module.h>
+#include <linux/jiffies.h>
 #include <linux/i2c.h>
 #include <linux/i2c-sensor.h>
 #include <linux/i2c-vid.h>
@@ -80,9 +81,7 @@ static struct atxp1_data * atxp1_update_device(struct device *dev)
 
 	down(&data->update_lock);
 
-	if ((jiffies - data->last_updated > HZ) ||
-	    (jiffies < data->last_updated) ||
-	    !data->valid) {
+	if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
 
 		/* Update local register data */
 		data->reg.vid = i2c_smbus_read_byte_data(client, ATXP1_VID);
diff --git a/drivers/hwmon/fscpos.c b/drivers/hwmon/fscpos.c
index 3beaa6191ef..270015b626a 100644
--- a/drivers/hwmon/fscpos.c
+++ b/drivers/hwmon/fscpos.c
@@ -32,6 +32,7 @@
 
 #include <linux/module.h>
 #include <linux/slab.h>
+#include <linux/jiffies.h>
 #include <linux/i2c.h>
 #include <linux/i2c-sensor.h>
 #include <linux/init.h>
@@ -572,8 +573,7 @@ static struct fscpos_data *fscpos_update_device(struct device *dev)
 
 	down(&data->update_lock);
 
-	if ((jiffies - data->last_updated > 2 * HZ) ||
-			(jiffies < data->last_updated) || !data->valid) {
+	if (time_after(jiffies, data->last_updated + 2 * HZ) || !data->valid) {
 		int i;
 
 		dev_dbg(&client->dev, "Starting fscpos update\n");
diff --git a/drivers/hwmon/gl520sm.c b/drivers/hwmon/gl520sm.c
index a13a504f5bf..80ae8d30c2a 100644
--- a/drivers/hwmon/gl520sm.c
+++ b/drivers/hwmon/gl520sm.c
@@ -24,6 +24,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/slab.h>
+#include <linux/jiffies.h>
 #include <linux/i2c.h>
 #include <linux/i2c-sensor.h>
 #include <linux/i2c-vid.h>
@@ -678,8 +679,7 @@ static struct gl520_data *gl520_update_device(struct device *dev)
 
 	down(&data->update_lock);
 
-	if ((jiffies - data->last_updated > 2 * HZ) ||
-	    (jiffies < data->last_updated) || !data->valid) {
+	if (time_after(jiffies, data->last_updated + 2 * HZ) || !data->valid) {
 
 		dev_dbg(&client->dev, "Starting gl520sm update\n");
 
diff --git a/drivers/hwmon/max1619.c b/drivers/hwmon/max1619.c
index bf553dcd97d..3c159f1d49e 100644
--- a/drivers/hwmon/max1619.c
+++ b/drivers/hwmon/max1619.c
@@ -363,7 +363,7 @@ static void __exit sensors_max1619_exit(void)
 	i2c_del_driver(&max1619_driver);
 }
 
-MODULE_AUTHOR("Alexey Fisher <fishor@mail.ru> and"
+MODULE_AUTHOR("Alexey Fisher <fishor@mail.ru> and "
 	"Jean Delvare <khali@linux-fr.org>");
 MODULE_DESCRIPTION("MAX1619 sensor driver");
 MODULE_LICENSE("GPL");
diff --git a/drivers/hwmon/pc87360.c b/drivers/hwmon/pc87360.c
index 876c68f3af3..fa4032d53b7 100644
--- a/drivers/hwmon/pc87360.c
+++ b/drivers/hwmon/pc87360.c
@@ -1043,7 +1043,7 @@ static void pc87360_init_client(struct i2c_client *client, int use_thermistors)
 	if (init >= 2 && data->innr) {
 		reg = pc87360_read_value(data, LD_IN, NO_BANK,
 					 PC87365_REG_IN_CONVRATE);
-		dev_info(&client->dev, "VLM conversion set to"
+		dev_info(&client->dev, "VLM conversion set to "
 			 "1s period, 160us delay\n");
 		pc87360_write_value(data, LD_IN, NO_BANK,
 				    PC87365_REG_IN_CONVRATE,
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index 0ab7e37f5b0..1ab41313ce5 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -137,7 +137,7 @@ static int i801_setup(struct pci_dev *dev)
 		pci_read_config_word(I801_dev, SMBBA, &i801_smba);
 		i801_smba &= 0xfff0;
 		if(i801_smba == 0) {
-			dev_err(&dev->dev, "SMB base address uninitialized"
+			dev_err(&dev->dev, "SMB base address uninitialized "
 				"- upgrade BIOS or use force_addr=0xaddr\n");
 			return -ENODEV;
 		}
@@ -186,7 +186,7 @@ static int i801_transaction(void)
 	int result = 0;
 	int timeout = 0;
 
-	dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x,"
+	dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
 		"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
 		inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
 		inb_p(SMBHSTDAT1));
@@ -240,7 +240,7 @@ static int i801_transaction(void)
 		outb_p(inb(SMBHSTSTS), SMBHSTSTS);
 
 	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
-		dev_dbg(&I801_dev->dev, "Failed reset at end of transaction"
+		dev_dbg(&I801_dev->dev, "Failed reset at end of transaction "
 			"(%02x)\n", temp);
 	}
 	dev_dbg(&I801_dev->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index 03c23ce98ed..9ad3e9262e8 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -288,6 +288,100 @@ static struct i2c_adapter mpc_ops = {
 	.retries = 1
 };
 
+static int fsl_i2c_probe(struct device *device)
+{
+	int result = 0;
+	struct mpc_i2c *i2c;
+	struct platform_device *pdev = to_platform_device(device);
+	struct fsl_i2c_platform_data *pdata;
+	struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	pdata = (struct fsl_i2c_platform_data *) pdev->dev.platform_data;
+
+	if (!(i2c = kmalloc(sizeof(*i2c), GFP_KERNEL))) {
+		return -ENOMEM;
+	}
+	memset(i2c, 0, sizeof(*i2c));
+
+	i2c->irq = platform_get_irq(pdev, 0);
+	i2c->flags = pdata->device_flags;
+	init_waitqueue_head(&i2c->queue);
+
+	i2c->base = ioremap((phys_addr_t)r->start, MPC_I2C_REGION);
+
+	if (!i2c->base) {
+		printk(KERN_ERR "i2c-mpc - failed to map controller\n");
+		result = -ENOMEM;
+		goto fail_map;
+	}
+
+	if (i2c->irq != 0)
+		if ((result = request_irq(i2c->irq, mpc_i2c_isr,
+					  SA_SHIRQ, "i2c-mpc", i2c)) < 0) {
+			printk(KERN_ERR
+			       "i2c-mpc - failed to attach interrupt\n");
+			goto fail_irq;
+		}
+
+	mpc_i2c_setclock(i2c);
+	dev_set_drvdata(device, i2c);
+
+	i2c->adap = mpc_ops;
+	i2c_set_adapdata(&i2c->adap, i2c);
+	i2c->adap.dev.parent = &pdev->dev;
+	if ((result = i2c_add_adapter(&i2c->adap)) < 0) {
+		printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
+		goto fail_add;
+	}
+
+	return result;
+
+      fail_add:
+	if (i2c->irq != 0)
+		free_irq(i2c->irq, NULL);
+      fail_irq:
+	iounmap(i2c->base);
+      fail_map:
+	kfree(i2c);
+	return result;
+};
+
+static int fsl_i2c_remove(struct device *device)
+{
+	struct mpc_i2c *i2c = dev_get_drvdata(device);
+
+	i2c_del_adapter(&i2c->adap);
+	dev_set_drvdata(device, NULL);
+
+	if (i2c->irq != 0)
+		free_irq(i2c->irq, i2c);
+
+	iounmap(i2c->base);
+	kfree(i2c);
+	return 0;
+};
+
+/* Structure for a device driver */
+static struct device_driver fsl_i2c_driver = {
+	.name = "fsl-i2c",
+	.bus = &platform_bus_type,
+	.probe = fsl_i2c_probe,
+	.remove = fsl_i2c_remove,
+};
+
+static int __init fsl_i2c_init(void)
+{
+	return driver_register(&fsl_i2c_driver);
+}
+
+static void __exit fsl_i2c_exit(void)
+{
+	driver_unregister(&fsl_i2c_driver);
+}
+
+module_init(fsl_i2c_init);
+module_exit(fsl_i2c_exit);
+
 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
 MODULE_DESCRIPTION
     ("I2C-Bus adapter for MPC107 bridge and MPC824x/85xx/52xx processors");
diff --git a/drivers/i2c/chips/ds1337.c b/drivers/i2c/chips/ds1337.c
index 74ece8ac1c2..82cf959989f 100644
--- a/drivers/i2c/chips/ds1337.c
+++ b/drivers/i2c/chips/ds1337.c
@@ -165,7 +165,7 @@ static int ds1337_set_datetime(struct i2c_client *client, struct rtc_time *dt)
 	buf[0] = 0;		/* reg offset */
 	buf[1] = BIN2BCD(dt->tm_sec);
 	buf[2] = BIN2BCD(dt->tm_min);
-	buf[3] = BIN2BCD(dt->tm_hour) | (1 << 6);
+	buf[3] = BIN2BCD(dt->tm_hour);
 	buf[4] = BIN2BCD(dt->tm_wday) + 1;
 	buf[5] = BIN2BCD(dt->tm_mday);
 	buf[6] = BIN2BCD(dt->tm_mon) + 1;
@@ -344,9 +344,9 @@ static void ds1337_init_client(struct i2c_client *client)
 
 	/* Ensure that device is set in 24-hour mode */
 	val = i2c_smbus_read_byte_data(client, DS1337_REG_HOUR);
-	if ((val >= 0) && (val & (1 << 6)) == 0)
+	if ((val >= 0) && (val & (1 << 6)))
 		i2c_smbus_write_byte_data(client, DS1337_REG_HOUR,
-					  val | (1 << 6));
+					  val & 0x3f);
 }
 
 static int ds1337_detach_client(struct i2c_client *client)
diff --git a/drivers/i2c/chips/eeprom.c b/drivers/i2c/chips/eeprom.c
index 6ea413f6d5e..a2da31b0dd7 100644
--- a/drivers/i2c/chips/eeprom.c
+++ b/drivers/i2c/chips/eeprom.c
@@ -163,6 +163,11 @@ int eeprom_detect(struct i2c_adapter *adapter, int address, int kind)
 	struct eeprom_data *data;
 	int err = 0;
 
+	/* prevent 24RF08 corruption */
+	if (kind < 0)
+		i2c_smbus_xfer(adapter, address, 0, 0, 0,
+			       I2C_SMBUS_QUICK, NULL);
+
 	/* There are three ways we can read the EEPROM data:
 	   (1) I2C block reads (faster, but unsupported by most adapters)
 	   (2) Consecutive byte reads (100% overhead)
@@ -187,9 +192,6 @@ int eeprom_detect(struct i2c_adapter *adapter, int address, int kind)
 	new_client->driver = &eeprom_driver;
 	new_client->flags = 0;
 
-	/* prevent 24RF08 corruption */
-	i2c_smbus_write_quick(new_client, 0);
-
 	/* Fill in the remaining client fields */
 	strlcpy(new_client->name, "eeprom", I2C_NAME_SIZE);
 	data->valid = 0;
diff --git a/drivers/i2c/chips/max6875.c b/drivers/i2c/chips/max6875.c
index c4f14d9623c..0230375f72e 100644
--- a/drivers/i2c/chips/max6875.c
+++ b/drivers/i2c/chips/max6875.c
@@ -343,6 +343,11 @@ static int max6875_detect(struct i2c_adapter *adapter, int address, int kind)
 	struct max6875_data *data;
 	int err = 0;
 
+	/* Prevent 24RF08 corruption (in case of user error) */
+	if (kind < 0)
+		i2c_smbus_xfer(adapter, address, 0, 0, 0,
+			       I2C_SMBUS_QUICK, NULL);
+
 	/* There are three ways we can read the EEPROM data:
 	   (1) I2C block reads (faster, but unsupported by most adapters)
 	   (2) Consecutive byte reads (100% overhead)
@@ -370,9 +375,6 @@ static int max6875_detect(struct i2c_adapter *adapter, int address, int kind)
 	new_client->driver = &max6875_driver;
 	new_client->flags = 0;
 
-	/* Prevent 24RF08 corruption */
-	i2c_smbus_write_quick(new_client, 0);
-
 	/* Setup the user section */
 	data->blocks[max6875_eeprom_user].type    = max6875_eeprom_user;
 	data->blocks[max6875_eeprom_user].slices  = USER_EEPROM_SLICES;
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index 4fd4f52c8e9..4a9ead27759 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -231,8 +231,8 @@ int i2c_del_adapter(struct i2c_adapter *adap)
 		if (driver->detach_adapter)
 			if ((res = driver->detach_adapter(adap))) {
 				dev_warn(&adap->dev, "can't detach adapter "
-					 "while detaching driver %s: driver not "
-					 "detached!", driver->name);
+					 "while detaching driver %s: driver "
+					 "not detached!\n", driver->name);
 				goto out_unlock;
 			}
 	}
@@ -456,8 +456,8 @@ int i2c_detach_client(struct i2c_client *client)
 		res = adapter->client_unregister(client);
 		if (res) {
 			dev_err(&client->dev,
-			       "client_unregister [%s] failed, "
-			       "client not detached", client->name);
+				"client_unregister [%s] failed, "
+				"client not detached\n", client->name);
 			goto out;
 		}
 	}
diff --git a/drivers/ide/cris/Makefile b/drivers/ide/cris/Makefile
index fdc294325d0..6176e8d6b2e 100644
--- a/drivers/ide/cris/Makefile
+++ b/drivers/ide/cris/Makefile
@@ -1,3 +1,3 @@
 EXTRA_CFLAGS				+= -Idrivers/ide
 
-obj-$(CONFIG_ETRAX_ARCH_V10)		+= ide-v10.o
+obj-y					+= ide-cris.o
diff --git a/drivers/ide/cris/ide-cris.c b/drivers/ide/cris/ide-cris.c
new file mode 100644
index 00000000000..cd15e626051
--- /dev/null
+++ b/drivers/ide/cris/ide-cris.c
@@ -0,0 +1,1107 @@
+/* $Id: cris-ide-driver.patch,v 1.1 2005/06/29 21:39:07 akpm Exp $
+ *
+ * Etrax specific IDE functions, like init and PIO-mode setting etc.
+ * Almost the entire ide.c is used for the rest of the Etrax ATA driver.
+ * Copyright (c) 2000-2005 Axis Communications AB
+ *
+ * Authors:    Bjorn Wesen        (initial version)
+ *             Mikael Starvik     (crisv32 port)
+ */
+
+/* Regarding DMA:
+ *
+ * There are two forms of DMA - "DMA handshaking" between the interface and the drive,
+ * and DMA between the memory and the interface. We can ALWAYS use the latter, since it's
+ * something built-in in the Etrax. However only some drives support the DMA-mode handshaking
+ * on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the
+ * device can't do DMA handshaking for some stupid reason. We don't need to do that.
+ */
+
+#undef REALLY_SLOW_IO           /* most systems can safely undef this */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/timer.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/blkdev.h>
+#include <linux/hdreg.h>
+#include <linux/ide.h>
+#include <linux/init.h>
+
+#include <asm/io.h>
+#include <asm/dma.h>
+
+/* number of DMA descriptors */
+#define MAX_DMA_DESCRS 64
+
+/* number of times to retry busy-flags when reading/writing IDE-registers
+ * this can't be too high because a hung harddisk might cause the watchdog
+ * to trigger (sometimes INB and OUTB are called with irq's disabled)
+ */
+
+#define IDE_REGISTER_TIMEOUT 300
+
+#define LOWDB(x)
+#define D(x)
+
+enum /* Transfer types */
+{
+	TYPE_PIO,
+	TYPE_DMA,
+	TYPE_UDMA
+};
+
+/* CRISv32 specifics */
+#ifdef CONFIG_ETRAX_ARCH_V32
+#include <asm/arch/hwregs/ata_defs.h>
+#include <asm/arch/hwregs/dma_defs.h>
+#include <asm/arch/hwregs/dma.h>
+#include <asm/arch/pinmux.h>
+
+#define ATA_UDMA2_CYC    2
+#define ATA_UDMA2_DVS    3
+#define ATA_UDMA1_CYC    2
+#define ATA_UDMA1_DVS    4
+#define ATA_UDMA0_CYC    4
+#define ATA_UDMA0_DVS    6
+#define ATA_DMA2_STROBE  7
+#define ATA_DMA2_HOLD    1
+#define ATA_DMA1_STROBE  8
+#define ATA_DMA1_HOLD    3
+#define ATA_DMA0_STROBE 25
+#define ATA_DMA0_HOLD   19
+#define ATA_PIO4_SETUP   3
+#define ATA_PIO4_STROBE  7
+#define ATA_PIO4_HOLD    1
+#define ATA_PIO3_SETUP   3
+#define ATA_PIO3_STROBE  9
+#define ATA_PIO3_HOLD    3
+#define ATA_PIO2_SETUP   3
+#define ATA_PIO2_STROBE 13
+#define ATA_PIO2_HOLD    5
+#define ATA_PIO1_SETUP   5
+#define ATA_PIO1_STROBE 23
+#define ATA_PIO1_HOLD    9
+#define ATA_PIO0_SETUP   9
+#define ATA_PIO0_STROBE 39
+#define ATA_PIO0_HOLD    9
+
+int
+cris_ide_ack_intr(ide_hwif_t* hwif)
+{
+	reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2,
+	                         int, hwif->io_ports[0]);
+	REG_WR_INT(ata, regi_ata, rw_ack_intr, 1 << ctrl2.sel);
+	return 1;
+}
+
+static inline int
+cris_ide_busy(void)
+{
+	reg_ata_rs_stat_data stat_data;
+	stat_data = REG_RD(ata, regi_ata, rs_stat_data);
+	return stat_data.busy;
+}
+
+static inline int
+cris_ide_ready(void)
+{
+	return !cris_ide_busy();
+}
+
+static inline int
+cris_ide_data_available(unsigned short* data)
+{
+	reg_ata_rs_stat_data stat_data;
+	stat_data = REG_RD(ata, regi_ata, rs_stat_data);
+	*data = stat_data.data;
+	return stat_data.dav;
+}
+
+static void
+cris_ide_write_command(unsigned long command)
+{
+	REG_WR_INT(ata, regi_ata, rw_ctrl2, command); /* write data to the drive's register */
+}
+
+static void
+cris_ide_set_speed(int type, int setup, int strobe, int hold)
+{
+	reg_ata_rw_ctrl0 ctrl0 = REG_RD(ata, regi_ata, rw_ctrl0);
+	reg_ata_rw_ctrl1 ctrl1 = REG_RD(ata, regi_ata, rw_ctrl1);
+
+	if (type == TYPE_PIO) {
+		ctrl0.pio_setup = setup;
+		ctrl0.pio_strb = strobe;
+		ctrl0.pio_hold = hold;
+	} else if (type == TYPE_DMA) {
+		ctrl0.dma_strb = strobe;
+		ctrl0.dma_hold = hold;
+	} else if (type == TYPE_UDMA) {
+		ctrl1.udma_tcyc = setup;
+		ctrl1.udma_tdvs = strobe;
+	}
+	REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
+	REG_WR(ata, regi_ata, rw_ctrl1, ctrl1);
+}
+
+static unsigned long
+cris_ide_base_address(int bus)
+{
+	reg_ata_rw_ctrl2 ctrl2 = {0};
+	ctrl2.sel = bus;
+	return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2);
+}
+
+static unsigned long
+cris_ide_reg_addr(unsigned long addr, int cs0, int cs1)
+{
+	reg_ata_rw_ctrl2 ctrl2 = {0};
+	ctrl2.addr = addr;
+	ctrl2.cs1 = cs1;
+	ctrl2.cs0 = cs0;
+	return REG_TYPE_CONV(int, reg_ata_rw_ctrl2, ctrl2);
+}
+
+static __init void
+cris_ide_reset(unsigned val)
+{
+	reg_ata_rw_ctrl0 ctrl0 = {0};
+	ctrl0.rst = val ? regk_ata_active : regk_ata_inactive;
+	REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
+}
+
+static __init void
+cris_ide_init(void)
+{
+	reg_ata_rw_ctrl0 ctrl0 = {0};
+	reg_ata_rw_intr_mask intr_mask = {0};
+
+	ctrl0.en = regk_ata_yes;
+	REG_WR(ata, regi_ata, rw_ctrl0, ctrl0);
+
+	intr_mask.bus0 = regk_ata_yes;
+	intr_mask.bus1 = regk_ata_yes;
+	intr_mask.bus2 = regk_ata_yes;
+	intr_mask.bus3 = regk_ata_yes;
+
+	REG_WR(ata, regi_ata, rw_intr_mask, intr_mask);
+
+	crisv32_request_dma(2, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata);
+	crisv32_request_dma(3, "ETRAX FS built-in ATA", DMA_VERBOSE_ON_ERROR, 0, dma_ata);
+
+	crisv32_pinmux_alloc_fixed(pinmux_ata);
+	crisv32_pinmux_alloc_fixed(pinmux_ata0);
+	crisv32_pinmux_alloc_fixed(pinmux_ata1);
+	crisv32_pinmux_alloc_fixed(pinmux_ata2);
+	crisv32_pinmux_alloc_fixed(pinmux_ata3);
+
+	DMA_RESET(regi_dma2);
+	DMA_ENABLE(regi_dma2);
+	DMA_RESET(regi_dma3);
+	DMA_ENABLE(regi_dma3);
+
+	DMA_WR_CMD (regi_dma2, regk_dma_set_w_size2);
+	DMA_WR_CMD (regi_dma3, regk_dma_set_w_size2);
+}
+
+static dma_descr_context mycontext __attribute__ ((__aligned__(32)));
+
+#define cris_dma_descr_type dma_descr_data
+#define cris_pio_read regk_ata_rd
+#define cris_ultra_mask 0x7
+#define MAX_DESCR_SIZE 0xffffffffUL
+
+static unsigned long
+cris_ide_get_reg(unsigned long reg)
+{
+	return (reg & 0x0e000000) >> 25;
+}
+
+static void
+cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last)
+{
+	d->buf = (char*)virt_to_phys(buf);
+	d->after = d->buf + len;
+	d->eol = last;
+}
+
+static void
+cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir,int type,int len)
+{
+	reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG);
+	reg_ata_rw_trf_cnt trf_cnt = {0};
+
+	mycontext.saved_data = (dma_descr_data*)virt_to_phys(d);
+	mycontext.saved_data_buf = d->buf;
+	/* start the dma channel */
+	DMA_START_CONTEXT(dir ? regi_dma3 : regi_dma2, virt_to_phys(&mycontext));
+
+	/* initiate a multi word dma read using PIO handshaking */
+	trf_cnt.cnt = len >> 1;
+	/* Due to a "feature" the transfer count has to be one extra word for UDMA. */
+	if (type == TYPE_UDMA)
+		trf_cnt.cnt++;
+	REG_WR(ata, regi_ata, rw_trf_cnt, trf_cnt);
+
+	ctrl2.rw = dir ? regk_ata_rd : regk_ata_wr;
+	ctrl2.trf_mode = regk_ata_dma;
+	ctrl2.hsh = type == TYPE_PIO ? regk_ata_pio :
+	            type == TYPE_DMA ? regk_ata_dma : regk_ata_udma;
+	ctrl2.multi = regk_ata_yes;
+	ctrl2.dma_size = regk_ata_word;
+	REG_WR(ata, regi_ata, rw_ctrl2, ctrl2);
+}
+
+static void
+cris_ide_wait_dma(int dir)
+{
+	reg_dma_rw_stat status;
+	do
+	{
+		status = REG_RD(dma, dir ? regi_dma3 : regi_dma2, rw_stat);
+	} while(status.list_state != regk_dma_data_at_eol);
+}
+
+static int cris_dma_test_irq(ide_drive_t *drive)
+{
+	int intr = REG_RD_INT(ata, regi_ata, r_intr);
+	reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, IDE_DATA_REG);
+	return intr & (1 << ctrl2.sel) ? 1 : 0;
+}
+
+static void cris_ide_initialize_dma(int dir)
+{
+}
+
+#else
+/* CRISv10 specifics */
+#include <asm/arch/svinto.h>
+#include <asm/arch/io_interface_mux.h>
+
+/* PIO timing (in R_ATA_CONFIG)
+ *
+ *                        _____________________________
+ * ADDRESS :     ________/
+ *
+ *                            _______________
+ * DIOR    :     ____________/               \__________
+ *
+ *                               _______________
+ * DATA    :     XXXXXXXXXXXXXXXX_______________XXXXXXXX
+ *
+ *
+ * DIOR is unbuffered while address and data is buffered.
+ * This creates two problems:
+ * 1. The DIOR pulse is to early (because it is unbuffered)
+ * 2. The rise time of DIOR is long
+ *
+ * There are at least three different plausible solutions
+ * 1. Use a pad capable of larger currents in Etrax
+ * 2. Use an external buffer
+ * 3. Make the strobe pulse longer
+ *
+ * Some of the strobe timings below are modified to compensate
+ * for this. This implies a slight performance decrease.
+ *
+ * THIS SHOULD NEVER BE CHANGED!
+ *
+ * TODO: Is this true for the latest LX boards still ?
+ */
+
+#define ATA_UDMA2_CYC    0 /* No UDMA supported, just to make it compile. */
+#define ATA_UDMA2_DVS    0
+#define ATA_UDMA1_CYC    0
+#define ATA_UDMA1_DVS    0
+#define ATA_UDMA0_CYC    0
+#define ATA_UDMA0_DVS    0
+#define ATA_DMA2_STROBE  4
+#define ATA_DMA2_HOLD    0
+#define ATA_DMA1_STROBE  4
+#define ATA_DMA1_HOLD    1
+#define ATA_DMA0_STROBE 12
+#define ATA_DMA0_HOLD    9
+#define ATA_PIO4_SETUP   1
+#define ATA_PIO4_STROBE  5
+#define ATA_PIO4_HOLD    0
+#define ATA_PIO3_SETUP   1
+#define ATA_PIO3_STROBE  5
+#define ATA_PIO3_HOLD    1
+#define ATA_PIO2_SETUP   1
+#define ATA_PIO2_STROBE  6
+#define ATA_PIO2_HOLD    2
+#define ATA_PIO1_SETUP   2
+#define ATA_PIO1_STROBE 11
+#define ATA_PIO1_HOLD    4
+#define ATA_PIO0_SETUP   4
+#define ATA_PIO0_STROBE 19
+#define ATA_PIO0_HOLD    4
+
+int
+cris_ide_ack_intr(ide_hwif_t* hwif)
+{
+	return 1;
+}
+
+static inline int
+cris_ide_busy(void)
+{
+	return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy) ;
+}
+
+static inline int
+cris_ide_ready(void)
+{
+	return *R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, tr_rdy) ;
+}
+
+static inline int
+cris_ide_data_available(unsigned short* data)
+{
+	unsigned long status = *R_ATA_STATUS_DATA;
+	*data = (unsigned short)status;
+	return status & IO_MASK(R_ATA_STATUS_DATA, dav);
+}
+
+static void
+cris_ide_write_command(unsigned long command)
+{
+	*R_ATA_CTRL_DATA = command;
+}
+
+static void
+cris_ide_set_speed(int type, int setup, int strobe, int hold)
+{
+	static int pio_setup = ATA_PIO4_SETUP;
+	static int pio_strobe = ATA_PIO4_STROBE;
+	static int pio_hold = ATA_PIO4_HOLD;
+	static int dma_strobe = ATA_DMA2_STROBE;
+	static int dma_hold = ATA_DMA2_HOLD;
+
+	if (type == TYPE_PIO) {
+		pio_setup = setup;
+		pio_strobe = strobe;
+		pio_hold = hold;
+	} else if (type == TYPE_DMA) {
+		dma_strobe = strobe;
+	  dma_hold = hold;
+	}
+	*R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ) |
+	  IO_FIELD( R_ATA_CONFIG, dma_strobe, dma_strobe ) |
+		IO_FIELD( R_ATA_CONFIG, dma_hold,   dma_hold ) |
+		IO_FIELD( R_ATA_CONFIG, pio_setup,  pio_setup ) |
+		IO_FIELD( R_ATA_CONFIG, pio_strobe, pio_strobe ) |
+		IO_FIELD( R_ATA_CONFIG, pio_hold,   pio_hold ) );
+}
+
+static unsigned long
+cris_ide_base_address(int bus)
+{
+	return IO_FIELD(R_ATA_CTRL_DATA, sel, bus);
+}
+
+static unsigned long
+cris_ide_reg_addr(unsigned long addr, int cs0, int cs1)
+{
+	return IO_FIELD(R_ATA_CTRL_DATA, addr, addr) |
+	       IO_FIELD(R_ATA_CTRL_DATA, cs0, cs0) |
+	       IO_FIELD(R_ATA_CTRL_DATA, cs1, cs1);
+}
+
+static __init void
+cris_ide_reset(unsigned val)
+{
+#ifdef CONFIG_ETRAX_IDE_G27_RESET
+	REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, val);
+#endif
+#ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET
+	REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, val);
+#endif
+#ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET
+	REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, val);
+#endif
+#ifdef CONFIG_ETRAX_IDE_PB7_RESET
+	port_pb_dir_shadow = port_pb_dir_shadow |
+		IO_STATE(R_PORT_PB_DIR, dir7, output);
+	*R_PORT_PB_DIR = port_pb_dir_shadow;
+	REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, val);
+#endif
+}
+
+static __init void
+cris_ide_init(void)
+{
+	volatile unsigned int dummy;
+
+	*R_ATA_CTRL_DATA = 0;
+	*R_ATA_TRANSFER_CNT = 0;
+	*R_ATA_CONFIG = 0;
+
+	if (cris_request_io_interface(if_ata, "ETRAX100LX IDE")) {
+		printk(KERN_CRIT "ide: Failed to get IO interface\n");
+		return;
+	} else if (cris_request_dma(ATA_TX_DMA_NBR,
+		                          "ETRAX100LX IDE TX",
+		                          DMA_VERBOSE_ON_ERROR,
+		                          dma_ata)) {
+		cris_free_io_interface(if_ata);
+		printk(KERN_CRIT "ide: Failed to get Tx DMA channel\n");
+		return;
+	} else if (cris_request_dma(ATA_RX_DMA_NBR,
+		                          "ETRAX100LX IDE RX",
+		                          DMA_VERBOSE_ON_ERROR,
+		                          dma_ata)) {
+		cris_free_dma(ATA_TX_DMA_NBR, "ETRAX100LX IDE Tx");
+		cris_free_io_interface(if_ata);
+		printk(KERN_CRIT "ide: Failed to get Rx DMA channel\n");
+		return;
+	}
+
+	/* make a dummy read to set the ata controller in a proper state */
+	dummy = *R_ATA_STATUS_DATA;
+
+	*R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable, 1 ));
+	*R_ATA_CTRL_DATA = ( IO_STATE( R_ATA_CTRL_DATA, rw,   read) |
+	                     IO_FIELD( R_ATA_CTRL_DATA, addr, 1   ) );
+
+	while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag*/
+
+	*R_IRQ_MASK0_SET = ( IO_STATE( R_IRQ_MASK0_SET, ata_irq0, set ) |
+	                     IO_STATE( R_IRQ_MASK0_SET, ata_irq1, set ) |
+	                     IO_STATE( R_IRQ_MASK0_SET, ata_irq2, set ) |
+	                     IO_STATE( R_IRQ_MASK0_SET, ata_irq3, set ) );
+
+	/* reset the dma channels we will use */
+
+	RESET_DMA(ATA_TX_DMA_NBR);
+	RESET_DMA(ATA_RX_DMA_NBR);
+	WAIT_DMA(ATA_TX_DMA_NBR);
+	WAIT_DMA(ATA_RX_DMA_NBR);
+}
+
+#define cris_dma_descr_type etrax_dma_descr
+#define cris_pio_read IO_STATE(R_ATA_CTRL_DATA, rw, read)
+#define cris_ultra_mask 0x0
+#define MAX_DESCR_SIZE 0x10000UL
+
+static unsigned long
+cris_ide_get_reg(unsigned long reg)
+{
+	return (reg & 0x0e000000) >> 25;
+}
+
+static void
+cris_ide_fill_descriptor(cris_dma_descr_type *d, void* buf, unsigned int len, int last)
+{
+	d->buf = virt_to_phys(buf);
+	d->sw_len = len == MAX_DESCR_SIZE ? 0 : len;
+	if (last)
+		d->ctrl |= d_eol;
+}
+
+static void cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir, int type, int len)
+{
+	unsigned long cmd;
+
+	if (dir) {
+		/* need to do this before RX DMA due to a chip bug
+		 * it is enough to just flush the part of the cache that
+		 * corresponds to the buffers we start, but since HD transfers
+		 * usually are more than 8 kB, it is easier to optimize for the
+		 * normal case and just flush the entire cache. its the only
+		 * way to be sure! (OB movie quote)
+		 */
+		flush_etrax_cache();
+		*R_DMA_CH3_FIRST = virt_to_phys(d);
+		*R_DMA_CH3_CMD   = IO_STATE(R_DMA_CH3_CMD, cmd, start);
+
+	} else {
+		*R_DMA_CH2_FIRST = virt_to_phys(d);
+		*R_DMA_CH2_CMD   = IO_STATE(R_DMA_CH2_CMD, cmd, start);
+	}
+
+	/* initiate a multi word dma read using DMA handshaking */
+
+	*R_ATA_TRANSFER_CNT =
+		IO_FIELD(R_ATA_TRANSFER_CNT, count, len >> 1);
+
+	cmd = dir ? IO_STATE(R_ATA_CTRL_DATA, rw, read) : IO_STATE(R_ATA_CTRL_DATA, rw, write);
+	cmd |= type == TYPE_PIO ? IO_STATE(R_ATA_CTRL_DATA, handsh, pio) :
+	                          IO_STATE(R_ATA_CTRL_DATA, handsh, dma);
+	*R_ATA_CTRL_DATA =
+		cmd |
+		IO_FIELD(R_ATA_CTRL_DATA, data, IDE_DATA_REG) |
+		IO_STATE(R_ATA_CTRL_DATA, src_dst,  dma)  |
+		IO_STATE(R_ATA_CTRL_DATA, multi,    on)   |
+		IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
+}
+
+static void
+cris_ide_wait_dma(int dir)
+{
+	if (dir)
+		WAIT_DMA(ATA_RX_DMA_NBR);
+	else
+		WAIT_DMA(ATA_TX_DMA_NBR);
+}
+
+static int cris_dma_test_irq(ide_drive_t *drive)
+{
+	int intr = *R_IRQ_MASK0_RD;
+	int bus = IO_EXTRACT(R_ATA_CTRL_DATA, sel, IDE_DATA_REG);
+	return intr & (1 << (bus + IO_BITNR(R_IRQ_MASK0_RD, ata_irq0))) ? 1 : 0;
+}
+
+
+static void cris_ide_initialize_dma(int dir)
+{
+	if (dir)
+	{
+		RESET_DMA(ATA_RX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
+		WAIT_DMA(ATA_RX_DMA_NBR);
+	}
+	else
+	{
+		RESET_DMA(ATA_TX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
+		WAIT_DMA(ATA_TX_DMA_NBR);
+	}
+}
+
+#endif
+
+void
+cris_ide_outw(unsigned short data, unsigned long reg) {
+	int timeleft;
+
+	LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg));
+
+	/* note the lack of handling any timeouts. we stop waiting, but we don't
+	 * really notify anybody.
+	 */
+
+	timeleft = IDE_REGISTER_TIMEOUT;
+	/* wait for busy flag */
+	do {
+		timeleft--;
+	} while(timeleft && cris_ide_busy());
+
+	/*
+	 * Fall through at a timeout, so the ongoing command will be
+	 * aborted by the write below, which is expected to be a dummy
+	 * command to the command register.  This happens when a faulty
+	 * drive times out on a command.  See comment on timeout in
+	 * INB.
+	 */
+	if(!timeleft)
+		printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data);
+
+	cris_ide_write_command(reg|data); /* write data to the drive's register */
+
+	timeleft = IDE_REGISTER_TIMEOUT;
+	/* wait for transmitter ready */
+	do {
+		timeleft--;
+	} while(timeleft && !cris_ide_ready());
+}
+
+void
+cris_ide_outb(unsigned char data, unsigned long reg)
+{
+	cris_ide_outw(data, reg);
+}
+
+void
+cris_ide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port)
+{
+	cris_ide_outw(addr, port);
+}
+
+unsigned short
+cris_ide_inw(unsigned long reg) {
+	int timeleft;
+	unsigned short val;
+
+	timeleft = IDE_REGISTER_TIMEOUT;
+	/* wait for busy flag */
+	do {
+		timeleft--;
+	} while(timeleft && cris_ide_busy());
+
+	if(!timeleft) {
+		/*
+		 * If we're asked to read the status register, like for
+		 * example when a command does not complete for an
+		 * extended time, but the ATA interface is stuck in a
+		 * busy state at the *ETRAX* ATA interface level (as has
+		 * happened repeatedly with at least one bad disk), then
+		 * the best thing to do is to pretend that we read
+		 * "busy" in the status register, so the IDE driver will
+		 * time-out, abort the ongoing command and perform a
+		 * reset sequence.  Note that the subsequent OUT_BYTE
+		 * call will also timeout on busy, but as long as the
+		 * write is still performed, everything will be fine.
+		 */
+		if (cris_ide_get_reg(reg) == IDE_STATUS_OFFSET)
+			return BUSY_STAT;
+		else
+			/* For other rare cases we assume 0 is good enough.  */
+			return 0;
+	}
+
+	cris_ide_write_command(reg | cris_pio_read);
+
+	timeleft = IDE_REGISTER_TIMEOUT;
+	/* wait for available */
+	do {
+		timeleft--;
+	} while(timeleft && !cris_ide_data_available(&val));
+
+	if(!timeleft)
+		return 0;
+
+	LOWDB(printk("inb: 0x%x from reg 0x%x\n", val & 0xff, reg));
+
+	return val;
+}
+
+unsigned char
+cris_ide_inb(unsigned long reg)
+{
+	return (unsigned char)cris_ide_inw(reg);
+}
+
+static int cris_dma_check (ide_drive_t *drive);
+static int cris_dma_end (ide_drive_t *drive);
+static int cris_dma_setup (ide_drive_t *drive);
+static void cris_dma_exec_cmd (ide_drive_t *drive, u8 command);
+static int cris_dma_test_irq(ide_drive_t *drive);
+static void cris_dma_start(ide_drive_t *drive);
+static void cris_ide_input_data (ide_drive_t *drive, void *, unsigned int);
+static void cris_ide_output_data (ide_drive_t *drive, void *, unsigned int);
+static void cris_atapi_input_bytes(ide_drive_t *drive, void *, unsigned int);
+static void cris_atapi_output_bytes(ide_drive_t *drive, void *, unsigned int);
+static int cris_dma_off (ide_drive_t *drive);
+static int cris_dma_on (ide_drive_t *drive);
+
+static void tune_cris_ide(ide_drive_t *drive, u8 pio)
+{
+	int setup, strobe, hold;
+
+	switch(pio)
+	{
+		case 0:
+			setup = ATA_PIO0_SETUP;
+			strobe = ATA_PIO0_STROBE;
+			hold = ATA_PIO0_HOLD;
+			break;
+		case 1:
+			setup = ATA_PIO1_SETUP;
+			strobe = ATA_PIO1_STROBE;
+			hold = ATA_PIO1_HOLD;
+			break;
+		case 2:
+			setup = ATA_PIO2_SETUP;
+			strobe = ATA_PIO2_STROBE;
+			hold = ATA_PIO2_HOLD;
+			break;
+		case 3:
+			setup = ATA_PIO3_SETUP;
+			strobe = ATA_PIO3_STROBE;
+			hold = ATA_PIO3_HOLD;
+			break;
+		case 4:
+			setup = ATA_PIO4_SETUP;
+			strobe = ATA_PIO4_STROBE;
+			hold = ATA_PIO4_HOLD;
+			break;
+		default:
+			return;
+	}
+
+	cris_ide_set_speed(TYPE_PIO, setup, strobe, hold);
+}
+
+static int speed_cris_ide(ide_drive_t *drive, u8 speed)
+{
+	int cyc = 0, dvs = 0, strobe = 0, hold = 0;
+
+	if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) {
+		tune_cris_ide(drive, speed - XFER_PIO_0);
+		return 0;
+	}
+
+	switch(speed)
+	{
+		case XFER_UDMA_0:
+			cyc = ATA_UDMA0_CYC;
+			dvs = ATA_UDMA0_DVS;
+			break;
+		case XFER_UDMA_1:
+			cyc = ATA_UDMA1_CYC;
+			dvs = ATA_UDMA1_DVS;
+			break;
+		case XFER_UDMA_2:
+			cyc = ATA_UDMA2_CYC;
+			dvs = ATA_UDMA2_DVS;
+			break;
+		case XFER_MW_DMA_0:
+			strobe = ATA_DMA0_STROBE;
+			hold = ATA_DMA0_HOLD;
+			break;
+		case XFER_MW_DMA_1:
+			strobe = ATA_DMA1_STROBE;
+			hold = ATA_DMA1_HOLD;
+			break;
+		case XFER_MW_DMA_2:
+			strobe = ATA_DMA2_STROBE;
+			hold = ATA_DMA2_HOLD;
+			break;
+		default:
+			return 0;
+	}
+
+	if (speed >= XFER_UDMA_0)
+		cris_ide_set_speed(TYPE_UDMA, cyc, dvs, 0);
+	else
+		cris_ide_set_speed(TYPE_DMA, 0, strobe, hold);
+
+	return 0;
+}
+
+void __init
+init_e100_ide (void)
+{
+	hw_regs_t hw;
+	int ide_offsets[IDE_NR_PORTS];
+	int h;
+	int i;
+
+	printk("ide: ETRAX FS built-in ATA DMA controller\n");
+
+	for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
+		ide_offsets[i] = cris_ide_reg_addr(i, 0, 1);
+
+	/* the IDE control register is at ATA address 6, with CS1 active instead of CS0 */
+	ide_offsets[IDE_CONTROL_OFFSET] = cris_ide_reg_addr(6, 1, 0);
+
+	/* first fill in some stuff in the ide_hwifs fields */
+
+	for(h = 0; h < MAX_HWIFS; h++) {
+		ide_hwif_t *hwif = &ide_hwifs[h];
+		ide_setup_ports(&hw, cris_ide_base_address(h),
+		                ide_offsets,
+		                0, 0, cris_ide_ack_intr,
+		                ide_default_irq(0));
+		ide_register_hw(&hw, &hwif);
+		hwif->mmio = 2;
+		hwif->chipset = ide_etrax100;
+		hwif->tuneproc = &tune_cris_ide;
+		hwif->speedproc = &speed_cris_ide;
+		hwif->ata_input_data = &cris_ide_input_data;
+		hwif->ata_output_data = &cris_ide_output_data;
+		hwif->atapi_input_bytes = &cris_atapi_input_bytes;
+		hwif->atapi_output_bytes = &cris_atapi_output_bytes;
+		hwif->ide_dma_check = &cris_dma_check;
+		hwif->ide_dma_end = &cris_dma_end;
+		hwif->dma_setup = &cris_dma_setup;
+		hwif->dma_exec_cmd = &cris_dma_exec_cmd;
+		hwif->ide_dma_test_irq = &cris_dma_test_irq;
+		hwif->dma_start = &cris_dma_start;
+		hwif->OUTB = &cris_ide_outb;
+		hwif->OUTW = &cris_ide_outw;
+		hwif->OUTBSYNC = &cris_ide_outbsync;
+		hwif->INB = &cris_ide_inb;
+		hwif->INW = &cris_ide_inw;
+		hwif->ide_dma_host_off = &cris_dma_off;
+		hwif->ide_dma_host_on = &cris_dma_on;
+		hwif->ide_dma_off_quietly = &cris_dma_off;
+		hwif->udma_four = 0;
+		hwif->ultra_mask = cris_ultra_mask;
+		hwif->mwdma_mask = 0x07; /* Multiword DMA 0-2 */
+		hwif->swdma_mask = 0x07; /* Singleword DMA 0-2 */
+	}
+
+	/* Reset pulse */
+	cris_ide_reset(0);
+	udelay(25);
+	cris_ide_reset(1);
+
+	cris_ide_init();
+
+	cris_ide_set_speed(TYPE_PIO, ATA_PIO4_SETUP, ATA_PIO4_STROBE, ATA_PIO4_HOLD);
+	cris_ide_set_speed(TYPE_DMA, 0, ATA_DMA2_STROBE, ATA_DMA2_HOLD);
+	cris_ide_set_speed(TYPE_UDMA, ATA_UDMA2_CYC, ATA_UDMA2_DVS, 0);
+}
+
+static int cris_dma_off (ide_drive_t *drive)
+{
+	return 0;
+}
+
+static int cris_dma_on (ide_drive_t *drive)
+{
+	return 0;
+}
+
+
+static cris_dma_descr_type mydescr __attribute__ ((__aligned__(16)));
+
+/*
+ * The following routines are mainly used by the ATAPI drivers.
+ *
+ * These routines will round up any request for an odd number of bytes,
+ * so if an odd bytecount is specified, be sure that there's at least one
+ * extra byte allocated for the buffer.
+ */
+static void
+cris_atapi_input_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
+{
+	D(printk("atapi_input_bytes, buffer 0x%x, count %d\n",
+	         buffer, bytecount));
+
+	if(bytecount & 1) {
+		printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount);
+		bytecount++; /* to round off */
+	}
+
+	/* setup DMA and start transfer */
+
+	cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1);
+	cris_ide_start_dma(drive, &mydescr, 1, TYPE_PIO, bytecount);
+
+	/* wait for completion */
+	LED_DISK_READ(1);
+	cris_ide_wait_dma(1);
+	LED_DISK_READ(0);
+}
+
+static void
+cris_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
+{
+	D(printk("atapi_output_bytes, buffer 0x%x, count %d\n",
+	         buffer, bytecount));
+
+	if(bytecount & 1) {
+		printk("odd bytecount %d in atapi_out_bytes!\n", bytecount);
+		bytecount++;
+	}
+
+	cris_ide_fill_descriptor(&mydescr, buffer, bytecount, 1);
+	cris_ide_start_dma(drive, &mydescr, 0, TYPE_PIO, bytecount);
+
+	/* wait for completion */
+
+	LED_DISK_WRITE(1);
+	LED_DISK_READ(1);
+	cris_ide_wait_dma(0);
+	LED_DISK_WRITE(0);
+}
+
+/*
+ * This is used for most PIO data transfers *from* the IDE interface
+ */
+static void
+cris_ide_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
+{
+	cris_atapi_input_bytes(drive, buffer, wcount << 2);
+}
+
+/*
+ * This is used for most PIO data transfers *to* the IDE interface
+ */
+static void
+cris_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
+{
+	cris_atapi_output_bytes(drive, buffer, wcount << 2);
+}
+
+/* we only have one DMA channel on the chip for ATA, so we can keep these statically */
+static cris_dma_descr_type ata_descrs[MAX_DMA_DESCRS] __attribute__ ((__aligned__(16)));
+static unsigned int ata_tot_size;
+
+/*
+ * cris_ide_build_dmatable() prepares a dma request.
+ * Returns 0 if all went okay, returns 1 otherwise.
+ */
+static int cris_ide_build_dmatable (ide_drive_t *drive)
+{
+	ide_hwif_t *hwif = drive->hwif;
+	struct scatterlist* sg;
+	struct request *rq  = drive->hwif->hwgroup->rq;
+	unsigned long size, addr;
+	unsigned int count = 0;
+	int i = 0;
+
+	sg = hwif->sg_table;
+
+	ata_tot_size = 0;
+
+	ide_map_sg(drive, rq);
+	i = hwif->sg_nents;
+
+	while(i) {
+		/*
+		 * Determine addr and size of next buffer area.  We assume that
+		 * individual virtual buffers are always composed linearly in
+		 * physical memory.  For example, we assume that any 8kB buffer
+		 * is always composed of two adjacent physical 4kB pages rather
+		 * than two possibly non-adjacent physical 4kB pages.
+		 */
+		/* group sequential buffers into one large buffer */
+		addr = page_to_phys(sg->page) + sg->offset;
+		size = sg_dma_len(sg);
+		while (sg++, --i) {
+			if ((addr + size) != page_to_phys(sg->page) + sg->offset)
+				break;
+			size += sg_dma_len(sg);
+		}
+
+		/* did we run out of descriptors? */
+
+		if(count >= MAX_DMA_DESCRS) {
+			printk("%s: too few DMA descriptors\n", drive->name);
+			return 1;
+		}
+
+		/* however, this case is more difficult - rw_trf_cnt cannot be more
+		   than 65536 words per transfer, so in that case we need to either
+		   1) use a DMA interrupt to re-trigger rw_trf_cnt and continue with
+		      the descriptors, or
+		   2) simply do the request here, and get dma_intr to only ide_end_request on
+		      those blocks that were actually set-up for transfer.
+		*/
+
+		if(ata_tot_size + size > 131072) {
+			printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, (int)size);
+			return 1;
+		}
+
+		/* If size > MAX_DESCR_SIZE it has to be splitted into new descriptors. Since we
+                   don't handle size > 131072 only one split is necessary */
+
+		if(size > MAX_DESCR_SIZE) {
+			cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, MAX_DESCR_SIZE, 0);
+			count++;
+			ata_tot_size += MAX_DESCR_SIZE;
+			size -= MAX_DESCR_SIZE;
+			addr += MAX_DESCR_SIZE;
+		}
+
+		cris_ide_fill_descriptor(&ata_descrs[count], (void*)addr, size,i ? 0 : 1);
+		count++;
+		ata_tot_size += size;
+	}
+
+	if (count) {
+		/* return and say all is ok */
+		return 0;
+	}
+
+	printk("%s: empty DMA table?\n", drive->name);
+	return 1;	/* let the PIO routines handle this weirdness */
+}
+
+static int cris_config_drive_for_dma (ide_drive_t *drive)
+{
+	u8 speed = ide_dma_speed(drive, 1);
+
+	if (!speed)
+		return 0;
+
+	speed_cris_ide(drive, speed);
+	ide_config_drive_speed(drive, speed);
+
+	return ide_dma_enable(drive);
+}
+
+/*
+ * cris_dma_intr() is the handler for disk read/write DMA interrupts
+ */
+static ide_startstop_t cris_dma_intr (ide_drive_t *drive)
+{
+	LED_DISK_READ(0);
+	LED_DISK_WRITE(0);
+
+	return ide_dma_intr(drive);
+}
+
+/*
+ * Functions below initiates/aborts DMA read/write operations on a drive.
+ *
+ * The caller is assumed to have selected the drive and programmed the drive's
+ * sector address using CHS or LBA.  All that remains is to prepare for DMA
+ * and then issue the actual read/write DMA/PIO command to the drive.
+ *
+ * For ATAPI devices, we just prepare for DMA and return. The caller should
+ * then issue the packet command to the drive and call us again with
+ * cris_dma_start afterwards.
+ *
+ * Returns 0 if all went well.
+ * Returns 1 if DMA read/write could not be started, in which case
+ * the caller should revert to PIO for the current request.
+ */
+
+static int cris_dma_check(ide_drive_t *drive)
+{
+	ide_hwif_t *hwif = drive->hwif;
+	struct hd_driveid* id = drive->id;
+
+	if (id && (id->capability & 1)) {
+		if (ide_use_dma(drive)) {
+			if (cris_config_drive_for_dma(drive))
+				return hwif->ide_dma_on(drive);
+		}
+	}
+
+	return hwif->ide_dma_off_quietly(drive);
+}
+
+static int cris_dma_end(ide_drive_t *drive)
+{
+	drive->waiting_for_dma = 0;
+	return 0;
+}
+
+static int cris_dma_setup(ide_drive_t *drive)
+{
+	struct request *rq = drive->hwif->hwgroup->rq;
+
+	cris_ide_initialize_dma(!rq_data_dir(rq));
+	if (cris_ide_build_dmatable (drive)) {
+		ide_map_sg(drive, rq);
+		return 1;
+	}
+
+	drive->waiting_for_dma = 1;
+	return 0;
+}
+
+static void cris_dma_exec_cmd(ide_drive_t *drive, u8 command)
+{
+	/* set the irq handler which will finish the request when DMA is done */
+	ide_set_handler(drive, &cris_dma_intr, WAIT_CMD, NULL);
+
+	/* issue cmd to drive */
+	cris_ide_outb(command, IDE_COMMAND_REG);
+}
+
+static void cris_dma_start(ide_drive_t *drive)
+{
+	struct request *rq = drive->hwif->hwgroup->rq;
+	int writing = rq_data_dir(rq);
+	int type = TYPE_DMA;
+
+	if (drive->current_speed >= XFER_UDMA_0)
+		type = TYPE_UDMA;
+
+	cris_ide_start_dma(drive, &ata_descrs[0], writing ? 0 : 1, type, ata_tot_size);
+
+	if (writing) {
+		LED_DISK_WRITE(1);
+	} else {
+		LED_DISK_READ(1);
+	}
+}
diff --git a/drivers/ide/cris/ide-v10.c b/drivers/ide/cris/ide-v10.c
deleted file mode 100644
index 5b40220d3dd..00000000000
--- a/drivers/ide/cris/ide-v10.c
+++ /dev/null
@@ -1,842 +0,0 @@
-/* $Id: ide.c,v 1.4 2004/10/12 07:55:48 starvik Exp $
- *
- * Etrax specific IDE functions, like init and PIO-mode setting etc.
- * Almost the entire ide.c is used for the rest of the Etrax ATA driver.
- * Copyright (c) 2000-2004 Axis Communications AB
- *
- * Authors:    Bjorn Wesen        (initial version)
- *             Mikael Starvik     (pio setup stuff, Linux 2.6 port)
- */
-
-/* Regarding DMA:
- *
- * There are two forms of DMA - "DMA handshaking" between the interface and the drive,
- * and DMA between the memory and the interface. We can ALWAYS use the latter, since it's
- * something built-in in the Etrax. However only some drives support the DMA-mode handshaking
- * on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the
- * device can't do DMA handshaking for some stupid reason. We don't need to do that.
- */
-
-#undef REALLY_SLOW_IO           /* most systems can safely undef this */
-
-#include <linux/config.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/timer.h>
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/blkdev.h>
-#include <linux/hdreg.h>
-#include <linux/ide.h>
-#include <linux/init.h>
-#include <linux/scatterlist.h>
-
-#include <asm/io.h>
-#include <asm/arch/svinto.h>
-#include <asm/dma.h>
-
-/* number of Etrax DMA descriptors */
-#define MAX_DMA_DESCRS 64
-
-/* number of times to retry busy-flags when reading/writing IDE-registers
- * this can't be too high because a hung harddisk might cause the watchdog
- * to trigger (sometimes INB and OUTB are called with irq's disabled)
- */
-
-#define IDE_REGISTER_TIMEOUT 300
-
-static int e100_read_command = 0;
-
-#define LOWDB(x)
-#define D(x)
-
-static int e100_ide_build_dmatable (ide_drive_t *drive);
-static ide_startstop_t etrax_dma_intr (ide_drive_t *drive);
-
-void
-etrax100_ide_outw(unsigned short data, unsigned long reg) {
-	int timeleft;
-	LOWDB(printk("ow: data 0x%x, reg 0x%x\n", data, reg));
-
-	/* note the lack of handling any timeouts. we stop waiting, but we don't
-	 * really notify anybody.
-	 */
-
-	timeleft = IDE_REGISTER_TIMEOUT;
-	/* wait for busy flag */
-	while(timeleft && (*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)))
-		timeleft--;
-
-	/*
-	 * Fall through at a timeout, so the ongoing command will be
-	 * aborted by the write below, which is expected to be a dummy
-	 * command to the command register.  This happens when a faulty
-	 * drive times out on a command.  See comment on timeout in
-	 * INB.
-	 */
-	if(!timeleft)
-		printk("ATA timeout reg 0x%lx := 0x%x\n", reg, data);
-
-	*R_ATA_CTRL_DATA = reg | data; /* write data to the drive's register */
-
-	timeleft = IDE_REGISTER_TIMEOUT;
-	/* wait for transmitter ready */
-	while(timeleft && !(*R_ATA_STATUS_DATA &
-			    IO_MASK(R_ATA_STATUS_DATA, tr_rdy)))
-		timeleft--;
-}
-
-void
-etrax100_ide_outb(unsigned char data, unsigned long reg)
-{
-	etrax100_ide_outw(data, reg);
-}
-
-void
-etrax100_ide_outbsync(ide_drive_t *drive, u8 addr, unsigned long port)
-{
-	etrax100_ide_outw(addr, port);
-}
-
-unsigned short
-etrax100_ide_inw(unsigned long reg) {
-	int status;
-	int timeleft;
-
-	timeleft = IDE_REGISTER_TIMEOUT;
-	/* wait for busy flag */
-	while(timeleft && (*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)))
-		timeleft--;
-
-	if(!timeleft) {
-		/*
-		 * If we're asked to read the status register, like for
-		 * example when a command does not complete for an
-		 * extended time, but the ATA interface is stuck in a
-		 * busy state at the *ETRAX* ATA interface level (as has
-		 * happened repeatedly with at least one bad disk), then
-		 * the best thing to do is to pretend that we read
-		 * "busy" in the status register, so the IDE driver will
-		 * time-out, abort the ongoing command and perform a
-		 * reset sequence.  Note that the subsequent OUT_BYTE
-		 * call will also timeout on busy, but as long as the
-		 * write is still performed, everything will be fine.
-		 */
-		if ((reg & IO_MASK (R_ATA_CTRL_DATA, addr))
-		    == IO_FIELD (R_ATA_CTRL_DATA, addr, IDE_STATUS_OFFSET))
-			return BUSY_STAT;
-		else
-			/* For other rare cases we assume 0 is good enough.  */
-			return 0;
-	}
-
-	*R_ATA_CTRL_DATA = reg | IO_STATE(R_ATA_CTRL_DATA, rw, read); /* read data */
-
-	timeleft = IDE_REGISTER_TIMEOUT;
-	/* wait for available */
-	while(timeleft && !((status = *R_ATA_STATUS_DATA) &
-			    IO_MASK(R_ATA_STATUS_DATA, dav)))
-		timeleft--;
-
-	if(!timeleft)
-		return 0;
-
-	LOWDB(printk("inb: 0x%x from reg 0x%x\n", status & 0xff, reg));
-
-        return (unsigned short)status;
-}
-
-unsigned char
-etrax100_ide_inb(unsigned long reg)
-{
-	return (unsigned char)etrax100_ide_inw(reg);
-}
-
-/* PIO timing (in R_ATA_CONFIG)
- *
- *                        _____________________________
- * ADDRESS :     ________/
- *
- *                            _______________
- * DIOR    :     ____________/               \__________
- *
- *                               _______________
- * DATA    :     XXXXXXXXXXXXXXXX_______________XXXXXXXX
- *
- *
- * DIOR is unbuffered while address and data is buffered.
- * This creates two problems:
- * 1. The DIOR pulse is to early (because it is unbuffered)
- * 2. The rise time of DIOR is long
- *
- * There are at least three different plausible solutions
- * 1. Use a pad capable of larger currents in Etrax
- * 2. Use an external buffer
- * 3. Make the strobe pulse longer
- *
- * Some of the strobe timings below are modified to compensate
- * for this. This implies a slight performance decrease.
- *
- * THIS SHOULD NEVER BE CHANGED!
- *
- * TODO: Is this true for the latest LX boards still ?
- */
-
-#define ATA_DMA2_STROBE  4
-#define ATA_DMA2_HOLD    0
-#define ATA_DMA1_STROBE  4
-#define ATA_DMA1_HOLD    1
-#define ATA_DMA0_STROBE 12
-#define ATA_DMA0_HOLD    9
-#define ATA_PIO4_SETUP   1
-#define ATA_PIO4_STROBE  5
-#define ATA_PIO4_HOLD    0
-#define ATA_PIO3_SETUP   1
-#define ATA_PIO3_STROBE  5
-#define ATA_PIO3_HOLD    1
-#define ATA_PIO2_SETUP   1
-#define ATA_PIO2_STROBE  6
-#define ATA_PIO2_HOLD    2
-#define ATA_PIO1_SETUP   2
-#define ATA_PIO1_STROBE 11
-#define ATA_PIO1_HOLD    4
-#define ATA_PIO0_SETUP   4
-#define ATA_PIO0_STROBE 19
-#define ATA_PIO0_HOLD    4
-
-static int e100_dma_check (ide_drive_t *drive);
-static void e100_dma_start(ide_drive_t *drive);
-static int e100_dma_end (ide_drive_t *drive);
-static void e100_ide_input_data (ide_drive_t *drive, void *, unsigned int);
-static void e100_ide_output_data (ide_drive_t *drive, void *, unsigned int);
-static void e100_atapi_input_bytes(ide_drive_t *drive, void *, unsigned int);
-static void e100_atapi_output_bytes(ide_drive_t *drive, void *, unsigned int);
-static int e100_dma_off (ide_drive_t *drive);
-
-
-/*
- * good_dma_drives() lists the model names (from "hdparm -i")
- * of drives which do not support mword2 DMA but which are
- * known to work fine with this interface under Linux.
- */
-
-const char *good_dma_drives[] = {"Micropolis 2112A",
-				 "CONNER CTMA 4000",
-				 "CONNER CTT8000-A",
-				 NULL};
-
-static void tune_e100_ide(ide_drive_t *drive, byte pio)
-{
-	pio = 4;
-	/* pio = ide_get_best_pio_mode(drive, pio, 4, NULL); */
-
-	/* set pio mode! */
-
-	switch(pio) {
-		case 0:
-			*R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable,     1 ) |
-					  IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
-					  IO_FIELD( R_ATA_CONFIG, dma_hold,   ATA_DMA2_HOLD ) |
-					  IO_FIELD( R_ATA_CONFIG, pio_setup,  ATA_PIO0_SETUP ) |
-					  IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO0_STROBE ) |
-					  IO_FIELD( R_ATA_CONFIG, pio_hold,   ATA_PIO0_HOLD ) );
-			break;
-		case 1:
-			*R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable,     1 ) |
-					  IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
-					  IO_FIELD( R_ATA_CONFIG, dma_hold,   ATA_DMA2_HOLD ) |
-					  IO_FIELD( R_ATA_CONFIG, pio_setup,  ATA_PIO1_SETUP ) |
-					  IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO1_STROBE ) |
-					  IO_FIELD( R_ATA_CONFIG, pio_hold,   ATA_PIO1_HOLD ) );
-			break;
-		case 2:
-			*R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable,     1 ) |
-					  IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
-					  IO_FIELD( R_ATA_CONFIG, dma_hold,   ATA_DMA2_HOLD ) |
-					  IO_FIELD( R_ATA_CONFIG, pio_setup,  ATA_PIO2_SETUP ) |
-					  IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO2_STROBE ) |
-					  IO_FIELD( R_ATA_CONFIG, pio_hold,   ATA_PIO2_HOLD ) );
-			break;
-		case 3:
-			*R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable,     1 ) |
-					  IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
-					  IO_FIELD( R_ATA_CONFIG, dma_hold,   ATA_DMA2_HOLD ) |
-					  IO_FIELD( R_ATA_CONFIG, pio_setup,  ATA_PIO3_SETUP ) |
-					  IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO3_STROBE ) |
-					  IO_FIELD( R_ATA_CONFIG, pio_hold,   ATA_PIO3_HOLD ) );
-			break;
-		case 4:
-			*R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable,     1 ) |
-					  IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
-					  IO_FIELD( R_ATA_CONFIG, dma_hold,   ATA_DMA2_HOLD ) |
-					  IO_FIELD( R_ATA_CONFIG, pio_setup,  ATA_PIO4_SETUP ) |
-					  IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO4_STROBE ) |
-					  IO_FIELD( R_ATA_CONFIG, pio_hold,   ATA_PIO4_HOLD ) );
-			break;
-	}
-}
-
-static int e100_dma_setup(ide_drive_t *drive)
-{
-	struct request *rq = drive->hwif->hwgroup->rq;
-
-	if (rq_data_dir(rq)) {
-		e100_read_command = 0;
-
-		RESET_DMA(ATA_TX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
-		WAIT_DMA(ATA_TX_DMA_NBR);
-	} else {
-		e100_read_command = 1;
-
-		RESET_DMA(ATA_RX_DMA_NBR); /* sometimes the DMA channel get stuck so we need to do this */
-		WAIT_DMA(ATA_RX_DMA_NBR);
-	}
-
-	/* set up the Etrax DMA descriptors */
-	if (e100_ide_build_dmatable(drive)) {
-		ide_map_sg(drive, rq);
-		return 1;
-	}
-
-	return 0;
-}
-
-static void e100_dma_exec_cmd(ide_drive_t *drive, u8 command)
-{
-	/* set the irq handler which will finish the request when DMA is done */
-	ide_set_handler(drive, &etrax_dma_intr, WAIT_CMD, NULL);
-
-	/* issue cmd to drive */
-	etrax100_ide_outb(command, IDE_COMMAND_REG);
-}
-
-void __init
-init_e100_ide (void)
-{
-	volatile unsigned int dummy;
-	int h;
-
-	printk("ide: ETRAX 100LX built-in ATA DMA controller\n");
-
-	/* first fill in some stuff in the ide_hwifs fields */
-
-	for(h = 0; h < MAX_HWIFS; h++) {
-		ide_hwif_t *hwif = &ide_hwifs[h];
-		hwif->mmio = 2;
-		hwif->chipset = ide_etrax100;
-		hwif->tuneproc = &tune_e100_ide;
-                hwif->ata_input_data = &e100_ide_input_data;
-                hwif->ata_output_data = &e100_ide_output_data;
-                hwif->atapi_input_bytes = &e100_atapi_input_bytes;
-                hwif->atapi_output_bytes = &e100_atapi_output_bytes;
-                hwif->ide_dma_check = &e100_dma_check;
-                hwif->ide_dma_end = &e100_dma_end;
-		hwif->dma_setup = &e100_dma_setup;
-		hwif->dma_exec_cmd = &e100_dma_exec_cmd;
-		hwif->dma_start = &e100_dma_start;
-		hwif->OUTB = &etrax100_ide_outb;
-		hwif->OUTW = &etrax100_ide_outw;
-		hwif->OUTBSYNC = &etrax100_ide_outbsync;
-		hwif->INB = &etrax100_ide_inb;
-		hwif->INW = &etrax100_ide_inw;
-		hwif->ide_dma_off_quietly = &e100_dma_off;
-	}
-
-	/* actually reset and configure the etrax100 ide/ata interface */
-
-	*R_ATA_CTRL_DATA = 0;
-	*R_ATA_TRANSFER_CNT = 0;
-	*R_ATA_CONFIG = 0;
-
-	genconfig_shadow = (genconfig_shadow &
-			    ~IO_MASK(R_GEN_CONFIG, dma2) &
-			    ~IO_MASK(R_GEN_CONFIG, dma3) &
-			    ~IO_MASK(R_GEN_CONFIG, ata)) |
-		( IO_STATE( R_GEN_CONFIG, dma3, ata    ) |
-		  IO_STATE( R_GEN_CONFIG, dma2, ata    ) |
-		  IO_STATE( R_GEN_CONFIG, ata,  select ) );
-
-	*R_GEN_CONFIG = genconfig_shadow;
-
-        /* pull the chosen /reset-line low */
-
-#ifdef CONFIG_ETRAX_IDE_G27_RESET
-        REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, 0);
-#endif
-#ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET
-        REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, 0);
-#endif
-#ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET
-        REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, 0);
-#endif
-#ifdef CONFIG_ETRAX_IDE_PB7_RESET
-	port_pb_dir_shadow = port_pb_dir_shadow |
-		IO_STATE(R_PORT_PB_DIR, dir7, output);
-	*R_PORT_PB_DIR = port_pb_dir_shadow;
-	REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, 1);
-#endif
-
-	/* wait some */
-
-	udelay(25);
-
-	/* de-assert bus-reset */
-
-#ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET
-	REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, 1);
-#endif
-#ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET
-	REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, 1);
-#endif
-#ifdef CONFIG_ETRAX_IDE_G27_RESET
-	REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, 27, 1);
-#endif
-
-	/* make a dummy read to set the ata controller in a proper state */
-	dummy = *R_ATA_STATUS_DATA;
-
-	*R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable,     1 ) |
-			  IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
-			  IO_FIELD( R_ATA_CONFIG, dma_hold,   ATA_DMA2_HOLD ) |
-			  IO_FIELD( R_ATA_CONFIG, pio_setup,  ATA_PIO4_SETUP ) |
-			  IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO4_STROBE ) |
-			  IO_FIELD( R_ATA_CONFIG, pio_hold,   ATA_PIO4_HOLD ) );
-
-	*R_ATA_CTRL_DATA = ( IO_STATE( R_ATA_CTRL_DATA, rw,   read) |
-			     IO_FIELD( R_ATA_CTRL_DATA, addr, 1   ) );
-
-	while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag*/
-
-	*R_IRQ_MASK0_SET = ( IO_STATE( R_IRQ_MASK0_SET, ata_irq0, set ) |
-			     IO_STATE( R_IRQ_MASK0_SET, ata_irq1, set ) |
-			     IO_STATE( R_IRQ_MASK0_SET, ata_irq2, set ) |
-			     IO_STATE( R_IRQ_MASK0_SET, ata_irq3, set ) );
-
-	printk("ide: waiting %d seconds for drives to regain consciousness\n",
-	       CONFIG_ETRAX_IDE_DELAY);
-
-	h = jiffies + (CONFIG_ETRAX_IDE_DELAY * HZ);
-	while(time_before(jiffies, h)) /* nothing */ ;
-
-	/* reset the dma channels we will use */
-
-	RESET_DMA(ATA_TX_DMA_NBR);
-	RESET_DMA(ATA_RX_DMA_NBR);
-	WAIT_DMA(ATA_TX_DMA_NBR);
-	WAIT_DMA(ATA_RX_DMA_NBR);
-
-}
-
-static int e100_dma_off (ide_drive_t *drive)
-{
-	return 0;
-}
-
-static etrax_dma_descr mydescr;
-
-/*
- * The following routines are mainly used by the ATAPI drivers.
- *
- * These routines will round up any request for an odd number of bytes,
- * so if an odd bytecount is specified, be sure that there's at least one
- * extra byte allocated for the buffer.
- */
-static void
-e100_atapi_input_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
-{
-	unsigned long data_reg = IDE_DATA_REG;
-
-	D(printk("atapi_input_bytes, dreg 0x%x, buffer 0x%x, count %d\n",
-		 data_reg, buffer, bytecount));
-
-	if(bytecount & 1) {
-		printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount);
-		bytecount++; /* to round off */
-	}
-
-	/* make sure the DMA channel is available */
-	RESET_DMA(ATA_RX_DMA_NBR);
-	WAIT_DMA(ATA_RX_DMA_NBR);
-
-	/* setup DMA descriptor */
-
-	mydescr.sw_len = bytecount;
-	mydescr.ctrl   = d_eol;
-	mydescr.buf    = virt_to_phys(buffer);
-
-	/* start the dma channel */
-
-	*R_DMA_CH3_FIRST = virt_to_phys(&mydescr);
-	*R_DMA_CH3_CMD   = IO_STATE(R_DMA_CH3_CMD, cmd, start);
-
-	/* initiate a multi word dma read using PIO handshaking */
-
-	*R_ATA_TRANSFER_CNT = IO_FIELD(R_ATA_TRANSFER_CNT, count, bytecount >> 1);
-
-	*R_ATA_CTRL_DATA = data_reg |
-		IO_STATE(R_ATA_CTRL_DATA, rw,       read) |
-		IO_STATE(R_ATA_CTRL_DATA, src_dst,  dma) |
-		IO_STATE(R_ATA_CTRL_DATA, handsh,   pio) |
-		IO_STATE(R_ATA_CTRL_DATA, multi,    on) |
-		IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
-
-	/* wait for completion */
-
-	LED_DISK_READ(1);
-	WAIT_DMA(ATA_RX_DMA_NBR);
-	LED_DISK_READ(0);
-
-#if 0
-        /* old polled transfer code
-	 * this should be moved into a new function that can do polled
-	 * transfers if DMA is not available
-	 */
-
-        /* initiate a multi word read */
-
-        *R_ATA_TRANSFER_CNT = wcount << 1;
-
-        *R_ATA_CTRL_DATA = data_reg |
-                IO_STATE(R_ATA_CTRL_DATA, rw,       read) |
-                IO_STATE(R_ATA_CTRL_DATA, src_dst,  register) |
-                IO_STATE(R_ATA_CTRL_DATA, handsh,   pio) |
-                IO_STATE(R_ATA_CTRL_DATA, multi,    on) |
-                IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
-
-        /* svinto has a latency until the busy bit actually is set */
-
-        nop(); nop();
-        nop(); nop();
-        nop(); nop();
-        nop(); nop();
-        nop(); nop();
-
-        /* unit should be busy during multi transfer */
-        while((status = *R_ATA_STATUS_DATA) & IO_MASK(R_ATA_STATUS_DATA, busy)) {
-                while(!(status & IO_MASK(R_ATA_STATUS_DATA, dav)))
-                        status = *R_ATA_STATUS_DATA;
-                *ptr++ = (unsigned short)(status & 0xffff);
-        }
-#endif
-}
-
-static void
-e100_atapi_output_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
-{
-	unsigned long data_reg = IDE_DATA_REG;
-
-	D(printk("atapi_output_bytes, dreg 0x%x, buffer 0x%x, count %d\n",
-		 data_reg, buffer, bytecount));
-
-	if(bytecount & 1) {
-		printk("odd bytecount %d in atapi_out_bytes!\n", bytecount);
-		bytecount++;
-	}
-
-	/* make sure the DMA channel is available */
-	RESET_DMA(ATA_TX_DMA_NBR);
-	WAIT_DMA(ATA_TX_DMA_NBR);
-
-	/* setup DMA descriptor */
-
-	mydescr.sw_len = bytecount;
-	mydescr.ctrl   = d_eol;
-	mydescr.buf    = virt_to_phys(buffer);
-
-	/* start the dma channel */
-
-	*R_DMA_CH2_FIRST = virt_to_phys(&mydescr);
-	*R_DMA_CH2_CMD   = IO_STATE(R_DMA_CH2_CMD, cmd, start);
-
-	/* initiate a multi word dma write using PIO handshaking */
-
-	*R_ATA_TRANSFER_CNT = IO_FIELD(R_ATA_TRANSFER_CNT, count, bytecount >> 1);
-
-	*R_ATA_CTRL_DATA = data_reg |
-		IO_STATE(R_ATA_CTRL_DATA, rw,       write) |
-		IO_STATE(R_ATA_CTRL_DATA, src_dst,  dma) |
-		IO_STATE(R_ATA_CTRL_DATA, handsh,   pio) |
-		IO_STATE(R_ATA_CTRL_DATA, multi,    on) |
-		IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
-
-	/* wait for completion */
-
-	LED_DISK_WRITE(1);
-	WAIT_DMA(ATA_TX_DMA_NBR);
-	LED_DISK_WRITE(0);
-
-#if 0
-        /* old polled write code - see comment in input_bytes */
-
-	/* wait for busy flag */
-        while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy));
-
-        /* initiate a multi word write */
-
-        *R_ATA_TRANSFER_CNT = bytecount >> 1;
-
-        ctrl = data_reg |
-                IO_STATE(R_ATA_CTRL_DATA, rw,       write) |
-                IO_STATE(R_ATA_CTRL_DATA, src_dst,  register) |
-                IO_STATE(R_ATA_CTRL_DATA, handsh,   pio) |
-                IO_STATE(R_ATA_CTRL_DATA, multi,    on) |
-                IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
-
-        LED_DISK_WRITE(1);
-
-        /* Etrax will set busy = 1 until the multi pio transfer has finished
-         * and tr_rdy = 1 after each successful word transfer.
-         * When the last byte has been transferred Etrax will first set tr_tdy = 1
-         * and then busy = 0 (not in the same cycle). If we read busy before it
-         * has been set to 0 we will think that we should transfer more bytes
-         * and then tr_rdy would be 0 forever. This is solved by checking busy
-         * in the inner loop.
-         */
-
-        do {
-                *R_ATA_CTRL_DATA = ctrl | *ptr++;
-                while(!(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, tr_rdy)) &&
-                      (*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)));
-        } while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy));
-
-        LED_DISK_WRITE(0);
-#endif
-
-}
-
-/*
- * This is used for most PIO data transfers *from* the IDE interface
- */
-static void
-e100_ide_input_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
-{
-	e100_atapi_input_bytes(drive, buffer, wcount << 2);
-}
-
-/*
- * This is used for most PIO data transfers *to* the IDE interface
- */
-static void
-e100_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
-{
-	e100_atapi_output_bytes(drive, buffer, wcount << 2);
-}
-
-/* we only have one DMA channel on the chip for ATA, so we can keep these statically */
-static etrax_dma_descr ata_descrs[MAX_DMA_DESCRS];
-static unsigned int ata_tot_size;
-
-/*
- * e100_ide_build_dmatable() prepares a dma request.
- * Returns 0 if all went okay, returns 1 otherwise.
- */
-static int e100_ide_build_dmatable (ide_drive_t *drive)
-{
-	ide_hwif_t *hwif = HWIF(drive);
-	struct scatterlist* sg;
-	struct request *rq  = HWGROUP(drive)->rq;
-	unsigned long size, addr;
-	unsigned int count = 0;
-	int i = 0;
-
-	sg = hwif->sg_table;
-
-	ata_tot_size = 0;
-
-	ide_map_sg(drive, rq);
-
-	i = hwif->sg_nents;
-
-	while(i) {
-		/*
-		 * Determine addr and size of next buffer area.  We assume that
-		 * individual virtual buffers are always composed linearly in
-		 * physical memory.  For example, we assume that any 8kB buffer
-		 * is always composed of two adjacent physical 4kB pages rather
-		 * than two possibly non-adjacent physical 4kB pages.
-		 */
-		/* group sequential buffers into one large buffer */
-		addr = page_to_phys(sg->page) + sg->offset;
-		size = sg_dma_len(sg);
-		while (sg++, --i) {
-			if ((addr + size) != page_to_phys(sg->page) + sg->offset)
-				break;
-			size += sg_dma_len(sg);
-		}
-
-		/* did we run out of descriptors? */
-
-		if(count >= MAX_DMA_DESCRS) {
-			printk("%s: too few DMA descriptors\n", drive->name);
-			return 1;
-		}
-
-		/* however, this case is more difficult - R_ATA_TRANSFER_CNT cannot be more
-		   than 65536 words per transfer, so in that case we need to either
-		   1) use a DMA interrupt to re-trigger R_ATA_TRANSFER_CNT and continue with
-		      the descriptors, or
-		   2) simply do the request here, and get dma_intr to only ide_end_request on
-		      those blocks that were actually set-up for transfer.
-		*/
-
-		if(ata_tot_size + size > 131072) {
-			printk("too large total ATA DMA request, %d + %d!\n", ata_tot_size, (int)size);
-			return 1;
-		}
-
-		/* If size > 65536 it has to be splitted into new descriptors. Since we don't handle
-                   size > 131072 only one split is necessary */
-
-		if(size > 65536) {
- 		        /* ok we want to do IO at addr, size bytes. set up a new descriptor entry */
-                        ata_descrs[count].sw_len = 0;  /* 0 means 65536, this is a 16-bit field */
-                        ata_descrs[count].ctrl = 0;
-                        ata_descrs[count].buf = addr;
-                        ata_descrs[count].next = virt_to_phys(&ata_descrs[count + 1]);
-                        count++;
-                        ata_tot_size += 65536;
-                        /* size and addr should refere to not handled data */
-                        size -= 65536;
-                        addr += 65536;
-                }
-		/* ok we want to do IO at addr, size bytes. set up a new descriptor entry */
-                if(size == 65536) {
-			ata_descrs[count].sw_len = 0;  /* 0 means 65536, this is a 16-bit field */
-                } else {
-			ata_descrs[count].sw_len = size;
-                }
-		ata_descrs[count].ctrl = 0;
-		ata_descrs[count].buf = addr;
-		ata_descrs[count].next = virt_to_phys(&ata_descrs[count + 1]);
-		count++;
-		ata_tot_size += size;
-	}
-
-	if (count) {
-		/* set the end-of-list flag on the last descriptor */
-		ata_descrs[count - 1].ctrl |= d_eol;
-		/* return and say all is ok */
-		return 0;
-	}
-
-	printk("%s: empty DMA table?\n", drive->name);
-	return 1;	/* let the PIO routines handle this weirdness */
-}
-
-static int config_drive_for_dma (ide_drive_t *drive)
-{
-        const char **list;
-        struct hd_driveid *id = drive->id;
-
-        if (id && (id->capability & 1)) {
-                /* Enable DMA on any drive that supports mword2 DMA */
-                if ((id->field_valid & 2) && (id->dma_mword & 0x404) == 0x404) {
-                        drive->using_dma = 1;
-                        return 0;               /* DMA enabled */
-                }
-
-                /* Consult the list of known "good" drives */
-                list = good_dma_drives;
-                while (*list) {
-                        if (!strcmp(*list++,id->model)) {
-                                drive->using_dma = 1;
-                                return 0;       /* DMA enabled */
-                        }
-                }
-        }
-        return 1;       /* DMA not enabled */
-}
-
-/*
- * etrax_dma_intr() is the handler for disk read/write DMA interrupts
- */
-static ide_startstop_t etrax_dma_intr (ide_drive_t *drive)
-{
-	LED_DISK_READ(0);
-	LED_DISK_WRITE(0);
-
-	return ide_dma_intr(drive);
-}
-
-/*
- * Functions below initiates/aborts DMA read/write operations on a drive.
- *
- * The caller is assumed to have selected the drive and programmed the drive's
- * sector address using CHS or LBA.  All that remains is to prepare for DMA
- * and then issue the actual read/write DMA/PIO command to the drive.
- *
- * Returns 0 if all went well.
- * Returns 1 if DMA read/write could not be started, in which case
- * the caller should revert to PIO for the current request.
- */
-
-static int e100_dma_check(ide_drive_t *drive)
-{
-	return config_drive_for_dma (drive);
-}
-
-static int e100_dma_end(ide_drive_t *drive)
-{
-	/* TODO: check if something went wrong with the DMA */
-	return 0;
-}
-
-static void e100_dma_start(ide_drive_t *drive)
-{
-	if (e100_read_command) {
-		/* begin DMA */
-
-		/* need to do this before RX DMA due to a chip bug
-		 * it is enough to just flush the part of the cache that
-		 * corresponds to the buffers we start, but since HD transfers
-		 * usually are more than 8 kB, it is easier to optimize for the
-		 * normal case and just flush the entire cache. its the only
-		 * way to be sure! (OB movie quote)
-		 */
-		flush_etrax_cache();
-		*R_DMA_CH3_FIRST = virt_to_phys(ata_descrs);
-		*R_DMA_CH3_CMD   = IO_STATE(R_DMA_CH3_CMD, cmd, start);
-
-		/* initiate a multi word dma read using DMA handshaking */
-
-		*R_ATA_TRANSFER_CNT =
-			IO_FIELD(R_ATA_TRANSFER_CNT, count, ata_tot_size >> 1);
-
-		*R_ATA_CTRL_DATA =
-			IO_FIELD(R_ATA_CTRL_DATA, data, IDE_DATA_REG) |
-			IO_STATE(R_ATA_CTRL_DATA, rw,       read) |
-			IO_STATE(R_ATA_CTRL_DATA, src_dst,  dma)  |
-			IO_STATE(R_ATA_CTRL_DATA, handsh,   dma)  |
-			IO_STATE(R_ATA_CTRL_DATA, multi,    on)   |
-			IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
-
-		LED_DISK_READ(1);
-
-		D(printk("dma read of %d bytes.\n", ata_tot_size));
-
-	} else {
-		/* writing */
-		/* begin DMA */
-
-		*R_DMA_CH2_FIRST = virt_to_phys(ata_descrs);
-		*R_DMA_CH2_CMD   = IO_STATE(R_DMA_CH2_CMD, cmd, start);
-
-		/* initiate a multi word dma write using DMA handshaking */
-
-		*R_ATA_TRANSFER_CNT =
-			IO_FIELD(R_ATA_TRANSFER_CNT, count, ata_tot_size >> 1);
-
-		*R_ATA_CTRL_DATA =
-			IO_FIELD(R_ATA_CTRL_DATA, data,     IDE_DATA_REG) |
-			IO_STATE(R_ATA_CTRL_DATA, rw,       write) |
-			IO_STATE(R_ATA_CTRL_DATA, src_dst,  dma) |
-			IO_STATE(R_ATA_CTRL_DATA, handsh,   dma) |
-			IO_STATE(R_ATA_CTRL_DATA, multi,    on) |
-			IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
-
-		LED_DISK_WRITE(1);
-
-		D(printk("dma write of %d bytes.\n", ata_tot_size));
-	}
-}
diff --git a/drivers/ide/ide-probe.c b/drivers/ide/ide-probe.c
index 7df85af7537..94daf40ae32 100644
--- a/drivers/ide/ide-probe.c
+++ b/drivers/ide/ide-probe.c
@@ -960,6 +960,15 @@ static void save_match(ide_hwif_t *hwif, ide_hwif_t *new, ide_hwif_t **match)
 }
 #endif /* MAX_HWIFS > 1 */
 
+static inline int hwif_to_node(ide_hwif_t *hwif)
+{
+	if (hwif->pci_dev)
+		return pcibus_to_node(hwif->pci_dev->bus);
+	else
+		/* Add ways to determine the node of other busses here */
+		return -1;
+}
+
 /*
  * init request queue
  */
@@ -978,8 +987,7 @@ static int ide_init_queue(ide_drive_t *drive)
 	 *	do not.
 	 */
 
-	q = blk_init_queue_node(do_ide_request, &ide_lock,
-				pcibus_to_node(drive->hwif->pci_dev->bus));
+	q = blk_init_queue_node(do_ide_request, &ide_lock, hwif_to_node(hwif));
 	if (!q)
 		return 1;
 
@@ -1048,6 +1056,8 @@ static int init_irq (ide_hwif_t *hwif)
 
 	BUG_ON(in_interrupt());
 	BUG_ON(irqs_disabled());	
+	BUG_ON(hwif == NULL);
+
 	down(&ide_cfg_sem);
 	hwif->hwgroup = NULL;
 #if MAX_HWIFS > 1
@@ -1097,7 +1107,7 @@ static int init_irq (ide_hwif_t *hwif)
 		spin_unlock_irq(&ide_lock);
 	} else {
 		hwgroup = kmalloc_node(sizeof(ide_hwgroup_t), GFP_KERNEL,
-			pcibus_to_node(hwif->drives[0].hwif->pci_dev->bus));
+					hwif_to_node(hwif->drives[0].hwif));
 		if (!hwgroup)
 	       		goto out_up;
 
diff --git a/drivers/ide/legacy/ide-cs.c b/drivers/ide/legacy/ide-cs.c
index aac59751e1b..f1d1ec4e967 100644
--- a/drivers/ide/legacy/ide-cs.c
+++ b/drivers/ide/legacy/ide-cs.c
@@ -465,7 +465,7 @@ static struct pcmcia_device_id ide_ids[] = {
 	PCMCIA_DEVICE_PROD_ID12("CNF CD-M", "CD-ROM", 0x7d93b852, 0x66536591),
 	PCMCIA_DEVICE_PROD_ID12("Creative Technology Ltd.", "PCMCIA CD-ROM Interface Card", 0xff8c8a45, 0xfe8020c4),
 	PCMCIA_DEVICE_PROD_ID12("Digital Equipment Corporation.", "Digital Mobile Media CD-ROM", 0x17692a66, 0xef1dcbde),
-	PCMCIA_DEVICE_PROD_ID12("EXP", "CD", 0x6f58c983, 0xaae5994f),
+	PCMCIA_DEVICE_PROD_ID12("EXP", "CD+GAME", 0x6f58c983, 0x63c13aaf),
 	PCMCIA_DEVICE_PROD_ID12("EXP   ", "CD-ROM", 0x0a5c52fd, 0x66536591),
 	PCMCIA_DEVICE_PROD_ID12("EXP   ", "PnPIDE", 0x0a5c52fd, 0x0c694728),
 	PCMCIA_DEVICE_PROD_ID12("FREECOM", "PCCARD-IDE", 0x5714cbf7, 0x48e0ab8e),
@@ -481,6 +481,7 @@ static struct pcmcia_device_id ide_ids[] = {
 	PCMCIA_DEVICE_PROD_ID12("TOSHIBA", "MK2001MPL", 0xb4585a1a, 0x3489e003),
 	PCMCIA_DEVICE_PROD_ID12("WIT", "IDE16", 0x244e5994, 0x3e232852),
 	PCMCIA_DEVICE_PROD_ID1("STI Flash", 0xe4a13209),
+	PCMCIA_MFC_DEVICE_PROD_ID12(1, "SanDisk", "ConnectPlus", 0x7a954bd9, 0x74be00c6),
 	PCMCIA_DEVICE_NULL,
 };
 MODULE_DEVICE_TABLE(pcmcia, ide_ids);
@@ -507,5 +508,5 @@ static void __exit exit_ide_cs(void)
 	BUG_ON(dev_list != NULL);
 }
 
-module_init(init_ide_cs);
+late_initcall(init_ide_cs);
 module_exit(exit_ide_cs);
diff --git a/drivers/ide/pci/cmd640.c b/drivers/ide/pci/cmd640.c
index 92a2b7caed5..11d035f1983 100644
--- a/drivers/ide/pci/cmd640.c
+++ b/drivers/ide/pci/cmd640.c
@@ -487,7 +487,7 @@ static void display_clocks (unsigned int index)
  * Pack active and recovery counts into single byte representation
  * used by controller
  */
-inline static u8 pack_nibbles (u8 upper, u8 lower)
+static inline u8 pack_nibbles (u8 upper, u8 lower)
 {
 	return ((upper & 0x0f) << 4) | (lower & 0x0f);
 }
diff --git a/drivers/ide/pci/trm290.c b/drivers/ide/pci/trm290.c
index 8b5eea5405e..c26c8ca90dd 100644
--- a/drivers/ide/pci/trm290.c
+++ b/drivers/ide/pci/trm290.c
@@ -5,7 +5,7 @@
  *  May be copied or modified under the terms of the GNU General Public License
  *
  *  June 22, 2004 - get rid of check_region
- *                  Jesper Juhl <juhl-lkml@dif.dk>
+ *                   - Jesper Juhl
  *
  */
 
diff --git a/drivers/ieee1394/sbp2.c b/drivers/ieee1394/sbp2.c
index fe3e1703fa6..627af507643 100644
--- a/drivers/ieee1394/sbp2.c
+++ b/drivers/ieee1394/sbp2.c
@@ -169,6 +169,7 @@ MODULE_DEVICE_TABLE(ieee1394, sbp2_id_table);
  * Debug levels, configured via kernel config, or enable here.
  */
 
+#define CONFIG_IEEE1394_SBP2_DEBUG 0
 /* #define CONFIG_IEEE1394_SBP2_DEBUG_ORBS */
 /* #define CONFIG_IEEE1394_SBP2_DEBUG_DMA */
 /* #define CONFIG_IEEE1394_SBP2_DEBUG 1 */
diff --git a/drivers/infiniband/core/Makefile b/drivers/infiniband/core/Makefile
index e1a7cf3e863..10be36731ed 100644
--- a/drivers/infiniband/core/Makefile
+++ b/drivers/infiniband/core/Makefile
@@ -1,15 +1,20 @@
 EXTRA_CFLAGS += -Idrivers/infiniband/include
 
-obj-$(CONFIG_INFINIBAND) +=		ib_core.o ib_mad.o ib_sa.o ib_umad.o
+obj-$(CONFIG_INFINIBAND) +=		ib_core.o ib_mad.o ib_sa.o \
+					ib_cm.o ib_umad.o ib_ucm.o
 obj-$(CONFIG_INFINIBAND_USER_VERBS) +=	ib_uverbs.o
 
 ib_core-y :=			packer.o ud_header.o verbs.o sysfs.o \
 				device.o fmr_pool.o cache.o
 
-ib_mad-y :=			mad.o smi.o agent.o
+ib_mad-y :=			mad.o smi.o agent.o mad_rmpp.o
 
 ib_sa-y :=			sa_query.o
 
+ib_cm-y :=			cm.o
+
 ib_umad-y :=			user_mad.o
 
+ib_ucm-y :=			ucm.o
+
 ib_uverbs-y :=			uverbs_main.o uverbs_cmd.o uverbs_mem.o
diff --git a/drivers/infiniband/core/agent.c b/drivers/infiniband/core/agent.c
index 23d1957c4b2..729f0b0d983 100644
--- a/drivers/infiniband/core/agent.c
+++ b/drivers/infiniband/core/agent.c
@@ -134,7 +134,7 @@ static int agent_mad_send(struct ib_mad_agent *mad_agent,
 					  sizeof(mad_priv->mad),
 					  DMA_TO_DEVICE);
 	gather_list.length = sizeof(mad_priv->mad);
-	gather_list.lkey = (*port_priv->mr).lkey;
+	gather_list.lkey = mad_agent->mr->lkey;
 
 	send_wr.next = NULL;
 	send_wr.opcode = IB_WR_SEND;
@@ -156,10 +156,10 @@ static int agent_mad_send(struct ib_mad_agent *mad_agent,
 			/* Should sgid be looked up ? */
 			ah_attr.grh.sgid_index = 0;
 			ah_attr.grh.hop_limit = grh->hop_limit;
-			ah_attr.grh.flow_label = be32_to_cpup(
-				&grh->version_tclass_flow)  & 0xfffff;
-			ah_attr.grh.traffic_class = (be32_to_cpup(
-				&grh->version_tclass_flow) >> 20) & 0xff;
+			ah_attr.grh.flow_label = be32_to_cpu(
+				grh->version_tclass_flow)  & 0xfffff;
+			ah_attr.grh.traffic_class = (be32_to_cpu(
+				grh->version_tclass_flow) >> 20) & 0xff;
 			memcpy(ah_attr.grh.dgid.raw,
 			       grh->sgid.raw,
 			       sizeof(ah_attr.grh.dgid));
@@ -322,22 +322,12 @@ int ib_agent_port_open(struct ib_device *device, int port_num)
 		goto error3;
 	}
 
-	port_priv->mr = ib_get_dma_mr(port_priv->smp_agent->qp->pd,
-				      IB_ACCESS_LOCAL_WRITE);
-	if (IS_ERR(port_priv->mr)) {
-		printk(KERN_ERR SPFX "Couldn't get DMA MR\n");
-		ret = PTR_ERR(port_priv->mr);
-		goto error4;
-	}
-
 	spin_lock_irqsave(&ib_agent_port_list_lock, flags);
 	list_add_tail(&port_priv->port_list, &ib_agent_port_list);
 	spin_unlock_irqrestore(&ib_agent_port_list_lock, flags);
 
 	return 0;
 
-error4:
-	ib_unregister_mad_agent(port_priv->perf_mgmt_agent);
 error3:
 	ib_unregister_mad_agent(port_priv->smp_agent);
 error2:
@@ -361,8 +351,6 @@ int ib_agent_port_close(struct ib_device *device, int port_num)
 	list_del(&port_priv->port_list);
 	spin_unlock_irqrestore(&ib_agent_port_list_lock, flags);
 
-	ib_dereg_mr(port_priv->mr);
-
 	ib_unregister_mad_agent(port_priv->perf_mgmt_agent);
 	ib_unregister_mad_agent(port_priv->smp_agent);
 	kfree(port_priv);
diff --git a/drivers/infiniband/core/agent_priv.h b/drivers/infiniband/core/agent_priv.h
index 17a0cce5813..17435af1e91 100644
--- a/drivers/infiniband/core/agent_priv.h
+++ b/drivers/infiniband/core/agent_priv.h
@@ -33,7 +33,7 @@
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
  *
- * $Id: agent_priv.h 1389 2004-12-27 22:56:47Z roland $
+ * $Id: agent_priv.h 1640 2005-01-24 22:39:02Z halr $
  */
 
 #ifndef __IB_AGENT_PRIV_H__
@@ -57,7 +57,6 @@ struct ib_agent_port_private {
 	int port_num;
 	struct ib_mad_agent *smp_agent;	      /* SM class */
 	struct ib_mad_agent *perf_mgmt_agent; /* PerfMgmt class */
-	struct ib_mr *mr;
 };
 
 #endif	/* __IB_AGENT_PRIV_H__ */
diff --git a/drivers/infiniband/core/cm.c b/drivers/infiniband/core/cm.c
new file mode 100644
index 00000000000..403ed125d8f
--- /dev/null
+++ b/drivers/infiniband/core/cm.c
@@ -0,0 +1,3324 @@
+/*
+ * Copyright (c) 2004, 2005 Intel Corporation.  All rights reserved.
+ * Copyright (c) 2004 Topspin Corporation.  All rights reserved.
+ * Copyright (c) 2004, 2005 Voltaire Corporation.  All rights reserved.
+ * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * $Id: cm.c 2821 2005-07-08 17:07:28Z sean.hefty $
+ */
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/idr.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/rbtree.h>
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+
+#include <ib_cache.h>
+#include <ib_cm.h>
+#include "cm_msgs.h"
+
+MODULE_AUTHOR("Sean Hefty");
+MODULE_DESCRIPTION("InfiniBand CM");
+MODULE_LICENSE("Dual BSD/GPL");
+
+static void cm_add_one(struct ib_device *device);
+static void cm_remove_one(struct ib_device *device);
+
+static struct ib_client cm_client = {
+	.name   = "cm",
+	.add    = cm_add_one,
+	.remove = cm_remove_one
+};
+
+static struct ib_cm {
+	spinlock_t lock;
+	struct list_head device_list;
+	rwlock_t device_lock;
+	struct rb_root listen_service_table;
+	u64 listen_service_id;
+	/* struct rb_root peer_service_table; todo: fix peer to peer */
+	struct rb_root remote_qp_table;
+	struct rb_root remote_id_table;
+	struct rb_root remote_sidr_table;
+	struct idr local_id_table;
+	struct workqueue_struct *wq;
+} cm;
+
+struct cm_port {
+	struct cm_device *cm_dev;
+	struct ib_mad_agent *mad_agent;
+	u8 port_num;
+};
+
+struct cm_device {
+	struct list_head list;
+	struct ib_device *device;
+	u64 ca_guid;
+	struct cm_port port[0];
+};
+
+struct cm_av {
+	struct cm_port *port;
+	union ib_gid dgid;
+	struct ib_ah_attr ah_attr;
+	u16 pkey_index;
+	u8 packet_life_time;
+};
+
+struct cm_work {
+	struct work_struct work;
+	struct list_head list;
+	struct cm_port *port;
+	struct ib_mad_recv_wc *mad_recv_wc;	/* Received MADs */
+	u32 local_id;				/* Established / timewait */
+	u32 remote_id;
+	struct ib_cm_event cm_event;
+	struct ib_sa_path_rec path[0];
+};
+
+struct cm_timewait_info {
+	struct cm_work work;			/* Must be first. */
+	struct rb_node remote_qp_node;
+	struct rb_node remote_id_node;
+	u64 remote_ca_guid;
+	u32 remote_qpn;
+	u8 inserted_remote_qp;
+	u8 inserted_remote_id;
+};
+
+struct cm_id_private {
+	struct ib_cm_id	id;
+
+	struct rb_node service_node;
+	struct rb_node sidr_id_node;
+	spinlock_t lock;
+	wait_queue_head_t wait;
+	atomic_t refcount;
+
+	struct ib_mad_send_buf *msg;
+	struct cm_timewait_info *timewait_info;
+	/* todo: use alternate port on send failure */
+	struct cm_av av;
+	struct cm_av alt_av;
+
+	void *private_data;
+	u64 tid;
+	u32 local_qpn;
+	u32 remote_qpn;
+	u32 sq_psn;
+	u32 rq_psn;
+	int timeout_ms;
+	enum ib_mtu path_mtu;
+	u8 private_data_len;
+	u8 max_cm_retries;
+	u8 peer_to_peer;
+	u8 responder_resources;
+	u8 initiator_depth;
+	u8 local_ack_timeout;
+	u8 retry_count;
+	u8 rnr_retry_count;
+	u8 service_timeout;
+
+	struct list_head work_list;
+	atomic_t work_count;
+};
+
+static void cm_work_handler(void *data);
+
+static inline void cm_deref_id(struct cm_id_private *cm_id_priv)
+{
+	if (atomic_dec_and_test(&cm_id_priv->refcount))
+		wake_up(&cm_id_priv->wait);
+}
+
+static int cm_alloc_msg(struct cm_id_private *cm_id_priv,
+			struct ib_mad_send_buf **msg)
+{
+	struct ib_mad_agent *mad_agent;
+	struct ib_mad_send_buf *m;
+	struct ib_ah *ah;
+
+	mad_agent = cm_id_priv->av.port->mad_agent;
+	ah = ib_create_ah(mad_agent->qp->pd, &cm_id_priv->av.ah_attr);
+	if (IS_ERR(ah))
+		return PTR_ERR(ah);
+
+	m = ib_create_send_mad(mad_agent, 1, cm_id_priv->av.pkey_index,
+			       ah, 0, sizeof(struct ib_mad_hdr),
+			       sizeof(struct ib_mad)-sizeof(struct ib_mad_hdr),
+			       GFP_ATOMIC);
+	if (IS_ERR(m)) {
+		ib_destroy_ah(ah);
+		return PTR_ERR(m);
+	}
+
+	/* Timeout set by caller if response is expected. */
+	m->send_wr.wr.ud.retries = cm_id_priv->max_cm_retries;
+
+	atomic_inc(&cm_id_priv->refcount);
+	m->context[0] = cm_id_priv;
+	*msg = m;
+	return 0;
+}
+
+static int cm_alloc_response_msg(struct cm_port *port,
+				 struct ib_mad_recv_wc *mad_recv_wc,
+				 struct ib_mad_send_buf **msg)
+{
+	struct ib_mad_send_buf *m;
+	struct ib_ah *ah;
+
+	ah = ib_create_ah_from_wc(port->mad_agent->qp->pd, mad_recv_wc->wc,
+				  mad_recv_wc->recv_buf.grh, port->port_num);
+	if (IS_ERR(ah))
+		return PTR_ERR(ah);
+
+	m = ib_create_send_mad(port->mad_agent, 1, mad_recv_wc->wc->pkey_index,
+			       ah, 0, sizeof(struct ib_mad_hdr),
+			       sizeof(struct ib_mad)-sizeof(struct ib_mad_hdr),
+			       GFP_ATOMIC);
+	if (IS_ERR(m)) {
+		ib_destroy_ah(ah);
+		return PTR_ERR(m);
+	}
+	*msg = m;
+	return 0;
+}
+
+static void cm_free_msg(struct ib_mad_send_buf *msg)
+{
+	ib_destroy_ah(msg->send_wr.wr.ud.ah);
+	if (msg->context[0])
+		cm_deref_id(msg->context[0]);
+	ib_free_send_mad(msg);
+}
+
+static void * cm_copy_private_data(const void *private_data,
+				   u8 private_data_len)
+{
+	void *data;
+
+	if (!private_data || !private_data_len)
+		return NULL;
+
+	data = kmalloc(private_data_len, GFP_KERNEL);
+	if (!data)
+		return ERR_PTR(-ENOMEM);
+
+	memcpy(data, private_data, private_data_len);
+	return data;
+}
+
+static void cm_set_private_data(struct cm_id_private *cm_id_priv,
+				 void *private_data, u8 private_data_len)
+{
+	if (cm_id_priv->private_data && cm_id_priv->private_data_len)
+		kfree(cm_id_priv->private_data);
+
+	cm_id_priv->private_data = private_data;
+	cm_id_priv->private_data_len = private_data_len;
+}
+
+static void cm_set_ah_attr(struct ib_ah_attr *ah_attr, u8 port_num,
+			   u16 dlid, u8 sl, u16 src_path_bits)
+{
+	memset(ah_attr, 0, sizeof ah_attr);
+	ah_attr->dlid = be16_to_cpu(dlid);
+	ah_attr->sl = sl;
+	ah_attr->src_path_bits = src_path_bits;
+	ah_attr->port_num = port_num;
+}
+
+static void cm_init_av_for_response(struct cm_port *port,
+				    struct ib_wc *wc, struct cm_av *av)
+{
+	av->port = port;
+	av->pkey_index = wc->pkey_index;
+	cm_set_ah_attr(&av->ah_attr, port->port_num, cpu_to_be16(wc->slid),
+		       wc->sl, wc->dlid_path_bits);
+}
+
+static int cm_init_av_by_path(struct ib_sa_path_rec *path, struct cm_av *av)
+{
+	struct cm_device *cm_dev;
+	struct cm_port *port = NULL;
+	unsigned long flags;
+	int ret;
+	u8 p;
+
+	read_lock_irqsave(&cm.device_lock, flags);
+	list_for_each_entry(cm_dev, &cm.device_list, list) {
+		if (!ib_find_cached_gid(cm_dev->device, &path->sgid,
+					&p, NULL)) {
+			port = &cm_dev->port[p-1];
+			break;
+		}
+	}
+	read_unlock_irqrestore(&cm.device_lock, flags);
+
+	if (!port)
+		return -EINVAL;
+
+	ret = ib_find_cached_pkey(cm_dev->device, port->port_num,
+				  be16_to_cpu(path->pkey), &av->pkey_index);
+	if (ret)
+		return ret;
+
+	av->port = port;
+	cm_set_ah_attr(&av->ah_attr, av->port->port_num, path->dlid,
+		       path->sl, path->slid & 0x7F);
+	av->packet_life_time = path->packet_life_time;
+	return 0;
+}
+
+static int cm_alloc_id(struct cm_id_private *cm_id_priv)
+{
+	unsigned long flags;
+	int ret;
+
+	do {
+		spin_lock_irqsave(&cm.lock, flags);
+		ret = idr_get_new_above(&cm.local_id_table, cm_id_priv, 1,
+					(int *) &cm_id_priv->id.local_id);
+		spin_unlock_irqrestore(&cm.lock, flags);
+	} while( (ret == -EAGAIN) && idr_pre_get(&cm.local_id_table, GFP_KERNEL) );
+	return ret;
+}
+
+static void cm_free_id(u32 local_id)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&cm.lock, flags);
+	idr_remove(&cm.local_id_table, (int) local_id);
+	spin_unlock_irqrestore(&cm.lock, flags);
+}
+
+static struct cm_id_private * cm_get_id(u32 local_id, u32 remote_id)
+{
+	struct cm_id_private *cm_id_priv;
+
+	cm_id_priv = idr_find(&cm.local_id_table, (int) local_id);
+	if (cm_id_priv) {
+		if (cm_id_priv->id.remote_id == remote_id)
+			atomic_inc(&cm_id_priv->refcount);
+		else
+			cm_id_priv = NULL;
+	}
+
+	return cm_id_priv;
+}
+
+static struct cm_id_private * cm_acquire_id(u32 local_id, u32 remote_id)
+{
+	struct cm_id_private *cm_id_priv;
+	unsigned long flags;
+
+	spin_lock_irqsave(&cm.lock, flags);
+	cm_id_priv = cm_get_id(local_id, remote_id);
+	spin_unlock_irqrestore(&cm.lock, flags);
+
+	return cm_id_priv;
+}
+
+static struct cm_id_private * cm_insert_listen(struct cm_id_private *cm_id_priv)
+{
+	struct rb_node **link = &cm.listen_service_table.rb_node;
+	struct rb_node *parent = NULL;
+	struct cm_id_private *cur_cm_id_priv;
+	u64 service_id = cm_id_priv->id.service_id;
+	u64 service_mask = cm_id_priv->id.service_mask;
+
+	while (*link) {
+		parent = *link;
+		cur_cm_id_priv = rb_entry(parent, struct cm_id_private,
+					  service_node);
+		if ((cur_cm_id_priv->id.service_mask & service_id) ==
+		    (service_mask & cur_cm_id_priv->id.service_id))
+			return cm_id_priv;
+		if (service_id < cur_cm_id_priv->id.service_id)
+			link = &(*link)->rb_left;
+		else
+			link = &(*link)->rb_right;
+	}
+	rb_link_node(&cm_id_priv->service_node, parent, link);
+	rb_insert_color(&cm_id_priv->service_node, &cm.listen_service_table);
+	return NULL;
+}
+
+static struct cm_id_private * cm_find_listen(u64 service_id)
+{
+	struct rb_node *node = cm.listen_service_table.rb_node;
+	struct cm_id_private *cm_id_priv;
+
+	while (node) {
+		cm_id_priv = rb_entry(node, struct cm_id_private, service_node);
+		if ((cm_id_priv->id.service_mask & service_id) ==
+		    (cm_id_priv->id.service_mask & cm_id_priv->id.service_id))
+			return cm_id_priv;
+		if (service_id < cm_id_priv->id.service_id)
+			node = node->rb_left;
+		else
+			node = node->rb_right;
+	}
+	return NULL;
+}
+
+static struct cm_timewait_info * cm_insert_remote_id(struct cm_timewait_info
+						     *timewait_info)
+{
+	struct rb_node **link = &cm.remote_id_table.rb_node;
+	struct rb_node *parent = NULL;
+	struct cm_timewait_info *cur_timewait_info;
+	u64 remote_ca_guid = timewait_info->remote_ca_guid;
+	u32 remote_id = timewait_info->work.remote_id;
+
+	while (*link) {
+		parent = *link;
+		cur_timewait_info = rb_entry(parent, struct cm_timewait_info,
+					     remote_id_node);
+		if (remote_id < cur_timewait_info->work.remote_id)
+			link = &(*link)->rb_left;
+		else if (remote_id > cur_timewait_info->work.remote_id)
+			link = &(*link)->rb_right;
+		else if (remote_ca_guid < cur_timewait_info->remote_ca_guid)
+			link = &(*link)->rb_left;
+		else if (remote_ca_guid > cur_timewait_info->remote_ca_guid)
+			link = &(*link)->rb_right;
+		else
+			return cur_timewait_info;
+	}
+	timewait_info->inserted_remote_id = 1;
+	rb_link_node(&timewait_info->remote_id_node, parent, link);
+	rb_insert_color(&timewait_info->remote_id_node, &cm.remote_id_table);
+	return NULL;
+}
+
+static struct cm_timewait_info * cm_find_remote_id(u64 remote_ca_guid,
+						   u32 remote_id)
+{
+	struct rb_node *node = cm.remote_id_table.rb_node;
+	struct cm_timewait_info *timewait_info;
+
+	while (node) {
+		timewait_info = rb_entry(node, struct cm_timewait_info,
+					 remote_id_node);
+		if (remote_id < timewait_info->work.remote_id)
+			node = node->rb_left;
+		else if (remote_id > timewait_info->work.remote_id)
+			node = node->rb_right;
+		else if (remote_ca_guid < timewait_info->remote_ca_guid)
+			node = node->rb_left;
+		else if (remote_ca_guid > timewait_info->remote_ca_guid)
+			node = node->rb_right;
+		else
+			return timewait_info;
+	}
+	return NULL;
+}
+
+static struct cm_timewait_info * cm_insert_remote_qpn(struct cm_timewait_info
+						      *timewait_info)
+{
+	struct rb_node **link = &cm.remote_qp_table.rb_node;
+	struct rb_node *parent = NULL;
+	struct cm_timewait_info *cur_timewait_info;
+	u64 remote_ca_guid = timewait_info->remote_ca_guid;
+	u32 remote_qpn = timewait_info->remote_qpn;
+
+	while (*link) {
+		parent = *link;
+		cur_timewait_info = rb_entry(parent, struct cm_timewait_info,
+					     remote_qp_node);
+		if (remote_qpn < cur_timewait_info->remote_qpn)
+			link = &(*link)->rb_left;
+		else if (remote_qpn > cur_timewait_info->remote_qpn)
+			link = &(*link)->rb_right;
+		else if (remote_ca_guid < cur_timewait_info->remote_ca_guid)
+			link = &(*link)->rb_left;
+		else if (remote_ca_guid > cur_timewait_info->remote_ca_guid)
+			link = &(*link)->rb_right;
+		else
+			return cur_timewait_info;
+	}
+	timewait_info->inserted_remote_qp = 1;
+	rb_link_node(&timewait_info->remote_qp_node, parent, link);
+	rb_insert_color(&timewait_info->remote_qp_node, &cm.remote_qp_table);
+	return NULL;
+}
+
+static struct cm_id_private * cm_insert_remote_sidr(struct cm_id_private
+						    *cm_id_priv)
+{
+	struct rb_node **link = &cm.remote_sidr_table.rb_node;
+	struct rb_node *parent = NULL;
+	struct cm_id_private *cur_cm_id_priv;
+	union ib_gid *port_gid = &cm_id_priv->av.dgid;
+	u32 remote_id = cm_id_priv->id.remote_id;
+
+	while (*link) {
+		parent = *link;
+		cur_cm_id_priv = rb_entry(parent, struct cm_id_private,
+					  sidr_id_node);
+		if (remote_id < cur_cm_id_priv->id.remote_id)
+			link = &(*link)->rb_left;
+		else if (remote_id > cur_cm_id_priv->id.remote_id)
+			link = &(*link)->rb_right;
+		else {
+			int cmp;
+			cmp = memcmp(port_gid, &cur_cm_id_priv->av.dgid,
+				     sizeof *port_gid);
+			if (cmp < 0)
+				link = &(*link)->rb_left;
+			else if (cmp > 0)
+				link = &(*link)->rb_right;
+			else
+				return cur_cm_id_priv;
+		}
+	}
+	rb_link_node(&cm_id_priv->sidr_id_node, parent, link);
+	rb_insert_color(&cm_id_priv->sidr_id_node, &cm.remote_sidr_table);
+	return NULL;
+}
+
+static void cm_reject_sidr_req(struct cm_id_private *cm_id_priv,
+			       enum ib_cm_sidr_status status)
+{
+	struct ib_cm_sidr_rep_param param;
+
+	memset(&param, 0, sizeof param);
+	param.status = status;
+	ib_send_cm_sidr_rep(&cm_id_priv->id, &param);
+}
+
+struct ib_cm_id *ib_create_cm_id(ib_cm_handler cm_handler,
+				 void *context)
+{
+	struct cm_id_private *cm_id_priv;
+	int ret;
+
+	cm_id_priv = kmalloc(sizeof *cm_id_priv, GFP_KERNEL);
+	if (!cm_id_priv)
+		return ERR_PTR(-ENOMEM);
+
+	memset(cm_id_priv, 0, sizeof *cm_id_priv);
+	cm_id_priv->id.state = IB_CM_IDLE;
+	cm_id_priv->id.cm_handler = cm_handler;
+	cm_id_priv->id.context = context;
+	ret = cm_alloc_id(cm_id_priv);
+	if (ret)
+		goto error;
+
+	spin_lock_init(&cm_id_priv->lock);
+	init_waitqueue_head(&cm_id_priv->wait);
+	INIT_LIST_HEAD(&cm_id_priv->work_list);
+	atomic_set(&cm_id_priv->work_count, -1);
+	atomic_set(&cm_id_priv->refcount, 1);
+	return &cm_id_priv->id;
+
+error:
+	kfree(cm_id_priv);
+	return ERR_PTR(-ENOMEM);
+}
+EXPORT_SYMBOL(ib_create_cm_id);
+
+static struct cm_work * cm_dequeue_work(struct cm_id_private *cm_id_priv)
+{
+	struct cm_work *work;
+
+	if (list_empty(&cm_id_priv->work_list))
+		return NULL;
+
+	work = list_entry(cm_id_priv->work_list.next, struct cm_work, list);
+	list_del(&work->list);
+	return work;
+}
+
+static void cm_free_work(struct cm_work *work)
+{
+	if (work->mad_recv_wc)
+		ib_free_recv_mad(work->mad_recv_wc);
+	kfree(work);
+}
+
+static inline int cm_convert_to_ms(int iba_time)
+{
+	/* approximate conversion to ms from 4.096us x 2^iba_time */
+	return 1 << max(iba_time - 8, 0);
+}
+
+static void cm_cleanup_timewait(struct cm_timewait_info *timewait_info)
+{
+	unsigned long flags;
+
+	if (!timewait_info->inserted_remote_id &&
+	    !timewait_info->inserted_remote_qp)
+	    return;
+
+	spin_lock_irqsave(&cm.lock, flags);
+	if (timewait_info->inserted_remote_id) {
+		rb_erase(&timewait_info->remote_id_node, &cm.remote_id_table);
+		timewait_info->inserted_remote_id = 0;
+	}
+
+	if (timewait_info->inserted_remote_qp) {
+		rb_erase(&timewait_info->remote_qp_node, &cm.remote_qp_table);
+		timewait_info->inserted_remote_qp = 0;
+	}
+	spin_unlock_irqrestore(&cm.lock, flags);
+}
+
+static struct cm_timewait_info * cm_create_timewait_info(u32 local_id)
+{
+	struct cm_timewait_info *timewait_info;
+
+	timewait_info = kmalloc(sizeof *timewait_info, GFP_KERNEL);
+	if (!timewait_info)
+		return ERR_PTR(-ENOMEM);
+	memset(timewait_info, 0, sizeof *timewait_info);
+
+	timewait_info->work.local_id = local_id;
+	INIT_WORK(&timewait_info->work.work, cm_work_handler,
+		  &timewait_info->work);
+	timewait_info->work.cm_event.event = IB_CM_TIMEWAIT_EXIT;
+	return timewait_info;
+}
+
+static void cm_enter_timewait(struct cm_id_private *cm_id_priv)
+{
+	int wait_time;
+
+	/*
+	 * The cm_id could be destroyed by the user before we exit timewait.
+	 * To protect against this, we search for the cm_id after exiting
+	 * timewait before notifying the user that we've exited timewait.
+	 */
+	cm_id_priv->id.state = IB_CM_TIMEWAIT;
+	wait_time = cm_convert_to_ms(cm_id_priv->local_ack_timeout);
+	queue_delayed_work(cm.wq, &cm_id_priv->timewait_info->work.work,
+			   msecs_to_jiffies(wait_time));
+	cm_id_priv->timewait_info = NULL;
+}
+
+static void cm_reset_to_idle(struct cm_id_private *cm_id_priv)
+{
+	cm_id_priv->id.state = IB_CM_IDLE;
+	if (cm_id_priv->timewait_info) {
+		cm_cleanup_timewait(cm_id_priv->timewait_info);
+		kfree(cm_id_priv->timewait_info);
+		cm_id_priv->timewait_info = NULL;
+	}
+}
+
+void ib_destroy_cm_id(struct ib_cm_id *cm_id)
+{
+	struct cm_id_private *cm_id_priv;
+	struct cm_work *work;
+	unsigned long flags;
+
+	cm_id_priv = container_of(cm_id, struct cm_id_private, id);
+retest:
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	switch (cm_id->state) {
+	case IB_CM_LISTEN:
+		cm_id->state = IB_CM_IDLE;
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		spin_lock_irqsave(&cm.lock, flags);
+		rb_erase(&cm_id_priv->service_node, &cm.listen_service_table);
+		spin_unlock_irqrestore(&cm.lock, flags);
+		break;
+	case IB_CM_SIDR_REQ_SENT:
+		cm_id->state = IB_CM_IDLE;
+		ib_cancel_mad(cm_id_priv->av.port->mad_agent,
+			      (unsigned long) cm_id_priv->msg);
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		break;
+	case IB_CM_SIDR_REQ_RCVD:
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		cm_reject_sidr_req(cm_id_priv, IB_SIDR_REJECT);
+		break;
+	case IB_CM_REQ_SENT:
+	case IB_CM_MRA_REQ_RCVD:
+	case IB_CM_REP_SENT:
+	case IB_CM_MRA_REP_RCVD:
+		ib_cancel_mad(cm_id_priv->av.port->mad_agent,
+			      (unsigned long) cm_id_priv->msg);
+		/* Fall through */
+	case IB_CM_REQ_RCVD:
+	case IB_CM_MRA_REQ_SENT:
+	case IB_CM_REP_RCVD:
+	case IB_CM_MRA_REP_SENT:
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		ib_send_cm_rej(cm_id, IB_CM_REJ_TIMEOUT,
+			       &cm_id_priv->av.port->cm_dev->ca_guid,
+			       sizeof cm_id_priv->av.port->cm_dev->ca_guid,
+			       NULL, 0);
+		break;
+	case IB_CM_ESTABLISHED:
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		ib_send_cm_dreq(cm_id, NULL, 0);
+		goto retest;
+	case IB_CM_DREQ_SENT:
+		ib_cancel_mad(cm_id_priv->av.port->mad_agent,
+			      (unsigned long) cm_id_priv->msg);
+		cm_enter_timewait(cm_id_priv);
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		break;
+	case IB_CM_DREQ_RCVD:
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		ib_send_cm_drep(cm_id, NULL, 0);
+		break;
+	default:
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		break;
+	}
+
+	cm_free_id(cm_id->local_id);
+	atomic_dec(&cm_id_priv->refcount);
+	wait_event(cm_id_priv->wait, !atomic_read(&cm_id_priv->refcount));
+	while ((work = cm_dequeue_work(cm_id_priv)) != NULL)
+		cm_free_work(work);
+	if (cm_id_priv->private_data && cm_id_priv->private_data_len)
+		kfree(cm_id_priv->private_data);
+	kfree(cm_id_priv);
+}
+EXPORT_SYMBOL(ib_destroy_cm_id);
+
+int ib_cm_listen(struct ib_cm_id *cm_id,
+		 u64 service_id,
+		 u64 service_mask)
+{
+	struct cm_id_private *cm_id_priv, *cur_cm_id_priv;
+	unsigned long flags;
+	int ret = 0;
+
+	service_mask = service_mask ? service_mask : ~0ULL;
+	service_id &= service_mask;
+	if ((service_id & IB_SERVICE_ID_AGN_MASK) == IB_CM_ASSIGN_SERVICE_ID &&
+	    (service_id != IB_CM_ASSIGN_SERVICE_ID))
+		return -EINVAL;
+
+	cm_id_priv = container_of(cm_id, struct cm_id_private, id);
+	BUG_ON(cm_id->state != IB_CM_IDLE);
+
+	cm_id->state = IB_CM_LISTEN;
+
+	spin_lock_irqsave(&cm.lock, flags);
+	if (service_id == IB_CM_ASSIGN_SERVICE_ID) {
+		cm_id->service_id = __cpu_to_be64(cm.listen_service_id++);
+		cm_id->service_mask = ~0ULL;
+	} else {
+		cm_id->service_id = service_id;
+		cm_id->service_mask = service_mask;
+	}
+	cur_cm_id_priv = cm_insert_listen(cm_id_priv);
+	spin_unlock_irqrestore(&cm.lock, flags);
+
+	if (cur_cm_id_priv) {
+		cm_id->state = IB_CM_IDLE;
+		ret = -EBUSY;
+	}
+	return ret;
+}
+EXPORT_SYMBOL(ib_cm_listen);
+
+static u64 cm_form_tid(struct cm_id_private *cm_id_priv,
+		       enum cm_msg_sequence msg_seq)
+{
+	u64 hi_tid, low_tid;
+
+	hi_tid   = ((u64) cm_id_priv->av.port->mad_agent->hi_tid) << 32;
+	low_tid  = (u64) (cm_id_priv->id.local_id | (msg_seq << 30));
+	return cpu_to_be64(hi_tid | low_tid);
+}
+
+static void cm_format_mad_hdr(struct ib_mad_hdr *hdr,
+			      enum cm_msg_attr_id attr_id, u64 tid)
+{
+	hdr->base_version  = IB_MGMT_BASE_VERSION;
+	hdr->mgmt_class	   = IB_MGMT_CLASS_CM;
+	hdr->class_version = IB_CM_CLASS_VERSION;
+	hdr->method	   = IB_MGMT_METHOD_SEND;
+	hdr->attr_id	   = attr_id;
+	hdr->tid	   = tid;
+}
+
+static void cm_format_req(struct cm_req_msg *req_msg,
+			  struct cm_id_private *cm_id_priv,
+			  struct ib_cm_req_param *param)
+{
+	cm_format_mad_hdr(&req_msg->hdr, CM_REQ_ATTR_ID,
+			  cm_form_tid(cm_id_priv, CM_MSG_SEQUENCE_REQ));
+
+	req_msg->local_comm_id = cm_id_priv->id.local_id;
+	req_msg->service_id = param->service_id;
+	req_msg->local_ca_guid = cm_id_priv->av.port->cm_dev->ca_guid;
+	cm_req_set_local_qpn(req_msg, cpu_to_be32(param->qp_num));
+	cm_req_set_resp_res(req_msg, param->responder_resources);
+	cm_req_set_init_depth(req_msg, param->initiator_depth);
+	cm_req_set_remote_resp_timeout(req_msg,
+				       param->remote_cm_response_timeout);
+	cm_req_set_qp_type(req_msg, param->qp_type);
+	cm_req_set_flow_ctrl(req_msg, param->flow_control);
+	cm_req_set_starting_psn(req_msg, cpu_to_be32(param->starting_psn));
+	cm_req_set_local_resp_timeout(req_msg,
+				      param->local_cm_response_timeout);
+	cm_req_set_retry_count(req_msg, param->retry_count);
+	req_msg->pkey = param->primary_path->pkey;
+	cm_req_set_path_mtu(req_msg, param->primary_path->mtu);
+	cm_req_set_rnr_retry_count(req_msg, param->rnr_retry_count);
+	cm_req_set_max_cm_retries(req_msg, param->max_cm_retries);
+	cm_req_set_srq(req_msg, param->srq);
+
+	req_msg->primary_local_lid = param->primary_path->slid;
+	req_msg->primary_remote_lid = param->primary_path->dlid;
+	req_msg->primary_local_gid = param->primary_path->sgid;
+	req_msg->primary_remote_gid = param->primary_path->dgid;
+	cm_req_set_primary_flow_label(req_msg, param->primary_path->flow_label);
+	cm_req_set_primary_packet_rate(req_msg, param->primary_path->rate);
+	req_msg->primary_traffic_class = param->primary_path->traffic_class;
+	req_msg->primary_hop_limit = param->primary_path->hop_limit;
+	cm_req_set_primary_sl(req_msg, param->primary_path->sl);
+	cm_req_set_primary_subnet_local(req_msg, 1); /* local only... */
+	cm_req_set_primary_local_ack_timeout(req_msg,
+		min(31, param->primary_path->packet_life_time + 1));
+
+	if (param->alternate_path) {
+		req_msg->alt_local_lid = param->alternate_path->slid;
+		req_msg->alt_remote_lid = param->alternate_path->dlid;
+		req_msg->alt_local_gid = param->alternate_path->sgid;
+		req_msg->alt_remote_gid = param->alternate_path->dgid;
+		cm_req_set_alt_flow_label(req_msg,
+					  param->alternate_path->flow_label);
+		cm_req_set_alt_packet_rate(req_msg, param->alternate_path->rate);
+		req_msg->alt_traffic_class = param->alternate_path->traffic_class;
+		req_msg->alt_hop_limit = param->alternate_path->hop_limit;
+		cm_req_set_alt_sl(req_msg, param->alternate_path->sl);
+		cm_req_set_alt_subnet_local(req_msg, 1); /* local only... */
+		cm_req_set_alt_local_ack_timeout(req_msg,
+			min(31, param->alternate_path->packet_life_time + 1));
+	}
+
+	if (param->private_data && param->private_data_len)
+		memcpy(req_msg->private_data, param->private_data,
+		       param->private_data_len);
+}
+
+static inline int cm_validate_req_param(struct ib_cm_req_param *param)
+{
+	/* peer-to-peer not supported */
+	if (param->peer_to_peer)
+		return -EINVAL;
+
+	if (!param->primary_path)
+		return -EINVAL;
+
+	if (param->qp_type != IB_QPT_RC && param->qp_type != IB_QPT_UC)
+		return -EINVAL;
+
+	if (param->private_data &&
+	    param->private_data_len > IB_CM_REQ_PRIVATE_DATA_SIZE)
+		return -EINVAL;
+
+	if (param->alternate_path &&
+	    (param->alternate_path->pkey != param->primary_path->pkey ||
+	     param->alternate_path->mtu != param->primary_path->mtu))
+		return -EINVAL;
+
+	return 0;
+}
+
+int ib_send_cm_req(struct ib_cm_id *cm_id,
+		   struct ib_cm_req_param *param)
+{
+	struct cm_id_private *cm_id_priv;
+	struct ib_send_wr *bad_send_wr;
+	struct cm_req_msg *req_msg;
+	unsigned long flags;
+	int ret;
+
+	ret = cm_validate_req_param(param);
+	if (ret)
+		return ret;
+
+	/* Verify that we're not in timewait. */
+	cm_id_priv = container_of(cm_id, struct cm_id_private, id);
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	if (cm_id->state != IB_CM_IDLE) {
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		ret = -EINVAL;
+		goto out;
+	}
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+
+	cm_id_priv->timewait_info = cm_create_timewait_info(cm_id_priv->
+							    id.local_id);
+	if (IS_ERR(cm_id_priv->timewait_info))
+		goto out;
+
+	ret = cm_init_av_by_path(param->primary_path, &cm_id_priv->av);
+	if (ret)
+		goto error1;
+	if (param->alternate_path) {
+		ret = cm_init_av_by_path(param->alternate_path,
+					 &cm_id_priv->alt_av);
+		if (ret)
+			goto error1;
+	}
+	cm_id->service_id = param->service_id;
+	cm_id->service_mask = ~0ULL;
+	cm_id_priv->timeout_ms = cm_convert_to_ms(
+				    param->primary_path->packet_life_time) * 2 +
+				 cm_convert_to_ms(
+				    param->remote_cm_response_timeout);
+	cm_id_priv->max_cm_retries = param->max_cm_retries;
+	cm_id_priv->initiator_depth = param->initiator_depth;
+	cm_id_priv->responder_resources = param->responder_resources;
+	cm_id_priv->retry_count = param->retry_count;
+	cm_id_priv->path_mtu = param->primary_path->mtu;
+
+	ret = cm_alloc_msg(cm_id_priv, &cm_id_priv->msg);
+	if (ret)
+		goto error1;
+
+	req_msg = (struct cm_req_msg *) cm_id_priv->msg->mad;
+	cm_format_req(req_msg, cm_id_priv, param);
+	cm_id_priv->tid = req_msg->hdr.tid;
+	cm_id_priv->msg->send_wr.wr.ud.timeout_ms = cm_id_priv->timeout_ms;
+	cm_id_priv->msg->context[1] = (void *) (unsigned long) IB_CM_REQ_SENT;
+
+	cm_id_priv->local_qpn = cm_req_get_local_qpn(req_msg);
+	cm_id_priv->rq_psn = cm_req_get_starting_psn(req_msg);
+	cm_id_priv->local_ack_timeout =
+				cm_req_get_primary_local_ack_timeout(req_msg);
+
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent,
+				&cm_id_priv->msg->send_wr, &bad_send_wr);
+	if (ret) {
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		goto error2;
+	}
+	BUG_ON(cm_id->state != IB_CM_IDLE);
+	cm_id->state = IB_CM_REQ_SENT;
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+	return 0;
+
+error2:	cm_free_msg(cm_id_priv->msg);
+error1:	kfree(cm_id_priv->timewait_info);
+out:	return ret;
+}
+EXPORT_SYMBOL(ib_send_cm_req);
+
+static int cm_issue_rej(struct cm_port *port,
+			struct ib_mad_recv_wc *mad_recv_wc,
+			enum ib_cm_rej_reason reason,
+			enum cm_msg_response msg_rejected,
+			void *ari, u8 ari_length)
+{
+	struct ib_mad_send_buf *msg = NULL;
+	struct ib_send_wr *bad_send_wr;
+	struct cm_rej_msg *rej_msg, *rcv_msg;
+	int ret;
+
+	ret = cm_alloc_response_msg(port, mad_recv_wc, &msg);
+	if (ret)
+		return ret;
+
+	/* We just need common CM header information.  Cast to any message. */
+	rcv_msg = (struct cm_rej_msg *) mad_recv_wc->recv_buf.mad;
+	rej_msg = (struct cm_rej_msg *) msg->mad;
+
+	cm_format_mad_hdr(&rej_msg->hdr, CM_REJ_ATTR_ID, rcv_msg->hdr.tid);
+	rej_msg->remote_comm_id = rcv_msg->local_comm_id;
+	rej_msg->local_comm_id = rcv_msg->remote_comm_id;
+	cm_rej_set_msg_rejected(rej_msg, msg_rejected);
+	rej_msg->reason = reason;
+
+	if (ari && ari_length) {
+		cm_rej_set_reject_info_len(rej_msg, ari_length);
+		memcpy(rej_msg->ari, ari, ari_length);
+	}
+
+	ret = ib_post_send_mad(port->mad_agent, &msg->send_wr, &bad_send_wr);
+	if (ret)
+		cm_free_msg(msg);
+
+	return ret;
+}
+
+static inline int cm_is_active_peer(u64 local_ca_guid, u64 remote_ca_guid,
+				    u32 local_qpn, u32 remote_qpn)
+{
+	return (be64_to_cpu(local_ca_guid) > be64_to_cpu(remote_ca_guid) ||
+		((local_ca_guid == remote_ca_guid) &&
+		 (be32_to_cpu(local_qpn) > be32_to_cpu(remote_qpn))));
+}
+
+static inline void cm_format_paths_from_req(struct cm_req_msg *req_msg,
+					    struct ib_sa_path_rec *primary_path,
+					    struct ib_sa_path_rec *alt_path)
+{
+	memset(primary_path, 0, sizeof *primary_path);
+	primary_path->dgid = req_msg->primary_local_gid;
+	primary_path->sgid = req_msg->primary_remote_gid;
+	primary_path->dlid = req_msg->primary_local_lid;
+	primary_path->slid = req_msg->primary_remote_lid;
+	primary_path->flow_label = cm_req_get_primary_flow_label(req_msg);
+	primary_path->hop_limit = req_msg->primary_hop_limit;
+	primary_path->traffic_class = req_msg->primary_traffic_class;
+	primary_path->reversible = 1;
+	primary_path->pkey = req_msg->pkey;
+	primary_path->sl = cm_req_get_primary_sl(req_msg);
+	primary_path->mtu_selector = IB_SA_EQ;
+	primary_path->mtu = cm_req_get_path_mtu(req_msg);
+	primary_path->rate_selector = IB_SA_EQ;
+	primary_path->rate = cm_req_get_primary_packet_rate(req_msg);
+	primary_path->packet_life_time_selector = IB_SA_EQ;
+	primary_path->packet_life_time =
+		cm_req_get_primary_local_ack_timeout(req_msg);
+	primary_path->packet_life_time -= (primary_path->packet_life_time > 0);
+
+	if (req_msg->alt_local_lid) {
+		memset(alt_path, 0, sizeof *alt_path);
+		alt_path->dgid = req_msg->alt_local_gid;
+		alt_path->sgid = req_msg->alt_remote_gid;
+		alt_path->dlid = req_msg->alt_local_lid;
+		alt_path->slid = req_msg->alt_remote_lid;
+		alt_path->flow_label = cm_req_get_alt_flow_label(req_msg);
+		alt_path->hop_limit = req_msg->alt_hop_limit;
+		alt_path->traffic_class = req_msg->alt_traffic_class;
+		alt_path->reversible = 1;
+		alt_path->pkey = req_msg->pkey;
+		alt_path->sl = cm_req_get_alt_sl(req_msg);
+		alt_path->mtu_selector = IB_SA_EQ;
+		alt_path->mtu = cm_req_get_path_mtu(req_msg);
+		alt_path->rate_selector = IB_SA_EQ;
+		alt_path->rate = cm_req_get_alt_packet_rate(req_msg);
+		alt_path->packet_life_time_selector = IB_SA_EQ;
+		alt_path->packet_life_time =
+			cm_req_get_alt_local_ack_timeout(req_msg);
+		alt_path->packet_life_time -= (alt_path->packet_life_time > 0);
+	}
+}
+
+static void cm_format_req_event(struct cm_work *work,
+				struct cm_id_private *cm_id_priv,
+				struct ib_cm_id *listen_id)
+{
+	struct cm_req_msg *req_msg;
+	struct ib_cm_req_event_param *param;
+
+	req_msg = (struct cm_req_msg *)work->mad_recv_wc->recv_buf.mad;
+	param = &work->cm_event.param.req_rcvd;
+	param->listen_id = listen_id;
+	param->device = cm_id_priv->av.port->mad_agent->device;
+	param->port = cm_id_priv->av.port->port_num;
+	param->primary_path = &work->path[0];
+	if (req_msg->alt_local_lid)
+		param->alternate_path = &work->path[1];
+	else
+		param->alternate_path = NULL;
+	param->remote_ca_guid = req_msg->local_ca_guid;
+	param->remote_qkey = be32_to_cpu(req_msg->local_qkey);
+	param->remote_qpn = be32_to_cpu(cm_req_get_local_qpn(req_msg));
+	param->qp_type = cm_req_get_qp_type(req_msg);
+	param->starting_psn = be32_to_cpu(cm_req_get_starting_psn(req_msg));
+	param->responder_resources = cm_req_get_init_depth(req_msg);
+	param->initiator_depth = cm_req_get_resp_res(req_msg);
+	param->local_cm_response_timeout =
+					cm_req_get_remote_resp_timeout(req_msg);
+	param->flow_control = cm_req_get_flow_ctrl(req_msg);
+	param->remote_cm_response_timeout =
+					cm_req_get_local_resp_timeout(req_msg);
+	param->retry_count = cm_req_get_retry_count(req_msg);
+	param->rnr_retry_count = cm_req_get_rnr_retry_count(req_msg);
+	param->srq = cm_req_get_srq(req_msg);
+	work->cm_event.private_data = &req_msg->private_data;
+}
+
+static void cm_process_work(struct cm_id_private *cm_id_priv,
+			    struct cm_work *work)
+{
+	unsigned long flags;
+	int ret;
+
+	/* We will typically only have the current event to report. */
+	ret = cm_id_priv->id.cm_handler(&cm_id_priv->id, &work->cm_event);
+	cm_free_work(work);
+
+	while (!ret && !atomic_add_negative(-1, &cm_id_priv->work_count)) {
+		spin_lock_irqsave(&cm_id_priv->lock, flags);
+		work = cm_dequeue_work(cm_id_priv);
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		BUG_ON(!work);
+		ret = cm_id_priv->id.cm_handler(&cm_id_priv->id,
+						&work->cm_event);
+		cm_free_work(work);
+	}
+	cm_deref_id(cm_id_priv);
+	if (ret)
+		ib_destroy_cm_id(&cm_id_priv->id);
+}
+
+static void cm_format_mra(struct cm_mra_msg *mra_msg,
+			  struct cm_id_private *cm_id_priv,
+			  enum cm_msg_response msg_mraed, u8 service_timeout,
+			  const void *private_data, u8 private_data_len)
+{
+	cm_format_mad_hdr(&mra_msg->hdr, CM_MRA_ATTR_ID, cm_id_priv->tid);
+	cm_mra_set_msg_mraed(mra_msg, msg_mraed);
+	mra_msg->local_comm_id = cm_id_priv->id.local_id;
+	mra_msg->remote_comm_id = cm_id_priv->id.remote_id;
+	cm_mra_set_service_timeout(mra_msg, service_timeout);
+
+	if (private_data && private_data_len)
+		memcpy(mra_msg->private_data, private_data, private_data_len);
+}
+
+static void cm_format_rej(struct cm_rej_msg *rej_msg,
+			  struct cm_id_private *cm_id_priv,
+			  enum ib_cm_rej_reason reason,
+			  void *ari,
+			  u8 ari_length,
+			  const void *private_data,
+			  u8 private_data_len)
+{
+	cm_format_mad_hdr(&rej_msg->hdr, CM_REJ_ATTR_ID, cm_id_priv->tid);
+	rej_msg->remote_comm_id = cm_id_priv->id.remote_id;
+
+	switch(cm_id_priv->id.state) {
+	case IB_CM_REQ_RCVD:
+		rej_msg->local_comm_id = 0;
+		cm_rej_set_msg_rejected(rej_msg, CM_MSG_RESPONSE_REQ);
+		break;
+	case IB_CM_MRA_REQ_SENT:
+		rej_msg->local_comm_id = cm_id_priv->id.local_id;
+		cm_rej_set_msg_rejected(rej_msg, CM_MSG_RESPONSE_REQ);
+		break;
+	case IB_CM_REP_RCVD:
+	case IB_CM_MRA_REP_SENT:
+		rej_msg->local_comm_id = cm_id_priv->id.local_id;
+		cm_rej_set_msg_rejected(rej_msg, CM_MSG_RESPONSE_REP);
+		break;
+	default:
+		rej_msg->local_comm_id = cm_id_priv->id.local_id;
+		cm_rej_set_msg_rejected(rej_msg, CM_MSG_RESPONSE_OTHER);
+		break;
+	}
+
+	rej_msg->reason = reason;
+	if (ari && ari_length) {
+		cm_rej_set_reject_info_len(rej_msg, ari_length);
+		memcpy(rej_msg->ari, ari, ari_length);
+	}
+
+	if (private_data && private_data_len)
+		memcpy(rej_msg->private_data, private_data, private_data_len);
+}
+
+static void cm_dup_req_handler(struct cm_work *work,
+			       struct cm_id_private *cm_id_priv)
+{
+	struct ib_mad_send_buf *msg = NULL;
+	struct ib_send_wr *bad_send_wr;
+	unsigned long flags;
+	int ret;
+
+	/* Quick state check to discard duplicate REQs. */
+	if (cm_id_priv->id.state == IB_CM_REQ_RCVD)
+		return;
+
+	ret = cm_alloc_response_msg(work->port, work->mad_recv_wc, &msg);
+	if (ret)
+		return;
+
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	switch (cm_id_priv->id.state) {
+	case IB_CM_MRA_REQ_SENT:
+		cm_format_mra((struct cm_mra_msg *) msg->mad, cm_id_priv,
+			      CM_MSG_RESPONSE_REQ, cm_id_priv->service_timeout,
+			      cm_id_priv->private_data,
+			      cm_id_priv->private_data_len);
+		break;
+	case IB_CM_TIMEWAIT:
+		cm_format_rej((struct cm_rej_msg *) msg->mad, cm_id_priv,
+			      IB_CM_REJ_STALE_CONN, NULL, 0, NULL, 0);
+		break;
+	default:
+		goto unlock;
+	}
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+
+	ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent, &msg->send_wr,
+			       &bad_send_wr);
+	if (ret)
+		goto free;
+	return;
+
+unlock:	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+free:	cm_free_msg(msg);
+}
+
+static struct cm_id_private * cm_match_req(struct cm_work *work,
+					   struct cm_id_private *cm_id_priv)
+{
+	struct cm_id_private *listen_cm_id_priv, *cur_cm_id_priv;
+	struct cm_timewait_info *timewait_info;
+	struct cm_req_msg *req_msg;
+	unsigned long flags;
+
+	req_msg = (struct cm_req_msg *)work->mad_recv_wc->recv_buf.mad;
+
+	/* Check for duplicate REQ and stale connections. */
+	spin_lock_irqsave(&cm.lock, flags);
+	timewait_info = cm_insert_remote_id(cm_id_priv->timewait_info);
+	if (!timewait_info)
+		timewait_info = cm_insert_remote_qpn(cm_id_priv->timewait_info);
+
+	if (timewait_info) {
+		cur_cm_id_priv = cm_get_id(timewait_info->work.local_id,
+					   timewait_info->work.remote_id);
+		spin_unlock_irqrestore(&cm.lock, flags);
+		if (cur_cm_id_priv) {
+			cm_dup_req_handler(work, cur_cm_id_priv);
+			cm_deref_id(cur_cm_id_priv);
+		} else
+			cm_issue_rej(work->port, work->mad_recv_wc,
+				     IB_CM_REJ_STALE_CONN, CM_MSG_RESPONSE_REQ,
+				     NULL, 0);
+		goto error;
+	}
+
+	/* Find matching listen request. */
+	listen_cm_id_priv = cm_find_listen(req_msg->service_id);
+	if (!listen_cm_id_priv) {
+		spin_unlock_irqrestore(&cm.lock, flags);
+		cm_issue_rej(work->port, work->mad_recv_wc,
+			     IB_CM_REJ_INVALID_SERVICE_ID, CM_MSG_RESPONSE_REQ,
+			     NULL, 0);
+		goto error;
+	}
+	atomic_inc(&listen_cm_id_priv->refcount);
+	atomic_inc(&cm_id_priv->refcount);
+	cm_id_priv->id.state = IB_CM_REQ_RCVD;
+	atomic_inc(&cm_id_priv->work_count);
+	spin_unlock_irqrestore(&cm.lock, flags);
+	return listen_cm_id_priv;
+
+error:	cm_cleanup_timewait(cm_id_priv->timewait_info);
+	return NULL;
+}
+
+static int cm_req_handler(struct cm_work *work)
+{
+	struct ib_cm_id *cm_id;
+	struct cm_id_private *cm_id_priv, *listen_cm_id_priv;
+	struct cm_req_msg *req_msg;
+	int ret;
+
+	req_msg = (struct cm_req_msg *)work->mad_recv_wc->recv_buf.mad;
+
+	cm_id = ib_create_cm_id(NULL, NULL);
+	if (IS_ERR(cm_id))
+		return PTR_ERR(cm_id);
+
+	cm_id_priv = container_of(cm_id, struct cm_id_private, id);
+	cm_id_priv->id.remote_id = req_msg->local_comm_id;
+	cm_init_av_for_response(work->port, work->mad_recv_wc->wc,
+				&cm_id_priv->av);
+	cm_id_priv->timewait_info = cm_create_timewait_info(cm_id_priv->
+							    id.local_id);
+	if (IS_ERR(cm_id_priv->timewait_info)) {
+		ret = PTR_ERR(cm_id_priv->timewait_info);
+		goto error1;
+	}
+	cm_id_priv->timewait_info->work.remote_id = req_msg->local_comm_id;
+	cm_id_priv->timewait_info->remote_ca_guid = req_msg->local_ca_guid;
+	cm_id_priv->timewait_info->remote_qpn = cm_req_get_local_qpn(req_msg);
+
+	listen_cm_id_priv = cm_match_req(work, cm_id_priv);
+	if (!listen_cm_id_priv) {
+		ret = -EINVAL;
+		goto error2;
+	}
+
+	cm_id_priv->id.cm_handler = listen_cm_id_priv->id.cm_handler;
+	cm_id_priv->id.context = listen_cm_id_priv->id.context;
+	cm_id_priv->id.service_id = req_msg->service_id;
+	cm_id_priv->id.service_mask = ~0ULL;
+
+	cm_format_paths_from_req(req_msg, &work->path[0], &work->path[1]);
+	ret = cm_init_av_by_path(&work->path[0], &cm_id_priv->av);
+	if (ret)
+		goto error3;
+	if (req_msg->alt_local_lid) {
+		ret = cm_init_av_by_path(&work->path[1], &cm_id_priv->alt_av);
+		if (ret)
+			goto error3;
+	}
+	cm_id_priv->tid = req_msg->hdr.tid;
+	cm_id_priv->timeout_ms = cm_convert_to_ms(
+					cm_req_get_local_resp_timeout(req_msg));
+	cm_id_priv->max_cm_retries = cm_req_get_max_cm_retries(req_msg);
+	cm_id_priv->remote_qpn = cm_req_get_local_qpn(req_msg);
+	cm_id_priv->initiator_depth = cm_req_get_resp_res(req_msg);
+	cm_id_priv->responder_resources = cm_req_get_init_depth(req_msg);
+	cm_id_priv->path_mtu = cm_req_get_path_mtu(req_msg);
+	cm_id_priv->sq_psn = cm_req_get_starting_psn(req_msg);
+	cm_id_priv->local_ack_timeout =
+				cm_req_get_primary_local_ack_timeout(req_msg);
+	cm_id_priv->retry_count = cm_req_get_retry_count(req_msg);
+	cm_id_priv->rnr_retry_count = cm_req_get_rnr_retry_count(req_msg);
+
+	cm_format_req_event(work, cm_id_priv, &listen_cm_id_priv->id);
+	cm_process_work(cm_id_priv, work);
+	cm_deref_id(listen_cm_id_priv);
+	return 0;
+
+error3:	atomic_dec(&cm_id_priv->refcount);
+	cm_deref_id(listen_cm_id_priv);
+	cm_cleanup_timewait(cm_id_priv->timewait_info);
+error2:	kfree(cm_id_priv->timewait_info);
+error1:	ib_destroy_cm_id(&cm_id_priv->id);
+	return ret;
+}
+
+static void cm_format_rep(struct cm_rep_msg *rep_msg,
+			  struct cm_id_private *cm_id_priv,
+			  struct ib_cm_rep_param *param)
+{
+	cm_format_mad_hdr(&rep_msg->hdr, CM_REP_ATTR_ID, cm_id_priv->tid);
+	rep_msg->local_comm_id = cm_id_priv->id.local_id;
+	rep_msg->remote_comm_id = cm_id_priv->id.remote_id;
+	cm_rep_set_local_qpn(rep_msg, cpu_to_be32(param->qp_num));
+	cm_rep_set_starting_psn(rep_msg, cpu_to_be32(param->starting_psn));
+	rep_msg->resp_resources = param->responder_resources;
+	rep_msg->initiator_depth = param->initiator_depth;
+	cm_rep_set_target_ack_delay(rep_msg, param->target_ack_delay);
+	cm_rep_set_failover(rep_msg, param->failover_accepted);
+	cm_rep_set_flow_ctrl(rep_msg, param->flow_control);
+	cm_rep_set_rnr_retry_count(rep_msg, param->rnr_retry_count);
+	cm_rep_set_srq(rep_msg, param->srq);
+	rep_msg->local_ca_guid = cm_id_priv->av.port->cm_dev->ca_guid;
+
+	if (param->private_data && param->private_data_len)
+		memcpy(rep_msg->private_data, param->private_data,
+		       param->private_data_len);
+}
+
+int ib_send_cm_rep(struct ib_cm_id *cm_id,
+		   struct ib_cm_rep_param *param)
+{
+	struct cm_id_private *cm_id_priv;
+	struct ib_mad_send_buf *msg;
+	struct cm_rep_msg *rep_msg;
+	struct ib_send_wr *bad_send_wr;
+	unsigned long flags;
+	int ret;
+
+	if (param->private_data &&
+	    param->private_data_len > IB_CM_REP_PRIVATE_DATA_SIZE)
+		return -EINVAL;
+
+	cm_id_priv = container_of(cm_id, struct cm_id_private, id);
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	if (cm_id->state != IB_CM_REQ_RCVD &&
+	    cm_id->state != IB_CM_MRA_REQ_SENT) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	ret = cm_alloc_msg(cm_id_priv, &msg);
+	if (ret)
+		goto out;
+
+	rep_msg = (struct cm_rep_msg *) msg->mad;
+	cm_format_rep(rep_msg, cm_id_priv, param);
+	msg->send_wr.wr.ud.timeout_ms = cm_id_priv->timeout_ms;
+	msg->context[1] = (void *) (unsigned long) IB_CM_REP_SENT;
+
+	ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent,
+			       &msg->send_wr, &bad_send_wr);
+	if (ret) {
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		cm_free_msg(msg);
+		return ret;
+	}
+
+	cm_id->state = IB_CM_REP_SENT;
+	cm_id_priv->msg = msg;
+	cm_id_priv->initiator_depth = param->initiator_depth;
+	cm_id_priv->responder_resources = param->responder_resources;
+	cm_id_priv->rq_psn = cm_rep_get_starting_psn(rep_msg);
+	cm_id_priv->local_qpn = cm_rep_get_local_qpn(rep_msg);
+
+out:	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL(ib_send_cm_rep);
+
+static void cm_format_rtu(struct cm_rtu_msg *rtu_msg,
+			  struct cm_id_private *cm_id_priv,
+			  const void *private_data,
+			  u8 private_data_len)
+{
+	cm_format_mad_hdr(&rtu_msg->hdr, CM_RTU_ATTR_ID, cm_id_priv->tid);
+	rtu_msg->local_comm_id = cm_id_priv->id.local_id;
+	rtu_msg->remote_comm_id = cm_id_priv->id.remote_id;
+
+	if (private_data && private_data_len)
+		memcpy(rtu_msg->private_data, private_data, private_data_len);
+}
+
+int ib_send_cm_rtu(struct ib_cm_id *cm_id,
+		   const void *private_data,
+		   u8 private_data_len)
+{
+	struct cm_id_private *cm_id_priv;
+	struct ib_mad_send_buf *msg;
+	struct ib_send_wr *bad_send_wr;
+	unsigned long flags;
+	void *data;
+	int ret;
+
+	if (private_data && private_data_len > IB_CM_RTU_PRIVATE_DATA_SIZE)
+		return -EINVAL;
+
+	data = cm_copy_private_data(private_data, private_data_len);
+	if (IS_ERR(data))
+		return PTR_ERR(data);
+
+	cm_id_priv = container_of(cm_id, struct cm_id_private, id);
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	if (cm_id->state != IB_CM_REP_RCVD &&
+	    cm_id->state != IB_CM_MRA_REP_SENT) {
+		ret = -EINVAL;
+		goto error;
+	}
+
+	ret = cm_alloc_msg(cm_id_priv, &msg);
+	if (ret)
+		goto error;
+
+	cm_format_rtu((struct cm_rtu_msg *) msg->mad, cm_id_priv,
+		      private_data, private_data_len);
+
+	ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent,
+			       &msg->send_wr, &bad_send_wr);
+	if (ret) {
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		cm_free_msg(msg);
+		kfree(data);
+		return ret;
+	}
+
+	cm_id->state = IB_CM_ESTABLISHED;
+	cm_set_private_data(cm_id_priv, data, private_data_len);
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+	return 0;
+
+error:	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+	kfree(data);
+	return ret;
+}
+EXPORT_SYMBOL(ib_send_cm_rtu);
+
+static void cm_format_rep_event(struct cm_work *work)
+{
+	struct cm_rep_msg *rep_msg;
+	struct ib_cm_rep_event_param *param;
+
+	rep_msg = (struct cm_rep_msg *)work->mad_recv_wc->recv_buf.mad;
+	param = &work->cm_event.param.rep_rcvd;
+	param->remote_ca_guid = rep_msg->local_ca_guid;
+	param->remote_qkey = be32_to_cpu(rep_msg->local_qkey);
+	param->remote_qpn = be32_to_cpu(cm_rep_get_local_qpn(rep_msg));
+	param->starting_psn = be32_to_cpu(cm_rep_get_starting_psn(rep_msg));
+	param->responder_resources = rep_msg->initiator_depth;
+	param->initiator_depth = rep_msg->resp_resources;
+	param->target_ack_delay = cm_rep_get_target_ack_delay(rep_msg);
+	param->failover_accepted = cm_rep_get_failover(rep_msg);
+	param->flow_control = cm_rep_get_flow_ctrl(rep_msg);
+	param->rnr_retry_count = cm_rep_get_rnr_retry_count(rep_msg);
+	param->srq = cm_rep_get_srq(rep_msg);
+	work->cm_event.private_data = &rep_msg->private_data;
+}
+
+static void cm_dup_rep_handler(struct cm_work *work)
+{
+	struct cm_id_private *cm_id_priv;
+	struct cm_rep_msg *rep_msg;
+	struct ib_mad_send_buf *msg = NULL;
+	struct ib_send_wr *bad_send_wr;
+	unsigned long flags;
+	int ret;
+
+	rep_msg = (struct cm_rep_msg *) work->mad_recv_wc->recv_buf.mad;
+	cm_id_priv = cm_acquire_id(rep_msg->remote_comm_id,
+				   rep_msg->local_comm_id);
+	if (!cm_id_priv)
+		return;
+
+	ret = cm_alloc_response_msg(work->port, work->mad_recv_wc, &msg);
+	if (ret)
+		goto deref;
+
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	if (cm_id_priv->id.state == IB_CM_ESTABLISHED)
+		cm_format_rtu((struct cm_rtu_msg *) msg->mad, cm_id_priv,
+			      cm_id_priv->private_data,
+			      cm_id_priv->private_data_len);
+	else if (cm_id_priv->id.state == IB_CM_MRA_REP_SENT)
+		cm_format_mra((struct cm_mra_msg *) msg->mad, cm_id_priv,
+			      CM_MSG_RESPONSE_REP, cm_id_priv->service_timeout,
+			      cm_id_priv->private_data,
+			      cm_id_priv->private_data_len);
+	else
+		goto unlock;
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+
+	ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent, &msg->send_wr,
+			       &bad_send_wr);
+	if (ret)
+		goto free;
+	goto deref;
+
+unlock:	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+free:	cm_free_msg(msg);
+deref:	cm_deref_id(cm_id_priv);
+}
+
+static int cm_rep_handler(struct cm_work *work)
+{
+	struct cm_id_private *cm_id_priv;
+	struct cm_rep_msg *rep_msg;
+	unsigned long flags;
+	int ret;
+
+	rep_msg = (struct cm_rep_msg *)work->mad_recv_wc->recv_buf.mad;
+	cm_id_priv = cm_acquire_id(rep_msg->remote_comm_id, 0);
+	if (!cm_id_priv) {
+		cm_dup_rep_handler(work);
+		return -EINVAL;
+	}
+
+	cm_id_priv->timewait_info->work.remote_id = rep_msg->local_comm_id;
+	cm_id_priv->timewait_info->remote_ca_guid = rep_msg->local_ca_guid;
+	cm_id_priv->timewait_info->remote_qpn = cm_rep_get_local_qpn(rep_msg);
+
+	spin_lock_irqsave(&cm.lock, flags);
+	/* Check for duplicate REP. */
+	if (cm_insert_remote_id(cm_id_priv->timewait_info)) {
+		spin_unlock_irqrestore(&cm.lock, flags);
+		ret = -EINVAL;
+		goto error;
+	}
+	/* Check for a stale connection. */
+	if (cm_insert_remote_qpn(cm_id_priv->timewait_info)) {
+		spin_unlock_irqrestore(&cm.lock, flags);
+		cm_issue_rej(work->port, work->mad_recv_wc,
+			     IB_CM_REJ_STALE_CONN, CM_MSG_RESPONSE_REP,
+			     NULL, 0);
+		ret = -EINVAL;
+		goto error;
+	}
+	spin_unlock_irqrestore(&cm.lock, flags);
+
+	cm_format_rep_event(work);
+
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	switch (cm_id_priv->id.state) {
+	case IB_CM_REQ_SENT:
+	case IB_CM_MRA_REQ_RCVD:
+		break;
+	default:
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		ret = -EINVAL;
+		goto error;
+	}
+	cm_id_priv->id.state = IB_CM_REP_RCVD;
+	cm_id_priv->id.remote_id = rep_msg->local_comm_id;
+	cm_id_priv->remote_qpn = cm_rep_get_local_qpn(rep_msg);
+	cm_id_priv->initiator_depth = rep_msg->resp_resources;
+	cm_id_priv->responder_resources = rep_msg->initiator_depth;
+	cm_id_priv->sq_psn = cm_rep_get_starting_psn(rep_msg);
+	cm_id_priv->rnr_retry_count = cm_rep_get_rnr_retry_count(rep_msg);
+
+	/* todo: handle peer_to_peer */
+
+	ib_cancel_mad(cm_id_priv->av.port->mad_agent,
+		      (unsigned long) cm_id_priv->msg);
+	ret = atomic_inc_and_test(&cm_id_priv->work_count);
+	if (!ret)
+		list_add_tail(&work->list, &cm_id_priv->work_list);
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+
+	if (ret)
+		cm_process_work(cm_id_priv, work);
+	else
+		cm_deref_id(cm_id_priv);
+	return 0;
+
+error:	cm_cleanup_timewait(cm_id_priv->timewait_info);
+	cm_deref_id(cm_id_priv);
+	return ret;
+}
+
+static int cm_establish_handler(struct cm_work *work)
+{
+	struct cm_id_private *cm_id_priv;
+	unsigned long flags;
+	int ret;
+
+	/* See comment in ib_cm_establish about lookup. */
+	cm_id_priv = cm_acquire_id(work->local_id, work->remote_id);
+	if (!cm_id_priv)
+		return -EINVAL;
+
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	if (cm_id_priv->id.state != IB_CM_ESTABLISHED) {
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		goto out;
+	}
+
+	ib_cancel_mad(cm_id_priv->av.port->mad_agent,
+		      (unsigned long) cm_id_priv->msg);
+	ret = atomic_inc_and_test(&cm_id_priv->work_count);
+	if (!ret)
+		list_add_tail(&work->list, &cm_id_priv->work_list);
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+
+	if (ret)
+		cm_process_work(cm_id_priv, work);
+	else
+		cm_deref_id(cm_id_priv);
+	return 0;
+out:
+	cm_deref_id(cm_id_priv);
+	return -EINVAL;
+}
+
+static int cm_rtu_handler(struct cm_work *work)
+{
+	struct cm_id_private *cm_id_priv;
+	struct cm_rtu_msg *rtu_msg;
+	unsigned long flags;
+	int ret;
+
+	rtu_msg = (struct cm_rtu_msg *)work->mad_recv_wc->recv_buf.mad;
+	cm_id_priv = cm_acquire_id(rtu_msg->remote_comm_id,
+				   rtu_msg->local_comm_id);
+	if (!cm_id_priv)
+		return -EINVAL;
+
+	work->cm_event.private_data = &rtu_msg->private_data;
+
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	if (cm_id_priv->id.state != IB_CM_REP_SENT &&
+	    cm_id_priv->id.state != IB_CM_MRA_REP_RCVD) {
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		goto out;
+	}
+	cm_id_priv->id.state = IB_CM_ESTABLISHED;
+
+	ib_cancel_mad(cm_id_priv->av.port->mad_agent,
+		      (unsigned long) cm_id_priv->msg);
+	ret = atomic_inc_and_test(&cm_id_priv->work_count);
+	if (!ret)
+		list_add_tail(&work->list, &cm_id_priv->work_list);
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+
+	if (ret)
+		cm_process_work(cm_id_priv, work);
+	else
+		cm_deref_id(cm_id_priv);
+	return 0;
+out:
+	cm_deref_id(cm_id_priv);
+	return -EINVAL;
+}
+
+static void cm_format_dreq(struct cm_dreq_msg *dreq_msg,
+			  struct cm_id_private *cm_id_priv,
+			  const void *private_data,
+			  u8 private_data_len)
+{
+	cm_format_mad_hdr(&dreq_msg->hdr, CM_DREQ_ATTR_ID,
+			  cm_form_tid(cm_id_priv, CM_MSG_SEQUENCE_DREQ));
+	dreq_msg->local_comm_id = cm_id_priv->id.local_id;
+	dreq_msg->remote_comm_id = cm_id_priv->id.remote_id;
+	cm_dreq_set_remote_qpn(dreq_msg, cm_id_priv->remote_qpn);
+
+	if (private_data && private_data_len)
+		memcpy(dreq_msg->private_data, private_data, private_data_len);
+}
+
+int ib_send_cm_dreq(struct ib_cm_id *cm_id,
+		    const void *private_data,
+		    u8 private_data_len)
+{
+	struct cm_id_private *cm_id_priv;
+	struct ib_mad_send_buf *msg;
+	struct ib_send_wr *bad_send_wr;
+	unsigned long flags;
+	int ret;
+
+	if (private_data && private_data_len > IB_CM_DREQ_PRIVATE_DATA_SIZE)
+		return -EINVAL;
+
+	cm_id_priv = container_of(cm_id, struct cm_id_private, id);
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	if (cm_id->state != IB_CM_ESTABLISHED) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	ret = cm_alloc_msg(cm_id_priv, &msg);
+	if (ret) {
+		cm_enter_timewait(cm_id_priv);
+		goto out;
+	}
+
+	cm_format_dreq((struct cm_dreq_msg *) msg->mad, cm_id_priv,
+		       private_data, private_data_len);
+	msg->send_wr.wr.ud.timeout_ms = cm_id_priv->timeout_ms;
+	msg->context[1] = (void *) (unsigned long) IB_CM_DREQ_SENT;
+
+	ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent,
+			       &msg->send_wr, &bad_send_wr);
+	if (ret) {
+		cm_enter_timewait(cm_id_priv);
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		cm_free_msg(msg);
+		return ret;
+	}
+
+	cm_id->state = IB_CM_DREQ_SENT;
+	cm_id_priv->msg = msg;
+out:	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL(ib_send_cm_dreq);
+
+static void cm_format_drep(struct cm_drep_msg *drep_msg,
+			  struct cm_id_private *cm_id_priv,
+			  const void *private_data,
+			  u8 private_data_len)
+{
+	cm_format_mad_hdr(&drep_msg->hdr, CM_DREP_ATTR_ID, cm_id_priv->tid);
+	drep_msg->local_comm_id = cm_id_priv->id.local_id;
+	drep_msg->remote_comm_id = cm_id_priv->id.remote_id;
+
+	if (private_data && private_data_len)
+		memcpy(drep_msg->private_data, private_data, private_data_len);
+}
+
+int ib_send_cm_drep(struct ib_cm_id *cm_id,
+		    const void *private_data,
+		    u8 private_data_len)
+{
+	struct cm_id_private *cm_id_priv;
+	struct ib_mad_send_buf *msg;
+	struct ib_send_wr *bad_send_wr;
+	unsigned long flags;
+	void *data;
+	int ret;
+
+	if (private_data && private_data_len > IB_CM_DREP_PRIVATE_DATA_SIZE)
+		return -EINVAL;
+
+	data = cm_copy_private_data(private_data, private_data_len);
+	if (IS_ERR(data))
+		return PTR_ERR(data);
+
+	cm_id_priv = container_of(cm_id, struct cm_id_private, id);
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	if (cm_id->state != IB_CM_DREQ_RCVD) {
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		kfree(data);
+		return -EINVAL;
+	}
+
+	cm_set_private_data(cm_id_priv, data, private_data_len);
+	cm_enter_timewait(cm_id_priv);
+
+	ret = cm_alloc_msg(cm_id_priv, &msg);
+	if (ret)
+		goto out;
+
+	cm_format_drep((struct cm_drep_msg *) msg->mad, cm_id_priv,
+		       private_data, private_data_len);
+
+	ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent, &msg->send_wr,
+			       &bad_send_wr);
+	if (ret) {
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		cm_free_msg(msg);
+		return ret;
+	}
+
+out:	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL(ib_send_cm_drep);
+
+static int cm_dreq_handler(struct cm_work *work)
+{
+	struct cm_id_private *cm_id_priv;
+	struct cm_dreq_msg *dreq_msg;
+	struct ib_mad_send_buf *msg = NULL;
+	struct ib_send_wr *bad_send_wr;
+	unsigned long flags;
+	int ret;
+
+	dreq_msg = (struct cm_dreq_msg *)work->mad_recv_wc->recv_buf.mad;
+	cm_id_priv = cm_acquire_id(dreq_msg->remote_comm_id,
+				   dreq_msg->local_comm_id);
+	if (!cm_id_priv)
+		return -EINVAL;
+
+	work->cm_event.private_data = &dreq_msg->private_data;
+
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	if (cm_id_priv->local_qpn != cm_dreq_get_remote_qpn(dreq_msg))
+		goto unlock;
+
+	switch (cm_id_priv->id.state) {
+	case IB_CM_REP_SENT:
+	case IB_CM_DREQ_SENT:
+		ib_cancel_mad(cm_id_priv->av.port->mad_agent,
+			      (unsigned long) cm_id_priv->msg);
+		break;
+	case IB_CM_ESTABLISHED:
+	case IB_CM_MRA_REP_RCVD:
+		break;
+	case IB_CM_TIMEWAIT:
+		if (cm_alloc_response_msg(work->port, work->mad_recv_wc, &msg))
+			goto unlock;
+
+		cm_format_drep((struct cm_drep_msg *) msg->mad, cm_id_priv,
+			       cm_id_priv->private_data,
+			       cm_id_priv->private_data_len);
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+
+		if (ib_post_send_mad(cm_id_priv->av.port->mad_agent,
+				     &msg->send_wr, &bad_send_wr))
+			cm_free_msg(msg);
+		goto deref;
+	default:
+		goto unlock;
+	}
+	cm_id_priv->id.state = IB_CM_DREQ_RCVD;
+	cm_id_priv->tid = dreq_msg->hdr.tid;
+	ret = atomic_inc_and_test(&cm_id_priv->work_count);
+	if (!ret)
+		list_add_tail(&work->list, &cm_id_priv->work_list);
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+
+	if (ret)
+		cm_process_work(cm_id_priv, work);
+	else
+		cm_deref_id(cm_id_priv);
+	return 0;
+
+unlock:	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+deref:	cm_deref_id(cm_id_priv);
+	return -EINVAL;
+}
+
+static int cm_drep_handler(struct cm_work *work)
+{
+	struct cm_id_private *cm_id_priv;
+	struct cm_drep_msg *drep_msg;
+	unsigned long flags;
+	int ret;
+
+	drep_msg = (struct cm_drep_msg *)work->mad_recv_wc->recv_buf.mad;
+	cm_id_priv = cm_acquire_id(drep_msg->remote_comm_id,
+				   drep_msg->local_comm_id);
+	if (!cm_id_priv)
+		return -EINVAL;
+
+	work->cm_event.private_data = &drep_msg->private_data;
+
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	if (cm_id_priv->id.state != IB_CM_DREQ_SENT &&
+	    cm_id_priv->id.state != IB_CM_DREQ_RCVD) {
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		goto out;
+	}
+	cm_enter_timewait(cm_id_priv);
+
+	ib_cancel_mad(cm_id_priv->av.port->mad_agent,
+		      (unsigned long) cm_id_priv->msg);
+	ret = atomic_inc_and_test(&cm_id_priv->work_count);
+	if (!ret)
+		list_add_tail(&work->list, &cm_id_priv->work_list);
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+
+	if (ret)
+		cm_process_work(cm_id_priv, work);
+	else
+		cm_deref_id(cm_id_priv);
+	return 0;
+out:
+	cm_deref_id(cm_id_priv);
+	return -EINVAL;
+}
+
+int ib_send_cm_rej(struct ib_cm_id *cm_id,
+		   enum ib_cm_rej_reason reason,
+		   void *ari,
+		   u8 ari_length,
+		   const void *private_data,
+		   u8 private_data_len)
+{
+	struct cm_id_private *cm_id_priv;
+	struct ib_mad_send_buf *msg;
+	struct ib_send_wr *bad_send_wr;
+	unsigned long flags;
+	int ret;
+
+	if ((private_data && private_data_len > IB_CM_REJ_PRIVATE_DATA_SIZE) ||
+	    (ari && ari_length > IB_CM_REJ_ARI_LENGTH))
+		return -EINVAL;
+
+	cm_id_priv = container_of(cm_id, struct cm_id_private, id);
+
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	switch (cm_id->state) {
+	case IB_CM_REQ_SENT:
+	case IB_CM_MRA_REQ_RCVD:
+	case IB_CM_REQ_RCVD:
+	case IB_CM_MRA_REQ_SENT:
+	case IB_CM_REP_RCVD:
+	case IB_CM_MRA_REP_SENT:
+		ret = cm_alloc_msg(cm_id_priv, &msg);
+		if (!ret)
+			cm_format_rej((struct cm_rej_msg *) msg->mad,
+				      cm_id_priv, reason, ari, ari_length,
+				      private_data, private_data_len);
+
+		cm_reset_to_idle(cm_id_priv);
+		break;
+	case IB_CM_REP_SENT:
+	case IB_CM_MRA_REP_RCVD:
+		ret = cm_alloc_msg(cm_id_priv, &msg);
+		if (!ret)
+			cm_format_rej((struct cm_rej_msg *) msg->mad,
+				      cm_id_priv, reason, ari, ari_length,
+				      private_data, private_data_len);
+
+		cm_enter_timewait(cm_id_priv);
+		break;
+	default:
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if (ret)
+		goto out;
+
+	ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent,
+			       &msg->send_wr, &bad_send_wr);
+	if (ret)
+		cm_free_msg(msg);
+
+out:	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL(ib_send_cm_rej);
+
+static void cm_format_rej_event(struct cm_work *work)
+{
+	struct cm_rej_msg *rej_msg;
+	struct ib_cm_rej_event_param *param;
+
+	rej_msg = (struct cm_rej_msg *)work->mad_recv_wc->recv_buf.mad;
+	param = &work->cm_event.param.rej_rcvd;
+	param->ari = rej_msg->ari;
+	param->ari_length = cm_rej_get_reject_info_len(rej_msg);
+	param->reason = rej_msg->reason;
+	work->cm_event.private_data = &rej_msg->private_data;
+}
+
+static struct cm_id_private * cm_acquire_rejected_id(struct cm_rej_msg *rej_msg)
+{
+	struct cm_timewait_info *timewait_info;
+	struct cm_id_private *cm_id_priv;
+	unsigned long flags;
+	u32 remote_id;
+
+	remote_id = rej_msg->local_comm_id;
+
+	if (rej_msg->reason == IB_CM_REJ_TIMEOUT) {
+		spin_lock_irqsave(&cm.lock, flags);
+		timewait_info = cm_find_remote_id( *((u64 *) rej_msg->ari),
+						  remote_id);
+		if (!timewait_info) {
+			spin_unlock_irqrestore(&cm.lock, flags);
+			return NULL;
+		}
+		cm_id_priv = idr_find(&cm.local_id_table,
+				      (int) timewait_info->work.local_id);
+		if (cm_id_priv) {
+			if (cm_id_priv->id.remote_id == remote_id)
+				atomic_inc(&cm_id_priv->refcount);
+			else
+				cm_id_priv = NULL;
+		}
+		spin_unlock_irqrestore(&cm.lock, flags);
+	} else if (cm_rej_get_msg_rejected(rej_msg) == CM_MSG_RESPONSE_REQ)
+		cm_id_priv = cm_acquire_id(rej_msg->remote_comm_id, 0);
+	else
+		cm_id_priv = cm_acquire_id(rej_msg->remote_comm_id, remote_id);
+
+	return cm_id_priv;
+}
+
+static int cm_rej_handler(struct cm_work *work)
+{
+	struct cm_id_private *cm_id_priv;
+	struct cm_rej_msg *rej_msg;
+	unsigned long flags;
+	int ret;
+
+	rej_msg = (struct cm_rej_msg *)work->mad_recv_wc->recv_buf.mad;
+	cm_id_priv = cm_acquire_rejected_id(rej_msg);
+	if (!cm_id_priv)
+		return -EINVAL;
+
+	cm_format_rej_event(work);
+
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	switch (cm_id_priv->id.state) {
+	case IB_CM_REQ_SENT:
+	case IB_CM_MRA_REQ_RCVD:
+	case IB_CM_REP_SENT:
+	case IB_CM_MRA_REP_RCVD:
+		ib_cancel_mad(cm_id_priv->av.port->mad_agent,
+			      (unsigned long) cm_id_priv->msg);
+		/* fall through */
+	case IB_CM_REQ_RCVD:
+	case IB_CM_MRA_REQ_SENT:
+		if (rej_msg->reason == IB_CM_REJ_STALE_CONN)
+			cm_enter_timewait(cm_id_priv);
+		else
+			cm_reset_to_idle(cm_id_priv);
+		break;
+	case IB_CM_DREQ_SENT:
+		ib_cancel_mad(cm_id_priv->av.port->mad_agent,
+			      (unsigned long) cm_id_priv->msg);
+		/* fall through */
+	case IB_CM_REP_RCVD:
+	case IB_CM_MRA_REP_SENT:
+	case IB_CM_ESTABLISHED:
+		cm_enter_timewait(cm_id_priv);
+		break;
+	default:
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		ret = -EINVAL;
+		goto out;
+	}
+
+	ret = atomic_inc_and_test(&cm_id_priv->work_count);
+	if (!ret)
+		list_add_tail(&work->list, &cm_id_priv->work_list);
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+
+	if (ret)
+		cm_process_work(cm_id_priv, work);
+	else
+		cm_deref_id(cm_id_priv);
+	return 0;
+out:
+	cm_deref_id(cm_id_priv);
+	return -EINVAL;
+}
+
+int ib_send_cm_mra(struct ib_cm_id *cm_id,
+		   u8 service_timeout,
+		   const void *private_data,
+		   u8 private_data_len)
+{
+	struct cm_id_private *cm_id_priv;
+	struct ib_mad_send_buf *msg;
+	struct ib_send_wr *bad_send_wr;
+	void *data;
+	unsigned long flags;
+	int ret;
+
+	if (private_data && private_data_len > IB_CM_MRA_PRIVATE_DATA_SIZE)
+		return -EINVAL;
+
+	data = cm_copy_private_data(private_data, private_data_len);
+	if (IS_ERR(data))
+		return PTR_ERR(data);
+
+	cm_id_priv = container_of(cm_id, struct cm_id_private, id);
+
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	switch(cm_id_priv->id.state) {
+	case IB_CM_REQ_RCVD:
+		ret = cm_alloc_msg(cm_id_priv, &msg);
+		if (ret)
+			goto error1;
+
+		cm_format_mra((struct cm_mra_msg *) msg->mad, cm_id_priv,
+			      CM_MSG_RESPONSE_REQ, service_timeout,
+			      private_data, private_data_len);
+		ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent,
+				       &msg->send_wr, &bad_send_wr);
+		if (ret)
+			goto error2;
+		cm_id->state = IB_CM_MRA_REQ_SENT;
+		break;
+	case IB_CM_REP_RCVD:
+		ret = cm_alloc_msg(cm_id_priv, &msg);
+		if (ret)
+			goto error1;
+
+		cm_format_mra((struct cm_mra_msg *) msg->mad, cm_id_priv,
+			      CM_MSG_RESPONSE_REP, service_timeout,
+			      private_data, private_data_len);
+		ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent,
+				       &msg->send_wr, &bad_send_wr);
+		if (ret)
+			goto error2;
+		cm_id->state = IB_CM_MRA_REP_SENT;
+		break;
+	case IB_CM_ESTABLISHED:
+		ret = cm_alloc_msg(cm_id_priv, &msg);
+		if (ret)
+			goto error1;
+
+		cm_format_mra((struct cm_mra_msg *) msg->mad, cm_id_priv,
+			      CM_MSG_RESPONSE_OTHER, service_timeout,
+			      private_data, private_data_len);
+		ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent,
+				       &msg->send_wr, &bad_send_wr);
+		if (ret)
+			goto error2;
+		cm_id->lap_state = IB_CM_MRA_LAP_SENT;
+		break;
+	default:
+		ret = -EINVAL;
+		goto error1;
+	}
+	cm_id_priv->service_timeout = service_timeout;
+	cm_set_private_data(cm_id_priv, data, private_data_len);
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+	return 0;
+
+error1:	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+	kfree(data);
+	return ret;
+
+error2:	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+	kfree(data);
+	cm_free_msg(msg);
+	return ret;
+}
+EXPORT_SYMBOL(ib_send_cm_mra);
+
+static struct cm_id_private * cm_acquire_mraed_id(struct cm_mra_msg *mra_msg)
+{
+	switch (cm_mra_get_msg_mraed(mra_msg)) {
+	case CM_MSG_RESPONSE_REQ:
+		return cm_acquire_id(mra_msg->remote_comm_id, 0);
+	case CM_MSG_RESPONSE_REP:
+	case CM_MSG_RESPONSE_OTHER:
+		return cm_acquire_id(mra_msg->remote_comm_id,
+				     mra_msg->local_comm_id);
+	default:
+		return NULL;
+	}
+}
+
+static int cm_mra_handler(struct cm_work *work)
+{
+	struct cm_id_private *cm_id_priv;
+	struct cm_mra_msg *mra_msg;
+	unsigned long flags;
+	int timeout, ret;
+
+	mra_msg = (struct cm_mra_msg *)work->mad_recv_wc->recv_buf.mad;
+	cm_id_priv = cm_acquire_mraed_id(mra_msg);
+	if (!cm_id_priv)
+		return -EINVAL;
+
+	work->cm_event.private_data = &mra_msg->private_data;
+	work->cm_event.param.mra_rcvd.service_timeout =
+					cm_mra_get_service_timeout(mra_msg);
+	timeout = cm_convert_to_ms(cm_mra_get_service_timeout(mra_msg)) +
+		  cm_convert_to_ms(cm_id_priv->av.packet_life_time);
+
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	switch (cm_id_priv->id.state) {
+	case IB_CM_REQ_SENT:
+		if (cm_mra_get_msg_mraed(mra_msg) != CM_MSG_RESPONSE_REQ ||
+		    ib_modify_mad(cm_id_priv->av.port->mad_agent,
+				  (unsigned long) cm_id_priv->msg, timeout))
+			goto out;
+		cm_id_priv->id.state = IB_CM_MRA_REQ_RCVD;
+		break;
+	case IB_CM_REP_SENT:
+		if (cm_mra_get_msg_mraed(mra_msg) != CM_MSG_RESPONSE_REP ||
+		    ib_modify_mad(cm_id_priv->av.port->mad_agent,
+				  (unsigned long) cm_id_priv->msg, timeout))
+			goto out;
+		cm_id_priv->id.state = IB_CM_MRA_REP_RCVD;
+		break;
+	case IB_CM_ESTABLISHED:
+		if (cm_mra_get_msg_mraed(mra_msg) != CM_MSG_RESPONSE_OTHER ||
+		    cm_id_priv->id.lap_state != IB_CM_LAP_SENT ||
+		    ib_modify_mad(cm_id_priv->av.port->mad_agent,
+				  (unsigned long) cm_id_priv->msg, timeout))
+			goto out;
+		cm_id_priv->id.lap_state = IB_CM_MRA_LAP_RCVD;
+		break;
+	default:
+		goto out;
+	}
+
+	cm_id_priv->msg->context[1] = (void *) (unsigned long)
+				      cm_id_priv->id.state;
+	ret = atomic_inc_and_test(&cm_id_priv->work_count);
+	if (!ret)
+		list_add_tail(&work->list, &cm_id_priv->work_list);
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+
+	if (ret)
+		cm_process_work(cm_id_priv, work);
+	else
+		cm_deref_id(cm_id_priv);
+	return 0;
+out:
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+	cm_deref_id(cm_id_priv);
+	return -EINVAL;
+}
+
+static void cm_format_lap(struct cm_lap_msg *lap_msg,
+			  struct cm_id_private *cm_id_priv,
+			  struct ib_sa_path_rec *alternate_path,
+			  const void *private_data,
+			  u8 private_data_len)
+{
+	cm_format_mad_hdr(&lap_msg->hdr, CM_LAP_ATTR_ID,
+			  cm_form_tid(cm_id_priv, CM_MSG_SEQUENCE_LAP));
+	lap_msg->local_comm_id = cm_id_priv->id.local_id;
+	lap_msg->remote_comm_id = cm_id_priv->id.remote_id;
+	cm_lap_set_remote_qpn(lap_msg, cm_id_priv->remote_qpn);
+	/* todo: need remote CM response timeout */
+	cm_lap_set_remote_resp_timeout(lap_msg, 0x1F);
+	lap_msg->alt_local_lid = alternate_path->slid;
+	lap_msg->alt_remote_lid = alternate_path->dlid;
+	lap_msg->alt_local_gid = alternate_path->sgid;
+	lap_msg->alt_remote_gid = alternate_path->dgid;
+	cm_lap_set_flow_label(lap_msg, alternate_path->flow_label);
+	cm_lap_set_traffic_class(lap_msg, alternate_path->traffic_class);
+	lap_msg->alt_hop_limit = alternate_path->hop_limit;
+	cm_lap_set_packet_rate(lap_msg, alternate_path->rate);
+	cm_lap_set_sl(lap_msg, alternate_path->sl);
+	cm_lap_set_subnet_local(lap_msg, 1); /* local only... */
+	cm_lap_set_local_ack_timeout(lap_msg,
+		min(31, alternate_path->packet_life_time + 1));
+
+	if (private_data && private_data_len)
+		memcpy(lap_msg->private_data, private_data, private_data_len);
+}
+
+int ib_send_cm_lap(struct ib_cm_id *cm_id,
+		   struct ib_sa_path_rec *alternate_path,
+		   const void *private_data,
+		   u8 private_data_len)
+{
+	struct cm_id_private *cm_id_priv;
+	struct ib_mad_send_buf *msg;
+	struct ib_send_wr *bad_send_wr;
+	unsigned long flags;
+	int ret;
+
+	if (private_data && private_data_len > IB_CM_LAP_PRIVATE_DATA_SIZE)
+		return -EINVAL;
+
+	cm_id_priv = container_of(cm_id, struct cm_id_private, id);
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	if (cm_id->state != IB_CM_ESTABLISHED ||
+	    cm_id->lap_state != IB_CM_LAP_IDLE) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	ret = cm_alloc_msg(cm_id_priv, &msg);
+	if (ret)
+		goto out;
+
+	cm_format_lap((struct cm_lap_msg *) msg->mad, cm_id_priv,
+		      alternate_path, private_data, private_data_len);
+	msg->send_wr.wr.ud.timeout_ms = cm_id_priv->timeout_ms;
+	msg->context[1] = (void *) (unsigned long) IB_CM_ESTABLISHED;
+
+	ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent,
+			       &msg->send_wr, &bad_send_wr);
+	if (ret) {
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		cm_free_msg(msg);
+		return ret;
+	}
+
+	cm_id->lap_state = IB_CM_LAP_SENT;
+	cm_id_priv->msg = msg;
+
+out:	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL(ib_send_cm_lap);
+
+static void cm_format_path_from_lap(struct ib_sa_path_rec *path,
+				    struct cm_lap_msg *lap_msg)
+{
+	memset(path, 0, sizeof *path);
+	path->dgid = lap_msg->alt_local_gid;
+	path->sgid = lap_msg->alt_remote_gid;
+	path->dlid = lap_msg->alt_local_lid;
+	path->slid = lap_msg->alt_remote_lid;
+	path->flow_label = cm_lap_get_flow_label(lap_msg);
+	path->hop_limit = lap_msg->alt_hop_limit;
+	path->traffic_class = cm_lap_get_traffic_class(lap_msg);
+	path->reversible = 1;
+	/* pkey is same as in REQ */
+	path->sl = cm_lap_get_sl(lap_msg);
+	path->mtu_selector = IB_SA_EQ;
+	/* mtu is same as in REQ */
+	path->rate_selector = IB_SA_EQ;
+	path->rate = cm_lap_get_packet_rate(lap_msg);
+	path->packet_life_time_selector = IB_SA_EQ;
+	path->packet_life_time = cm_lap_get_local_ack_timeout(lap_msg);
+	path->packet_life_time -= (path->packet_life_time > 0);
+}
+
+static int cm_lap_handler(struct cm_work *work)
+{
+	struct cm_id_private *cm_id_priv;
+	struct cm_lap_msg *lap_msg;
+	struct ib_cm_lap_event_param *param;
+	struct ib_mad_send_buf *msg = NULL;
+	struct ib_send_wr *bad_send_wr;
+	unsigned long flags;
+	int ret;
+
+	/* todo: verify LAP request and send reject APR if invalid. */
+	lap_msg = (struct cm_lap_msg *)work->mad_recv_wc->recv_buf.mad;
+	cm_id_priv = cm_acquire_id(lap_msg->remote_comm_id,
+				   lap_msg->local_comm_id);
+	if (!cm_id_priv)
+		return -EINVAL;
+
+	param = &work->cm_event.param.lap_rcvd;
+	param->alternate_path = &work->path[0];
+	cm_format_path_from_lap(param->alternate_path, lap_msg);
+	work->cm_event.private_data = &lap_msg->private_data;
+
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	if (cm_id_priv->id.state != IB_CM_ESTABLISHED)
+		goto unlock;
+
+	switch (cm_id_priv->id.lap_state) {
+	case IB_CM_LAP_IDLE:
+		break;
+	case IB_CM_MRA_LAP_SENT:
+		if (cm_alloc_response_msg(work->port, work->mad_recv_wc, &msg))
+			goto unlock;
+
+		cm_format_mra((struct cm_mra_msg *) msg->mad, cm_id_priv,
+			      CM_MSG_RESPONSE_OTHER,
+			      cm_id_priv->service_timeout,
+			      cm_id_priv->private_data,
+			      cm_id_priv->private_data_len);
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+
+		if (ib_post_send_mad(cm_id_priv->av.port->mad_agent,
+				     &msg->send_wr, &bad_send_wr))
+			cm_free_msg(msg);
+		goto deref;
+	default:
+		goto unlock;
+	}
+
+	cm_id_priv->id.lap_state = IB_CM_LAP_RCVD;
+	cm_id_priv->tid = lap_msg->hdr.tid;
+	ret = atomic_inc_and_test(&cm_id_priv->work_count);
+	if (!ret)
+		list_add_tail(&work->list, &cm_id_priv->work_list);
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+
+	if (ret)
+		cm_process_work(cm_id_priv, work);
+	else
+		cm_deref_id(cm_id_priv);
+	return 0;
+
+unlock:	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+deref:	cm_deref_id(cm_id_priv);
+	return -EINVAL;
+}
+
+static void cm_format_apr(struct cm_apr_msg *apr_msg,
+			  struct cm_id_private *cm_id_priv,
+			  enum ib_cm_apr_status status,
+			  void *info,
+			  u8 info_length,
+			  const void *private_data,
+			  u8 private_data_len)
+{
+	cm_format_mad_hdr(&apr_msg->hdr, CM_APR_ATTR_ID, cm_id_priv->tid);
+	apr_msg->local_comm_id = cm_id_priv->id.local_id;
+	apr_msg->remote_comm_id = cm_id_priv->id.remote_id;
+	apr_msg->ap_status = (u8) status;
+
+	if (info && info_length) {
+		apr_msg->info_length = info_length;
+		memcpy(apr_msg->info, info, info_length);
+	}
+
+	if (private_data && private_data_len)
+		memcpy(apr_msg->private_data, private_data, private_data_len);
+}
+
+int ib_send_cm_apr(struct ib_cm_id *cm_id,
+		   enum ib_cm_apr_status status,
+		   void *info,
+		   u8 info_length,
+		   const void *private_data,
+		   u8 private_data_len)
+{
+	struct cm_id_private *cm_id_priv;
+	struct ib_mad_send_buf *msg;
+	struct ib_send_wr *bad_send_wr;
+	unsigned long flags;
+	int ret;
+
+	if ((private_data && private_data_len > IB_CM_APR_PRIVATE_DATA_SIZE) ||
+	    (info && info_length > IB_CM_APR_INFO_LENGTH))
+		return -EINVAL;
+
+	cm_id_priv = container_of(cm_id, struct cm_id_private, id);
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	if (cm_id->state != IB_CM_ESTABLISHED ||
+	    (cm_id->lap_state != IB_CM_LAP_RCVD &&
+	     cm_id->lap_state != IB_CM_MRA_LAP_SENT)) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	ret = cm_alloc_msg(cm_id_priv, &msg);
+	if (ret)
+		goto out;
+
+	cm_format_apr((struct cm_apr_msg *) msg->mad, cm_id_priv, status,
+		      info, info_length, private_data, private_data_len);
+	ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent,
+			       &msg->send_wr, &bad_send_wr);
+	if (ret) {
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		cm_free_msg(msg);
+		return ret;
+	}
+
+	cm_id->lap_state = IB_CM_LAP_IDLE;
+out:	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL(ib_send_cm_apr);
+
+static int cm_apr_handler(struct cm_work *work)
+{
+	struct cm_id_private *cm_id_priv;
+	struct cm_apr_msg *apr_msg;
+	unsigned long flags;
+	int ret;
+
+	apr_msg = (struct cm_apr_msg *)work->mad_recv_wc->recv_buf.mad;
+	cm_id_priv = cm_acquire_id(apr_msg->remote_comm_id,
+				   apr_msg->local_comm_id);
+	if (!cm_id_priv)
+		return -EINVAL; /* Unmatched reply. */
+
+	work->cm_event.param.apr_rcvd.ap_status = apr_msg->ap_status;
+	work->cm_event.param.apr_rcvd.apr_info = &apr_msg->info;
+	work->cm_event.param.apr_rcvd.info_len = apr_msg->info_length;
+	work->cm_event.private_data = &apr_msg->private_data;
+
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	if (cm_id_priv->id.state != IB_CM_ESTABLISHED ||
+	    (cm_id_priv->id.lap_state != IB_CM_LAP_SENT &&
+	     cm_id_priv->id.lap_state != IB_CM_MRA_LAP_RCVD)) {
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		goto out;
+	}
+	cm_id_priv->id.lap_state = IB_CM_LAP_IDLE;
+	ib_cancel_mad(cm_id_priv->av.port->mad_agent,
+		      (unsigned long) cm_id_priv->msg);
+	cm_id_priv->msg = NULL;
+
+	ret = atomic_inc_and_test(&cm_id_priv->work_count);
+	if (!ret)
+		list_add_tail(&work->list, &cm_id_priv->work_list);
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+
+	if (ret)
+		cm_process_work(cm_id_priv, work);
+	else
+		cm_deref_id(cm_id_priv);
+	return 0;
+out:
+	cm_deref_id(cm_id_priv);
+	return -EINVAL;
+}
+
+static int cm_timewait_handler(struct cm_work *work)
+{
+	struct cm_timewait_info *timewait_info;
+	struct cm_id_private *cm_id_priv;
+	unsigned long flags;
+	int ret;
+
+	timewait_info = (struct cm_timewait_info *)work;
+	cm_cleanup_timewait(timewait_info);
+
+	cm_id_priv = cm_acquire_id(timewait_info->work.local_id,
+				   timewait_info->work.remote_id);
+	if (!cm_id_priv)
+		return -EINVAL;
+
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	if (cm_id_priv->id.state != IB_CM_TIMEWAIT ||
+	    cm_id_priv->remote_qpn != timewait_info->remote_qpn) {
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		goto out;
+	}
+	cm_id_priv->id.state = IB_CM_IDLE;
+	ret = atomic_inc_and_test(&cm_id_priv->work_count);
+	if (!ret)
+		list_add_tail(&work->list, &cm_id_priv->work_list);
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+
+	if (ret)
+		cm_process_work(cm_id_priv, work);
+	else
+		cm_deref_id(cm_id_priv);
+	return 0;
+out:
+	cm_deref_id(cm_id_priv);
+	return -EINVAL;
+}
+
+static void cm_format_sidr_req(struct cm_sidr_req_msg *sidr_req_msg,
+			       struct cm_id_private *cm_id_priv,
+			       struct ib_cm_sidr_req_param *param)
+{
+	cm_format_mad_hdr(&sidr_req_msg->hdr, CM_SIDR_REQ_ATTR_ID,
+			  cm_form_tid(cm_id_priv, CM_MSG_SEQUENCE_SIDR));
+	sidr_req_msg->request_id = cm_id_priv->id.local_id;
+	sidr_req_msg->pkey = param->pkey;
+	sidr_req_msg->service_id = param->service_id;
+
+	if (param->private_data && param->private_data_len)
+		memcpy(sidr_req_msg->private_data, param->private_data,
+		       param->private_data_len);
+}
+
+int ib_send_cm_sidr_req(struct ib_cm_id *cm_id,
+			struct ib_cm_sidr_req_param *param)
+{
+	struct cm_id_private *cm_id_priv;
+	struct ib_mad_send_buf *msg;
+	struct ib_send_wr *bad_send_wr;
+	unsigned long flags;
+	int ret;
+
+	if (!param->path || (param->private_data &&
+	     param->private_data_len > IB_CM_SIDR_REQ_PRIVATE_DATA_SIZE))
+		return -EINVAL;
+
+	cm_id_priv = container_of(cm_id, struct cm_id_private, id);
+	ret = cm_init_av_by_path(param->path, &cm_id_priv->av);
+	if (ret)
+		goto out;
+
+	cm_id->service_id = param->service_id;
+	cm_id->service_mask = ~0ULL;
+	cm_id_priv->timeout_ms = param->timeout_ms;
+	cm_id_priv->max_cm_retries = param->max_cm_retries;
+	ret = cm_alloc_msg(cm_id_priv, &msg);
+	if (ret)
+		goto out;
+
+	cm_format_sidr_req((struct cm_sidr_req_msg *) msg->mad, cm_id_priv,
+			   param);
+	msg->send_wr.wr.ud.timeout_ms = cm_id_priv->timeout_ms;
+	msg->context[1] = (void *) (unsigned long) IB_CM_SIDR_REQ_SENT;
+
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	if (cm_id->state == IB_CM_IDLE)
+		ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent,
+				       &msg->send_wr, &bad_send_wr);
+	else
+		ret = -EINVAL;
+
+	if (ret) {
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		cm_free_msg(msg);
+		goto out;
+	}
+	cm_id->state = IB_CM_SIDR_REQ_SENT;
+	cm_id_priv->msg = msg;
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+out:
+	return ret;
+}
+EXPORT_SYMBOL(ib_send_cm_sidr_req);
+
+static void cm_format_sidr_req_event(struct cm_work *work,
+				     struct ib_cm_id *listen_id)
+{
+	struct cm_sidr_req_msg *sidr_req_msg;
+	struct ib_cm_sidr_req_event_param *param;
+
+	sidr_req_msg = (struct cm_sidr_req_msg *)
+				work->mad_recv_wc->recv_buf.mad;
+	param = &work->cm_event.param.sidr_req_rcvd;
+	param->pkey = sidr_req_msg->pkey;
+	param->listen_id = listen_id;
+	param->device = work->port->mad_agent->device;
+	param->port = work->port->port_num;
+	work->cm_event.private_data = &sidr_req_msg->private_data;
+}
+
+static int cm_sidr_req_handler(struct cm_work *work)
+{
+	struct ib_cm_id *cm_id;
+	struct cm_id_private *cm_id_priv, *cur_cm_id_priv;
+	struct cm_sidr_req_msg *sidr_req_msg;
+	struct ib_wc *wc;
+	unsigned long flags;
+
+	cm_id = ib_create_cm_id(NULL, NULL);
+	if (IS_ERR(cm_id))
+		return PTR_ERR(cm_id);
+	cm_id_priv = container_of(cm_id, struct cm_id_private, id);
+
+	/* Record SGID/SLID and request ID for lookup. */
+	sidr_req_msg = (struct cm_sidr_req_msg *)
+				work->mad_recv_wc->recv_buf.mad;
+	wc = work->mad_recv_wc->wc;
+	cm_id_priv->av.dgid.global.subnet_prefix = wc->slid;
+	cm_id_priv->av.dgid.global.interface_id = 0;
+	cm_init_av_for_response(work->port, work->mad_recv_wc->wc,
+				&cm_id_priv->av);
+	cm_id_priv->id.remote_id = sidr_req_msg->request_id;
+	cm_id_priv->id.state = IB_CM_SIDR_REQ_RCVD;
+	cm_id_priv->tid = sidr_req_msg->hdr.tid;
+	atomic_inc(&cm_id_priv->work_count);
+
+	spin_lock_irqsave(&cm.lock, flags);
+	cur_cm_id_priv = cm_insert_remote_sidr(cm_id_priv);
+	if (cur_cm_id_priv) {
+		spin_unlock_irqrestore(&cm.lock, flags);
+		goto out; /* Duplicate message. */
+	}
+	cur_cm_id_priv = cm_find_listen(sidr_req_msg->service_id);
+	if (!cur_cm_id_priv) {
+		rb_erase(&cm_id_priv->sidr_id_node, &cm.remote_sidr_table);
+		spin_unlock_irqrestore(&cm.lock, flags);
+		/* todo: reply with no match */
+		goto out; /* No match. */
+	}
+	atomic_inc(&cur_cm_id_priv->refcount);
+	spin_unlock_irqrestore(&cm.lock, flags);
+
+	cm_id_priv->id.cm_handler = cur_cm_id_priv->id.cm_handler;
+	cm_id_priv->id.context = cur_cm_id_priv->id.context;
+	cm_id_priv->id.service_id = sidr_req_msg->service_id;
+	cm_id_priv->id.service_mask = ~0ULL;
+
+	cm_format_sidr_req_event(work, &cur_cm_id_priv->id);
+	cm_process_work(cm_id_priv, work);
+	cm_deref_id(cur_cm_id_priv);
+	return 0;
+out:
+	ib_destroy_cm_id(&cm_id_priv->id);
+	return -EINVAL;
+}
+
+static void cm_format_sidr_rep(struct cm_sidr_rep_msg *sidr_rep_msg,
+			       struct cm_id_private *cm_id_priv,
+			       struct ib_cm_sidr_rep_param *param)
+{
+	cm_format_mad_hdr(&sidr_rep_msg->hdr, CM_SIDR_REP_ATTR_ID,
+			  cm_id_priv->tid);
+	sidr_rep_msg->request_id = cm_id_priv->id.remote_id;
+	sidr_rep_msg->status = param->status;
+	cm_sidr_rep_set_qpn(sidr_rep_msg, cpu_to_be32(param->qp_num));
+	sidr_rep_msg->service_id = cm_id_priv->id.service_id;
+	sidr_rep_msg->qkey = cpu_to_be32(param->qkey);
+
+	if (param->info && param->info_length)
+		memcpy(sidr_rep_msg->info, param->info, param->info_length);
+
+	if (param->private_data && param->private_data_len)
+		memcpy(sidr_rep_msg->private_data, param->private_data,
+		       param->private_data_len);
+}
+
+int ib_send_cm_sidr_rep(struct ib_cm_id *cm_id,
+			struct ib_cm_sidr_rep_param *param)
+{
+	struct cm_id_private *cm_id_priv;
+	struct ib_mad_send_buf *msg;
+	struct ib_send_wr *bad_send_wr;
+	unsigned long flags;
+	int ret;
+
+	if ((param->info && param->info_length > IB_CM_SIDR_REP_INFO_LENGTH) ||
+	    (param->private_data &&
+	     param->private_data_len > IB_CM_SIDR_REP_PRIVATE_DATA_SIZE))
+		return -EINVAL;
+
+	cm_id_priv = container_of(cm_id, struct cm_id_private, id);
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	if (cm_id->state != IB_CM_SIDR_REQ_RCVD) {
+		ret = -EINVAL;
+		goto error;
+	}
+
+	ret = cm_alloc_msg(cm_id_priv, &msg);
+	if (ret)
+		goto error;
+
+	cm_format_sidr_rep((struct cm_sidr_rep_msg *) msg->mad, cm_id_priv,
+			   param);
+	ret = ib_post_send_mad(cm_id_priv->av.port->mad_agent,
+			       &msg->send_wr, &bad_send_wr);
+	if (ret) {
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		cm_free_msg(msg);
+		return ret;
+	}
+	cm_id->state = IB_CM_IDLE;
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+
+	spin_lock_irqsave(&cm.lock, flags);
+	rb_erase(&cm_id_priv->sidr_id_node, &cm.remote_sidr_table);
+	spin_unlock_irqrestore(&cm.lock, flags);
+	return 0;
+
+error:	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL(ib_send_cm_sidr_rep);
+
+static void cm_format_sidr_rep_event(struct cm_work *work)
+{
+	struct cm_sidr_rep_msg *sidr_rep_msg;
+	struct ib_cm_sidr_rep_event_param *param;
+
+	sidr_rep_msg = (struct cm_sidr_rep_msg *)
+				work->mad_recv_wc->recv_buf.mad;
+	param = &work->cm_event.param.sidr_rep_rcvd;
+	param->status = sidr_rep_msg->status;
+	param->qkey = be32_to_cpu(sidr_rep_msg->qkey);
+	param->qpn = be32_to_cpu(cm_sidr_rep_get_qpn(sidr_rep_msg));
+	param->info = &sidr_rep_msg->info;
+	param->info_len = sidr_rep_msg->info_length;
+	work->cm_event.private_data = &sidr_rep_msg->private_data;
+}
+
+static int cm_sidr_rep_handler(struct cm_work *work)
+{
+	struct cm_sidr_rep_msg *sidr_rep_msg;
+	struct cm_id_private *cm_id_priv;
+	unsigned long flags;
+
+	sidr_rep_msg = (struct cm_sidr_rep_msg *)
+				work->mad_recv_wc->recv_buf.mad;
+	cm_id_priv = cm_acquire_id(sidr_rep_msg->request_id, 0);
+	if (!cm_id_priv)
+		return -EINVAL; /* Unmatched reply. */
+
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	if (cm_id_priv->id.state != IB_CM_SIDR_REQ_SENT) {
+		spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+		goto out;
+	}
+	cm_id_priv->id.state = IB_CM_IDLE;
+	ib_cancel_mad(cm_id_priv->av.port->mad_agent,
+		      (unsigned long) cm_id_priv->msg);
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+
+	cm_format_sidr_rep_event(work);
+	cm_process_work(cm_id_priv, work);
+	return 0;
+out:
+	cm_deref_id(cm_id_priv);
+	return -EINVAL;
+}
+
+static void cm_process_send_error(struct ib_mad_send_buf *msg,
+				  enum ib_wc_status wc_status)
+{
+	struct cm_id_private *cm_id_priv;
+	struct ib_cm_event cm_event;
+	enum ib_cm_state state;
+	unsigned long flags;
+	int ret;
+
+	memset(&cm_event, 0, sizeof cm_event);
+	cm_id_priv = msg->context[0];
+
+	/* Discard old sends or ones without a response. */
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	state = (enum ib_cm_state) (unsigned long) msg->context[1];
+	if (msg != cm_id_priv->msg || state != cm_id_priv->id.state)
+		goto discard;
+
+	switch (state) {
+	case IB_CM_REQ_SENT:
+	case IB_CM_MRA_REQ_RCVD:
+		cm_reset_to_idle(cm_id_priv);
+		cm_event.event = IB_CM_REQ_ERROR;
+		break;
+	case IB_CM_REP_SENT:
+	case IB_CM_MRA_REP_RCVD:
+		cm_reset_to_idle(cm_id_priv);
+		cm_event.event = IB_CM_REP_ERROR;
+		break;
+	case IB_CM_DREQ_SENT:
+		cm_enter_timewait(cm_id_priv);
+		cm_event.event = IB_CM_DREQ_ERROR;
+		break;
+	case IB_CM_SIDR_REQ_SENT:
+		cm_id_priv->id.state = IB_CM_IDLE;
+		cm_event.event = IB_CM_SIDR_REQ_ERROR;
+		break;
+	default:
+		goto discard;
+	}
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+	cm_event.param.send_status = wc_status;
+
+	/* No other events can occur on the cm_id at this point. */
+	ret = cm_id_priv->id.cm_handler(&cm_id_priv->id, &cm_event);
+	cm_free_msg(msg);
+	if (ret)
+		ib_destroy_cm_id(&cm_id_priv->id);
+	return;
+discard:
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+	cm_free_msg(msg);
+}
+
+static void cm_send_handler(struct ib_mad_agent *mad_agent,
+			    struct ib_mad_send_wc *mad_send_wc)
+{
+	struct ib_mad_send_buf *msg;
+
+	msg = (struct ib_mad_send_buf *)(unsigned long)mad_send_wc->wr_id;
+
+	switch (mad_send_wc->status) {
+	case IB_WC_SUCCESS:
+	case IB_WC_WR_FLUSH_ERR:
+		cm_free_msg(msg);
+		break;
+	default:
+		if (msg->context[0] && msg->context[1])
+			cm_process_send_error(msg, mad_send_wc->status);
+		else
+			cm_free_msg(msg);
+		break;
+	}
+}
+
+static void cm_work_handler(void *data)
+{
+	struct cm_work *work = data;
+	int ret;
+
+	switch (work->cm_event.event) {
+	case IB_CM_REQ_RECEIVED:
+		ret = cm_req_handler(work);
+		break;
+	case IB_CM_MRA_RECEIVED:
+		ret = cm_mra_handler(work);
+		break;
+	case IB_CM_REJ_RECEIVED:
+		ret = cm_rej_handler(work);
+		break;
+	case IB_CM_REP_RECEIVED:
+		ret = cm_rep_handler(work);
+		break;
+	case IB_CM_RTU_RECEIVED:
+		ret = cm_rtu_handler(work);
+		break;
+	case IB_CM_USER_ESTABLISHED:
+		ret = cm_establish_handler(work);
+		break;
+	case IB_CM_DREQ_RECEIVED:
+		ret = cm_dreq_handler(work);
+		break;
+	case IB_CM_DREP_RECEIVED:
+		ret = cm_drep_handler(work);
+		break;
+	case IB_CM_SIDR_REQ_RECEIVED:
+		ret = cm_sidr_req_handler(work);
+		break;
+	case IB_CM_SIDR_REP_RECEIVED:
+		ret = cm_sidr_rep_handler(work);
+		break;
+	case IB_CM_LAP_RECEIVED:
+		ret = cm_lap_handler(work);
+		break;
+	case IB_CM_APR_RECEIVED:
+		ret = cm_apr_handler(work);
+		break;
+	case IB_CM_TIMEWAIT_EXIT:
+		ret = cm_timewait_handler(work);
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	if (ret)
+		cm_free_work(work);
+}
+
+int ib_cm_establish(struct ib_cm_id *cm_id)
+{
+	struct cm_id_private *cm_id_priv;
+	struct cm_work *work;
+	unsigned long flags;
+	int ret = 0;
+
+	work = kmalloc(sizeof *work, GFP_ATOMIC);
+	if (!work)
+		return -ENOMEM;
+
+	cm_id_priv = container_of(cm_id, struct cm_id_private, id);
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	switch (cm_id->state)
+	{
+	case IB_CM_REP_SENT:
+	case IB_CM_MRA_REP_RCVD:
+		cm_id->state = IB_CM_ESTABLISHED;
+		break;
+	case IB_CM_ESTABLISHED:
+		ret = -EISCONN;
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+
+	if (ret) {
+		kfree(work);
+		goto out;
+	}
+
+	/*
+	 * The CM worker thread may try to destroy the cm_id before it
+	 * can execute this work item.  To prevent potential deadlock,
+	 * we need to find the cm_id once we're in the context of the
+	 * worker thread, rather than holding a reference on it.
+	 */
+	INIT_WORK(&work->work, cm_work_handler, work);
+	work->local_id = cm_id->local_id;
+	work->remote_id = cm_id->remote_id;
+	work->mad_recv_wc = NULL;
+	work->cm_event.event = IB_CM_USER_ESTABLISHED;
+	queue_work(cm.wq, &work->work);
+out:
+	return ret;
+}
+EXPORT_SYMBOL(ib_cm_establish);
+
+static void cm_recv_handler(struct ib_mad_agent *mad_agent,
+			    struct ib_mad_recv_wc *mad_recv_wc)
+{
+	struct cm_work *work;
+	enum ib_cm_event_type event;
+	int paths = 0;
+
+	switch (mad_recv_wc->recv_buf.mad->mad_hdr.attr_id) {
+	case CM_REQ_ATTR_ID:
+		paths = 1 + (((struct cm_req_msg *) mad_recv_wc->recv_buf.mad)->
+						    alt_local_lid != 0);
+		event = IB_CM_REQ_RECEIVED;
+		break;
+	case CM_MRA_ATTR_ID:
+		event = IB_CM_MRA_RECEIVED;
+		break;
+	case CM_REJ_ATTR_ID:
+		event = IB_CM_REJ_RECEIVED;
+		break;
+	case CM_REP_ATTR_ID:
+		event = IB_CM_REP_RECEIVED;
+		break;
+	case CM_RTU_ATTR_ID:
+		event = IB_CM_RTU_RECEIVED;
+		break;
+	case CM_DREQ_ATTR_ID:
+		event = IB_CM_DREQ_RECEIVED;
+		break;
+	case CM_DREP_ATTR_ID:
+		event = IB_CM_DREP_RECEIVED;
+		break;
+	case CM_SIDR_REQ_ATTR_ID:
+		event = IB_CM_SIDR_REQ_RECEIVED;
+		break;
+	case CM_SIDR_REP_ATTR_ID:
+		event = IB_CM_SIDR_REP_RECEIVED;
+		break;
+	case CM_LAP_ATTR_ID:
+		paths = 1;
+		event = IB_CM_LAP_RECEIVED;
+		break;
+	case CM_APR_ATTR_ID:
+		event = IB_CM_APR_RECEIVED;
+		break;
+	default:
+		ib_free_recv_mad(mad_recv_wc);
+		return;
+	}
+
+	work = kmalloc(sizeof *work + sizeof(struct ib_sa_path_rec) * paths,
+		       GFP_KERNEL);
+	if (!work) {
+		ib_free_recv_mad(mad_recv_wc);
+		return;
+	}
+
+	INIT_WORK(&work->work, cm_work_handler, work);
+	work->cm_event.event = event;
+	work->mad_recv_wc = mad_recv_wc;
+	work->port = (struct cm_port *)mad_agent->context;
+	queue_work(cm.wq, &work->work);
+}
+
+static int cm_init_qp_init_attr(struct cm_id_private *cm_id_priv,
+				struct ib_qp_attr *qp_attr,
+				int *qp_attr_mask)
+{
+	unsigned long flags;
+	int ret;
+
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	switch (cm_id_priv->id.state) {
+	case IB_CM_REQ_SENT:
+	case IB_CM_MRA_REQ_RCVD:
+	case IB_CM_REQ_RCVD:
+	case IB_CM_MRA_REQ_SENT:
+	case IB_CM_REP_RCVD:
+	case IB_CM_MRA_REP_SENT:
+	case IB_CM_REP_SENT:
+	case IB_CM_MRA_REP_RCVD:
+	case IB_CM_ESTABLISHED:
+		*qp_attr_mask = IB_QP_STATE | IB_QP_ACCESS_FLAGS |
+				IB_QP_PKEY_INDEX | IB_QP_PORT;
+		qp_attr->qp_access_flags = IB_ACCESS_LOCAL_WRITE;
+		if (cm_id_priv->responder_resources)
+			qp_attr->qp_access_flags |= IB_ACCESS_REMOTE_WRITE |
+						    IB_ACCESS_REMOTE_READ;
+		qp_attr->pkey_index = cm_id_priv->av.pkey_index;
+		qp_attr->port_num = cm_id_priv->av.port->port_num;
+		ret = 0;
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+	return ret;
+}
+
+static int cm_init_qp_rtr_attr(struct cm_id_private *cm_id_priv,
+			       struct ib_qp_attr *qp_attr,
+			       int *qp_attr_mask)
+{
+	unsigned long flags;
+	int ret;
+
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	switch (cm_id_priv->id.state) {
+	case IB_CM_REQ_RCVD:
+	case IB_CM_MRA_REQ_SENT:
+	case IB_CM_REP_RCVD:
+	case IB_CM_MRA_REP_SENT:
+	case IB_CM_REP_SENT:
+	case IB_CM_MRA_REP_RCVD:
+	case IB_CM_ESTABLISHED:
+		*qp_attr_mask = IB_QP_STATE | IB_QP_AV | IB_QP_PATH_MTU |
+				IB_QP_DEST_QPN | IB_QP_RQ_PSN |
+				IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER;
+		qp_attr->ah_attr = cm_id_priv->av.ah_attr;
+		qp_attr->path_mtu = cm_id_priv->path_mtu;
+		qp_attr->dest_qp_num = be32_to_cpu(cm_id_priv->remote_qpn);
+		qp_attr->rq_psn = be32_to_cpu(cm_id_priv->rq_psn);
+		qp_attr->max_dest_rd_atomic = cm_id_priv->responder_resources;
+		qp_attr->min_rnr_timer = 0;
+		if (cm_id_priv->alt_av.ah_attr.dlid) {
+			*qp_attr_mask |= IB_QP_ALT_PATH;
+			qp_attr->alt_ah_attr = cm_id_priv->alt_av.ah_attr;
+		}
+		ret = 0;
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+	return ret;
+}
+
+static int cm_init_qp_rts_attr(struct cm_id_private *cm_id_priv,
+			       struct ib_qp_attr *qp_attr,
+			       int *qp_attr_mask)
+{
+	unsigned long flags;
+	int ret;
+
+	spin_lock_irqsave(&cm_id_priv->lock, flags);
+	switch (cm_id_priv->id.state) {
+	case IB_CM_REP_RCVD:
+	case IB_CM_MRA_REP_SENT:
+	case IB_CM_REP_SENT:
+	case IB_CM_MRA_REP_RCVD:
+	case IB_CM_ESTABLISHED:
+		*qp_attr_mask = IB_QP_STATE | IB_QP_TIMEOUT | IB_QP_RETRY_CNT |
+				IB_QP_RNR_RETRY | IB_QP_SQ_PSN |
+				IB_QP_MAX_QP_RD_ATOMIC;
+		qp_attr->timeout = cm_id_priv->local_ack_timeout;
+		qp_attr->retry_cnt = cm_id_priv->retry_count;
+		qp_attr->rnr_retry = cm_id_priv->rnr_retry_count;
+		qp_attr->sq_psn = be32_to_cpu(cm_id_priv->sq_psn);
+		qp_attr->max_rd_atomic = cm_id_priv->initiator_depth;
+		if (cm_id_priv->alt_av.ah_attr.dlid) {
+			*qp_attr_mask |= IB_QP_PATH_MIG_STATE;
+			qp_attr->path_mig_state = IB_MIG_REARM;
+		}
+		ret = 0;
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	spin_unlock_irqrestore(&cm_id_priv->lock, flags);
+	return ret;
+}
+
+int ib_cm_init_qp_attr(struct ib_cm_id *cm_id,
+		       struct ib_qp_attr *qp_attr,
+		       int *qp_attr_mask)
+{
+	struct cm_id_private *cm_id_priv;
+	int ret;
+
+	cm_id_priv = container_of(cm_id, struct cm_id_private, id);
+	switch (qp_attr->qp_state) {
+	case IB_QPS_INIT:
+		ret = cm_init_qp_init_attr(cm_id_priv, qp_attr, qp_attr_mask);
+		break;
+	case IB_QPS_RTR:
+		ret = cm_init_qp_rtr_attr(cm_id_priv, qp_attr, qp_attr_mask);
+		break;
+	case IB_QPS_RTS:
+		ret = cm_init_qp_rts_attr(cm_id_priv, qp_attr, qp_attr_mask);
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	return ret;
+}
+EXPORT_SYMBOL(ib_cm_init_qp_attr);
+
+static u64 cm_get_ca_guid(struct ib_device *device)
+{
+	struct ib_device_attr *device_attr;
+	u64 guid;
+	int ret;
+
+	device_attr = kmalloc(sizeof *device_attr, GFP_KERNEL);
+	if (!device_attr)
+		return 0;
+
+	ret = ib_query_device(device, device_attr);
+	guid = ret ? 0 : device_attr->node_guid;
+	kfree(device_attr);
+	return guid;
+}
+
+static void cm_add_one(struct ib_device *device)
+{
+	struct cm_device *cm_dev;
+	struct cm_port *port;
+	struct ib_mad_reg_req reg_req = {
+		.mgmt_class = IB_MGMT_CLASS_CM,
+		.mgmt_class_version = IB_CM_CLASS_VERSION
+	};
+	struct ib_port_modify port_modify = {
+		.set_port_cap_mask = IB_PORT_CM_SUP
+	};
+	unsigned long flags;
+	int ret;
+	u8 i;
+
+	cm_dev = kmalloc(sizeof(*cm_dev) + sizeof(*port) *
+			 device->phys_port_cnt, GFP_KERNEL);
+	if (!cm_dev)
+		return;
+
+	cm_dev->device = device;
+	cm_dev->ca_guid = cm_get_ca_guid(device);
+	if (!cm_dev->ca_guid)
+		goto error1;
+
+	set_bit(IB_MGMT_METHOD_SEND, reg_req.method_mask);
+	for (i = 1; i <= device->phys_port_cnt; i++) {
+		port = &cm_dev->port[i-1];
+		port->cm_dev = cm_dev;
+		port->port_num = i;
+		port->mad_agent = ib_register_mad_agent(device, i,
+							IB_QPT_GSI,
+							&reg_req,
+							0,
+							cm_send_handler,
+							cm_recv_handler,
+							port);
+		if (IS_ERR(port->mad_agent))
+			goto error2;
+
+		ret = ib_modify_port(device, i, 0, &port_modify);
+		if (ret)
+			goto error3;
+	}
+	ib_set_client_data(device, &cm_client, cm_dev);
+
+	write_lock_irqsave(&cm.device_lock, flags);
+	list_add_tail(&cm_dev->list, &cm.device_list);
+	write_unlock_irqrestore(&cm.device_lock, flags);
+	return;
+
+error3:
+	ib_unregister_mad_agent(port->mad_agent);
+error2:
+	port_modify.set_port_cap_mask = 0;
+	port_modify.clr_port_cap_mask = IB_PORT_CM_SUP;
+	while (--i) {
+		port = &cm_dev->port[i-1];
+		ib_modify_port(device, port->port_num, 0, &port_modify);
+		ib_unregister_mad_agent(port->mad_agent);
+	}
+error1:
+	kfree(cm_dev);
+}
+
+static void cm_remove_one(struct ib_device *device)
+{
+	struct cm_device *cm_dev;
+	struct cm_port *port;
+	struct ib_port_modify port_modify = {
+		.clr_port_cap_mask = IB_PORT_CM_SUP
+	};
+	unsigned long flags;
+	int i;
+
+	cm_dev = ib_get_client_data(device, &cm_client);
+	if (!cm_dev)
+		return;
+
+	write_lock_irqsave(&cm.device_lock, flags);
+	list_del(&cm_dev->list);
+	write_unlock_irqrestore(&cm.device_lock, flags);
+
+	for (i = 1; i <= device->phys_port_cnt; i++) {
+		port = &cm_dev->port[i-1];
+		ib_modify_port(device, port->port_num, 0, &port_modify);
+		ib_unregister_mad_agent(port->mad_agent);
+	}
+	kfree(cm_dev);
+}
+
+static int __init ib_cm_init(void)
+{
+	int ret;
+
+	memset(&cm, 0, sizeof cm);
+	INIT_LIST_HEAD(&cm.device_list);
+	rwlock_init(&cm.device_lock);
+	spin_lock_init(&cm.lock);
+	cm.listen_service_table = RB_ROOT;
+	cm.listen_service_id = __constant_be64_to_cpu(IB_CM_ASSIGN_SERVICE_ID);
+	cm.remote_id_table = RB_ROOT;
+	cm.remote_qp_table = RB_ROOT;
+	cm.remote_sidr_table = RB_ROOT;
+	idr_init(&cm.local_id_table);
+	idr_pre_get(&cm.local_id_table, GFP_KERNEL);
+
+	cm.wq = create_workqueue("ib_cm");
+	if (!cm.wq)
+		return -ENOMEM;
+
+	ret = ib_register_client(&cm_client);
+	if (ret)
+		goto error;
+
+	return 0;
+error:
+	destroy_workqueue(cm.wq);
+	return ret;
+}
+
+static void __exit ib_cm_cleanup(void)
+{
+	flush_workqueue(cm.wq);
+	destroy_workqueue(cm.wq);
+	ib_unregister_client(&cm_client);
+}
+
+module_init(ib_cm_init);
+module_exit(ib_cm_cleanup);
+
diff --git a/drivers/infiniband/core/cm_msgs.h b/drivers/infiniband/core/cm_msgs.h
new file mode 100644
index 00000000000..15a309a77b2
--- /dev/null
+++ b/drivers/infiniband/core/cm_msgs.h
@@ -0,0 +1,819 @@
+/*
+ * Copyright (c) 2004 Intel Corporation.  All rights reserved.
+ * Copyright (c) 2004 Topspin Corporation.  All rights reserved.
+ * Copyright (c) 2004 Voltaire Corporation.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING the madirectory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use source and binary forms, with or
+ *     withmodification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retathe above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHWARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS THE
+ * SOFTWARE.
+ */
+#if !defined(CM_MSGS_H)
+#define CM_MSGS_H
+
+#include <ib_mad.h>
+
+/*
+ * Parameters to routines below should be in network-byte order, and values
+ * are returned in network-byte order.
+ */
+
+#define IB_CM_CLASS_VERSION	2 /* IB specification 1.2 */
+
+enum cm_msg_attr_id {
+	CM_REQ_ATTR_ID	    = __constant_htons(0x0010),
+	CM_MRA_ATTR_ID	    = __constant_htons(0x0011),
+	CM_REJ_ATTR_ID	    = __constant_htons(0x0012),
+	CM_REP_ATTR_ID	    = __constant_htons(0x0013),
+	CM_RTU_ATTR_ID	    = __constant_htons(0x0014),
+	CM_DREQ_ATTR_ID	    = __constant_htons(0x0015),
+	CM_DREP_ATTR_ID	    = __constant_htons(0x0016),
+	CM_SIDR_REQ_ATTR_ID = __constant_htons(0x0017),
+	CM_SIDR_REP_ATTR_ID = __constant_htons(0x0018),
+	CM_LAP_ATTR_ID      = __constant_htons(0x0019),
+	CM_APR_ATTR_ID      = __constant_htons(0x001A)
+};
+
+enum cm_msg_sequence {
+	CM_MSG_SEQUENCE_REQ,
+	CM_MSG_SEQUENCE_LAP,
+	CM_MSG_SEQUENCE_DREQ,
+	CM_MSG_SEQUENCE_SIDR
+};
+
+struct cm_req_msg {
+	struct ib_mad_hdr hdr;
+
+	u32 local_comm_id;
+	u32 rsvd4;
+	u64 service_id;
+	u64 local_ca_guid;
+	u32 rsvd24;
+	u32 local_qkey;
+	/* local QPN:24, responder resources:8 */
+	u32 offset32;
+	/* local EECN:24, initiator depth:8 */
+	u32 offset36;
+	/*
+	 * remote EECN:24, remote CM response timeout:5,
+	 * transport service type:2, end-to-end flow control:1
+	 */
+	u32 offset40;
+	/* starting PSN:24, local CM response timeout:5, retry count:3 */
+	u32 offset44;
+	u16 pkey;
+	/* path MTU:4, RDC exists:1, RNR retry count:3. */
+	u8 offset50;
+	/* max CM Retries:4, SRQ:1, rsvd:3 */
+	u8 offset51;
+
+	u16 primary_local_lid;
+	u16 primary_remote_lid;
+	union ib_gid primary_local_gid;
+	union ib_gid primary_remote_gid;
+	/* flow label:20, rsvd:6, packet rate:6 */
+	u32 primary_offset88;
+	u8 primary_traffic_class;
+	u8 primary_hop_limit;
+	/* SL:4, subnet local:1, rsvd:3 */
+	u8 primary_offset94;
+	/* local ACK timeout:5, rsvd:3 */
+	u8 primary_offset95;
+
+	u16 alt_local_lid;
+	u16 alt_remote_lid;
+	union ib_gid alt_local_gid;
+	union ib_gid alt_remote_gid;
+	/* flow label:20, rsvd:6, packet rate:6 */
+	u32 alt_offset132;
+	u8 alt_traffic_class;
+	u8 alt_hop_limit;
+	/* SL:4, subnet local:1, rsvd:3 */
+	u8 alt_offset138;
+	/* local ACK timeout:5, rsvd:3 */
+	u8 alt_offset139;
+
+	u8 private_data[IB_CM_REQ_PRIVATE_DATA_SIZE];
+
+} __attribute__ ((packed));
+
+static inline u32 cm_req_get_local_qpn(struct cm_req_msg *req_msg)
+{
+	return cpu_to_be32(be32_to_cpu(req_msg->offset32) >> 8);
+}
+
+static inline void cm_req_set_local_qpn(struct cm_req_msg *req_msg, u32 qpn)
+{
+	req_msg->offset32 = cpu_to_be32((be32_to_cpu(qpn) << 8) |
+					 (be32_to_cpu(req_msg->offset32) &
+					  0x000000FF));
+}
+
+static inline u8 cm_req_get_resp_res(struct cm_req_msg *req_msg)
+{
+	return (u8) be32_to_cpu(req_msg->offset32);
+}
+
+static inline void cm_req_set_resp_res(struct cm_req_msg *req_msg, u8 resp_res)
+{
+	req_msg->offset32 = cpu_to_be32(resp_res |
+					(be32_to_cpu(req_msg->offset32) &
+					 0xFFFFFF00));
+}
+
+static inline u8 cm_req_get_init_depth(struct cm_req_msg *req_msg)
+{
+	return (u8) be32_to_cpu(req_msg->offset36);
+}
+
+static inline void cm_req_set_init_depth(struct cm_req_msg *req_msg,
+					 u8 init_depth)
+{
+	req_msg->offset36 = cpu_to_be32(init_depth |
+					(be32_to_cpu(req_msg->offset36) &
+					 0xFFFFFF00));
+}
+
+static inline u8 cm_req_get_remote_resp_timeout(struct cm_req_msg *req_msg)
+{
+	return (u8) ((be32_to_cpu(req_msg->offset40) & 0xF8) >> 3);
+}
+
+static inline void cm_req_set_remote_resp_timeout(struct cm_req_msg *req_msg,
+						  u8 resp_timeout)
+{
+	req_msg->offset40 = cpu_to_be32((resp_timeout << 3) |
+					 (be32_to_cpu(req_msg->offset40) &
+					  0xFFFFFF07));
+}
+
+static inline enum ib_qp_type cm_req_get_qp_type(struct cm_req_msg *req_msg)
+{
+	u8 transport_type = (u8) (be32_to_cpu(req_msg->offset40) & 0x06) >> 1;
+	switch(transport_type) {
+	case 0: return IB_QPT_RC;
+	case 1: return IB_QPT_UC;
+	default: return 0;
+	}
+}
+
+static inline void cm_req_set_qp_type(struct cm_req_msg *req_msg,
+				      enum ib_qp_type qp_type)
+{
+	switch(qp_type) {
+	case IB_QPT_UC:
+		req_msg->offset40 = cpu_to_be32((be32_to_cpu(
+						  req_msg->offset40) &
+						   0xFFFFFFF9) | 0x2);
+	default:
+		req_msg->offset40 = cpu_to_be32(be32_to_cpu(
+						 req_msg->offset40) &
+						  0xFFFFFFF9);
+	}
+}
+
+static inline u8 cm_req_get_flow_ctrl(struct cm_req_msg *req_msg)
+{
+	return be32_to_cpu(req_msg->offset40) & 0x1;
+}
+
+static inline void cm_req_set_flow_ctrl(struct cm_req_msg *req_msg,
+					u8 flow_ctrl)
+{
+	req_msg->offset40 = cpu_to_be32((flow_ctrl & 0x1) |
+					 (be32_to_cpu(req_msg->offset40) &
+					  0xFFFFFFFE));
+}
+
+static inline u32 cm_req_get_starting_psn(struct cm_req_msg *req_msg)
+{
+	return cpu_to_be32(be32_to_cpu(req_msg->offset44) >> 8);
+}
+
+static inline void cm_req_set_starting_psn(struct cm_req_msg *req_msg,
+					   u32 starting_psn)
+{
+	req_msg->offset44 = cpu_to_be32((be32_to_cpu(starting_psn) << 8) |
+			    (be32_to_cpu(req_msg->offset44) & 0x000000FF));
+}
+
+static inline u8 cm_req_get_local_resp_timeout(struct cm_req_msg *req_msg)
+{
+	return (u8) ((be32_to_cpu(req_msg->offset44) & 0xF8) >> 3);
+}
+
+static inline void cm_req_set_local_resp_timeout(struct cm_req_msg *req_msg,
+						 u8 resp_timeout)
+{
+	req_msg->offset44 = cpu_to_be32((resp_timeout << 3) |
+			    (be32_to_cpu(req_msg->offset44) & 0xFFFFFF07));
+}
+
+static inline u8 cm_req_get_retry_count(struct cm_req_msg *req_msg)
+{
+	return (u8) (be32_to_cpu(req_msg->offset44) & 0x7);
+}
+
+static inline void cm_req_set_retry_count(struct cm_req_msg *req_msg,
+					  u8 retry_count)
+{
+	req_msg->offset44 = cpu_to_be32((retry_count & 0x7) |
+			    (be32_to_cpu(req_msg->offset44) & 0xFFFFFFF8));
+}
+
+static inline u8 cm_req_get_path_mtu(struct cm_req_msg *req_msg)
+{
+	return req_msg->offset50 >> 4;
+}
+
+static inline void cm_req_set_path_mtu(struct cm_req_msg *req_msg, u8 path_mtu)
+{
+	req_msg->offset50 = (u8) ((req_msg->offset50 & 0xF) | (path_mtu << 4));
+}
+
+static inline u8 cm_req_get_rnr_retry_count(struct cm_req_msg *req_msg)
+{
+	return req_msg->offset50 & 0x7;
+}
+
+static inline void cm_req_set_rnr_retry_count(struct cm_req_msg *req_msg,
+					      u8 rnr_retry_count)
+{
+	req_msg->offset50 = (u8) ((req_msg->offset50 & 0xF8) |
+				  (rnr_retry_count & 0x7));
+}
+
+static inline u8 cm_req_get_max_cm_retries(struct cm_req_msg *req_msg)
+{
+	return req_msg->offset51 >> 4;
+}
+
+static inline void cm_req_set_max_cm_retries(struct cm_req_msg *req_msg,
+					     u8 retries)
+{
+	req_msg->offset51 = (u8) ((req_msg->offset51 & 0xF) | (retries << 4));
+}
+
+static inline u8 cm_req_get_srq(struct cm_req_msg *req_msg)
+{
+	return (req_msg->offset51 & 0x8) >> 3;
+}
+
+static inline void cm_req_set_srq(struct cm_req_msg *req_msg, u8 srq)
+{
+	req_msg->offset51 = (u8) ((req_msg->offset51 & 0xF7) |
+				  ((srq & 0x1) << 3));
+}
+
+static inline u32 cm_req_get_primary_flow_label(struct cm_req_msg *req_msg)
+{
+	return cpu_to_be32((be32_to_cpu(req_msg->primary_offset88) >> 12));
+}
+
+static inline void cm_req_set_primary_flow_label(struct cm_req_msg *req_msg,
+						 u32 flow_label)
+{
+	req_msg->primary_offset88 = cpu_to_be32(
+				    (be32_to_cpu(req_msg->primary_offset88) &
+				     0x00000FFF) |
+				     (be32_to_cpu(flow_label) << 12));
+}
+
+static inline u8 cm_req_get_primary_packet_rate(struct cm_req_msg *req_msg)
+{
+	return (u8) (be32_to_cpu(req_msg->primary_offset88) & 0x3F);
+}
+
+static inline void cm_req_set_primary_packet_rate(struct cm_req_msg *req_msg,
+						  u8 rate)
+{
+	req_msg->primary_offset88 = cpu_to_be32(
+				    (be32_to_cpu(req_msg->primary_offset88) &
+				     0xFFFFFFC0) | (rate & 0x3F));
+}
+
+static inline u8 cm_req_get_primary_sl(struct cm_req_msg *req_msg)
+{
+	return (u8) (req_msg->primary_offset94 >> 4);
+}
+
+static inline void cm_req_set_primary_sl(struct cm_req_msg *req_msg, u8 sl)
+{
+	req_msg->primary_offset94 = (u8) ((req_msg->primary_offset94 & 0x0F) |
+					  (sl << 4));
+}
+
+static inline u8 cm_req_get_primary_subnet_local(struct cm_req_msg *req_msg)
+{
+	return (u8) ((req_msg->primary_offset94 & 0x08) >> 3);
+}
+
+static inline void cm_req_set_primary_subnet_local(struct cm_req_msg *req_msg,
+						   u8 subnet_local)
+{
+	req_msg->primary_offset94 = (u8) ((req_msg->primary_offset94 & 0xF7) |
+					  ((subnet_local & 0x1) << 3));
+}
+
+static inline u8 cm_req_get_primary_local_ack_timeout(struct cm_req_msg *req_msg)
+{
+	return (u8) (req_msg->primary_offset95 >> 3);
+}
+
+static inline void cm_req_set_primary_local_ack_timeout(struct cm_req_msg *req_msg,
+							u8 local_ack_timeout)
+{
+	req_msg->primary_offset95 = (u8) ((req_msg->primary_offset95 & 0x07) |
+					  (local_ack_timeout << 3));
+}
+
+static inline u32 cm_req_get_alt_flow_label(struct cm_req_msg *req_msg)
+{
+	return cpu_to_be32((be32_to_cpu(req_msg->alt_offset132) >> 12));
+}
+
+static inline void cm_req_set_alt_flow_label(struct cm_req_msg *req_msg,
+					     u32 flow_label)
+{
+	req_msg->alt_offset132 = cpu_to_be32(
+				 (be32_to_cpu(req_msg->alt_offset132) &
+				  0x00000FFF) |
+				  (be32_to_cpu(flow_label) << 12));
+}
+
+static inline u8 cm_req_get_alt_packet_rate(struct cm_req_msg *req_msg)
+{
+	return (u8) (be32_to_cpu(req_msg->alt_offset132) & 0x3F);
+}
+
+static inline void cm_req_set_alt_packet_rate(struct cm_req_msg *req_msg,
+					      u8 rate)
+{
+	req_msg->alt_offset132 = cpu_to_be32(
+				 (be32_to_cpu(req_msg->alt_offset132) &
+				  0xFFFFFFC0) | (rate & 0x3F));
+}
+
+static inline u8 cm_req_get_alt_sl(struct cm_req_msg *req_msg)
+{
+	return (u8) (req_msg->alt_offset138 >> 4);
+}
+
+static inline void cm_req_set_alt_sl(struct cm_req_msg *req_msg, u8 sl)
+{
+	req_msg->alt_offset138 = (u8) ((req_msg->alt_offset138 & 0x0F) |
+				       (sl << 4));
+}
+
+static inline u8 cm_req_get_alt_subnet_local(struct cm_req_msg *req_msg)
+{
+	return (u8) ((req_msg->alt_offset138 & 0x08) >> 3);
+}
+
+static inline void cm_req_set_alt_subnet_local(struct cm_req_msg *req_msg,
+					       u8 subnet_local)
+{
+	req_msg->alt_offset138 = (u8) ((req_msg->alt_offset138 & 0xF7) |
+				       ((subnet_local & 0x1) << 3));
+}
+
+static inline u8 cm_req_get_alt_local_ack_timeout(struct cm_req_msg *req_msg)
+{
+	return (u8) (req_msg->alt_offset139 >> 3);
+}
+
+static inline void cm_req_set_alt_local_ack_timeout(struct cm_req_msg *req_msg,
+						    u8 local_ack_timeout)
+{
+	req_msg->alt_offset139 = (u8) ((req_msg->alt_offset139 & 0x07) |
+				       (local_ack_timeout << 3));
+}
+
+/* Message REJected or MRAed */
+enum cm_msg_response {
+	CM_MSG_RESPONSE_REQ = 0x0,
+	CM_MSG_RESPONSE_REP = 0x1,
+	CM_MSG_RESPONSE_OTHER = 0x2
+};
+
+ struct cm_mra_msg {
+	struct ib_mad_hdr hdr;
+
+	u32 local_comm_id;
+	u32 remote_comm_id;
+	/* message MRAed:2, rsvd:6 */
+	u8 offset8;
+	/* service timeout:5, rsvd:3 */
+	u8 offset9;
+
+	u8 private_data[IB_CM_MRA_PRIVATE_DATA_SIZE];
+
+} __attribute__ ((packed));
+
+static inline u8 cm_mra_get_msg_mraed(struct cm_mra_msg *mra_msg)
+{
+	return (u8) (mra_msg->offset8 >> 6);
+}
+
+static inline void cm_mra_set_msg_mraed(struct cm_mra_msg *mra_msg, u8 msg)
+{
+	mra_msg->offset8 = (u8) ((mra_msg->offset8 & 0x3F) | (msg << 6));
+}
+
+static inline u8 cm_mra_get_service_timeout(struct cm_mra_msg *mra_msg)
+{
+	return (u8) (mra_msg->offset9 >> 3);
+}
+
+static inline void cm_mra_set_service_timeout(struct cm_mra_msg *mra_msg,
+					      u8 service_timeout)
+{
+	mra_msg->offset9 = (u8) ((mra_msg->offset9 & 0x07) |
+				 (service_timeout << 3));
+}
+
+struct cm_rej_msg {
+	struct ib_mad_hdr hdr;
+
+	u32 local_comm_id;
+	u32 remote_comm_id;
+	/* message REJected:2, rsvd:6 */
+	u8 offset8;
+	/* reject info length:7, rsvd:1. */
+	u8 offset9;
+	u16 reason;
+	u8 ari[IB_CM_REJ_ARI_LENGTH];
+
+	u8 private_data[IB_CM_REJ_PRIVATE_DATA_SIZE];
+
+} __attribute__ ((packed));
+
+static inline u8 cm_rej_get_msg_rejected(struct cm_rej_msg *rej_msg)
+{
+	return (u8) (rej_msg->offset8 >> 6);
+}
+
+static inline void cm_rej_set_msg_rejected(struct cm_rej_msg *rej_msg, u8 msg)
+{
+	rej_msg->offset8 = (u8) ((rej_msg->offset8 & 0x3F) | (msg << 6));
+}
+
+static inline u8 cm_rej_get_reject_info_len(struct cm_rej_msg *rej_msg)
+{
+	return (u8) (rej_msg->offset9 >> 1);
+}
+
+static inline void cm_rej_set_reject_info_len(struct cm_rej_msg *rej_msg,
+					      u8 len)
+{
+	rej_msg->offset9 = (u8) ((rej_msg->offset9 & 0x1) | (len << 1));
+}
+
+struct cm_rep_msg {
+	struct ib_mad_hdr hdr;
+
+	u32 local_comm_id;
+	u32 remote_comm_id;
+	u32 local_qkey;
+	/* local QPN:24, rsvd:8 */
+	u32 offset12;
+	/* local EECN:24, rsvd:8 */
+	u32 offset16;
+	/* starting PSN:24 rsvd:8 */
+	u32 offset20;
+	u8 resp_resources;
+	u8 initiator_depth;
+	/* target ACK delay:5, failover accepted:2, end-to-end flow control:1 */
+	u8 offset26;
+	/* RNR retry count:3, SRQ:1, rsvd:5 */
+	u8 offset27;
+	u64 local_ca_guid;
+
+	u8 private_data[IB_CM_REP_PRIVATE_DATA_SIZE];
+
+} __attribute__ ((packed));
+
+static inline u32 cm_rep_get_local_qpn(struct cm_rep_msg *rep_msg)
+{
+	return cpu_to_be32(be32_to_cpu(rep_msg->offset12) >> 8);
+}
+
+static inline void cm_rep_set_local_qpn(struct cm_rep_msg *rep_msg, u32 qpn)
+{
+	rep_msg->offset12 = cpu_to_be32((be32_to_cpu(qpn) << 8) |
+			    (be32_to_cpu(rep_msg->offset12) & 0x000000FF));
+}
+
+static inline u32 cm_rep_get_starting_psn(struct cm_rep_msg *rep_msg)
+{
+	return cpu_to_be32(be32_to_cpu(rep_msg->offset20) >> 8);
+}
+
+static inline void cm_rep_set_starting_psn(struct cm_rep_msg *rep_msg,
+					   u32 starting_psn)
+{
+	rep_msg->offset20 = cpu_to_be32((be32_to_cpu(starting_psn) << 8) |
+			    (be32_to_cpu(rep_msg->offset20) & 0x000000FF));
+}
+
+static inline u8 cm_rep_get_target_ack_delay(struct cm_rep_msg *rep_msg)
+{
+	return (u8) (rep_msg->offset26 >> 3);
+}
+
+static inline void cm_rep_set_target_ack_delay(struct cm_rep_msg *rep_msg,
+					       u8 target_ack_delay)
+{
+	rep_msg->offset26 = (u8) ((rep_msg->offset26 & 0x07) |
+				  (target_ack_delay << 3));
+}
+
+static inline u8 cm_rep_get_failover(struct cm_rep_msg *rep_msg)
+{
+	return (u8) ((rep_msg->offset26 & 0x06) >> 1);
+}
+
+static inline void cm_rep_set_failover(struct cm_rep_msg *rep_msg, u8 failover)
+{
+	rep_msg->offset26 = (u8) ((rep_msg->offset26 & 0xF9) |
+				  ((failover & 0x3) << 1));
+}
+
+static inline u8 cm_rep_get_flow_ctrl(struct cm_rep_msg *rep_msg)
+{
+	return (u8) (rep_msg->offset26 & 0x01);
+}
+
+static inline void cm_rep_set_flow_ctrl(struct cm_rep_msg *rep_msg,
+					    u8 flow_ctrl)
+{
+	rep_msg->offset26 = (u8) ((rep_msg->offset26 & 0xFE) |
+				  (flow_ctrl & 0x1));
+}
+
+static inline u8 cm_rep_get_rnr_retry_count(struct cm_rep_msg *rep_msg)
+{
+	return (u8) (rep_msg->offset27 >> 5);
+}
+
+static inline void cm_rep_set_rnr_retry_count(struct cm_rep_msg *rep_msg,
+					      u8 rnr_retry_count)
+{
+	rep_msg->offset27 = (u8) ((rep_msg->offset27 & 0x1F) |
+				  (rnr_retry_count << 5));
+}
+
+static inline u8 cm_rep_get_srq(struct cm_rep_msg *rep_msg)
+{
+	return (u8) ((rep_msg->offset27 >> 4) & 0x1);
+}
+
+static inline void cm_rep_set_srq(struct cm_rep_msg *rep_msg, u8 srq)
+{
+	rep_msg->offset27 = (u8) ((rep_msg->offset27 & 0xEF) |
+				  ((srq & 0x1) << 4));
+}
+
+struct cm_rtu_msg {
+	struct ib_mad_hdr hdr;
+
+	u32 local_comm_id;
+	u32 remote_comm_id;
+
+	u8 private_data[IB_CM_RTU_PRIVATE_DATA_SIZE];
+
+} __attribute__ ((packed));
+
+struct cm_dreq_msg {
+	struct ib_mad_hdr hdr;
+
+	u32 local_comm_id;
+	u32 remote_comm_id;
+	/* remote QPN/EECN:24, rsvd:8 */
+	u32 offset8;
+
+	u8 private_data[IB_CM_DREQ_PRIVATE_DATA_SIZE];
+
+} __attribute__ ((packed));
+
+static inline u32 cm_dreq_get_remote_qpn(struct cm_dreq_msg *dreq_msg)
+{
+	return cpu_to_be32(be32_to_cpu(dreq_msg->offset8) >> 8);
+}
+
+static inline void cm_dreq_set_remote_qpn(struct cm_dreq_msg *dreq_msg, u32 qpn)
+{
+	dreq_msg->offset8 = cpu_to_be32((be32_to_cpu(qpn) << 8) |
+			    (be32_to_cpu(dreq_msg->offset8) & 0x000000FF));
+}
+
+struct cm_drep_msg {
+	struct ib_mad_hdr hdr;
+
+	u32 local_comm_id;
+	u32 remote_comm_id;
+
+	u8 private_data[IB_CM_DREP_PRIVATE_DATA_SIZE];
+
+} __attribute__ ((packed));
+
+struct cm_lap_msg {
+	struct ib_mad_hdr hdr;
+
+	u32 local_comm_id;
+	u32 remote_comm_id;
+
+	u32 rsvd8;
+	/* remote QPN/EECN:24, remote CM response timeout:5, rsvd:3 */
+	u32 offset12;
+	u32 rsvd16;
+
+	u16 alt_local_lid;
+	u16 alt_remote_lid;
+	union ib_gid alt_local_gid;
+	union ib_gid alt_remote_gid;
+	/* flow label:20, rsvd:4, traffic class:8 */
+	u32 offset56;
+	u8 alt_hop_limit;
+	/* rsvd:2, packet rate:6 */
+	uint8_t offset61;
+	/* SL:4, subnet local:1, rsvd:3 */
+	uint8_t offset62;
+	/* local ACK timeout:5, rsvd:3 */
+	uint8_t offset63;
+
+	u8 private_data[IB_CM_LAP_PRIVATE_DATA_SIZE];
+} __attribute__  ((packed));
+
+static inline u32 cm_lap_get_remote_qpn(struct cm_lap_msg *lap_msg)
+{
+	return cpu_to_be32(be32_to_cpu(lap_msg->offset12) >> 8);
+}
+
+static inline void cm_lap_set_remote_qpn(struct cm_lap_msg *lap_msg, u32 qpn)
+{
+	lap_msg->offset12 = cpu_to_be32((be32_to_cpu(qpn) << 8) |
+					 (be32_to_cpu(lap_msg->offset12) &
+					  0x000000FF));
+}
+
+static inline u8 cm_lap_get_remote_resp_timeout(struct cm_lap_msg *lap_msg)
+{
+	return (u8) ((be32_to_cpu(lap_msg->offset12) & 0xF8) >> 3);
+}
+
+static inline void cm_lap_set_remote_resp_timeout(struct cm_lap_msg *lap_msg,
+						  u8 resp_timeout)
+{
+	lap_msg->offset12 = cpu_to_be32((resp_timeout << 3) |
+					 (be32_to_cpu(lap_msg->offset12) &
+					  0xFFFFFF07));
+}
+
+static inline u32 cm_lap_get_flow_label(struct cm_lap_msg *lap_msg)
+{
+	return be32_to_cpu(lap_msg->offset56) >> 12;
+}
+
+static inline void cm_lap_set_flow_label(struct cm_lap_msg *lap_msg,
+					 u32 flow_label)
+{
+	lap_msg->offset56 = cpu_to_be32((flow_label << 12) |
+					 (be32_to_cpu(lap_msg->offset56) &
+					  0x00000FFF));
+}
+
+static inline u8 cm_lap_get_traffic_class(struct cm_lap_msg *lap_msg)
+{
+	return (u8) be32_to_cpu(lap_msg->offset56);
+}
+
+static inline void cm_lap_set_traffic_class(struct cm_lap_msg *lap_msg,
+					    u8 traffic_class)
+{
+	lap_msg->offset56 = cpu_to_be32(traffic_class |
+					 (be32_to_cpu(lap_msg->offset56) &
+					  0xFFFFFF00));
+}
+
+static inline u8 cm_lap_get_packet_rate(struct cm_lap_msg *lap_msg)
+{
+	return lap_msg->offset61 & 0x3F;
+}
+
+static inline void cm_lap_set_packet_rate(struct cm_lap_msg *lap_msg,
+					  u8 packet_rate)
+{
+	lap_msg->offset61 = (packet_rate & 0x3F) | (lap_msg->offset61 & 0xC0);
+}
+
+static inline u8 cm_lap_get_sl(struct cm_lap_msg *lap_msg)
+{
+	return lap_msg->offset62 >> 4;
+}
+
+static inline void cm_lap_set_sl(struct cm_lap_msg *lap_msg, u8 sl)
+{
+	lap_msg->offset62 = (sl << 4) | (lap_msg->offset62 & 0x0F);
+}
+
+static inline u8 cm_lap_get_subnet_local(struct cm_lap_msg *lap_msg)
+{
+	return (lap_msg->offset62 >> 3) & 0x1;
+}
+
+static inline void cm_lap_set_subnet_local(struct cm_lap_msg *lap_msg,
+					   u8 subnet_local)
+{
+	lap_msg->offset62 = ((subnet_local & 0x1) << 3) |
+			     (lap_msg->offset61 & 0xF7);
+}
+static inline u8 cm_lap_get_local_ack_timeout(struct cm_lap_msg *lap_msg)
+{
+	return lap_msg->offset63 >> 3;
+}
+
+static inline void cm_lap_set_local_ack_timeout(struct cm_lap_msg *lap_msg,
+						u8 local_ack_timeout)
+{
+	lap_msg->offset63 = (local_ack_timeout << 3) |
+			    (lap_msg->offset63 & 0x07);
+}
+
+struct cm_apr_msg {
+	struct ib_mad_hdr hdr;
+
+	u32 local_comm_id;
+	u32 remote_comm_id;
+
+	u8 info_length;
+	u8 ap_status;
+	u8 info[IB_CM_APR_INFO_LENGTH];
+
+	u8 private_data[IB_CM_APR_PRIVATE_DATA_SIZE];
+} __attribute__ ((packed));
+
+struct cm_sidr_req_msg {
+	struct ib_mad_hdr hdr;
+
+	u32 request_id;
+	u16 pkey;
+	u16 rsvd;
+	u64 service_id;
+
+	u8 private_data[IB_CM_SIDR_REQ_PRIVATE_DATA_SIZE];
+} __attribute__ ((packed));
+
+struct cm_sidr_rep_msg {
+	struct ib_mad_hdr hdr;
+
+	u32 request_id;
+	u8 status;
+	u8 info_length;
+	u16 rsvd;
+	/* QPN:24, rsvd:8 */
+	u32 offset8;
+	u64 service_id;
+	u32 qkey;
+	u8 info[IB_CM_SIDR_REP_INFO_LENGTH];
+
+	u8 private_data[IB_CM_SIDR_REP_PRIVATE_DATA_SIZE];
+} __attribute__ ((packed));
+
+static inline u32 cm_sidr_rep_get_qpn(struct cm_sidr_rep_msg *sidr_rep_msg)
+{
+	return cpu_to_be32(be32_to_cpu(sidr_rep_msg->offset8) >> 8);
+}
+
+static inline void cm_sidr_rep_set_qpn(struct cm_sidr_rep_msg *sidr_rep_msg,
+				       u32 qpn)
+{
+	sidr_rep_msg->offset8 = cpu_to_be32((be32_to_cpu(qpn) << 8) |
+					(be32_to_cpu(sidr_rep_msg->offset8) &
+					 0x000000FF));
+}
+
+#endif /* CM_MSGS_H */
diff --git a/drivers/infiniband/core/fmr_pool.c b/drivers/infiniband/core/fmr_pool.c
index 328feae2a5b..7763b31abba 100644
--- a/drivers/infiniband/core/fmr_pool.c
+++ b/drivers/infiniband/core/fmr_pool.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
+ * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
@@ -29,7 +30,7 @@
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
  *
- * $Id: fmr_pool.c 1349 2004-12-16 21:09:43Z roland $
+ * $Id: fmr_pool.c 2730 2005-06-28 16:43:03Z sean.hefty $
  */
 
 #include <linux/errno.h>
@@ -329,7 +330,7 @@ EXPORT_SYMBOL(ib_create_fmr_pool);
  *
  * Destroy an FMR pool and free all associated resources.
  */
-int ib_destroy_fmr_pool(struct ib_fmr_pool *pool)
+void ib_destroy_fmr_pool(struct ib_fmr_pool *pool)
 {
 	struct ib_pool_fmr *fmr;
 	struct ib_pool_fmr *tmp;
@@ -352,8 +353,6 @@ int ib_destroy_fmr_pool(struct ib_fmr_pool *pool)
 
 	kfree(pool->cache_bucket);
 	kfree(pool);
-
-	return 0;
 }
 EXPORT_SYMBOL(ib_destroy_fmr_pool);
 
diff --git a/drivers/infiniband/core/mad.c b/drivers/infiniband/core/mad.c
index 23628c622a5..b97e210ce9c 100644
--- a/drivers/infiniband/core/mad.c
+++ b/drivers/infiniband/core/mad.c
@@ -1,5 +1,7 @@
 /*
  * Copyright (c) 2004, 2005 Voltaire, Inc. All rights reserved.
+ * Copyright (c) 2005 Intel Corporation.  All rights reserved.
+ * Copyright (c) 2005 Mellanox Technologies Ltd.  All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
@@ -29,12 +31,12 @@
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
  *
- * $Id: mad.c 1389 2004-12-27 22:56:47Z roland $
+ * $Id: mad.c 2817 2005-07-07 11:29:26Z halr $
  */
-
 #include <linux/dma-mapping.h>
 
 #include "mad_priv.h"
+#include "mad_rmpp.h"
 #include "smi.h"
 #include "agent.h"
 
@@ -45,6 +47,7 @@ MODULE_AUTHOR("Sean Hefty");
 
 
 kmem_cache_t *ib_mad_cache;
+
 static struct list_head ib_mad_port_list;
 static u32 ib_mad_client_id = 0;
 
@@ -58,16 +61,12 @@ static int method_in_use(struct ib_mad_mgmt_method_table **method,
 static void remove_mad_reg_req(struct ib_mad_agent_private *priv);
 static struct ib_mad_agent_private *find_mad_agent(
 					struct ib_mad_port_private *port_priv,
-					struct ib_mad *mad, int solicited);
+					struct ib_mad *mad);
 static int ib_mad_post_receive_mads(struct ib_mad_qp_info *qp_info,
 				    struct ib_mad_private *mad);
 static void cancel_mads(struct ib_mad_agent_private *mad_agent_priv);
-static void ib_mad_complete_send_wr(struct ib_mad_send_wr_private *mad_send_wr,
-				    struct ib_mad_send_wc *mad_send_wc);
 static void timeout_sends(void *data);
-static void cancel_sends(void *data);
 static void local_completions(void *data);
-static int solicited_mad(struct ib_mad *mad);
 static int add_nonoui_reg_req(struct ib_mad_reg_req *mad_reg_req,
 			      struct ib_mad_agent_private *agent_priv,
 			      u8 mgmt_class);
@@ -197,8 +196,8 @@ struct ib_mad_agent *ib_register_mad_agent(struct ib_device *device,
 	if (qpn == -1)
 		goto error1;
 
-	if (rmpp_version)
-		goto error1;	/* XXX: until RMPP implemented */
+	if (rmpp_version && rmpp_version != IB_MGMT_RMPP_VERSION)
+		goto error1;
 
 	/* Validate MAD registration request if supplied */
 	if (mad_reg_req) {
@@ -261,22 +260,29 @@ struct ib_mad_agent *ib_register_mad_agent(struct ib_device *device,
 		ret = ERR_PTR(-ENOMEM);
 		goto error1;
 	}
+	memset(mad_agent_priv, 0, sizeof *mad_agent_priv);
+
+	mad_agent_priv->agent.mr = ib_get_dma_mr(port_priv->qp_info[qpn].qp->pd,
+						 IB_ACCESS_LOCAL_WRITE);
+	if (IS_ERR(mad_agent_priv->agent.mr)) {
+		ret = ERR_PTR(-ENOMEM);
+		goto error2;
+	}
 
 	if (mad_reg_req) {
 		reg_req = kmalloc(sizeof *reg_req, GFP_KERNEL);
 		if (!reg_req) {
 			ret = ERR_PTR(-ENOMEM);
-			goto error2;
+			goto error3;
 		}
 		/* Make a copy of the MAD registration request */
 		memcpy(reg_req, mad_reg_req, sizeof *reg_req);
 	}
 
 	/* Now, fill in the various structures */
-	memset(mad_agent_priv, 0, sizeof *mad_agent_priv);
 	mad_agent_priv->qp_info = &port_priv->qp_info[qpn];
 	mad_agent_priv->reg_req = reg_req;
-	mad_agent_priv->rmpp_version = rmpp_version;
+	mad_agent_priv->agent.rmpp_version = rmpp_version;
 	mad_agent_priv->agent.device = device;
 	mad_agent_priv->agent.recv_handler = recv_handler;
 	mad_agent_priv->agent.send_handler = send_handler;
@@ -301,7 +307,7 @@ struct ib_mad_agent *ib_register_mad_agent(struct ib_device *device,
 				if (method) {
 					if (method_in_use(&method,
 							   mad_reg_req))
-						goto error3;
+						goto error4;
 				}
 			}
 			ret2 = add_nonoui_reg_req(mad_reg_req, mad_agent_priv,
@@ -317,14 +323,14 @@ struct ib_mad_agent *ib_register_mad_agent(struct ib_device *device,
 					if (is_vendor_method_in_use(
 							vendor_class,
 							mad_reg_req))
-						goto error3;
+						goto error4;
 				}
 			}
 			ret2 = add_oui_reg_req(mad_reg_req, mad_agent_priv);
 		}
 		if (ret2) {
 			ret = ERR_PTR(ret2);
-			goto error3;
+			goto error4;
 		}
 	}
 
@@ -335,22 +341,24 @@ struct ib_mad_agent *ib_register_mad_agent(struct ib_device *device,
 	spin_lock_init(&mad_agent_priv->lock);
 	INIT_LIST_HEAD(&mad_agent_priv->send_list);
 	INIT_LIST_HEAD(&mad_agent_priv->wait_list);
+	INIT_LIST_HEAD(&mad_agent_priv->done_list);
+	INIT_LIST_HEAD(&mad_agent_priv->rmpp_list);
 	INIT_WORK(&mad_agent_priv->timed_work, timeout_sends, mad_agent_priv);
 	INIT_LIST_HEAD(&mad_agent_priv->local_list);
 	INIT_WORK(&mad_agent_priv->local_work, local_completions,
 		   mad_agent_priv);
-	INIT_LIST_HEAD(&mad_agent_priv->canceled_list);
-	INIT_WORK(&mad_agent_priv->canceled_work, cancel_sends, mad_agent_priv);
 	atomic_set(&mad_agent_priv->refcount, 1);
 	init_waitqueue_head(&mad_agent_priv->wait);
 
 	return &mad_agent_priv->agent;
 
-error3:
+error4:
 	spin_unlock_irqrestore(&port_priv->reg_lock, flags);
 	kfree(reg_req);
-error2:
+error3:
 	kfree(mad_agent_priv);
+error2:
+	ib_dereg_mr(mad_agent_priv->agent.mr);
 error1:
 	return ret;
 }
@@ -487,18 +495,16 @@ static void unregister_mad_agent(struct ib_mad_agent_private *mad_agent_priv)
 	 * MADs, preventing us from queuing additional work
 	 */
 	cancel_mads(mad_agent_priv);
-
 	port_priv = mad_agent_priv->qp_info->port_priv;
-
 	cancel_delayed_work(&mad_agent_priv->timed_work);
-	flush_workqueue(port_priv->wq);
 
 	spin_lock_irqsave(&port_priv->reg_lock, flags);
 	remove_mad_reg_req(mad_agent_priv);
 	list_del(&mad_agent_priv->agent_list);
 	spin_unlock_irqrestore(&port_priv->reg_lock, flags);
 
-	/* XXX: Cleanup pending RMPP receives for this agent */
+	flush_workqueue(port_priv->wq);
+	ib_cancel_rmpp_recvs(mad_agent_priv);
 
 	atomic_dec(&mad_agent_priv->refcount);
 	wait_event(mad_agent_priv->wait,
@@ -506,6 +512,7 @@ static void unregister_mad_agent(struct ib_mad_agent_private *mad_agent_priv)
 
 	if (mad_agent_priv->reg_req)
 		kfree(mad_agent_priv->reg_req);
+	ib_dereg_mr(mad_agent_priv->agent.mr);
 	kfree(mad_agent_priv);
 }
 
@@ -551,6 +558,13 @@ int ib_unregister_mad_agent(struct ib_mad_agent *mad_agent)
 }
 EXPORT_SYMBOL(ib_unregister_mad_agent);
 
+static inline int response_mad(struct ib_mad *mad)
+{
+	/* Trap represses are responses although response bit is reset */
+	return ((mad->mad_hdr.method == IB_MGMT_METHOD_TRAP_REPRESS) ||
+		(mad->mad_hdr.method & IB_MGMT_METHOD_RESP));
+}
+
 static void dequeue_mad(struct ib_mad_list_head *mad_list)
 {
 	struct ib_mad_queue *mad_queue;
@@ -643,7 +657,7 @@ static int handle_outgoing_dr_smp(struct ib_mad_agent_private *mad_agent_priv,
 				  struct ib_smp *smp,
 				  struct ib_send_wr *send_wr)
 {
-	int ret, solicited;
+	int ret;
 	unsigned long flags;
 	struct ib_mad_local_private *local;
 	struct ib_mad_private *mad_priv;
@@ -689,11 +703,7 @@ static int handle_outgoing_dr_smp(struct ib_mad_agent_private *mad_agent_priv,
 	switch (ret)
 	{
 	case IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY:
-		/*
-		 * See if response is solicited and
-		 * there is a recv handler
-		 */
-		if (solicited_mad(&mad_priv->mad.mad) &&
+		if (response_mad(&mad_priv->mad.mad) &&
 		    mad_agent_priv->agent.recv_handler) {
 			local->mad_priv = mad_priv;
 			local->recv_mad_agent = mad_agent_priv;
@@ -710,15 +720,13 @@ static int handle_outgoing_dr_smp(struct ib_mad_agent_private *mad_agent_priv,
 		break;
 	case IB_MAD_RESULT_SUCCESS:
 		/* Treat like an incoming receive MAD */
-		solicited = solicited_mad(&mad_priv->mad.mad);
 		port_priv = ib_get_mad_port(mad_agent_priv->agent.device,
 					    mad_agent_priv->agent.port_num);
 		if (port_priv) {
 			mad_priv->mad.mad.mad_hdr.tid =
 				((struct ib_mad *)smp)->mad_hdr.tid;
 			recv_mad_agent = find_mad_agent(port_priv,
-						       &mad_priv->mad.mad,
-							solicited);
+						        &mad_priv->mad.mad);
 		}
 		if (!port_priv || !recv_mad_agent) {
 			kmem_cache_free(ib_mad_cache, mad_priv);
@@ -750,43 +758,133 @@ static int handle_outgoing_dr_smp(struct ib_mad_agent_private *mad_agent_priv,
 	list_add_tail(&local->completion_list, &mad_agent_priv->local_list);
 	spin_unlock_irqrestore(&mad_agent_priv->lock, flags);
 	queue_work(mad_agent_priv->qp_info->port_priv->wq,
-		  &mad_agent_priv->local_work);
+		   &mad_agent_priv->local_work);
 	ret = 1;
 out:
 	return ret;
 }
 
-static int ib_send_mad(struct ib_mad_agent_private *mad_agent_priv,
-		       struct ib_mad_send_wr_private *mad_send_wr)
+static int get_buf_length(int hdr_len, int data_len)
+{
+	int seg_size, pad;
+
+	seg_size = sizeof(struct ib_mad) - hdr_len;
+	if (data_len && seg_size) {
+		pad = seg_size - data_len % seg_size;
+		if (pad == seg_size)
+			pad = 0;
+	} else
+		pad = seg_size;
+	return hdr_len + data_len + pad;
+}
+
+struct ib_mad_send_buf * ib_create_send_mad(struct ib_mad_agent *mad_agent,
+					    u32 remote_qpn, u16 pkey_index,
+					    struct ib_ah *ah, int rmpp_active,
+					    int hdr_len, int data_len,
+					    unsigned int __nocast gfp_mask)
+{
+	struct ib_mad_agent_private *mad_agent_priv;
+	struct ib_mad_send_buf *send_buf;
+	int buf_size;
+	void *buf;
+
+	mad_agent_priv = container_of(mad_agent,
+				      struct ib_mad_agent_private, agent);
+	buf_size = get_buf_length(hdr_len, data_len);
+
+	if ((!mad_agent->rmpp_version &&
+	     (rmpp_active || buf_size > sizeof(struct ib_mad))) ||
+	    (!rmpp_active && buf_size > sizeof(struct ib_mad)))
+		return ERR_PTR(-EINVAL);
+
+	buf = kmalloc(sizeof *send_buf + buf_size, gfp_mask);
+	if (!buf)
+		return ERR_PTR(-ENOMEM);
+	memset(buf, 0, sizeof *send_buf + buf_size);
+
+	send_buf = buf + buf_size;
+	send_buf->mad = buf;
+
+	send_buf->sge.addr = dma_map_single(mad_agent->device->dma_device,
+					    buf, buf_size, DMA_TO_DEVICE);
+	pci_unmap_addr_set(send_buf, mapping, send_buf->sge.addr);
+	send_buf->sge.length = buf_size;
+	send_buf->sge.lkey = mad_agent->mr->lkey;
+
+	send_buf->send_wr.wr_id = (unsigned long) send_buf;
+	send_buf->send_wr.sg_list = &send_buf->sge;
+	send_buf->send_wr.num_sge = 1;
+	send_buf->send_wr.opcode = IB_WR_SEND;
+	send_buf->send_wr.send_flags = IB_SEND_SIGNALED;
+	send_buf->send_wr.wr.ud.ah = ah;
+	send_buf->send_wr.wr.ud.mad_hdr = &send_buf->mad->mad_hdr;
+	send_buf->send_wr.wr.ud.remote_qpn = remote_qpn;
+	send_buf->send_wr.wr.ud.remote_qkey = IB_QP_SET_QKEY;
+	send_buf->send_wr.wr.ud.pkey_index = pkey_index;
+
+	if (rmpp_active) {
+		struct ib_rmpp_mad *rmpp_mad;
+		rmpp_mad = (struct ib_rmpp_mad *)send_buf->mad;
+		rmpp_mad->rmpp_hdr.paylen_newwin = cpu_to_be32(hdr_len -
+			offsetof(struct ib_rmpp_mad, data) + data_len);
+		rmpp_mad->rmpp_hdr.rmpp_version = mad_agent->rmpp_version;
+		rmpp_mad->rmpp_hdr.rmpp_type = IB_MGMT_RMPP_TYPE_DATA;
+		ib_set_rmpp_flags(&rmpp_mad->rmpp_hdr,
+				  IB_MGMT_RMPP_FLAG_ACTIVE);
+	}
+
+	send_buf->mad_agent = mad_agent;
+	atomic_inc(&mad_agent_priv->refcount);
+	return send_buf;
+}
+EXPORT_SYMBOL(ib_create_send_mad);
+
+void ib_free_send_mad(struct ib_mad_send_buf *send_buf)
+{
+	struct ib_mad_agent_private *mad_agent_priv;
+
+	mad_agent_priv = container_of(send_buf->mad_agent,
+				      struct ib_mad_agent_private, agent);
+
+	dma_unmap_single(send_buf->mad_agent->device->dma_device,
+			 pci_unmap_addr(send_buf, mapping),
+			 send_buf->sge.length, DMA_TO_DEVICE);
+	kfree(send_buf->mad);
+
+	if (atomic_dec_and_test(&mad_agent_priv->refcount))
+		wake_up(&mad_agent_priv->wait);
+}
+EXPORT_SYMBOL(ib_free_send_mad);
+
+int ib_send_mad(struct ib_mad_send_wr_private *mad_send_wr)
 {
 	struct ib_mad_qp_info *qp_info;
 	struct ib_send_wr *bad_send_wr;
+	struct list_head *list;
 	unsigned long flags;
 	int ret;
 
-	/* Replace user's WR ID with our own to find WR upon completion */
-	qp_info = mad_agent_priv->qp_info;
-	mad_send_wr->wr_id = mad_send_wr->send_wr.wr_id;
+	/* Set WR ID to find mad_send_wr upon completion */
+	qp_info = mad_send_wr->mad_agent_priv->qp_info;
 	mad_send_wr->send_wr.wr_id = (unsigned long)&mad_send_wr->mad_list;
 	mad_send_wr->mad_list.mad_queue = &qp_info->send_queue;
 
 	spin_lock_irqsave(&qp_info->send_queue.lock, flags);
-	if (qp_info->send_queue.count++ < qp_info->send_queue.max_active) {
-		list_add_tail(&mad_send_wr->mad_list.list,
-			      &qp_info->send_queue.list);
-		spin_unlock_irqrestore(&qp_info->send_queue.lock, flags);
-		ret = ib_post_send(mad_agent_priv->agent.qp,
+	if (qp_info->send_queue.count < qp_info->send_queue.max_active) {
+		ret = ib_post_send(mad_send_wr->mad_agent_priv->agent.qp,
 				   &mad_send_wr->send_wr, &bad_send_wr);
-		if (ret) {
-			printk(KERN_ERR PFX "ib_post_send failed: %d\n", ret);
-			dequeue_mad(&mad_send_wr->mad_list);
-		}
+		list = &qp_info->send_queue.list;
 	} else {
-		list_add_tail(&mad_send_wr->mad_list.list,
-			      &qp_info->overflow_list);
-		spin_unlock_irqrestore(&qp_info->send_queue.lock, flags);
 		ret = 0;
+		list = &qp_info->overflow_list;
 	}
+
+	if (!ret) {
+		qp_info->send_queue.count++;
+		list_add_tail(&mad_send_wr->mad_list.list, list);
+	}
+	spin_unlock_irqrestore(&qp_info->send_queue.lock, flags);
 	return ret;
 }
 
@@ -860,18 +958,19 @@ int ib_post_send_mad(struct ib_mad_agent *mad_agent,
 			ret = -ENOMEM;
 			goto error2;
 		}
+		memset(mad_send_wr, 0, sizeof *mad_send_wr);
 
 		mad_send_wr->send_wr = *send_wr;
 		mad_send_wr->send_wr.sg_list = mad_send_wr->sg_list;
 		memcpy(mad_send_wr->sg_list, send_wr->sg_list,
 		       sizeof *send_wr->sg_list * send_wr->num_sge);
-		mad_send_wr->send_wr.next = NULL;
+		mad_send_wr->wr_id = send_wr->wr_id;
 		mad_send_wr->tid = send_wr->wr.ud.mad_hdr->tid;
-		mad_send_wr->agent = mad_agent;
+		mad_send_wr->mad_agent_priv = mad_agent_priv;
 		/* Timeout will be updated after send completes */
 		mad_send_wr->timeout = msecs_to_jiffies(send_wr->wr.
 							ud.timeout_ms);
-		mad_send_wr->retry = 0;
+		mad_send_wr->retries = mad_send_wr->send_wr.wr.ud.retries;
 		/* One reference for each work request to QP + response */
 		mad_send_wr->refcount = 1 + (mad_send_wr->timeout > 0);
 		mad_send_wr->status = IB_WC_SUCCESS;
@@ -883,8 +982,13 @@ int ib_post_send_mad(struct ib_mad_agent *mad_agent,
 			      &mad_agent_priv->send_list);
 		spin_unlock_irqrestore(&mad_agent_priv->lock, flags);
 
-		ret = ib_send_mad(mad_agent_priv, mad_send_wr);
-		if (ret) {
+		if (mad_agent_priv->agent.rmpp_version) {
+			ret = ib_send_rmpp_mad(mad_send_wr);
+			if (ret >= 0 && ret != IB_RMPP_RESULT_CONSUMED)
+				ret = ib_send_mad(mad_send_wr);
+		} else
+			ret = ib_send_mad(mad_send_wr);
+		if (ret < 0) {
 			/* Fail send request */
 			spin_lock_irqsave(&mad_agent_priv->lock, flags);
 			list_del(&mad_send_wr->agent_list);
@@ -910,41 +1014,28 @@ EXPORT_SYMBOL(ib_post_send_mad);
  */
 void ib_free_recv_mad(struct ib_mad_recv_wc *mad_recv_wc)
 {
-	struct ib_mad_recv_buf *entry;
+	struct ib_mad_recv_buf *mad_recv_buf, *temp_recv_buf;
 	struct ib_mad_private_header *mad_priv_hdr;
 	struct ib_mad_private *priv;
+	struct list_head free_list;
 
-	mad_priv_hdr = container_of(mad_recv_wc,
-				    struct ib_mad_private_header,
-				    recv_wc);
-	priv = container_of(mad_priv_hdr, struct ib_mad_private, header);
+	INIT_LIST_HEAD(&free_list);
+	list_splice_init(&mad_recv_wc->rmpp_list, &free_list);
 
-	/*
-	 * Walk receive buffer list associated with this WC
-	 * No need to remove them from list of receive buffers
-	 */
-	list_for_each_entry(entry, &mad_recv_wc->recv_buf.list, list) {
-		/* Free previous receive buffer */
-		kmem_cache_free(ib_mad_cache, priv);
+	list_for_each_entry_safe(mad_recv_buf, temp_recv_buf,
+					&free_list, list) {
+		mad_recv_wc = container_of(mad_recv_buf, struct ib_mad_recv_wc,
+					   recv_buf);
 		mad_priv_hdr = container_of(mad_recv_wc,
 					    struct ib_mad_private_header,
 					    recv_wc);
 		priv = container_of(mad_priv_hdr, struct ib_mad_private,
 				    header);
+		kmem_cache_free(ib_mad_cache, priv);
 	}
-
-	/* Free last buffer */
-	kmem_cache_free(ib_mad_cache, priv);
 }
 EXPORT_SYMBOL(ib_free_recv_mad);
 
-void ib_coalesce_recv_mad(struct ib_mad_recv_wc *mad_recv_wc,
-			  void *buf)
-{
-	printk(KERN_ERR PFX "ib_coalesce_recv_mad() not implemented yet\n");
-}
-EXPORT_SYMBOL(ib_coalesce_recv_mad);
-
 struct ib_mad_agent *ib_redirect_mad_qp(struct ib_qp *qp,
 					u8 rmpp_version,
 					ib_mad_send_handler send_handler,
@@ -1338,42 +1429,15 @@ out:
 	return;
 }
 
-static int response_mad(struct ib_mad *mad)
-{
-	/* Trap represses are responses although response bit is reset */
-	return ((mad->mad_hdr.method == IB_MGMT_METHOD_TRAP_REPRESS) ||
-		(mad->mad_hdr.method & IB_MGMT_METHOD_RESP));
-}
-
-static int solicited_mad(struct ib_mad *mad)
-{
-	/* CM MADs are never solicited */
-	if (mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_CM) {
-		return 0;
-	}
-
-	/* XXX: Determine whether MAD is using RMPP */
-
-	/* Not using RMPP */
-	/* Is this MAD a response to a previous MAD ? */
-	return response_mad(mad);
-}
-
 static struct ib_mad_agent_private *
 find_mad_agent(struct ib_mad_port_private *port_priv,
-	       struct ib_mad *mad,
-	       int solicited)
+	       struct ib_mad *mad)
 {
 	struct ib_mad_agent_private *mad_agent = NULL;
 	unsigned long flags;
 
 	spin_lock_irqsave(&port_priv->reg_lock, flags);
-
-	/*
-	 * Whether MAD was solicited determines type of routing to
-	 * MAD client.
-	 */
-	if (solicited) {
+	if (response_mad(mad)) {
 		u32 hi_tid;
 		struct ib_mad_agent_private *entry;
 
@@ -1477,21 +1541,20 @@ out:
 	return valid;
 }
 
-/*
- * Return start of fully reassembled MAD, or NULL, if MAD isn't assembled yet
- */
-static struct ib_mad_private *
-reassemble_recv(struct ib_mad_agent_private *mad_agent_priv,
-		struct ib_mad_private *recv)
+static int is_data_mad(struct ib_mad_agent_private *mad_agent_priv,
+		       struct ib_mad_hdr *mad_hdr)
 {
-	/* Until we have RMPP, all receives are reassembled!... */
-	INIT_LIST_HEAD(&recv->header.recv_wc.recv_buf.list);
-	return recv;
+	struct ib_rmpp_mad *rmpp_mad;
+
+	rmpp_mad = (struct ib_rmpp_mad *)mad_hdr;
+	return !mad_agent_priv->agent.rmpp_version ||
+		!(ib_get_rmpp_flags(&rmpp_mad->rmpp_hdr) &
+				    IB_MGMT_RMPP_FLAG_ACTIVE) ||
+		(rmpp_mad->rmpp_hdr.rmpp_type == IB_MGMT_RMPP_TYPE_DATA);
 }
 
-static struct ib_mad_send_wr_private*
-find_send_req(struct ib_mad_agent_private *mad_agent_priv,
-	      u64 tid)
+struct ib_mad_send_wr_private*
+ib_find_send_mad(struct ib_mad_agent_private *mad_agent_priv, u64 tid)
 {
 	struct ib_mad_send_wr_private *mad_send_wr;
 
@@ -1507,7 +1570,9 @@ find_send_req(struct ib_mad_agent_private *mad_agent_priv,
 	 */
 	list_for_each_entry(mad_send_wr, &mad_agent_priv->send_list,
 			    agent_list) {
-		if (mad_send_wr->tid == tid && mad_send_wr->timeout) {
+		if (is_data_mad(mad_agent_priv,
+				mad_send_wr->send_wr.wr.ud.mad_hdr) &&
+		    mad_send_wr->tid == tid && mad_send_wr->timeout) {
 			/* Verify request has not been canceled */
 			return (mad_send_wr->status == IB_WC_SUCCESS) ?
 				mad_send_wr : NULL;
@@ -1516,43 +1581,55 @@ find_send_req(struct ib_mad_agent_private *mad_agent_priv,
 	return NULL;
 }
 
+void ib_mark_mad_done(struct ib_mad_send_wr_private *mad_send_wr)
+{
+	mad_send_wr->timeout = 0;
+	if (mad_send_wr->refcount == 1) {
+		list_del(&mad_send_wr->agent_list);
+		list_add_tail(&mad_send_wr->agent_list,
+			      &mad_send_wr->mad_agent_priv->done_list);
+	}
+}
+
 static void ib_mad_complete_recv(struct ib_mad_agent_private *mad_agent_priv,
-				 struct ib_mad_private *recv,
-				 int solicited)
+				 struct ib_mad_recv_wc *mad_recv_wc)
 {
 	struct ib_mad_send_wr_private *mad_send_wr;
 	struct ib_mad_send_wc mad_send_wc;
 	unsigned long flags;
-
-	/* Fully reassemble receive before processing */
-	recv = reassemble_recv(mad_agent_priv, recv);
-	if (!recv) {
-		if (atomic_dec_and_test(&mad_agent_priv->refcount))
-			wake_up(&mad_agent_priv->wait);
-		return;
+	u64 tid;
+
+	INIT_LIST_HEAD(&mad_recv_wc->rmpp_list);
+	list_add(&mad_recv_wc->recv_buf.list, &mad_recv_wc->rmpp_list);
+	if (mad_agent_priv->agent.rmpp_version) {
+		mad_recv_wc = ib_process_rmpp_recv_wc(mad_agent_priv,
+						      mad_recv_wc);
+		if (!mad_recv_wc) {
+			if (atomic_dec_and_test(&mad_agent_priv->refcount))
+				wake_up(&mad_agent_priv->wait);
+			return;
+		}
 	}
 
 	/* Complete corresponding request */
-	if (solicited) {
+	if (response_mad(mad_recv_wc->recv_buf.mad)) {
+		tid = mad_recv_wc->recv_buf.mad->mad_hdr.tid;
 		spin_lock_irqsave(&mad_agent_priv->lock, flags);
-		mad_send_wr = find_send_req(mad_agent_priv,
-					    recv->mad.mad.mad_hdr.tid);
+		mad_send_wr = ib_find_send_mad(mad_agent_priv, tid);
 		if (!mad_send_wr) {
 			spin_unlock_irqrestore(&mad_agent_priv->lock, flags);
-			ib_free_recv_mad(&recv->header.recv_wc);
+			ib_free_recv_mad(mad_recv_wc);
 			if (atomic_dec_and_test(&mad_agent_priv->refcount))
 				wake_up(&mad_agent_priv->wait);
 			return;
 		}
-		/* Timeout = 0 means that we won't wait for a response */
-		mad_send_wr->timeout = 0;
+		ib_mark_mad_done(mad_send_wr);
 		spin_unlock_irqrestore(&mad_agent_priv->lock, flags);
 
 		/* Defined behavior is to complete response before request */
-		recv->header.recv_wc.wc->wr_id = mad_send_wr->wr_id;
-		mad_agent_priv->agent.recv_handler(
-						&mad_agent_priv->agent,
-						&recv->header.recv_wc);
+		mad_recv_wc->wc->wr_id = mad_send_wr->wr_id;
+		mad_agent_priv->agent.recv_handler(&mad_agent_priv->agent,
+						   mad_recv_wc);
 		atomic_dec(&mad_agent_priv->refcount);
 
 		mad_send_wc.status = IB_WC_SUCCESS;
@@ -1560,9 +1637,8 @@ static void ib_mad_complete_recv(struct ib_mad_agent_private *mad_agent_priv,
 		mad_send_wc.wr_id = mad_send_wr->wr_id;
 		ib_mad_complete_send_wr(mad_send_wr, &mad_send_wc);
 	} else {
-		mad_agent_priv->agent.recv_handler(
-						&mad_agent_priv->agent,
-						&recv->header.recv_wc);
+		mad_agent_priv->agent.recv_handler(&mad_agent_priv->agent,
+						   mad_recv_wc);
 		if (atomic_dec_and_test(&mad_agent_priv->refcount))
 			wake_up(&mad_agent_priv->wait);
 	}
@@ -1576,7 +1652,6 @@ static void ib_mad_recv_done_handler(struct ib_mad_port_private *port_priv,
 	struct ib_mad_private *recv, *response;
 	struct ib_mad_list_head *mad_list;
 	struct ib_mad_agent_private *mad_agent;
-	int solicited;
 
 	response = kmem_cache_alloc(ib_mad_cache, GFP_KERNEL);
 	if (!response)
@@ -1662,11 +1737,9 @@ local:
 		}
 	}
 
-	/* Determine corresponding MAD agent for incoming receive MAD */
-	solicited = solicited_mad(&recv->mad.mad);
-	mad_agent = find_mad_agent(port_priv, &recv->mad.mad, solicited);
+	mad_agent = find_mad_agent(port_priv, &recv->mad.mad);
 	if (mad_agent) {
-		ib_mad_complete_recv(mad_agent, recv, solicited);
+		ib_mad_complete_recv(mad_agent, &recv->header.recv_wc);
 		/*
 		 * recv is freed up in error cases in ib_mad_complete_recv
 		 * or via recv_handler in ib_mad_complete_recv()
@@ -1710,26 +1783,31 @@ static void adjust_timeout(struct ib_mad_agent_private *mad_agent_priv)
 	}
 }
 
-static void wait_for_response(struct ib_mad_agent_private *mad_agent_priv,
-			      struct ib_mad_send_wr_private *mad_send_wr )
+static void wait_for_response(struct ib_mad_send_wr_private *mad_send_wr)
 {
+	struct ib_mad_agent_private *mad_agent_priv;
 	struct ib_mad_send_wr_private *temp_mad_send_wr;
 	struct list_head *list_item;
 	unsigned long delay;
 
+	mad_agent_priv = mad_send_wr->mad_agent_priv;
 	list_del(&mad_send_wr->agent_list);
 
 	delay = mad_send_wr->timeout;
 	mad_send_wr->timeout += jiffies;
 
-	list_for_each_prev(list_item, &mad_agent_priv->wait_list) {
-		temp_mad_send_wr = list_entry(list_item,
-					      struct ib_mad_send_wr_private,
-					      agent_list);
-		if (time_after(mad_send_wr->timeout,
-			       temp_mad_send_wr->timeout))
-			break;
+	if (delay) {
+		list_for_each_prev(list_item, &mad_agent_priv->wait_list) {
+			temp_mad_send_wr = list_entry(list_item,
+						struct ib_mad_send_wr_private,
+						agent_list);
+			if (time_after(mad_send_wr->timeout,
+				       temp_mad_send_wr->timeout))
+				break;
+		}
 	}
+	else
+		list_item = &mad_agent_priv->wait_list;
 	list_add(&mad_send_wr->agent_list, list_item);
 
 	/* Reschedule a work item if we have a shorter timeout */
@@ -1740,19 +1818,32 @@ static void wait_for_response(struct ib_mad_agent_private *mad_agent_priv,
 	}
 }
 
+void ib_reset_mad_timeout(struct ib_mad_send_wr_private *mad_send_wr,
+			  int timeout_ms)
+{
+	mad_send_wr->timeout = msecs_to_jiffies(timeout_ms);
+	wait_for_response(mad_send_wr);
+}
+
 /*
  * Process a send work completion
  */
-static void ib_mad_complete_send_wr(struct ib_mad_send_wr_private *mad_send_wr,
-				    struct ib_mad_send_wc *mad_send_wc)
+void ib_mad_complete_send_wr(struct ib_mad_send_wr_private *mad_send_wr,
+			     struct ib_mad_send_wc *mad_send_wc)
 {
 	struct ib_mad_agent_private	*mad_agent_priv;
 	unsigned long			flags;
+	int				ret;
 
-	mad_agent_priv = container_of(mad_send_wr->agent,
-				      struct ib_mad_agent_private, agent);
-
+	mad_agent_priv = mad_send_wr->mad_agent_priv;
 	spin_lock_irqsave(&mad_agent_priv->lock, flags);
+	if (mad_agent_priv->agent.rmpp_version) {
+		ret = ib_process_rmpp_send_wc(mad_send_wr, mad_send_wc);
+		if (ret == IB_RMPP_RESULT_CONSUMED)
+			goto done;
+	} else
+		ret = IB_RMPP_RESULT_UNHANDLED;
+
 	if (mad_send_wc->status != IB_WC_SUCCESS &&
 	    mad_send_wr->status == IB_WC_SUCCESS) {
 		mad_send_wr->status = mad_send_wc->status;
@@ -1762,10 +1853,9 @@ static void ib_mad_complete_send_wr(struct ib_mad_send_wr_private *mad_send_wr,
 	if (--mad_send_wr->refcount > 0) {
 		if (mad_send_wr->refcount == 1 && mad_send_wr->timeout &&
 		    mad_send_wr->status == IB_WC_SUCCESS) {
-			wait_for_response(mad_agent_priv, mad_send_wr);
+			wait_for_response(mad_send_wr);
 		}
-		spin_unlock_irqrestore(&mad_agent_priv->lock, flags);
-		return;
+		goto done;
 	}
 
 	/* Remove send from MAD agent and notify client of completion */
@@ -1775,14 +1865,18 @@ static void ib_mad_complete_send_wr(struct ib_mad_send_wr_private *mad_send_wr,
 
 	if (mad_send_wr->status != IB_WC_SUCCESS )
 		mad_send_wc->status = mad_send_wr->status;
-	mad_agent_priv->agent.send_handler(&mad_agent_priv->agent,
-					    mad_send_wc);
+	if (ret != IB_RMPP_RESULT_INTERNAL)
+		mad_agent_priv->agent.send_handler(&mad_agent_priv->agent,
+						   mad_send_wc);
 
 	/* Release reference on agent taken when sending */
 	if (atomic_dec_and_test(&mad_agent_priv->refcount))
 		wake_up(&mad_agent_priv->wait);
 
 	kfree(mad_send_wr);
+	return;
+done:
+	spin_unlock_irqrestore(&mad_agent_priv->lock, flags);
 }
 
 static void ib_mad_send_done_handler(struct ib_mad_port_private *port_priv,
@@ -1961,6 +2055,8 @@ static void cancel_mads(struct ib_mad_agent_private *mad_agent_priv)
 
 	/* Empty wait list to prevent receives from finding a request */
 	list_splice_init(&mad_agent_priv->wait_list, &cancel_list);
+	/* Empty local completion list as well */
+	list_splice_init(&mad_agent_priv->local_list, &cancel_list);
 	spin_unlock_irqrestore(&mad_agent_priv->lock, flags);
 
 	/* Report all cancelled requests */
@@ -1980,8 +2076,7 @@ static void cancel_mads(struct ib_mad_agent_private *mad_agent_priv)
 }
 
 static struct ib_mad_send_wr_private*
-find_send_by_wr_id(struct ib_mad_agent_private *mad_agent_priv,
-		   u64 wr_id)
+find_send_by_wr_id(struct ib_mad_agent_private *mad_agent_priv, u64 wr_id)
 {
 	struct ib_mad_send_wr_private *mad_send_wr;
 
@@ -1993,79 +2088,50 @@ find_send_by_wr_id(struct ib_mad_agent_private *mad_agent_priv,
 
 	list_for_each_entry(mad_send_wr, &mad_agent_priv->send_list,
 			    agent_list) {
-		if (mad_send_wr->wr_id == wr_id)
+		if (is_data_mad(mad_agent_priv,
+				mad_send_wr->send_wr.wr.ud.mad_hdr) &&
+		    mad_send_wr->wr_id == wr_id)
 			return mad_send_wr;
 	}
 	return NULL;
 }
 
-void cancel_sends(void *data)
-{
-	struct ib_mad_agent_private *mad_agent_priv;
-	struct ib_mad_send_wr_private *mad_send_wr;
-	struct ib_mad_send_wc mad_send_wc;
-	unsigned long flags;
-
-	mad_agent_priv = data;
-
-	mad_send_wc.status = IB_WC_WR_FLUSH_ERR;
-	mad_send_wc.vendor_err = 0;
-
-	spin_lock_irqsave(&mad_agent_priv->lock, flags);
-	while (!list_empty(&mad_agent_priv->canceled_list)) {
-		mad_send_wr = list_entry(mad_agent_priv->canceled_list.next,
-					 struct ib_mad_send_wr_private,
-					 agent_list);
-
-		list_del(&mad_send_wr->agent_list);
-		spin_unlock_irqrestore(&mad_agent_priv->lock, flags);
-
-		mad_send_wc.wr_id = mad_send_wr->wr_id;
-		mad_agent_priv->agent.send_handler(&mad_agent_priv->agent,
-						   &mad_send_wc);
-
-		kfree(mad_send_wr);
-		if (atomic_dec_and_test(&mad_agent_priv->refcount))
-			wake_up(&mad_agent_priv->wait);
-		spin_lock_irqsave(&mad_agent_priv->lock, flags);
-	}
-	spin_unlock_irqrestore(&mad_agent_priv->lock, flags);
-}
-
-void ib_cancel_mad(struct ib_mad_agent *mad_agent,
-		  u64 wr_id)
+int ib_modify_mad(struct ib_mad_agent *mad_agent, u64 wr_id, u32 timeout_ms)
 {
 	struct ib_mad_agent_private *mad_agent_priv;
 	struct ib_mad_send_wr_private *mad_send_wr;
 	unsigned long flags;
+	int active;
 
 	mad_agent_priv = container_of(mad_agent, struct ib_mad_agent_private,
 				      agent);
 	spin_lock_irqsave(&mad_agent_priv->lock, flags);
 	mad_send_wr = find_send_by_wr_id(mad_agent_priv, wr_id);
-	if (!mad_send_wr) {
+	if (!mad_send_wr || mad_send_wr->status != IB_WC_SUCCESS) {
 		spin_unlock_irqrestore(&mad_agent_priv->lock, flags);
-		goto out;
+		return -EINVAL;
 	}
 
-	if (mad_send_wr->status == IB_WC_SUCCESS)
-		mad_send_wr->refcount -= (mad_send_wr->timeout > 0);
-
-	if (mad_send_wr->refcount != 0) {
+	active = (!mad_send_wr->timeout || mad_send_wr->refcount > 1);
+	if (!timeout_ms) {
 		mad_send_wr->status = IB_WC_WR_FLUSH_ERR;
-		spin_unlock_irqrestore(&mad_agent_priv->lock, flags);
-		goto out;
+		mad_send_wr->refcount -= (mad_send_wr->timeout > 0);
 	}
 
-	list_del(&mad_send_wr->agent_list);
-	list_add_tail(&mad_send_wr->agent_list, &mad_agent_priv->canceled_list);
-	adjust_timeout(mad_agent_priv);
+	mad_send_wr->send_wr.wr.ud.timeout_ms = timeout_ms;
+	if (active)
+		mad_send_wr->timeout = msecs_to_jiffies(timeout_ms);
+	else
+		ib_reset_mad_timeout(mad_send_wr, timeout_ms);
+
 	spin_unlock_irqrestore(&mad_agent_priv->lock, flags);
+	return 0;
+}
+EXPORT_SYMBOL(ib_modify_mad);
 
-	queue_work(mad_agent_priv->qp_info->port_priv->wq,
-		   &mad_agent_priv->canceled_work);
-out:
-	return;
+void ib_cancel_mad(struct ib_mad_agent *mad_agent, u64 wr_id)
+{
+	ib_modify_mad(mad_agent, wr_id, 0);
 }
 EXPORT_SYMBOL(ib_cancel_mad);
 
@@ -2075,6 +2141,7 @@ static void local_completions(void *data)
 	struct ib_mad_local_private *local;
 	struct ib_mad_agent_private *recv_mad_agent;
 	unsigned long flags;
+	int recv = 0;
 	struct ib_wc wc;
 	struct ib_mad_send_wc mad_send_wc;
 
@@ -2090,10 +2157,10 @@ static void local_completions(void *data)
 			recv_mad_agent = local->recv_mad_agent;
 			if (!recv_mad_agent) {
 				printk(KERN_ERR PFX "No receive MAD agent for local completion\n");
-				kmem_cache_free(ib_mad_cache, local->mad_priv);
 				goto local_send_completion;
 			}
 
+			recv = 1;
 			/*
 			 * Defined behavior is to complete response
 			 * before request
@@ -2105,7 +2172,9 @@ static void local_completions(void *data)
 			local->mad_priv->header.recv_wc.wc = &wc;
 			local->mad_priv->header.recv_wc.mad_len =
 						sizeof(struct ib_mad);
-			INIT_LIST_HEAD(&local->mad_priv->header.recv_wc.recv_buf.list);
+			INIT_LIST_HEAD(&local->mad_priv->header.recv_wc.rmpp_list);
+			list_add(&local->mad_priv->header.recv_wc.recv_buf.list,
+				 &local->mad_priv->header.recv_wc.rmpp_list);
 			local->mad_priv->header.recv_wc.recv_buf.grh = NULL;
 			local->mad_priv->header.recv_wc.recv_buf.mad =
 						&local->mad_priv->mad.mad;
@@ -2136,11 +2205,47 @@ local_send_completion:
 		spin_lock_irqsave(&mad_agent_priv->lock, flags);
 		list_del(&local->completion_list);
 		atomic_dec(&mad_agent_priv->refcount);
+		if (!recv)
+			kmem_cache_free(ib_mad_cache, local->mad_priv);
 		kfree(local);
 	}
 	spin_unlock_irqrestore(&mad_agent_priv->lock, flags);
 }
 
+static int retry_send(struct ib_mad_send_wr_private *mad_send_wr)
+{
+	int ret;
+
+	if (!mad_send_wr->retries--)
+		return -ETIMEDOUT;
+
+	mad_send_wr->timeout = msecs_to_jiffies(mad_send_wr->send_wr.
+						wr.ud.timeout_ms);
+
+	if (mad_send_wr->mad_agent_priv->agent.rmpp_version) {
+		ret = ib_retry_rmpp(mad_send_wr);
+		switch (ret) {
+		case IB_RMPP_RESULT_UNHANDLED:
+			ret = ib_send_mad(mad_send_wr);
+			break;
+		case IB_RMPP_RESULT_CONSUMED:
+			ret = 0;
+			break;
+		default:
+			ret = -ECOMM;
+			break;
+		}
+	} else
+		ret = ib_send_mad(mad_send_wr);
+
+	if (!ret) {
+		mad_send_wr->refcount++;
+		list_add_tail(&mad_send_wr->agent_list,
+			      &mad_send_wr->mad_agent_priv->send_list);
+	}
+	return ret;
+}
+
 static void timeout_sends(void *data)
 {
 	struct ib_mad_agent_private *mad_agent_priv;
@@ -2149,8 +2254,6 @@ static void timeout_sends(void *data)
 	unsigned long flags, delay;
 
 	mad_agent_priv = (struct ib_mad_agent_private *)data;
-
-	mad_send_wc.status = IB_WC_RESP_TIMEOUT_ERR;
 	mad_send_wc.vendor_err = 0;
 
 	spin_lock_irqsave(&mad_agent_priv->lock, flags);
@@ -2170,8 +2273,16 @@ static void timeout_sends(void *data)
 		}
 
 		list_del(&mad_send_wr->agent_list);
+		if (mad_send_wr->status == IB_WC_SUCCESS &&
+		    !retry_send(mad_send_wr))
+			continue;
+
 		spin_unlock_irqrestore(&mad_agent_priv->lock, flags);
 
+		if (mad_send_wr->status == IB_WC_SUCCESS)
+			mad_send_wc.status = IB_WC_RESP_TIMEOUT_ERR;
+		else
+			mad_send_wc.status = mad_send_wr->status;
 		mad_send_wc.wr_id = mad_send_wr->wr_id;
 		mad_agent_priv->agent.send_handler(&mad_agent_priv->agent,
 						   &mad_send_wc);
@@ -2447,14 +2558,6 @@ static int ib_mad_port_open(struct ib_device *device,
 	unsigned long flags;
 	char name[sizeof "ib_mad123"];
 
-	/* First, check if port already open at MAD layer */
-	port_priv = ib_get_mad_port(device, port_num);
-	if (port_priv) {
-		printk(KERN_DEBUG PFX "%s port %d already open\n",
-		       device->name, port_num);
-		return 0;
-	}
-
 	/* Create new device info */
 	port_priv = kmalloc(sizeof *port_priv, GFP_KERNEL);
 	if (!port_priv) {
@@ -2579,7 +2682,7 @@ static int ib_mad_port_close(struct ib_device *device, int port_num)
 
 static void ib_mad_init_device(struct ib_device *device)
 {
-	int ret, num_ports, cur_port, i, ret2;
+	int num_ports, cur_port, i;
 
 	if (device->node_type == IB_NODE_SWITCH) {
 		num_ports = 1;
@@ -2589,47 +2692,37 @@ static void ib_mad_init_device(struct ib_device *device)
 		cur_port = 1;
 	}
 	for (i = 0; i < num_ports; i++, cur_port++) {
-		ret = ib_mad_port_open(device, cur_port);
-		if (ret) {
+		if (ib_mad_port_open(device, cur_port)) {
 			printk(KERN_ERR PFX "Couldn't open %s port %d\n",
 			       device->name, cur_port);
 			goto error_device_open;
 		}
-		ret = ib_agent_port_open(device, cur_port);
-		if (ret) {
+		if (ib_agent_port_open(device, cur_port)) {
 			printk(KERN_ERR PFX "Couldn't open %s port %d "
 			       "for agents\n",
 			       device->name, cur_port);
 			goto error_device_open;
 		}
 	}
-
-	goto error_device_query;
+	return;
 
 error_device_open:
 	while (i > 0) {
 		cur_port--;
-		ret2 = ib_agent_port_close(device, cur_port);
-		if (ret2) {
+		if (ib_agent_port_close(device, cur_port))
 			printk(KERN_ERR PFX "Couldn't close %s port %d "
 			       "for agents\n",
 			       device->name, cur_port);
-		}
-		ret2 = ib_mad_port_close(device, cur_port);
-		if (ret2) {
+		if (ib_mad_port_close(device, cur_port))
 			printk(KERN_ERR PFX "Couldn't close %s port %d\n",
 			       device->name, cur_port);
-		}
 		i--;
 	}
-
-error_device_query:
-	return;
 }
 
 static void ib_mad_remove_device(struct ib_device *device)
 {
-	int ret = 0, i, num_ports, cur_port, ret2;
+	int i, num_ports, cur_port;
 
 	if (device->node_type == IB_NODE_SWITCH) {
 		num_ports = 1;
@@ -2639,21 +2732,13 @@ static void ib_mad_remove_device(struct ib_device *device)
 		cur_port = 1;
 	}
 	for (i = 0; i < num_ports; i++, cur_port++) {
-		ret2 = ib_agent_port_close(device, cur_port);
-		if (ret2) {
+		if (ib_agent_port_close(device, cur_port))
 			printk(KERN_ERR PFX "Couldn't close %s port %d "
 			       "for agents\n",
 			       device->name, cur_port);
-			if (!ret)
-				ret = ret2;
-		}
-		ret2 = ib_mad_port_close(device, cur_port);
-		if (ret2) {
+		if (ib_mad_port_close(device, cur_port))
 			printk(KERN_ERR PFX "Couldn't close %s port %d\n",
 			       device->name, cur_port);
-			if (!ret)
-				ret = ret2;
-		}
 	}
 }
 
@@ -2709,3 +2794,4 @@ static void __exit ib_mad_cleanup_module(void)
 
 module_init(ib_mad_init_module);
 module_exit(ib_mad_cleanup_module);
+
diff --git a/drivers/infiniband/core/mad_priv.h b/drivers/infiniband/core/mad_priv.h
index 008cbcb94b1..568da10b05a 100644
--- a/drivers/infiniband/core/mad_priv.h
+++ b/drivers/infiniband/core/mad_priv.h
@@ -1,5 +1,7 @@
 /*
  * Copyright (c) 2004, 2005, Voltaire, Inc. All rights reserved.
+ * Copyright (c) 2005 Intel Corporation. All rights reserved.
+ * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
@@ -29,7 +31,7 @@
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
  *
- * $Id: mad_priv.h 1389 2004-12-27 22:56:47Z roland $
+ * $Id: mad_priv.h 2730 2005-06-28 16:43:03Z sean.hefty $
  */
 
 #ifndef __IB_MAD_PRIV_H__
@@ -92,16 +94,15 @@ struct ib_mad_agent_private {
 	spinlock_t lock;
 	struct list_head send_list;
 	struct list_head wait_list;
+	struct list_head done_list;
 	struct work_struct timed_work;
 	unsigned long timeout;
 	struct list_head local_list;
 	struct work_struct local_work;
-	struct list_head canceled_list;
-	struct work_struct canceled_work;
+	struct list_head rmpp_list;
 
 	atomic_t refcount;
 	wait_queue_head_t wait;
-	u8 rmpp_version;
 };
 
 struct ib_mad_snoop_private {
@@ -116,15 +117,24 @@ struct ib_mad_snoop_private {
 struct ib_mad_send_wr_private {
 	struct ib_mad_list_head mad_list;
 	struct list_head agent_list;
-	struct ib_mad_agent *agent;
+	struct ib_mad_agent_private *mad_agent_priv;
 	struct ib_send_wr send_wr;
 	struct ib_sge sg_list[IB_MAD_SEND_REQ_MAX_SG];
 	u64 wr_id;			/* client WR ID */
 	u64 tid;
 	unsigned long timeout;
+	int retries;
 	int retry;
 	int refcount;
 	enum ib_wc_status status;
+
+	/* RMPP control */
+	int last_ack;
+	int seg_num;
+	int newwin;
+	int total_seg;
+	int data_offset;
+	int pad;
 };
 
 struct ib_mad_local_private {
@@ -197,4 +207,17 @@ struct ib_mad_port_private {
 
 extern kmem_cache_t *ib_mad_cache;
 
+int ib_send_mad(struct ib_mad_send_wr_private *mad_send_wr);
+
+struct ib_mad_send_wr_private *
+ib_find_send_mad(struct ib_mad_agent_private *mad_agent_priv, u64 tid);
+
+void ib_mad_complete_send_wr(struct ib_mad_send_wr_private *mad_send_wr,
+			     struct ib_mad_send_wc *mad_send_wc);
+
+void ib_mark_mad_done(struct ib_mad_send_wr_private *mad_send_wr);
+
+void ib_reset_mad_timeout(struct ib_mad_send_wr_private *mad_send_wr,
+			  int timeout_ms);
+
 #endif	/* __IB_MAD_PRIV_H__ */
diff --git a/drivers/infiniband/core/mad_rmpp.c b/drivers/infiniband/core/mad_rmpp.c
new file mode 100644
index 00000000000..8f1eb80e421
--- /dev/null
+++ b/drivers/infiniband/core/mad_rmpp.c
@@ -0,0 +1,765 @@
+/*
+ * Copyright (c) 2005 Intel Inc. All rights reserved.
+ * Copyright (c) 2005 Voltaire, Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * $Id: mad_rmpp.c 1921 2005-03-02 22:58:44Z sean.hefty $
+ */
+
+#include <linux/dma-mapping.h>
+
+#include "mad_priv.h"
+#include "mad_rmpp.h"
+
+enum rmpp_state {
+	RMPP_STATE_ACTIVE,
+	RMPP_STATE_TIMEOUT,
+	RMPP_STATE_COMPLETE
+};
+
+struct mad_rmpp_recv {
+	struct ib_mad_agent_private *agent;
+	struct list_head list;
+	struct work_struct timeout_work;
+	struct work_struct cleanup_work;
+	wait_queue_head_t wait;
+	enum rmpp_state state;
+	spinlock_t lock;
+	atomic_t refcount;
+
+	struct ib_ah *ah;
+	struct ib_mad_recv_wc *rmpp_wc;
+	struct ib_mad_recv_buf *cur_seg_buf;
+	int last_ack;
+	int seg_num;
+	int newwin;
+
+	u64 tid;
+	u32 src_qp;
+	u16 slid;
+	u8 mgmt_class;
+	u8 class_version;
+	u8 method;
+};
+
+static void destroy_rmpp_recv(struct mad_rmpp_recv *rmpp_recv)
+{
+	atomic_dec(&rmpp_recv->refcount);
+	wait_event(rmpp_recv->wait, !atomic_read(&rmpp_recv->refcount));
+	ib_destroy_ah(rmpp_recv->ah);
+	kfree(rmpp_recv);
+}
+
+void ib_cancel_rmpp_recvs(struct ib_mad_agent_private *agent)
+{
+	struct mad_rmpp_recv *rmpp_recv, *temp_rmpp_recv;
+	unsigned long flags;
+
+	spin_lock_irqsave(&agent->lock, flags);
+	list_for_each_entry(rmpp_recv, &agent->rmpp_list, list) {
+		cancel_delayed_work(&rmpp_recv->timeout_work);
+		cancel_delayed_work(&rmpp_recv->cleanup_work);
+	}
+	spin_unlock_irqrestore(&agent->lock, flags);
+
+	flush_workqueue(agent->qp_info->port_priv->wq);
+
+	list_for_each_entry_safe(rmpp_recv, temp_rmpp_recv,
+				 &agent->rmpp_list, list) {
+		list_del(&rmpp_recv->list);
+		if (rmpp_recv->state != RMPP_STATE_COMPLETE)
+			ib_free_recv_mad(rmpp_recv->rmpp_wc);
+		destroy_rmpp_recv(rmpp_recv);
+	}
+}
+
+static void recv_timeout_handler(void *data)
+{
+	struct mad_rmpp_recv *rmpp_recv = data;
+	struct ib_mad_recv_wc *rmpp_wc;
+	unsigned long flags;
+
+	spin_lock_irqsave(&rmpp_recv->agent->lock, flags);
+	if (rmpp_recv->state != RMPP_STATE_ACTIVE) {
+		spin_unlock_irqrestore(&rmpp_recv->agent->lock, flags);
+		return;
+	}
+	rmpp_recv->state = RMPP_STATE_TIMEOUT;
+	list_del(&rmpp_recv->list);
+	spin_unlock_irqrestore(&rmpp_recv->agent->lock, flags);
+
+	/* TODO: send abort. */
+	rmpp_wc = rmpp_recv->rmpp_wc;
+	destroy_rmpp_recv(rmpp_recv);
+	ib_free_recv_mad(rmpp_wc);
+}
+
+static void recv_cleanup_handler(void *data)
+{
+	struct mad_rmpp_recv *rmpp_recv = data;
+	unsigned long flags;
+
+	spin_lock_irqsave(&rmpp_recv->agent->lock, flags);
+	list_del(&rmpp_recv->list);
+	spin_unlock_irqrestore(&rmpp_recv->agent->lock, flags);
+	destroy_rmpp_recv(rmpp_recv);
+}
+
+static struct mad_rmpp_recv *
+create_rmpp_recv(struct ib_mad_agent_private *agent,
+		 struct ib_mad_recv_wc *mad_recv_wc)
+{
+	struct mad_rmpp_recv *rmpp_recv;
+	struct ib_mad_hdr *mad_hdr;
+
+	rmpp_recv = kmalloc(sizeof *rmpp_recv, GFP_KERNEL);
+	if (!rmpp_recv)
+		return NULL;
+
+	rmpp_recv->ah = ib_create_ah_from_wc(agent->agent.qp->pd,
+					     mad_recv_wc->wc,
+					     mad_recv_wc->recv_buf.grh,
+					     agent->agent.port_num);
+	if (IS_ERR(rmpp_recv->ah))
+		goto error;
+
+	rmpp_recv->agent = agent;
+	init_waitqueue_head(&rmpp_recv->wait);
+	INIT_WORK(&rmpp_recv->timeout_work, recv_timeout_handler, rmpp_recv);
+	INIT_WORK(&rmpp_recv->cleanup_work, recv_cleanup_handler, rmpp_recv);
+	spin_lock_init(&rmpp_recv->lock);
+	rmpp_recv->state = RMPP_STATE_ACTIVE;
+	atomic_set(&rmpp_recv->refcount, 1);
+
+	rmpp_recv->rmpp_wc = mad_recv_wc;
+	rmpp_recv->cur_seg_buf = &mad_recv_wc->recv_buf;
+	rmpp_recv->newwin = 1;
+	rmpp_recv->seg_num = 1;
+	rmpp_recv->last_ack = 0;
+
+	mad_hdr = &mad_recv_wc->recv_buf.mad->mad_hdr;
+	rmpp_recv->tid = mad_hdr->tid;
+	rmpp_recv->src_qp = mad_recv_wc->wc->src_qp;
+	rmpp_recv->slid = mad_recv_wc->wc->slid;
+	rmpp_recv->mgmt_class = mad_hdr->mgmt_class;
+	rmpp_recv->class_version = mad_hdr->class_version;
+	rmpp_recv->method  = mad_hdr->method;
+	return rmpp_recv;
+
+error:	kfree(rmpp_recv);
+	return NULL;
+}
+
+static inline void deref_rmpp_recv(struct mad_rmpp_recv *rmpp_recv)
+{
+	if (atomic_dec_and_test(&rmpp_recv->refcount))
+		wake_up(&rmpp_recv->wait);
+}
+
+static struct mad_rmpp_recv *
+find_rmpp_recv(struct ib_mad_agent_private *agent,
+	       struct ib_mad_recv_wc *mad_recv_wc)
+{
+	struct mad_rmpp_recv *rmpp_recv;
+	struct ib_mad_hdr *mad_hdr = &mad_recv_wc->recv_buf.mad->mad_hdr;
+
+	list_for_each_entry(rmpp_recv, &agent->rmpp_list, list) {
+		if (rmpp_recv->tid == mad_hdr->tid &&
+		    rmpp_recv->src_qp == mad_recv_wc->wc->src_qp &&
+		    rmpp_recv->slid == mad_recv_wc->wc->slid &&
+		    rmpp_recv->mgmt_class == mad_hdr->mgmt_class &&
+		    rmpp_recv->class_version == mad_hdr->class_version &&
+		    rmpp_recv->method == mad_hdr->method)
+			return rmpp_recv;
+	}
+	return NULL;
+}
+
+static struct mad_rmpp_recv *
+acquire_rmpp_recv(struct ib_mad_agent_private *agent,
+		  struct ib_mad_recv_wc *mad_recv_wc)
+{
+	struct mad_rmpp_recv *rmpp_recv;
+	unsigned long flags;
+
+	spin_lock_irqsave(&agent->lock, flags);
+	rmpp_recv = find_rmpp_recv(agent, mad_recv_wc);
+	if (rmpp_recv)
+		atomic_inc(&rmpp_recv->refcount);
+	spin_unlock_irqrestore(&agent->lock, flags);
+	return rmpp_recv;
+}
+
+static struct mad_rmpp_recv *
+insert_rmpp_recv(struct ib_mad_agent_private *agent,
+		 struct mad_rmpp_recv *rmpp_recv)
+{
+	struct mad_rmpp_recv *cur_rmpp_recv;
+
+	cur_rmpp_recv = find_rmpp_recv(agent, rmpp_recv->rmpp_wc);
+	if (!cur_rmpp_recv)
+		list_add_tail(&rmpp_recv->list, &agent->rmpp_list);
+
+	return cur_rmpp_recv;
+}
+
+static int data_offset(u8 mgmt_class)
+{
+	if (mgmt_class == IB_MGMT_CLASS_SUBN_ADM)
+		return offsetof(struct ib_sa_mad, data);
+	else if ((mgmt_class >= IB_MGMT_CLASS_VENDOR_RANGE2_START) &&
+		 (mgmt_class <= IB_MGMT_CLASS_VENDOR_RANGE2_END))
+		return offsetof(struct ib_vendor_mad, data);
+	else
+		return offsetof(struct ib_rmpp_mad, data);
+}
+
+static void format_ack(struct ib_rmpp_mad *ack,
+		       struct ib_rmpp_mad *data,
+		       struct mad_rmpp_recv *rmpp_recv)
+{
+	unsigned long flags;
+
+	memcpy(&ack->mad_hdr, &data->mad_hdr,
+	       data_offset(data->mad_hdr.mgmt_class));
+
+	ack->mad_hdr.method ^= IB_MGMT_METHOD_RESP;
+	ack->rmpp_hdr.rmpp_type = IB_MGMT_RMPP_TYPE_ACK;
+	ib_set_rmpp_flags(&ack->rmpp_hdr, IB_MGMT_RMPP_FLAG_ACTIVE);
+
+	spin_lock_irqsave(&rmpp_recv->lock, flags);
+	rmpp_recv->last_ack = rmpp_recv->seg_num;
+	ack->rmpp_hdr.seg_num = cpu_to_be32(rmpp_recv->seg_num);
+	ack->rmpp_hdr.paylen_newwin = cpu_to_be32(rmpp_recv->newwin);
+	spin_unlock_irqrestore(&rmpp_recv->lock, flags);
+}
+
+static void ack_recv(struct mad_rmpp_recv *rmpp_recv,
+		     struct ib_mad_recv_wc *recv_wc)
+{
+	struct ib_mad_send_buf *msg;
+	struct ib_send_wr *bad_send_wr;
+	int hdr_len, ret;
+
+	hdr_len = sizeof(struct ib_mad_hdr) + sizeof(struct ib_rmpp_hdr);
+	msg = ib_create_send_mad(&rmpp_recv->agent->agent, recv_wc->wc->src_qp,
+				 recv_wc->wc->pkey_index, rmpp_recv->ah, 1,
+				 hdr_len, sizeof(struct ib_rmpp_mad) - hdr_len,
+				 GFP_KERNEL);
+	if (!msg)
+		return;
+
+	format_ack((struct ib_rmpp_mad *) msg->mad,
+		   (struct ib_rmpp_mad *) recv_wc->recv_buf.mad, rmpp_recv);
+	ret = ib_post_send_mad(&rmpp_recv->agent->agent, &msg->send_wr,
+			       &bad_send_wr);
+	if (ret)
+		ib_free_send_mad(msg);
+}
+
+static inline int get_last_flag(struct ib_mad_recv_buf *seg)
+{
+	struct ib_rmpp_mad *rmpp_mad;
+
+	rmpp_mad = (struct ib_rmpp_mad *) seg->mad;
+	return ib_get_rmpp_flags(&rmpp_mad->rmpp_hdr) & IB_MGMT_RMPP_FLAG_LAST;
+}
+
+static inline int get_seg_num(struct ib_mad_recv_buf *seg)
+{
+	struct ib_rmpp_mad *rmpp_mad;
+
+	rmpp_mad = (struct ib_rmpp_mad *) seg->mad;
+	return be32_to_cpu(rmpp_mad->rmpp_hdr.seg_num);
+}
+
+static inline struct ib_mad_recv_buf * get_next_seg(struct list_head *rmpp_list,
+						    struct ib_mad_recv_buf *seg)
+{
+	if (seg->list.next == rmpp_list)
+		return NULL;
+
+	return container_of(seg->list.next, struct ib_mad_recv_buf, list);
+}
+
+static inline int window_size(struct ib_mad_agent_private *agent)
+{
+	return max(agent->qp_info->recv_queue.max_active >> 3, 1);
+}
+
+static struct ib_mad_recv_buf * find_seg_location(struct list_head *rmpp_list,
+						  int seg_num)
+{
+        struct ib_mad_recv_buf *seg_buf;
+	int cur_seg_num;
+
+	list_for_each_entry_reverse(seg_buf, rmpp_list, list) {
+		cur_seg_num = get_seg_num(seg_buf);
+		if (seg_num > cur_seg_num)
+			return seg_buf;
+		if (seg_num == cur_seg_num)
+			break;
+	}
+	return NULL;
+}
+
+static void update_seg_num(struct mad_rmpp_recv *rmpp_recv,
+			   struct ib_mad_recv_buf *new_buf)
+{
+	struct list_head *rmpp_list = &rmpp_recv->rmpp_wc->rmpp_list;
+
+	while (new_buf && (get_seg_num(new_buf) == rmpp_recv->seg_num + 1)) {
+		rmpp_recv->cur_seg_buf = new_buf;
+		rmpp_recv->seg_num++;
+		new_buf = get_next_seg(rmpp_list, new_buf);
+	}
+}
+
+static inline int get_mad_len(struct mad_rmpp_recv *rmpp_recv)
+{
+	struct ib_rmpp_mad *rmpp_mad;
+	int hdr_size, data_size, pad;
+
+	rmpp_mad = (struct ib_rmpp_mad *)rmpp_recv->cur_seg_buf->mad;
+
+	hdr_size = data_offset(rmpp_mad->mad_hdr.mgmt_class);
+	data_size = sizeof(struct ib_rmpp_mad) - hdr_size;
+	pad = data_size - be32_to_cpu(rmpp_mad->rmpp_hdr.paylen_newwin);
+	if (pad > data_size || pad < 0)
+		pad = 0;
+
+	return hdr_size + rmpp_recv->seg_num * data_size - pad;
+}
+
+static struct ib_mad_recv_wc * complete_rmpp(struct mad_rmpp_recv *rmpp_recv)
+{
+	struct ib_mad_recv_wc *rmpp_wc;
+
+	ack_recv(rmpp_recv, rmpp_recv->rmpp_wc);
+	if (rmpp_recv->seg_num > 1)
+		cancel_delayed_work(&rmpp_recv->timeout_work);
+
+	rmpp_wc = rmpp_recv->rmpp_wc;
+	rmpp_wc->mad_len = get_mad_len(rmpp_recv);
+	/* 10 seconds until we can find the packet lifetime */
+	queue_delayed_work(rmpp_recv->agent->qp_info->port_priv->wq,
+			   &rmpp_recv->cleanup_work, msecs_to_jiffies(10000));
+	return rmpp_wc;
+}
+
+void ib_coalesce_recv_mad(struct ib_mad_recv_wc *mad_recv_wc, void *buf)
+{
+	struct ib_mad_recv_buf *seg_buf;
+	struct ib_rmpp_mad *rmpp_mad;
+	void *data;
+	int size, len, offset;
+	u8 flags;
+
+	len = mad_recv_wc->mad_len;
+	if (len <= sizeof(struct ib_mad)) {
+		memcpy(buf, mad_recv_wc->recv_buf.mad, len);
+		return;
+	}
+
+	offset = data_offset(mad_recv_wc->recv_buf.mad->mad_hdr.mgmt_class);
+
+	list_for_each_entry(seg_buf, &mad_recv_wc->rmpp_list, list) {
+		rmpp_mad = (struct ib_rmpp_mad *)seg_buf->mad;
+		flags = ib_get_rmpp_flags(&rmpp_mad->rmpp_hdr);
+
+		if (flags & IB_MGMT_RMPP_FLAG_FIRST) {
+			data = rmpp_mad;
+			size = sizeof(*rmpp_mad);
+		} else {
+			data = (void *) rmpp_mad + offset;
+			if (flags & IB_MGMT_RMPP_FLAG_LAST)
+				size = len;
+			else
+				size = sizeof(*rmpp_mad) - offset;
+		}
+
+		memcpy(buf, data, size);
+		len -= size;
+		buf += size;
+	}
+}
+EXPORT_SYMBOL(ib_coalesce_recv_mad);
+
+static struct ib_mad_recv_wc *
+continue_rmpp(struct ib_mad_agent_private *agent,
+	      struct ib_mad_recv_wc *mad_recv_wc)
+{
+	struct mad_rmpp_recv *rmpp_recv;
+	struct ib_mad_recv_buf *prev_buf;
+	struct ib_mad_recv_wc *done_wc;
+	int seg_num;
+	unsigned long flags;
+
+	rmpp_recv = acquire_rmpp_recv(agent, mad_recv_wc);
+	if (!rmpp_recv)
+		goto drop1;
+
+	seg_num = get_seg_num(&mad_recv_wc->recv_buf);
+
+	spin_lock_irqsave(&rmpp_recv->lock, flags);
+	if ((rmpp_recv->state == RMPP_STATE_TIMEOUT) ||
+	    (seg_num > rmpp_recv->newwin))
+		goto drop3;
+
+	if ((seg_num <= rmpp_recv->last_ack) ||
+	    (rmpp_recv->state == RMPP_STATE_COMPLETE)) {
+		spin_unlock_irqrestore(&rmpp_recv->lock, flags);
+		ack_recv(rmpp_recv, mad_recv_wc);
+		goto drop2;
+	}
+
+	prev_buf = find_seg_location(&rmpp_recv->rmpp_wc->rmpp_list, seg_num);
+	if (!prev_buf)
+		goto drop3;
+
+	done_wc = NULL;
+	list_add(&mad_recv_wc->recv_buf.list, &prev_buf->list);
+	if (rmpp_recv->cur_seg_buf == prev_buf) {
+		update_seg_num(rmpp_recv, &mad_recv_wc->recv_buf);
+		if (get_last_flag(rmpp_recv->cur_seg_buf)) {
+			rmpp_recv->state = RMPP_STATE_COMPLETE;
+			spin_unlock_irqrestore(&rmpp_recv->lock, flags);
+			done_wc = complete_rmpp(rmpp_recv);
+			goto out;
+		} else if (rmpp_recv->seg_num == rmpp_recv->newwin) {
+			rmpp_recv->newwin += window_size(agent);
+			spin_unlock_irqrestore(&rmpp_recv->lock, flags);
+			ack_recv(rmpp_recv, mad_recv_wc);
+			goto out;
+		}
+	}
+	spin_unlock_irqrestore(&rmpp_recv->lock, flags);
+out:
+	deref_rmpp_recv(rmpp_recv);
+	return done_wc;
+
+drop3:	spin_unlock_irqrestore(&rmpp_recv->lock, flags);
+drop2:	deref_rmpp_recv(rmpp_recv);
+drop1:	ib_free_recv_mad(mad_recv_wc);
+	return NULL;
+}
+
+static struct ib_mad_recv_wc *
+start_rmpp(struct ib_mad_agent_private *agent,
+	   struct ib_mad_recv_wc *mad_recv_wc)
+{
+	struct mad_rmpp_recv *rmpp_recv;
+	unsigned long flags;
+
+	rmpp_recv = create_rmpp_recv(agent, mad_recv_wc);
+	if (!rmpp_recv) {
+		ib_free_recv_mad(mad_recv_wc);
+		return NULL;
+	}
+
+	spin_lock_irqsave(&agent->lock, flags);
+	if (insert_rmpp_recv(agent, rmpp_recv)) {
+		spin_unlock_irqrestore(&agent->lock, flags);
+		/* duplicate first MAD */
+		destroy_rmpp_recv(rmpp_recv);
+		return continue_rmpp(agent, mad_recv_wc);
+	}
+	atomic_inc(&rmpp_recv->refcount);
+
+	if (get_last_flag(&mad_recv_wc->recv_buf)) {
+		rmpp_recv->state = RMPP_STATE_COMPLETE;
+		spin_unlock_irqrestore(&agent->lock, flags);
+		complete_rmpp(rmpp_recv);
+	} else {
+		spin_unlock_irqrestore(&agent->lock, flags);
+		/* 40 seconds until we can find the packet lifetimes */
+		queue_delayed_work(agent->qp_info->port_priv->wq,
+				   &rmpp_recv->timeout_work,
+				   msecs_to_jiffies(40000));
+		rmpp_recv->newwin += window_size(agent);
+		ack_recv(rmpp_recv, mad_recv_wc);
+		mad_recv_wc = NULL;
+	}
+	deref_rmpp_recv(rmpp_recv);
+	return mad_recv_wc;
+}
+
+static inline u64 get_seg_addr(struct ib_mad_send_wr_private *mad_send_wr)
+{
+	return mad_send_wr->sg_list[0].addr + mad_send_wr->data_offset +
+	       (sizeof(struct ib_rmpp_mad) - mad_send_wr->data_offset) *
+	       (mad_send_wr->seg_num - 1);
+}
+
+static int send_next_seg(struct ib_mad_send_wr_private *mad_send_wr)
+{
+	struct ib_rmpp_mad *rmpp_mad;
+	int timeout;
+
+	rmpp_mad = (struct ib_rmpp_mad *)mad_send_wr->send_wr.wr.ud.mad_hdr;
+	ib_set_rmpp_flags(&rmpp_mad->rmpp_hdr, IB_MGMT_RMPP_FLAG_ACTIVE);
+	rmpp_mad->rmpp_hdr.seg_num = cpu_to_be32(mad_send_wr->seg_num);
+
+	if (mad_send_wr->seg_num == 1) {
+		rmpp_mad->rmpp_hdr.rmpp_rtime_flags |= IB_MGMT_RMPP_FLAG_FIRST;
+		rmpp_mad->rmpp_hdr.paylen_newwin =
+			cpu_to_be32(mad_send_wr->total_seg *
+				    (sizeof(struct ib_rmpp_mad) -
+				       offsetof(struct ib_rmpp_mad, data)));
+		mad_send_wr->sg_list[0].length = sizeof(struct ib_rmpp_mad);
+	} else {
+		mad_send_wr->send_wr.num_sge = 2;
+		mad_send_wr->sg_list[0].length = mad_send_wr->data_offset;
+		mad_send_wr->sg_list[1].addr = get_seg_addr(mad_send_wr);
+		mad_send_wr->sg_list[1].length = sizeof(struct ib_rmpp_mad) -
+						 mad_send_wr->data_offset;
+		mad_send_wr->sg_list[1].lkey = mad_send_wr->sg_list[0].lkey;
+	}
+
+	if (mad_send_wr->seg_num == mad_send_wr->total_seg) {
+		rmpp_mad->rmpp_hdr.rmpp_rtime_flags |= IB_MGMT_RMPP_FLAG_LAST;
+		rmpp_mad->rmpp_hdr.paylen_newwin =
+			cpu_to_be32(sizeof(struct ib_rmpp_mad) -
+				    offsetof(struct ib_rmpp_mad, data) -
+				    mad_send_wr->pad);
+	}
+
+	/* 2 seconds for an ACK until we can find the packet lifetime */
+	timeout = mad_send_wr->send_wr.wr.ud.timeout_ms;
+	if (!timeout || timeout > 2000)
+		mad_send_wr->timeout = msecs_to_jiffies(2000);
+	mad_send_wr->seg_num++;
+	return ib_send_mad(mad_send_wr);
+}
+
+static void process_rmpp_ack(struct ib_mad_agent_private *agent,
+			     struct ib_mad_recv_wc *mad_recv_wc)
+{
+	struct ib_mad_send_wr_private *mad_send_wr;
+	struct ib_rmpp_mad *rmpp_mad;
+	unsigned long flags;
+	int seg_num, newwin, ret;
+
+	rmpp_mad = (struct ib_rmpp_mad *)mad_recv_wc->recv_buf.mad;
+	if (rmpp_mad->rmpp_hdr.rmpp_status)
+		return;
+
+	seg_num = be32_to_cpu(rmpp_mad->rmpp_hdr.seg_num);
+	newwin = be32_to_cpu(rmpp_mad->rmpp_hdr.paylen_newwin);
+
+	spin_lock_irqsave(&agent->lock, flags);
+	mad_send_wr = ib_find_send_mad(agent, rmpp_mad->mad_hdr.tid);
+	if (!mad_send_wr)
+		goto out;	/* Unmatched ACK */
+
+	if ((mad_send_wr->last_ack == mad_send_wr->total_seg) ||
+	    (!mad_send_wr->timeout) || (mad_send_wr->status != IB_WC_SUCCESS))
+		goto out;	/* Send is already done */
+
+	if (seg_num > mad_send_wr->total_seg)
+		goto out;	/* Bad ACK */
+
+	if (newwin < mad_send_wr->newwin || seg_num < mad_send_wr->last_ack)
+		goto out;	/* Old ACK */
+
+	if (seg_num > mad_send_wr->last_ack) {
+		mad_send_wr->last_ack = seg_num;
+		mad_send_wr->retries = mad_send_wr->send_wr.wr.ud.retries;
+	}
+	mad_send_wr->newwin = newwin;
+	if (mad_send_wr->last_ack == mad_send_wr->total_seg) {
+		/* If no response is expected, the ACK completes the send */
+		if (!mad_send_wr->send_wr.wr.ud.timeout_ms) {
+			struct ib_mad_send_wc wc;
+
+			ib_mark_mad_done(mad_send_wr);
+			spin_unlock_irqrestore(&agent->lock, flags);
+
+			wc.status = IB_WC_SUCCESS;
+			wc.vendor_err = 0;
+			wc.wr_id = mad_send_wr->wr_id;
+			ib_mad_complete_send_wr(mad_send_wr, &wc);
+			return;
+		}
+		if (mad_send_wr->refcount == 1)
+			ib_reset_mad_timeout(mad_send_wr, mad_send_wr->
+					     send_wr.wr.ud.timeout_ms);
+	} else if (mad_send_wr->refcount == 1 &&
+		   mad_send_wr->seg_num < mad_send_wr->newwin &&
+		   mad_send_wr->seg_num <= mad_send_wr->total_seg) {
+		/* Send failure will just result in a timeout/retry */
+		ret = send_next_seg(mad_send_wr);
+		if (ret)
+			goto out;
+
+		mad_send_wr->refcount++;
+		list_del(&mad_send_wr->agent_list);
+		list_add_tail(&mad_send_wr->agent_list,
+			      &mad_send_wr->mad_agent_priv->send_list);
+	}
+out:
+	spin_unlock_irqrestore(&agent->lock, flags);
+}
+
+struct ib_mad_recv_wc *
+ib_process_rmpp_recv_wc(struct ib_mad_agent_private *agent,
+			struct ib_mad_recv_wc *mad_recv_wc)
+{
+	struct ib_rmpp_mad *rmpp_mad;
+
+	rmpp_mad = (struct ib_rmpp_mad *)mad_recv_wc->recv_buf.mad;
+	if (!(rmpp_mad->rmpp_hdr.rmpp_rtime_flags & IB_MGMT_RMPP_FLAG_ACTIVE))
+		return mad_recv_wc;
+
+	if (rmpp_mad->rmpp_hdr.rmpp_version != IB_MGMT_RMPP_VERSION)
+		goto out;
+
+	switch (rmpp_mad->rmpp_hdr.rmpp_type) {
+	case IB_MGMT_RMPP_TYPE_DATA:
+		if (rmpp_mad->rmpp_hdr.seg_num == __constant_htonl(1))
+			return start_rmpp(agent, mad_recv_wc);
+		else
+			return continue_rmpp(agent, mad_recv_wc);
+	case IB_MGMT_RMPP_TYPE_ACK:
+		process_rmpp_ack(agent, mad_recv_wc);
+		break;
+	case IB_MGMT_RMPP_TYPE_STOP:
+	case IB_MGMT_RMPP_TYPE_ABORT:
+		/* TODO: process_rmpp_nack(agent, mad_recv_wc); */
+		break;
+	default:
+		break;
+	}
+out:
+	ib_free_recv_mad(mad_recv_wc);
+	return NULL;
+}
+
+int ib_send_rmpp_mad(struct ib_mad_send_wr_private *mad_send_wr)
+{
+	struct ib_rmpp_mad *rmpp_mad;
+	int i, total_len, ret;
+
+	rmpp_mad = (struct ib_rmpp_mad *)mad_send_wr->send_wr.wr.ud.mad_hdr;
+	if (!(ib_get_rmpp_flags(&rmpp_mad->rmpp_hdr) &
+	      IB_MGMT_RMPP_FLAG_ACTIVE))
+		return IB_RMPP_RESULT_UNHANDLED;
+
+	if (rmpp_mad->rmpp_hdr.rmpp_type != IB_MGMT_RMPP_TYPE_DATA)
+		return IB_RMPP_RESULT_INTERNAL;
+
+	if (mad_send_wr->send_wr.num_sge > 1)
+		return -EINVAL;		/* TODO: support num_sge > 1 */
+
+	mad_send_wr->seg_num = 1;
+	mad_send_wr->newwin = 1;
+	mad_send_wr->data_offset = data_offset(rmpp_mad->mad_hdr.mgmt_class);
+
+	total_len = 0;
+	for (i = 0; i < mad_send_wr->send_wr.num_sge; i++)
+		total_len += mad_send_wr->send_wr.sg_list[i].length;
+
+        mad_send_wr->total_seg = (total_len - mad_send_wr->data_offset) /
+			(sizeof(struct ib_rmpp_mad) - mad_send_wr->data_offset);
+	mad_send_wr->pad = total_len - offsetof(struct ib_rmpp_mad, data) -
+			   be32_to_cpu(rmpp_mad->rmpp_hdr.paylen_newwin);
+
+	/* We need to wait for the final ACK even if there isn't a response */
+	mad_send_wr->refcount += (mad_send_wr->timeout == 0);
+	ret = send_next_seg(mad_send_wr);
+	if (!ret)
+		return IB_RMPP_RESULT_CONSUMED;
+	return ret;
+}
+
+int ib_process_rmpp_send_wc(struct ib_mad_send_wr_private *mad_send_wr,
+			    struct ib_mad_send_wc *mad_send_wc)
+{
+	struct ib_rmpp_mad *rmpp_mad;
+	struct ib_mad_send_buf *msg;
+	int ret;
+
+	rmpp_mad = (struct ib_rmpp_mad *)mad_send_wr->send_wr.wr.ud.mad_hdr;
+	if (!(ib_get_rmpp_flags(&rmpp_mad->rmpp_hdr) &
+	      IB_MGMT_RMPP_FLAG_ACTIVE))
+		return IB_RMPP_RESULT_UNHANDLED; /* RMPP not active */
+
+	if (rmpp_mad->rmpp_hdr.rmpp_type != IB_MGMT_RMPP_TYPE_DATA) {
+		msg = (struct ib_mad_send_buf *) (unsigned long)
+		      mad_send_wc->wr_id;
+		ib_free_send_mad(msg);
+		return IB_RMPP_RESULT_INTERNAL;	 /* ACK, STOP, or ABORT */
+	}
+
+	if (mad_send_wc->status != IB_WC_SUCCESS ||
+	    mad_send_wr->status != IB_WC_SUCCESS)
+		return IB_RMPP_RESULT_PROCESSED; /* Canceled or send error */
+
+	if (!mad_send_wr->timeout)
+		return IB_RMPP_RESULT_PROCESSED; /* Response received */
+
+	if (mad_send_wr->last_ack == mad_send_wr->total_seg) {
+		mad_send_wr->timeout =
+			msecs_to_jiffies(mad_send_wr->send_wr.wr.ud.timeout_ms);
+		return IB_RMPP_RESULT_PROCESSED; /* Send done */
+	}
+
+	if (mad_send_wr->seg_num > mad_send_wr->newwin ||
+	    mad_send_wr->seg_num > mad_send_wr->total_seg)
+		return IB_RMPP_RESULT_PROCESSED; /* Wait for ACK */
+
+	ret = send_next_seg(mad_send_wr);
+	if (ret) {
+		mad_send_wc->status = IB_WC_GENERAL_ERR;
+		return IB_RMPP_RESULT_PROCESSED;
+	}
+	return IB_RMPP_RESULT_CONSUMED;
+}
+
+int ib_retry_rmpp(struct ib_mad_send_wr_private *mad_send_wr)
+{
+	struct ib_rmpp_mad *rmpp_mad;
+	int ret;
+
+	rmpp_mad = (struct ib_rmpp_mad *)mad_send_wr->send_wr.wr.ud.mad_hdr;
+	if (!(ib_get_rmpp_flags(&rmpp_mad->rmpp_hdr) &
+	      IB_MGMT_RMPP_FLAG_ACTIVE))
+		return IB_RMPP_RESULT_UNHANDLED; /* RMPP not active */
+
+	if (mad_send_wr->last_ack == mad_send_wr->total_seg)
+		return IB_RMPP_RESULT_PROCESSED;
+
+	mad_send_wr->seg_num = mad_send_wr->last_ack + 1;
+	ret = send_next_seg(mad_send_wr);
+	if (ret)
+		return IB_RMPP_RESULT_PROCESSED;
+
+	return IB_RMPP_RESULT_CONSUMED;
+}
diff --git a/drivers/infiniband/core/mad_rmpp.h b/drivers/infiniband/core/mad_rmpp.h
new file mode 100644
index 00000000000..c4924dfb8e7
--- /dev/null
+++ b/drivers/infiniband/core/mad_rmpp.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2005 Intel Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * $Id: mad_rmpp.h 1921 2005-02-25 22:58:44Z sean.hefty $
+ */
+
+#ifndef __MAD_RMPP_H__
+#define __MAD_RMPP_H__
+
+enum {
+	IB_RMPP_RESULT_PROCESSED,
+	IB_RMPP_RESULT_CONSUMED,
+	IB_RMPP_RESULT_INTERNAL,
+	IB_RMPP_RESULT_UNHANDLED
+};
+
+int ib_send_rmpp_mad(struct ib_mad_send_wr_private *mad_send_wr);
+
+struct ib_mad_recv_wc *
+ib_process_rmpp_recv_wc(struct ib_mad_agent_private *agent,
+			struct ib_mad_recv_wc *mad_recv_wc);
+
+int ib_process_rmpp_send_wc(struct ib_mad_send_wr_private *mad_send_wr,
+			    struct ib_mad_send_wc *mad_send_wc);
+
+void ib_cancel_rmpp_recvs(struct ib_mad_agent_private *agent);
+
+int ib_retry_rmpp(struct ib_mad_send_wr_private *mad_send_wr);
+
+#endif	/* __MAD_RMPP_H__ */
diff --git a/drivers/infiniband/core/sa_query.c b/drivers/infiniband/core/sa_query.c
index 5a08e81fa82..795184931c8 100644
--- a/drivers/infiniband/core/sa_query.c
+++ b/drivers/infiniband/core/sa_query.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
+ * Copyright (c) 2005 Voltaire, Inc.  All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
@@ -29,7 +30,7 @@
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
  *
- * $Id: sa_query.c 1389 2004-12-27 22:56:47Z roland $
+ * $Id: sa_query.c 2811 2005-07-06 18:11:43Z halr $
  */
 
 #include <linux/module.h>
@@ -50,26 +51,6 @@ MODULE_AUTHOR("Roland Dreier");
 MODULE_DESCRIPTION("InfiniBand subnet administration query support");
 MODULE_LICENSE("Dual BSD/GPL");
 
-/*
- * These two structures must be packed because they have 64-bit fields
- * that are only 32-bit aligned.  64-bit architectures will lay them
- * out wrong otherwise.  (And unfortunately they are sent on the wire
- * so we can't change the layout)
- */
-struct ib_sa_hdr {
-	u64			sm_key;
-	u16			attr_offset;
-	u16			reserved;
-	ib_sa_comp_mask		comp_mask;
-} __attribute__ ((packed));
-
-struct ib_sa_mad {
-	struct ib_mad_hdr	mad_hdr;
-	struct ib_rmpp_hdr	rmpp_hdr;
-	struct ib_sa_hdr	sa_hdr;
-	u8			data[200];
-} __attribute__ ((packed));
-
 struct ib_sa_sm_ah {
 	struct ib_ah        *ah;
 	struct kref          ref;
@@ -77,7 +58,6 @@ struct ib_sa_sm_ah {
 
 struct ib_sa_port {
 	struct ib_mad_agent *agent;
-	struct ib_mr        *mr;
 	struct ib_sa_sm_ah  *sm_ah;
 	struct work_struct   update_task;
 	spinlock_t           ah_lock;
@@ -100,6 +80,12 @@ struct ib_sa_query {
 	int                 id;
 };
 
+struct ib_sa_service_query {
+	void (*callback)(int, struct ib_sa_service_rec *, void *);
+	void *context;
+	struct ib_sa_query sa_query;
+};
+
 struct ib_sa_path_query {
 	void (*callback)(int, struct ib_sa_path_rec *, void *);
 	void *context;
@@ -341,6 +327,54 @@ static const struct ib_field mcmember_rec_table[] = {
 	  .size_bits    = 23 },
 };
 
+#define SERVICE_REC_FIELD(field) \
+	.struct_offset_bytes = offsetof(struct ib_sa_service_rec, field),	\
+	.struct_size_bytes   = sizeof ((struct ib_sa_service_rec *) 0)->field,	\
+	.field_name          = "sa_service_rec:" #field
+
+static const struct ib_field service_rec_table[] = {
+	{ SERVICE_REC_FIELD(id),
+	  .offset_words = 0,
+	  .offset_bits  = 0,
+	  .size_bits    = 64 },
+	{ SERVICE_REC_FIELD(gid),
+	  .offset_words = 2,
+	  .offset_bits  = 0,
+	  .size_bits    = 128 },
+	{ SERVICE_REC_FIELD(pkey),
+	  .offset_words = 6,
+	  .offset_bits  = 0,
+	  .size_bits    = 16 },
+	{ SERVICE_REC_FIELD(lease),
+	  .offset_words = 7,
+	  .offset_bits  = 0,
+	  .size_bits    = 32 },
+	{ SERVICE_REC_FIELD(key),
+	  .offset_words = 8,
+	  .offset_bits  = 0,
+	  .size_bits    = 128 },
+	{ SERVICE_REC_FIELD(name),
+	  .offset_words = 12,
+	  .offset_bits  = 0,
+	  .size_bits    = 64*8 },
+	{ SERVICE_REC_FIELD(data8),
+	  .offset_words = 28,
+	  .offset_bits  = 0,
+	  .size_bits    = 16*8 },
+	{ SERVICE_REC_FIELD(data16),
+	  .offset_words = 32,
+	  .offset_bits  = 0,
+	  .size_bits    = 8*16 },
+	{ SERVICE_REC_FIELD(data32),
+	  .offset_words = 36,
+	  .offset_bits  = 0,
+	  .size_bits    = 4*32 },
+	{ SERVICE_REC_FIELD(data64),
+	  .offset_words = 40,
+	  .offset_bits  = 0,
+	  .size_bits    = 2*64 },
+};
+
 static void free_sm_ah(struct kref *kref)
 {
 	struct ib_sa_sm_ah *sm_ah = container_of(kref, struct ib_sa_sm_ah, ref);
@@ -463,7 +497,7 @@ static int send_mad(struct ib_sa_query *query, int timeout_ms)
 				 .mad_hdr     = &query->mad->mad_hdr,
 				 .remote_qpn  = 1,
 				 .remote_qkey = IB_QP1_QKEY,
-				 .timeout_ms  = timeout_ms
+				 .timeout_ms  = timeout_ms,
 			 }
 		 }
 	};
@@ -492,7 +526,7 @@ retry:
 					    sizeof (struct ib_sa_mad),
 					    DMA_TO_DEVICE);
 	gather_list.length = sizeof (struct ib_sa_mad);
-	gather_list.lkey   = port->mr->lkey;
+	gather_list.lkey   = port->agent->mr->lkey;
 	pci_unmap_addr_set(query, mapping, gather_list.addr);
 
 	ret = ib_post_send_mad(port->agent, &wr, &bad_wr);
@@ -566,7 +600,7 @@ static void ib_sa_path_rec_release(struct ib_sa_query *sa_query)
 int ib_sa_path_rec_get(struct ib_device *device, u8 port_num,
 		       struct ib_sa_path_rec *rec,
 		       ib_sa_comp_mask comp_mask,
-		       int timeout_ms, int gfp_mask,
+		       int timeout_ms, unsigned int __nocast gfp_mask,
 		       void (*callback)(int status,
 					struct ib_sa_path_rec *resp,
 					void *context),
@@ -616,6 +650,114 @@ int ib_sa_path_rec_get(struct ib_device *device, u8 port_num,
 }
 EXPORT_SYMBOL(ib_sa_path_rec_get);
 
+static void ib_sa_service_rec_callback(struct ib_sa_query *sa_query,
+				    int status,
+				    struct ib_sa_mad *mad)
+{
+	struct ib_sa_service_query *query =
+		container_of(sa_query, struct ib_sa_service_query, sa_query);
+
+	if (mad) {
+		struct ib_sa_service_rec rec;
+
+		ib_unpack(service_rec_table, ARRAY_SIZE(service_rec_table),
+			  mad->data, &rec);
+		query->callback(status, &rec, query->context);
+	} else
+		query->callback(status, NULL, query->context);
+}
+
+static void ib_sa_service_rec_release(struct ib_sa_query *sa_query)
+{
+	kfree(sa_query->mad);
+	kfree(container_of(sa_query, struct ib_sa_service_query, sa_query));
+}
+
+/**
+ * ib_sa_service_rec_query - Start Service Record operation
+ * @device:device to send request on
+ * @port_num: port number to send request on
+ * @method:SA method - should be get, set, or delete
+ * @rec:Service Record to send in request
+ * @comp_mask:component mask to send in request
+ * @timeout_ms:time to wait for response
+ * @gfp_mask:GFP mask to use for internal allocations
+ * @callback:function called when request completes, times out or is
+ * canceled
+ * @context:opaque user context passed to callback
+ * @sa_query:request context, used to cancel request
+ *
+ * Send a Service Record set/get/delete to the SA to register,
+ * unregister or query a service record.
+ * The callback function will be called when the request completes (or
+ * fails); status is 0 for a successful response, -EINTR if the query
+ * is canceled, -ETIMEDOUT is the query timed out, or -EIO if an error
+ * occurred sending the query.  The resp parameter of the callback is
+ * only valid if status is 0.
+ *
+ * If the return value of ib_sa_service_rec_query() is negative, it is an
+ * error code.  Otherwise it is a request ID that can be used to cancel
+ * the query.
+ */
+int ib_sa_service_rec_query(struct ib_device *device, u8 port_num, u8 method,
+			    struct ib_sa_service_rec *rec,
+			    ib_sa_comp_mask comp_mask,
+			    int timeout_ms, unsigned int __nocast gfp_mask,
+			    void (*callback)(int status,
+					     struct ib_sa_service_rec *resp,
+					     void *context),
+			    void *context,
+			    struct ib_sa_query **sa_query)
+{
+	struct ib_sa_service_query *query;
+	struct ib_sa_device *sa_dev = ib_get_client_data(device, &sa_client);
+	struct ib_sa_port   *port   = &sa_dev->port[port_num - sa_dev->start_port];
+	struct ib_mad_agent *agent  = port->agent;
+	int ret;
+
+	if (method != IB_MGMT_METHOD_GET &&
+	    method != IB_MGMT_METHOD_SET &&
+	    method != IB_SA_METHOD_DELETE)
+		return -EINVAL;
+
+	query = kmalloc(sizeof *query, gfp_mask);
+	if (!query)
+		return -ENOMEM;
+	query->sa_query.mad = kmalloc(sizeof *query->sa_query.mad, gfp_mask);
+	if (!query->sa_query.mad) {
+		kfree(query);
+		return -ENOMEM;
+	}
+
+	query->callback = callback;
+	query->context  = context;
+
+	init_mad(query->sa_query.mad, agent);
+
+	query->sa_query.callback              = callback ? ib_sa_service_rec_callback : NULL;
+	query->sa_query.release               = ib_sa_service_rec_release;
+	query->sa_query.port                  = port;
+	query->sa_query.mad->mad_hdr.method   = method;
+	query->sa_query.mad->mad_hdr.attr_id  =
+				cpu_to_be16(IB_SA_ATTR_SERVICE_REC);
+	query->sa_query.mad->sa_hdr.comp_mask = comp_mask;
+
+	ib_pack(service_rec_table, ARRAY_SIZE(service_rec_table),
+		rec, query->sa_query.mad->data);
+
+	*sa_query = &query->sa_query;
+
+	ret = send_mad(&query->sa_query, timeout_ms);
+	if (ret < 0) {
+		*sa_query = NULL;
+		kfree(query->sa_query.mad);
+		kfree(query);
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL(ib_sa_service_rec_query);
+
 static void ib_sa_mcmember_rec_callback(struct ib_sa_query *sa_query,
 					int status,
 					struct ib_sa_mad *mad)
@@ -643,7 +785,7 @@ int ib_sa_mcmember_rec_query(struct ib_device *device, u8 port_num,
 			     u8 method,
 			     struct ib_sa_mcmember_rec *rec,
 			     ib_sa_comp_mask comp_mask,
-			     int timeout_ms, int gfp_mask,
+			     int timeout_ms, unsigned int __nocast gfp_mask,
 			     void (*callback)(int status,
 					      struct ib_sa_mcmember_rec *resp,
 					      void *context),
@@ -780,7 +922,6 @@ static void ib_sa_add_one(struct ib_device *device)
 	sa_dev->end_port   = e;
 
 	for (i = 0; i <= e - s; ++i) {
-		sa_dev->port[i].mr       = NULL;
 		sa_dev->port[i].sm_ah    = NULL;
 		sa_dev->port[i].port_num = i + s;
 		spin_lock_init(&sa_dev->port[i].ah_lock);
@@ -792,13 +933,6 @@ static void ib_sa_add_one(struct ib_device *device)
 		if (IS_ERR(sa_dev->port[i].agent))
 			goto err;
 
-		sa_dev->port[i].mr = ib_get_dma_mr(sa_dev->port[i].agent->qp->pd,
-						   IB_ACCESS_LOCAL_WRITE);
-		if (IS_ERR(sa_dev->port[i].mr)) {
-			ib_unregister_mad_agent(sa_dev->port[i].agent);
-			goto err;
-		}
-
 		INIT_WORK(&sa_dev->port[i].update_task,
 			  update_sm_ah, &sa_dev->port[i]);
 	}
@@ -822,10 +956,8 @@ static void ib_sa_add_one(struct ib_device *device)
 	return;
 
 err:
-	while (--i >= 0) {
-		ib_dereg_mr(sa_dev->port[i].mr);
+	while (--i >= 0)
 		ib_unregister_mad_agent(sa_dev->port[i].agent);
-	}
 
 	kfree(sa_dev);
 
diff --git a/drivers/infiniband/core/ucm.c b/drivers/infiniband/core/ucm.c
new file mode 100644
index 00000000000..61d07c732f4
--- /dev/null
+++ b/drivers/infiniband/core/ucm.c
@@ -0,0 +1,1387 @@
+/*
+ * Copyright (c) 2005 Topspin Communications.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *	copyright notice, this list of conditions and the following
+ *	disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *	copyright notice, this list of conditions and the following
+ *	disclaimer in the documentation and/or other materials
+ *	provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * $Id: ucm.c 2594 2005-06-13 19:46:02Z libor $
+ */
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/poll.h>
+#include <linux/file.h>
+#include <linux/mount.h>
+#include <linux/cdev.h>
+
+#include <asm/uaccess.h>
+
+#include "ucm.h"
+
+MODULE_AUTHOR("Libor Michalek");
+MODULE_DESCRIPTION("InfiniBand userspace Connection Manager access");
+MODULE_LICENSE("Dual BSD/GPL");
+
+static int ucm_debug_level;
+
+module_param_named(debug_level, ucm_debug_level, int, 0644);
+MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
+
+enum {
+	IB_UCM_MAJOR = 231,
+	IB_UCM_MINOR = 255
+};
+
+#define IB_UCM_DEV MKDEV(IB_UCM_MAJOR, IB_UCM_MINOR)
+
+#define PFX "UCM: "
+
+#define ucm_dbg(format, arg...)			\
+	do {					\
+		if (ucm_debug_level > 0)	\
+			printk(KERN_DEBUG PFX format, ## arg); \
+	} while (0)
+
+static struct semaphore ctx_id_mutex;
+static struct idr       ctx_id_table;
+static int              ctx_id_rover = 0;
+
+static struct ib_ucm_context *ib_ucm_ctx_get(int id)
+{
+	struct ib_ucm_context *ctx;
+
+	down(&ctx_id_mutex);
+	ctx = idr_find(&ctx_id_table, id);
+	if (ctx)
+		ctx->ref++;
+	up(&ctx_id_mutex);
+
+	return ctx;
+}
+
+static void ib_ucm_ctx_put(struct ib_ucm_context *ctx)
+{
+	struct ib_ucm_event *uevent;
+
+	down(&ctx_id_mutex);
+
+	ctx->ref--;
+	if (!ctx->ref)
+		idr_remove(&ctx_id_table, ctx->id);
+
+	up(&ctx_id_mutex);
+
+	if (ctx->ref)
+		return;
+
+	down(&ctx->file->mutex);
+
+	list_del(&ctx->file_list);
+	while (!list_empty(&ctx->events)) {
+
+		uevent = list_entry(ctx->events.next,
+				    struct ib_ucm_event, ctx_list);
+		list_del(&uevent->file_list);
+		list_del(&uevent->ctx_list);
+
+		/* clear incoming connections. */
+		if (uevent->cm_id)
+			ib_destroy_cm_id(uevent->cm_id);
+
+		kfree(uevent);
+	}
+
+	up(&ctx->file->mutex);
+
+	ucm_dbg("Destroyed CM ID <%d>\n", ctx->id);
+
+	ib_destroy_cm_id(ctx->cm_id);
+	kfree(ctx);
+}
+
+static struct ib_ucm_context *ib_ucm_ctx_alloc(struct ib_ucm_file *file)
+{
+	struct ib_ucm_context *ctx;
+	int result;
+
+	ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
+	if (!ctx)
+		return NULL;
+
+	ctx->ref  = 1; /* user reference */
+	ctx->file = file;
+
+	INIT_LIST_HEAD(&ctx->events);
+	init_MUTEX(&ctx->mutex);
+
+	list_add_tail(&ctx->file_list, &file->ctxs);
+
+	ctx_id_rover = (ctx_id_rover + 1) & INT_MAX;
+retry:
+	result = idr_pre_get(&ctx_id_table, GFP_KERNEL);
+	if (!result)
+		goto error;
+
+	down(&ctx_id_mutex);
+	result = idr_get_new_above(&ctx_id_table, ctx, ctx_id_rover, &ctx->id);
+	up(&ctx_id_mutex);
+
+	if (result == -EAGAIN)
+		goto retry;
+	if (result)
+		goto error;
+
+	ucm_dbg("Allocated CM ID <%d>\n", ctx->id);
+
+	return ctx;
+error:
+	list_del(&ctx->file_list);
+	kfree(ctx);
+
+	return NULL;
+}
+/*
+ * Event portion of the API, handle CM events
+ * and allow event polling.
+ */
+static void ib_ucm_event_path_get(struct ib_ucm_path_rec *upath,
+				  struct ib_sa_path_rec	 *kpath)
+{
+	if (!kpath || !upath)
+		return;
+
+	memcpy(upath->dgid, kpath->dgid.raw, sizeof(union ib_gid));
+	memcpy(upath->sgid, kpath->sgid.raw, sizeof(union ib_gid));
+
+	upath->dlid             = kpath->dlid;
+	upath->slid             = kpath->slid;
+	upath->raw_traffic      = kpath->raw_traffic;
+	upath->flow_label       = kpath->flow_label;
+	upath->hop_limit        = kpath->hop_limit;
+	upath->traffic_class    = kpath->traffic_class;
+	upath->reversible       = kpath->reversible;
+	upath->numb_path        = kpath->numb_path;
+	upath->pkey             = kpath->pkey;
+	upath->sl	        = kpath->sl;
+	upath->mtu_selector     = kpath->mtu_selector;
+	upath->mtu              = kpath->mtu;
+	upath->rate_selector    = kpath->rate_selector;
+	upath->rate             = kpath->rate;
+	upath->packet_life_time = kpath->packet_life_time;
+	upath->preference       = kpath->preference;
+
+	upath->packet_life_time_selector =
+		kpath->packet_life_time_selector;
+}
+
+static void ib_ucm_event_req_get(struct ib_ucm_req_event_resp *ureq,
+				 struct ib_cm_req_event_param *kreq)
+{
+	ureq->listen_id = (long)kreq->listen_id->context;
+
+	ureq->remote_ca_guid             = kreq->remote_ca_guid;
+	ureq->remote_qkey                = kreq->remote_qkey;
+	ureq->remote_qpn                 = kreq->remote_qpn;
+	ureq->qp_type                    = kreq->qp_type;
+	ureq->starting_psn               = kreq->starting_psn;
+	ureq->responder_resources        = kreq->responder_resources;
+	ureq->initiator_depth            = kreq->initiator_depth;
+	ureq->local_cm_response_timeout  = kreq->local_cm_response_timeout;
+	ureq->flow_control               = kreq->flow_control;
+	ureq->remote_cm_response_timeout = kreq->remote_cm_response_timeout;
+	ureq->retry_count                = kreq->retry_count;
+	ureq->rnr_retry_count            = kreq->rnr_retry_count;
+	ureq->srq                        = kreq->srq;
+
+	ib_ucm_event_path_get(&ureq->primary_path, kreq->primary_path);
+	ib_ucm_event_path_get(&ureq->alternate_path, kreq->alternate_path);
+}
+
+static void ib_ucm_event_rep_get(struct ib_ucm_rep_event_resp *urep,
+				 struct ib_cm_rep_event_param *krep)
+{
+	urep->remote_ca_guid      = krep->remote_ca_guid;
+	urep->remote_qkey         = krep->remote_qkey;
+	urep->remote_qpn          = krep->remote_qpn;
+	urep->starting_psn        = krep->starting_psn;
+	urep->responder_resources = krep->responder_resources;
+	urep->initiator_depth     = krep->initiator_depth;
+	urep->target_ack_delay    = krep->target_ack_delay;
+	urep->failover_accepted   = krep->failover_accepted;
+	urep->flow_control        = krep->flow_control;
+	urep->rnr_retry_count     = krep->rnr_retry_count;
+	urep->srq                 = krep->srq;
+}
+
+static void ib_ucm_event_rej_get(struct ib_ucm_rej_event_resp *urej,
+				 struct ib_cm_rej_event_param *krej)
+{
+	urej->reason = krej->reason;
+}
+
+static void ib_ucm_event_mra_get(struct ib_ucm_mra_event_resp *umra,
+				 struct ib_cm_mra_event_param *kmra)
+{
+	umra->timeout = kmra->service_timeout;
+}
+
+static void ib_ucm_event_lap_get(struct ib_ucm_lap_event_resp *ulap,
+				 struct ib_cm_lap_event_param *klap)
+{
+	ib_ucm_event_path_get(&ulap->path, klap->alternate_path);
+}
+
+static void ib_ucm_event_apr_get(struct ib_ucm_apr_event_resp *uapr,
+				 struct ib_cm_apr_event_param *kapr)
+{
+	uapr->status = kapr->ap_status;
+}
+
+static void ib_ucm_event_sidr_req_get(struct ib_ucm_sidr_req_event_resp *ureq,
+				      struct ib_cm_sidr_req_event_param *kreq)
+{
+	ureq->listen_id = (long)kreq->listen_id->context;
+	ureq->pkey      = kreq->pkey;
+}
+
+static void ib_ucm_event_sidr_rep_get(struct ib_ucm_sidr_rep_event_resp *urep,
+				      struct ib_cm_sidr_rep_event_param *krep)
+{
+	urep->status = krep->status;
+	urep->qkey   = krep->qkey;
+	urep->qpn    = krep->qpn;
+};
+
+static int ib_ucm_event_process(struct ib_cm_event *evt,
+				struct ib_ucm_event *uvt)
+{
+	void *info = NULL;
+	int result;
+
+	switch (evt->event) {
+	case IB_CM_REQ_RECEIVED:
+		ib_ucm_event_req_get(&uvt->resp.u.req_resp,
+				     &evt->param.req_rcvd);
+		uvt->data_len      = IB_CM_REQ_PRIVATE_DATA_SIZE;
+		uvt->resp.present |= (evt->param.req_rcvd.primary_path ?
+				      IB_UCM_PRES_PRIMARY : 0);
+		uvt->resp.present |= (evt->param.req_rcvd.alternate_path ?
+				      IB_UCM_PRES_ALTERNATE : 0);
+		break;
+	case IB_CM_REP_RECEIVED:
+		ib_ucm_event_rep_get(&uvt->resp.u.rep_resp,
+				     &evt->param.rep_rcvd);
+		uvt->data_len = IB_CM_REP_PRIVATE_DATA_SIZE;
+
+		break;
+	case IB_CM_RTU_RECEIVED:
+		uvt->data_len = IB_CM_RTU_PRIVATE_DATA_SIZE;
+		uvt->resp.u.send_status = evt->param.send_status;
+
+		break;
+	case IB_CM_DREQ_RECEIVED:
+		uvt->data_len = IB_CM_DREQ_PRIVATE_DATA_SIZE;
+		uvt->resp.u.send_status = evt->param.send_status;
+
+		break;
+	case IB_CM_DREP_RECEIVED:
+		uvt->data_len = IB_CM_DREP_PRIVATE_DATA_SIZE;
+		uvt->resp.u.send_status = evt->param.send_status;
+
+		break;
+	case IB_CM_MRA_RECEIVED:
+		ib_ucm_event_mra_get(&uvt->resp.u.mra_resp,
+				     &evt->param.mra_rcvd);
+		uvt->data_len = IB_CM_MRA_PRIVATE_DATA_SIZE;
+
+		break;
+	case IB_CM_REJ_RECEIVED:
+		ib_ucm_event_rej_get(&uvt->resp.u.rej_resp,
+				     &evt->param.rej_rcvd);
+		uvt->data_len = IB_CM_REJ_PRIVATE_DATA_SIZE;
+		uvt->info_len = evt->param.rej_rcvd.ari_length;
+		info	      = evt->param.rej_rcvd.ari;
+
+		break;
+	case IB_CM_LAP_RECEIVED:
+		ib_ucm_event_lap_get(&uvt->resp.u.lap_resp,
+				     &evt->param.lap_rcvd);
+		uvt->data_len = IB_CM_LAP_PRIVATE_DATA_SIZE;
+		uvt->resp.present |= (evt->param.lap_rcvd.alternate_path ?
+				      IB_UCM_PRES_ALTERNATE : 0);
+		break;
+	case IB_CM_APR_RECEIVED:
+		ib_ucm_event_apr_get(&uvt->resp.u.apr_resp,
+				     &evt->param.apr_rcvd);
+		uvt->data_len = IB_CM_APR_PRIVATE_DATA_SIZE;
+		uvt->info_len = evt->param.apr_rcvd.info_len;
+		info	      = evt->param.apr_rcvd.apr_info;
+
+		break;
+	case IB_CM_SIDR_REQ_RECEIVED:
+		ib_ucm_event_sidr_req_get(&uvt->resp.u.sidr_req_resp,
+					  &evt->param.sidr_req_rcvd);
+		uvt->data_len = IB_CM_SIDR_REQ_PRIVATE_DATA_SIZE;
+
+		break;
+	case IB_CM_SIDR_REP_RECEIVED:
+		ib_ucm_event_sidr_rep_get(&uvt->resp.u.sidr_rep_resp,
+					  &evt->param.sidr_rep_rcvd);
+		uvt->data_len = IB_CM_SIDR_REP_PRIVATE_DATA_SIZE;
+		uvt->info_len = evt->param.sidr_rep_rcvd.info_len;
+		info	      = evt->param.sidr_rep_rcvd.info;
+
+		break;
+	default:
+		uvt->resp.u.send_status = evt->param.send_status;
+
+		break;
+	}
+
+	if (uvt->data_len && evt->private_data) {
+
+		uvt->data = kmalloc(uvt->data_len, GFP_KERNEL);
+		if (!uvt->data) {
+			result = -ENOMEM;
+			goto error;
+		}
+
+		memcpy(uvt->data, evt->private_data, uvt->data_len);
+		uvt->resp.present |= IB_UCM_PRES_DATA;
+	}
+
+	if (uvt->info_len && info) {
+
+		uvt->info = kmalloc(uvt->info_len, GFP_KERNEL);
+		if (!uvt->info) {
+			result = -ENOMEM;
+			goto error;
+		}
+
+		memcpy(uvt->info, info, uvt->info_len);
+		uvt->resp.present |= IB_UCM_PRES_INFO;
+	}
+
+	return 0;
+error:
+	kfree(uvt->info);
+	kfree(uvt->data);
+	return result;
+}
+
+static int ib_ucm_event_handler(struct ib_cm_id *cm_id,
+				struct ib_cm_event *event)
+{
+	struct ib_ucm_event *uevent;
+	struct ib_ucm_context *ctx;
+	int result = 0;
+	int id;
+	/*
+	 * lookup correct context based on event type.
+	 */
+	switch (event->event) {
+	case IB_CM_REQ_RECEIVED:
+		id = (long)event->param.req_rcvd.listen_id->context;
+		break;
+	case IB_CM_SIDR_REQ_RECEIVED:
+		id = (long)event->param.sidr_req_rcvd.listen_id->context;
+		break;
+	default:
+		id = (long)cm_id->context;
+		break;
+	}
+
+	ucm_dbg("Event. CM ID <%d> event <%d>\n", id, event->event);
+
+	ctx = ib_ucm_ctx_get(id);
+	if (!ctx)
+		return -ENOENT;
+
+	if (event->event == IB_CM_REQ_RECEIVED ||
+	    event->event == IB_CM_SIDR_REQ_RECEIVED)
+		id = IB_UCM_CM_ID_INVALID;
+
+	uevent = kmalloc(sizeof(*uevent), GFP_KERNEL);
+	if (!uevent) {
+		result = -ENOMEM;
+		goto done;
+	}
+
+	memset(uevent, 0, sizeof(*uevent));
+
+	uevent->resp.id    = id;
+	uevent->resp.event = event->event;
+
+	result = ib_ucm_event_process(event, uevent);
+	if (result)
+		goto done;
+
+	uevent->ctx   = ctx;
+	uevent->cm_id = ((event->event == IB_CM_REQ_RECEIVED ||
+			  event->event == IB_CM_SIDR_REQ_RECEIVED ) ?
+			 cm_id : NULL);
+
+	down(&ctx->file->mutex);
+
+	list_add_tail(&uevent->file_list, &ctx->file->events);
+	list_add_tail(&uevent->ctx_list, &ctx->events);
+
+	wake_up_interruptible(&ctx->file->poll_wait);
+
+	up(&ctx->file->mutex);
+done:
+	ctx->error = result;
+	ib_ucm_ctx_put(ctx); /* func reference */
+	return result;
+}
+
+static ssize_t ib_ucm_event(struct ib_ucm_file *file,
+			    const char __user *inbuf,
+			    int in_len, int out_len)
+{
+	struct ib_ucm_context *ctx;
+	struct ib_ucm_event_get cmd;
+	struct ib_ucm_event *uevent = NULL;
+	int result = 0;
+	DEFINE_WAIT(wait);
+
+	if (out_len < sizeof(struct ib_ucm_event_resp))
+		return -ENOSPC;
+
+	if (copy_from_user(&cmd, inbuf, sizeof(cmd)))
+		return -EFAULT;
+	/*
+	 * wait
+	 */
+	down(&file->mutex);
+
+	while (list_empty(&file->events)) {
+
+		if (file->filp->f_flags & O_NONBLOCK) {
+			result = -EAGAIN;
+			break;
+		}
+
+		if (signal_pending(current)) {
+			result = -ERESTARTSYS;
+			break;
+		}
+
+		prepare_to_wait(&file->poll_wait, &wait, TASK_INTERRUPTIBLE);
+
+		up(&file->mutex);
+		schedule();
+		down(&file->mutex);
+
+		finish_wait(&file->poll_wait, &wait);
+	}
+
+	if (result)
+		goto done;
+
+	uevent = list_entry(file->events.next, struct ib_ucm_event, file_list);
+
+	if (!uevent->cm_id)
+		goto user;
+
+	ctx = ib_ucm_ctx_alloc(file);
+	if (!ctx) {
+		result = -ENOMEM;
+		goto done;
+	}
+
+	ctx->cm_id             = uevent->cm_id;
+	ctx->cm_id->cm_handler = ib_ucm_event_handler;
+	ctx->cm_id->context    = (void *)(unsigned long)ctx->id;
+
+	uevent->resp.id = ctx->id;
+
+user:
+	if (copy_to_user((void __user *)(unsigned long)cmd.response,
+			 &uevent->resp, sizeof(uevent->resp))) {
+		result = -EFAULT;
+		goto done;
+	}
+
+	if (uevent->data) {
+
+		if (cmd.data_len < uevent->data_len) {
+			result = -ENOMEM;
+			goto done;
+		}
+
+		if (copy_to_user((void __user *)(unsigned long)cmd.data,
+				 uevent->data, uevent->data_len)) {
+			result = -EFAULT;
+			goto done;
+		}
+	}
+
+	if (uevent->info) {
+
+		if (cmd.info_len < uevent->info_len) {
+			result = -ENOMEM;
+			goto done;
+		}
+
+		if (copy_to_user((void __user *)(unsigned long)cmd.info,
+				 uevent->info, uevent->info_len)) {
+			result = -EFAULT;
+			goto done;
+		}
+	}
+
+	list_del(&uevent->file_list);
+	list_del(&uevent->ctx_list);
+
+	kfree(uevent->data);
+	kfree(uevent->info);
+	kfree(uevent);
+done:
+	up(&file->mutex);
+	return result;
+}
+
+
+static ssize_t ib_ucm_create_id(struct ib_ucm_file *file,
+				const char __user *inbuf,
+				int in_len, int out_len)
+{
+	struct ib_ucm_create_id cmd;
+	struct ib_ucm_create_id_resp resp;
+	struct ib_ucm_context *ctx;
+	int result;
+
+	if (out_len < sizeof(resp))
+		return -ENOSPC;
+
+	if (copy_from_user(&cmd, inbuf, sizeof(cmd)))
+		return -EFAULT;
+
+	ctx = ib_ucm_ctx_alloc(file);
+	if (!ctx)
+		return -ENOMEM;
+
+	ctx->cm_id = ib_create_cm_id(ib_ucm_event_handler,
+				     (void *)(unsigned long)ctx->id);
+	if (!ctx->cm_id) {
+		result = -ENOMEM;
+		goto err_cm;
+	}
+
+	resp.id = ctx->id;
+	if (copy_to_user((void __user *)(unsigned long)cmd.response,
+			 &resp, sizeof(resp))) {
+		result = -EFAULT;
+		goto err_ret;
+	}
+
+	return 0;
+err_ret:
+	ib_destroy_cm_id(ctx->cm_id);
+err_cm:
+	ib_ucm_ctx_put(ctx); /* user reference */
+
+	return result;
+}
+
+static ssize_t ib_ucm_destroy_id(struct ib_ucm_file *file,
+				 const char __user *inbuf,
+				 int in_len, int out_len)
+{
+	struct ib_ucm_destroy_id cmd;
+	struct ib_ucm_context *ctx;
+
+	if (copy_from_user(&cmd, inbuf, sizeof(cmd)))
+		return -EFAULT;
+
+	ctx = ib_ucm_ctx_get(cmd.id);
+	if (!ctx)
+		return -ENOENT;
+
+	ib_ucm_ctx_put(ctx); /* user reference */
+	ib_ucm_ctx_put(ctx); /* func reference */
+
+	return 0;
+}
+
+static ssize_t ib_ucm_attr_id(struct ib_ucm_file *file,
+			      const char __user *inbuf,
+			      int in_len, int out_len)
+{
+	struct ib_ucm_attr_id_resp resp;
+	struct ib_ucm_attr_id cmd;
+	struct ib_ucm_context *ctx;
+	int result = 0;
+
+	if (out_len < sizeof(resp))
+		return -ENOSPC;
+
+	if (copy_from_user(&cmd, inbuf, sizeof(cmd)))
+		return -EFAULT;
+
+	ctx = ib_ucm_ctx_get(cmd.id);
+	if (!ctx)
+		return -ENOENT;
+
+ 	down(&ctx->file->mutex);
+	if (ctx->file != file) {
+		result = -EINVAL;
+		goto done;
+	}
+
+	resp.service_id   = ctx->cm_id->service_id;
+	resp.service_mask = ctx->cm_id->service_mask;
+	resp.local_id     = ctx->cm_id->local_id;
+	resp.remote_id    = ctx->cm_id->remote_id;
+
+	if (copy_to_user((void __user *)(unsigned long)cmd.response,
+			 &resp, sizeof(resp)))
+		result = -EFAULT;
+
+done:
+	up(&ctx->file->mutex);
+	ib_ucm_ctx_put(ctx); /* func reference */
+	return result;
+}
+
+static ssize_t ib_ucm_listen(struct ib_ucm_file *file,
+			     const char __user *inbuf,
+			     int in_len, int out_len)
+{
+	struct ib_ucm_listen cmd;
+	struct ib_ucm_context *ctx;
+	int result;
+
+	if (copy_from_user(&cmd, inbuf, sizeof(cmd)))
+		return -EFAULT;
+
+	ctx = ib_ucm_ctx_get(cmd.id);
+	if (!ctx)
+		return -ENOENT;
+
+ 	down(&ctx->file->mutex);
+	if (ctx->file != file)
+		result = -EINVAL;
+	else
+		result = ib_cm_listen(ctx->cm_id, cmd.service_id,
+				      cmd.service_mask);
+
+	up(&ctx->file->mutex);
+	ib_ucm_ctx_put(ctx); /* func reference */
+	return result;
+}
+
+static ssize_t ib_ucm_establish(struct ib_ucm_file *file,
+				const char __user *inbuf,
+				int in_len, int out_len)
+{
+	struct ib_ucm_establish cmd;
+	struct ib_ucm_context *ctx;
+	int result;
+
+	if (copy_from_user(&cmd, inbuf, sizeof(cmd)))
+		return -EFAULT;
+
+	ctx = ib_ucm_ctx_get(cmd.id);
+	if (!ctx)
+		return -ENOENT;
+
+ 	down(&ctx->file->mutex);
+	if (ctx->file != file)
+		result = -EINVAL;
+	else
+		result = ib_cm_establish(ctx->cm_id);
+
+	up(&ctx->file->mutex);
+	ib_ucm_ctx_put(ctx); /* func reference */
+	return result;
+}
+
+static int ib_ucm_alloc_data(const void **dest, u64 src, u32 len)
+{
+	void *data;
+
+	*dest = NULL;
+
+	if (!len)
+		return 0;
+
+	data = kmalloc(len, GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	if (copy_from_user(data, (void __user *)(unsigned long)src, len)) {
+		kfree(data);
+		return -EFAULT;
+	}
+
+	*dest = data;
+	return 0;
+}
+
+static int ib_ucm_path_get(struct ib_sa_path_rec **path, u64 src)
+{
+	struct ib_ucm_path_rec ucm_path;
+	struct ib_sa_path_rec  *sa_path;
+
+	*path = NULL;
+
+	if (!src)
+		return 0;
+
+	sa_path = kmalloc(sizeof(*sa_path), GFP_KERNEL);
+	if (!sa_path)
+		return -ENOMEM;
+
+	if (copy_from_user(&ucm_path, (void __user *)(unsigned long)src,
+			   sizeof(ucm_path))) {
+
+		kfree(sa_path);
+		return -EFAULT;
+	}
+
+	memcpy(sa_path->dgid.raw, ucm_path.dgid, sizeof(union ib_gid));
+	memcpy(sa_path->sgid.raw, ucm_path.sgid, sizeof(union ib_gid));
+
+	sa_path->dlid	          = ucm_path.dlid;
+	sa_path->slid	          = ucm_path.slid;
+	sa_path->raw_traffic      = ucm_path.raw_traffic;
+	sa_path->flow_label       = ucm_path.flow_label;
+	sa_path->hop_limit        = ucm_path.hop_limit;
+	sa_path->traffic_class    = ucm_path.traffic_class;
+	sa_path->reversible       = ucm_path.reversible;
+	sa_path->numb_path        = ucm_path.numb_path;
+	sa_path->pkey             = ucm_path.pkey;
+	sa_path->sl               = ucm_path.sl;
+	sa_path->mtu_selector     = ucm_path.mtu_selector;
+	sa_path->mtu              = ucm_path.mtu;
+	sa_path->rate_selector    = ucm_path.rate_selector;
+	sa_path->rate             = ucm_path.rate;
+	sa_path->packet_life_time = ucm_path.packet_life_time;
+	sa_path->preference       = ucm_path.preference;
+
+	sa_path->packet_life_time_selector =
+		ucm_path.packet_life_time_selector;
+
+	*path = sa_path;
+	return 0;
+}
+
+static ssize_t ib_ucm_send_req(struct ib_ucm_file *file,
+			       const char __user *inbuf,
+			       int in_len, int out_len)
+{
+	struct ib_cm_req_param param;
+	struct ib_ucm_context *ctx;
+	struct ib_ucm_req cmd;
+	int result;
+
+	param.private_data   = NULL;
+	param.primary_path   = NULL;
+	param.alternate_path = NULL;
+
+	if (copy_from_user(&cmd, inbuf, sizeof(cmd)))
+		return -EFAULT;
+
+	result = ib_ucm_alloc_data(&param.private_data, cmd.data, cmd.len);
+	if (result)
+		goto done;
+
+	result = ib_ucm_path_get(&param.primary_path, cmd.primary_path);
+	if (result)
+		goto done;
+
+	result = ib_ucm_path_get(&param.alternate_path, cmd.alternate_path);
+	if (result)
+		goto done;
+
+	param.private_data_len           = cmd.len;
+	param.service_id                 = cmd.sid;
+	param.qp_num                     = cmd.qpn;
+	param.qp_type                    = cmd.qp_type;
+	param.starting_psn               = cmd.psn;
+	param.peer_to_peer               = cmd.peer_to_peer;
+	param.responder_resources        = cmd.responder_resources;
+	param.initiator_depth            = cmd.initiator_depth;
+	param.remote_cm_response_timeout = cmd.remote_cm_response_timeout;
+	param.flow_control               = cmd.flow_control;
+	param.local_cm_response_timeout  = cmd.local_cm_response_timeout;
+	param.retry_count                = cmd.retry_count;
+	param.rnr_retry_count            = cmd.rnr_retry_count;
+	param.max_cm_retries             = cmd.max_cm_retries;
+	param.srq                        = cmd.srq;
+
+	ctx = ib_ucm_ctx_get(cmd.id);
+	if (!ctx) {
+		result = -ENOENT;
+		goto done;
+	}
+
+ 	down(&ctx->file->mutex);
+	if (ctx->file != file)
+		result = -EINVAL;
+	else
+		result = ib_send_cm_req(ctx->cm_id, &param);
+
+	up(&ctx->file->mutex);
+	ib_ucm_ctx_put(ctx); /* func reference */
+done:
+	kfree(param.private_data);
+	kfree(param.primary_path);
+	kfree(param.alternate_path);
+
+	return result;
+}
+
+static ssize_t ib_ucm_send_rep(struct ib_ucm_file *file,
+			       const char __user *inbuf,
+			       int in_len, int out_len)
+{
+	struct ib_cm_rep_param param;
+	struct ib_ucm_context *ctx;
+	struct ib_ucm_rep cmd;
+	int result;
+
+	param.private_data = NULL;
+
+	if (copy_from_user(&cmd, inbuf, sizeof(cmd)))
+		return -EFAULT;
+
+	result = ib_ucm_alloc_data(&param.private_data, cmd.data, cmd.len);
+	if (result)
+		return result;
+
+	param.qp_num              = cmd.qpn;
+	param.starting_psn        = cmd.psn;
+	param.private_data_len    = cmd.len;
+	param.responder_resources = cmd.responder_resources;
+	param.initiator_depth     = cmd.initiator_depth;
+	param.target_ack_delay    = cmd.target_ack_delay;
+	param.failover_accepted   = cmd.failover_accepted;
+	param.flow_control        = cmd.flow_control;
+	param.rnr_retry_count     = cmd.rnr_retry_count;
+	param.srq                 = cmd.srq;
+
+	ctx = ib_ucm_ctx_get(cmd.id);
+	if (!ctx) {
+		result = -ENOENT;
+		goto done;
+	}
+
+ 	down(&ctx->file->mutex);
+	if (ctx->file != file)
+		result = -EINVAL;
+	else
+		result = ib_send_cm_rep(ctx->cm_id, &param);
+
+	up(&ctx->file->mutex);
+	ib_ucm_ctx_put(ctx); /* func reference */
+done:
+	kfree(param.private_data);
+
+	return result;
+}
+
+static ssize_t ib_ucm_send_private_data(struct ib_ucm_file *file,
+					const char __user *inbuf, int in_len,
+					int (*func)(struct ib_cm_id *cm_id,
+						    const void *private_data,
+						    u8 private_data_len))
+{
+	struct ib_ucm_private_data cmd;
+	struct ib_ucm_context *ctx;
+	const void *private_data = NULL;
+	int result;
+
+	if (copy_from_user(&cmd, inbuf, sizeof(cmd)))
+		return -EFAULT;
+
+	result = ib_ucm_alloc_data(&private_data, cmd.data, cmd.len);
+	if (result)
+		return result;
+
+	ctx = ib_ucm_ctx_get(cmd.id);
+	if (!ctx) {
+		result = -ENOENT;
+		goto done;
+	}
+
+ 	down(&ctx->file->mutex);
+	if (ctx->file != file)
+		result = -EINVAL;
+	else
+		result = func(ctx->cm_id, private_data, cmd.len);
+
+	up(&ctx->file->mutex);
+	ib_ucm_ctx_put(ctx); /* func reference */
+done:
+	kfree(private_data);
+
+	return result;
+}
+
+static ssize_t ib_ucm_send_rtu(struct ib_ucm_file *file,
+			       const char __user *inbuf,
+			       int in_len, int out_len)
+{
+	return ib_ucm_send_private_data(file, inbuf, in_len, ib_send_cm_rtu);
+}
+
+static ssize_t ib_ucm_send_dreq(struct ib_ucm_file *file,
+				const char __user *inbuf,
+				int in_len, int out_len)
+{
+	return ib_ucm_send_private_data(file, inbuf, in_len, ib_send_cm_dreq);
+}
+
+static ssize_t ib_ucm_send_drep(struct ib_ucm_file *file,
+				const char __user *inbuf,
+				int in_len, int out_len)
+{
+	return ib_ucm_send_private_data(file, inbuf, in_len, ib_send_cm_drep);
+}
+
+static ssize_t ib_ucm_send_info(struct ib_ucm_file *file,
+				const char __user *inbuf, int in_len,
+				int (*func)(struct ib_cm_id *cm_id,
+					    int status,
+					    const void *info,
+					    u8 info_len,
+					    const void *data,
+					    u8 data_len))
+{
+	struct ib_ucm_context *ctx;
+	struct ib_ucm_info cmd;
+	const void *data = NULL;
+	const void *info = NULL;
+	int result;
+
+	if (copy_from_user(&cmd, inbuf, sizeof(cmd)))
+		return -EFAULT;
+
+	result = ib_ucm_alloc_data(&data, cmd.data, cmd.data_len);
+	if (result)
+		goto done;
+
+	result = ib_ucm_alloc_data(&info, cmd.info, cmd.info_len);
+	if (result)
+		goto done;
+
+	ctx = ib_ucm_ctx_get(cmd.id);
+	if (!ctx) {
+		result = -ENOENT;
+		goto done;
+	}
+
+ 	down(&ctx->file->mutex);
+	if (ctx->file != file)
+		result = -EINVAL;
+	else
+		result = func(ctx->cm_id, cmd.status,
+			      info, cmd.info_len,
+			      data, cmd.data_len);
+
+	up(&ctx->file->mutex);
+	ib_ucm_ctx_put(ctx); /* func reference */
+done:
+	kfree(data);
+	kfree(info);
+
+	return result;
+}
+
+static ssize_t ib_ucm_send_rej(struct ib_ucm_file *file,
+			       const char __user *inbuf,
+			       int in_len, int out_len)
+{
+	return ib_ucm_send_info(file, inbuf, in_len, (void *)ib_send_cm_rej);
+}
+
+static ssize_t ib_ucm_send_apr(struct ib_ucm_file *file,
+			       const char __user *inbuf,
+			       int in_len, int out_len)
+{
+	return ib_ucm_send_info(file, inbuf, in_len, (void *)ib_send_cm_apr);
+}
+
+static ssize_t ib_ucm_send_mra(struct ib_ucm_file *file,
+			       const char __user *inbuf,
+			       int in_len, int out_len)
+{
+	struct ib_ucm_context *ctx;
+	struct ib_ucm_mra cmd;
+	const void *data = NULL;
+	int result;
+
+	if (copy_from_user(&cmd, inbuf, sizeof(cmd)))
+		return -EFAULT;
+
+	result = ib_ucm_alloc_data(&data, cmd.data, cmd.len);
+	if (result)
+		return result;
+
+	ctx = ib_ucm_ctx_get(cmd.id);
+	if (!ctx) {
+		result = -ENOENT;
+		goto done;
+	}
+
+ 	down(&ctx->file->mutex);
+	if (ctx->file != file)
+		result = -EINVAL;
+	else
+		result = ib_send_cm_mra(ctx->cm_id, cmd.timeout,
+					data, cmd.len);
+
+	up(&ctx->file->mutex);
+	ib_ucm_ctx_put(ctx); /* func reference */
+done:
+	kfree(data);
+
+	return result;
+}
+
+static ssize_t ib_ucm_send_lap(struct ib_ucm_file *file,
+			       const char __user *inbuf,
+			       int in_len, int out_len)
+{
+	struct ib_ucm_context *ctx;
+	struct ib_sa_path_rec *path = NULL;
+	struct ib_ucm_lap cmd;
+	const void *data = NULL;
+	int result;
+
+	if (copy_from_user(&cmd, inbuf, sizeof(cmd)))
+		return -EFAULT;
+
+	result = ib_ucm_alloc_data(&data, cmd.data, cmd.len);
+	if (result)
+		goto done;
+
+	result = ib_ucm_path_get(&path, cmd.path);
+	if (result)
+		goto done;
+
+	ctx = ib_ucm_ctx_get(cmd.id);
+	if (!ctx) {
+		result = -ENOENT;
+		goto done;
+	}
+
+ 	down(&ctx->file->mutex);
+	if (ctx->file != file)
+		result = -EINVAL;
+	else
+		result = ib_send_cm_lap(ctx->cm_id, path, data, cmd.len);
+
+	up(&ctx->file->mutex);
+	ib_ucm_ctx_put(ctx); /* func reference */
+done:
+	kfree(data);
+	kfree(path);
+
+	return result;
+}
+
+static ssize_t ib_ucm_send_sidr_req(struct ib_ucm_file *file,
+				    const char __user *inbuf,
+				    int in_len, int out_len)
+{
+	struct ib_cm_sidr_req_param param;
+	struct ib_ucm_context *ctx;
+	struct ib_ucm_sidr_req cmd;
+	int result;
+
+	param.private_data = NULL;
+	param.path = NULL;
+
+	if (copy_from_user(&cmd, inbuf, sizeof(cmd)))
+		return -EFAULT;
+
+	result = ib_ucm_alloc_data(&param.private_data, cmd.data, cmd.len);
+	if (result)
+		goto done;
+
+	result = ib_ucm_path_get(&param.path, cmd.path);
+	if (result)
+		goto done;
+
+	param.private_data_len = cmd.len;
+	param.service_id       = cmd.sid;
+	param.timeout_ms       = cmd.timeout;
+	param.max_cm_retries   = cmd.max_cm_retries;
+	param.pkey             = cmd.pkey;
+
+	ctx = ib_ucm_ctx_get(cmd.id);
+	if (!ctx) {
+		result = -ENOENT;
+		goto done;
+	}
+
+ 	down(&ctx->file->mutex);
+	if (ctx->file != file)
+		result = -EINVAL;
+	else
+		result = ib_send_cm_sidr_req(ctx->cm_id, &param);
+
+	up(&ctx->file->mutex);
+	ib_ucm_ctx_put(ctx); /* func reference */
+done:
+	kfree(param.private_data);
+	kfree(param.path);
+
+	return result;
+}
+
+static ssize_t ib_ucm_send_sidr_rep(struct ib_ucm_file *file,
+				    const char __user *inbuf,
+				    int in_len, int out_len)
+{
+	struct ib_cm_sidr_rep_param param;
+	struct ib_ucm_sidr_rep cmd;
+	struct ib_ucm_context *ctx;
+	int result;
+
+	param.info = NULL;
+
+	if (copy_from_user(&cmd, inbuf, sizeof(cmd)))
+		return -EFAULT;
+
+	result = ib_ucm_alloc_data(&param.private_data,
+				   cmd.data, cmd.data_len);
+	if (result)
+		goto done;
+
+	result = ib_ucm_alloc_data(&param.info, cmd.info, cmd.info_len);
+	if (result)
+		goto done;
+
+	param.qp_num	   = cmd.qpn;
+	param.qkey	     = cmd.qkey;
+	param.status	   = cmd.status;
+	param.info_length      = cmd.info_len;
+	param.private_data_len = cmd.data_len;
+
+	ctx = ib_ucm_ctx_get(cmd.id);
+	if (!ctx) {
+		result = -ENOENT;
+		goto done;
+	}
+
+ 	down(&ctx->file->mutex);
+	if (ctx->file != file)
+		result = -EINVAL;
+	else
+		result = ib_send_cm_sidr_rep(ctx->cm_id, &param);
+
+	up(&ctx->file->mutex);
+	ib_ucm_ctx_put(ctx); /* func reference */
+done:
+	kfree(param.private_data);
+	kfree(param.info);
+
+	return result;
+}
+
+static ssize_t (*ucm_cmd_table[])(struct ib_ucm_file *file,
+				  const char __user *inbuf,
+				  int in_len, int out_len) = {
+	[IB_USER_CM_CMD_CREATE_ID]     = ib_ucm_create_id,
+	[IB_USER_CM_CMD_DESTROY_ID]    = ib_ucm_destroy_id,
+	[IB_USER_CM_CMD_ATTR_ID]       = ib_ucm_attr_id,
+	[IB_USER_CM_CMD_LISTEN]        = ib_ucm_listen,
+	[IB_USER_CM_CMD_ESTABLISH]     = ib_ucm_establish,
+	[IB_USER_CM_CMD_SEND_REQ]      = ib_ucm_send_req,
+	[IB_USER_CM_CMD_SEND_REP]      = ib_ucm_send_rep,
+	[IB_USER_CM_CMD_SEND_RTU]      = ib_ucm_send_rtu,
+	[IB_USER_CM_CMD_SEND_DREQ]     = ib_ucm_send_dreq,
+	[IB_USER_CM_CMD_SEND_DREP]     = ib_ucm_send_drep,
+	[IB_USER_CM_CMD_SEND_REJ]      = ib_ucm_send_rej,
+	[IB_USER_CM_CMD_SEND_MRA]      = ib_ucm_send_mra,
+	[IB_USER_CM_CMD_SEND_LAP]      = ib_ucm_send_lap,
+	[IB_USER_CM_CMD_SEND_APR]      = ib_ucm_send_apr,
+	[IB_USER_CM_CMD_SEND_SIDR_REQ] = ib_ucm_send_sidr_req,
+	[IB_USER_CM_CMD_SEND_SIDR_REP] = ib_ucm_send_sidr_rep,
+	[IB_USER_CM_CMD_EVENT]	       = ib_ucm_event,
+};
+
+static ssize_t ib_ucm_write(struct file *filp, const char __user *buf,
+			    size_t len, loff_t *pos)
+{
+	struct ib_ucm_file *file = filp->private_data;
+	struct ib_ucm_cmd_hdr hdr;
+	ssize_t result;
+
+	if (len < sizeof(hdr))
+		return -EINVAL;
+
+	if (copy_from_user(&hdr, buf, sizeof(hdr)))
+		return -EFAULT;
+
+	ucm_dbg("Write. cmd <%d> in <%d> out <%d> len <%Zu>\n",
+		hdr.cmd, hdr.in, hdr.out, len);
+
+	if (hdr.cmd < 0 || hdr.cmd >= ARRAY_SIZE(ucm_cmd_table))
+		return -EINVAL;
+
+	if (hdr.in + sizeof(hdr) > len)
+		return -EINVAL;
+
+	result = ucm_cmd_table[hdr.cmd](file, buf + sizeof(hdr),
+					hdr.in, hdr.out);
+	if (!result)
+		result = len;
+
+	return result;
+}
+
+static unsigned int ib_ucm_poll(struct file *filp,
+				struct poll_table_struct *wait)
+{
+	struct ib_ucm_file *file = filp->private_data;
+	unsigned int mask = 0;
+
+	poll_wait(filp, &file->poll_wait, wait);
+
+	if (!list_empty(&file->events))
+		mask = POLLIN | POLLRDNORM;
+
+	return mask;
+}
+
+static int ib_ucm_open(struct inode *inode, struct file *filp)
+{
+	struct ib_ucm_file *file;
+
+	file = kmalloc(sizeof(*file), GFP_KERNEL);
+	if (!file)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&file->events);
+	INIT_LIST_HEAD(&file->ctxs);
+	init_waitqueue_head(&file->poll_wait);
+
+	init_MUTEX(&file->mutex);
+
+	filp->private_data = file;
+	file->filp = filp;
+
+	ucm_dbg("Created struct\n");
+
+	return 0;
+}
+
+static int ib_ucm_close(struct inode *inode, struct file *filp)
+{
+	struct ib_ucm_file *file = filp->private_data;
+	struct ib_ucm_context *ctx;
+
+	down(&file->mutex);
+
+	while (!list_empty(&file->ctxs)) {
+
+		ctx = list_entry(file->ctxs.next,
+				 struct ib_ucm_context, file_list);
+
+		up(&ctx->file->mutex);
+		ib_ucm_ctx_put(ctx); /* user reference */
+		down(&file->mutex);
+	}
+
+	up(&file->mutex);
+
+	kfree(file);
+
+	ucm_dbg("Deleted struct\n");
+	return 0;
+}
+
+static struct file_operations ib_ucm_fops = {
+	.owner 	 = THIS_MODULE,
+	.open 	 = ib_ucm_open,
+	.release = ib_ucm_close,
+	.write 	 = ib_ucm_write,
+	.poll    = ib_ucm_poll,
+};
+
+
+static struct class *ib_ucm_class;
+static struct cdev	  ib_ucm_cdev;
+
+static int __init ib_ucm_init(void)
+{
+	int result;
+
+	result = register_chrdev_region(IB_UCM_DEV, 1, "infiniband_cm");
+	if (result) {
+		ucm_dbg("Error <%d> registering dev\n", result);
+		goto err_chr;
+	}
+
+	cdev_init(&ib_ucm_cdev, &ib_ucm_fops);
+
+	result = cdev_add(&ib_ucm_cdev, IB_UCM_DEV, 1);
+	if (result) {
+ 		ucm_dbg("Error <%d> adding cdev\n", result);
+		goto err_cdev;
+	}
+
+	ib_ucm_class = class_create(THIS_MODULE, "infiniband_cm");
+	if (IS_ERR(ib_ucm_class)) {
+		result = PTR_ERR(ib_ucm_class);
+ 		ucm_dbg("Error <%d> creating class\n", result);
+		goto err_class;
+	}
+
+	class_device_create(ib_ucm_class, IB_UCM_DEV, NULL, "ucm");
+
+	idr_init(&ctx_id_table);
+	init_MUTEX(&ctx_id_mutex);
+
+	return 0;
+err_class:
+	cdev_del(&ib_ucm_cdev);
+err_cdev:
+	unregister_chrdev_region(IB_UCM_DEV, 1);
+err_chr:
+	return result;
+}
+
+static void __exit ib_ucm_cleanup(void)
+{
+	class_device_destroy(ib_ucm_class, IB_UCM_DEV);
+	class_destroy(ib_ucm_class);
+	cdev_del(&ib_ucm_cdev);
+	unregister_chrdev_region(IB_UCM_DEV, 1);
+}
+
+module_init(ib_ucm_init);
+module_exit(ib_ucm_cleanup);
diff --git a/drivers/infiniband/core/ucm.h b/drivers/infiniband/core/ucm.h
new file mode 100644
index 00000000000..6d36606151b
--- /dev/null
+++ b/drivers/infiniband/core/ucm.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2005 Topspin Communications.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * $Id: ucm.h 2208 2005-04-22 23:24:31Z libor $
+ */
+
+#ifndef UCM_H
+#define UCM_H
+
+#include <linux/fs.h>
+#include <linux/device.h>
+#include <linux/cdev.h>
+#include <linux/idr.h>
+
+#include <ib_cm.h>
+#include <ib_user_cm.h>
+
+#define IB_UCM_CM_ID_INVALID 0xffffffff
+
+struct ib_ucm_file {
+	struct semaphore mutex;
+	struct file *filp;
+	/*
+	 * list of pending events
+	 */
+	struct list_head  ctxs;   /* list of active connections */
+	struct list_head  events; /* list of pending events */
+	wait_queue_head_t poll_wait;
+};
+
+struct ib_ucm_context {
+	int                 id;
+	int                 ref;
+	int                 error;
+
+	struct ib_ucm_file *file;
+	struct ib_cm_id    *cm_id;
+	struct semaphore    mutex;
+
+	struct list_head    events;    /* list of pending events. */
+	struct list_head    file_list; /* member in file ctx list */
+};
+
+struct ib_ucm_event {
+	struct ib_ucm_context *ctx;
+	struct list_head file_list; /* member in file event list */
+	struct list_head ctx_list;  /* member in ctx event list */
+
+	struct ib_ucm_event_resp resp;
+	void *data;
+	void *info;
+	int data_len;
+	int info_len;
+	/*
+	 * new connection identifiers needs to be saved until
+	 * userspace can get a handle on them.
+	 */
+	struct ib_cm_id *cm_id;
+};
+
+#endif /* UCM_H */
diff --git a/drivers/infiniband/core/user_mad.c b/drivers/infiniband/core/user_mad.c
index 9d912d6877f..2e38792df53 100644
--- a/drivers/infiniband/core/user_mad.c
+++ b/drivers/infiniband/core/user_mad.c
@@ -1,5 +1,7 @@
 /*
  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
+ * Copyright (c) 2005 Voltaire, Inc. All rights reserved.
+ * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
@@ -29,7 +31,7 @@
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
  *
- * $Id: user_mad.c 1389 2004-12-27 22:56:47Z roland $
+ * $Id: user_mad.c 2814 2005-07-06 19:14:09Z halr $
  */
 
 #include <linux/module.h>
@@ -94,10 +96,12 @@ struct ib_umad_file {
 };
 
 struct ib_umad_packet {
-	struct ib_user_mad mad;
 	struct ib_ah      *ah;
+	struct ib_mad_send_buf *msg;
 	struct list_head   list;
+	int		   length;
 	DECLARE_PCI_UNMAP_ADDR(mapping)
+	struct ib_user_mad mad;
 };
 
 static const dev_t base_dev = MKDEV(IB_UMAD_MAJOR, IB_UMAD_MINOR_BASE);
@@ -114,10 +118,10 @@ static int queue_packet(struct ib_umad_file *file,
 	int ret = 1;
 
 	down_read(&file->agent_mutex);
-	for (packet->mad.id = 0;
-	     packet->mad.id < IB_UMAD_MAX_AGENTS;
-	     packet->mad.id++)
-		if (agent == file->agent[packet->mad.id]) {
+	for (packet->mad.hdr.id = 0;
+	     packet->mad.hdr.id < IB_UMAD_MAX_AGENTS;
+	     packet->mad.hdr.id++)
+		if (agent == file->agent[packet->mad.hdr.id]) {
 			spin_lock_irq(&file->recv_lock);
 			list_add_tail(&packet->list, &file->recv_list);
 			spin_unlock_irq(&file->recv_lock);
@@ -135,22 +139,30 @@ static void send_handler(struct ib_mad_agent *agent,
 			 struct ib_mad_send_wc *send_wc)
 {
 	struct ib_umad_file *file = agent->context;
-	struct ib_umad_packet *packet =
+	struct ib_umad_packet *timeout, *packet =
 		(void *) (unsigned long) send_wc->wr_id;
 
-	dma_unmap_single(agent->device->dma_device,
-			 pci_unmap_addr(packet, mapping),
-			 sizeof packet->mad.data,
-			 DMA_TO_DEVICE);
-	ib_destroy_ah(packet->ah);
+	ib_destroy_ah(packet->msg->send_wr.wr.ud.ah);
+	ib_free_send_mad(packet->msg);
 
 	if (send_wc->status == IB_WC_RESP_TIMEOUT_ERR) {
-		packet->mad.status = ETIMEDOUT;
+		timeout = kmalloc(sizeof *timeout + sizeof (struct ib_mad_hdr),
+				  GFP_KERNEL);
+		if (!timeout)
+			goto out;
 
-		if (!queue_packet(file, agent, packet))
-			return;
-	}
+		memset(timeout, 0, sizeof *timeout + sizeof (struct ib_mad_hdr));
 
+		timeout->length = sizeof (struct ib_mad_hdr);
+		timeout->mad.hdr.id = packet->mad.hdr.id;
+		timeout->mad.hdr.status = ETIMEDOUT;
+		memcpy(timeout->mad.data, packet->mad.data,
+		       sizeof (struct ib_mad_hdr));
+
+		if (!queue_packet(file, agent, timeout))
+				return;
+	}
+out:
 	kfree(packet);
 }
 
@@ -159,30 +171,35 @@ static void recv_handler(struct ib_mad_agent *agent,
 {
 	struct ib_umad_file *file = agent->context;
 	struct ib_umad_packet *packet;
+	int length;
 
 	if (mad_recv_wc->wc->status != IB_WC_SUCCESS)
 		goto out;
 
-	packet = kmalloc(sizeof *packet, GFP_KERNEL);
+	length = mad_recv_wc->mad_len;
+	packet = kmalloc(sizeof *packet + length, GFP_KERNEL);
 	if (!packet)
 		goto out;
 
-	memset(packet, 0, sizeof *packet);
+	memset(packet, 0, sizeof *packet + length);
+	packet->length = length;
+
+	ib_coalesce_recv_mad(mad_recv_wc, packet->mad.data);
 
-	memcpy(packet->mad.data, mad_recv_wc->recv_buf.mad, sizeof packet->mad.data);
-	packet->mad.status        = 0;
-	packet->mad.qpn 	  = cpu_to_be32(mad_recv_wc->wc->src_qp);
-	packet->mad.lid 	  = cpu_to_be16(mad_recv_wc->wc->slid);
-	packet->mad.sl  	  = mad_recv_wc->wc->sl;
-	packet->mad.path_bits 	  = mad_recv_wc->wc->dlid_path_bits;
-	packet->mad.grh_present   = !!(mad_recv_wc->wc->wc_flags & IB_WC_GRH);
-	if (packet->mad.grh_present) {
+	packet->mad.hdr.status    = 0;
+	packet->mad.hdr.length    = length + sizeof (struct ib_user_mad);
+	packet->mad.hdr.qpn 	  = cpu_to_be32(mad_recv_wc->wc->src_qp);
+	packet->mad.hdr.lid 	  = cpu_to_be16(mad_recv_wc->wc->slid);
+	packet->mad.hdr.sl  	  = mad_recv_wc->wc->sl;
+	packet->mad.hdr.path_bits = mad_recv_wc->wc->dlid_path_bits;
+	packet->mad.hdr.grh_present = !!(mad_recv_wc->wc->wc_flags & IB_WC_GRH);
+	if (packet->mad.hdr.grh_present) {
 		/* XXX parse GRH */
-		packet->mad.gid_index 	  = 0;
-		packet->mad.hop_limit 	  = 0;
-		packet->mad.traffic_class = 0;
-		memset(packet->mad.gid, 0, 16);
-		packet->mad.flow_label 	  = 0;
+		packet->mad.hdr.gid_index 	= 0;
+		packet->mad.hdr.hop_limit 	= 0;
+		packet->mad.hdr.traffic_class	= 0;
+		memset(packet->mad.hdr.gid, 0, 16);
+		packet->mad.hdr.flow_label	= 0;
 	}
 
 	if (queue_packet(file, agent, packet))
@@ -199,7 +216,7 @@ static ssize_t ib_umad_read(struct file *filp, char __user *buf,
 	struct ib_umad_packet *packet;
 	ssize_t ret;
 
-	if (count < sizeof (struct ib_user_mad))
+	if (count < sizeof (struct ib_user_mad) + sizeof (struct ib_mad))
 		return -EINVAL;
 
 	spin_lock_irq(&file->recv_lock);
@@ -222,12 +239,25 @@ static ssize_t ib_umad_read(struct file *filp, char __user *buf,
 
 	spin_unlock_irq(&file->recv_lock);
 
-	if (copy_to_user(buf, &packet->mad, sizeof packet->mad))
+	if (count < packet->length + sizeof (struct ib_user_mad)) {
+		/* Return length needed (and first RMPP segment) if too small */
+		if (copy_to_user(buf, &packet->mad,
+				 sizeof (struct ib_user_mad) + sizeof (struct ib_mad)))
+			ret = -EFAULT;
+		else
+			ret = -ENOSPC;
+	} else if (copy_to_user(buf, &packet->mad,
+			      packet->length + sizeof (struct ib_user_mad)))
 		ret = -EFAULT;
 	else
-		ret = sizeof packet->mad;
-
-	kfree(packet);
+		ret = packet->length + sizeof (struct ib_user_mad);
+	if (ret < 0) {
+		/* Requeue packet */
+		spin_lock_irq(&file->recv_lock);
+		list_add(&packet->list, &file->recv_list);
+		spin_unlock_irq(&file->recv_lock);
+	} else
+		kfree(packet);
 	return ret;
 }
 
@@ -238,69 +268,57 @@ static ssize_t ib_umad_write(struct file *filp, const char __user *buf,
 	struct ib_umad_packet *packet;
 	struct ib_mad_agent *agent;
 	struct ib_ah_attr ah_attr;
-	struct ib_sge      gather_list;
-	struct ib_send_wr *bad_wr, wr = {
-		.opcode      = IB_WR_SEND,
-		.sg_list     = &gather_list,
-		.num_sge     = 1,
-		.send_flags  = IB_SEND_SIGNALED,
-	};
+	struct ib_send_wr *bad_wr;
+	struct ib_rmpp_mad *rmpp_mad;
 	u8 method;
 	u64 *tid;
-	int ret;
+	int ret, length, hdr_len, data_len, rmpp_hdr_size;
+	int rmpp_active = 0;
 
 	if (count < sizeof (struct ib_user_mad))
 		return -EINVAL;
 
-	packet = kmalloc(sizeof *packet, GFP_KERNEL);
+	length = count - sizeof (struct ib_user_mad);
+	packet = kmalloc(sizeof *packet + sizeof(struct ib_mad_hdr) +
+			 sizeof(struct ib_rmpp_hdr), GFP_KERNEL);
 	if (!packet)
 		return -ENOMEM;
 
-	if (copy_from_user(&packet->mad, buf, sizeof packet->mad)) {
-		kfree(packet);
-		return -EFAULT;
+	if (copy_from_user(&packet->mad, buf,
+			    sizeof (struct ib_user_mad) +
+			    sizeof(struct ib_mad_hdr) +
+			    sizeof(struct ib_rmpp_hdr))) {
+		ret = -EFAULT;
+		goto err;
 	}
 
-	if (packet->mad.id < 0 || packet->mad.id >= IB_UMAD_MAX_AGENTS) {
+	if (packet->mad.hdr.id < 0 ||
+	    packet->mad.hdr.id >= IB_UMAD_MAX_AGENTS) {
 		ret = -EINVAL;
 		goto err;
 	}
 
+	packet->length = length;
+
 	down_read(&file->agent_mutex);
 
-	agent = file->agent[packet->mad.id];
+	agent = file->agent[packet->mad.hdr.id];
 	if (!agent) {
 		ret = -EINVAL;
 		goto err_up;
 	}
 
-	/*
-	 * If userspace is generating a request that will generate a
-	 * response, we need to make sure the high-order part of the
-	 * transaction ID matches the agent being used to send the
-	 * MAD.
-	 */
-	method = ((struct ib_mad_hdr *) packet->mad.data)->method;
-
-	if (!(method & IB_MGMT_METHOD_RESP)       &&
-	    method != IB_MGMT_METHOD_TRAP_REPRESS &&
-	    method != IB_MGMT_METHOD_SEND) {
-		tid = &((struct ib_mad_hdr *) packet->mad.data)->tid;
-		*tid = cpu_to_be64(((u64) agent->hi_tid) << 32 |
-				   (be64_to_cpup(tid) & 0xffffffff));
-	}
-
 	memset(&ah_attr, 0, sizeof ah_attr);
-	ah_attr.dlid          = be16_to_cpu(packet->mad.lid);
-	ah_attr.sl            = packet->mad.sl;
-	ah_attr.src_path_bits = packet->mad.path_bits;
+	ah_attr.dlid          = be16_to_cpu(packet->mad.hdr.lid);
+	ah_attr.sl            = packet->mad.hdr.sl;
+	ah_attr.src_path_bits = packet->mad.hdr.path_bits;
 	ah_attr.port_num      = file->port->port_num;
-	if (packet->mad.grh_present) {
+	if (packet->mad.hdr.grh_present) {
 		ah_attr.ah_flags = IB_AH_GRH;
-		memcpy(ah_attr.grh.dgid.raw, packet->mad.gid, 16);
-		ah_attr.grh.flow_label 	   = packet->mad.flow_label;
-		ah_attr.grh.hop_limit  	   = packet->mad.hop_limit;
-		ah_attr.grh.traffic_class  = packet->mad.traffic_class;
+		memcpy(ah_attr.grh.dgid.raw, packet->mad.hdr.gid, 16);
+		ah_attr.grh.flow_label 	   = packet->mad.hdr.flow_label;
+		ah_attr.grh.hop_limit  	   = packet->mad.hdr.hop_limit;
+		ah_attr.grh.traffic_class  = packet->mad.hdr.traffic_class;
 	}
 
 	packet->ah = ib_create_ah(agent->qp->pd, &ah_attr);
@@ -309,34 +327,104 @@ static ssize_t ib_umad_write(struct file *filp, const char __user *buf,
 		goto err_up;
 	}
 
-	gather_list.addr = dma_map_single(agent->device->dma_device,
-					  packet->mad.data,
-					  sizeof packet->mad.data,
-					  DMA_TO_DEVICE);
-	gather_list.length = sizeof packet->mad.data;
-	gather_list.lkey   = file->mr[packet->mad.id]->lkey;
-	pci_unmap_addr_set(packet, mapping, gather_list.addr);
+	rmpp_mad = (struct ib_rmpp_mad *) packet->mad.data;
+	if (ib_get_rmpp_flags(&rmpp_mad->rmpp_hdr) & IB_MGMT_RMPP_FLAG_ACTIVE) {
+		/* RMPP active */
+		if (!agent->rmpp_version) {
+			ret = -EINVAL;
+			goto err_ah;
+		}
+		/* Validate that management class can support RMPP */
+		if (rmpp_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_ADM) {
+			hdr_len = offsetof(struct ib_sa_mad, data);
+			data_len = length;
+		} else if ((rmpp_mad->mad_hdr.mgmt_class >= IB_MGMT_CLASS_VENDOR_RANGE2_START) &&
+			    (rmpp_mad->mad_hdr.mgmt_class <= IB_MGMT_CLASS_VENDOR_RANGE2_END)) {
+				hdr_len = offsetof(struct ib_vendor_mad, data);
+				data_len = length - hdr_len;
+		} else {
+			ret = -EINVAL;
+			goto err_ah;
+		}
+		rmpp_active = 1;
+	} else {
+		if (length > sizeof(struct ib_mad)) {
+			ret = -EINVAL;
+			goto err_ah;
+		}
+		hdr_len = offsetof(struct ib_mad, data);
+		data_len = length - hdr_len;
+	}
+
+	packet->msg = ib_create_send_mad(agent,
+					 be32_to_cpu(packet->mad.hdr.qpn),
+					 0, packet->ah, rmpp_active,
+					 hdr_len, data_len,
+					 GFP_KERNEL);
+	if (IS_ERR(packet->msg)) {
+		ret = PTR_ERR(packet->msg);
+		goto err_ah;
+	}
 
-	wr.wr.ud.mad_hdr     = (struct ib_mad_hdr *) packet->mad.data;
-	wr.wr.ud.ah          = packet->ah;
-	wr.wr.ud.remote_qpn  = be32_to_cpu(packet->mad.qpn);
-	wr.wr.ud.remote_qkey = be32_to_cpu(packet->mad.qkey);
-	wr.wr.ud.timeout_ms  = packet->mad.timeout_ms;
+	packet->msg->send_wr.wr.ud.timeout_ms  = packet->mad.hdr.timeout_ms;
+	packet->msg->send_wr.wr.ud.retries = packet->mad.hdr.retries;
 
-	wr.wr_id            = (unsigned long) packet;
+	/* Override send WR WRID initialized in ib_create_send_mad */
+	packet->msg->send_wr.wr_id = (unsigned long) packet;
 
-	ret = ib_post_send_mad(agent, &wr, &bad_wr);
-	if (ret) {
-		dma_unmap_single(agent->device->dma_device,
-				 pci_unmap_addr(packet, mapping),
-				 sizeof packet->mad.data,
-				 DMA_TO_DEVICE);
-		goto err_up;
+	if (!rmpp_active) {
+		/* Copy message from user into send buffer */
+		if (copy_from_user(packet->msg->mad,
+				   buf + sizeof(struct ib_user_mad), length)) {
+			ret = -EFAULT;
+			goto err_msg;
+		}
+	} else {
+		rmpp_hdr_size = sizeof(struct ib_mad_hdr) +
+				sizeof(struct ib_rmpp_hdr);
+
+		/* Only copy MAD headers (RMPP header in place) */
+		memcpy(packet->msg->mad, packet->mad.data,
+		       sizeof(struct ib_mad_hdr));
+
+		/* Now, copy rest of message from user into send buffer */
+		if (copy_from_user(((struct ib_rmpp_mad *) packet->msg->mad)->data,
+				   buf + sizeof (struct ib_user_mad) + rmpp_hdr_size,
+				   length - rmpp_hdr_size)) {
+			ret = -EFAULT;
+			goto err_msg;
+		}
+	}
+
+	/*
+	 * If userspace is generating a request that will generate a
+	 * response, we need to make sure the high-order part of the
+	 * transaction ID matches the agent being used to send the
+	 * MAD.
+	 */
+	method = packet->msg->mad->mad_hdr.method;
+
+	if (!(method & IB_MGMT_METHOD_RESP)       &&
+	    method != IB_MGMT_METHOD_TRAP_REPRESS &&
+	    method != IB_MGMT_METHOD_SEND) {
+		tid = &packet->msg->mad->mad_hdr.tid;
+		*tid = cpu_to_be64(((u64) agent->hi_tid) << 32 |
+				   (be64_to_cpup(tid) & 0xffffffff));
 	}
 
+	ret = ib_post_send_mad(agent, &packet->msg->send_wr, &bad_wr);
+	if (ret)
+		goto err_msg;
+
 	up_read(&file->agent_mutex);
 
-	return sizeof packet->mad;
+	return sizeof (struct ib_user_mad_hdr) + packet->length;
+
+err_msg:
+	ib_free_send_mad(packet->msg);
+
+err_ah:
+	ib_destroy_ah(packet->ah);
 
 err_up:
 	up_read(&file->agent_mutex);
@@ -399,7 +487,8 @@ found:
 	agent = ib_register_mad_agent(file->port->ib_dev, file->port->port_num,
 				      ureq.qpn ? IB_QPT_GSI : IB_QPT_SMI,
 				      ureq.mgmt_class ? &req : NULL,
-				      0, send_handler, recv_handler, file);
+				      ureq.rmpp_version,
+				      send_handler, recv_handler, file);
 	if (IS_ERR(agent)) {
 		ret = PTR_ERR(agent);
 		goto out;
@@ -460,8 +549,8 @@ out:
 	return ret;
 }
 
-static long ib_umad_ioctl(struct file *filp,
-			 unsigned int cmd, unsigned long arg)
+static long ib_umad_ioctl(struct file *filp, unsigned int cmd,
+			  unsigned long arg)
 {
 	switch (cmd) {
 	case IB_USER_MAD_REGISTER_AGENT:
@@ -517,14 +606,14 @@ static int ib_umad_close(struct inode *inode, struct file *filp)
 }
 
 static struct file_operations umad_fops = {
-	.owner 	        = THIS_MODULE,
-	.read 	        = ib_umad_read,
-	.write 	        = ib_umad_write,
-	.poll 	        = ib_umad_poll,
+	.owner 	 	= THIS_MODULE,
+	.read 	 	= ib_umad_read,
+	.write 	 	= ib_umad_write,
+	.poll 	 	= ib_umad_poll,
 	.unlocked_ioctl = ib_umad_ioctl,
-	.compat_ioctl   = ib_umad_ioctl,
-	.open 	        = ib_umad_open,
-	.release        = ib_umad_close
+	.compat_ioctl 	= ib_umad_ioctl,
+	.open 	 	= ib_umad_open,
+	.release 	= ib_umad_close
 };
 
 static int ib_umad_sm_open(struct inode *inode, struct file *filp)
diff --git a/drivers/infiniband/core/uverbs.h b/drivers/infiniband/core/uverbs.h
index 57347f1e82c..7696022f9a4 100644
--- a/drivers/infiniband/core/uverbs.h
+++ b/drivers/infiniband/core/uverbs.h
@@ -61,6 +61,7 @@ struct ib_uverbs_event_file {
 	int					fd;
 	int					is_async;
 	wait_queue_head_t			poll_wait;
+	struct fasync_struct		       *async_queue;
 	struct list_head			event_list;
 };
 
diff --git a/drivers/infiniband/core/uverbs_main.c b/drivers/infiniband/core/uverbs_main.c
index fbbe03d8c90..eb99e693dec 100644
--- a/drivers/infiniband/core/uverbs_main.c
+++ b/drivers/infiniband/core/uverbs_main.c
@@ -257,11 +257,19 @@ static void ib_uverbs_event_release(struct ib_uverbs_event_file *file)
 	spin_unlock_irq(&file->lock);
 }
 
+static int ib_uverbs_event_fasync(int fd, struct file *filp, int on)
+{
+	struct ib_uverbs_event_file *file = filp->private_data;
+
+	return fasync_helper(fd, filp, on, &file->async_queue);
+}
+
 static int ib_uverbs_event_close(struct inode *inode, struct file *filp)
 {
 	struct ib_uverbs_event_file *file = filp->private_data;
 
 	ib_uverbs_event_release(file);
+	ib_uverbs_event_fasync(-1, filp, 0);
 	kref_put(&file->uverbs_file->ref, ib_uverbs_release_file);
 
 	return 0;
@@ -276,7 +284,8 @@ static struct file_operations uverbs_event_fops = {
 	 */
 	.read 	 = ib_uverbs_event_read,
 	.poll    = ib_uverbs_event_poll,
-	.release = ib_uverbs_event_close
+	.release = ib_uverbs_event_close,
+	.fasync  = ib_uverbs_event_fasync
 };
 
 void ib_uverbs_comp_handler(struct ib_cq *cq, void *cq_context)
@@ -296,6 +305,7 @@ void ib_uverbs_comp_handler(struct ib_cq *cq, void *cq_context)
 	spin_unlock_irqrestore(&file->comp_file[0].lock, flags);
 
 	wake_up_interruptible(&file->comp_file[0].poll_wait);
+	kill_fasync(&file->comp_file[0].async_queue, SIGIO, POLL_IN);
 }
 
 static void ib_uverbs_async_handler(struct ib_uverbs_file *file,
@@ -316,6 +326,7 @@ static void ib_uverbs_async_handler(struct ib_uverbs_file *file,
 	spin_unlock_irqrestore(&file->async_file.lock, flags);
 
 	wake_up_interruptible(&file->async_file.poll_wait);
+	kill_fasync(&file->async_file.async_queue, SIGIO, POLL_IN);
 }
 
 void ib_uverbs_cq_event_handler(struct ib_event *event, void *context_ptr)
@@ -350,6 +361,7 @@ static int ib_uverbs_event_init(struct ib_uverbs_event_file *file,
 	INIT_LIST_HEAD(&file->event_list);
 	init_waitqueue_head(&file->poll_wait);
 	file->uverbs_file = uverbs_file;
+	file->async_queue = NULL;
 
 	file->fd = get_unused_fd();
 	if (file->fd < 0)
diff --git a/drivers/infiniband/core/verbs.c b/drivers/infiniband/core/verbs.c
index 2516f964651..506fdf1f2a2 100644
--- a/drivers/infiniband/core/verbs.c
+++ b/drivers/infiniband/core/verbs.c
@@ -41,6 +41,7 @@
 #include <linux/err.h>
 
 #include <ib_verbs.h>
+#include <ib_cache.h>
 
 /* Protection domains */
 
@@ -88,6 +89,40 @@ struct ib_ah *ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr)
 }
 EXPORT_SYMBOL(ib_create_ah);
 
+struct ib_ah *ib_create_ah_from_wc(struct ib_pd *pd, struct ib_wc *wc,
+				   struct ib_grh *grh, u8 port_num)
+{
+	struct ib_ah_attr ah_attr;
+	u32 flow_class;
+	u16 gid_index;
+	int ret;
+
+	memset(&ah_attr, 0, sizeof ah_attr);
+	ah_attr.dlid = wc->slid;
+	ah_attr.sl = wc->sl;
+	ah_attr.src_path_bits = wc->dlid_path_bits;
+	ah_attr.port_num = port_num;
+
+	if (wc->wc_flags & IB_WC_GRH) {
+		ah_attr.ah_flags = IB_AH_GRH;
+		ah_attr.grh.dgid = grh->dgid;
+
+		ret = ib_find_cached_gid(pd->device, &grh->sgid, &port_num,
+					 &gid_index);
+		if (ret)
+			return ERR_PTR(ret);
+
+		ah_attr.grh.sgid_index = (u8) gid_index;
+		flow_class = be32_to_cpu(grh->version_tclass_flow);
+		ah_attr.grh.flow_label = flow_class & 0xFFFFF;
+		ah_attr.grh.traffic_class = (flow_class >> 20) & 0xFF;
+		ah_attr.grh.hop_limit = grh->hop_limit;
+	}
+
+	return ib_create_ah(pd, &ah_attr);
+}
+EXPORT_SYMBOL(ib_create_ah_from_wc);
+
 int ib_modify_ah(struct ib_ah *ah, struct ib_ah_attr *ah_attr)
 {
 	return ah->device->modify_ah ?
diff --git a/drivers/infiniband/hw/mthca/mthca_cq.c b/drivers/infiniband/hw/mthca/mthca_cq.c
index b5aea7b869f..5687c301452 100644
--- a/drivers/infiniband/hw/mthca/mthca_cq.c
+++ b/drivers/infiniband/hw/mthca/mthca_cq.c
@@ -373,8 +373,12 @@ static int handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq,
 	 * If we're at the end of the WQE chain, or we've used up our
 	 * doorbell count, free the CQE.  Otherwise just update it for
 	 * the next poll operation.
+	 *
+	 * This does not apply to mem-free HCAs: they don't use the
+	 * doorbell count field, and so we should always free the CQE.
 	 */
-	if (!(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd))
+	if (mthca_is_memfree(dev) ||
+	    !(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd))
 		return 0;
 
 	cqe->db_cnt   = cpu_to_be16(be16_to_cpu(cqe->db_cnt) - dbd);
diff --git a/drivers/infiniband/hw/mthca/mthca_provider.c b/drivers/infiniband/hw/mthca/mthca_provider.c
index 7a58ce90e17..81919a7b493 100644
--- a/drivers/infiniband/hw/mthca/mthca_provider.c
+++ b/drivers/infiniband/hw/mthca/mthca_provider.c
@@ -349,9 +349,9 @@ static int mthca_mmap_uar(struct ib_ucontext *context,
 
 	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 
-	if (remap_pfn_range(vma, vma->vm_start,
-			    to_mucontext(context)->uar.pfn,
-			    PAGE_SIZE, vma->vm_page_prot))
+	if (io_remap_pfn_range(vma, vma->vm_start,
+			       to_mucontext(context)->uar.pfn,
+			       PAGE_SIZE, vma->vm_page_prot))
 		return -EAGAIN;
 
 	return 0;
diff --git a/drivers/infiniband/include/ib_cm.h b/drivers/infiniband/include/ib_cm.h
new file mode 100644
index 00000000000..da650115e79
--- /dev/null
+++ b/drivers/infiniband/include/ib_cm.h
@@ -0,0 +1,569 @@
+/*
+ * Copyright (c) 2004 Intel Corporation.  All rights reserved.
+ * Copyright (c) 2004 Topspin Corporation.  All rights reserved.
+ * Copyright (c) 2004 Voltaire Corporation.  All rights reserved.
+ * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * $Id: ib_cm.h 2730 2005-06-28 16:43:03Z sean.hefty $
+ */
+#if !defined(IB_CM_H)
+#define IB_CM_H
+
+#include <ib_mad.h>
+#include <ib_sa.h>
+
+enum ib_cm_state {
+	IB_CM_IDLE,
+	IB_CM_LISTEN,
+	IB_CM_REQ_SENT,
+	IB_CM_REQ_RCVD,
+	IB_CM_MRA_REQ_SENT,
+	IB_CM_MRA_REQ_RCVD,
+	IB_CM_REP_SENT,
+	IB_CM_REP_RCVD,
+	IB_CM_MRA_REP_SENT,
+	IB_CM_MRA_REP_RCVD,
+	IB_CM_ESTABLISHED,
+	IB_CM_DREQ_SENT,
+	IB_CM_DREQ_RCVD,
+	IB_CM_TIMEWAIT,
+	IB_CM_SIDR_REQ_SENT,
+	IB_CM_SIDR_REQ_RCVD
+};
+
+enum ib_cm_lap_state {
+	IB_CM_LAP_IDLE,
+	IB_CM_LAP_SENT,
+	IB_CM_LAP_RCVD,
+	IB_CM_MRA_LAP_SENT,
+	IB_CM_MRA_LAP_RCVD,
+};
+
+enum ib_cm_event_type {
+	IB_CM_REQ_ERROR,
+	IB_CM_REQ_RECEIVED,
+	IB_CM_REP_ERROR,
+	IB_CM_REP_RECEIVED,
+	IB_CM_RTU_RECEIVED,
+	IB_CM_USER_ESTABLISHED,
+	IB_CM_DREQ_ERROR,
+	IB_CM_DREQ_RECEIVED,
+	IB_CM_DREP_RECEIVED,
+	IB_CM_TIMEWAIT_EXIT,
+	IB_CM_MRA_RECEIVED,
+	IB_CM_REJ_RECEIVED,
+	IB_CM_LAP_ERROR,
+	IB_CM_LAP_RECEIVED,
+	IB_CM_APR_RECEIVED,
+	IB_CM_SIDR_REQ_ERROR,
+	IB_CM_SIDR_REQ_RECEIVED,
+	IB_CM_SIDR_REP_RECEIVED
+};
+
+enum ib_cm_data_size {
+	IB_CM_REQ_PRIVATE_DATA_SIZE	 = 92,
+	IB_CM_MRA_PRIVATE_DATA_SIZE	 = 222,
+	IB_CM_REJ_PRIVATE_DATA_SIZE	 = 148,
+	IB_CM_REP_PRIVATE_DATA_SIZE	 = 196,
+	IB_CM_RTU_PRIVATE_DATA_SIZE	 = 224,
+	IB_CM_DREQ_PRIVATE_DATA_SIZE	 = 220,
+	IB_CM_DREP_PRIVATE_DATA_SIZE	 = 224,
+	IB_CM_REJ_ARI_LENGTH		 = 72,
+	IB_CM_LAP_PRIVATE_DATA_SIZE	 = 168,
+	IB_CM_APR_PRIVATE_DATA_SIZE	 = 148,
+	IB_CM_APR_INFO_LENGTH		 = 72,
+	IB_CM_SIDR_REQ_PRIVATE_DATA_SIZE = 216,
+	IB_CM_SIDR_REP_PRIVATE_DATA_SIZE = 136,
+	IB_CM_SIDR_REP_INFO_LENGTH	 = 72
+};
+
+struct ib_cm_id;
+
+struct ib_cm_req_event_param {
+	struct ib_cm_id		*listen_id;
+	struct ib_device	*device;
+	u8			port;
+
+	struct ib_sa_path_rec	*primary_path;
+	struct ib_sa_path_rec	*alternate_path;
+
+	u64			remote_ca_guid;
+	u32			remote_qkey;
+	u32			remote_qpn;
+	enum ib_qp_type		qp_type;
+
+	u32			starting_psn;
+	u8			responder_resources;
+	u8			initiator_depth;
+	unsigned int		local_cm_response_timeout:5;
+	unsigned int		flow_control:1;
+	unsigned int		remote_cm_response_timeout:5;
+	unsigned int		retry_count:3;
+	unsigned int		rnr_retry_count:3;
+	unsigned int		srq:1;
+};
+
+struct ib_cm_rep_event_param {
+	u64			remote_ca_guid;
+	u32			remote_qkey;
+	u32			remote_qpn;
+	u32			starting_psn;
+	u8			responder_resources;
+	u8			initiator_depth;
+	unsigned int		target_ack_delay:5;
+	unsigned int		failover_accepted:2;
+	unsigned int		flow_control:1;
+	unsigned int		rnr_retry_count:3;
+	unsigned int		srq:1;
+};
+
+enum ib_cm_rej_reason {
+	IB_CM_REJ_NO_QP				= __constant_htons(1),
+	IB_CM_REJ_NO_EEC			= __constant_htons(2),
+	IB_CM_REJ_NO_RESOURCES			= __constant_htons(3),
+	IB_CM_REJ_TIMEOUT			= __constant_htons(4),
+	IB_CM_REJ_UNSUPPORTED			= __constant_htons(5),
+	IB_CM_REJ_INVALID_COMM_ID		= __constant_htons(6),
+	IB_CM_REJ_INVALID_COMM_INSTANCE		= __constant_htons(7),
+	IB_CM_REJ_INVALID_SERVICE_ID		= __constant_htons(8),
+	IB_CM_REJ_INVALID_TRANSPORT_TYPE	= __constant_htons(9),
+	IB_CM_REJ_STALE_CONN			= __constant_htons(10),
+	IB_CM_REJ_RDC_NOT_EXIST			= __constant_htons(11),
+	IB_CM_REJ_INVALID_GID			= __constant_htons(12),
+	IB_CM_REJ_INVALID_LID			= __constant_htons(13),
+	IB_CM_REJ_INVALID_SL			= __constant_htons(14),
+	IB_CM_REJ_INVALID_TRAFFIC_CLASS		= __constant_htons(15),
+	IB_CM_REJ_INVALID_HOP_LIMIT		= __constant_htons(16),
+	IB_CM_REJ_INVALID_PACKET_RATE		= __constant_htons(17),
+	IB_CM_REJ_INVALID_ALT_GID		= __constant_htons(18),
+	IB_CM_REJ_INVALID_ALT_LID		= __constant_htons(19),
+	IB_CM_REJ_INVALID_ALT_SL		= __constant_htons(20),
+	IB_CM_REJ_INVALID_ALT_TRAFFIC_CLASS	= __constant_htons(21),
+	IB_CM_REJ_INVALID_ALT_HOP_LIMIT		= __constant_htons(22),
+	IB_CM_REJ_INVALID_ALT_PACKET_RATE	= __constant_htons(23),
+	IB_CM_REJ_PORT_CM_REDIRECT		= __constant_htons(24),
+	IB_CM_REJ_PORT_REDIRECT			= __constant_htons(25),
+	IB_CM_REJ_INVALID_MTU			= __constant_htons(26),
+	IB_CM_REJ_INSUFFICIENT_RESP_RESOURCES	= __constant_htons(27),
+	IB_CM_REJ_CONSUMER_DEFINED		= __constant_htons(28),
+	IB_CM_REJ_INVALID_RNR_RETRY		= __constant_htons(29),
+	IB_CM_REJ_DUPLICATE_LOCAL_COMM_ID	= __constant_htons(30),
+	IB_CM_REJ_INVALID_CLASS_VERSION		= __constant_htons(31),
+	IB_CM_REJ_INVALID_FLOW_LABEL		= __constant_htons(32),
+	IB_CM_REJ_INVALID_ALT_FLOW_LABEL	= __constant_htons(33)
+};
+
+struct ib_cm_rej_event_param {
+	enum ib_cm_rej_reason	reason;
+	void			*ari;
+	u8			ari_length;
+};
+
+struct ib_cm_mra_event_param {
+	u8	service_timeout;
+};
+
+struct ib_cm_lap_event_param {
+	struct ib_sa_path_rec	*alternate_path;
+};
+
+enum ib_cm_apr_status {
+	IB_CM_APR_SUCCESS,
+	IB_CM_APR_INVALID_COMM_ID,
+	IB_CM_APR_UNSUPPORTED,
+	IB_CM_APR_REJECT,
+	IB_CM_APR_REDIRECT,
+	IB_CM_APR_IS_CURRENT,
+	IB_CM_APR_INVALID_QPN_EECN,
+	IB_CM_APR_INVALID_LID,
+	IB_CM_APR_INVALID_GID,
+	IB_CM_APR_INVALID_FLOW_LABEL,
+	IB_CM_APR_INVALID_TCLASS,
+	IB_CM_APR_INVALID_HOP_LIMIT,
+	IB_CM_APR_INVALID_PACKET_RATE,
+	IB_CM_APR_INVALID_SL
+};
+
+struct ib_cm_apr_event_param {
+	enum ib_cm_apr_status	ap_status;
+	void			*apr_info;
+	u8			info_len;
+};
+
+struct ib_cm_sidr_req_event_param {
+	struct ib_cm_id		*listen_id;
+	struct ib_device	*device;
+	u8			port;
+
+	u16	pkey;
+};
+
+enum ib_cm_sidr_status {
+	IB_SIDR_SUCCESS,
+	IB_SIDR_UNSUPPORTED,
+	IB_SIDR_REJECT,
+	IB_SIDR_NO_QP,
+	IB_SIDR_REDIRECT,
+	IB_SIDR_UNSUPPORTED_VERSION
+};
+
+struct ib_cm_sidr_rep_event_param {
+	enum ib_cm_sidr_status	status;
+	u32			qkey;
+	u32			qpn;
+	void			*info;
+	u8			info_len;
+
+};
+
+struct ib_cm_event {
+	enum ib_cm_event_type	event;
+	union {
+		struct ib_cm_req_event_param	req_rcvd;
+		struct ib_cm_rep_event_param	rep_rcvd;
+		/* No data for RTU received events. */
+		struct ib_cm_rej_event_param	rej_rcvd;
+		struct ib_cm_mra_event_param	mra_rcvd;
+		struct ib_cm_lap_event_param	lap_rcvd;
+		struct ib_cm_apr_event_param	apr_rcvd;
+		/* No data for DREQ/DREP received events. */
+		struct ib_cm_sidr_req_event_param sidr_req_rcvd;
+		struct ib_cm_sidr_rep_event_param sidr_rep_rcvd;
+		enum ib_wc_status		send_status;
+	} param;
+
+	void			*private_data;
+};
+
+/**
+ * ib_cm_handler - User-defined callback to process communication events.
+ * @cm_id: Communication identifier associated with the reported event.
+ * @event: Information about the communication event.
+ *
+ * IB_CM_REQ_RECEIVED and IB_CM_SIDR_REQ_RECEIVED communication events
+ * generated as a result of listen requests result in the allocation of a
+ * new @cm_id.  The new @cm_id is returned to the user through this callback.
+ * Clients are responsible for destroying the new @cm_id.  For peer-to-peer
+ * IB_CM_REQ_RECEIVED and all other events, the returned @cm_id corresponds
+ * to a user's existing communication identifier.
+ *
+ * Users may not call ib_destroy_cm_id while in the context of this callback;
+ * however, returning a non-zero value instructs the communication manager to
+ * destroy the @cm_id after the callback completes.
+ */
+typedef int (*ib_cm_handler)(struct ib_cm_id *cm_id,
+			     struct ib_cm_event *event);
+
+struct ib_cm_id {
+	ib_cm_handler		cm_handler;
+	void			*context;
+	u64			service_id;
+	u64			service_mask;
+	enum ib_cm_state	state;		/* internal CM/debug use */
+	enum ib_cm_lap_state	lap_state;	/* internal CM/debug use */
+	u32			local_id;
+	u32			remote_id;
+};
+
+/**
+ * ib_create_cm_id - Allocate a communication identifier.
+ * @cm_handler: Callback invoked to notify the user of CM events.
+ * @context: User specified context associated with the communication
+ *   identifier.
+ *
+ * Communication identifiers are used to track connection states, service
+ * ID resolution requests, and listen requests.
+ */
+struct ib_cm_id *ib_create_cm_id(ib_cm_handler cm_handler,
+				 void *context);
+
+/**
+ * ib_destroy_cm_id - Destroy a connection identifier.
+ * @cm_id: Connection identifier to destroy.
+ *
+ * This call blocks until the connection identifier is destroyed.
+ */
+void ib_destroy_cm_id(struct ib_cm_id *cm_id);
+
+#define IB_SERVICE_ID_AGN_MASK	__constant_cpu_to_be64(0xFF00000000000000ULL)
+#define IB_CM_ASSIGN_SERVICE_ID __constant_cpu_to_be64(0x0200000000000000ULL)
+
+/**
+ * ib_cm_listen - Initiates listening on the specified service ID for
+ *   connection and service ID resolution requests.
+ * @cm_id: Connection identifier associated with the listen request.
+ * @service_id: Service identifier matched against incoming connection
+ *   and service ID resolution requests.  The service ID should be specified
+ *   network-byte order.  If set to IB_CM_ASSIGN_SERVICE_ID, the CM will
+ *   assign a service ID to the caller.
+ * @service_mask: Mask applied to service ID used to listen across a
+ *   range of service IDs.  If set to 0, the service ID is matched
+ *   exactly.  This parameter is ignored if %service_id is set to
+ *   IB_CM_ASSIGN_SERVICE_ID.
+ */
+int ib_cm_listen(struct ib_cm_id *cm_id,
+		 u64 service_id,
+		 u64 service_mask);
+
+struct ib_cm_req_param {
+	struct ib_sa_path_rec	*primary_path;
+	struct ib_sa_path_rec	*alternate_path;
+	u64			service_id;
+	u32			qp_num;
+	enum ib_qp_type		qp_type;
+	u32			starting_psn;
+	const void		*private_data;
+	u8			private_data_len;
+	u8			peer_to_peer;
+	u8			responder_resources;
+	u8			initiator_depth;
+	u8			remote_cm_response_timeout;
+	u8			flow_control;
+	u8			local_cm_response_timeout;
+	u8			retry_count;
+	u8			rnr_retry_count;
+	u8			max_cm_retries;
+	u8			srq;
+};
+
+/**
+ * ib_send_cm_req - Sends a connection request to the remote node.
+ * @cm_id: Connection identifier that will be associated with the
+ *   connection request.
+ * @param: Connection request information needed to establish the
+ *   connection.
+ */
+int ib_send_cm_req(struct ib_cm_id *cm_id,
+		   struct ib_cm_req_param *param);
+
+struct ib_cm_rep_param {
+	u32		qp_num;
+	u32		starting_psn;
+	const void	*private_data;
+	u8		private_data_len;
+	u8		responder_resources;
+	u8		initiator_depth;
+	u8		target_ack_delay;
+	u8		failover_accepted;
+	u8		flow_control;
+	u8		rnr_retry_count;
+	u8		srq;
+};
+
+/**
+ * ib_send_cm_rep - Sends a connection reply in response to a connection
+ *   request.
+ * @cm_id: Connection identifier that will be associated with the
+ *   connection request.
+ * @param: Connection reply information needed to establish the
+ *   connection.
+ */
+int ib_send_cm_rep(struct ib_cm_id *cm_id,
+		   struct ib_cm_rep_param *param);
+
+/**
+ * ib_send_cm_rtu - Sends a connection ready to use message in response
+ *   to a connection reply message.
+ * @cm_id: Connection identifier associated with the connection request.
+ * @private_data: Optional user-defined private data sent with the
+ *   ready to use message.
+ * @private_data_len: Size of the private data buffer, in bytes.
+ */
+int ib_send_cm_rtu(struct ib_cm_id *cm_id,
+		   const void *private_data,
+		   u8 private_data_len);
+
+/**
+ * ib_send_cm_dreq - Sends a disconnection request for an existing
+ *   connection.
+ * @cm_id: Connection identifier associated with the connection being
+ *   released.
+ * @private_data: Optional user-defined private data sent with the
+ *   disconnection request message.
+ * @private_data_len: Size of the private data buffer, in bytes.
+ */
+int ib_send_cm_dreq(struct ib_cm_id *cm_id,
+		    const void *private_data,
+		    u8 private_data_len);
+
+/**
+ * ib_send_cm_drep - Sends a disconnection reply to a disconnection request.
+ * @cm_id: Connection identifier associated with the connection being
+ *   released.
+ * @private_data: Optional user-defined private data sent with the
+ *   disconnection reply message.
+ * @private_data_len: Size of the private data buffer, in bytes.
+ *
+ * If the cm_id is in the correct state, the CM will transition the connection
+ * to the timewait state, even if an error occurs sending the DREP message.
+ */
+int ib_send_cm_drep(struct ib_cm_id *cm_id,
+		    const void *private_data,
+		    u8 private_data_len);
+
+/**
+ * ib_cm_establish - Forces a connection state to established.
+ * @cm_id: Connection identifier to transition to established.
+ *
+ * This routine should be invoked by users who receive messages on a
+ * connected QP before an RTU has been received.
+ */
+int ib_cm_establish(struct ib_cm_id *cm_id);
+
+/**
+ * ib_send_cm_rej - Sends a connection rejection message to the
+ *   remote node.
+ * @cm_id: Connection identifier associated with the connection being
+ *   rejected.
+ * @reason: Reason for the connection request rejection.
+ * @ari: Optional additional rejection information.
+ * @ari_length: Size of the additional rejection information, in bytes.
+ * @private_data: Optional user-defined private data sent with the
+ *   rejection message.
+ * @private_data_len: Size of the private data buffer, in bytes.
+ */
+int ib_send_cm_rej(struct ib_cm_id *cm_id,
+		   enum ib_cm_rej_reason reason,
+		   void *ari,
+		   u8 ari_length,
+		   const void *private_data,
+		   u8 private_data_len);
+
+/**
+ * ib_send_cm_mra - Sends a message receipt acknowledgement to a connection
+ *   message.
+ * @cm_id: Connection identifier associated with the connection message.
+ * @service_timeout: The maximum time required for the sender to reply to
+ *   to the connection message.
+ * @private_data: Optional user-defined private data sent with the
+ *   message receipt acknowledgement.
+ * @private_data_len: Size of the private data buffer, in bytes.
+ */
+int ib_send_cm_mra(struct ib_cm_id *cm_id,
+		   u8 service_timeout,
+		   const void *private_data,
+		   u8 private_data_len);
+
+/**
+ * ib_send_cm_lap - Sends a load alternate path request.
+ * @cm_id: Connection identifier associated with the load alternate path
+ *   message.
+ * @alternate_path: A path record that identifies the alternate path to
+ *   load.
+ * @private_data: Optional user-defined private data sent with the
+ *   load alternate path message.
+ * @private_data_len: Size of the private data buffer, in bytes.
+ */
+int ib_send_cm_lap(struct ib_cm_id *cm_id,
+		   struct ib_sa_path_rec *alternate_path,
+		   const void *private_data,
+		   u8 private_data_len);
+
+/**
+ * ib_cm_init_qp_attr - Initializes the QP attributes for use in transitioning
+ *   to a specified QP state.
+ * @cm_id: Communication identifier associated with the QP attributes to
+ *   initialize.
+ * @qp_attr: On input, specifies the desired QP state.  On output, the
+ *   mandatory and desired optional attributes will be set in order to
+ *   modify the QP to the specified state.
+ * @qp_attr_mask: The QP attribute mask that may be used to transition the
+ *   QP to the specified state.
+ *
+ * Users must set the @qp_attr->qp_state to the desired QP state.  This call
+ * will set all required attributes for the given transition, along with
+ * known optional attributes.  Users may override the attributes returned from
+ * this call before calling ib_modify_qp.
+ */
+int ib_cm_init_qp_attr(struct ib_cm_id *cm_id,
+		       struct ib_qp_attr *qp_attr,
+		       int *qp_attr_mask);
+
+/**
+ * ib_send_cm_apr - Sends an alternate path response message in response to
+ *   a load alternate path request.
+ * @cm_id: Connection identifier associated with the alternate path response.
+ * @status: Reply status sent with the alternate path response.
+ * @info: Optional additional information sent with the alternate path
+ *   response.
+ * @info_length: Size of the additional information, in bytes.
+ * @private_data: Optional user-defined private data sent with the
+ *   alternate path response message.
+ * @private_data_len: Size of the private data buffer, in bytes.
+ */
+int ib_send_cm_apr(struct ib_cm_id *cm_id,
+		   enum ib_cm_apr_status status,
+		   void *info,
+		   u8 info_length,
+		   const void *private_data,
+		   u8 private_data_len);
+
+struct ib_cm_sidr_req_param {
+	struct ib_sa_path_rec	*path;
+	u64			service_id;
+	int			timeout_ms;
+	const void		*private_data;
+	u8			private_data_len;
+	u8			max_cm_retries;
+	u16			pkey;
+};
+
+/**
+ * ib_send_cm_sidr_req - Sends a service ID resolution request to the
+ *   remote node.
+ * @cm_id: Communication identifier that will be associated with the
+ *   service ID resolution request.
+ * @param: Service ID resolution request information.
+ */
+int ib_send_cm_sidr_req(struct ib_cm_id *cm_id,
+			struct ib_cm_sidr_req_param *param);
+
+struct ib_cm_sidr_rep_param {
+	u32			qp_num;
+	u32			qkey;
+	enum ib_cm_sidr_status	status;
+	const void		*info;
+	u8			info_length;
+	const void		*private_data;
+	u8			private_data_len;
+};
+
+/**
+ * ib_send_cm_sidr_rep - Sends a service ID resolution request to the
+ *   remote node.
+ * @cm_id: Communication identifier associated with the received service ID
+ *   resolution request.
+ * @param: Service ID resolution reply information.
+ */
+int ib_send_cm_sidr_rep(struct ib_cm_id *cm_id,
+			struct ib_cm_sidr_rep_param *param);
+
+#endif /* IB_CM_H */
diff --git a/drivers/infiniband/include/ib_fmr_pool.h b/drivers/infiniband/include/ib_fmr_pool.h
index e8769657cbb..6c9e24d6e14 100644
--- a/drivers/infiniband/include/ib_fmr_pool.h
+++ b/drivers/infiniband/include/ib_fmr_pool.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2004 Topspin Corporation.  All rights reserved.
+ * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
@@ -29,7 +30,7 @@
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
  *
- * $Id: ib_fmr_pool.h 1349 2004-12-16 21:09:43Z roland $
+ * $Id: ib_fmr_pool.h 2730 2005-06-28 16:43:03Z sean.hefty $
  */
 
 #if !defined(IB_FMR_POOL_H)
@@ -78,7 +79,7 @@ struct ib_pool_fmr {
 struct ib_fmr_pool *ib_create_fmr_pool(struct ib_pd             *pd,
 				       struct ib_fmr_pool_param *params);
 
-int ib_destroy_fmr_pool(struct ib_fmr_pool *pool);
+void ib_destroy_fmr_pool(struct ib_fmr_pool *pool);
 
 int ib_flush_fmr_pool(struct ib_fmr_pool *pool);
 
diff --git a/drivers/infiniband/include/ib_mad.h b/drivers/infiniband/include/ib_mad.h
index 4a6bf6763a9..491b6f25b3b 100644
--- a/drivers/infiniband/include/ib_mad.h
+++ b/drivers/infiniband/include/ib_mad.h
@@ -33,12 +33,14 @@
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
  *
- * $Id: ib_mad.h 1389 2004-12-27 22:56:47Z roland $
+ * $Id: ib_mad.h 2775 2005-07-02 13:42:12Z halr $
  */
 
 #if !defined( IB_MAD_H )
 #define IB_MAD_H
 
+#include <linux/pci.h>
+
 #include <ib_verbs.h>
 
 /* Management base version */
@@ -56,6 +58,8 @@
 #define IB_MGMT_CLASS_VENDOR_RANGE2_START	0x30
 #define IB_MGMT_CLASS_VENDOR_RANGE2_END		0x4F
 
+#define	IB_OPENIB_OUI				(0x001405)
+
 /* Management methods */
 #define IB_MGMT_METHOD_GET			0x01
 #define IB_MGMT_METHOD_SET			0x02
@@ -70,18 +74,37 @@
 
 #define IB_MGMT_MAX_METHODS			128
 
+/* RMPP information */
+#define IB_MGMT_RMPP_VERSION			1
+
+#define IB_MGMT_RMPP_TYPE_DATA			1
+#define IB_MGMT_RMPP_TYPE_ACK			2
+#define IB_MGMT_RMPP_TYPE_STOP			3
+#define IB_MGMT_RMPP_TYPE_ABORT			4
+
+#define IB_MGMT_RMPP_FLAG_ACTIVE		1
+#define IB_MGMT_RMPP_FLAG_FIRST			(1<<1)
+#define IB_MGMT_RMPP_FLAG_LAST			(1<<2)
+
+#define IB_MGMT_RMPP_NO_RESPTIME		0x1F
+
+#define	IB_MGMT_RMPP_STATUS_SUCCESS		0
+#define	IB_MGMT_RMPP_STATUS_RESX		1
+#define	IB_MGMT_RMPP_STATUS_T2L			118
+#define	IB_MGMT_RMPP_STATUS_BAD_LEN		119
+#define	IB_MGMT_RMPP_STATUS_BAD_SEG		120
+#define	IB_MGMT_RMPP_STATUS_BADT		121
+#define	IB_MGMT_RMPP_STATUS_W2S			122
+#define	IB_MGMT_RMPP_STATUS_S2B			123
+#define	IB_MGMT_RMPP_STATUS_BAD_STATUS		124
+#define	IB_MGMT_RMPP_STATUS_UNV			125
+#define	IB_MGMT_RMPP_STATUS_TMR			126
+#define	IB_MGMT_RMPP_STATUS_UNSPEC		127
+
 #define IB_QP0		0
 #define IB_QP1		__constant_htonl(1)
 #define IB_QP1_QKEY	0x80010000
-
-struct ib_grh {
-	u32		version_tclass_flow;
-	u16		paylen;
-	u8		next_hdr;
-	u8		hop_limit;
-	union ib_gid	sgid;
-	union ib_gid	dgid;
-} __attribute__ ((packed));
+#define IB_QP_SET_QKEY	0x80000000
 
 struct ib_mad_hdr {
 	u8	base_version;
@@ -94,7 +117,7 @@ struct ib_mad_hdr {
 	u16	attr_id;
 	u16	resv;
 	u32	attr_mod;
-} __attribute__ ((packed));
+};
 
 struct ib_rmpp_hdr {
 	u8	rmpp_version;
@@ -103,17 +126,41 @@ struct ib_rmpp_hdr {
 	u8	rmpp_status;
 	u32	seg_num;
 	u32	paylen_newwin;
+};
+
+typedef u64 __bitwise ib_sa_comp_mask;
+
+#define IB_SA_COMP_MASK(n) ((__force ib_sa_comp_mask) cpu_to_be64(1ull << n))
+
+/*
+ * ib_sa_hdr and ib_sa_mad structures must be packed because they have
+ * 64-bit fields that are only 32-bit aligned. 64-bit architectures will
+ * lay them out wrong otherwise.  (And unfortunately they are sent on
+ * the wire so we can't change the layout)
+ */
+struct ib_sa_hdr {
+	u64			sm_key;
+	u16			attr_offset;
+	u16			reserved;
+	ib_sa_comp_mask		comp_mask;
 } __attribute__ ((packed));
 
 struct ib_mad {
 	struct ib_mad_hdr	mad_hdr;
 	u8			data[232];
-} __attribute__ ((packed));
+};
 
 struct ib_rmpp_mad {
 	struct ib_mad_hdr	mad_hdr;
 	struct ib_rmpp_hdr	rmpp_hdr;
 	u8			data[220];
+};
+
+struct ib_sa_mad {
+	struct ib_mad_hdr	mad_hdr;
+	struct ib_rmpp_hdr	rmpp_hdr;
+	struct ib_sa_hdr	sa_hdr;
+	u8			data[200];
 } __attribute__ ((packed));
 
 struct ib_vendor_mad {
@@ -122,7 +169,70 @@ struct ib_vendor_mad {
 	u8			reserved;
 	u8			oui[3];
 	u8			data[216];
-} __attribute__ ((packed));
+};
+
+/**
+ * ib_mad_send_buf - MAD data buffer and work request for sends.
+ * @mad: References an allocated MAD data buffer.  The size of the data
+ *   buffer is specified in the @send_wr.length field.
+ * @mapping: DMA mapping information.
+ * @mad_agent: MAD agent that allocated the buffer.
+ * @context: User-controlled context fields.
+ * @send_wr: An initialized work request structure used when sending the MAD.
+ *   The wr_id field of the work request is initialized to reference this
+ *   data structure.
+ * @sge: A scatter-gather list referenced by the work request.
+ *
+ * Users are responsible for initializing the MAD buffer itself, with the
+ * exception of specifying the payload length field in any RMPP MAD.
+ */
+struct ib_mad_send_buf {
+	struct ib_mad		*mad;
+	DECLARE_PCI_UNMAP_ADDR(mapping)
+	struct ib_mad_agent	*mad_agent;
+	void			*context[2];
+	struct ib_send_wr	send_wr;
+	struct ib_sge		sge;
+};
+
+/**
+ * ib_get_rmpp_resptime - Returns the RMPP response time.
+ * @rmpp_hdr: An RMPP header.
+ */
+static inline u8 ib_get_rmpp_resptime(struct ib_rmpp_hdr *rmpp_hdr)
+{
+	return rmpp_hdr->rmpp_rtime_flags >> 3;
+}
+
+/**
+ * ib_get_rmpp_flags - Returns the RMPP flags.
+ * @rmpp_hdr: An RMPP header.
+ */
+static inline u8 ib_get_rmpp_flags(struct ib_rmpp_hdr *rmpp_hdr)
+{
+	return rmpp_hdr->rmpp_rtime_flags & 0x7;
+}
+
+/**
+ * ib_set_rmpp_resptime - Sets the response time in an RMPP header.
+ * @rmpp_hdr: An RMPP header.
+ * @rtime: The response time to set.
+ */
+static inline void ib_set_rmpp_resptime(struct ib_rmpp_hdr *rmpp_hdr, u8 rtime)
+{
+	rmpp_hdr->rmpp_rtime_flags = ib_get_rmpp_flags(rmpp_hdr) | (rtime << 3);
+}
+
+/**
+ * ib_set_rmpp_flags - Sets the flags in an RMPP header.
+ * @rmpp_hdr: An RMPP header.
+ * @flags: The flags to set.
+ */
+static inline void ib_set_rmpp_flags(struct ib_rmpp_hdr *rmpp_hdr, u8 flags)
+{
+	rmpp_hdr->rmpp_rtime_flags = (rmpp_hdr->rmpp_rtime_flags & 0xF1) |
+				     (flags & 0x7);
+}
 
 struct ib_mad_agent;
 struct ib_mad_send_wc;
@@ -168,6 +278,7 @@ typedef void (*ib_mad_recv_handler)(struct ib_mad_agent *mad_agent,
  * ib_mad_agent - Used to track MAD registration with the access layer.
  * @device: Reference to device registration is on.
  * @qp: Reference to QP used for sending and receiving MADs.
+ * @mr: Memory region for system memory usable for DMA.
  * @recv_handler: Callback handler for a received MAD.
  * @send_handler: Callback handler for a sent MAD.
  * @snoop_handler: Callback handler for snooped sent MADs.
@@ -176,16 +287,19 @@ typedef void (*ib_mad_recv_handler)(struct ib_mad_agent *mad_agent,
  *   Unsolicited MADs sent by this client will have the upper 32-bits
  *   of their TID set to this value.
  * @port_num: Port number on which QP is registered
+ * @rmpp_version: If set, indicates the RMPP version used by this agent.
  */
 struct ib_mad_agent {
 	struct ib_device	*device;
 	struct ib_qp		*qp;
+	struct ib_mr		*mr;
 	ib_mad_recv_handler	recv_handler;
 	ib_mad_send_handler	send_handler;
 	ib_mad_snoop_handler	snoop_handler;
 	void			*context;
 	u32			hi_tid;
 	u8			port_num;
+	u8			rmpp_version;
 };
 
 /**
@@ -219,6 +333,7 @@ struct ib_mad_recv_buf {
  * ib_mad_recv_wc - received MAD information.
  * @wc: Completion information for the received data.
  * @recv_buf: Specifies the location of the received data buffer(s).
+ * @rmpp_list: Specifies a list of RMPP reassembled received MAD buffers.
  * @mad_len: The length of the received MAD, without duplicated headers.
  *
  * For received response, the wr_id field of the wc is set to the wr_id
@@ -227,6 +342,7 @@ struct ib_mad_recv_buf {
 struct ib_mad_recv_wc {
 	struct ib_wc		*wc;
 	struct ib_mad_recv_buf	recv_buf;
+	struct list_head	rmpp_list;
 	int			mad_len;
 };
 
@@ -322,6 +438,16 @@ int ib_unregister_mad_agent(struct ib_mad_agent *mad_agent);
  * @bad_send_wr: Specifies the MAD on which an error was encountered.
  *
  * Sent MADs are not guaranteed to complete in the order that they were posted.
+ *
+ * If the MAD requires RMPP, the data buffer should contain a single copy
+ * of the common MAD, RMPP, and class specific headers, followed by the class
+ * defined data.  If the class defined data would not divide evenly into
+ * RMPP segments, then space must be allocated at the end of the referenced
+ * buffer for any required padding.  To indicate the amount of class defined
+ * data being transferred, the paylen_newwin field in the RMPP header should
+ * be set to the size of the class specific header plus the amount of class
+ * defined data being transferred.  The paylen_newwin field should be
+ * specified in network-byte order.
  */
 int ib_post_send_mad(struct ib_mad_agent *mad_agent,
 		     struct ib_send_wr *send_wr,
@@ -334,15 +460,13 @@ int ib_post_send_mad(struct ib_mad_agent *mad_agent,
  *   referenced buffer should be at least the size of the mad_len specified
  *   by @mad_recv_wc.
  *
- * This call copies a chain of received RMPP MADs into a single data buffer,
+ * This call copies a chain of received MAD segments into a single data buffer,
  * removing duplicated headers.
  */
-void ib_coalesce_recv_mad(struct ib_mad_recv_wc *mad_recv_wc,
-			  void *buf);
+void ib_coalesce_recv_mad(struct ib_mad_recv_wc *mad_recv_wc, void *buf);
 
 /**
- * ib_free_recv_mad - Returns data buffers used to receive a MAD to the
- *   access layer.
+ * ib_free_recv_mad - Returns data buffers used to receive a MAD.
  * @mad_recv_wc: Work completion information for a received MAD.
  *
  * Clients receiving MADs through their ib_mad_recv_handler must call this
@@ -358,8 +482,18 @@ void ib_free_recv_mad(struct ib_mad_recv_wc *mad_recv_wc);
  * MADs will be returned to the user through the corresponding
  * ib_mad_send_handler.
  */
-void ib_cancel_mad(struct ib_mad_agent *mad_agent,
-		   u64 wr_id);
+void ib_cancel_mad(struct ib_mad_agent *mad_agent, u64 wr_id);
+
+/**
+ * ib_modify_mad - Modifies an outstanding send MAD operation.
+ * @mad_agent: Specifies the registration associated with sent MAD.
+ * @wr_id: Indicates the work request identifier of the MAD to modify.
+ * @timeout_ms: New timeout value for sent MAD.
+ *
+ * This call will reset the timeout value for a sent MAD to the specified
+ * value.
+ */
+int ib_modify_mad(struct ib_mad_agent *mad_agent, u64 wr_id, u32 timeout_ms);
 
 /**
  * ib_redirect_mad_qp - Registers a QP for MAD services.
@@ -401,4 +535,43 @@ struct ib_mad_agent *ib_redirect_mad_qp(struct ib_qp *qp,
 int ib_process_mad_wc(struct ib_mad_agent *mad_agent,
 		      struct ib_wc *wc);
 
+/**
+ * ib_create_send_mad - Allocate and initialize a data buffer and work request
+ *   for sending a MAD.
+ * @mad_agent: Specifies the registered MAD service to associate with the MAD.
+ * @remote_qpn: Specifies the QPN of the receiving node.
+ * @pkey_index: Specifies which PKey the MAD will be sent using.  This field
+ *   is valid only if the remote_qpn is QP 1.
+ * @ah: References the address handle used to transfer to the remote node.
+ * @rmpp_active: Indicates if the send will enable RMPP.
+ * @hdr_len: Indicates the size of the data header of the MAD.  This length
+ *   should include the common MAD header, RMPP header, plus any class
+ *   specific header.
+ * @data_len: Indicates the size of any user-transferred data.  The call will
+ *   automatically adjust the allocated buffer size to account for any
+ *   additional padding that may be necessary.
+ * @gfp_mask: GFP mask used for the memory allocation.
+ *
+ * This is a helper routine that may be used to allocate a MAD.  Users are
+ * not required to allocate outbound MADs using this call.  The returned
+ * MAD send buffer will reference a data buffer usable for sending a MAD, along
+ * with an initialized work request structure.  Users may modify the returned
+ * MAD data buffer or work request before posting the send.
+ *
+ * The returned data buffer will be cleared.  Users are responsible for
+ * initializing the common MAD and any class specific headers.  If @rmpp_active
+ * is set, the RMPP header will be initialized for sending.
+ */
+struct ib_mad_send_buf * ib_create_send_mad(struct ib_mad_agent *mad_agent,
+					    u32 remote_qpn, u16 pkey_index,
+					    struct ib_ah *ah, int rmpp_active,
+					    int hdr_len, int data_len,
+					    unsigned int __nocast gfp_mask);
+
+/**
+ * ib_free_send_mad - Returns data buffers used to send a MAD.
+ * @send_buf: Previously allocated send data buffer.
+ */
+void ib_free_send_mad(struct ib_mad_send_buf *send_buf);
+
 #endif /* IB_MAD_H */
diff --git a/drivers/infiniband/include/ib_sa.h b/drivers/infiniband/include/ib_sa.h
index 00222285eb9..6d999f7b5d9 100644
--- a/drivers/infiniband/include/ib_sa.h
+++ b/drivers/infiniband/include/ib_sa.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
+ * Copyright (c) 2005 Voltaire, Inc.  All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
@@ -29,7 +30,7 @@
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
  *
- * $Id: ib_sa.h 1389 2004-12-27 22:56:47Z roland $
+ * $Id: ib_sa.h 2811 2005-07-06 18:11:43Z halr $
  */
 
 #ifndef IB_SA_H
@@ -41,9 +42,11 @@
 #include <ib_mad.h>
 
 enum {
-	IB_SA_CLASS_VERSION	= 2,	/* IB spec version 1.1/1.2 */
+	IB_SA_CLASS_VERSION		= 2,	/* IB spec version 1.1/1.2 */
 
-	IB_SA_METHOD_DELETE	= 0x15
+	IB_SA_METHOD_GET_TABLE		= 0x12,
+	IB_SA_METHOD_GET_TABLE_RESP	= 0x92,
+	IB_SA_METHOD_DELETE		= 0x15
 };
 
 enum ib_sa_selector {
@@ -87,10 +90,6 @@ static inline int ib_sa_rate_enum_to_int(enum ib_sa_rate rate)
 	}
 }
 
-typedef u64 __bitwise ib_sa_comp_mask;
-
-#define IB_SA_COMP_MASK(n)	((__force ib_sa_comp_mask) cpu_to_be64(1ull << n))
-
 /*
  * Structures for SA records are named "struct ib_sa_xxx_rec."  No
  * attempt is made to pack structures to match the physical layout of
@@ -195,6 +194,61 @@ struct ib_sa_mcmember_rec {
 	int          proxy_join;
 };
 
+/* Service Record Component Mask Sec 15.2.5.14 Ver 1.1	*/
+#define IB_SA_SERVICE_REC_SERVICE_ID			IB_SA_COMP_MASK( 0)
+#define IB_SA_SERVICE_REC_SERVICE_GID			IB_SA_COMP_MASK( 1)
+#define IB_SA_SERVICE_REC_SERVICE_PKEY			IB_SA_COMP_MASK( 2)
+/* reserved:								 3 */
+#define IB_SA_SERVICE_REC_SERVICE_LEASE			IB_SA_COMP_MASK( 4)
+#define IB_SA_SERVICE_REC_SERVICE_KEY			IB_SA_COMP_MASK( 5)
+#define IB_SA_SERVICE_REC_SERVICE_NAME			IB_SA_COMP_MASK( 6)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_0		IB_SA_COMP_MASK( 7)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_1		IB_SA_COMP_MASK( 8)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_2		IB_SA_COMP_MASK( 9)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_3		IB_SA_COMP_MASK(10)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_4		IB_SA_COMP_MASK(11)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_5		IB_SA_COMP_MASK(12)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_6		IB_SA_COMP_MASK(13)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_7		IB_SA_COMP_MASK(14)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_8		IB_SA_COMP_MASK(15)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_9		IB_SA_COMP_MASK(16)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_10		IB_SA_COMP_MASK(17)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_11		IB_SA_COMP_MASK(18)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_12		IB_SA_COMP_MASK(19)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_13		IB_SA_COMP_MASK(20)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_14		IB_SA_COMP_MASK(21)
+#define IB_SA_SERVICE_REC_SERVICE_DATA8_15		IB_SA_COMP_MASK(22)
+#define IB_SA_SERVICE_REC_SERVICE_DATA16_0		IB_SA_COMP_MASK(23)
+#define IB_SA_SERVICE_REC_SERVICE_DATA16_1		IB_SA_COMP_MASK(24)
+#define IB_SA_SERVICE_REC_SERVICE_DATA16_2		IB_SA_COMP_MASK(25)
+#define IB_SA_SERVICE_REC_SERVICE_DATA16_3		IB_SA_COMP_MASK(26)
+#define IB_SA_SERVICE_REC_SERVICE_DATA16_4		IB_SA_COMP_MASK(27)
+#define IB_SA_SERVICE_REC_SERVICE_DATA16_5		IB_SA_COMP_MASK(28)
+#define IB_SA_SERVICE_REC_SERVICE_DATA16_6		IB_SA_COMP_MASK(29)
+#define IB_SA_SERVICE_REC_SERVICE_DATA16_7		IB_SA_COMP_MASK(30)
+#define IB_SA_SERVICE_REC_SERVICE_DATA32_0		IB_SA_COMP_MASK(31)
+#define IB_SA_SERVICE_REC_SERVICE_DATA32_1		IB_SA_COMP_MASK(32)
+#define IB_SA_SERVICE_REC_SERVICE_DATA32_2		IB_SA_COMP_MASK(33)
+#define IB_SA_SERVICE_REC_SERVICE_DATA32_3		IB_SA_COMP_MASK(34)
+#define IB_SA_SERVICE_REC_SERVICE_DATA64_0		IB_SA_COMP_MASK(35)
+#define IB_SA_SERVICE_REC_SERVICE_DATA64_1		IB_SA_COMP_MASK(36)
+
+#define IB_DEFAULT_SERVICE_LEASE 	0xFFFFFFFF
+
+struct ib_sa_service_rec {
+	u64		id;
+	union ib_gid	gid;
+	u16 		pkey;
+	/* reserved */
+	u32		lease;
+	u8		key[16];
+	u8		name[64];
+	u8		data8[16];
+	u16		data16[8];
+	u32		data32[4];
+	u64		data64[2];
+};
+
 struct ib_sa_query;
 
 void ib_sa_cancel_query(int id, struct ib_sa_query *query);
@@ -202,7 +256,7 @@ void ib_sa_cancel_query(int id, struct ib_sa_query *query);
 int ib_sa_path_rec_get(struct ib_device *device, u8 port_num,
 		       struct ib_sa_path_rec *rec,
 		       ib_sa_comp_mask comp_mask,
-		       int timeout_ms, int gfp_mask,
+		       int timeout_ms, unsigned int __nocast gfp_mask,
 		       void (*callback)(int status,
 					struct ib_sa_path_rec *resp,
 					void *context),
@@ -213,13 +267,24 @@ int ib_sa_mcmember_rec_query(struct ib_device *device, u8 port_num,
 			     u8 method,
 			     struct ib_sa_mcmember_rec *rec,
 			     ib_sa_comp_mask comp_mask,
-			     int timeout_ms, int gfp_mask,
+			     int timeout_ms, unsigned int __nocast gfp_mask,
 			     void (*callback)(int status,
 					      struct ib_sa_mcmember_rec *resp,
 					      void *context),
 			     void *context,
 			     struct ib_sa_query **query);
 
+int ib_sa_service_rec_query(struct ib_device *device, u8 port_num,
+			 u8 method,
+			 struct ib_sa_service_rec *rec,
+			 ib_sa_comp_mask comp_mask,
+			 int timeout_ms, unsigned int __nocast gfp_mask,
+			 void (*callback)(int status,
+					  struct ib_sa_service_rec *resp,
+					  void *context),
+			 void *context,
+			 struct ib_sa_query **sa_query);
+
 /**
  * ib_sa_mcmember_rec_set - Start an MCMember set query
  * @device:device to send query on
@@ -248,7 +313,7 @@ static inline int
 ib_sa_mcmember_rec_set(struct ib_device *device, u8 port_num,
 		       struct ib_sa_mcmember_rec *rec,
 		       ib_sa_comp_mask comp_mask,
-		       int timeout_ms, int gfp_mask,
+		       int timeout_ms, unsigned int __nocast gfp_mask,
 		       void (*callback)(int status,
 					struct ib_sa_mcmember_rec *resp,
 					void *context),
@@ -290,7 +355,7 @@ static inline int
 ib_sa_mcmember_rec_delete(struct ib_device *device, u8 port_num,
 			  struct ib_sa_mcmember_rec *rec,
 			  ib_sa_comp_mask comp_mask,
-			  int timeout_ms, int gfp_mask,
+			  int timeout_ms, unsigned int __nocast gfp_mask,
 			  void (*callback)(int status,
 					   struct ib_sa_mcmember_rec *resp,
 					   void *context),
diff --git a/drivers/infiniband/include/ib_user_cm.h b/drivers/infiniband/include/ib_user_cm.h
new file mode 100644
index 00000000000..500b1af6ff7
--- /dev/null
+++ b/drivers/infiniband/include/ib_user_cm.h
@@ -0,0 +1,328 @@
+/*
+ * Copyright (c) 2005 Topspin Communications.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * $Id: ib_user_cm.h 2576 2005-06-09 17:00:30Z libor $
+ */
+
+#ifndef IB_USER_CM_H
+#define IB_USER_CM_H
+
+#include <linux/types.h>
+
+#define IB_USER_CM_ABI_VERSION 1
+
+enum {
+	IB_USER_CM_CMD_CREATE_ID,
+	IB_USER_CM_CMD_DESTROY_ID,
+	IB_USER_CM_CMD_ATTR_ID,
+
+	IB_USER_CM_CMD_LISTEN,
+	IB_USER_CM_CMD_ESTABLISH,
+
+	IB_USER_CM_CMD_SEND_REQ,
+	IB_USER_CM_CMD_SEND_REP,
+	IB_USER_CM_CMD_SEND_RTU,
+	IB_USER_CM_CMD_SEND_DREQ,
+	IB_USER_CM_CMD_SEND_DREP,
+	IB_USER_CM_CMD_SEND_REJ,
+	IB_USER_CM_CMD_SEND_MRA,
+	IB_USER_CM_CMD_SEND_LAP,
+	IB_USER_CM_CMD_SEND_APR,
+	IB_USER_CM_CMD_SEND_SIDR_REQ,
+	IB_USER_CM_CMD_SEND_SIDR_REP,
+
+	IB_USER_CM_CMD_EVENT,
+};
+/*
+ * command ABI structures.
+ */
+struct ib_ucm_cmd_hdr {
+	__u32 cmd;
+	__u16 in;
+	__u16 out;
+};
+
+struct ib_ucm_create_id {
+	__u64 response;
+};
+
+struct ib_ucm_create_id_resp {
+	__u32 id;
+};
+
+struct ib_ucm_destroy_id {
+	__u32 id;
+};
+
+struct ib_ucm_attr_id {
+	__u64 response;
+	__u32 id;
+};
+
+struct ib_ucm_attr_id_resp {
+	__u64 service_id;
+	__u64 service_mask;
+	__u32 local_id;
+	__u32 remote_id;
+};
+
+struct ib_ucm_listen {
+	__u64 service_id;
+	__u64 service_mask;
+	__u32 id;
+};
+
+struct ib_ucm_establish {
+	__u32 id;
+};
+
+struct ib_ucm_private_data {
+	__u64 data;
+	__u32 id;
+	__u8  len;
+	__u8  reserved[3];
+};
+
+struct ib_ucm_path_rec {
+	__u8  dgid[16];
+	__u8  sgid[16];
+	__u16 dlid;
+	__u16 slid;
+	__u32 raw_traffic;
+	__u32 flow_label;
+	__u32 reversible;
+	__u32 mtu;
+	__u16 pkey;
+	__u8  hop_limit;
+	__u8  traffic_class;
+	__u8  numb_path;
+	__u8  sl;
+	__u8  mtu_selector;
+	__u8  rate_selector;
+	__u8  rate;
+	__u8  packet_life_time_selector;
+	__u8  packet_life_time;
+	__u8  preference;
+};
+
+struct ib_ucm_req {
+	__u32 id;
+	__u32 qpn;
+	__u32 qp_type;
+	__u32 psn;
+	__u64 sid;
+	__u64 data;
+	__u64 primary_path;
+	__u64 alternate_path;
+	__u8  len;
+	__u8  peer_to_peer;
+	__u8  responder_resources;
+	__u8  initiator_depth;
+	__u8  remote_cm_response_timeout;
+	__u8  flow_control;
+	__u8  local_cm_response_timeout;
+	__u8  retry_count;
+	__u8  rnr_retry_count;
+	__u8  max_cm_retries;
+	__u8  srq;
+	__u8  reserved[1];
+};
+
+struct ib_ucm_rep {
+	__u64 data;
+	__u32 id;
+	__u32 qpn;
+	__u32 psn;
+	__u8  len;
+	__u8  responder_resources;
+	__u8  initiator_depth;
+	__u8  target_ack_delay;
+	__u8  failover_accepted;
+	__u8  flow_control;
+	__u8  rnr_retry_count;
+	__u8  srq;
+};
+
+struct ib_ucm_info {
+	__u32 id;
+	__u32 status;
+	__u64 info;
+	__u64 data;
+	__u8  info_len;
+	__u8  data_len;
+	__u8  reserved[2];
+};
+
+struct ib_ucm_mra {
+	__u64 data;
+	__u32 id;
+	__u8  len;
+	__u8  timeout;
+	__u8  reserved[2];
+};
+
+struct ib_ucm_lap {
+	__u64 path;
+	__u64 data;
+	__u32 id;
+	__u8  len;
+	__u8  reserved[3];
+};
+
+struct ib_ucm_sidr_req {
+	__u32 id;
+	__u32 timeout;
+	__u64 sid;
+	__u64 data;
+	__u64 path;
+	__u16 pkey;
+	__u8  len;
+	__u8  max_cm_retries;
+};
+
+struct ib_ucm_sidr_rep {
+	__u32 id;
+	__u32 qpn;
+	__u32 qkey;
+	__u32 status;
+	__u64 info;
+	__u64 data;
+	__u8  info_len;
+	__u8  data_len;
+	__u8  reserved[2];
+};
+/*
+ * event notification ABI structures.
+ */
+struct ib_ucm_event_get {
+	__u64 response;
+	__u64 data;
+	__u64 info;
+	__u8  data_len;
+	__u8  info_len;
+	__u8  reserved[2];
+};
+
+struct ib_ucm_req_event_resp {
+	__u32                  listen_id;
+	/* device */
+	/* port */
+	struct ib_ucm_path_rec primary_path;
+	struct ib_ucm_path_rec alternate_path;
+	__u64                  remote_ca_guid;
+	__u32                  remote_qkey;
+	__u32                  remote_qpn;
+	__u32                  qp_type;
+	__u32                  starting_psn;
+	__u8  responder_resources;
+	__u8  initiator_depth;
+	__u8  local_cm_response_timeout;
+	__u8  flow_control;
+	__u8  remote_cm_response_timeout;
+	__u8  retry_count;
+	__u8  rnr_retry_count;
+	__u8  srq;
+};
+
+struct ib_ucm_rep_event_resp {
+	__u64 remote_ca_guid;
+	__u32 remote_qkey;
+	__u32 remote_qpn;
+	__u32 starting_psn;
+	__u8  responder_resources;
+	__u8  initiator_depth;
+	__u8  target_ack_delay;
+	__u8  failover_accepted;
+	__u8  flow_control;
+	__u8  rnr_retry_count;
+	__u8  srq;
+	__u8  reserved[1];
+};
+
+struct ib_ucm_rej_event_resp {
+	__u32 reason;
+	/* ari in ib_ucm_event_get info field. */
+};
+
+struct ib_ucm_mra_event_resp {
+	__u8  timeout;
+	__u8  reserved[3];
+};
+
+struct ib_ucm_lap_event_resp {
+	struct ib_ucm_path_rec path;
+};
+
+struct ib_ucm_apr_event_resp {
+	__u32 status;
+	/* apr info in ib_ucm_event_get info field. */
+};
+
+struct ib_ucm_sidr_req_event_resp {
+	__u32 listen_id;
+	/* device */
+	/* port */
+	__u16 pkey;
+	__u8  reserved[2];
+};
+
+struct ib_ucm_sidr_rep_event_resp {
+	__u32 status;
+	__u32 qkey;
+	__u32 qpn;
+	/* info in ib_ucm_event_get info field. */
+};
+
+#define IB_UCM_PRES_DATA      0x01
+#define IB_UCM_PRES_INFO      0x02
+#define IB_UCM_PRES_PRIMARY   0x04
+#define IB_UCM_PRES_ALTERNATE 0x08
+
+struct ib_ucm_event_resp {
+	__u32 id;
+	__u32 event;
+	__u32 present;
+	union {
+		struct ib_ucm_req_event_resp req_resp;
+		struct ib_ucm_rep_event_resp rep_resp;
+		struct ib_ucm_rej_event_resp rej_resp;
+		struct ib_ucm_mra_event_resp mra_resp;
+		struct ib_ucm_lap_event_resp lap_resp;
+		struct ib_ucm_apr_event_resp apr_resp;
+
+		struct ib_ucm_sidr_req_event_resp sidr_req_resp;
+		struct ib_ucm_sidr_rep_event_resp sidr_rep_resp;
+
+		__u32                             send_status;
+	} u;
+};
+
+#endif /* IB_USER_CM_H */
diff --git a/drivers/infiniband/include/ib_user_mad.h b/drivers/infiniband/include/ib_user_mad.h
index 06ad4a6075f..a9a56b50aac 100644
--- a/drivers/infiniband/include/ib_user_mad.h
+++ b/drivers/infiniband/include/ib_user_mad.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
+ * Copyright (c) 2005 Voltaire, Inc. All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
@@ -29,7 +30,7 @@
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
  *
- * $Id: ib_user_mad.h 1389 2004-12-27 22:56:47Z roland $
+ * $Id: ib_user_mad.h 2814 2005-07-06 19:14:09Z halr $
  */
 
 #ifndef IB_USER_MAD_H
@@ -42,7 +43,7 @@
  * Increment this value if any changes that break userspace ABI
  * compatibility are made.
  */
-#define IB_USER_MAD_ABI_VERSION	2
+#define IB_USER_MAD_ABI_VERSION	5
 
 /*
  * Make sure that all structs defined in this file remain laid out so
@@ -51,13 +52,13 @@
  */
 
 /**
- * ib_user_mad - MAD packet
- * @data - Contents of MAD
+ * ib_user_mad_hdr - MAD packet header
  * @id - ID of agent MAD received with/to be sent with
  * @status - 0 on successful receive, ETIMEDOUT if no response
  *   received (transaction ID in data[] will be set to TID of original
  *   request) (ignored on send)
  * @timeout_ms - Milliseconds to wait for response (unset on receive)
+ * @retries - Number of automatic retries to attempt
  * @qpn - Remote QP number received from/to be sent to
  * @qkey - Remote Q_Key to be sent with (unset on receive)
  * @lid - Remote lid received from/to be sent to
@@ -72,11 +73,12 @@
  *
  * All multi-byte quantities are stored in network (big endian) byte order.
  */
-struct ib_user_mad {
-	__u8	data[256];
+struct ib_user_mad_hdr {
 	__u32	id;
 	__u32	status;
 	__u32	timeout_ms;
+	__u32	retries;
+	__u32	length;
 	__u32	qpn;
 	__u32   qkey;
 	__u16	lid;
@@ -91,6 +93,17 @@ struct ib_user_mad {
 };
 
 /**
+ * ib_user_mad - MAD packet
+ * @hdr - MAD packet header
+ * @data - Contents of MAD
+ *
+ */
+struct ib_user_mad {
+	struct ib_user_mad_hdr hdr;
+	__u8	data[0];
+};
+
+/**
  * ib_user_mad_reg_req - MAD registration request
  * @id - Set by the kernel; used to identify agent in future requests.
  * @qpn - Queue pair number; must be 0 or 1.
@@ -103,6 +116,8 @@ struct ib_user_mad {
  *   management class to receive.
  * @oui: Indicates IEEE OUI when mgmt_class is a vendor class
  *   in the range from 0x30 to 0x4f. Otherwise not used.
+ * @rmpp_version: If set, indicates the RMPP version used.
+ *
  */
 struct ib_user_mad_reg_req {
 	__u32	id;
@@ -111,6 +126,7 @@ struct ib_user_mad_reg_req {
 	__u8	mgmt_class;
 	__u8	mgmt_class_version;
 	__u8    oui[3];
+	__u8	rmpp_version;
 };
 
 #define IB_IOCTL_MAGIC		0x1b
diff --git a/drivers/infiniband/include/ib_verbs.h b/drivers/infiniband/include/ib_verbs.h
index e5bd9a10c20..5d24edaa66e 100644
--- a/drivers/infiniband/include/ib_verbs.h
+++ b/drivers/infiniband/include/ib_verbs.h
@@ -289,6 +289,15 @@ struct ib_global_route {
 	u8		traffic_class;
 };
 
+struct ib_grh {
+	u32		version_tclass_flow;
+	u16		paylen;
+	u8		next_hdr;
+	u8		hop_limit;
+	union ib_gid	sgid;
+	union ib_gid	dgid;
+};
+
 enum {
 	IB_MULTICAST_QPN = 0xffffff
 };
@@ -566,6 +575,7 @@ struct ib_send_wr {
 			u32	remote_qpn;
 			u32	remote_qkey;
 			int	timeout_ms; /* valid for MADs only */
+			int	retries;    /* valid for MADs only */
 			u16	pkey_index; /* valid for GSI only */
 			u8	port_num;   /* valid for DR SMPs on switch only */
 		} ud;
@@ -990,6 +1000,21 @@ int ib_dealloc_pd(struct ib_pd *pd);
 struct ib_ah *ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr);
 
 /**
+ * ib_create_ah_from_wc - Creates an address handle associated with the
+ *   sender of the specified work completion.
+ * @pd: The protection domain associated with the address handle.
+ * @wc: Work completion information associated with a received message.
+ * @grh: References the received global route header.  This parameter is
+ *   ignored unless the work completion indicates that the GRH is valid.
+ * @port_num: The outbound port number to associate with the address.
+ *
+ * The address handle is used to reference a local or global destination
+ * in all UD QP post sends.
+ */
+struct ib_ah *ib_create_ah_from_wc(struct ib_pd *pd, struct ib_wc *wc,
+				   struct ib_grh *grh, u8 port_num);
+
+/**
  * ib_modify_ah - Modifies the address vector associated with an address
  *   handle.
  * @ah: The address handle to modify.
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_ib.c b/drivers/infiniband/ulp/ipoib/ipoib_ib.c
index 8238766746b..eee82363167 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib_ib.c
+++ b/drivers/infiniband/ulp/ipoib/ipoib_ib.c
@@ -81,7 +81,7 @@ void ipoib_free_ah(struct kref *kref)
 
 	unsigned long flags;
 
-	if (ah->last_send <= priv->tx_tail) {
+	if ((int) priv->tx_tail - (int) ah->last_send >= 0) {
 		ipoib_dbg(priv, "Freeing ah %p\n", ah->ah);
 		ib_destroy_ah(ah->ah);
 		kfree(ah);
@@ -355,7 +355,7 @@ static void __ipoib_reap_ah(struct net_device *dev)
 
 	spin_lock_irq(&priv->lock);
 	list_for_each_entry_safe(ah, tah, &priv->dead_ahs, list)
-		if (ah->last_send <= priv->tx_tail) {
+		if ((int) priv->tx_tail - (int) ah->last_send >= 0) {
 			list_del(&ah->list);
 			list_add_tail(&ah->list, &remove_list);
 		}
@@ -486,7 +486,7 @@ int ipoib_ib_dev_stop(struct net_device *dev)
 			 * assume the HW is wedged and just free up
 			 * all our pending work requests.
 			 */
-			while (priv->tx_tail < priv->tx_head) {
+			while ((int) priv->tx_tail - (int) priv->tx_head < 0) {
 				tx_req = &priv->tx_ring[priv->tx_tail &
 							(IPOIB_TX_RING_SIZE - 1)];
 				dma_unmap_single(priv->ca->dma_device,
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_main.c b/drivers/infiniband/ulp/ipoib/ipoib_main.c
index 6f60abbaebd..fa00816a3cf 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib_main.c
+++ b/drivers/infiniband/ulp/ipoib/ipoib_main.c
@@ -600,9 +600,10 @@ static int ipoib_start_xmit(struct sk_buff *skb, struct net_device *dev)
 
 			ipoib_mcast_send(dev, (union ib_gid *) (phdr->hwaddr + 4), skb);
 		} else {
-			/* unicast GID -- should be ARP reply */
+			/* unicast GID -- should be ARP or RARP reply */
 
-			if (be16_to_cpup((u16 *) skb->data) != ETH_P_ARP) {
+			if ((be16_to_cpup((__be16 *) skb->data) != ETH_P_ARP) &&
+			    (be16_to_cpup((__be16 *) skb->data) != ETH_P_RARP)) {
 				ipoib_warn(priv, "Unicast, no %s: type %04x, QPN %06x "
 					   IPOIB_GID_FMT "\n",
 					   skb->dst ? "neigh" : "dst",
diff --git a/drivers/input/evdev.c b/drivers/input/evdev.c
index 374f404e81d..20e3a165989 100644
--- a/drivers/input/evdev.c
+++ b/drivers/input/evdev.c
@@ -320,6 +320,7 @@ static long evdev_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 			if (t < 0 || t >= dev->keycodemax || !dev->keycodesize) return -EINVAL;
 			if (get_user(v, ip + 1)) return -EFAULT;
 			if (v < 0 || v > KEY_MAX) return -EINVAL;
+			if (v >> (dev->keycodesize * 8)) return -EINVAL;
 			u = SET_INPUT_KEYCODE(dev, t, v);
 			clear_bit(u, dev->keybit);
 			set_bit(v, dev->keybit);
diff --git a/drivers/input/input.c b/drivers/input/input.c
index 7c4b4d37b3e..a275211c8e1 100644
--- a/drivers/input/input.c
+++ b/drivers/input/input.c
@@ -48,12 +48,6 @@ static LIST_HEAD(input_handler_list);
 
 static struct input_handler *input_table[8];
 
-#ifdef CONFIG_PROC_FS
-static struct proc_dir_entry *proc_bus_input_dir;
-static DECLARE_WAIT_QUEUE_HEAD(input_devices_poll_wait);
-static int input_devices_state;
-#endif
-
 void input_event(struct input_dev *dev, unsigned int type, unsigned int code, int value)
 {
 	struct input_handle *handle;
@@ -312,6 +306,7 @@ static struct input_device_id *input_match_device(struct input_device_id *id, st
 	return NULL;
 }
 
+
 /*
  * Input hotplugging interface - loading event handlers based on
  * device bitfields.
@@ -428,6 +423,177 @@ static void input_call_hotplug(char *verb, struct input_dev *dev)
 
 #endif
 
+#ifdef CONFIG_PROC_FS
+
+static struct proc_dir_entry *proc_bus_input_dir;
+static DECLARE_WAIT_QUEUE_HEAD(input_devices_poll_wait);
+static int input_devices_state;
+
+static inline void input_wakeup_procfs_readers(void)
+{
+	input_devices_state++;
+	wake_up(&input_devices_poll_wait);
+}
+
+static unsigned int input_devices_poll(struct file *file, poll_table *wait)
+{
+	int state = input_devices_state;
+	poll_wait(file, &input_devices_poll_wait, wait);
+	if (state != input_devices_state)
+		return POLLIN | POLLRDNORM;
+	return 0;
+}
+
+#define SPRINTF_BIT_B(bit, name, max) \
+	do { \
+		len += sprintf(buf + len, "B: %s", name); \
+		for (i = NBITS(max) - 1; i >= 0; i--) \
+			if (dev->bit[i]) break; \
+		for (; i >= 0; i--) \
+			len += sprintf(buf + len, "%lx ", dev->bit[i]); \
+		len += sprintf(buf + len, "\n"); \
+	} while (0)
+
+#define SPRINTF_BIT_B2(bit, name, max, ev) \
+	do { \
+		if (test_bit(ev, dev->evbit)) \
+			SPRINTF_BIT_B(bit, name, max); \
+	} while (0)
+
+static int input_devices_read(char *buf, char **start, off_t pos, int count, int *eof, void *data)
+{
+	struct input_dev *dev;
+	struct input_handle *handle;
+
+	off_t at = 0;
+	int i, len, cnt = 0;
+
+	list_for_each_entry(dev, &input_dev_list, node) {
+
+		len = sprintf(buf, "I: Bus=%04x Vendor=%04x Product=%04x Version=%04x\n",
+			dev->id.bustype, dev->id.vendor, dev->id.product, dev->id.version);
+
+		len += sprintf(buf + len, "N: Name=\"%s\"\n", dev->name ? dev->name : "");
+		len += sprintf(buf + len, "P: Phys=%s\n", dev->phys ? dev->phys : "");
+		len += sprintf(buf + len, "H: Handlers=");
+
+		list_for_each_entry(handle, &dev->h_list, d_node)
+			len += sprintf(buf + len, "%s ", handle->name);
+
+		len += sprintf(buf + len, "\n");
+
+		SPRINTF_BIT_B(evbit, "EV=", EV_MAX);
+		SPRINTF_BIT_B2(keybit, "KEY=", KEY_MAX, EV_KEY);
+		SPRINTF_BIT_B2(relbit, "REL=", REL_MAX, EV_REL);
+		SPRINTF_BIT_B2(absbit, "ABS=", ABS_MAX, EV_ABS);
+		SPRINTF_BIT_B2(mscbit, "MSC=", MSC_MAX, EV_MSC);
+		SPRINTF_BIT_B2(ledbit, "LED=", LED_MAX, EV_LED);
+		SPRINTF_BIT_B2(sndbit, "SND=", SND_MAX, EV_SND);
+		SPRINTF_BIT_B2(ffbit,  "FF=",  FF_MAX, EV_FF);
+
+		len += sprintf(buf + len, "\n");
+
+		at += len;
+
+		if (at >= pos) {
+			if (!*start) {
+				*start = buf + (pos - (at - len));
+				cnt = at - pos;
+			} else  cnt += len;
+			buf += len;
+			if (cnt >= count)
+				break;
+		}
+	}
+
+	if (&dev->node == &input_dev_list)
+		*eof = 1;
+
+	return (count > cnt) ? cnt : count;
+}
+
+static int input_handlers_read(char *buf, char **start, off_t pos, int count, int *eof, void *data)
+{
+	struct input_handler *handler;
+
+	off_t at = 0;
+	int len = 0, cnt = 0;
+	int i = 0;
+
+	list_for_each_entry(handler, &input_handler_list, node) {
+
+		if (handler->fops)
+			len = sprintf(buf, "N: Number=%d Name=%s Minor=%d\n",
+				i++, handler->name, handler->minor);
+		else
+			len = sprintf(buf, "N: Number=%d Name=%s\n",
+				i++, handler->name);
+
+		at += len;
+
+		if (at >= pos) {
+			if (!*start) {
+				*start = buf + (pos - (at - len));
+				cnt = at - pos;
+			} else  cnt += len;
+			buf += len;
+			if (cnt >= count)
+				break;
+		}
+	}
+	if (&handler->node == &input_handler_list)
+		*eof = 1;
+
+	return (count > cnt) ? cnt : count;
+}
+
+static struct file_operations input_fileops;
+
+static int __init input_proc_init(void)
+{
+	struct proc_dir_entry *entry;
+
+	proc_bus_input_dir = proc_mkdir("input", proc_bus);
+	if (!proc_bus_input_dir)
+		return -ENOMEM;
+
+	proc_bus_input_dir->owner = THIS_MODULE;
+
+	entry = create_proc_read_entry("devices", 0, proc_bus_input_dir, input_devices_read, NULL);
+	if (!entry)
+		goto fail1;
+
+	entry->owner = THIS_MODULE;
+	input_fileops = *entry->proc_fops;
+	entry->proc_fops = &input_fileops;
+	entry->proc_fops->poll = input_devices_poll;
+
+	entry = create_proc_read_entry("handlers", 0, proc_bus_input_dir, input_handlers_read, NULL);
+	if (!entry)
+		goto fail2;
+
+	entry->owner = THIS_MODULE;
+
+	return 0;
+
+ fail2:	remove_proc_entry("devices", proc_bus_input_dir);
+ fail1: remove_proc_entry("input", proc_bus);
+	return -ENOMEM;
+}
+
+static void input_proc_exit(void)
+{
+	remove_proc_entry("devices", proc_bus_input_dir);
+	remove_proc_entry("handlers", proc_bus_input_dir);
+	remove_proc_entry("input", proc_bus);
+}
+
+#else /* !CONFIG_PROC_FS */
+static inline void input_wakeup_procfs_readers(void) { }
+static inline int input_proc_init(void) { return 0; }
+static inline void input_proc_exit(void) { }
+#endif
+
 void input_register_device(struct input_dev *dev)
 {
 	struct input_handle *handle;
@@ -464,10 +630,7 @@ void input_register_device(struct input_dev *dev)
 	input_call_hotplug("add", dev);
 #endif
 
-#ifdef CONFIG_PROC_FS
-	input_devices_state++;
-	wake_up(&input_devices_poll_wait);
-#endif
+	input_wakeup_procfs_readers();
 }
 
 void input_unregister_device(struct input_dev *dev)
@@ -491,10 +654,7 @@ void input_unregister_device(struct input_dev *dev)
 
 	list_del_init(&dev->node);
 
-#ifdef CONFIG_PROC_FS
-	input_devices_state++;
-	wake_up(&input_devices_poll_wait);
-#endif
+	input_wakeup_procfs_readers();
 }
 
 void input_register_handler(struct input_handler *handler)
@@ -518,10 +678,7 @@ void input_register_handler(struct input_handler *handler)
 				if ((handle = handler->connect(handler, dev, id)))
 					input_link_handle(handle);
 
-#ifdef CONFIG_PROC_FS
-	input_devices_state++;
-	wake_up(&input_devices_poll_wait);
-#endif
+	input_wakeup_procfs_readers();
 }
 
 void input_unregister_handler(struct input_handler *handler)
@@ -540,10 +697,7 @@ void input_unregister_handler(struct input_handler *handler)
 	if (handler->fops != NULL)
 		input_table[handler->minor >> 5] = NULL;
 
-#ifdef CONFIG_PROC_FS
-	input_devices_state++;
-	wake_up(&input_devices_poll_wait);
-#endif
+	input_wakeup_procfs_readers();
 }
 
 static int input_open_file(struct inode *inode, struct file *file)
@@ -582,190 +736,43 @@ static struct file_operations input_fops = {
 	.open = input_open_file,
 };
 
-#ifdef CONFIG_PROC_FS
-
-#define SPRINTF_BIT_B(bit, name, max) \
-	do { \
-		len += sprintf(buf + len, "B: %s", name); \
-		for (i = NBITS(max) - 1; i >= 0; i--) \
-			if (dev->bit[i]) break; \
-		for (; i >= 0; i--) \
-			len += sprintf(buf + len, "%lx ", dev->bit[i]); \
-		len += sprintf(buf + len, "\n"); \
-	} while (0)
-
-#define SPRINTF_BIT_B2(bit, name, max, ev) \
-	do { \
-		if (test_bit(ev, dev->evbit)) \
-			SPRINTF_BIT_B(bit, name, max); \
-	} while (0)
-
-
-static unsigned int input_devices_poll(struct file *file, poll_table *wait)
-{
-	int state = input_devices_state;
-	poll_wait(file, &input_devices_poll_wait, wait);
-	if (state != input_devices_state)
-		return POLLIN | POLLRDNORM;
-	return 0;
-}
+struct class *input_class;
 
-static int input_devices_read(char *buf, char **start, off_t pos, int count, int *eof, void *data)
+static int __init input_init(void)
 {
-	struct input_dev *dev;
-	struct input_handle *handle;
-
-	off_t at = 0;
-	int i, len, cnt = 0;
-
-	list_for_each_entry(dev, &input_dev_list, node) {
-
-		len = sprintf(buf, "I: Bus=%04x Vendor=%04x Product=%04x Version=%04x\n",
-			dev->id.bustype, dev->id.vendor, dev->id.product, dev->id.version);
-
-		len += sprintf(buf + len, "N: Name=\"%s\"\n", dev->name ? dev->name : "");
-		len += sprintf(buf + len, "P: Phys=%s\n", dev->phys ? dev->phys : "");
-		len += sprintf(buf + len, "H: Handlers=");
-
-		list_for_each_entry(handle, &dev->h_list, d_node)
-			len += sprintf(buf + len, "%s ", handle->name);
-
-		len += sprintf(buf + len, "\n");
-
-		SPRINTF_BIT_B(evbit, "EV=", EV_MAX);
-		SPRINTF_BIT_B2(keybit, "KEY=", KEY_MAX, EV_KEY);
-		SPRINTF_BIT_B2(relbit, "REL=", REL_MAX, EV_REL);
-		SPRINTF_BIT_B2(absbit, "ABS=", ABS_MAX, EV_ABS);
-		SPRINTF_BIT_B2(mscbit, "MSC=", MSC_MAX, EV_MSC);
-		SPRINTF_BIT_B2(ledbit, "LED=", LED_MAX, EV_LED);
-		SPRINTF_BIT_B2(sndbit, "SND=", SND_MAX, EV_SND);
-		SPRINTF_BIT_B2(ffbit,  "FF=",  FF_MAX, EV_FF);
-
-		len += sprintf(buf + len, "\n");
-
-		at += len;
+	int err;
 
-		if (at >= pos) {
-			if (!*start) {
-				*start = buf + (pos - (at - len));
-				cnt = at - pos;
-			} else  cnt += len;
-			buf += len;
-			if (cnt >= count)
-				break;
-		}
+	input_class = class_create(THIS_MODULE, "input");
+	if (IS_ERR(input_class)) {
+		printk(KERN_ERR "input: unable to register input class\n");
+		return PTR_ERR(input_class);
 	}
 
-	if (&dev->node == &input_dev_list)
-		*eof = 1;
-
-	return (count > cnt) ? cnt : count;
-}
-
-static int input_handlers_read(char *buf, char **start, off_t pos, int count, int *eof, void *data)
-{
-	struct input_handler *handler;
-
-	off_t at = 0;
-	int len = 0, cnt = 0;
-	int i = 0;
-
-	list_for_each_entry(handler, &input_handler_list, node) {
-
-		if (handler->fops)
-			len = sprintf(buf, "N: Number=%d Name=%s Minor=%d\n",
-				i++, handler->name, handler->minor);
-		else
-			len = sprintf(buf, "N: Number=%d Name=%s\n",
-				i++, handler->name);
-
-		at += len;
+	err = input_proc_init();
+	if (err)
+		goto fail1;
 
-		if (at >= pos) {
-			if (!*start) {
-				*start = buf + (pos - (at - len));
-				cnt = at - pos;
-			} else  cnt += len;
-			buf += len;
-			if (cnt >= count)
-				break;
-		}
+	err = register_chrdev(INPUT_MAJOR, "input", &input_fops);
+	if (err) {
+		printk(KERN_ERR "input: unable to register char major %d", INPUT_MAJOR);
+		goto fail2;
 	}
-	if (&handler->node == &input_handler_list)
-		*eof = 1;
-
-	return (count > cnt) ? cnt : count;
-}
-
-static struct file_operations input_fileops;
 
-static int __init input_proc_init(void)
-{
-	struct proc_dir_entry *entry;
+	err = devfs_mk_dir("input");
+	if (err)
+		goto fail3;
 
-	proc_bus_input_dir = proc_mkdir("input", proc_bus);
-	if (proc_bus_input_dir == NULL)
-		return -ENOMEM;
-	proc_bus_input_dir->owner = THIS_MODULE;
-	entry = create_proc_read_entry("devices", 0, proc_bus_input_dir, input_devices_read, NULL);
-	if (entry == NULL) {
-		remove_proc_entry("input", proc_bus);
-		return -ENOMEM;
-	}
-	entry->owner = THIS_MODULE;
-	input_fileops = *entry->proc_fops;
-	entry->proc_fops = &input_fileops;
-	entry->proc_fops->poll = input_devices_poll;
-	entry = create_proc_read_entry("handlers", 0, proc_bus_input_dir, input_handlers_read, NULL);
-	if (entry == NULL) {
-		remove_proc_entry("devices", proc_bus_input_dir);
-		remove_proc_entry("input", proc_bus);
-		return -ENOMEM;
-	}
-	entry->owner = THIS_MODULE;
 	return 0;
-}
-#else /* !CONFIG_PROC_FS */
-static inline int input_proc_init(void) { return 0; }
-#endif
 
-struct class *input_class;
-
-static int __init input_init(void)
-{
-	int retval = -ENOMEM;
-
-	input_class = class_create(THIS_MODULE, "input");
-	if (IS_ERR(input_class))
-		return PTR_ERR(input_class);
-	input_proc_init();
-	retval = register_chrdev(INPUT_MAJOR, "input", &input_fops);
-	if (retval) {
-		printk(KERN_ERR "input: unable to register char major %d", INPUT_MAJOR);
-		remove_proc_entry("devices", proc_bus_input_dir);
-		remove_proc_entry("handlers", proc_bus_input_dir);
-		remove_proc_entry("input", proc_bus);
-		class_destroy(input_class);
-		return retval;
-	}
-
-	retval = devfs_mk_dir("input");
-	if (retval) {
-		remove_proc_entry("devices", proc_bus_input_dir);
-		remove_proc_entry("handlers", proc_bus_input_dir);
-		remove_proc_entry("input", proc_bus);
-		unregister_chrdev(INPUT_MAJOR, "input");
-		class_destroy(input_class);
-	}
-	return retval;
+ fail3:	unregister_chrdev(INPUT_MAJOR, "input");
+ fail2:	input_proc_exit();
+ fail1:	class_destroy(input_class);
+	return err;
 }
 
 static void __exit input_exit(void)
 {
-	remove_proc_entry("devices", proc_bus_input_dir);
-	remove_proc_entry("handlers", proc_bus_input_dir);
-	remove_proc_entry("input", proc_bus);
-
+	input_proc_exit();
 	devfs_remove("input");
 	unregister_chrdev(INPUT_MAJOR, "input");
 	class_destroy(input_class);
diff --git a/drivers/input/joydev.c b/drivers/input/joydev.c
index ff8e1bbd0e1..e0938d1d3ad 100644
--- a/drivers/input/joydev.c
+++ b/drivers/input/joydev.c
@@ -37,8 +37,6 @@ MODULE_LICENSE("GPL");
 #define JOYDEV_MINORS		16
 #define JOYDEV_BUFFER_SIZE	64
 
-#define MSECS(t)	(1000 * ((t) / HZ) + 1000 * ((t) % HZ) / HZ)
-
 struct joydev {
 	int exist;
 	int open;
@@ -117,7 +115,7 @@ static void joydev_event(struct input_handle *handle, unsigned int type, unsigne
 			return;
 	}
 
-	event.time = MSECS(jiffies);
+	event.time = jiffies_to_msecs(jiffies);
 
 	list_for_each_entry(list, &joydev->list, node) {
 
@@ -245,7 +243,7 @@ static ssize_t joydev_read(struct file *file, char __user *buf, size_t count, lo
 
 		struct js_event event;
 
-		event.time = MSECS(jiffies);
+		event.time = jiffies_to_msecs(jiffies);
 
 		if (list->startup < joydev->nkey) {
 			event.type = JS_EVENT_BUTTON | JS_EVENT_INIT;
diff --git a/drivers/input/misc/uinput.c b/drivers/input/misc/uinput.c
index 98710997aaa..d5c5b32045a 100644
--- a/drivers/input/misc/uinput.c
+++ b/drivers/input/misc/uinput.c
@@ -36,16 +36,6 @@
 #include <linux/miscdevice.h>
 #include <linux/uinput.h>
 
-static int uinput_dev_open(struct input_dev *dev)
-{
-	return 0;
-}
-
-static void uinput_dev_close(struct input_dev *dev)
-{
-
-}
-
 static int uinput_dev_event(struct input_dev *dev, unsigned int type, unsigned int code, int value)
 {
 	struct uinput_device	*udev;
@@ -63,22 +53,24 @@ static int uinput_dev_event(struct input_dev *dev, unsigned int type, unsigned i
 	return 0;
 }
 
-static int uinput_request_alloc_id(struct input_dev *dev, struct uinput_request *request)
+static int uinput_request_alloc_id(struct uinput_device *udev, struct uinput_request *request)
 {
 	/* Atomically allocate an ID for the given request. Returns 0 on success. */
-	struct uinput_device *udev = dev->private;
 	int id;
+	int err = -1;
+
+	spin_lock(&udev->requests_lock);
 
-	down(&udev->requests_sem);
-	for (id=0; id<UINPUT_NUM_REQUESTS; id++)
+	for (id = 0; id < UINPUT_NUM_REQUESTS; id++)
 		if (!udev->requests[id]) {
-			udev->requests[id] = request;
 			request->id = id;
-			up(&udev->requests_sem);
-			return 0;
+			udev->requests[id] = request;
+			err = 0;
+			break;
 		}
-	up(&udev->requests_sem);
-	return -1;
+
+	spin_unlock(&udev->requests_lock);
+	return err;
 }
 
 static struct uinput_request* uinput_request_find(struct uinput_device *udev, int id)
@@ -86,70 +78,78 @@ static struct uinput_request* uinput_request_find(struct uinput_device *udev, in
 	/* Find an input request, by ID. Returns NULL if the ID isn't valid. */
 	if (id >= UINPUT_NUM_REQUESTS || id < 0)
 		return NULL;
-	if (udev->requests[id]->completed)
-		return NULL;
 	return udev->requests[id];
 }
 
-static void uinput_request_init(struct input_dev *dev, struct uinput_request *request, int code)
+static inline int uinput_request_reserve_slot(struct uinput_device *udev, struct uinput_request *request)
 {
-	struct uinput_device *udev = dev->private;
+	/* Allocate slot. If none are available right away, wait. */
+	return wait_event_interruptible(udev->requests_waitq,
+					!uinput_request_alloc_id(udev, request));
+}
 
-	memset(request, 0, sizeof(struct uinput_request));
-	request->code = code;
-	init_waitqueue_head(&request->waitq);
+static void uinput_request_done(struct uinput_device *udev, struct uinput_request *request)
+{
+	complete(&request->done);
 
-	/* Allocate an ID. If none are available right away, wait. */
-	request->retval = wait_event_interruptible(udev->requests_waitq,
-				       !uinput_request_alloc_id(dev, request));
+	/* Mark slot as available */
+	udev->requests[request->id] = NULL;
+	wake_up_interruptible(&udev->requests_waitq);
 }
 
-static void uinput_request_submit(struct input_dev *dev, struct uinput_request *request)
+static int uinput_request_submit(struct input_dev *dev, struct uinput_request *request)
 {
-	struct uinput_device *udev = dev->private;
 	int retval;
 
 	/* Tell our userspace app about this new request by queueing an input event */
 	uinput_dev_event(dev, EV_UINPUT, request->code, request->id);
 
 	/* Wait for the request to complete */
-	retval = wait_event_interruptible(request->waitq, request->completed);
-	if (retval)
-		request->retval = retval;
+	retval = wait_for_completion_interruptible(&request->done);
+	if (!retval)
+		retval = request->retval;
 
-	/* Release this request's ID, let others know it's available */
-	udev->requests[request->id] = NULL;
-	wake_up_interruptible(&udev->requests_waitq);
+	return retval;
 }
 
 static int uinput_dev_upload_effect(struct input_dev *dev, struct ff_effect *effect)
 {
 	struct uinput_request request;
+	int retval;
 
 	if (!test_bit(EV_FF, dev->evbit))
 		return -ENOSYS;
 
-	uinput_request_init(dev, &request, UI_FF_UPLOAD);
-	if (request.retval)
-		return request.retval;
+	request.id = -1;
+	init_completion(&request.done);
+	request.code = UI_FF_UPLOAD;
 	request.u.effect = effect;
-	uinput_request_submit(dev, &request);
-	return request.retval;
+
+	retval = uinput_request_reserve_slot(dev->private, &request);
+	if (!retval)
+		retval = uinput_request_submit(dev, &request);
+
+	return retval;
 }
 
 static int uinput_dev_erase_effect(struct input_dev *dev, int effect_id)
 {
 	struct uinput_request request;
+	int retval;
 
 	if (!test_bit(EV_FF, dev->evbit))
 		return -ENOSYS;
 
-	uinput_request_init(dev, &request, UI_FF_ERASE);
-	if (request.retval)
-		return request.retval;
+	request.id = -1;
+	init_completion(&request.done);
+	request.code = UI_FF_ERASE;
 	request.u.effect_id = effect_id;
-	uinput_request_submit(dev, &request);
-	return request.retval;
+
+	retval = uinput_request_reserve_slot(dev->private, &request);
+	if (!retval)
+		retval = uinput_request_submit(dev, &request);
+
+	return retval;
 }
 
 static int uinput_create_device(struct uinput_device *udev)
@@ -159,32 +159,30 @@ static int uinput_create_device(struct uinput_device *udev)
 		return -EINVAL;
 	}
 
-	udev->dev->open = uinput_dev_open;
-	udev->dev->close = uinput_dev_close;
 	udev->dev->event = uinput_dev_event;
 	udev->dev->upload_effect = uinput_dev_upload_effect;
 	udev->dev->erase_effect = uinput_dev_erase_effect;
 	udev->dev->private = udev;
 
-	init_waitqueue_head(&(udev->waitq));
+	init_waitqueue_head(&udev->waitq);
 
 	input_register_device(udev->dev);
 
-	set_bit(UIST_CREATED, &(udev->state));
+	set_bit(UIST_CREATED, &udev->state);
 
 	return 0;
 }
 
 static int uinput_destroy_device(struct uinput_device *udev)
 {
-	if (!test_bit(UIST_CREATED, &(udev->state))) {
+	if (!test_bit(UIST_CREATED, &udev->state)) {
 		printk(KERN_WARNING "%s: create the device first\n", UINPUT_NAME);
 		return -EINVAL;
 	}
 
 	input_unregister_device(udev->dev);
 
-	clear_bit(UIST_CREATED, &(udev->state));
+	clear_bit(UIST_CREATED, &udev->state);
 
 	return 0;
 }
@@ -198,7 +196,7 @@ static int uinput_open(struct inode *inode, struct file *file)
 	if (!newdev)
 		goto error;
 	memset(newdev, 0, sizeof(struct uinput_device));
-	init_MUTEX(&newdev->requests_sem);
+	spin_lock_init(&newdev->requests_lock);
 	init_waitqueue_head(&newdev->requests_waitq);
 
 	newinput = kmalloc(sizeof(struct input_dev), GFP_KERNEL);
@@ -253,15 +251,16 @@ static int uinput_alloc_device(struct file *file, const char __user *buffer, siz
 	struct uinput_user_dev	*user_dev;
 	struct input_dev	*dev;
 	struct uinput_device	*udev;
-	int			size,
-				retval;
+	char			*name;
+	int			size;
+	int			retval;
 
 	retval = count;
 
 	udev = file->private_data;
 	dev = udev->dev;
 
-	user_dev = kmalloc(sizeof(*user_dev), GFP_KERNEL);
+	user_dev = kmalloc(sizeof(struct uinput_user_dev), GFP_KERNEL);
 	if (!user_dev) {
 		retval = -ENOMEM;
 		goto exit;
@@ -272,17 +271,17 @@ static int uinput_alloc_device(struct file *file, const char __user *buffer, siz
 		goto exit;
 	}
 
-	if (NULL != dev->name)
+	if (dev->name)
 		kfree(dev->name);
 
 	size = strnlen(user_dev->name, UINPUT_MAX_NAME_SIZE) + 1;
-	dev->name = kmalloc(size, GFP_KERNEL);
-	if (!dev->name) {
+	dev->name = name = kmalloc(size, GFP_KERNEL);
+	if (!name) {
 		retval = -ENOMEM;
 		goto exit;
 	}
+	strlcpy(name, user_dev->name, size);
 
-	strlcpy(dev->name, user_dev->name, size);
 	dev->id.bustype	= user_dev->id.bustype;
 	dev->id.vendor	= user_dev->id.vendor;
 	dev->id.product	= user_dev->id.product;
@@ -314,14 +313,13 @@ static ssize_t uinput_write(struct file *file, const char __user *buffer, size_t
 {
 	struct uinput_device *udev = file->private_data;
 
-	if (test_bit(UIST_CREATED, &(udev->state))) {
+	if (test_bit(UIST_CREATED, &udev->state)) {
 		struct input_event	ev;
 
 		if (copy_from_user(&ev, buffer, sizeof(struct input_event)))
 			return -EFAULT;
 		input_event(udev->dev, ev.type, ev.code, ev.value);
-	}
-	else
+	} else
 		count = uinput_alloc_device(file, buffer, count);
 
 	return count;
@@ -332,26 +330,24 @@ static ssize_t uinput_read(struct file *file, char __user *buffer, size_t count,
 	struct uinput_device *udev = file->private_data;
 	int retval = 0;
 
-	if (!test_bit(UIST_CREATED, &(udev->state)))
+	if (!test_bit(UIST_CREATED, &udev->state))
 		return -ENODEV;
 
-	if ((udev->head == udev->tail) && (file->f_flags & O_NONBLOCK))
+	if (udev->head == udev->tail && (file->f_flags & O_NONBLOCK))
 		return -EAGAIN;
 
 	retval = wait_event_interruptible(udev->waitq,
-			(udev->head != udev->tail) ||
-			!test_bit(UIST_CREATED, &(udev->state)));
-
+			udev->head != udev->tail || !test_bit(UIST_CREATED, &udev->state));
 	if (retval)
 		return retval;
 
-	if (!test_bit(UIST_CREATED, &(udev->state)))
+	if (!test_bit(UIST_CREATED, &udev->state))
 		return -ENODEV;
 
 	while ((udev->head != udev->tail) &&
 	    (retval + sizeof(struct input_event) <= count)) {
-		if (copy_to_user(buffer + retval, &(udev->buff[udev->tail]),
-		    sizeof(struct input_event))) return -EFAULT;
+		if (copy_to_user(buffer + retval, &udev->buff[udev->tail], sizeof(struct input_event)))
+			return -EFAULT;
 		udev->tail = (udev->tail + 1) % UINPUT_BUFFER_SIZE;
 		retval += sizeof(struct input_event);
 	}
@@ -373,12 +369,12 @@ static unsigned int uinput_poll(struct file *file, poll_table *wait)
 
 static int uinput_burn_device(struct uinput_device *udev)
 {
-	if (test_bit(UIST_CREATED, &(udev->state)))
+	if (test_bit(UIST_CREATED, &udev->state))
 		uinput_destroy_device(udev);
 
-	if (NULL != udev->dev->name)
+	if (udev->dev->name)
 		kfree(udev->dev->name);
-	if (NULL != udev->dev->phys)
+	if (udev->dev->phys)
 		kfree(udev->dev->phys);
 
 	kfree(udev->dev);
@@ -389,7 +385,8 @@ static int uinput_burn_device(struct uinput_device *udev)
 
 static int uinput_close(struct inode *inode, struct file *file)
 {
-	return uinput_burn_device(file->private_data);
+	uinput_burn_device(file->private_data);
+	return 0;
 }
 
 static int uinput_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
@@ -401,6 +398,7 @@ static int uinput_ioctl(struct inode *inode, struct file *file, unsigned int cmd
 	struct uinput_ff_erase  ff_erase;
 	struct uinput_request   *req;
 	int                     length;
+	char			*phys;
 
 	udev = file->private_data;
 
@@ -415,7 +413,7 @@ static int uinput_ioctl(struct inode *inode, struct file *file, unsigned int cmd
 		case UI_SET_SNDBIT:
 		case UI_SET_FFBIT:
 		case UI_SET_PHYS:
-			if (test_bit(UIST_CREATED, &(udev->state)))
+			if (test_bit(UIST_CREATED, &udev->state))
 				return -EINVAL;
 	}
 
@@ -498,20 +496,19 @@ static int uinput_ioctl(struct inode *inode, struct file *file, unsigned int cmd
 				retval = -EFAULT;
 				break;
 			}
-			if (NULL != udev->dev->phys)
-				kfree(udev->dev->phys);
-			udev->dev->phys = kmalloc(length, GFP_KERNEL);
-			if (!udev->dev->phys) {
+			kfree(udev->dev->phys);
+			udev->dev->phys = phys = kmalloc(length, GFP_KERNEL);
+			if (!phys) {
 				retval = -ENOMEM;
 				break;
 			}
-			if (copy_from_user(udev->dev->phys, p, length)) {
-				retval = -EFAULT;
-				kfree(udev->dev->phys);
+			if (copy_from_user(phys, p, length)) {
 				udev->dev->phys = NULL;
+				kfree(phys);
+				retval = -EFAULT;
 				break;
 			}
-			udev->dev->phys[length-1] = '\0';
+			phys[length - 1] = '\0';
 			break;
 
 		case UI_BEGIN_FF_UPLOAD:
@@ -520,7 +517,7 @@ static int uinput_ioctl(struct inode *inode, struct file *file, unsigned int cmd
 				break;
 			}
 			req = uinput_request_find(udev, ff_up.request_id);
-			if (!(req && req->code==UI_FF_UPLOAD && req->u.effect)) {
+			if (!(req && req->code == UI_FF_UPLOAD && req->u.effect)) {
 				retval = -EINVAL;
 				break;
 			}
@@ -538,7 +535,7 @@ static int uinput_ioctl(struct inode *inode, struct file *file, unsigned int cmd
 				break;
 			}
 			req = uinput_request_find(udev, ff_erase.request_id);
-			if (!(req && req->code==UI_FF_ERASE)) {
+			if (!(req && req->code == UI_FF_ERASE)) {
 				retval = -EINVAL;
 				break;
 			}
@@ -556,14 +553,13 @@ static int uinput_ioctl(struct inode *inode, struct file *file, unsigned int cmd
 				break;
 			}
 			req = uinput_request_find(udev, ff_up.request_id);
-			if (!(req && req->code==UI_FF_UPLOAD && req->u.effect)) {
+			if (!(req && req->code == UI_FF_UPLOAD && req->u.effect)) {
 				retval = -EINVAL;
 				break;
 			}
 			req->retval = ff_up.retval;
 			memcpy(req->u.effect, &ff_up.effect, sizeof(struct ff_effect));
-			req->completed = 1;
-			wake_up_interruptible(&req->waitq);
+			uinput_request_done(udev, req);
 			break;
 
 		case UI_END_FF_ERASE:
@@ -572,13 +568,12 @@ static int uinput_ioctl(struct inode *inode, struct file *file, unsigned int cmd
 				break;
 			}
 			req = uinput_request_find(udev, ff_erase.request_id);
-			if (!(req && req->code==UI_FF_ERASE)) {
+			if (!(req && req->code == UI_FF_ERASE)) {
 				retval = -EINVAL;
 				break;
 			}
 			req->retval = ff_erase.retval;
-			req->completed = 1;
-			wake_up_interruptible(&req->waitq);
+			uinput_request_done(udev, req);
 			break;
 
 		default:
diff --git a/drivers/input/mouse/alps.c b/drivers/input/mouse/alps.c
index a12e98158a7..0d68e5e0182 100644
--- a/drivers/input/mouse/alps.c
+++ b/drivers/input/mouse/alps.c
@@ -2,7 +2,7 @@
  * ALPS touchpad PS/2 mouse driver
  *
  * Copyright (c) 2003 Neil Brown <neilb@cse.unsw.edu.au>
- * Copyright (c) 2003 Peter Osterlund <petero2@telia.com>
+ * Copyright (c) 2003-2005 Peter Osterlund <petero2@telia.com>
  * Copyright (c) 2004 Dmitry Torokhov <dtor@mail.ru>
  * Copyright (c) 2005 Vojtech Pavlik <vojtech@suse.cz>
  *
@@ -350,7 +350,6 @@ static int alps_tap_mode(struct psmouse *psmouse, int enable)
 static int alps_reconnect(struct psmouse *psmouse)
 {
 	struct alps_data *priv = psmouse->private;
-	unsigned char param[4];
 	int version;
 
 	psmouse_reset(psmouse);
@@ -358,21 +357,20 @@ static int alps_reconnect(struct psmouse *psmouse)
 	if (!(priv->i = alps_get_model(psmouse, &version)))
 		return -1;
 
-	if (priv->i->flags & ALPS_PASS && alps_passthrough_mode(psmouse, 1))
+	if ((priv->i->flags & ALPS_PASS) && alps_passthrough_mode(psmouse, 1))
 		return -1;
 
-	if (alps_get_status(psmouse, param))
+	if (alps_tap_mode(psmouse, 1)) {
+		printk(KERN_WARNING "alps.c: Failed to reenable hardware tapping\n");
 		return -1;
-
-	if (!(param[0] & 0x04))
-		alps_tap_mode(psmouse, 1);
+	}
 
 	if (alps_absolute_mode(psmouse)) {
-		printk(KERN_ERR "alps.c: Failed to enable absolute mode\n");
+		printk(KERN_ERR "alps.c: Failed to reenable absolute mode\n");
 		return -1;
 	}
 
-	if (priv->i->flags == ALPS_PASS && alps_passthrough_mode(psmouse, 0))
+	if ((priv->i->flags & ALPS_PASS) && alps_passthrough_mode(psmouse, 0))
 		return -1;
 
 	return 0;
@@ -389,7 +387,6 @@ static void alps_disconnect(struct psmouse *psmouse)
 int alps_init(struct psmouse *psmouse)
 {
 	struct alps_data *priv;
-	unsigned char param[4];
 	int version;
 
 	psmouse->private = priv = kmalloc(sizeof(struct alps_data), GFP_KERNEL);
@@ -403,16 +400,8 @@ int alps_init(struct psmouse *psmouse)
 	if ((priv->i->flags & ALPS_PASS) && alps_passthrough_mode(psmouse, 1))
 		goto init_fail;
 
-	if (alps_get_status(psmouse, param)) {
-		printk(KERN_ERR "alps.c: touchpad status report request failed\n");
-		goto init_fail;
-	}
-
-	if (param[0] & 0x04) {
-		printk(KERN_INFO "alps.c: Enabling hardware tapping\n");
-		if (alps_tap_mode(psmouse, 1))
-			printk(KERN_WARNING "alps.c: Failed to enable hardware tapping\n");
-	}
+	if (alps_tap_mode(psmouse, 1))
+		printk(KERN_WARNING "alps.c: Failed to enable hardware tapping\n");
 
 	if (alps_absolute_mode(psmouse)) {
 		printk(KERN_ERR "alps.c: Failed to enable absolute mode\n");
diff --git a/drivers/input/mouse/logips2pp.c b/drivers/input/mouse/logips2pp.c
index 5ab1bd7d529..48d2b20d264 100644
--- a/drivers/input/mouse/logips2pp.c
+++ b/drivers/input/mouse/logips2pp.c
@@ -385,8 +385,6 @@ int ps2pp_init(struct psmouse *psmouse, int set_properties)
 
 		if (buttons < 3)
 			clear_bit(BTN_MIDDLE, psmouse->dev.keybit);
-		if (buttons < 2)
-			clear_bit(BTN_RIGHT, psmouse->dev.keybit);
 
 		if (model_info)
 			ps2pp_set_model_properties(psmouse, model_info, use_ps2pp);
diff --git a/drivers/input/mouse/psmouse-base.c b/drivers/input/mouse/psmouse-base.c
index 19785a6c5ab..2bb2fe78bdc 100644
--- a/drivers/input/mouse/psmouse-base.c
+++ b/drivers/input/mouse/psmouse-base.c
@@ -344,6 +344,7 @@ static int intellimouse_detect(struct psmouse *psmouse, int set_properties)
 		return -1;
 
 	if (set_properties) {
+		set_bit(BTN_MIDDLE, psmouse->dev.keybit);
 		set_bit(REL_WHEEL, psmouse->dev.relbit);
 
 		if (!psmouse->vendor) psmouse->vendor = "Generic";
@@ -376,6 +377,7 @@ static int im_explorer_detect(struct psmouse *psmouse, int set_properties)
 		return -1;
 
 	if (set_properties) {
+		set_bit(BTN_MIDDLE, psmouse->dev.keybit);
 		set_bit(REL_WHEEL, psmouse->dev.relbit);
 		set_bit(BTN_SIDE, psmouse->dev.keybit);
 		set_bit(BTN_EXTRA, psmouse->dev.keybit);
diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c
index 36c721227b6..02930942240 100644
--- a/drivers/input/mouse/synaptics.c
+++ b/drivers/input/mouse/synaptics.c
@@ -219,7 +219,7 @@ static void synaptics_pass_pt_packet(struct serio *ptport, unsigned char *packet
 		serio_interrupt(ptport, packet[1], 0, NULL);
 		serio_interrupt(ptport, packet[4], 0, NULL);
 		serio_interrupt(ptport, packet[5], 0, NULL);
-		if (child->type >= PSMOUSE_GENPS)
+		if (child->pktsize == 4)
 			serio_interrupt(ptport, packet[2], 0, NULL);
 	} else
 		serio_interrupt(ptport, packet[1], 0, NULL);
@@ -233,7 +233,7 @@ static void synaptics_pt_activate(struct psmouse *psmouse)
 
 	/* adjust the touchpad to child's choice of protocol */
 	if (child) {
-		if (child->type >= PSMOUSE_GENPS)
+		if (child->pktsize == 4)
 			priv->mode |= SYN_BIT_FOUR_BYTE_CLIENT;
 		else
 			priv->mode &= ~SYN_BIT_FOUR_BYTE_CLIENT;
@@ -608,6 +608,13 @@ static struct dmi_system_id toshiba_dmi_table[] = {
 			DMI_MATCH(DMI_PRODUCT_NAME , "Satellite"),
 		},
 	},
+	{
+		.ident = "Toshiba Dynabook",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+			DMI_MATCH(DMI_PRODUCT_NAME , "dynabook"),
+		},
+	},
 	{ }
 };
 #endif
@@ -656,7 +663,8 @@ int synaptics_init(struct psmouse *psmouse)
 	 * thye same as rate of standard PS/2 mouse.
 	 */
 	if (psmouse->rate >= 80 && dmi_check_system(toshiba_dmi_table)) {
-		printk(KERN_INFO "synaptics: Toshiba Satellite detected, limiting rate to 40pps.\n");
+		printk(KERN_INFO "synaptics: Toshiba %s detected, limiting rate to 40pps.\n",
+			dmi_get_system_info(DMI_PRODUCT_NAME));
 		psmouse->rate = 40;
 	}
 #endif
diff --git a/drivers/input/serio/Kconfig b/drivers/input/serio/Kconfig
index b3710733b36..98acf170252 100644
--- a/drivers/input/serio/Kconfig
+++ b/drivers/input/serio/Kconfig
@@ -175,7 +175,7 @@ config SERIO_RAW
 	  allocating minor 1 (that historically corresponds to /dev/psaux)
 	  first. To bind this driver to a serio port use sysfs interface:
 
-	      echo -n "serio_raw" > /sys/bus/serio/devices/serioX/driver
+	      echo -n "serio_raw" > /sys/bus/serio/devices/serioX/drvctl
 
 	  To compile this driver as a module, choose M here: the
 	  module will be called serio_raw.
diff --git a/drivers/input/serio/i8042-x86ia64io.h b/drivers/input/serio/i8042-x86ia64io.h
index 0487ecbb8a4..03877c84e6f 100644
--- a/drivers/input/serio/i8042-x86ia64io.h
+++ b/drivers/input/serio/i8042-x86ia64io.h
@@ -131,12 +131,26 @@ static struct dmi_system_id __initdata i8042_dmi_nomux_table[] = {
 		},
 	},
 	{
+		.ident = "Fujitsu-Siemens Lifebook T3010",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU SIEMENS"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "LIFEBOOK T3010"),
+		},
+	},
+	{
 		.ident = "Toshiba P10",
 		.matches = {
 			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 			DMI_MATCH(DMI_PRODUCT_NAME, "Satellite P10"),
 		},
 	},
+	{
+		.ident = "Alienware Sentia",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "ALIENWARE"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "Sentia"),
+		},
+	},
 	{ }
 };
 
diff --git a/drivers/input/serio/i8042.c b/drivers/input/serio/i8042.c
index a9bf549c8dc..708a1d3beab 100644
--- a/drivers/input/serio/i8042.c
+++ b/drivers/input/serio/i8042.c
@@ -100,7 +100,7 @@ struct i8042_port {
 static struct i8042_port i8042_ports[I8042_NUM_PORTS] = {
 	{
 		.disable	= I8042_CTR_KBDDIS,
-		.irqen 		= I8042_CTR_KBDINT,
+		.irqen		= I8042_CTR_KBDINT,
 		.mux		= -1,
 		.name		= "KBD",
 	},
@@ -191,41 +191,45 @@ static int i8042_flush(void)
 static int i8042_command(unsigned char *param, int command)
 {
 	unsigned long flags;
-	int retval = 0, i = 0;
+	int i, retval, auxerr = 0;
 
 	if (i8042_noloop && command == I8042_CMD_AUX_LOOP)
 		return -1;
 
 	spin_lock_irqsave(&i8042_lock, flags);
 
-	retval = i8042_wait_write();
-	if (!retval) {
-		dbg("%02x -> i8042 (command)", command & 0xff);
-		i8042_write_command(command & 0xff);
+	if ((retval = i8042_wait_write()))
+		goto out;
+
+	dbg("%02x -> i8042 (command)", command & 0xff);
+	i8042_write_command(command & 0xff);
+
+	for (i = 0; i < ((command >> 12) & 0xf); i++) {
+		if ((retval = i8042_wait_write()))
+			goto out;
+		dbg("%02x -> i8042 (parameter)", param[i]);
+		i8042_write_data(param[i]);
 	}
 
-	if (!retval)
-		for (i = 0; i < ((command >> 12) & 0xf); i++) {
-			if ((retval = i8042_wait_write())) break;
-			dbg("%02x -> i8042 (parameter)", param[i]);
-			i8042_write_data(param[i]);
-		}
+	for (i = 0; i < ((command >> 8) & 0xf); i++) {
+		if ((retval = i8042_wait_read()))
+			goto out;
 
-	if (!retval)
-		for (i = 0; i < ((command >> 8) & 0xf); i++) {
-			if ((retval = i8042_wait_read())) break;
-			if (i8042_read_status() & I8042_STR_AUXDATA)
-				param[i] = ~i8042_read_data();
-			else
-				param[i] = i8042_read_data();
-			dbg("%02x <- i8042 (return)", param[i]);
+		if (command == I8042_CMD_AUX_LOOP &&
+		    !(i8042_read_status() & I8042_STR_AUXDATA)) {
+			retval = auxerr = -1;
+			goto out;
 		}
 
-	spin_unlock_irqrestore(&i8042_lock, flags);
+		param[i] = i8042_read_data();
+		dbg("%02x <- i8042 (return)", param[i]);
+	}
 
 	if (retval)
-		dbg("     -- i8042 (timeout)");
+		dbg("     -- i8042 (%s)", auxerr ? "auxerr" : "timeout");
 
+ out:
+	spin_unlock_irqrestore(&i8042_lock, flags);
 	return retval;
 }
 
@@ -507,17 +511,17 @@ static int i8042_set_mux_mode(unsigned int mode, unsigned char *mux_version)
  */
 
 	param = 0xf0;
-	if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param != 0x0f)
+	if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param != 0xf0)
 		return -1;
 	param = mode ? 0x56 : 0xf6;
-	if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param != (mode ? 0xa9 : 0x09))
+	if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param != (mode ? 0x56 : 0xf6))
 		return -1;
 	param = mode ? 0xa4 : 0xa5;
-	if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param == (mode ? 0x5b : 0x5a))
+	if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param == (mode ? 0xa4 : 0xa5))
 		return -1;
 
 	if (mux_version)
-		*mux_version = ~param;
+		*mux_version = param;
 
 	return 0;
 }
@@ -619,7 +623,7 @@ static int __init i8042_check_aux(void)
  */
 
 	param = 0x5a;
-	if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param != 0xa5) {
+	if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param != 0x5a) {
 
 /*
  * External connection test - filters out AT-soldered PS/2 i8042's
@@ -630,7 +634,7 @@ static int __init i8042_check_aux(void)
  */
 
 		if (i8042_command(&param, I8042_CMD_AUX_TEST)
-		    	|| (param && param != 0xfa && param != 0xff))
+			|| (param && param != 0xfa && param != 0xff))
 				return -1;
 	}
 
diff --git a/drivers/input/serio/serio.c b/drivers/input/serio/serio.c
index f367695e69b..edd15db1771 100644
--- a/drivers/input/serio/serio.c
+++ b/drivers/input/serio/serio.c
@@ -389,6 +389,14 @@ static ssize_t serio_show_description(struct device *dev, struct device_attribut
 	return sprintf(buf, "%s\n", serio->name);
 }
 
+static ssize_t serio_show_modalias(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct serio *serio = to_serio_port(dev);
+
+	return sprintf(buf, "serio:ty%02Xpr%02Xid%02Xex%02X\n",
+			serio->id.type, serio->id.proto, serio->id.id, serio->id.extra);
+}
+
 static ssize_t serio_show_id_type(struct device *dev, struct device_attribute *attr, char *buf)
 {
 	struct serio *serio = to_serio_port(dev);
@@ -487,6 +495,7 @@ static ssize_t serio_set_bind_mode(struct device *dev, struct device_attribute *
 
 static struct device_attribute serio_device_attrs[] = {
 	__ATTR(description, S_IRUGO, serio_show_description, NULL),
+	__ATTR(modalias, S_IRUGO, serio_show_modalias, NULL),
 	__ATTR(drvctl, S_IWUSR, NULL, serio_rebind_driver),
 	__ATTR(bind_mode, S_IWUSR | S_IRUGO, serio_show_bind_mode, serio_set_bind_mode),
 	__ATTR_NULL
@@ -785,36 +794,37 @@ static int serio_bus_match(struct device *dev, struct device_driver *drv)
 
 #ifdef CONFIG_HOTPLUG
 
-#define PUT_ENVP(fmt, val) 						\
-do {									\
-	envp[i++] = buffer;						\
-	length += snprintf(buffer, buffer_size - length, fmt, val);	\
-	if (buffer_size - length <= 0 || i >= num_envp)			\
-		return -ENOMEM;						\
-	length++;							\
-	buffer += length;						\
-} while (0)
+#define SERIO_ADD_HOTPLUG_VAR(fmt, val...)				\
+	do {								\
+		int err = add_hotplug_env_var(envp, num_envp, &i,	\
+					buffer, buffer_size, &len,	\
+					fmt, val);			\
+		if (err)						\
+			return err;					\
+	} while (0)
+
 static int serio_hotplug(struct device *dev, char **envp, int num_envp, char *buffer, int buffer_size)
 {
 	struct serio *serio;
 	int i = 0;
-	int length = 0;
+	int len = 0;
 
 	if (!dev)
 		return -ENODEV;
 
 	serio = to_serio_port(dev);
 
-	PUT_ENVP("SERIO_TYPE=%02x", serio->id.type);
-	PUT_ENVP("SERIO_PROTO=%02x", serio->id.proto);
-	PUT_ENVP("SERIO_ID=%02x", serio->id.id);
-	PUT_ENVP("SERIO_EXTRA=%02x", serio->id.extra);
-
+	SERIO_ADD_HOTPLUG_VAR("SERIO_TYPE=%02x", serio->id.type);
+	SERIO_ADD_HOTPLUG_VAR("SERIO_PROTO=%02x", serio->id.proto);
+	SERIO_ADD_HOTPLUG_VAR("SERIO_ID=%02x", serio->id.id);
+	SERIO_ADD_HOTPLUG_VAR("SERIO_EXTRA=%02x", serio->id.extra);
+	SERIO_ADD_HOTPLUG_VAR("MODALIAS=serio:ty%02Xpr%02Xid%02Xex%02X",
+				serio->id.type, serio->id.proto, serio->id.id, serio->id.extra);
 	envp[i] = NULL;
 
 	return 0;
 }
-#undef PUT_ENVP
+#undef SERIO_ADD_HOTPLUG_VAR
 
 #else
 
diff --git a/drivers/input/serio/serio_raw.c b/drivers/input/serio/serio_raw.c
index d914e7e93db..47e08de18d0 100644
--- a/drivers/input/serio/serio_raw.c
+++ b/drivers/input/serio/serio_raw.c
@@ -299,6 +299,7 @@ static int serio_raw_connect(struct serio *serio, struct serio_driver *drv)
 
 	serio_raw->dev.minor = PSMOUSE_MINOR;
 	serio_raw->dev.name = serio_raw->name;
+	serio_raw->dev.dev = &serio->dev;
 	serio_raw->dev.fops = &serio_raw_fops;
 
 	err = misc_register(&serio_raw->dev);
diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
index 7e991274ea4..0489af5a80c 100644
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -58,7 +58,7 @@ config TOUCHSCREEN_ELO
 	  If unsure, say N.
 
 	  To compile this driver as a module, choose M here: the
-	  module will be called gunze.
+	  module will be called elo.
 
 config TOUCHSCREEN_MTOUCH
 	tristate "MicroTouch serial touchscreens"
diff --git a/drivers/isdn/hisax/avm_a1.c b/drivers/isdn/hisax/avm_a1.c
index 8f028d42fd2..9a8b02557ff 100644
--- a/drivers/isdn/hisax/avm_a1.c
+++ b/drivers/isdn/hisax/avm_a1.c
@@ -135,7 +135,7 @@ avm_a1_interrupt(int intno, void *dev_id, struct pt_regs *regs)
 	return IRQ_HANDLED;
 }
 
-inline static void
+static inline void
 release_ioregs(struct IsdnCardState *cs, int mask)
 {
 	release_region(cs->hw.avm.cfg_reg, 8);
diff --git a/drivers/isdn/hisax/config.c b/drivers/isdn/hisax/config.c
index c542e6fb2bd..fbaab435290 100644
--- a/drivers/isdn/hisax/config.c
+++ b/drivers/isdn/hisax/config.c
@@ -1900,6 +1900,7 @@ static struct pci_device_id hisax_pci_tbl[] __initdata = {
 	{PCI_VENDOR_ID_PLX,      PCI_DEVICE_ID_PLX_R685,         PCI_ANY_ID, PCI_ANY_ID},
 	{PCI_VENDOR_ID_PLX,      PCI_DEVICE_ID_PLX_R753,         PCI_ANY_ID, PCI_ANY_ID},
 	{PCI_VENDOR_ID_PLX,      PCI_DEVICE_ID_PLX_DJINN_ITOO,   PCI_ANY_ID, PCI_ANY_ID},
+	{PCI_VENDOR_ID_PLX,      PCI_DEVICE_ID_PLX_OLITEC,       PCI_ANY_ID, PCI_ANY_ID},
 #endif
 #ifdef CONFIG_HISAX_QUADRO
 	{PCI_VENDOR_ID_PLX,      PCI_DEVICE_ID_PLX_9050,         PCI_ANY_ID, PCI_ANY_ID},
diff --git a/drivers/isdn/hisax/gazel.c b/drivers/isdn/hisax/gazel.c
index 352b45ac534..60b04c6d9e7 100644
--- a/drivers/isdn/hisax/gazel.c
+++ b/drivers/isdn/hisax/gazel.c
@@ -546,8 +546,9 @@ setup_gazelpci(struct IsdnCardState *cs)
 
 	found = 0;
 	seekcard = PCI_DEVICE_ID_PLX_R685;
-	for (nbseek = 0; nbseek < 3; nbseek++) {
-		if ((dev_tel = pci_find_device(PCI_VENDOR_ID_PLX, seekcard, dev_tel))) {
+	for (nbseek = 0; nbseek < 4; nbseek++) {
+		if ((dev_tel = pci_find_device(PCI_VENDOR_ID_PLX,
+					seekcard, dev_tel))) {
 			if (pci_enable_device(dev_tel))
 				return 1;
 			pci_irq = dev_tel->irq;
@@ -565,6 +566,9 @@ setup_gazelpci(struct IsdnCardState *cs)
 				case PCI_DEVICE_ID_PLX_R753:
 					seekcard = PCI_DEVICE_ID_PLX_DJINN_ITOO;
 					break;
+				case PCI_DEVICE_ID_PLX_DJINN_ITOO:
+					seekcard = PCI_DEVICE_ID_PLX_OLITEC;
+					break;
 			}
 		}
 	}
@@ -605,6 +609,7 @@ setup_gazelpci(struct IsdnCardState *cs)
 			break;
 		case PCI_DEVICE_ID_PLX_R753:
 		case PCI_DEVICE_ID_PLX_DJINN_ITOO:
+		case PCI_DEVICE_ID_PLX_OLITEC:
 			printk(KERN_INFO "Gazel: Card PCI R753 found\n");
 			cs->subtyp = R753;
 			test_and_set_bit(HW_IPAC, &cs->HW_Flags);
diff --git a/drivers/isdn/hisax/isdnl2.c b/drivers/isdn/hisax/isdnl2.c
index 1615c1a76ab..6d043172555 100644
--- a/drivers/isdn/hisax/isdnl2.c
+++ b/drivers/isdn/hisax/isdnl2.c
@@ -213,7 +213,7 @@ sethdraddr(struct Layer2 *l2, u_char * header, int rsp)
 	}
 }
 
-inline static void
+static inline void
 enqueue_super(struct PStack *st,
 	      struct sk_buff *skb)
 {
diff --git a/drivers/isdn/hisax/l3dss1.c b/drivers/isdn/hisax/l3dss1.c
index a6d2abdb478..e96845cdd4f 100644
--- a/drivers/isdn/hisax/l3dss1.c
+++ b/drivers/isdn/hisax/l3dss1.c
@@ -353,7 +353,7 @@ l3dss1_parse_facility(struct PStack *st, struct l3_process *pc,
 			         { l3dss1_dummy_invoke(st, cr, id, ident, p, nlen);
                                    return;
                                  } 
-#if HISAX_DE_AOC
+#ifdef HISAX_DE_AOC
 			{
 
 #define FOO1(s,a,b) \
@@ -977,7 +977,7 @@ l3dss1_release_cmpl(struct l3_process *pc, u_char pr, void *arg)
 	dss1_release_l3_process(pc);
 }
 
-#if EXT_BEARER_CAPS
+#ifdef EXT_BEARER_CAPS
 
 static u_char *
 EncodeASyncParams(u_char * p, u_char si2)
@@ -1369,7 +1369,7 @@ l3dss1_setup_req(struct l3_process *pc, u_char pr,
 				*p++ = *sub++ & 0x7f;
 		}
         }
-#if EXT_BEARER_CAPS
+#ifdef EXT_BEARER_CAPS
 	if ((pc->para.setup.si2 >= 160) && (pc->para.setup.si2 <= 175)) {	// sync. Bitratenadaption, V.110/X.30
 
 		*p++ = IE_LLC;
@@ -1609,7 +1609,7 @@ l3dss1_setup(struct l3_process *pc, u_char pr, void *arg)
 				case 0x08: /* Unrestricted digital information */
 					pc->para.setup.si1 = 7;
 /* JIM, 05.11.97 I wanna set service indicator 2 */
-#if EXT_BEARER_CAPS
+#ifdef EXT_BEARER_CAPS
 					pc->para.setup.si2 = DecodeSI2(skb);
 #endif
 					break;
diff --git a/drivers/isdn/hisax/teles3.c b/drivers/isdn/hisax/teles3.c
index adeaad62d35..a3eaf4d6570 100644
--- a/drivers/isdn/hisax/teles3.c
+++ b/drivers/isdn/hisax/teles3.c
@@ -143,7 +143,7 @@ teles3_interrupt(int intno, void *dev_id, struct pt_regs *regs)
 	return IRQ_HANDLED;
 }
 
-inline static void
+static inline void
 release_ioregs(struct IsdnCardState *cs, int mask)
 {
 	if (mask & 1)
diff --git a/drivers/isdn/icn/icn.c b/drivers/isdn/icn/icn.c
index e0d1b01cc74..386df71eee7 100644
--- a/drivers/isdn/icn/icn.c
+++ b/drivers/isdn/icn/icn.c
@@ -1650,7 +1650,7 @@ static void __exit icn_exit(void)
 {
 	isdn_ctrl cmd;
 	icn_card *card = cards;
-	icn_card *last;
+	icn_card *last, *tmpcard;
 	int i;
 	unsigned long flags;
 
@@ -1670,8 +1670,9 @@ static void __exit icn_exit(void)
 			for (i = 0; i < ICN_BCH; i++)
 				icn_free_queue(card, i);
 		}
-		card = card->next;
+		tmpcard = card->next;
 		spin_unlock_irqrestore(&card->lock, flags);
+		card = tmpcard;
 	}
 	card = cards;
 	cards = NULL;
diff --git a/drivers/macintosh/Kconfig b/drivers/macintosh/Kconfig
index 91691a6c004..65ab64c43b3 100644
--- a/drivers/macintosh/Kconfig
+++ b/drivers/macintosh/Kconfig
@@ -4,7 +4,7 @@ menu "Macintosh device drivers"
 
 config ADB
 	bool "Apple Desktop Bus (ADB) support"
-	depends on MAC || PPC_PMAC
+	depends on MAC || (PPC_PMAC && PPC32)
 	help
 	  Apple Desktop Bus (ADB) support is for support of devices which
 	  are connected to an ADB port.  ADB devices tend to have 4 pins.
diff --git a/drivers/md/bitmap.c b/drivers/md/bitmap.c
index 0c2ed99a383..41df4cda66e 100644
--- a/drivers/md/bitmap.c
+++ b/drivers/md/bitmap.c
@@ -108,7 +108,7 @@ static unsigned char *bitmap_alloc_page(struct bitmap *bitmap)
 {
 	unsigned char *page;
 
-#if INJECT_FAULTS_1
+#ifdef INJECT_FAULTS_1
 	page = NULL;
 #else
 	page = kmalloc(PAGE_SIZE, GFP_NOIO);
@@ -818,8 +818,7 @@ int bitmap_unplug(struct bitmap *bitmap)
 	return 0;
 }
 
-static void bitmap_set_memory_bits(struct bitmap *bitmap, sector_t offset,
-	unsigned long sectors, int in_sync);
+static void bitmap_set_memory_bits(struct bitmap *bitmap, sector_t offset);
 /* * bitmap_init_from_disk -- called at bitmap_create time to initialize
  * the in-memory bitmap from the on-disk bitmap -- also, sets up the
  * memory mapping of the bitmap file
@@ -828,7 +827,7 @@ static void bitmap_set_memory_bits(struct bitmap *bitmap, sector_t offset,
  *   previously kicked from the array, we mark all the bits as
  *   1's in order to cause a full resync.
  */
-static int bitmap_init_from_disk(struct bitmap *bitmap, int in_sync)
+static int bitmap_init_from_disk(struct bitmap *bitmap)
 {
 	unsigned long i, chunks, index, oldindex, bit;
 	struct page *page = NULL, *oldpage = NULL;
@@ -843,7 +842,7 @@ static int bitmap_init_from_disk(struct bitmap *bitmap, int in_sync)
 
 	BUG_ON(!file && !bitmap->offset);
 
-#if INJECT_FAULTS_3
+#ifdef INJECT_FAULTS_3
 	outofdate = 1;
 #else
 	outofdate = bitmap->flags & BITMAP_STALE;
@@ -929,8 +928,7 @@ static int bitmap_init_from_disk(struct bitmap *bitmap, int in_sync)
 		}
 		if (test_bit(bit, page_address(page))) {
 			/* if the disk bit is set, set the memory bit */
-			bitmap_set_memory_bits(bitmap,
-					i << CHUNK_BLOCK_SHIFT(bitmap), 1, in_sync);
+			bitmap_set_memory_bits(bitmap, i << CHUNK_BLOCK_SHIFT(bitmap));
 			bit_cnt++;
 		}
 	}
@@ -1187,7 +1185,7 @@ static int bitmap_start_daemon(struct bitmap *bitmap, mdk_thread_t **ptr,
 
 	spin_unlock_irqrestore(&bitmap->lock, flags);
 
-#if INJECT_FATAL_FAULT_2
+#ifdef INJECT_FATAL_FAULT_2
 	daemon = NULL;
 #else
 	sprintf(namebuf, "%%s_%s", name);
@@ -1426,35 +1424,53 @@ void bitmap_close_sync(struct bitmap *bitmap)
 	}
 }
 
-static void bitmap_set_memory_bits(struct bitmap *bitmap, sector_t offset,
-				   unsigned long sectors, int in_sync)
+static void bitmap_set_memory_bits(struct bitmap *bitmap, sector_t offset)
 {
 	/* For each chunk covered by any of these sectors, set the
-	 * counter to 1 and set resync_needed unless in_sync.  They should all
+	 * counter to 1 and set resync_needed.  They should all
 	 * be 0 at this point
 	 */
-	while (sectors) {
-		int secs;
-		bitmap_counter_t *bmc;
-		spin_lock_irq(&bitmap->lock);
-		bmc = bitmap_get_counter(bitmap, offset, &secs, 1);
-		if (!bmc) {
-			spin_unlock_irq(&bitmap->lock);
-			return;
-		}
-		if (! *bmc) {
-			struct page *page;
-			*bmc = 1 | (in_sync? 0 : NEEDED_MASK);
-			bitmap_count_page(bitmap, offset, 1);
-			page = filemap_get_page(bitmap, offset >> CHUNK_BLOCK_SHIFT(bitmap));
-			set_page_attr(bitmap, page, BITMAP_PAGE_CLEAN);
-		}
+
+	int secs;
+	bitmap_counter_t *bmc;
+	spin_lock_irq(&bitmap->lock);
+	bmc = bitmap_get_counter(bitmap, offset, &secs, 1);
+	if (!bmc) {
 		spin_unlock_irq(&bitmap->lock);
-		if (sectors > secs)
-			sectors -= secs;
-		else
-			sectors = 0;
+		return;
+	}
+	if (! *bmc) {
+		struct page *page;
+		*bmc = 1 | NEEDED_MASK;
+		bitmap_count_page(bitmap, offset, 1);
+		page = filemap_get_page(bitmap, offset >> CHUNK_BLOCK_SHIFT(bitmap));
+		set_page_attr(bitmap, page, BITMAP_PAGE_CLEAN);
 	}
+	spin_unlock_irq(&bitmap->lock);
+
+}
+
+/*
+ * flush out any pending updates
+ */
+void bitmap_flush(mddev_t *mddev)
+{
+	struct bitmap *bitmap = mddev->bitmap;
+	int sleep;
+
+	if (!bitmap) /* there was no bitmap */
+		return;
+
+	/* run the daemon_work three time to ensure everything is flushed
+	 * that can be
+	 */
+	sleep = bitmap->daemon_sleep;
+	bitmap->daemon_sleep = 0;
+	bitmap_daemon_work(bitmap);
+	bitmap_daemon_work(bitmap);
+	bitmap_daemon_work(bitmap);
+	bitmap->daemon_sleep = sleep;
+	bitmap_update_sb(bitmap);
 }
 
 /*
@@ -1552,7 +1568,7 @@ int bitmap_create(mddev_t *mddev)
 
 	bitmap->syncchunk = ~0UL;
 
-#if INJECT_FATAL_FAULT_1
+#ifdef INJECT_FATAL_FAULT_1
 	bitmap->bp = NULL;
 #else
 	bitmap->bp = kmalloc(pages * sizeof(*bitmap->bp), GFP_KERNEL);
@@ -1565,7 +1581,8 @@ int bitmap_create(mddev_t *mddev)
 
 	/* now that we have some pages available, initialize the in-memory
 	 * bitmap from the on-disk bitmap */
-	err = bitmap_init_from_disk(bitmap, mddev->recovery_cp == MaxSector);
+	err = bitmap_init_from_disk(bitmap);
+
 	if (err)
 		return err;
 
diff --git a/drivers/md/dm-raid1.c b/drivers/md/dm-raid1.c
index 12031c9d3f1..b08df8b9b2c 100644
--- a/drivers/md/dm-raid1.c
+++ b/drivers/md/dm-raid1.c
@@ -1230,7 +1230,7 @@ static int __init dm_mirror_init(void)
 	if (r)
 		return r;
 
-	_kmirrord_wq = create_workqueue("kmirrord");
+	_kmirrord_wq = create_singlethread_workqueue("kmirrord");
 	if (!_kmirrord_wq) {
 		DMERR("couldn't start kmirrord");
 		dm_dirty_log_exit();
diff --git a/drivers/md/dm-table.c b/drivers/md/dm-table.c
index a5a4c0ed8a1..a6d3baa46f6 100644
--- a/drivers/md/dm-table.c
+++ b/drivers/md/dm-table.c
@@ -869,11 +869,17 @@ static void suspend_targets(struct dm_table *t, unsigned postsuspend)
 
 void dm_table_presuspend_targets(struct dm_table *t)
 {
+	if (!t)
+		return;
+
 	return suspend_targets(t, 0);
 }
 
 void dm_table_postsuspend_targets(struct dm_table *t)
 {
+	if (!t)
+		return;
+
 	return suspend_targets(t, 1);
 }
 
diff --git a/drivers/md/dm.c b/drivers/md/dm.c
index 54fabbf0667..d487d9deb98 100644
--- a/drivers/md/dm.c
+++ b/drivers/md/dm.c
@@ -55,10 +55,10 @@ union map_info *dm_get_mapinfo(struct bio *bio)
  */
 #define DMF_BLOCK_IO 0
 #define DMF_SUSPENDED 1
-#define DMF_FS_LOCKED 2
 
 struct mapped_device {
-	struct rw_semaphore lock;
+	struct rw_semaphore io_lock;
+	struct semaphore suspend_lock;
 	rwlock_t map_lock;
 	atomic_t holders;
 
@@ -248,16 +248,16 @@ static inline void free_tio(struct mapped_device *md, struct target_io *tio)
  */
 static int queue_io(struct mapped_device *md, struct bio *bio)
 {
-	down_write(&md->lock);
+	down_write(&md->io_lock);
 
 	if (!test_bit(DMF_BLOCK_IO, &md->flags)) {
-		up_write(&md->lock);
+		up_write(&md->io_lock);
 		return 1;
 	}
 
 	bio_list_add(&md->deferred, bio);
 
-	up_write(&md->lock);
+	up_write(&md->io_lock);
 	return 0;		/* deferred successfully */
 }
 
@@ -568,14 +568,14 @@ static int dm_request(request_queue_t *q, struct bio *bio)
 	int r;
 	struct mapped_device *md = q->queuedata;
 
-	down_read(&md->lock);
+	down_read(&md->io_lock);
 
 	/*
 	 * If we're suspended we have to queue
 	 * this io for later.
 	 */
 	while (test_bit(DMF_BLOCK_IO, &md->flags)) {
-		up_read(&md->lock);
+		up_read(&md->io_lock);
 
 		if (bio_rw(bio) == READA) {
 			bio_io_error(bio, bio->bi_size);
@@ -594,11 +594,11 @@ static int dm_request(request_queue_t *q, struct bio *bio)
 		 * We're in a while loop, because someone could suspend
 		 * before we get to the following read lock.
 		 */
-		down_read(&md->lock);
+		down_read(&md->io_lock);
 	}
 
 	__split_bio(md, bio);
-	up_read(&md->lock);
+	up_read(&md->io_lock);
 	return 0;
 }
 
@@ -610,7 +610,7 @@ static int dm_flush_all(request_queue_t *q, struct gendisk *disk,
 	int ret = -ENXIO;
 
 	if (map) {
-		ret = dm_table_flush_all(md->map);
+		ret = dm_table_flush_all(map);
 		dm_table_put(map);
 	}
 
@@ -747,7 +747,8 @@ static struct mapped_device *alloc_dev(unsigned int minor, int persistent)
 		goto bad1;
 
 	memset(md, 0, sizeof(*md));
-	init_rwsem(&md->lock);
+	init_rwsem(&md->io_lock);
+	init_MUTEX(&md->suspend_lock);
 	rwlock_init(&md->map_lock);
 	atomic_set(&md->holders, 1);
 	atomic_set(&md->event_nr, 0);
@@ -825,18 +826,13 @@ static void event_callback(void *context)
 	wake_up(&md->eventq);
 }
 
-static void __set_size(struct gendisk *disk, sector_t size)
+static void __set_size(struct mapped_device *md, sector_t size)
 {
-	struct block_device *bdev;
-
-	set_capacity(disk, size);
-	bdev = bdget_disk(disk, 0);
-	if (bdev) {
-		down(&bdev->bd_inode->i_sem);
-		i_size_write(bdev->bd_inode, (loff_t)size << SECTOR_SHIFT);
-		up(&bdev->bd_inode->i_sem);
-		bdput(bdev);
-	}
+	set_capacity(md->disk, size);
+
+	down(&md->frozen_bdev->bd_inode->i_sem);
+	i_size_write(md->frozen_bdev->bd_inode, (loff_t)size << SECTOR_SHIFT);
+	up(&md->frozen_bdev->bd_inode->i_sem);
 }
 
 static int __bind(struct mapped_device *md, struct dm_table *t)
@@ -845,17 +841,18 @@ static int __bind(struct mapped_device *md, struct dm_table *t)
 	sector_t size;
 
 	size = dm_table_get_size(t);
-	__set_size(md->disk, size);
+	__set_size(md, size);
 	if (size == 0)
 		return 0;
 
+	dm_table_get(t);
+	dm_table_event_callback(t, event_callback, md);
+
 	write_lock(&md->map_lock);
 	md->map = t;
+	dm_table_set_restrictions(t, q);
 	write_unlock(&md->map_lock);
 
-	dm_table_get(t);
-	dm_table_event_callback(md->map, event_callback, md);
-	dm_table_set_restrictions(t, q);
 	return 0;
 }
 
@@ -935,7 +932,7 @@ void dm_put(struct mapped_device *md)
 	struct dm_table *map = dm_get_table(md);
 
 	if (atomic_dec_and_test(&md->holders)) {
-		if (!test_bit(DMF_SUSPENDED, &md->flags) && map) {
+		if (!dm_suspended(md)) {
 			dm_table_presuspend_targets(map);
 			dm_table_postsuspend_targets(map);
 		}
@@ -968,17 +965,17 @@ int dm_swap_table(struct mapped_device *md, struct dm_table *table)
 {
 	int r = -EINVAL;
 
-	down_write(&md->lock);
+	down(&md->suspend_lock);
 
 	/* device must be suspended */
-	if (!test_bit(DMF_SUSPENDED, &md->flags))
+	if (!dm_suspended(md))
 		goto out;
 
 	__unbind(md);
 	r = __bind(md, table);
 
 out:
-	up_write(&md->lock);
+	up(&md->suspend_lock);
 	return r;
 }
 
@@ -986,16 +983,13 @@ out:
  * Functions to lock and unlock any filesystem running on the
  * device.
  */
-static int __lock_fs(struct mapped_device *md)
+static int lock_fs(struct mapped_device *md)
 {
-	int error = -ENOMEM;
-
-	if (test_and_set_bit(DMF_FS_LOCKED, &md->flags))
-		return 0;
+	int r = -ENOMEM;
 
 	md->frozen_bdev = bdget_disk(md->disk, 0);
 	if (!md->frozen_bdev) {
-		DMWARN("bdget failed in __lock_fs");
+		DMWARN("bdget failed in lock_fs");
 		goto out;
 	}
 
@@ -1003,13 +997,13 @@ static int __lock_fs(struct mapped_device *md)
 
 	md->frozen_sb = freeze_bdev(md->frozen_bdev);
 	if (IS_ERR(md->frozen_sb)) {
-		error = PTR_ERR(md->frozen_sb);
+		r = PTR_ERR(md->frozen_sb);
 		goto out_bdput;
 	}
 
 	/* don't bdput right now, we don't want the bdev
 	 * to go away while it is locked.  We'll bdput
-	 * in __unlock_fs
+	 * in unlock_fs
 	 */
 	return 0;
 
@@ -1018,15 +1012,11 @@ out_bdput:
 	md->frozen_sb = NULL;
 	md->frozen_bdev = NULL;
 out:
-	clear_bit(DMF_FS_LOCKED, &md->flags);
-	return error;
+	return r;
 }
 
-static void __unlock_fs(struct mapped_device *md)
+static void unlock_fs(struct mapped_device *md)
 {
-	if (!test_and_clear_bit(DMF_FS_LOCKED, &md->flags))
-		return;
-
 	thaw_bdev(md->frozen_bdev, md->frozen_sb);
 	bdput(md->frozen_bdev);
 
@@ -1043,50 +1033,37 @@ static void __unlock_fs(struct mapped_device *md)
  */
 int dm_suspend(struct mapped_device *md)
 {
-	struct dm_table *map;
+	struct dm_table *map = NULL;
 	DECLARE_WAITQUEUE(wait, current);
-	int error = -EINVAL;
+	int r = -EINVAL;
 
-	/* Flush I/O to the device. */
-	down_read(&md->lock);
-	if (test_bit(DMF_BLOCK_IO, &md->flags))
-		goto out_read_unlock;
+	down(&md->suspend_lock);
+
+	if (dm_suspended(md))
+		goto out;
 
 	map = dm_get_table(md);
-	if (map)
-		/* This does not get reverted if there's an error later. */
-		dm_table_presuspend_targets(map);
 
-	error = __lock_fs(md);
-	if (error) {
-		dm_table_put(map);
-		goto out_read_unlock;
-	}
+	/* This does not get reverted if there's an error later. */
+	dm_table_presuspend_targets(map);
 
-	up_read(&md->lock);
+	/* Flush I/O to the device. */
+	r = lock_fs(md);
+	if (r)
+		goto out;
 
 	/*
 	 * First we set the BLOCK_IO flag so no more ios will be mapped.
-	 *
-	 * If the flag is already set we know another thread is trying to
-	 * suspend as well, so we leave the fs locked for this thread.
 	 */
-	error = -EINVAL;
-	down_write(&md->lock);
-	if (test_and_set_bit(DMF_BLOCK_IO, &md->flags)) {
-		if (map)
-			dm_table_put(map);
-		goto out_write_unlock;
-	}
+	down_write(&md->io_lock);
+	set_bit(DMF_BLOCK_IO, &md->flags);
 
 	add_wait_queue(&md->wait, &wait);
-	up_write(&md->lock);
+	up_write(&md->io_lock);
 
 	/* unplug */
-	if (map) {
+	if (map)
 		dm_table_unplug_all(map);
-		dm_table_put(map);
-	}
 
 	/*
 	 * Then we wait for the already mapped ios to
@@ -1102,62 +1079,67 @@ int dm_suspend(struct mapped_device *md)
 	}
 	set_current_state(TASK_RUNNING);
 
-	down_write(&md->lock);
+	down_write(&md->io_lock);
 	remove_wait_queue(&md->wait, &wait);
 
 	/* were we interrupted ? */
-	error = -EINTR;
-	if (atomic_read(&md->pending))
-		goto out_unfreeze;
-
-	set_bit(DMF_SUSPENDED, &md->flags);
+	r = -EINTR;
+	if (atomic_read(&md->pending)) {
+		up_write(&md->io_lock);
+		unlock_fs(md);
+		clear_bit(DMF_BLOCK_IO, &md->flags);
+		goto out;
+	}
+	up_write(&md->io_lock);
 
-	map = dm_get_table(md);
-	if (map)
-		dm_table_postsuspend_targets(map);
-	dm_table_put(map);
-	up_write(&md->lock);
+	dm_table_postsuspend_targets(map);
 
-	return 0;
+	set_bit(DMF_SUSPENDED, &md->flags);
 
-out_unfreeze:
-	__unlock_fs(md);
-	clear_bit(DMF_BLOCK_IO, &md->flags);
-out_write_unlock:
-	up_write(&md->lock);
-	return error;
+	r = 0;
 
-out_read_unlock:
-	up_read(&md->lock);
-	return error;
+out:
+	dm_table_put(map);
+	up(&md->suspend_lock);
+	return r;
 }
 
 int dm_resume(struct mapped_device *md)
 {
+	int r = -EINVAL;
 	struct bio *def;
-	struct dm_table *map = dm_get_table(md);
+	struct dm_table *map = NULL;
 
-	down_write(&md->lock);
-	if (!map ||
-	    !test_bit(DMF_SUSPENDED, &md->flags) ||
-	    !dm_table_get_size(map)) {
-		up_write(&md->lock);
-		dm_table_put(map);
-		return -EINVAL;
-	}
+	down(&md->suspend_lock);
+	if (!dm_suspended(md))
+		goto out;
+
+	map = dm_get_table(md);
+	if (!map || !dm_table_get_size(map))
+		goto out;
 
 	dm_table_resume_targets(map);
-	clear_bit(DMF_SUSPENDED, &md->flags);
+
+	down_write(&md->io_lock);
 	clear_bit(DMF_BLOCK_IO, &md->flags);
 
 	def = bio_list_get(&md->deferred);
 	__flush_deferred_io(md, def);
-	up_write(&md->lock);
-	__unlock_fs(md);
+	up_write(&md->io_lock);
+
+	unlock_fs(md);
+
+	clear_bit(DMF_SUSPENDED, &md->flags);
+
 	dm_table_unplug_all(map);
+
+	r = 0;
+
+out:
 	dm_table_put(map);
+	up(&md->suspend_lock);
 
-	return 0;
+	return r;
 }
 
 /*-----------------------------------------------------------------
diff --git a/drivers/md/md.c b/drivers/md/md.c
index 4a0c57db2b6..480f658db6f 100644
--- a/drivers/md/md.c
+++ b/drivers/md/md.c
@@ -284,7 +284,7 @@ static mdk_rdev_t * find_rdev(mddev_t * mddev, dev_t dev)
 	return NULL;
 }
 
-inline static sector_t calc_dev_sboffset(struct block_device *bdev)
+static inline sector_t calc_dev_sboffset(struct block_device *bdev)
 {
 	sector_t size = bdev->bd_inode->i_size >> BLOCK_SIZE_BITS;
 	return MD_NEW_SIZE_BLOCKS(size);
@@ -1798,6 +1798,8 @@ static int do_md_stop(mddev_t * mddev, int ro)
 				goto out;
 			mddev->ro = 1;
 		} else {
+			bitmap_flush(mddev);
+			wait_event(mddev->sb_wait, atomic_read(&mddev->pending_writes)==0);
 			if (mddev->ro)
 				set_disk_ro(disk, 0);
 			blk_queue_make_request(mddev->queue, md_fail_request);
@@ -3484,7 +3486,6 @@ static void md_do_sync(mddev_t *mddev)
 			goto skip;
 		}
 		ITERATE_MDDEV(mddev2,tmp) {
-			printk(".");
 			if (mddev2 == mddev)
 				continue;
 			if (mddev2->curr_resync && 
@@ -4007,3 +4008,4 @@ EXPORT_SYMBOL(md_wakeup_thread);
 EXPORT_SYMBOL(md_print_devices);
 EXPORT_SYMBOL(md_check_recovery);
 MODULE_LICENSE("GPL");
+MODULE_ALIAS("md");
diff --git a/drivers/md/raid1.c b/drivers/md/raid1.c
index 5f253ee536b..51d9645ed09 100644
--- a/drivers/md/raid1.c
+++ b/drivers/md/raid1.c
@@ -893,7 +893,6 @@ static int end_sync_read(struct bio *bio, unsigned int bytes_done, int error)
 	if (!uptodate) {
 		md_error(r1_bio->mddev,
 			 conf->mirrors[r1_bio->read_disk].rdev);
-		set_bit(R1BIO_Degraded, &r1_bio->state);
 	} else
 		set_bit(R1BIO_Uptodate, &r1_bio->state);
 	rdev_dec_pending(conf->mirrors[r1_bio->read_disk].rdev, conf->mddev);
@@ -918,10 +917,9 @@ static int end_sync_write(struct bio *bio, unsigned int bytes_done, int error)
 			mirror = i;
 			break;
 		}
-	if (!uptodate) {
+	if (!uptodate)
 		md_error(mddev, conf->mirrors[mirror].rdev);
-		set_bit(R1BIO_Degraded, &r1_bio->state);
-	}
+
 	update_head_pos(mirror, r1_bio);
 
 	if (atomic_dec_and_test(&r1_bio->remaining)) {
@@ -1109,6 +1107,7 @@ static sector_t sync_request(mddev_t *mddev, sector_t sector_nr, int *skipped, i
 	int i;
 	int write_targets = 0;
 	int sync_blocks;
+	int still_degraded = 0;
 
 	if (!conf->r1buf_pool)
 	{
@@ -1137,7 +1136,10 @@ static sector_t sync_request(mddev_t *mddev, sector_t sector_nr, int *skipped, i
 		return 0;
 	}
 
-	if (!bitmap_start_sync(mddev->bitmap, sector_nr, &sync_blocks, mddev->degraded) &&
+	/* before building a request, check if we can skip these blocks..
+	 * This call the bitmap_start_sync doesn't actually record anything
+	 */
+	if (!bitmap_start_sync(mddev->bitmap, sector_nr, &sync_blocks, 1) &&
 	    !conf->fullsync) {
 		/* We can skip this block, and probably several more */
 		*skipped = 1;
@@ -1203,24 +1205,23 @@ static sector_t sync_request(mddev_t *mddev, sector_t sector_nr, int *skipped, i
 		if (i == disk) {
 			bio->bi_rw = READ;
 			bio->bi_end_io = end_sync_read;
-		} else if (conf->mirrors[i].rdev &&
-			   !conf->mirrors[i].rdev->faulty &&
-			   (!conf->mirrors[i].rdev->in_sync ||
-			    sector_nr + RESYNC_SECTORS > mddev->recovery_cp)) {
+		} else if (conf->mirrors[i].rdev == NULL ||
+			   conf->mirrors[i].rdev->faulty) {
+			still_degraded = 1;
+			continue;
+		} else if (!conf->mirrors[i].rdev->in_sync ||
+			   sector_nr + RESYNC_SECTORS > mddev->recovery_cp) {
 			bio->bi_rw = WRITE;
 			bio->bi_end_io = end_sync_write;
 			write_targets ++;
 		} else
+			/* no need to read or write here */
 			continue;
 		bio->bi_sector = sector_nr + conf->mirrors[i].rdev->data_offset;
 		bio->bi_bdev = conf->mirrors[i].rdev->bdev;
 		bio->bi_private = r1_bio;
 	}
 
-	if (write_targets + 1 < conf->raid_disks)
-		/* array degraded, can't clear bitmap */
-		set_bit(R1BIO_Degraded, &r1_bio->state);
-
 	if (write_targets == 0) {
 		/* There is nowhere to write, so all non-sync
 		 * drives must be failed - so we are finished
@@ -1243,7 +1244,7 @@ static sector_t sync_request(mddev_t *mddev, sector_t sector_nr, int *skipped, i
 			break;
 		if (sync_blocks == 0) {
 			if (!bitmap_start_sync(mddev->bitmap, sector_nr,
-					&sync_blocks, mddev->degraded) &&
+					&sync_blocks, still_degraded) &&
 					!conf->fullsync)
 				break;
 			if (sync_blocks < (PAGE_SIZE>>9))
@@ -1468,6 +1469,7 @@ static int raid1_resize(mddev_t *mddev, sector_t sectors)
 		set_bit(MD_RECOVERY_NEEDED, &mddev->recovery);
 	}
 	mddev->size = mddev->array_size;
+	mddev->resync_max_sectors = sectors;
 	return 0;
 }
 
diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
index 93a9726cc2d..43f231a467d 100644
--- a/drivers/md/raid5.c
+++ b/drivers/md/raid5.c
@@ -1653,6 +1653,7 @@ static int run (mddev_t *mddev)
 
 	/* device size must be a multiple of chunk size */
 	mddev->size &= ~(mddev->chunk_size/1024 -1);
+	mddev->resync_max_sectors = mddev->size << 1;
 
 	if (!conf->chunk_size || conf->chunk_size % 4) {
 		printk(KERN_ERR "raid5: invalid chunk size %d for %s\n",
@@ -1931,6 +1932,7 @@ static int raid5_resize(mddev_t *mddev, sector_t sectors)
 		set_bit(MD_RECOVERY_NEEDED, &mddev->recovery);
 	}
 	mddev->size = sectors /2;
+	mddev->resync_max_sectors = sectors;
 	return 0;
 }
 
diff --git a/drivers/md/raid6main.c b/drivers/md/raid6main.c
index f62ea1a73d0..495dee1d1e8 100644
--- a/drivers/md/raid6main.c
+++ b/drivers/md/raid6main.c
@@ -1813,6 +1813,7 @@ static int run (mddev_t *mddev)
 
 	/* device size must be a multiple of chunk size */
 	mddev->size &= ~(mddev->chunk_size/1024 -1);
+	mddev->resync_max_sectors = mddev->size << 1;
 
 	if (conf->raid_disks < 4) {
 		printk(KERN_ERR "raid6: not enough configured devices for %s (%d, minimum 4)\n",
@@ -2095,6 +2096,7 @@ static int raid6_resize(mddev_t *mddev, sector_t sectors)
 		set_bit(MD_RECOVERY_NEEDED, &mddev->recovery);
 	}
 	mddev->size = sectors /2;
+	mddev->resync_max_sectors = sectors;
 	return 0;
 }
 
diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig
index d847c62bd83..e83256d0fd1 100644
--- a/drivers/media/dvb/frontends/Kconfig
+++ b/drivers/media/dvb/frontends/Kconfig
@@ -187,8 +187,8 @@ config DVB_BCM3510
 	  An ATSC 8VSB/16VSB and QAM64/256 tuner module. Say Y when you want to
 	  support this frontend.
 
-config DVB_LGDT3302
-	tristate "LGDT3302 based (DViCO FusionHDTV3 Gold)"
+config DVB_LGDT330X
+	tristate "LGDT3302 or LGDT3303 based (DViCO FusionHDTV Gold)"
 	depends on DVB_CORE
 	help
 	  An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want
diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile
index de5e240cba7..ad8658ffd60 100644
--- a/drivers/media/dvb/frontends/Makefile
+++ b/drivers/media/dvb/frontends/Makefile
@@ -30,4 +30,4 @@ obj-$(CONFIG_DVB_OR51211) += or51211.o
 obj-$(CONFIG_DVB_OR51132) += or51132.o
 obj-$(CONFIG_DVB_BCM3510) += bcm3510.o
 obj-$(CONFIG_DVB_S5H1420) += s5h1420.o
-obj-$(CONFIG_DVB_LGDT3302) += lgdt3302.o
+obj-$(CONFIG_DVB_LGDT330X) += lgdt330x.o
diff --git a/drivers/media/dvb/frontends/dvb-pll.c b/drivers/media/dvb/frontends/dvb-pll.c
index 5afeaa9b43b..536c35d969b 100644
--- a/drivers/media/dvb/frontends/dvb-pll.c
+++ b/drivers/media/dvb/frontends/dvb-pll.c
@@ -82,13 +82,14 @@ struct dvb_pll_desc dvb_pll_lg_z201 = {
 	.name  = "LG z201",
 	.min   = 174000000,
 	.max   = 862000000,
-	.count = 5,
+	.count = 6,
 	.entries = {
 		{          0, 36166667, 166666, 0xbc, 0x03 },
-		{  443250000, 36166667, 166666, 0xbc, 0x01 },
-		{  542000000, 36166667, 166666, 0xbc, 0x02 },
-		{  830000000, 36166667, 166666, 0xf4, 0x02 },
-		{  999999999, 36166667, 166666, 0xfc, 0x02 },
+		{  157500000, 36166667, 166666, 0xbc, 0x01 },
+		{  443250000, 36166667, 166666, 0xbc, 0x02 },
+		{  542000000, 36166667, 166666, 0xbc, 0x04 },
+		{  830000000, 36166667, 166666, 0xf4, 0x04 },
+		{  999999999, 36166667, 166666, 0xfc, 0x04 },
 	},
 };
 EXPORT_SYMBOL(dvb_pll_lg_z201);
@@ -224,6 +225,22 @@ struct dvb_pll_desc dvb_pll_tua6034 = {
 };
 EXPORT_SYMBOL(dvb_pll_tua6034);
 
+/* Infineon TUA6034
+ * used in LG Innotek TDVS-H062F
+ */
+struct dvb_pll_desc dvb_pll_tdvs_tua6034 = {
+	.name  = "LG/Infineon TUA6034",
+	.min   =  54000000,
+	.max   = 863000000,
+	.count = 3,
+	.entries = {
+		{  160000000, 44000000, 62500, 0xce, 0x01 },
+		{  455000000, 44000000, 62500, 0xce, 0x02 },
+		{  999999999, 44000000, 62500, 0xce, 0x04 },
+	},
+};
+EXPORT_SYMBOL(dvb_pll_tdvs_tua6034);
+
 /* Philips FMD1216ME
  * used in Medion Hybrid PCMCIA card and USB Box
  */
diff --git a/drivers/media/dvb/frontends/dvb-pll.h b/drivers/media/dvb/frontends/dvb-pll.h
index cb794759d89..205b2d1a885 100644
--- a/drivers/media/dvb/frontends/dvb-pll.h
+++ b/drivers/media/dvb/frontends/dvb-pll.h
@@ -31,6 +31,7 @@ extern struct dvb_pll_desc dvb_pll_unknown_1;
 extern struct dvb_pll_desc dvb_pll_tua6010xs;
 extern struct dvb_pll_desc dvb_pll_env57h1xd5;
 extern struct dvb_pll_desc dvb_pll_tua6034;
+extern struct dvb_pll_desc dvb_pll_tdvs_tua6034;
 extern struct dvb_pll_desc dvb_pll_tda665x;
 extern struct dvb_pll_desc dvb_pll_fmd1216me;
 extern struct dvb_pll_desc dvb_pll_tded4;
diff --git a/drivers/media/dvb/frontends/lgdt3302.c b/drivers/media/dvb/frontends/lgdt3302.c
deleted file mode 100644
index c85a2a99df4..00000000000
--- a/drivers/media/dvb/frontends/lgdt3302.c
+++ /dev/null
@@ -1,599 +0,0 @@
-/*
- *    Support for LGDT3302 (DViCO FustionHDTV 3 Gold) - VSB/QAM
- *
- *    Copyright (C) 2005 Wilson Michaels <wilsonmichaels@earthlink.net>
- *
- *    Based on code from  Kirk Lapray <kirk_lapray@bigfoot.com>
- *                           Copyright (C) 2005
- *
- *    This program is free software; you can redistribute it and/or modify
- *    it under the terms of the GNU General Public License as published by
- *    the Free Software Foundation; either version 2 of the License, or
- *    (at your option) any later version.
- *
- *    This program is distributed in the hope that it will be useful,
- *    but WITHOUT ANY WARRANTY; without even the implied warranty of
- *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *    GNU General Public License for more details.
- *
- *    You should have received a copy of the GNU General Public License
- *    along with this program; if not, write to the Free Software
- *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-/*
- *                      NOTES ABOUT THIS DRIVER
- *
- * This driver supports DViCO FusionHDTV 3 Gold under Linux.
- *
- * TODO:
- * BER and signal strength always return 0.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <asm/byteorder.h>
-
-#include "dvb_frontend.h"
-#include "dvb-pll.h"
-#include "lgdt3302_priv.h"
-#include "lgdt3302.h"
-
-static int debug = 0;
-module_param(debug, int, 0644);
-MODULE_PARM_DESC(debug,"Turn on/off lgdt3302 frontend debugging (default:off).");
-#define dprintk(args...) \
-do { \
-if (debug) printk(KERN_DEBUG "lgdt3302: " args); \
-} while (0)
-
-struct lgdt3302_state
-{
-	struct i2c_adapter* i2c;
-	struct dvb_frontend_ops ops;
-
-	/* Configuration settings */
-	const struct lgdt3302_config* config;
-
-	struct dvb_frontend frontend;
-
-	/* Demodulator private data */
-	fe_modulation_t current_modulation;
-
-	/* Tuner private data */
-	u32 current_frequency;
-};
-
-static int i2c_writebytes (struct lgdt3302_state* state,
-			   u8 addr, /* demod_address or pll_address */
-			   u8 *buf, /* data bytes to send */
-			   int len  /* number of bytes to send */ )
-{
-	if (addr == state->config->pll_address) {
-		struct i2c_msg msg =
-			{ .addr = addr, .flags = 0, .buf = buf,  .len = len };
-		int err;
-
-		if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
-			printk(KERN_WARNING "lgdt3302: %s error (addr %02x <- %02x, err == %i)\n", __FUNCTION__, addr, buf[0], err);
-			if (err < 0)
-				return err;
-			else
-				return -EREMOTEIO;
-		}
-	} else {
-		u8 tmp[] = { buf[0], buf[1] };
-		struct i2c_msg msg =
-			{ .addr = addr, .flags = 0, .buf = tmp,  .len = 2 };
-		int err;
-		int i;
-
-		for (i=1; i<len; i++) {
-			tmp[1] = buf[i];
-			if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
-				printk(KERN_WARNING "lgdt3302: %s error (addr %02x <- %02x, err == %i)\n", __FUNCTION__, addr, buf[0], err);
-				if (err < 0)
-					return err;
-				else
-					return -EREMOTEIO;
-			}
-			tmp[0]++;
-		}
-	}
-	return 0;
-}
-static int i2c_readbytes (struct lgdt3302_state* state,
-			  u8 addr, /* demod_address or pll_address */
-			  u8 *buf, /* holds data bytes read */
-			  int len  /* number of bytes to read */ )
-{
-	struct i2c_msg msg =
-		{ .addr = addr, .flags = I2C_M_RD, .buf = buf,  .len = len };
-	int err;
-
-	if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
-		printk(KERN_WARNING "lgdt3302: %s error (addr %02x, err == %i)\n", __FUNCTION__, addr, err);
-		return -EREMOTEIO;
-	}
-	return 0;
-}
-
-/*
- * This routine writes the register (reg) to the demod bus
- * then reads the data returned for (len) bytes.
- */
-
-static u8 i2c_selectreadbytes (struct lgdt3302_state* state,
-			       enum I2C_REG reg, u8* buf, int len)
-{
-	u8 wr [] = { reg };
-	struct i2c_msg msg [] = {
-		{ .addr = state->config->demod_address,
-		  .flags = 0, .buf = wr,  .len = 1 },
-		{ .addr = state->config->demod_address,
-		  .flags = I2C_M_RD, .buf = buf, .len = len },
-	};
-	int ret;
-	ret = i2c_transfer(state->i2c, msg, 2);
-	if (ret != 2) {
-		printk(KERN_WARNING "lgdt3302: %s: addr 0x%02x select 0x%02x error (ret == %i)\n", __FUNCTION__, state->config->demod_address, reg, ret);
-	} else {
-		ret = 0;
-	}
-	return ret;
-}
-
-/* Software reset */
-int lgdt3302_SwReset(struct lgdt3302_state* state)
-{
-	u8 ret;
-	u8 reset[] = {
-		IRQ_MASK,
-		0x00 /* bit 6 is active low software reset
-		      *	bits 5-0 are 1 to mask interrupts */
-	};
-
-	ret = i2c_writebytes(state,
-			     state->config->demod_address,
-			     reset, sizeof(reset));
-	if (ret == 0) {
-		/* spec says reset takes 100 ns why wait */
-		/* mdelay(100);    */ /* keep low for 100mS */
-		reset[1] = 0x7f;      /* force reset high (inactive)
-				       * and unmask interrupts */
-		ret = i2c_writebytes(state,
-				     state->config->demod_address,
-				     reset, sizeof(reset));
-	}
-	/* Spec does not indicate a need for this either */
-	/*mdelay(5); */               /* wait 5 msec before doing more */
-	return ret;
-}
-
-static int lgdt3302_init(struct dvb_frontend* fe)
-{
-	/* Hardware reset is done using gpio[0] of cx23880x chip.
-	 * I'd like to do it here, but don't know how to find chip address.
-	 * cx88-cards.c arranges for the reset bit to be inactive (high).
-	 * Maybe there needs to be a callable function in cx88-core or
-	 * the caller of this function needs to do it. */
-
-	dprintk("%s entered\n", __FUNCTION__);
-	return lgdt3302_SwReset((struct lgdt3302_state*) fe->demodulator_priv);
-}
-
-static int lgdt3302_read_ber(struct dvb_frontend* fe, u32* ber)
-{
-	*ber = 0; /* Dummy out for now */
-	return 0;
-}
-
-static int lgdt3302_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
-{
-	struct lgdt3302_state* state = (struct lgdt3302_state*) fe->demodulator_priv;
-	u8 buf[2];
-
-	i2c_selectreadbytes(state, PACKET_ERR_COUNTER1, buf, sizeof(buf));
-
-	*ucblocks = (buf[0] << 8) | buf[1];
-	return 0;
-}
-
-static int lgdt3302_set_parameters(struct dvb_frontend* fe,
-				   struct dvb_frontend_parameters *param)
-{
-	u8 buf[4];
-	struct lgdt3302_state* state =
-		(struct lgdt3302_state*) fe->demodulator_priv;
-
-	/* Use 50MHz parameter values from spec sheet since xtal is 50 */
-	static u8 top_ctrl_cfg[]   = { TOP_CONTROL, 0x03 };
-	static u8 vsb_freq_cfg[]   = { VSB_CARRIER_FREQ0, 0x00, 0x87, 0x8e, 0x01 };
-	static u8 demux_ctrl_cfg[] = { DEMUX_CONTROL, 0xfb };
-	static u8 agc_rf_cfg[]     = { AGC_RF_BANDWIDTH0, 0x40, 0x93, 0x00 };
-	static u8 agc_ctrl_cfg[]   = { AGC_FUNC_CTRL2, 0xc6, 0x40 };
-	static u8 agc_delay_cfg[]  = { AGC_DELAY0, 0x07, 0x00, 0xfe };
-	static u8 agc_loop_cfg[]   = { AGC_LOOP_BANDWIDTH0, 0x08, 0x9a };
-
-	/* Change only if we are actually changing the modulation */
-	if (state->current_modulation != param->u.vsb.modulation) {
-		switch(param->u.vsb.modulation) {
-		case VSB_8:
-			dprintk("%s: VSB_8 MODE\n", __FUNCTION__);
-
-			/* Select VSB mode and serial MPEG interface */
-			top_ctrl_cfg[1] = 0x07;
-			break;
-
-		case QAM_64:
-			dprintk("%s: QAM_64 MODE\n", __FUNCTION__);
-
-			/* Select QAM_64 mode and serial MPEG interface */
-			top_ctrl_cfg[1] = 0x04;
-			break;
-
-		case QAM_256:
-			dprintk("%s: QAM_256 MODE\n", __FUNCTION__);
-
-			/* Select QAM_256 mode and serial MPEG interface */
-			top_ctrl_cfg[1] = 0x05;
-			break;
-		default:
-			printk(KERN_WARNING "lgdt3302: %s: Modulation type(%d) UNSUPPORTED\n", __FUNCTION__, param->u.vsb.modulation);
-			return -1;
-		}
-		/* Initializations common to all modes */
-
-		/* Select the requested mode */
-		i2c_writebytes(state, state->config->demod_address,
-			       top_ctrl_cfg, sizeof(top_ctrl_cfg));
-
-		/* Change the value of IFBW[11:0]
-		   of AGC IF/RF loop filter bandwidth register */
-		i2c_writebytes(state, state->config->demod_address,
-			       agc_rf_cfg, sizeof(agc_rf_cfg));
-
-		/* Change the value of bit 6, 'nINAGCBY' and
-		   'NSSEL[1:0] of ACG function control register 2 */
-		/* Change the value of bit 6 'RFFIX'
-		   of AGC function control register 3 */
-		i2c_writebytes(state, state->config->demod_address,
-			       agc_ctrl_cfg, sizeof(agc_ctrl_cfg));
-
-		/* Change the TPCLK pin polarity
-		   data is valid on falling clock */
-		i2c_writebytes(state, state->config->demod_address,
-			       demux_ctrl_cfg, sizeof(demux_ctrl_cfg));
-
-		/* Change the value of NCOCTFV[25:0] of carrier
-		   recovery center frequency register */
-		i2c_writebytes(state, state->config->demod_address,
-				       vsb_freq_cfg, sizeof(vsb_freq_cfg));
-
-		/* Set the value of 'INLVTHD' register 0x2a/0x2c to 0x7fe */
-		i2c_writebytes(state, state->config->demod_address,
-			       agc_delay_cfg, sizeof(agc_delay_cfg));
-
-		/* Change the value of IAGCBW[15:8]
-		   of inner AGC loop filter bandwith */
-		i2c_writebytes(state, state->config->demod_address,
-			       agc_loop_cfg, sizeof(agc_loop_cfg));
-
-		state->config->set_ts_params(fe, 0);
-		state->current_modulation = param->u.vsb.modulation;
-	}
-
-	/* Change only if we are actually changing the channel */
-	if (state->current_frequency != param->frequency) {
-		dvb_pll_configure(state->config->pll_desc, buf,
-				  param->frequency, 0);
-		dprintk("%s: tuner bytes: 0x%02x 0x%02x "
-			"0x%02x 0x%02x\n", __FUNCTION__, buf[0],buf[1],buf[2],buf[3]);
-		i2c_writebytes(state, state->config->pll_address ,buf, 4);
-
-		/* Check the status of the tuner pll */
-		i2c_readbytes(state, state->config->pll_address, buf, 1);
-		dprintk("%s: tuner status byte = 0x%02x\n", __FUNCTION__, buf[0]);
-
-		/* Update current frequency */
-		state->current_frequency = param->frequency;
-	}
-	lgdt3302_SwReset(state);
-	return 0;
-}
-
-static int lgdt3302_get_frontend(struct dvb_frontend* fe,
-				 struct dvb_frontend_parameters* param)
-{
-	struct lgdt3302_state *state = fe->demodulator_priv;
-	param->frequency = state->current_frequency;
-	return 0;
-}
-
-static int lgdt3302_read_status(struct dvb_frontend* fe, fe_status_t* status)
-{
-	struct lgdt3302_state* state = (struct lgdt3302_state*) fe->demodulator_priv;
-	u8 buf[3];
-
-	*status = 0; /* Reset status result */
-
-	/* Check the status of the tuner pll */
-	i2c_readbytes(state, state->config->pll_address, buf, 1);
-	dprintk("%s: tuner status byte = 0x%02x\n", __FUNCTION__, buf[0]);
-	if ((buf[0] & 0xc0) != 0x40)
-		return 0; /* Tuner PLL not locked or not powered on */
-
-	/*
-	 * You must set the Mask bits to 1 in the IRQ_MASK in order
-	 * to see that status bit in the IRQ_STATUS register.
-	 * This is done in SwReset();
-	 */
-
-	/* AGC status register */
-	i2c_selectreadbytes(state, AGC_STATUS, buf, 1);
-	dprintk("%s: AGC_STATUS = 0x%02x\n", __FUNCTION__, buf[0]);
-	if ((buf[0] & 0x0c) == 0x8){
-		/* Test signal does not exist flag */
-		/* as well as the AGC lock flag.   */
-		*status |= FE_HAS_SIGNAL;
-	} else {
-		/* Without a signal all other status bits are meaningless */
-		return 0;
-	}
-
-	/* signal status */
-	i2c_selectreadbytes(state, TOP_CONTROL, buf, sizeof(buf));
-	dprintk("%s: TOP_CONTROL = 0x%02x, IRO_MASK = 0x%02x, IRQ_STATUS = 0x%02x\n", __FUNCTION__, buf[0], buf[1], buf[2]);
-
-#if 0
-	/* Alternative method to check for a signal */
-	/* using the SNR good/bad interrupts.   */
-	if ((buf[2] & 0x30) == 0x10)
-		*status |= FE_HAS_SIGNAL;
-#endif
-
-	/* sync status */
-	if ((buf[2] & 0x03) == 0x01) {
-		*status |= FE_HAS_SYNC;
-	}
-
-	/* FEC error status */
-	if ((buf[2] & 0x0c) == 0x08) {
-		*status |= FE_HAS_LOCK;
-		*status |= FE_HAS_VITERBI;
-	}
-
-	/* Carrier Recovery Lock Status Register */
-	i2c_selectreadbytes(state, CARRIER_LOCK, buf, 1);
-	dprintk("%s: CARRIER_LOCK = 0x%02x\n", __FUNCTION__, buf[0]);
-	switch (state->current_modulation) {
-	case QAM_256:
-	case QAM_64:
-		/* Need to undestand why there are 3 lock levels here */
-		if ((buf[0] & 0x07) == 0x07)
-			*status |= FE_HAS_CARRIER;
-		break;
-	case VSB_8:
-		if ((buf[0] & 0x80) == 0x80)
-			*status |= FE_HAS_CARRIER;
-		break;
-	default:
-		printk("KERN_WARNING lgdt3302: %s: Modulation set to unsupported value\n", __FUNCTION__);
-	}
-
-	return 0;
-}
-
-static int lgdt3302_read_signal_strength(struct dvb_frontend* fe, u16* strength)
-{
-	/* not directly available. */
-	return 0;
-}
-
-static int lgdt3302_read_snr(struct dvb_frontend* fe, u16* snr)
-{
-#ifdef SNR_IN_DB
-	/*
-	 * Spec sheet shows formula for SNR_EQ = 10 log10(25 * 24**2 / noise)
-	 * and SNR_PH = 10 log10(25 * 32**2 / noise) for equalizer and phase tracker
-	 * respectively. The following tables are built on these formulas.
-	 * The usual definition is SNR = 20 log10(signal/noise)
-	 * If the specification is wrong the value retuned is 1/2 the actual SNR in db.
-	 *
-	 * This table is a an ordered list of noise values computed by the
-	 * formula from the spec sheet such that the index into the table
-	 * starting at 43 or 45 is the SNR value in db. There are duplicate noise
-	 * value entries at the beginning because the SNR varies more than
-	 * 1 db for a change of 1 digit in noise at very small values of noise.
-	 *
-	 * Examples from SNR_EQ table:
-	 * noise SNR
-	 *   0    43
-	 *   1    42
-	 *   2    39
-	 *   3    37
-	 *   4    36
-	 *   5    35
-	 *   6    34
-	 *   7    33
-	 *   8    33
-	 *   9    32
-	 *   10   32
-	 *   11   31
-	 *   12   31
-	 *   13   30
-	 */
-
-	static const u32 SNR_EQ[] =
-		{ 1,     2,      2,      2, 3,      3,      4,     4,     5,     7,
-		  9,     11,     13,     17, 21,     26,     33,    41,    52,    65,
-		  81,    102,    129,    162, 204,    257,    323,   406,   511,   644,
-		  810,   1020,   1284,   1616, 2035,   2561,   3224,  4059,  5110,  6433,
-		  8098,  10195,  12835,  16158, 20341,  25608,  32238, 40585, 51094, 64323,
-		  80978, 101945, 128341, 161571, 203406, 256073, 0x40000
-		};
-
-	static const u32 SNR_PH[] =
-		{ 1,     2,      2,      2,      3,      3,     4,     5,     6,     8,
-		  10,    12,     15,     19,     23,     29, 37,    46,    58,    73,
-		  91,    115,    144,    182,    229,    288, 362,   456,   574,   722,
-		  909,   1144,   1440,   1813,   2282,   2873, 3617,  4553,  5732,  7216,
-		  9084,  11436,  14396,  18124,  22817,  28724,  36161, 45524, 57312, 72151,
-		  90833, 114351, 143960, 181235, 228161, 0x040000
-		};
-
-	static u8 buf[5];/* read data buffer */
-	static u32 noise;   /* noise value */
-	static u32 snr_db;  /* index into SNR_EQ[] */
-	struct lgdt3302_state* state = (struct lgdt3302_state*) fe->demodulator_priv;
-
-	/* read both equalizer and pase tracker noise data */
-	i2c_selectreadbytes(state, EQPH_ERR0, buf, sizeof(buf));
-
-	if (state->current_modulation == VSB_8) {
-		/* Equalizer Mean-Square Error Register for VSB */
-		noise = ((buf[0] & 7) << 16) | (buf[1] << 8) | buf[2];
-
-		/*
-		 * Look up noise value in table.
-		 * A better search algorithm could be used...
-		 * watch out there are duplicate entries.
-		 */
-		for (snr_db = 0; snr_db < sizeof(SNR_EQ); snr_db++) {
-			if (noise < SNR_EQ[snr_db]) {
-				*snr = 43 - snr_db;
-				break;
-			}
-		}
-	} else {
-		/* Phase Tracker Mean-Square Error Register for QAM */
-		noise = ((buf[0] & 7<<3) << 13) | (buf[3] << 8) | buf[4];
-
-		/* Look up noise value in table. */
-		for (snr_db = 0; snr_db < sizeof(SNR_PH); snr_db++) {
-			if (noise < SNR_PH[snr_db]) {
-				*snr = 45 - snr_db;
-				break;
-			}
-		}
-	}
-#else
-	/* Return the raw noise value */
-	static u8 buf[5];/* read data buffer */
-	static u32 noise;   /* noise value */
-	struct lgdt3302_state* state = (struct lgdt3302_state*) fe->demodulator_priv;
-
-	/* read both equalizer and pase tracker noise data */
-	i2c_selectreadbytes(state, EQPH_ERR0, buf, sizeof(buf));
-
-	if (state->current_modulation == VSB_8) {
-		/* Equalizer Mean-Square Error Register for VSB */
-		noise = ((buf[0] & 7) << 16) | (buf[1] << 8) | buf[2];
-	} else {
-		/* Phase Tracker Mean-Square Error Register for QAM */
-		noise = ((buf[0] & 7<<3) << 13) | (buf[3] << 8) | buf[4];
-	}
-
-	/* Small values for noise mean signal is better so invert noise */
-	/* Noise is 19 bit value so discard 3 LSB*/
-	*snr = ~noise>>3;
-#endif
-
-	dprintk("%s: noise = 0x%05x, snr = %idb\n",__FUNCTION__, noise, *snr);
-
-	return 0;
-}
-
-static int lgdt3302_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
-{
-	/* I have no idea about this - it may not be needed */
-	fe_tune_settings->min_delay_ms = 500;
-	fe_tune_settings->step_size = 0;
-	fe_tune_settings->max_drift = 0;
-	return 0;
-}
-
-static void lgdt3302_release(struct dvb_frontend* fe)
-{
-	struct lgdt3302_state* state = (struct lgdt3302_state*) fe->demodulator_priv;
-	kfree(state);
-}
-
-static struct dvb_frontend_ops lgdt3302_ops;
-
-struct dvb_frontend* lgdt3302_attach(const struct lgdt3302_config* config,
-				     struct i2c_adapter* i2c)
-{
-	struct lgdt3302_state* state = NULL;
-	u8 buf[1];
-
-	/* Allocate memory for the internal state */
-	state = (struct lgdt3302_state*) kmalloc(sizeof(struct lgdt3302_state), GFP_KERNEL);
-	if (state == NULL)
-		goto error;
-	memset(state,0,sizeof(*state));
-
-	/* Setup the state */
-	state->config = config;
-	state->i2c = i2c;
-	memcpy(&state->ops, &lgdt3302_ops, sizeof(struct dvb_frontend_ops));
-	/* Verify communication with demod chip */
-	if (i2c_selectreadbytes(state, 2, buf, 1))
-		goto error;
-
-	state->current_frequency = -1;
-	state->current_modulation = -1;
-
-	/* Create dvb_frontend */
-	state->frontend.ops = &state->ops;
-	state->frontend.demodulator_priv = state;
-	return &state->frontend;
-
-error:
-	if (state)
-		kfree(state);
-	dprintk("%s: ERROR\n",__FUNCTION__);
-	return NULL;
-}
-
-static struct dvb_frontend_ops lgdt3302_ops = {
-	.info = {
-		.name= "LG Electronics LGDT3302 VSB/QAM Frontend",
-		.type = FE_ATSC,
-		.frequency_min= 54000000,
-		.frequency_max= 858000000,
-		.frequency_stepsize= 62500,
-		/* Symbol rate is for all VSB modes need to check QAM */
-		.symbol_rate_min    = 10762000,
-		.symbol_rate_max    = 10762000,
-		.caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
-	},
-	.init                 = lgdt3302_init,
-	.set_frontend         = lgdt3302_set_parameters,
-	.get_frontend         = lgdt3302_get_frontend,
-	.get_tune_settings    = lgdt3302_get_tune_settings,
-	.read_status          = lgdt3302_read_status,
-	.read_ber             = lgdt3302_read_ber,
-	.read_signal_strength = lgdt3302_read_signal_strength,
-	.read_snr             = lgdt3302_read_snr,
-	.read_ucblocks        = lgdt3302_read_ucblocks,
-	.release              = lgdt3302_release,
-};
-
-MODULE_DESCRIPTION("LGDT3302 [DViCO FusionHDTV 3 Gold] (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver");
-MODULE_AUTHOR("Wilson Michaels");
-MODULE_LICENSE("GPL");
-
-EXPORT_SYMBOL(lgdt3302_attach);
-
-/*
- * Local variables:
- * c-basic-offset: 8
- * compile-command: "make DVB=1"
- * End:
- */
diff --git a/drivers/media/dvb/frontends/lgdt330x.c b/drivers/media/dvb/frontends/lgdt330x.c
new file mode 100644
index 00000000000..c48e7c11d70
--- /dev/null
+++ b/drivers/media/dvb/frontends/lgdt330x.c
@@ -0,0 +1,831 @@
+/*
+ *    Support for LGDT3302 and LGDT3303 - VSB/QAM
+ *
+ *    Copyright (C) 2005 Wilson Michaels <wilsonmichaels@earthlink.net>
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+/*
+ *                      NOTES ABOUT THIS DRIVER
+ *
+ * This Linux driver supports:
+ *   DViCO FusionHDTV 3 Gold-Q
+ *   DViCO FusionHDTV 3 Gold-T
+ *   DViCO FusionHDTV 5 Gold
+ *
+ * TODO:
+ * signal strength always returns 0.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <asm/byteorder.h>
+
+#include "dvb_frontend.h"
+#include "lgdt330x_priv.h"
+#include "lgdt330x.h"
+
+static int debug = 0;
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug,"Turn on/off lgdt330x frontend debugging (default:off).");
+#define dprintk(args...) \
+do { \
+if (debug) printk(KERN_DEBUG "lgdt330x: " args); \
+} while (0)
+
+struct lgdt330x_state
+{
+	struct i2c_adapter* i2c;
+	struct dvb_frontend_ops ops;
+
+	/* Configuration settings */
+	const struct lgdt330x_config* config;
+
+	struct dvb_frontend frontend;
+
+	/* Demodulator private data */
+	fe_modulation_t current_modulation;
+
+	/* Tuner private data */
+	u32 current_frequency;
+};
+
+static int i2c_write_demod_bytes (struct lgdt330x_state* state,
+			   u8 *buf, /* data bytes to send */
+			   int len  /* number of bytes to send */ )
+{
+	struct i2c_msg msg =
+		{ .addr = state->config->demod_address,
+		  .flags = 0,
+		  .buf = buf,
+		  .len = 2 };
+	int i;
+	int err;
+
+	for (i=0; i<len-1; i+=2){
+		if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
+			printk(KERN_WARNING "lgdt330x: %s error (addr %02x <- %02x, err = %i)\n", __FUNCTION__, msg.buf[0], msg.buf[1], err);
+			if (err < 0)
+				return err;
+			else
+				return -EREMOTEIO;
+		}
+		msg.buf += 2;
+	}
+	return 0;
+}
+
+/*
+ * This routine writes the register (reg) to the demod bus
+ * then reads the data returned for (len) bytes.
+ */
+
+static u8 i2c_read_demod_bytes (struct lgdt330x_state* state,
+			       enum I2C_REG reg, u8* buf, int len)
+{
+	u8 wr [] = { reg };
+	struct i2c_msg msg [] = {
+		{ .addr = state->config->demod_address,
+		  .flags = 0, .buf = wr,  .len = 1 },
+		{ .addr = state->config->demod_address,
+		  .flags = I2C_M_RD, .buf = buf, .len = len },
+	};
+	int ret;
+	ret = i2c_transfer(state->i2c, msg, 2);
+	if (ret != 2) {
+		printk(KERN_WARNING "lgdt330x: %s: addr 0x%02x select 0x%02x error (ret == %i)\n", __FUNCTION__, state->config->demod_address, reg, ret);
+	} else {
+		ret = 0;
+	}
+	return ret;
+}
+
+/* Software reset */
+static int lgdt3302_SwReset(struct lgdt330x_state* state)
+{
+	u8 ret;
+	u8 reset[] = {
+		IRQ_MASK,
+		0x00 /* bit 6 is active low software reset
+		      *	bits 5-0 are 1 to mask interrupts */
+	};
+
+	ret = i2c_write_demod_bytes(state,
+			     reset, sizeof(reset));
+	if (ret == 0) {
+
+		/* force reset high (inactive) and unmask interrupts */
+		reset[1] = 0x7f;
+		ret = i2c_write_demod_bytes(state,
+				     reset, sizeof(reset));
+	}
+	return ret;
+}
+
+static int lgdt3303_SwReset(struct lgdt330x_state* state)
+{
+	u8 ret;
+	u8 reset[] = {
+		0x02,
+		0x00 /* bit 0 is active low software reset */
+	};
+
+	ret = i2c_write_demod_bytes(state,
+			     reset, sizeof(reset));
+	if (ret == 0) {
+
+		/* force reset high (inactive) */
+		reset[1] = 0x01;
+		ret = i2c_write_demod_bytes(state,
+				     reset, sizeof(reset));
+	}
+	return ret;
+}
+
+static int lgdt330x_SwReset(struct lgdt330x_state* state)
+{
+	switch (state->config->demod_chip) {
+	case LGDT3302:
+		return lgdt3302_SwReset(state);
+	case LGDT3303:
+		return lgdt3303_SwReset(state);
+	default:
+		return -ENODEV;
+	}
+}
+
+#ifdef MUTE_TDA9887
+static int i2c_write_ntsc_demod (struct lgdt330x_state* state, u8 buf[2])
+{
+	struct i2c_msg msg =
+		{ .addr = 0x43,
+		  .flags = 0,
+		  .buf = buf,
+		  .len = 2 };
+	int err;
+
+	if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
+			printk(KERN_WARNING "lgdt330x: %s error (addr %02x <- %02x, err = %i)\n", __FUNCTION__, msg.buf[0], msg.buf[1], err);
+		if (err < 0)
+			return err;
+		else
+			return -EREMOTEIO;
+	}
+	return 0;
+}
+
+static void fiddle_with_ntsc_if_demod(struct lgdt330x_state* state)
+{
+	// Experimental code
+	u8 buf0[] = {0x00, 0x20};
+	u8 buf1[] = {0x01, 0x00};
+	u8 buf2[] = {0x02, 0x00};
+
+	i2c_write_ntsc_demod(state, buf0);
+	i2c_write_ntsc_demod(state, buf1);
+	i2c_write_ntsc_demod(state, buf2);
+}
+#endif
+
+static int lgdt330x_init(struct dvb_frontend* fe)
+{
+	/* Hardware reset is done using gpio[0] of cx23880x chip.
+	 * I'd like to do it here, but don't know how to find chip address.
+	 * cx88-cards.c arranges for the reset bit to be inactive (high).
+	 * Maybe there needs to be a callable function in cx88-core or
+	 * the caller of this function needs to do it. */
+
+	/*
+	 * Array of byte pairs <address, value>
+	 * to initialize each different chip
+	 */
+	static u8 lgdt3302_init_data[] = {
+		/* Use 50MHz parameter values from spec sheet since xtal is 50 */
+		/* Change the value of NCOCTFV[25:0] of carrier
+		   recovery center frequency register */
+		VSB_CARRIER_FREQ0, 0x00,
+		VSB_CARRIER_FREQ1, 0x87,
+		VSB_CARRIER_FREQ2, 0x8e,
+		VSB_CARRIER_FREQ3, 0x01,
+		/* Change the TPCLK pin polarity
+		   data is valid on falling clock */
+		DEMUX_CONTROL, 0xfb,
+		/* Change the value of IFBW[11:0] of
+		   AGC IF/RF loop filter bandwidth register */
+		AGC_RF_BANDWIDTH0, 0x40,
+		AGC_RF_BANDWIDTH1, 0x93,
+		AGC_RF_BANDWIDTH2, 0x00,
+		/* Change the value of bit 6, 'nINAGCBY' and
+		   'NSSEL[1:0] of ACG function control register 2 */
+		AGC_FUNC_CTRL2, 0xc6,
+		/* Change the value of bit 6 'RFFIX'
+		   of AGC function control register 3 */
+		AGC_FUNC_CTRL3, 0x40,
+		/* Set the value of 'INLVTHD' register 0x2a/0x2c
+		   to 0x7fe */
+		AGC_DELAY0, 0x07,
+		AGC_DELAY2, 0xfe,
+		/* Change the value of IAGCBW[15:8]
+		   of inner AGC loop filter bandwith */
+		AGC_LOOP_BANDWIDTH0, 0x08,
+		AGC_LOOP_BANDWIDTH1, 0x9a
+	};
+
+	static u8 lgdt3303_init_data[] = {
+		0x4c, 0x14
+	};
+
+	struct lgdt330x_state* state = fe->demodulator_priv;
+	char  *chip_name;
+	int    err;
+
+	switch (state->config->demod_chip) {
+	case LGDT3302:
+		chip_name = "LGDT3302";
+		err = i2c_write_demod_bytes(state, lgdt3302_init_data,
+									sizeof(lgdt3302_init_data));
+  		break;
+	case LGDT3303:
+		chip_name = "LGDT3303";
+		err = i2c_write_demod_bytes(state, lgdt3303_init_data,
+									sizeof(lgdt3303_init_data));
+#ifdef MUTE_TDA9887
+		fiddle_with_ntsc_if_demod(state);
+#endif
+  		break;
+	default:
+		chip_name = "undefined";
+		printk (KERN_WARNING "Only LGDT3302 and LGDT3303 are supported chips.\n");
+		err = -ENODEV;
+	}
+	dprintk("%s entered as %s\n", __FUNCTION__, chip_name);
+	if (err < 0)
+		return err;
+	return lgdt330x_SwReset(state);
+}
+
+static int lgdt330x_read_ber(struct dvb_frontend* fe, u32* ber)
+{
+	*ber = 0; /* Not supplied by the demod chips */
+	return 0;
+}
+
+static int lgdt330x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
+{
+	struct lgdt330x_state* state = fe->demodulator_priv;
+	int err;
+	u8 buf[2];
+
+	switch (state->config->demod_chip) {
+	case LGDT3302:
+		err = i2c_read_demod_bytes(state, LGDT3302_PACKET_ERR_COUNTER1,
+								  buf, sizeof(buf));
+  		break;
+	case LGDT3303:
+		err = i2c_read_demod_bytes(state, LGDT3303_PACKET_ERR_COUNTER1,
+								  buf, sizeof(buf));
+  		break;
+	default:
+		printk(KERN_WARNING
+			   "Only LGDT3302 and LGDT3303 are supported chips.\n");
+		err = -ENODEV;
+	}
+
+	*ucblocks = (buf[0] << 8) | buf[1];
+	return 0;
+}
+
+static int lgdt330x_set_parameters(struct dvb_frontend* fe,
+				   struct dvb_frontend_parameters *param)
+{
+	/*
+	 * Array of byte pairs <address, value>
+	 * to initialize 8VSB for lgdt3303 chip 50 MHz IF
+	 */
+	static u8 lgdt3303_8vsb_44_data[] = {
+		0x04, 0x00,
+		0x0d, 0x40,
+        0x0e, 0x87,
+        0x0f, 0x8e,
+        0x10, 0x01,
+        0x47, 0x8b };
+
+	/*
+	 * Array of byte pairs <address, value>
+	 * to initialize QAM for lgdt3303 chip
+	 */
+	static u8 lgdt3303_qam_data[] = {
+		0x04, 0x00,
+		0x0d, 0x00,
+		0x0e, 0x00,
+		0x0f, 0x00,
+		0x10, 0x00,
+		0x51, 0x63,
+		0x47, 0x66,
+		0x48, 0x66,
+		0x4d, 0x1a,
+		0x49, 0x08,
+		0x4a, 0x9b };
+
+	struct lgdt330x_state* state = fe->demodulator_priv;
+
+	static u8 top_ctrl_cfg[]   = { TOP_CONTROL, 0x03 };
+
+	int err;
+	/* Change only if we are actually changing the modulation */
+	if (state->current_modulation != param->u.vsb.modulation) {
+		switch(param->u.vsb.modulation) {
+		case VSB_8:
+			dprintk("%s: VSB_8 MODE\n", __FUNCTION__);
+
+			/* Select VSB mode */
+			top_ctrl_cfg[1] = 0x03;
+
+			/* Select ANT connector if supported by card */
+			if (state->config->pll_rf_set)
+				state->config->pll_rf_set(fe, 1);
+
+			if (state->config->demod_chip == LGDT3303) {
+				err = i2c_write_demod_bytes(state, lgdt3303_8vsb_44_data,
+											sizeof(lgdt3303_8vsb_44_data));
+			}
+			break;
+
+		case QAM_64:
+			dprintk("%s: QAM_64 MODE\n", __FUNCTION__);
+
+			/* Select QAM_64 mode */
+			top_ctrl_cfg[1] = 0x00;
+
+			/* Select CABLE connector if supported by card */
+			if (state->config->pll_rf_set)
+				state->config->pll_rf_set(fe, 0);
+
+			if (state->config->demod_chip == LGDT3303) {
+				err = i2c_write_demod_bytes(state, lgdt3303_qam_data,
+											sizeof(lgdt3303_qam_data));
+			}
+			break;
+
+		case QAM_256:
+			dprintk("%s: QAM_256 MODE\n", __FUNCTION__);
+
+			/* Select QAM_256 mode */
+			top_ctrl_cfg[1] = 0x01;
+
+			/* Select CABLE connector if supported by card */
+			if (state->config->pll_rf_set)
+				state->config->pll_rf_set(fe, 0);
+
+			if (state->config->demod_chip == LGDT3303) {
+				err = i2c_write_demod_bytes(state, lgdt3303_qam_data,
+											sizeof(lgdt3303_qam_data));
+			}
+			break;
+		default:
+			printk(KERN_WARNING "lgdt330x: %s: Modulation type(%d) UNSUPPORTED\n", __FUNCTION__, param->u.vsb.modulation);
+			return -1;
+		}
+		/*
+		 * select serial or parallel MPEG harware interface
+		 * Serial:   0x04 for LGDT3302 or 0x40 for LGDT3303
+		 * Parallel: 0x00
+		 */
+		top_ctrl_cfg[1] |= state->config->serial_mpeg;
+
+		/* Select the requested mode */
+		i2c_write_demod_bytes(state, top_ctrl_cfg,
+							  sizeof(top_ctrl_cfg));
+		state->config->set_ts_params(fe, 0);
+		state->current_modulation = param->u.vsb.modulation;
+	}
+
+	/* Change only if we are actually changing the channel */
+	if (state->current_frequency != param->frequency) {
+		/* Tune to the new frequency */
+		state->config->pll_set(fe, param);
+		/* Keep track of the new frequency */
+		state->current_frequency = param->frequency;
+	}
+	lgdt330x_SwReset(state);
+	return 0;
+}
+
+static int lgdt330x_get_frontend(struct dvb_frontend* fe,
+				 struct dvb_frontend_parameters* param)
+{
+	struct lgdt330x_state *state = fe->demodulator_priv;
+	param->frequency = state->current_frequency;
+	return 0;
+}
+
+static int lgdt3302_read_status(struct dvb_frontend* fe, fe_status_t* status)
+{
+	struct lgdt330x_state* state = fe->demodulator_priv;
+	u8 buf[3];
+
+	*status = 0; /* Reset status result */
+
+	/* AGC status register */
+	i2c_read_demod_bytes(state, AGC_STATUS, buf, 1);
+	dprintk("%s: AGC_STATUS = 0x%02x\n", __FUNCTION__, buf[0]);
+	if ((buf[0] & 0x0c) == 0x8){
+		/* Test signal does not exist flag */
+		/* as well as the AGC lock flag.   */
+		*status |= FE_HAS_SIGNAL;
+	} else {
+		/* Without a signal all other status bits are meaningless */
+		return 0;
+	}
+
+	/*
+	 * You must set the Mask bits to 1 in the IRQ_MASK in order
+	 * to see that status bit in the IRQ_STATUS register.
+	 * This is done in SwReset();
+	 */
+	/* signal status */
+	i2c_read_demod_bytes(state, TOP_CONTROL, buf, sizeof(buf));
+	dprintk("%s: TOP_CONTROL = 0x%02x, IRO_MASK = 0x%02x, IRQ_STATUS = 0x%02x\n", __FUNCTION__, buf[0], buf[1], buf[2]);
+
+
+	/* sync status */
+	if ((buf[2] & 0x03) == 0x01) {
+		*status |= FE_HAS_SYNC;
+	}
+
+	/* FEC error status */
+	if ((buf[2] & 0x0c) == 0x08) {
+		*status |= FE_HAS_LOCK;
+		*status |= FE_HAS_VITERBI;
+	}
+
+	/* Carrier Recovery Lock Status Register */
+	i2c_read_demod_bytes(state, CARRIER_LOCK, buf, 1);
+	dprintk("%s: CARRIER_LOCK = 0x%02x\n", __FUNCTION__, buf[0]);
+	switch (state->current_modulation) {
+	case QAM_256:
+	case QAM_64:
+		/* Need to undestand why there are 3 lock levels here */
+		if ((buf[0] & 0x07) == 0x07)
+			*status |= FE_HAS_CARRIER;
+		break;
+	case VSB_8:
+		if ((buf[0] & 0x80) == 0x80)
+			*status |= FE_HAS_CARRIER;
+		break;
+	default:
+		printk("KERN_WARNING lgdt330x: %s: Modulation set to unsupported value\n", __FUNCTION__);
+	}
+
+	return 0;
+}
+
+static int lgdt3303_read_status(struct dvb_frontend* fe, fe_status_t* status)
+{
+	struct lgdt330x_state* state = fe->demodulator_priv;
+	int err;
+	u8 buf[3];
+
+	*status = 0; /* Reset status result */
+
+	/* lgdt3303 AGC status register */
+	err = i2c_read_demod_bytes(state, 0x58, buf, 1);
+	if (err < 0)
+		return err;
+
+	dprintk("%s: AGC_STATUS = 0x%02x\n", __FUNCTION__, buf[0]);
+	if ((buf[0] & 0x21) == 0x01){
+		/* Test input signal does not exist flag */
+		/* as well as the AGC lock flag.   */
+		*status |= FE_HAS_SIGNAL;
+	} else {
+		/* Without a signal all other status bits are meaningless */
+		return 0;
+	}
+
+	/* Carrier Recovery Lock Status Register */
+	i2c_read_demod_bytes(state, CARRIER_LOCK, buf, 1);
+	dprintk("%s: CARRIER_LOCK = 0x%02x\n", __FUNCTION__, buf[0]);
+	switch (state->current_modulation) {
+	case QAM_256:
+	case QAM_64:
+		/* Need to undestand why there are 3 lock levels here */
+		if ((buf[0] & 0x07) == 0x07)
+			*status |= FE_HAS_CARRIER;
+		else
+			break;
+		i2c_read_demod_bytes(state, 0x8a, buf, 1);
+		if ((buf[0] & 0x04) == 0x04)
+			*status |= FE_HAS_SYNC;
+		if ((buf[0] & 0x01) == 0x01)
+			*status |= FE_HAS_LOCK;
+		if ((buf[0] & 0x08) == 0x08)
+			*status |= FE_HAS_VITERBI;
+		break;
+	case VSB_8:
+		if ((buf[0] & 0x80) == 0x80)
+			*status |= FE_HAS_CARRIER;
+		else
+			break;
+		i2c_read_demod_bytes(state, 0x38, buf, 1);
+		if ((buf[0] & 0x02) == 0x00)
+			*status |= FE_HAS_SYNC;
+		if ((buf[0] & 0x01) == 0x01) {
+			*status |= FE_HAS_LOCK;
+			*status |= FE_HAS_VITERBI;
+		}
+		break;
+	default:
+		printk("KERN_WARNING lgdt330x: %s: Modulation set to unsupported value\n", __FUNCTION__);
+	}
+	return 0;
+}
+
+static int lgdt330x_read_signal_strength(struct dvb_frontend* fe, u16* strength)
+{
+	/* not directly available. */
+	*strength = 0;
+	return 0;
+}
+
+static int lgdt3302_read_snr(struct dvb_frontend* fe, u16* snr)
+{
+#ifdef SNR_IN_DB
+	/*
+	 * Spec sheet shows formula for SNR_EQ = 10 log10(25 * 24**2 / noise)
+	 * and SNR_PH = 10 log10(25 * 32**2 / noise) for equalizer and phase tracker
+	 * respectively. The following tables are built on these formulas.
+	 * The usual definition is SNR = 20 log10(signal/noise)
+	 * If the specification is wrong the value retuned is 1/2 the actual SNR in db.
+	 *
+	 * This table is a an ordered list of noise values computed by the
+	 * formula from the spec sheet such that the index into the table
+	 * starting at 43 or 45 is the SNR value in db. There are duplicate noise
+	 * value entries at the beginning because the SNR varies more than
+	 * 1 db for a change of 1 digit in noise at very small values of noise.
+	 *
+	 * Examples from SNR_EQ table:
+	 * noise SNR
+	 *   0    43
+	 *   1    42
+	 *   2    39
+	 *   3    37
+	 *   4    36
+	 *   5    35
+	 *   6    34
+	 *   7    33
+	 *   8    33
+	 *   9    32
+	 *   10   32
+	 *   11   31
+	 *   12   31
+	 *   13   30
+	 */
+
+	static const u32 SNR_EQ[] =
+		{ 1,     2,      2,      2, 3,      3,      4,     4,     5,     7,
+		  9,     11,     13,     17, 21,     26,     33,    41,    52,    65,
+		  81,    102,    129,    162, 204,    257,    323,   406,   511,   644,
+		  810,   1020,   1284,   1616, 2035,   2561,   3224,  4059,  5110,  6433,
+		  8098,  10195,  12835,  16158, 20341,  25608,  32238, 40585, 51094, 64323,
+		  80978, 101945, 128341, 161571, 203406, 256073, 0x40000
+		};
+
+	static const u32 SNR_PH[] =
+		{ 1,     2,      2,      2,      3,      3,     4,     5,     6,     8,
+		  10,    12,     15,     19,     23,     29, 37,    46,    58,    73,
+		  91,    115,    144,    182,    229,    288, 362,   456,   574,   722,
+		  909,   1144,   1440,   1813,   2282,   2873, 3617,  4553,  5732,  7216,
+		  9084,  11436,  14396,  18124,  22817,  28724,  36161, 45524, 57312, 72151,
+		  90833, 114351, 143960, 181235, 228161, 0x080000
+		};
+
+	static u8 buf[5];/* read data buffer */
+	static u32 noise;   /* noise value */
+	static u32 snr_db;  /* index into SNR_EQ[] */
+	struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv;
+
+	/* read both equalizer and phase tracker noise data */
+	i2c_read_demod_bytes(state, EQPH_ERR0, buf, sizeof(buf));
+
+	if (state->current_modulation == VSB_8) {
+		/* Equalizer Mean-Square Error Register for VSB */
+		noise = ((buf[0] & 7) << 16) | (buf[1] << 8) | buf[2];
+
+		/*
+		 * Look up noise value in table.
+		 * A better search algorithm could be used...
+		 * watch out there are duplicate entries.
+		 */
+		for (snr_db = 0; snr_db < sizeof(SNR_EQ); snr_db++) {
+			if (noise < SNR_EQ[snr_db]) {
+				*snr = 43 - snr_db;
+				break;
+			}
+		}
+	} else {
+		/* Phase Tracker Mean-Square Error Register for QAM */
+		noise = ((buf[0] & 7<<3) << 13) | (buf[3] << 8) | buf[4];
+
+		/* Look up noise value in table. */
+		for (snr_db = 0; snr_db < sizeof(SNR_PH); snr_db++) {
+			if (noise < SNR_PH[snr_db]) {
+				*snr = 45 - snr_db;
+				break;
+			}
+		}
+	}
+#else
+	/* Return the raw noise value */
+	static u8 buf[5];/* read data buffer */
+	static u32 noise;   /* noise value */
+	struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv;
+
+	/* read both equalizer and pase tracker noise data */
+	i2c_read_demod_bytes(state, EQPH_ERR0, buf, sizeof(buf));
+
+	if (state->current_modulation == VSB_8) {
+		/* Phase Tracker Mean-Square Error Register for VSB */
+		noise = ((buf[0] & 7<<3) << 13) | (buf[3] << 8) | buf[4];
+	} else {
+
+		/* Carrier Recovery Mean-Square Error for QAM */
+		i2c_read_demod_bytes(state, 0x1a, buf, 2);
+		noise = ((buf[0] & 3) << 8) | buf[1];
+	}
+
+	/* Small values for noise mean signal is better so invert noise */
+	*snr = ~noise;
+#endif
+
+	dprintk("%s: noise = 0x%05x, snr = %idb\n",__FUNCTION__, noise, *snr);
+
+	return 0;
+}
+
+static int lgdt3303_read_snr(struct dvb_frontend* fe, u16* snr)
+{
+	/* Return the raw noise value */
+	static u8 buf[5];/* read data buffer */
+	static u32 noise;   /* noise value */
+	struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv;
+
+	if (state->current_modulation == VSB_8) {
+
+		/* Phase Tracker Mean-Square Error Register for VSB */
+		noise = ((buf[0] & 7) << 16) | (buf[3] << 8) | buf[4];
+	} else {
+
+		/* Carrier Recovery Mean-Square Error for QAM */
+		i2c_read_demod_bytes(state, 0x1a, buf, 2);
+		noise = (buf[0] << 8) | buf[1];
+	}
+
+	/* Small values for noise mean signal is better so invert noise */
+	*snr = ~noise;
+
+	dprintk("%s: noise = 0x%05x, snr = %idb\n",__FUNCTION__, noise, *snr);
+
+	return 0;
+}
+
+static int lgdt330x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
+{
+	/* I have no idea about this - it may not be needed */
+	fe_tune_settings->min_delay_ms = 500;
+	fe_tune_settings->step_size = 0;
+	fe_tune_settings->max_drift = 0;
+	return 0;
+}
+
+static void lgdt330x_release(struct dvb_frontend* fe)
+{
+	struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv;
+	kfree(state);
+}
+
+static struct dvb_frontend_ops lgdt3302_ops;
+static struct dvb_frontend_ops lgdt3303_ops;
+
+struct dvb_frontend* lgdt330x_attach(const struct lgdt330x_config* config,
+				     struct i2c_adapter* i2c)
+{
+	struct lgdt330x_state* state = NULL;
+	u8 buf[1];
+
+	/* Allocate memory for the internal state */
+	state = (struct lgdt330x_state*) kmalloc(sizeof(struct lgdt330x_state), GFP_KERNEL);
+	if (state == NULL)
+		goto error;
+	memset(state,0,sizeof(*state));
+
+	/* Setup the state */
+	state->config = config;
+	state->i2c = i2c;
+	switch (config->demod_chip) {
+	case LGDT3302:
+		memcpy(&state->ops, &lgdt3302_ops, sizeof(struct dvb_frontend_ops));
+		break;
+	case LGDT3303:
+		memcpy(&state->ops, &lgdt3303_ops, sizeof(struct dvb_frontend_ops));
+		break;
+	default:
+		goto error;
+	}
+
+	/* Verify communication with demod chip */
+	if (i2c_read_demod_bytes(state, 2, buf, 1))
+		goto error;
+
+	state->current_frequency = -1;
+	state->current_modulation = -1;
+
+	/* Create dvb_frontend */
+	state->frontend.ops = &state->ops;
+	state->frontend.demodulator_priv = state;
+	return &state->frontend;
+
+error:
+	if (state)
+		kfree(state);
+	dprintk("%s: ERROR\n",__FUNCTION__);
+	return NULL;
+}
+
+static struct dvb_frontend_ops lgdt3302_ops = {
+	.info = {
+		.name= "LG Electronics LGDT3302/LGDT3303 VSB/QAM Frontend",
+		.type = FE_ATSC,
+		.frequency_min= 54000000,
+		.frequency_max= 858000000,
+		.frequency_stepsize= 62500,
+		/* Symbol rate is for all VSB modes need to check QAM */
+		.symbol_rate_min    = 10762000,
+		.symbol_rate_max    = 10762000,
+		.caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
+	},
+	.init                 = lgdt330x_init,
+	.set_frontend         = lgdt330x_set_parameters,
+	.get_frontend         = lgdt330x_get_frontend,
+	.get_tune_settings    = lgdt330x_get_tune_settings,
+	.read_status          = lgdt3302_read_status,
+	.read_ber             = lgdt330x_read_ber,
+	.read_signal_strength = lgdt330x_read_signal_strength,
+	.read_snr             = lgdt3302_read_snr,
+	.read_ucblocks        = lgdt330x_read_ucblocks,
+	.release              = lgdt330x_release,
+};
+
+static struct dvb_frontend_ops lgdt3303_ops = {
+	.info = {
+		.name= "LG Electronics LGDT3303 VSB/QAM Frontend",
+		.type = FE_ATSC,
+		.frequency_min= 54000000,
+		.frequency_max= 858000000,
+		.frequency_stepsize= 62500,
+		/* Symbol rate is for all VSB modes need to check QAM */
+		.symbol_rate_min    = 10762000,
+		.symbol_rate_max    = 10762000,
+		.caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
+	},
+	.init                 = lgdt330x_init,
+	.set_frontend         = lgdt330x_set_parameters,
+	.get_frontend         = lgdt330x_get_frontend,
+	.get_tune_settings    = lgdt330x_get_tune_settings,
+	.read_status          = lgdt3303_read_status,
+	.read_ber             = lgdt330x_read_ber,
+	.read_signal_strength = lgdt330x_read_signal_strength,
+	.read_snr             = lgdt3303_read_snr,
+	.read_ucblocks        = lgdt330x_read_ucblocks,
+	.release              = lgdt330x_release,
+};
+
+MODULE_DESCRIPTION("LGDT330X (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver");
+MODULE_AUTHOR("Wilson Michaels");
+MODULE_LICENSE("GPL");
+
+EXPORT_SYMBOL(lgdt330x_attach);
+
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
diff --git a/drivers/media/dvb/frontends/lgdt3302.h b/drivers/media/dvb/frontends/lgdt330x.h
index 81587a40032..e209ba1e47c 100644
--- a/drivers/media/dvb/frontends/lgdt3302.h
+++ b/drivers/media/dvb/frontends/lgdt330x.h
@@ -1,7 +1,5 @@
 /*
- * $Id: lgdt3302.h,v 1.2 2005/06/28 23:50:48 mkrufky Exp $
- *
- *    Support for LGDT3302 (DViCO FustionHDTV 3 Gold) - VSB/QAM
+ *    Support for LGDT3302 and LGDT3303 - VSB/QAM
  *
  *    Copyright (C) 2005 Wilson Michaels <wilsonmichaels@earthlink.net>
  *
@@ -21,26 +19,40 @@
  *
  */
 
-#ifndef LGDT3302_H
-#define LGDT3302_H
+#ifndef LGDT330X_H
+#define LGDT330X_H
 
 #include <linux/dvb/frontend.h>
 
-struct lgdt3302_config
+typedef enum lg_chip_t {
+		UNDEFINED,
+		LGDT3302,
+		LGDT3303
+}lg_chip_type;
+
+struct lgdt330x_config
 {
 	/* The demodulator's i2c address */
 	u8 demod_address;
-	u8 pll_address;
-	struct dvb_pll_desc *pll_desc;
+
+	/* LG demodulator chip LGDT3302 or LGDT3303 */
+	lg_chip_type demod_chip;
+
+	/* MPEG hardware interface - 0:parallel 1:serial */
+	int serial_mpeg;
+
+	/* PLL interface */
+	int (*pll_rf_set) (struct dvb_frontend* fe, int index);
+	int (*pll_set)(struct dvb_frontend* fe, struct dvb_frontend_parameters* params);
 
 	/* Need to set device param for start_dma */
 	int (*set_ts_params)(struct dvb_frontend* fe, int is_punctured);
 };
 
-extern struct dvb_frontend* lgdt3302_attach(const struct lgdt3302_config* config,
+extern struct dvb_frontend* lgdt330x_attach(const struct lgdt330x_config* config,
 					    struct i2c_adapter* i2c);
 
-#endif /* LGDT3302_H */
+#endif /* LGDT330X_H */
 
 /*
  * Local variables:
diff --git a/drivers/media/dvb/frontends/lgdt3302_priv.h b/drivers/media/dvb/frontends/lgdt330x_priv.h
index 6193fa7a569..59b7c5b9012 100644
--- a/drivers/media/dvb/frontends/lgdt3302_priv.h
+++ b/drivers/media/dvb/frontends/lgdt330x_priv.h
@@ -1,7 +1,5 @@
 /*
- * $Id: lgdt3302_priv.h,v 1.2 2005/06/28 23:50:48 mkrufky Exp $
- *
- *    Support for LGDT3302 (DViCO FustionHDTV 3 Gold) - VSB/QAM
+ *    Support for LGDT3302 and LGDT3303 - VSB/QAM
  *
  *    Copyright (C) 2005 Wilson Michaels <wilsonmichaels@earthlink.net>
  *
@@ -21,8 +19,8 @@
  *
  */
 
-#ifndef _LGDT3302_PRIV_
-#define _LGDT3302_PRIV_
+#ifndef _LGDT330X_PRIV_
+#define _LGDT330X_PRIV_
 
 /* i2c control register addresses */
 enum I2C_REG {
@@ -59,11 +57,13 @@ enum I2C_REG {
 	PH_ERR1= 0x4a,
 	PH_ERR2= 0x4b,
 	DEMUX_CONTROL= 0x66,
-	PACKET_ERR_COUNTER1= 0x6a,
-	PACKET_ERR_COUNTER2= 0x6b,
+	LGDT3302_PACKET_ERR_COUNTER1= 0x6a,
+	LGDT3302_PACKET_ERR_COUNTER2= 0x6b,
+	LGDT3303_PACKET_ERR_COUNTER1= 0x8b,
+	LGDT3303_PACKET_ERR_COUNTER2= 0x8c,
 };
 
-#endif /* _LGDT3302_PRIV_ */
+#endif /* _LGDT330X_PRIV_ */
 
 /*
  * Local variables:
diff --git a/drivers/media/radio/radio-maestro.c b/drivers/media/radio/radio-maestro.c
index e62147e4ed1..e5e2021a731 100644
--- a/drivers/media/radio/radio-maestro.c
+++ b/drivers/media/radio/radio-maestro.c
@@ -154,7 +154,7 @@ static void radio_bits_set(struct radio_device *dev, __u32 data)
 	msleep(125);
 }
 
-inline static int radio_function(struct inode *inode, struct file *file,
+static inline int radio_function(struct inode *inode, struct file *file,
 				 unsigned int cmd, void *arg)
 {
 	struct video_device *dev = video_devdata(file);
@@ -283,7 +283,7 @@ static int __init maestro_radio_init(void)
 module_init(maestro_radio_init);
 module_exit(maestro_radio_exit);
 
-inline static __u16 radio_power_on(struct radio_device *dev)
+static inline __u16 radio_power_on(struct radio_device *dev)
 {
 	register __u16 io=dev->io;
 	register __u32 ofreq;
diff --git a/drivers/media/radio/radio-maxiradio.c b/drivers/media/radio/radio-maxiradio.c
index 5b748a48ce7..02d39a50d5e 100644
--- a/drivers/media/radio/radio-maxiradio.c
+++ b/drivers/media/radio/radio-maxiradio.c
@@ -166,7 +166,7 @@ static int get_tune(__u16 io)
 }
 
 
-inline static int radio_function(struct inode *inode, struct file *file,
+static inline int radio_function(struct inode *inode, struct file *file,
 				 unsigned int cmd, void *arg)
 {
 	struct video_device *dev = video_devdata(file);
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index f461750c764..ac81e5e01a9 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -236,7 +236,7 @@ config VIDEO_MEYE
 
 config VIDEO_SAA7134
 	tristate "Philips SAA7134 support"
-	depends on VIDEO_DEV && PCI && I2C
+	depends on VIDEO_DEV && PCI && I2C && SOUND
 	select VIDEO_BUF
 	select VIDEO_IR
 	select VIDEO_TUNER
@@ -331,7 +331,7 @@ config VIDEO_CX88_DVB
 	select DVB_MT352
 	select DVB_OR51132
 	select DVB_CX22702
-	select DVB_LGDT3302
+	select DVB_LGDT330X
 	---help---
 	  This adds support for DVB/ATSC cards based on the
 	  Connexant 2388x chip.
diff --git a/drivers/media/video/bttv-cards.c b/drivers/media/video/bttv-cards.c
index 2dbf5ec43ab..a97b9b958ed 100644
--- a/drivers/media/video/bttv-cards.c
+++ b/drivers/media/video/bttv-cards.c
@@ -1,5 +1,5 @@
 /*
-    $Id: bttv-cards.c,v 1.53 2005/07/05 17:37:35 nsh Exp $
+    $Id: bttv-cards.c,v 1.54 2005/07/19 18:26:46 mkrufky Exp $
 
     bttv-cards.c
 
@@ -95,7 +95,7 @@ static int __devinit pvr_boot(struct bttv *btv);
 static unsigned int triton1=0;
 static unsigned int vsfx=0;
 static unsigned int latency = UNSET;
-static unsigned int no_overlay=-1;
+int no_overlay=-1;
 
 static unsigned int card[BTTV_MAX]   = { [ 0 ... (BTTV_MAX-1) ] = UNSET };
 static unsigned int pll[BTTV_MAX]    = { [ 0 ... (BTTV_MAX-1) ] = UNSET };
@@ -2772,8 +2772,6 @@ void __devinit bttv_init_card2(struct bttv *btv)
         }
 	btv->pll.pll_current = -1;
 
-	bttv_reset_audio(btv);
-
 	/* tuner configuration (from card list / autodetect / insmod option) */
  	if (UNSET != bttv_tvcards[btv->c.type].tuner_type)
 		if(UNSET == btv->tuner_type)
@@ -4298,9 +4296,11 @@ void __devinit bttv_check_chipset(void)
 		printk(KERN_INFO "bttv: Host bridge needs VSFX enabled.\n");
 	if (pcipci_fail) {
 		printk(KERN_WARNING "bttv: BT848 and your chipset may not work together.\n");
-		if (UNSET == no_overlay) {
-			printk(KERN_WARNING "bttv: going to disable overlay.\n");
+		if (!no_overlay) {
+			printk(KERN_WARNING "bttv: overlay will be disabled.\n");
 			no_overlay = 1;
+		} else {
+			printk(KERN_WARNING "bttv: overlay forced. Use this option at your own risk.\n");
 		}
 	}
 	if (UNSET != latency)
diff --git a/drivers/media/video/bttv-driver.c b/drivers/media/video/bttv-driver.c
index 51a0f6d68e7..eee9322ce21 100644
--- a/drivers/media/video/bttv-driver.c
+++ b/drivers/media/video/bttv-driver.c
@@ -1,5 +1,5 @@
 /*
-    $Id: bttv-driver.c,v 1.42 2005/07/05 17:37:35 nsh Exp $
+    $Id: bttv-driver.c,v 1.52 2005/08/04 00:55:16 mchehab Exp $
 
     bttv - Bt848 frame grabber driver
 
@@ -80,6 +80,7 @@ static unsigned int irq_iswitch = 0;
 static unsigned int uv_ratio    = 50;
 static unsigned int full_luma_range = 0;
 static unsigned int coring      = 0;
+extern int no_overlay;
 
 /* API features (turn on/off stuff for testing) */
 static unsigned int v4l2        = 1;
@@ -2151,6 +2152,10 @@ static int bttv_s_fmt(struct bttv_fh *fh, struct bttv *btv,
 		return 0;
 	}
 	case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+		if (no_overlay > 0) {
+			printk ("V4L2_BUF_TYPE_VIDEO_OVERLAY: no_overlay\n");
+			return -EINVAL;
+		}
 		return setup_window(fh, btv, &f->fmt.win, 1);
 	case V4L2_BUF_TYPE_VBI_CAPTURE:
 		retval = bttv_switch_type(fh,f->type);
@@ -2224,9 +2229,11 @@ static int bttv_do_ioctl(struct inode *inode, struct file *file,
 			/* others */
 			cap->type = VID_TYPE_CAPTURE|
 				VID_TYPE_TUNER|
-				VID_TYPE_OVERLAY|
 				VID_TYPE_CLIPPING|
 				VID_TYPE_SCALES;
+			if (no_overlay <= 0)
+				cap->type |= VID_TYPE_OVERLAY;
+
 			cap->maxwidth  = bttv_tvnorms[btv->tvnorm].swidth;
 			cap->maxheight = bttv_tvnorms[btv->tvnorm].sheight;
 			cap->minwidth  = 48;
@@ -2302,6 +2309,11 @@ static int bttv_do_ioctl(struct inode *inode, struct file *file,
 		struct video_window *win = arg;
 		struct v4l2_window w2;
 
+		if (no_overlay > 0) {
+			printk ("VIDIOCSWIN: no_overlay\n");
+			return -EINVAL;
+		}
+
 		w2.field = V4L2_FIELD_ANY;
 		w2.w.left    = win->x;
 		w2.w.top     = win->y;
@@ -2577,10 +2589,12 @@ static int bttv_do_ioctl(struct inode *inode, struct file *file,
 		cap->version = BTTV_VERSION_CODE;
 		cap->capabilities =
 			V4L2_CAP_VIDEO_CAPTURE |
-			V4L2_CAP_VIDEO_OVERLAY |
 			V4L2_CAP_VBI_CAPTURE |
 			V4L2_CAP_READWRITE |
 			V4L2_CAP_STREAMING;
+		if (no_overlay <= 0)
+			cap->capabilities |= V4L2_CAP_VIDEO_OVERLAY;
+
 		if (bttv_tvcards[btv->c.type].tuner != UNSET &&
 		    bttv_tvcards[btv->c.type].tuner != TUNER_ABSENT)
 			cap->capabilities |= V4L2_CAP_TUNER;
@@ -3076,7 +3090,7 @@ static struct file_operations bttv_fops =
 static struct video_device bttv_video_template =
 {
 	.name     = "UNSET",
-	.type     = VID_TYPE_CAPTURE|VID_TYPE_TUNER|VID_TYPE_OVERLAY|
+	.type     = VID_TYPE_CAPTURE|VID_TYPE_TUNER|
 	            VID_TYPE_CLIPPING|VID_TYPE_SCALES,
 	.hardware = VID_HARDWARE_BT848,
 	.fops     = &bttv_fops,
@@ -3756,6 +3770,12 @@ static void bttv_unregister_video(struct bttv *btv)
 /* register video4linux devices */
 static int __devinit bttv_register_video(struct bttv *btv)
 {
+	if (no_overlay <= 0) {
+		bttv_video_template.type |= VID_TYPE_OVERLAY;
+	} else {
+		printk("bttv: Overlay support disabled.\n");
+	}
+
 	/* video */
 	btv->video_dev = vdev_init(btv, &bttv_video_template, "video");
         if (NULL == btv->video_dev)
@@ -3869,11 +3889,6 @@ static int __devinit bttv_probe(struct pci_dev *dev,
         pci_set_master(dev);
 	pci_set_command(dev);
 	pci_set_drvdata(dev,btv);
-	if (!pci_dma_supported(dev,0xffffffff)) {
-		printk("bttv%d: Oops: no 32bit PCI DMA ???\n", btv->c.nr);
-		result = -EIO;
-		goto fail1;
-	}
 
         pci_read_config_byte(dev, PCI_CLASS_REVISION, &btv->revision);
         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
diff --git a/drivers/media/video/bttv.h b/drivers/media/video/bttv.h
index 191eaf1714b..f2af9e1454f 100644
--- a/drivers/media/video/bttv.h
+++ b/drivers/media/video/bttv.h
@@ -1,5 +1,5 @@
 /*
- * $Id: bttv.h,v 1.18 2005/05/24 23:41:42 nsh Exp $
+ * $Id: bttv.h,v 1.22 2005/07/28 18:41:21 mchehab Exp $
  *
  *  bttv - Bt848 frame grabber driver
  *
@@ -135,7 +135,9 @@
 #define BTTV_DVICO_DVBT_LITE  0x80
 #define BTTV_TIBET_CS16  0x83
 #define BTTV_KODICOM_4400R  0x84
-#define BTTV_ADLINK_RTV24   0x85
+#define BTTV_ADLINK_RTV24   0x86
+#define BTTV_DVICO_FUSIONHDTV_5_LITE 0x87
+#define BTTV_ACORP_Y878F   0x88
 
 /* i2c address list */
 #define I2C_TSA5522        0xc2
diff --git a/drivers/media/video/bttvp.h b/drivers/media/video/bttvp.h
index f3293e4a15a..aab094bc243 100644
--- a/drivers/media/video/bttvp.h
+++ b/drivers/media/video/bttvp.h
@@ -1,5 +1,5 @@
 /*
-    $Id: bttvp.h,v 1.19 2005/06/16 21:38:45 nsh Exp $
+    $Id: bttvp.h,v 1.21 2005/07/15 21:44:14 mchehab Exp $
 
     bttv - Bt848 frame grabber driver
 
@@ -27,7 +27,7 @@
 #define _BTTVP_H_
 
 #include <linux/version.h>
-#define BTTV_VERSION_CODE KERNEL_VERSION(0,9,15)
+#define BTTV_VERSION_CODE KERNEL_VERSION(0,9,16)
 
 #include <linux/types.h>
 #include <linux/wait.h>
diff --git a/drivers/media/video/cx88/Makefile b/drivers/media/video/cx88/Makefile
index 606d0348da2..107e48645e3 100644
--- a/drivers/media/video/cx88/Makefile
+++ b/drivers/media/video/cx88/Makefile
@@ -9,3 +9,15 @@ obj-$(CONFIG_VIDEO_CX88_DVB) += cx88-dvb.o
 EXTRA_CFLAGS += -I$(src)/..
 EXTRA_CFLAGS += -I$(srctree)/drivers/media/dvb/dvb-core
 EXTRA_CFLAGS += -I$(srctree)/drivers/media/dvb/frontends
+ifneq ($(CONFIG_DVB_CX22702),n)
+ EXTRA_CFLAGS += -DHAVE_CX22702=1
+endif
+ifneq ($(CONFIG_DVB_OR51132),n)
+ EXTRA_CFLAGS += -DHAVE_OR51132=1
+endif
+ifneq ($(CONFIG_DVB_LGDT330X),n)
+ EXTRA_CFLAGS += -DHAVE_LGDT330X=1
+endif
+ifneq ($(CONFIG_DVB_MT352),n)
+ EXTRA_CFLAGS += -DHAVE_MT352=1
+endif
diff --git a/drivers/media/video/cx88/cx88-cards.c b/drivers/media/video/cx88/cx88-cards.c
index 3d0c784b376..ebf02a7f81e 100644
--- a/drivers/media/video/cx88/cx88-cards.c
+++ b/drivers/media/video/cx88/cx88-cards.c
@@ -1,5 +1,5 @@
 /*
- * $Id: cx88-cards.c,v 1.86 2005/07/14 03:06:43 mchehab Exp $
+ * $Id: cx88-cards.c,v 1.90 2005/07/28 02:47:42 mkrufky Exp $
  *
  * device driver for Conexant 2388x based TV cards
  * card-specific stuff.
@@ -90,6 +90,9 @@ struct cx88_board cx88_boards[] = {
 		.input          = {{
 			.type   = CX88_VMUX_TELEVISION,
 			.vmux   = 0,
+		},{
+			.type   = CX88_VMUX_SVIDEO,
+			.vmux   = 2,
 		}},
 	},
 	[CX88_BOARD_PIXELVIEW] = {
@@ -496,6 +499,9 @@ struct cx88_board cx88_boards[] = {
 		.input          = {{
                         .type   = CX88_VMUX_DVB,
                         .vmux   = 0,
+		},{
+			.type   = CX88_VMUX_SVIDEO,
+			.vmux   = 2,
                 }},
 		.dvb            = 1,
 	},
@@ -753,6 +759,27 @@ struct cx88_board cx88_boards[] = {
 		}},
 		.dvb            = 1,
 	},
+	[CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD] = {
+		.name           = "DViCO FusionHDTV 5 Gold",
+		.tuner_type     = TUNER_LG_TDVS_H062F,
+		.radio_type     = UNSET,
+		.tuner_addr	= ADDR_UNSET,
+		.radio_addr	= ADDR_UNSET,
+		/*  See DViCO FusionHDTV 3 Gold-Q for GPIO documentation.  */
+		.input          = {{
+                        .type   = CX88_VMUX_TELEVISION,
+                        .vmux   = 0,
+                        .gpio0  = 0x0f0d,
+                },{
+                        .type   = CX88_VMUX_COMPOSITE1,
+                        .vmux   = 1,
+                        .gpio0  = 0x0f00,
+                },{
+                        .type   = CX88_VMUX_SVIDEO,
+                        .vmux   = 2,
+                        .gpio0  = 0x0f00,
+                }},
+	},
 };
 const unsigned int cx88_bcount = ARRAY_SIZE(cx88_boards);
 
@@ -880,6 +907,10 @@ struct cx88_subid cx88_subids[] = {
 		.subvendor = 0x153b,
 		.subdevice = 0x1166,
 		.card      = CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1,
+ 	},{
+		.subvendor = 0x18ac,
+		.subdevice = 0xd500,
+		.card      = CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD,
 	},
 };
 const unsigned int cx88_idcount = ARRAY_SIZE(cx88_subids);
diff --git a/drivers/media/video/cx88/cx88-dvb.c b/drivers/media/video/cx88/cx88-dvb.c
index 6ad1458ab65..78d223257a6 100644
--- a/drivers/media/video/cx88/cx88-dvb.c
+++ b/drivers/media/video/cx88/cx88-dvb.c
@@ -1,5 +1,5 @@
 /*
- * $Id: cx88-dvb.c,v 1.42 2005/07/12 15:44:55 mkrufky Exp $
+ * $Id: cx88-dvb.c,v 1.58 2005/08/07 09:24:08 mkrufky Exp $
  *
  * device driver for Conexant 2388x based TV cards
  * MPEG Transport Stream (DVB) routines
@@ -29,27 +29,23 @@
 #include <linux/kthread.h>
 #include <linux/file.h>
 #include <linux/suspend.h>
-
-#define CONFIG_DVB_MT352 1
-#define CONFIG_DVB_CX22702 1
-#define CONFIG_DVB_OR51132 1
-#define CONFIG_DVB_LGDT3302 1
+#include <linux/config.h>
 
 #include "cx88.h"
 #include "dvb-pll.h"
 
-#if CONFIG_DVB_MT352
+#ifdef HAVE_MT352
 # include "mt352.h"
 # include "mt352_priv.h"
 #endif
-#if CONFIG_DVB_CX22702
+#ifdef HAVE_CX22702
 # include "cx22702.h"
 #endif
-#if CONFIG_DVB_OR51132
+#ifdef HAVE_OR51132
 # include "or51132.h"
 #endif
-#if CONFIG_DVB_LGDT3302
-# include "lgdt3302.h"
+#ifdef HAVE_LGDT330X
+# include "lgdt330x.h"
 #endif
 
 MODULE_DESCRIPTION("driver for cx2388x based DVB cards");
@@ -107,7 +103,7 @@ static struct videobuf_queue_ops dvb_qops = {
 
 /* ------------------------------------------------------------------ */
 
-#if CONFIG_DVB_MT352
+#ifdef HAVE_MT352
 static int dvico_fusionhdtv_demod_init(struct dvb_frontend* fe)
 {
 	static u8 clock_config []  = { CLOCK_CTL,  0x38, 0x39 };
@@ -177,7 +173,7 @@ static struct mt352_config dntv_live_dvbt_config = {
 };
 #endif
 
-#if CONFIG_DVB_CX22702
+#ifdef HAVE_CX22702
 static struct cx22702_config connexant_refboard_config = {
 	.demod_address = 0x43,
 	.output_mode   = CX22702_SERIAL_OUTPUT,
@@ -193,7 +189,7 @@ static struct cx22702_config hauppauge_novat_config = {
 };
 #endif
 
-#if CONFIG_DVB_OR51132
+#ifdef HAVE_OR51132
 static int or51132_set_ts_param(struct dvb_frontend* fe,
 				int is_punctured)
 {
@@ -210,8 +206,45 @@ static struct or51132_config pchdtv_hd3000 = {
 };
 #endif
 
-#if CONFIG_DVB_LGDT3302
-static int lgdt3302_set_ts_param(struct dvb_frontend* fe, int is_punctured)
+#ifdef HAVE_LGDT330X
+static int lgdt330x_pll_set(struct dvb_frontend* fe,
+			    struct dvb_frontend_parameters* params)
+{
+	struct cx8802_dev *dev= fe->dvb->priv;
+	u8 buf[4];
+	struct i2c_msg msg =
+		{ .addr = dev->core->pll_addr, .flags = 0, .buf = buf, .len = 4 };
+	int err;
+
+	dvb_pll_configure(dev->core->pll_desc, buf, params->frequency, 0);
+	dprintk(1, "%s: tuner at 0x%02x bytes: 0x%02x 0x%02x 0x%02x 0x%02x\n",
+			__FUNCTION__, msg.addr, buf[0],buf[1],buf[2],buf[3]);
+	if ((err = i2c_transfer(&dev->core->i2c_adap, &msg, 1)) != 1) {
+		printk(KERN_WARNING "cx88-dvb: %s error "
+			   "(addr %02x <- %02x, err = %i)\n",
+			   __FUNCTION__, buf[0], buf[1], err);
+		if (err < 0)
+			return err;
+		else
+			return -EREMOTEIO;
+	}
+	return 0;
+}
+
+static int lgdt330x_pll_rf_set(struct dvb_frontend* fe, int index)
+{
+	struct cx8802_dev *dev= fe->dvb->priv;
+	struct cx88_core *core = dev->core;
+
+	dprintk(1, "%s: index = %d\n", __FUNCTION__, index);
+	if (index == 0)
+		cx_clear(MO_GP0_IO, 8);
+	else
+		cx_set(MO_GP0_IO, 8);
+	return 0;
+}
+
+static int lgdt330x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
 {
 	struct cx8802_dev *dev= fe->dvb->priv;
 	if (is_punctured)
@@ -221,18 +254,12 @@ static int lgdt3302_set_ts_param(struct dvb_frontend* fe, int is_punctured)
 	return 0;
 }
 
-static struct lgdt3302_config fusionhdtv_3_gold_q = {
-	.demod_address    = 0x0e,
-	.pll_address      = 0x61,
-	.pll_desc         = &dvb_pll_microtune_4042,
-	.set_ts_params    = lgdt3302_set_ts_param,
-};
-
-static struct lgdt3302_config fusionhdtv_3_gold_t = {
+static struct lgdt330x_config fusionhdtv_3_gold = {
 	.demod_address    = 0x0e,
-	.pll_address      = 0x61,
-	.pll_desc         = &dvb_pll_thomson_dtt7611,
-	.set_ts_params    = lgdt3302_set_ts_param,
+	.demod_chip       = LGDT3302,
+	.serial_mpeg      = 0x04, /* TPSERIAL for 3302 in TOP_CONTROL */
+	.pll_set          = lgdt330x_pll_set,
+	.set_ts_params    = lgdt330x_set_ts_param,
 };
 #endif
 
@@ -244,7 +271,7 @@ static int dvb_register(struct cx8802_dev *dev)
 
 	/* init frontend */
 	switch (dev->core->board) {
-#if CONFIG_DVB_CX22702
+#ifdef HAVE_CX22702
 	case CX88_BOARD_HAUPPAUGE_DVB_T1:
 		dev->dvb.frontend = cx22702_attach(&hauppauge_novat_config,
 						   &dev->core->i2c_adap);
@@ -255,7 +282,7 @@ static int dvb_register(struct cx8802_dev *dev)
 						   &dev->core->i2c_adap);
 		break;
 #endif
-#if CONFIG_DVB_MT352
+#ifdef HAVE_MT352
 	case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1:
 		dev->core->pll_addr = 0x61;
 		dev->core->pll_desc = &dvb_pll_lg_z201;
@@ -277,13 +304,13 @@ static int dvb_register(struct cx8802_dev *dev)
 						 &dev->core->i2c_adap);
 		break;
 #endif
-#if CONFIG_DVB_OR51132
+#ifdef HAVE_OR51132
 	case CX88_BOARD_PCHDTV_HD3000:
 		dev->dvb.frontend = or51132_attach(&pchdtv_hd3000,
 						 &dev->core->i2c_adap);
 		break;
 #endif
-#if CONFIG_DVB_LGDT3302
+#ifdef HAVE_LGDT330X
 	case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:
 		dev->ts_gen_cntrl = 0x08;
 		{
@@ -292,9 +319,14 @@ static int dvb_register(struct cx8802_dev *dev)
 
 		cx_clear(MO_GP0_IO, 1);
 		mdelay(100);
-		cx_set(MO_GP0_IO, 9); // ANT connector too FIXME
+		cx_set(MO_GP0_IO, 1);
 		mdelay(200);
-		dev->dvb.frontend = lgdt3302_attach(&fusionhdtv_3_gold_q,
+
+		/* Select RF connector callback */
+		fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set;
+		dev->core->pll_addr = 0x61;
+		dev->core->pll_desc = &dvb_pll_microtune_4042;
+		dev->dvb.frontend = lgdt330x_attach(&fusionhdtv_3_gold,
 						    &dev->core->i2c_adap);
 		}
 		break;
@@ -306,9 +338,11 @@ static int dvb_register(struct cx8802_dev *dev)
 
 		cx_clear(MO_GP0_IO, 1);
 		mdelay(100);
-		cx_set(MO_GP0_IO, 9); /* ANT connector too FIXME */
+		cx_set(MO_GP0_IO, 9);
 		mdelay(200);
-		dev->dvb.frontend = lgdt3302_attach(&fusionhdtv_3_gold_t,
+		dev->core->pll_addr = 0x61;
+		dev->core->pll_desc = &dvb_pll_thomson_dtt7611;
+		dev->dvb.frontend = lgdt330x_attach(&fusionhdtv_3_gold,
 						    &dev->core->i2c_adap);
 		}
 		break;
diff --git a/drivers/media/video/cx88/cx88-i2c.c b/drivers/media/video/cx88/cx88-i2c.c
index 8403c4e9505..a628a55299c 100644
--- a/drivers/media/video/cx88/cx88-i2c.c
+++ b/drivers/media/video/cx88/cx88-i2c.c
@@ -1,5 +1,5 @@
 /*
-    $Id: cx88-i2c.c,v 1.28 2005/07/05 17:37:35 nsh Exp $
+    $Id: cx88-i2c.c,v 1.30 2005/07/25 05:10:13 mkrufky Exp $
 
     cx88-i2c.c  --  all the i2c code is here
 
@@ -164,7 +164,7 @@ static struct i2c_client cx8800_i2c_client_template = {
 };
 
 static char *i2c_devs[128] = {
-	[ 0x1c >> 1 ] = "lgdt3302",
+	[ 0x1c >> 1 ] = "lgdt330x",
 	[ 0x86 >> 1 ] = "tda9887/cx22702",
 	[ 0xa0 >> 1 ] = "eeprom",
 	[ 0xc0 >> 1 ] = "tuner (analog)",
diff --git a/drivers/media/video/cx88/cx88-video.c b/drivers/media/video/cx88/cx88-video.c
index 5588a3aeecb..5f58c103198 100644
--- a/drivers/media/video/cx88/cx88-video.c
+++ b/drivers/media/video/cx88/cx88-video.c
@@ -1,5 +1,5 @@
 /*
- * $Id: cx88-video.c,v 1.80 2005/07/13 08:49:08 mchehab Exp $
+ * $Id: cx88-video.c,v 1.82 2005/07/22 05:13:34 mkrufky Exp $
  *
  * device driver for Conexant 2388x based TV cards
  * video4linux video interface
@@ -758,10 +758,10 @@ static int video_open(struct inode *inode, struct file *file)
 		struct cx88_core *core = dev->core;
 		int board = core->board;
 		dprintk(1,"video_open: setting radio device\n");
+		cx_write(MO_GP3_IO, cx88_boards[board].radio.gpio3);
 		cx_write(MO_GP0_IO, cx88_boards[board].radio.gpio0);
 		cx_write(MO_GP1_IO, cx88_boards[board].radio.gpio1);
 		cx_write(MO_GP2_IO, cx88_boards[board].radio.gpio2);
-		cx_write(MO_GP3_IO, cx88_boards[board].radio.gpio3);
 		dev->core->tvaudio = WW_FM;
 		cx88_set_tvaudio(core);
 		cx88_set_stereo(core,V4L2_TUNER_MODE_STEREO,1);
diff --git a/drivers/media/video/cx88/cx88.h b/drivers/media/video/cx88/cx88.h
index b008f7db6df..da65dc92787 100644
--- a/drivers/media/video/cx88/cx88.h
+++ b/drivers/media/video/cx88/cx88.h
@@ -1,5 +1,5 @@
 /*
- * $Id: cx88.h,v 1.69 2005/07/13 17:25:25 mchehab Exp $
+ * $Id: cx88.h,v 1.70 2005/07/24 17:44:09 mkrufky Exp $
  *
  * v4l2 device driver for cx2388x based TV cards
  *
@@ -171,6 +171,7 @@ extern struct sram_channel cx88_sram_channels[];
 #define CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T  28
 #define CX88_BOARD_ADSTECH_DVB_T_PCI          29
 #define CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1  30
+#define CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD 31
 
 enum cx88_itype {
 	CX88_VMUX_COMPOSITE1 = 1,
diff --git a/drivers/media/video/msp3400.c b/drivers/media/video/msp3400.c
index 6239254db27..62f1b8ddb98 100644
--- a/drivers/media/video/msp3400.c
+++ b/drivers/media/video/msp3400.c
@@ -741,11 +741,9 @@ static int msp34xx_sleep(struct msp3400c *msp, int timeout)
 			schedule_timeout(msecs_to_jiffies(timeout));
 		}
 	}
-	if (current->flags & PF_FREEZE) {
-		refrigerator ();
-	}
 
 	remove_wait_queue(&msp->wq, &wait);
+	try_to_freeze();
 	return msp->restart;
 }
 
diff --git a/drivers/media/video/mxb.c b/drivers/media/video/mxb.c
index 486234d41b5..d04793fb80f 100644
--- a/drivers/media/video/mxb.c
+++ b/drivers/media/video/mxb.c
@@ -142,8 +142,8 @@ struct mxb
 
 	int	cur_mode;	/* current audio mode (mono, stereo, ...) */
 	int	cur_input;	/* current input */
-	int	cur_freq;	/* current frequency the tuner is tuned to */
 	int	cur_mute;	/* current mute status */
+	struct v4l2_frequency	cur_freq;	/* current frequency the tuner is tuned to */
 };
 
 static struct saa7146_extension extension;
@@ -352,9 +352,15 @@ static int mxb_init_done(struct saa7146_dev* dev)
 	/* select a tuner type */
 	tun_setup.mode_mask = T_ANALOG_TV;
 	tun_setup.addr = ADDR_UNSET;
-	tun_setup.type = 5;
+	tun_setup.type = TUNER_PHILIPS_PAL;
 	mxb->tuner->driver->command(mxb->tuner,TUNER_SET_TYPE_ADDR, &tun_setup);
-	
+	/* tune in some frequency on tuner */
+	mxb->cur_freq.tuner = 0;
+	mxb->cur_freq.type = V4L2_TUNER_ANALOG_TV;
+	mxb->cur_freq.frequency = freq;
+	mxb->tuner->driver->command(mxb->tuner, VIDIOC_S_FREQUENCY,
+					&mxb->cur_freq);
+
 	/* mute audio on tea6420s */
 	mxb->tea6420_1->driver->command(mxb->tea6420_1,TEA6420_SWITCH, &TEA6420_line[6][0]);
 	mxb->tea6420_2->driver->command(mxb->tea6420_2,TEA6420_SWITCH, &TEA6420_line[6][1]);
@@ -371,12 +377,8 @@ static int mxb_init_done(struct saa7146_dev* dev)
 	vm.out = 13;
 	mxb->tea6415c->driver->command(mxb->tea6415c,TEA6415C_SWITCH, &vm);
 				
-	/* tune in some frequency on tuner */
-	mxb->tuner->driver->command(mxb->tuner, VIDIOCSFREQ, &freq);
-
 	/* the rest for mxb */
 	mxb->cur_input = 0;
-	mxb->cur_freq = freq;
 	mxb->cur_mute = 1;
 
 	mxb->cur_mode = V4L2_TUNER_MODE_STEREO;
@@ -819,18 +821,14 @@ static int mxb_ioctl(struct saa7146_fh *fh, unsigned int cmd, void *arg)
 			return -EINVAL;
 		}
 
-		memset(f,0,sizeof(*f));
-		f->type = V4L2_TUNER_ANALOG_TV;
-		f->frequency =  mxb->cur_freq;
+		*f = mxb->cur_freq;
 
-		DEB_EE(("VIDIOC_G_FREQ: freq:0x%08x.\n", mxb->cur_freq));
+		DEB_EE(("VIDIOC_G_FREQ: freq:0x%08x.\n", mxb->cur_freq.frequency));
 		return 0;
 	}
 	case VIDIOC_S_FREQUENCY:
 	{
 		struct v4l2_frequency *f = arg;
-		int t_locked = 0;
-		int v_byte = 0;
 
 		if (0 != f->tuner)
 			return -EINVAL;
@@ -843,20 +841,11 @@ static int mxb_ioctl(struct saa7146_fh *fh, unsigned int cmd, void *arg)
 			return -EINVAL;
 		}
 
-		DEB_EE(("VIDIOC_S_FREQUENCY: freq:0x%08x.\n",f->frequency));
-
-		mxb->cur_freq = f->frequency;
+		mxb->cur_freq = *f;
+		DEB_EE(("VIDIOC_S_FREQUENCY: freq:0x%08x.\n", mxb->cur_freq.frequency));
 
 		/* tune in desired frequency */			
-		mxb->tuner->driver->command(mxb->tuner, VIDIOCSFREQ, &mxb->cur_freq);
-
-		/* check if pll of tuner & saa7111a is locked */
-//		mxb->tuner->driver->command(mxb->tuner,TUNER_IS_LOCKED, &t_locked);
-		mxb->saa7111a->driver->command(mxb->saa7111a,DECODER_GET_STATUS, &v_byte);
-
-		/* not locked -- anything to do here ? */
-		if( 0 == t_locked || 0 == (v_byte & DECODER_STATUS_GOOD)) {
-		}
+		mxb->tuner->driver->command(mxb->tuner, VIDIOC_S_FREQUENCY, &mxb->cur_freq);
 
 		/* hack: changing the frequency should invalidate the vbi-counter (=> alevt) */
 		spin_lock(&dev->slock);
diff --git a/drivers/media/video/saa7134/Makefile b/drivers/media/video/saa7134/Makefile
index e577a06b136..b778ffd94e6 100644
--- a/drivers/media/video/saa7134/Makefile
+++ b/drivers/media/video/saa7134/Makefile
@@ -9,3 +9,9 @@ obj-$(CONFIG_VIDEO_SAA7134_DVB) += saa7134-dvb.o
 EXTRA_CFLAGS += -I$(src)/..
 EXTRA_CFLAGS += -I$(srctree)/drivers/media/dvb/dvb-core
 EXTRA_CFLAGS += -I$(srctree)/drivers/media/dvb/frontends
+ifneq ($(CONFIG_DVB_MT352),n)
+ EXTRA_CFLAGS += -DHAVE_MT352=1
+endif
+ifneq ($(CONFIG_DVB_TDA1004X),n)
+ EXTRA_CFLAGS += -DHAVE_TDA1004X=1
+endif
diff --git a/drivers/media/video/saa7134/saa7134-dvb.c b/drivers/media/video/saa7134/saa7134-dvb.c
index 334bc185009..8be6a90358c 100644
--- a/drivers/media/video/saa7134/saa7134-dvb.c
+++ b/drivers/media/video/saa7134/saa7134-dvb.c
@@ -1,5 +1,5 @@
 /*
- * $Id: saa7134-dvb.c,v 1.18 2005/07/04 16:05:50 mkrufky Exp $
+ * $Id: saa7134-dvb.c,v 1.23 2005/07/24 22:12:47 mkrufky Exp $
  *
  * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
  *
@@ -29,18 +29,17 @@
 #include <linux/delay.h>
 #include <linux/kthread.h>
 #include <linux/suspend.h>
+#include <linux/config.h>
 
-#define CONFIG_DVB_MT352 1
-#define CONFIG_DVB_TDA1004X 1
 
 #include "saa7134-reg.h"
 #include "saa7134.h"
 
-#if CONFIG_DVB_MT352
+#ifdef HAVE_MT352
 # include "mt352.h"
 # include "mt352_priv.h" /* FIXME */
 #endif
-#if CONFIG_DVB_TDA1004X
+#ifdef HAVE_TDA1004X
 # include "tda1004x.h"
 #endif
 
@@ -54,7 +53,7 @@ MODULE_PARM_DESC(antenna_pwr,"enable antenna power (Pinnacle 300i)");
 
 /* ------------------------------------------------------------------ */
 
-#if CONFIG_DVB_MT352
+#ifdef HAVE_MT352
 static int pinnacle_antenna_pwr(struct saa7134_dev *dev, int on)
 {
 	u32 ok;
@@ -153,7 +152,7 @@ static struct mt352_config pinnacle_300i = {
 
 /* ------------------------------------------------------------------ */
 
-#if CONFIG_DVB_TDA1004X
+#ifdef HAVE_TDA1004X
 static int philips_tu1216_pll_init(struct dvb_frontend *fe)
 {
 	struct saa7134_dev *dev = fe->dvb->priv;
@@ -385,7 +384,7 @@ static int philips_fmd1216_pll_set(struct dvb_frontend *fe, struct dvb_frontend_
 	return 0;
 }
 
-
+#ifdef HAVE_TDA1004X
 static struct tda1004x_config medion_cardbus = {
 	.demod_address = 0x08,
 	.invert        = 1,
@@ -398,6 +397,7 @@ static struct tda1004x_config medion_cardbus = {
 	.pll_sleep	   = philips_fmd1216_analog,
 	.request_firmware = NULL,
 };
+#endif
 
 /* ------------------------------------------------------------------ */
 
@@ -547,14 +547,14 @@ static int dvb_init(struct saa7134_dev *dev)
 			    dev);
 
 	switch (dev->board) {
-#if CONFIG_DVB_MT352
+#ifdef HAVE_MT352
 	case SAA7134_BOARD_PINNACLE_300I_DVBT_PAL:
 		printk("%s: pinnacle 300i dvb setup\n",dev->name);
 		dev->dvb.frontend = mt352_attach(&pinnacle_300i,
 						 &dev->i2c_adap);
 		break;
 #endif
-#if CONFIG_DVB_TDA1004X
+#ifdef HAVE_TDA1004X
 	case SAA7134_BOARD_MD7134:
 		dev->dvb.frontend = tda10046_attach(&medion_cardbus,
 						    &dev->i2c_adap);
diff --git a/drivers/media/video/saa7134/saa7134-i2c.c b/drivers/media/video/saa7134/saa7134-i2c.c
index 93dd6197854..1203b93a572 100644
--- a/drivers/media/video/saa7134/saa7134-i2c.c
+++ b/drivers/media/video/saa7134/saa7134-i2c.c
@@ -1,5 +1,5 @@
 /*
- * $Id: saa7134-i2c.c,v 1.19 2005/07/07 01:49:30 mkrufky Exp $
+ * $Id: saa7134-i2c.c,v 1.22 2005/07/22 04:09:41 mkrufky Exp $
  *
  * device driver for philips saa7134 based TV cards
  * i2c interface support
@@ -300,6 +300,8 @@ static int saa7134_i2c_xfer(struct i2c_adapter *i2c_adap,
   	status = i2c_get_status(dev);
 	if (i2c_is_error(status))
 		goto err;
+	/* ensure that the bus is idle for at least one bit slot */
+	msleep(1);
 
 	d1printk("\n");
 	return num;
diff --git a/drivers/media/video/saa7134/saa7134.h b/drivers/media/video/saa7134/saa7134.h
index 6836c07794f..2af0cb2a731 100644
--- a/drivers/media/video/saa7134/saa7134.h
+++ b/drivers/media/video/saa7134/saa7134.h
@@ -1,5 +1,5 @@
 /*
- * $Id: saa7134.h,v 1.48 2005/07/01 08:22:24 nsh Exp $
+ * $Id: saa7134.h,v 1.49 2005/07/13 17:25:25 mchehab Exp $
  *
  * v4l2 device driver for philips saa7134 based TV cards
  *
@@ -21,7 +21,7 @@
  */
 
 #include <linux/version.h>
-#define SAA7134_VERSION_CODE KERNEL_VERSION(0,2,13)
+#define SAA7134_VERSION_CODE KERNEL_VERSION(0,2,14)
 
 #include <linux/pci.h>
 #include <linux/i2c.h>
diff --git a/drivers/media/video/tea5767.c b/drivers/media/video/tea5767.c
index 4d27ac1b7fb..cebcc1fa68d 100644
--- a/drivers/media/video/tea5767.c
+++ b/drivers/media/video/tea5767.c
@@ -2,7 +2,7 @@
  * For Philips TEA5767 FM Chip used on some TV Cards like Prolink Pixelview
  * I2C address is allways 0xC0.
  *
- * $Id: tea5767.c,v 1.21 2005/07/14 03:06:43 mchehab Exp $
+ * $Id: tea5767.c,v 1.27 2005/07/31 12:10:56 mchehab Exp $
  *
  * Copyright (c) 2005 Mauro Carvalho Chehab (mchehab@brturbo.com.br)
  * This code is placed under the terms of the GNU General Public License
@@ -15,7 +15,6 @@
 #include <linux/videodev.h>
 #include <linux/delay.h>
 #include <media/tuner.h>
-#include <media/tuner.h>
 
 #define PREFIX "TEA5767 "
 
@@ -293,16 +292,16 @@ static int tea5767_stereo(struct i2c_client *c)
 
 int tea5767_autodetection(struct i2c_client *c)
 {
-	unsigned char buffer[5] = { 0xff, 0xff, 0xff, 0xff, 0xff };
+	unsigned char buffer[7] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 	int rc;
 	struct tuner *t = i2c_get_clientdata(c);
 
-	if (5 != (rc = i2c_master_recv(c, buffer, 5))) {
+	if (7 != (rc = i2c_master_recv(c, buffer, 7))) {
 		tuner_warn("It is not a TEA5767. Received %i bytes.\n", rc);
 		return EINVAL;
 	}
 
-	/* If all bytes are the same then it's a TV tuner and not a tea5767 chip. */
+	/* If all bytes are the same then it's a TV tuner and not a tea5767 */
 	if (buffer[0] == buffer[1] && buffer[0] == buffer[2] &&
 	    buffer[0] == buffer[3] && buffer[0] == buffer[4]) {
 		tuner_warn("All bytes are equal. It is not a TEA5767\n");
@@ -318,6 +317,17 @@ int tea5767_autodetection(struct i2c_client *c)
 		tuner_warn("Chip ID is not zero. It is not a TEA5767\n");
 		return EINVAL;
 	}
+	/* It seems that tea5767 returns 0xff after the 5th byte */
+	if ((buffer[5] != 0xff) || (buffer[6] != 0xff)) {
+		tuner_warn("Returned more than 5 bytes. It is not a TEA5767\n");
+		return EINVAL;
+	}
+
+	/* It seems that tea5767 returns 0xff after the 5th byte */
+	if ((buffer[5] != 0xff) || (buffer[6] != 0xff)) {
+		tuner_warn("Returned more than 5 bytes. It is not a TEA5767\n");
+		return EINVAL;
+	}
 
 	tuner_warn("TEA5767 detected.\n");
 	return 0;
@@ -327,10 +337,8 @@ int tea5767_tuner_init(struct i2c_client *c)
 {
 	struct tuner *t = i2c_get_clientdata(c);
 
-	if (tea5767_autodetection(c) == EINVAL)
-		return EINVAL;
-
-	tuner_info("type set to %d (%s)\n", t->type, "Philips TEA5767HN FM Radio");
+	tuner_info("type set to %d (%s)\n", t->type,
+			"Philips TEA5767HN FM Radio");
 	strlcpy(c->name, "tea5767", sizeof(c->name));
 
 	t->tv_freq = set_tv_freq;
diff --git a/drivers/media/video/tuner-core.c b/drivers/media/video/tuner-core.c
index b25a9c08ac0..f0a579827a2 100644
--- a/drivers/media/video/tuner-core.c
+++ b/drivers/media/video/tuner-core.c
@@ -1,5 +1,5 @@
 /*
- * $Id: tuner-core.c,v 1.58 2005/07/14 03:06:43 mchehab Exp $
+ * $Id: tuner-core.c,v 1.63 2005/07/28 18:19:55 mchehab Exp $
  *
  * i2c tv tuner chip device driver
  * core core, i.e. kernel interfaces, registering and so on
@@ -23,6 +23,8 @@
 #include <media/tuner.h>
 #include <media/audiochip.h>
 
+#include "msp3400.h"
+
 #define UNSET (-1U)
 
 /* standard i2c insmod options */
@@ -42,6 +44,9 @@ module_param(addr, int, 0444);
 static unsigned int no_autodetect = 0;
 module_param(no_autodetect, int, 0444);
 
+static unsigned int show_i2c = 0;
+module_param(show_i2c, int, 0444);
+
 /* insmod options used at runtime => read/write */
 unsigned int tuner_debug = 0;
 module_param(tuner_debug, int, 0644);
@@ -320,6 +325,17 @@ static int tuner_attach(struct i2c_adapter *adap, int addr, int kind)
 
 	tuner_info("chip found @ 0x%x (%s)\n", addr << 1, adap->name);
 
+	if (show_i2c) {
+		unsigned char buffer[16];
+		int i,rc;
+
+		memset(buffer, 0, sizeof(buffer));
+		rc = i2c_master_recv(&t->i2c, buffer, sizeof(buffer));
+		printk("tuner-%04x I2C RECV = ",addr);
+		for (i=0;i<rc;i++)
+			printk("%02x ",buffer[i]);
+		printk("\n");
+	}
 	/* TEA5767 autodetection code - only for addr = 0xc0 */
 	if (!no_autodetect) {
 		if (addr == 0x60) {
@@ -451,6 +467,17 @@ static int tuner_command(struct i2c_client *client, unsigned int cmd, void *arg)
 			break;
 		}
 		break;
+	case VIDIOCSAUDIO:
+		if (check_mode(t, "VIDIOCSAUDIO") == EINVAL)
+			return 0;
+		if (check_v4l2(t) == EINVAL)
+			return 0;
+
+		/* Should be implemented, since bttv calls it */
+		tuner_dbg("VIDIOCSAUDIO not implemented.\n");
+
+		break;
+	case MSP_SET_MATRIX:
 	case TDA9887_SET_CONFIG:
 		break;
 	/* --- v4l ioctls --- */
diff --git a/drivers/media/video/tuner-simple.c b/drivers/media/video/tuner-simple.c
index a3f8e83f531..de0c93aeb75 100644
--- a/drivers/media/video/tuner-simple.c
+++ b/drivers/media/video/tuner-simple.c
@@ -1,5 +1,5 @@
 /*
- * $Id: tuner-simple.c,v 1.39 2005/07/07 01:49:30 mkrufky Exp $
+ * $Id: tuner-simple.c,v 1.43 2005/07/28 18:41:21 mchehab Exp $
  *
  * i2c tv tuner chip device driver
  * controls all those simple 4-control-bytes style tuners.
@@ -245,6 +245,12 @@ static struct tunertype tuners[] = {
           /* see tea5767.c for details */},
 	{ "Philips FMD1216ME MK3 Hybrid Tuner", Philips, PAL,
 	  16*160.00,16*442.00,0x51,0x52,0x54,0x86,623 },
+
+	{ "LG TDVS-H062F/TUA6034", LGINNOTEK, NTSC,
+	  16*160.00,16*455.00,0x01,0x02,0x04,0x8e,732},
+
+	{ "Ymec TVF66T5-B/DFF", Philips, PAL,
+          16*160.25,16*464.25,0x01,0x02,0x08,0x8e,623},
 };
 
 unsigned const int tuner_count = ARRAY_SIZE(tuners);
diff --git a/drivers/media/video/tvaudio.c b/drivers/media/video/tvaudio.c
index d8b78f1d686..f42a1efa8fc 100644
--- a/drivers/media/video/tvaudio.c
+++ b/drivers/media/video/tvaudio.c
@@ -285,6 +285,7 @@ static int chip_thread(void *data)
 			schedule();
 		}
 		remove_wait_queue(&chip->wq, &wait);
+		try_to_freeze();
 		if (chip->done || signal_pending(current))
 			break;
 		dprintk("%s: thread wakeup\n", i2c_clientname(&chip->c));
diff --git a/drivers/media/video/tveeprom.c b/drivers/media/video/tveeprom.c
index e8d9440977c..127ec38ebd6 100644
--- a/drivers/media/video/tveeprom.c
+++ b/drivers/media/video/tveeprom.c
@@ -189,7 +189,7 @@ hauppauge_tuner[] =
 	{ TUNER_ABSENT,        "Philips FQ1236 MK3"},
 	{ TUNER_ABSENT,        "Samsung TCPN 2121P30A"},
 	{ TUNER_ABSENT,        "Samsung TCPE 4121P30A"},
-	{ TUNER_ABSENT,        "TCL MFPE05 2"},
+	{ TUNER_PHILIPS_FM1216ME_MK3, "TCL MFPE05 2"},
 	/* 90-99 */
 	{ TUNER_ABSENT,        "LG TALN H202T"},
 	{ TUNER_PHILIPS_FQ1216AME_MK4, "Philips FQ1216AME MK4"},
@@ -445,6 +445,7 @@ int tveeprom_read(struct i2c_client *c, unsigned char *eedata, int len)
 }
 EXPORT_SYMBOL(tveeprom_read);
 
+#if 0
 int tveeprom_dump(unsigned char *eedata, int len)
 {
 	int i;
@@ -460,6 +461,7 @@ int tveeprom_dump(unsigned char *eedata, int len)
 	return 0;
 }
 EXPORT_SYMBOL(tveeprom_dump);
+#endif  /*  0  */
 
 /* ----------------------------------------------------------------------- */
 /* needed for ivtv.sf.net at the moment.  Should go away in the long       */
@@ -477,7 +479,7 @@ static unsigned short normal_i2c[] = {
 
 I2C_CLIENT_INSMOD;
 
-struct i2c_driver i2c_driver_tveeprom;
+static struct i2c_driver i2c_driver_tveeprom;
 
 static int
 tveeprom_command(struct i2c_client *client,
@@ -549,7 +551,7 @@ tveeprom_detach_client (struct i2c_client *client)
 	return 0;
 }
 
-struct i2c_driver i2c_driver_tveeprom = {
+static struct i2c_driver i2c_driver_tveeprom = {
 	.owner          = THIS_MODULE,
 	.name           = "tveeprom",
 	.id             = I2C_DRIVERID_TVEEPROM,
diff --git a/drivers/mmc/wbsd.c b/drivers/mmc/wbsd.c
index 0c41d4b41a6..8b487ed1069 100644
--- a/drivers/mmc/wbsd.c
+++ b/drivers/mmc/wbsd.c
@@ -1053,7 +1053,7 @@ static void wbsd_detect_card(unsigned long data)
  * Tasklets
  */
 
-inline static struct mmc_data* wbsd_get_data(struct wbsd_host* host)
+static inline struct mmc_data* wbsd_get_data(struct wbsd_host* host)
 {
 	WARN_ON(!host->mrq);
 	if (!host->mrq)
diff --git a/drivers/mtd/devices/docecc.c b/drivers/mtd/devices/docecc.c
index 933877ff4d8..9a087c1fb0b 100644
--- a/drivers/mtd/devices/docecc.c
+++ b/drivers/mtd/devices/docecc.c
@@ -40,6 +40,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/doc2000.h>
 
+#define DEBUG 0
 /* need to undef it (from asm/termbits.h) */
 #undef B0
 
diff --git a/drivers/net/3c505.c b/drivers/net/3c505.c
index ad17f17e8e7..111601ca4ca 100644
--- a/drivers/net/3c505.c
+++ b/drivers/net/3c505.c
@@ -272,7 +272,7 @@ static inline void set_hsf(struct net_device *dev, int hsf)
 
 static int start_receive(struct net_device *, pcb_struct *);
 
-inline static void adapter_reset(struct net_device *dev)
+static inline void adapter_reset(struct net_device *dev)
 {
 	unsigned long timeout;
 	elp_device *adapter = dev->priv;
diff --git a/drivers/net/8139too.c b/drivers/net/8139too.c
index 5a4a08a7c95..4c2cf7bbd25 100644
--- a/drivers/net/8139too.c
+++ b/drivers/net/8139too.c
@@ -126,14 +126,14 @@
 #define USE_IO_OPS 1
 #endif
 
-/* define to 1 to enable copious debugging info */
-#undef RTL8139_DEBUG
+/* define to 1, 2 or 3 to enable copious debugging info */
+#define RTL8139_DEBUG 0
 
 /* define to 1 to disable lightweight runtime debugging checks */
 #undef RTL8139_NDEBUG
 
 
-#ifdef RTL8139_DEBUG
+#if RTL8139_DEBUG
 /* note: prints function name for you */
 #  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
 #else
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 534b598866b..8a835eb5880 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -23,9 +23,12 @@ config NETDEVICES
 
 	  If unsure, say Y.
 
+# All the following symbols are dependent on NETDEVICES - do not repeat
+# that for each of the symbols.
+if NETDEVICES
+
 config DUMMY
 	tristate "Dummy net driver support"
-	depends on NETDEVICES
 	---help---
 	  This is essentially a bit-bucket device (i.e. traffic you send to
 	  this device is consigned into oblivion) with a configurable IP
@@ -45,7 +48,6 @@ config DUMMY
 
 config BONDING
 	tristate "Bonding driver support"
-	depends on NETDEVICES
 	depends on INET
 	---help---
 	  Say 'Y' or 'M' if you wish to be able to 'bond' multiple Ethernet
@@ -63,7 +65,6 @@ config BONDING
 
 config EQUALIZER
 	tristate "EQL (serial line load balancing) support"
-	depends on NETDEVICES
 	---help---
 	  If you have two serial connections to some other computer (this
 	  usually requires two modems and two telephone lines) and you use
@@ -83,7 +84,6 @@ config EQUALIZER
 
 config TUN
 	tristate "Universal TUN/TAP device driver support"
-	depends on NETDEVICES
 	select CRC32
 	---help---
 	  TUN/TAP provides packet reception and transmission for user space
@@ -107,7 +107,7 @@ config TUN
 
 config NET_SB1000
 	tristate "General Instruments Surfboard 1000"
-	depends on NETDEVICES && PNP
+	depends on PNP
 	---help---
 	  This is a driver for the General Instrument (also known as
 	  NextLevel) SURFboard 1000 internal
@@ -129,16 +129,14 @@ config NET_SB1000
 
 	  If you don't have this card, of course say N.
 
-if NETDEVICES
 	source "drivers/net/arcnet/Kconfig"
-endif
 
 #
 #	Ethernet
 #
 
 menu "Ethernet (10 or 100Mbit)"
-	depends on NETDEVICES && !UML
+	depends on !UML
 
 config NET_ETHERNET
 	bool "Ethernet (10 or 100Mbit)"
@@ -1137,7 +1135,7 @@ config IBMLANA
 
 config IBMVETH
 	tristate "IBM LAN Virtual Ethernet support"
-	depends on NETDEVICES && NET_ETHERNET && PPC_PSERIES
+	depends on NET_ETHERNET && PPC_PSERIES
 	---help---
 	  This driver supports virtual ethernet adapters on newer IBM iSeries
 	  and pSeries systems.
@@ -1760,7 +1758,7 @@ endmenu
 #
 
 menu "Ethernet (1000 Mbit)"
-	depends on NETDEVICES && !UML
+	depends on !UML
 
 config ACENIC
 	tristate "Alteon AceNIC/3Com 3C985/NetGear GA620 Gigabit support"
@@ -2091,7 +2089,7 @@ endmenu
 #
 
 menu "Ethernet (10000 Mbit)"
-	depends on NETDEVICES && !UML
+	depends on !UML
 
 config IXGB
 	tristate "Intel(R) PRO/10GbE support"
@@ -2186,11 +2184,11 @@ source "drivers/s390/net/Kconfig"
 
 config ISERIES_VETH
 	tristate "iSeries Virtual Ethernet driver support"
-	depends on NETDEVICES && PPC_ISERIES
+	depends on PPC_ISERIES
 
 config FDDI
 	bool "FDDI driver support"
-	depends on NETDEVICES && (PCI || EISA)
+	depends on (PCI || EISA)
 	help
 	  Fiber Distributed Data Interface is a high speed local area network
 	  design; essentially a replacement for high speed Ethernet. FDDI can
@@ -2239,7 +2237,7 @@ config SKFP
 
 config HIPPI
 	bool "HIPPI driver support (EXPERIMENTAL)"
-	depends on NETDEVICES && EXPERIMENTAL && INET && PCI
+	depends on EXPERIMENTAL && INET && PCI
 	help
 	  HIgh Performance Parallel Interface (HIPPI) is a 800Mbit/sec and
 	  1600Mbit/sec dual-simplex switched or point-to-point network. HIPPI
@@ -2271,7 +2269,7 @@ config ROADRUNNER_LARGE_RINGS
 
 config PLIP
 	tristate "PLIP (parallel port) support"
-	depends on NETDEVICES && PARPORT
+	depends on PARPORT
 	---help---
 	  PLIP (Parallel Line Internet Protocol) is used to create a
 	  reasonably fast mini network consisting of two (or, rarely, more)
@@ -2307,7 +2305,6 @@ config PLIP
 
 config PPP
 	tristate "PPP (point-to-point protocol) support"
-	depends on NETDEVICES
 	---help---
 	  PPP (Point to Point Protocol) is a newer and better SLIP.  It serves
 	  the same purpose: sending Internet traffic over telephone (and other
@@ -2443,7 +2440,6 @@ config PPPOATM
 
 config SLIP
 	tristate "SLIP (serial line) support"
-	depends on NETDEVICES
 	---help---
 	  Say Y if you intend to use SLIP or CSLIP (compressed SLIP) to
 	  connect to your Internet service provider or to connect to some
@@ -2510,7 +2506,7 @@ config SLIP_MODE_SLIP6
 
 config NET_FC
 	bool "Fibre Channel driver support"
-	depends on NETDEVICES && SCSI && PCI
+	depends on SCSI && PCI
 	help
 	  Fibre Channel is a high speed serial protocol mainly used to connect
 	  large storage devices to the computer; it is compatible with and
@@ -2523,7 +2519,7 @@ config NET_FC
 
 config SHAPER
 	tristate "Traffic Shaper (EXPERIMENTAL)"
-	depends on NETDEVICES && EXPERIMENTAL
+	depends on EXPERIMENTAL
 	---help---
 	  The traffic shaper is a virtual network device that allows you to
 	  limit the rate of outgoing data flow over some other network device.
@@ -2544,11 +2540,13 @@ config SHAPER
 
 config NETCONSOLE
 	tristate "Network console logging support (EXPERIMENTAL)"
-	depends on NETDEVICES && INET && EXPERIMENTAL
+	depends on EXPERIMENTAL
 	---help---
 	If you want to log kernel messages over the network, enable this.
 	See <file:Documentation/networking/netconsole.txt> for details.
 
+endif #NETDEVICES
+
 config NETPOLL
 	def_bool NETCONSOLE
 
diff --git a/drivers/net/amd8111e.c b/drivers/net/amd8111e.c
index 8618012df06..d9ba8be72af 100755
--- a/drivers/net/amd8111e.c
+++ b/drivers/net/amd8111e.c
@@ -1290,7 +1290,7 @@ static irqreturn_t amd8111e_interrupt(int irq, void *dev_id, struct pt_regs *reg
 	writel(intr0, mmio + INT0);
 
 	/* Check if Receive Interrupt has occurred. */
-#if CONFIG_AMD8111E_NAPI
+#ifdef CONFIG_AMD8111E_NAPI
 	if(intr0 & RINT0){
 		if(netif_rx_schedule_prep(dev)){
 			/* Disable receive interupts */
diff --git a/drivers/net/cs89x0.c b/drivers/net/cs89x0.c
index b96d6fb1929..b780307093e 100644
--- a/drivers/net/cs89x0.c
+++ b/drivers/net/cs89x0.c
@@ -417,6 +417,7 @@ cs89x0_probe1(struct net_device *dev, int ioaddr, int modular)
 	struct net_local *lp = netdev_priv(dev);
 	static unsigned version_printed;
 	int i;
+	int tmp;
 	unsigned rev_type = 0;
 	int eeprom_buff[CHKSUM_LEN];
 	int retval;
@@ -492,14 +493,17 @@ cs89x0_probe1(struct net_device *dev, int ioaddr, int modular)
 				goto out2;
 			}
 	}
-printk("PP_addr=0x%x\n", inw(ioaddr + ADD_PORT));
+	printk(KERN_DEBUG "PP_addr at %x: 0x%x\n",
+			ioaddr + ADD_PORT, inw(ioaddr + ADD_PORT));
 
 	ioaddr &= ~3;
 	outw(PP_ChipID, ioaddr + ADD_PORT);
 
-	if (inw(ioaddr + DATA_PORT) != CHIP_EISA_ID_SIG) {
-		printk(KERN_ERR "%s: incorrect signature 0x%x\n",
-			dev->name, inw(ioaddr + DATA_PORT));
+	tmp = inw(ioaddr + DATA_PORT);
+	if (tmp != CHIP_EISA_ID_SIG) {
+		printk(KERN_DEBUG "%s: incorrect signature at %x: 0x%x!="
+			CHIP_EISA_ID_SIG_STR "\n",
+			dev->name, ioaddr + DATA_PORT, tmp);
   		retval = -ENODEV;
   		goto out2;
 	}
@@ -1450,6 +1454,7 @@ static int net_send_packet(struct sk_buff *skb, struct net_device *dev)
 	/* Write the contents of the packet */
 	outsw(dev->base_addr + TX_FRAME_PORT,skb->data,(skb->len+1) >>1);
 	spin_unlock_irq(&lp->lock);
+	lp->stats.tx_bytes += skb->len;
 	dev->trans_start = jiffies;
 	dev_kfree_skb (skb);
 
diff --git a/drivers/net/cs89x0.h b/drivers/net/cs89x0.h
index bd3ad8e6cce..decea264f12 100644
--- a/drivers/net/cs89x0.h
+++ b/drivers/net/cs89x0.h
@@ -93,6 +93,7 @@
 #endif
 
 #define CHIP_EISA_ID_SIG 0x630E   /*  Product ID Code for Crystal Chip (CS8900 spec 4.3) */
+#define CHIP_EISA_ID_SIG_STR "0x630E"
 
 #ifdef IBMEIPKT
 #define EISA_ID_SIG 0x4D24	/*  IBM */
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index cb7f051a60a..5e5d2c3c7ce 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -162,7 +162,6 @@ static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
 static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
 static void e1000_restore_vlan(struct e1000_adapter *adapter);
 
-static int e1000_notify_reboot(struct notifier_block *, unsigned long event, void *ptr);
 static int e1000_suspend(struct pci_dev *pdev, uint32_t state);
 #ifdef CONFIG_PM
 static int e1000_resume(struct pci_dev *pdev);
@@ -173,12 +172,6 @@ static int e1000_resume(struct pci_dev *pdev);
 static void e1000_netpoll (struct net_device *netdev);
 #endif
 
-struct notifier_block e1000_notifier_reboot = {
-	.notifier_call	= e1000_notify_reboot,
-	.next		= NULL,
-	.priority	= 0
-};
-
 /* Exported from other modules */
 
 extern void e1000_check_options(struct e1000_adapter *adapter);
@@ -221,9 +214,7 @@ e1000_init_module(void)
 	printk(KERN_INFO "%s\n", e1000_copyright);
 
 	ret = pci_module_init(&e1000_driver);
-	if(ret >= 0) {
-		register_reboot_notifier(&e1000_notifier_reboot);
-	}
+
 	return ret;
 }
 
@@ -239,7 +230,6 @@ module_init(e1000_init_module);
 static void __exit
 e1000_exit_module(void)
 {
-	unregister_reboot_notifier(&e1000_notifier_reboot);
 	pci_unregister_driver(&e1000_driver);
 }
 
@@ -3652,23 +3642,6 @@ e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
 }
 
 static int
-e1000_notify_reboot(struct notifier_block *nb, unsigned long event, void *p)
-{
-	struct pci_dev *pdev = NULL;
-
-	switch(event) {
-	case SYS_DOWN:
-	case SYS_HALT:
-	case SYS_POWER_OFF:
-		while((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev))) {
-			if(pci_dev_driver(pdev) == &e1000_driver)
-				e1000_suspend(pdev, 3);
-		}
-	}
-	return NOTIFY_DONE;
-}
-
-static int
 e1000_suspend(struct pci_dev *pdev, uint32_t state)
 {
 	struct net_device *netdev = pci_get_drvdata(pdev);
diff --git a/drivers/net/hamradio/Kconfig b/drivers/net/hamradio/Kconfig
index 7cdebe1a0b6..0cd54306e63 100644
--- a/drivers/net/hamradio/Kconfig
+++ b/drivers/net/hamradio/Kconfig
@@ -17,7 +17,7 @@ config MKISS
 
 config 6PACK
 	tristate "Serial port 6PACK driver"
-	depends on AX25 && BROKEN_ON_SMP
+	depends on AX25
 	---help---
 	  6pack is a transmission protocol for the data exchange between your
 	  PC and your TNC (the Terminal Node Controller acts as a kind of
diff --git a/drivers/net/ne.c b/drivers/net/ne.c
index 6c57096aa2e..d209a1556b2 100644
--- a/drivers/net/ne.c
+++ b/drivers/net/ne.c
@@ -129,9 +129,9 @@ bad_clone_list[] __initdata = {
 #define NESM_START_PG	0x40	/* First page of TX buffer */
 #define NESM_STOP_PG	0x80	/* Last page +1 of RX ring */
 
-#ifdef CONFIG_PLAT_MAPPI
+#if defined(CONFIG_PLAT_MAPPI)
 #  define DCR_VAL 0x4b
-#elif CONFIG_PLAT_OAKS32R
+#elif defined(CONFIG_PLAT_OAKS32R)
 #  define DCR_VAL 0x48
 #else
 #  define DCR_VAL 0x49
diff --git a/drivers/net/pcmcia/nmclan_cs.c b/drivers/net/pcmcia/nmclan_cs.c
index dbb941004ae..980d7e5d66c 100644
--- a/drivers/net/pcmcia/nmclan_cs.c
+++ b/drivers/net/pcmcia/nmclan_cs.c
@@ -1671,7 +1671,7 @@ static void set_multicast_list(struct net_device *dev)
 
 static struct pcmcia_device_id nmclan_ids[] = {
 	PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
-	PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet", 0x0ebf1d60, 0x00b2e941),
+	PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
 	PCMCIA_DEVICE_NULL,
 };
 MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
diff --git a/drivers/net/pcmcia/pcnet_cs.c b/drivers/net/pcmcia/pcnet_cs.c
index e1664aef3df..9f22d138e3a 100644
--- a/drivers/net/pcmcia/pcnet_cs.c
+++ b/drivers/net/pcmcia/pcnet_cs.c
@@ -1639,7 +1639,7 @@ static struct pcmcia_device_id pcnet_ids[] = {
 	PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x0143, 0xc0ab),
 	PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x021b, 0x0101),
 	PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x08a1, 0xc0ab),
-	PCMCIA_PFC_DEVICE_PROD_ID12(0, "AnyCom", "Fast Ethernet ", 0x578ba6e7, 0x02d92d1e),
+	PCMCIA_PFC_DEVICE_PROD_ID12(0, "AnyCom", "Fast Ethernet + 56K COMBO", 0x578ba6e7, 0xb0ac62c4),
 	PCMCIA_PFC_DEVICE_PROD_ID12(0, "D-Link", "DME336T", 0x1a424a1c, 0xb23897ff),
 	PCMCIA_PFC_DEVICE_PROD_ID12(0, "Grey Cell", "GCS3000", 0x2a151fac, 0x48b932ae),
 	PCMCIA_PFC_DEVICE_PROD_ID12(0, "Linksys", "EtherFast 10&100 + 56K PC Card (PCMLM56)", 0x0733cc81, 0xb3765033),
@@ -1683,7 +1683,6 @@ static struct pcmcia_device_id pcnet_ids[] = {
 	PCMCIA_DEVICE_PROD_ID12("ACCTON", "EN2212", 0xdfc6b5b2, 0xcb112a11),
 	PCMCIA_DEVICE_PROD_ID12("ACCTON", "EN2216-PCMCIA-ETHERNET", 0xdfc6b5b2, 0x5542bfff),
 	PCMCIA_DEVICE_PROD_ID12("Allied Telesis, K.K.", "CentreCOM LA100-PCM-T V2 100/10M LAN PC Card", 0xbb7fbdd7, 0xcd91cc68),
-	PCMCIA_DEVICE_PROD_ID12("Allied Telesis, K.K.", "CentreCOM LA-PCM", 0xbb7fbdd7, 0x5ba10d49),
 	PCMCIA_DEVICE_PROD_ID12("Allied Telesis K.K.", "LA100-PCM V2", 0x36634a66, 0xc6d05997),
   	PCMCIA_DEVICE_PROD_ID12("Allied Telesis, K.K.", "CentreCOM LA-PCM_V2", 0xbb7fBdd7, 0x28e299f8),
 	PCMCIA_DEVICE_PROD_ID12("Allied Telesis K.K.", "LA-PCM V3", 0x36634a66, 0x62241d96),
@@ -1719,6 +1718,7 @@ static struct pcmcia_device_id pcnet_ids[] = {
 	PCMCIA_DEVICE_PROD_ID12("DIGITAL", "DEPCM-XX", 0x69616cb3, 0xe600e76e),
 	PCMCIA_DEVICE_PROD_ID12("D-Link", "DE-650", 0x1a424a1c, 0xf28c8398),
 	PCMCIA_DEVICE_PROD_ID12("D-Link", "DE-660", 0x1a424a1c, 0xd9a1d05b),
+	PCMCIA_DEVICE_PROD_ID12("D-Link", "DE-660+", 0x1a424a1c, 0x50dcd0ec),
 	PCMCIA_DEVICE_PROD_ID12("D-Link", "DFE-650", 0x1a424a1c, 0x0f0073f9),
 	PCMCIA_DEVICE_PROD_ID12("Dual Speed", "10/100 PC Card", 0x725b842d, 0xf1efee84),
 	PCMCIA_DEVICE_PROD_ID12("Dual Speed", "10/100 Port Attached PC Card", 0x725b842d, 0x2db1f8e9),
@@ -1737,6 +1737,7 @@ static struct pcmcia_device_id pcnet_ids[] = {
 	PCMCIA_DEVICE_PROD_ID12("GVC", "NIC-2000p", 0x76e171bd, 0x6eb1c947),
 	PCMCIA_DEVICE_PROD_ID12("IBM Corp.", "Ethernet", 0xe3736c88, 0x00b2e941),
 	PCMCIA_DEVICE_PROD_ID12("IC-CARD", "IC-CARD", 0x60cb09a6, 0x60cb09a6),
+	PCMCIA_DEVICE_PROD_ID12("IC-CARD+", "IC-CARD+", 0x93693494, 0x93693494),
 	PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCETTX", 0x547e66dc, 0x6fc5459b),
 	PCMCIA_DEVICE_PROD_ID12("iPort", "10/100 Ethernet Card", 0x56c538d2, 0x11b0ffc0),
 	PCMCIA_DEVICE_PROD_ID12("KANSAI ELECTRIC CO.,LTD", "KLA-PCM/T", 0xb18dc3b4, 0xcc51a956),
@@ -1753,7 +1754,7 @@ static struct pcmcia_device_id pcnet_ids[] = {
 	PCMCIA_DEVICE_PROD_ID12("Linksys", "EtherFast 10/100 Integrated PC Card (PCM100)", 0x0733cc81, 0x453c3f9d),
 	PCMCIA_DEVICE_PROD_ID12("Linksys", "EtherFast 10/100 PC Card (PCMPC100)", 0x0733cc81, 0x66c5a389),
 	PCMCIA_DEVICE_PROD_ID12("Linksys", "EtherFast 10/100 PC Card (PCMPC100 V2)", 0x0733cc81, 0x3a3b28e9),
-	PCMCIA_DEVICE_PROD_ID12("Linksys", "HomeLink Phoneline ", 0x0733cc81, 0x5e07cfa0),
+	PCMCIA_DEVICE_PROD_ID12("Linksys", "HomeLink Phoneline + 10/100 Network PC Card (PCM100H1)", 0x733cc81, 0x7a3e5c3a),
 	PCMCIA_DEVICE_PROD_ID12("Logitec", "LPM-LN100TX", 0x88fcdeda, 0x6d772737),
 	PCMCIA_DEVICE_PROD_ID12("Logitec", "LPM-LN20T", 0x88fcdeda, 0x81090922),
 	PCMCIA_DEVICE_PROD_ID12("LONGSHINE", "PCMCIA Ethernet Card", 0xf866b0b0, 0x6f6652e0),
diff --git a/drivers/net/pcmcia/smc91c92_cs.c b/drivers/net/pcmcia/smc91c92_cs.c
index 0d8bb4cccbb..d652e1eddb4 100644
--- a/drivers/net/pcmcia/smc91c92_cs.c
+++ b/drivers/net/pcmcia/smc91c92_cs.c
@@ -2332,8 +2332,8 @@ static struct pcmcia_device_id smc91c92_ids[] = {
 	PCMCIA_PFC_DEVICE_PROD_ID123(0, "MEGAHERTZ", "XJEM1144/CCEM1144", "PCMCIA MODEM", 0xf510db04, 0x52d21e1e, 0xbd6c43ef),
 	PCMCIA_PFC_DEVICE_PROD_ID12(0, "Gateway 2000", "XJEM3336", 0xdd9989be, 0x662c394c),
 	PCMCIA_PFC_DEVICE_PROD_ID12(0, "MEGAHERTZ", "XJEM1144/CCEM1144", 0xf510db04, 0x52d21e1e),
-	PCMCIA_PFC_DEVICE_PROD_ID12(0, "Ositech", "Trumpcard", 0x0c2f80cd, 0x0573c29f),
-	PCMCIA_PFC_DEVICE_PROD_ID12(0, "Ositech", "Trumpcard", 0x0c2f80cd, 0x0573c29f),
+	PCMCIA_PFC_DEVICE_PROD_ID12(0, "Ositech", "Trumpcard:Jack of Diamonds Modem+Ethernet", 0xc2f80cd, 0x656947b9),
+	PCMCIA_PFC_DEVICE_PROD_ID12(0, "Ositech", "Trumpcard:Jack of Hearts Modem+Ethernet", 0xc2f80cd, 0xdc9ba5ed),
 	PCMCIA_MFC_DEVICE_MANF_CARD(0, 0x016c, 0x0020),
 	PCMCIA_DEVICE_MANF_CARD(0x016c, 0x0023),
 	PCMCIA_DEVICE_PROD_ID123("BASICS by New Media Corporation", "Ethernet", "SMC91C94", 0x23c78a9d, 0x00b2e941, 0xcef397fb),
@@ -2343,8 +2343,8 @@ static struct pcmcia_device_id smc91c92_ids[] = {
 	PCMCIA_DEVICE_PROD_ID12("Farallon", "Farallon Enet", 0x58d93fc4, 0x244734e9),
 	PCMCIA_DEVICE_PROD_ID12("Megahertz", "CC10BT/2", 0x33234748, 0x3c95b953),
 	PCMCIA_DEVICE_PROD_ID12("MELCO/SMC", "LPC-TX", 0xa2cd8e6d, 0x42da662a),
-	PCMCIA_DEVICE_PROD_ID12("Ositech", "Trumpcard", 0x0c2f80cd, 0x0573c29f),
-	PCMCIA_DEVICE_PROD_ID12("Ositech", "Trumpcard", 0x0c2f80cd, 0x0573c29f),
+	PCMCIA_DEVICE_PROD_ID12("Ositech", "Trumpcard:Four of Diamonds Ethernet", 0xc2f80cd, 0xb3466314),
+	PCMCIA_DEVICE_PROD_ID12("Ositech", "Trumpcard:Seven of Diamonds Ethernet", 0xc2f80cd, 0x194b650a),
 	PCMCIA_DEVICE_PROD_ID12("PCMCIA", "Fast Ethernet PCCard", 0x281f1c5d, 0xdcea68bc),
 	PCMCIA_DEVICE_PROD_ID12("Psion", "10Mb Ethernet", 0x4ef00b21, 0x844be9e9),
 	PCMCIA_DEVICE_PROD_ID12("SMC", "EtherEZ Ethernet 8020", 0xc4f8b18b, 0x4a0eeb2d),
diff --git a/drivers/net/pcmcia/xirc2ps_cs.c b/drivers/net/pcmcia/xirc2ps_cs.c
index 9f33bad174e..ce143f08638 100644
--- a/drivers/net/pcmcia/xirc2ps_cs.c
+++ b/drivers/net/pcmcia/xirc2ps_cs.c
@@ -1985,7 +1985,7 @@ static struct pcmcia_device_id xirc2ps_ids[] = {
 	PCMCIA_PFC_DEVICE_PROD_ID13(0, "Xircom", "CEM56", 0x2e3ee845, 0xa650c32a),
 	PCMCIA_PFC_DEVICE_PROD_ID13(0, "Xircom", "REM10", 0x2e3ee845, 0x76df1d29),
 	PCMCIA_PFC_DEVICE_PROD_ID13(0, "Xircom", "XEM5600", 0x2e3ee845, 0xf1403719),
-	PCMCIA_PFC_DEVICE_PROD_ID12(0, "Xircom", "CreditCard Ethernet", 0x2e3ee845, 0xc0e778c2),
+	PCMCIA_PFC_DEVICE_PROD_ID12(0, "Xircom", "CreditCard Ethernet+Modem II", 0x2e3ee845, 0xeca401bf),
 	PCMCIA_DEVICE_MANF_CARD(0x01bf, 0x010a),
 	PCMCIA_DEVICE_PROD_ID13("Toshiba Information Systems", "TPCENET", 0x1b3b94fe, 0xf381c1a2),
 	PCMCIA_DEVICE_PROD_ID13("Xircom", "CE3-10/100", 0x2e3ee845, 0x0ec0ac37),
diff --git a/drivers/net/plip.c b/drivers/net/plip.c
index 21537ee3a6a..1bd22cd40c7 100644
--- a/drivers/net/plip.c
+++ b/drivers/net/plip.c
@@ -160,7 +160,7 @@ static struct net_device_stats *plip_get_stats(struct net_device *dev);
 static int plip_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
 static int plip_preempt(void *handle);
 static void plip_wakeup(void *handle);
-
+
 enum plip_connection_state {
 	PLIP_CN_NONE=0,
 	PLIP_CN_RECEIVE,
@@ -231,8 +231,8 @@ struct net_local {
 	atomic_t kill_timer;
 	struct semaphore killed_timer_sem;
 };
-
-inline static void enable_parport_interrupts (struct net_device *dev)
+
+static inline void enable_parport_interrupts (struct net_device *dev)
 {
 	if (dev->irq != -1)
 	{
@@ -242,7 +242,7 @@ inline static void enable_parport_interrupts (struct net_device *dev)
 	}
 }
 
-inline static void disable_parport_interrupts (struct net_device *dev)
+static inline void disable_parport_interrupts (struct net_device *dev)
 {
 	if (dev->irq != -1)
 	{
@@ -252,7 +252,7 @@ inline static void disable_parport_interrupts (struct net_device *dev)
 	}
 }
 
-inline static void write_data (struct net_device *dev, unsigned char data)
+static inline void write_data (struct net_device *dev, unsigned char data)
 {
 	struct parport *port =
 	   ((struct net_local *)dev->priv)->pardev->port;
@@ -260,14 +260,14 @@ inline static void write_data (struct net_device *dev, unsigned char data)
 	port->ops->write_data (port, data);
 }
 
-inline static unsigned char read_status (struct net_device *dev)
+static inline unsigned char read_status (struct net_device *dev)
 {
 	struct parport *port =
 	   ((struct net_local *)dev->priv)->pardev->port;
 
 	return port->ops->read_status (port);
 }
-
+
 /* Entry point of PLIP driver.
    Probe the hardware, and register/initialize the driver.
 
@@ -316,7 +316,7 @@ plip_init_netdev(struct net_device *dev)
 
 	spin_lock_init(&nl->lock);
 }
-
+
 /* Bottom half handler for the delayed request.
    This routine is kicked by do_timer().
    Request `plip_bh' to be invoked. */
@@ -471,7 +471,7 @@ plip_bh_timeout_error(struct net_device *dev, struct net_local *nl,
 
 	return TIMEOUT;
 }
-
+
 static int
 plip_none(struct net_device *dev, struct net_local *nl,
 	  struct plip_local *snd, struct plip_local *rcv)
@@ -481,7 +481,7 @@ plip_none(struct net_device *dev, struct net_local *nl,
 
 /* PLIP_RECEIVE --- receive a byte(two nibbles)
    Returns OK on success, TIMEOUT on timeout */
-inline static int
+static inline int
 plip_receive(unsigned short nibble_timeout, struct net_device *dev,
 	     enum plip_nibble_state *ns_p, unsigned char *data_p)
 {
@@ -582,7 +582,6 @@ static __be16 plip_type_trans(struct sk_buff *skb, struct net_device *dev)
 	return htons(ETH_P_802_2);
 }
 
-
 /* PLIP_RECEIVE_PACKET --- receive a packet */
 static int
 plip_receive_packet(struct net_device *dev, struct net_local *nl,
@@ -702,7 +701,7 @@ plip_receive_packet(struct net_device *dev, struct net_local *nl,
 
 /* PLIP_SEND --- send a byte (two nibbles)
    Returns OK on success, TIMEOUT when timeout    */
-inline static int
+static inline int
 plip_send(unsigned short nibble_timeout, struct net_device *dev,
 	  enum plip_nibble_state *ns_p, unsigned char data)
 {
@@ -902,7 +901,7 @@ plip_error(struct net_device *dev, struct net_local *nl,
 
 	return OK;
 }
-
+
 /* Handle the parallel port interrupts. */
 static void
 plip_interrupt(int irq, void *dev_id, struct pt_regs * regs)
@@ -957,7 +956,7 @@ plip_interrupt(int irq, void *dev_id, struct pt_regs * regs)
 
 	spin_unlock_irq(&nl->lock);
 }
-
+
 static int
 plip_tx_packet(struct sk_buff *skb, struct net_device *dev)
 {
@@ -1238,7 +1237,7 @@ plip_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 	}
 	return 0;
 }
-
+
 static int parport[PLIP_MAX] = { [0 ... PLIP_MAX-1] = -1 };
 static int timid;
 
diff --git a/drivers/net/sk98lin/skge.c b/drivers/net/sk98lin/skge.c
index 82570ec44d8..6ee4771addf 100644
--- a/drivers/net/sk98lin/skge.c
+++ b/drivers/net/sk98lin/skge.c
@@ -5133,6 +5133,84 @@ static void __devexit skge_remove_one(struct pci_dev *pdev)
 	kfree(pAC);
 }
 
+#ifdef CONFIG_PM
+static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+	struct net_device *dev = pci_get_drvdata(pdev);
+	DEV_NET *pNet = netdev_priv(dev);
+	SK_AC *pAC = pNet->pAC;
+	struct net_device *otherdev = pAC->dev[1];
+
+	if (netif_running(dev)) {
+		netif_carrier_off(dev);
+		DoPrintInterfaceChange = SK_FALSE;
+		SkDrvDeInitAdapter(pAC, 0);  /* performs SkGeClose */
+		netif_device_detach(dev);
+	}
+	if (otherdev != dev) {
+		if (netif_running(otherdev)) {
+			netif_carrier_off(otherdev);
+			DoPrintInterfaceChange = SK_FALSE;
+			SkDrvDeInitAdapter(pAC, 1);  /* performs SkGeClose */
+			netif_device_detach(otherdev);
+		}
+	}
+
+	pci_save_state(pdev);
+	pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
+	if (pAC->AllocFlag & SK_ALLOC_IRQ) {
+		free_irq(dev->irq, dev);
+	}
+	pci_disable_device(pdev);
+	pci_set_power_state(pdev, pci_choose_state(pdev, state));
+
+	return 0;
+}
+
+static int skge_resume(struct pci_dev *pdev)
+{
+	struct net_device *dev = pci_get_drvdata(pdev);
+	DEV_NET *pNet = netdev_priv(dev);
+	SK_AC *pAC = pNet->pAC;
+	struct net_device *otherdev = pAC->dev[1];
+	int ret;
+
+	pci_set_power_state(pdev, PCI_D0);
+	pci_restore_state(pdev);
+	pci_enable_device(pdev);
+	pci_set_master(pdev);
+	if (pAC->GIni.GIMacsFound == 2)
+		ret = request_irq(dev->irq, SkGeIsr, SA_SHIRQ, pAC->Name, dev);
+	else
+		ret = request_irq(dev->irq, SkGeIsrOnePort, SA_SHIRQ, pAC->Name, dev);
+	if (ret) {
+		printk(KERN_WARNING "sk98lin: unable to acquire IRQ %d\n", dev->irq);
+		pAC->AllocFlag &= ~SK_ALLOC_IRQ;
+		dev->irq = 0;
+		pci_disable_device(pdev);
+		return -EBUSY;
+	}
+
+	netif_device_attach(dev);
+	if (netif_running(dev)) {
+		DoPrintInterfaceChange = SK_FALSE;
+		SkDrvInitAdapter(pAC, 0);    /* first device  */
+	}
+	if (otherdev != dev) {
+		netif_device_attach(otherdev);
+		if (netif_running(otherdev)) {
+			DoPrintInterfaceChange = SK_FALSE;
+			SkDrvInitAdapter(pAC, 1);    /* second device  */
+		}
+	}
+
+	return 0;
+}
+#else
+#define skge_suspend NULL
+#define skge_resume NULL
+#endif
+
 static struct pci_device_id skge_pci_tbl[] = {
 	{ PCI_VENDOR_ID_3COM, 0x1700, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 	{ PCI_VENDOR_ID_3COM, 0x80eb, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
@@ -5158,6 +5236,8 @@ static struct pci_driver skge_driver = {
 	.id_table	= skge_pci_tbl,
 	.probe		= skge_probe_one,
 	.remove		= __devexit_p(skge_remove_one),
+	.suspend	= skge_suspend,
+	.resume		= skge_resume,
 };
 
 static int __init skge_init(void)
diff --git a/drivers/net/sk98lin/skgeinit.c b/drivers/net/sk98lin/skgeinit.c
index df4483429a7..6cb49dd0225 100644
--- a/drivers/net/sk98lin/skgeinit.c
+++ b/drivers/net/sk98lin/skgeinit.c
@@ -2016,7 +2016,7 @@ SK_IOC	IoC)		/* IO context */
 	 * we set the PHY to coma mode and switch to D3 power state.
 	 */
 	if (pAC->GIni.GIYukonLite &&
-		pAC->GIni.GIChipRev == CHIP_REV_YU_LITE_A3) {
+		pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
 
 		/* for all ports switch PHY to coma mode */
 		for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
diff --git a/drivers/net/sk98lin/skxmac2.c b/drivers/net/sk98lin/skxmac2.c
index 94a09deecb3..42d2d963150 100644
--- a/drivers/net/sk98lin/skxmac2.c
+++ b/drivers/net/sk98lin/skxmac2.c
@@ -1065,7 +1065,7 @@ int		Port)	/* Port Index (MAC_1 + n) */
 	
 	/* WA code for COMA mode */
 	if (pAC->GIni.GIYukonLite &&
-		pAC->GIni.GIChipRev == CHIP_REV_YU_LITE_A3) {
+		pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
 		
 		SK_IN32(IoC, B2_GP_IO, &DWord);
 
@@ -1110,7 +1110,7 @@ int		Port)	/* Port Index (MAC_1 + n) */
 
 	/* WA code for COMA mode */
 	if (pAC->GIni.GIYukonLite &&
-		pAC->GIni.GIChipRev == CHIP_REV_YU_LITE_A3) {
+		pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
 		
 		SK_IN32(IoC, B2_GP_IO, &DWord);
 
@@ -2126,7 +2126,7 @@ SK_U8	Mode)		/* low power mode */
 	int		Ret = 0;
 
 	if (pAC->GIni.GIYukonLite &&
-	    pAC->GIni.GIChipRev == CHIP_REV_YU_LITE_A3) {
+	    pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
 
 		/* save current power mode */
 		LastMode = pAC->GIni.GP[Port].PPhyPowerState;
@@ -2253,7 +2253,7 @@ int		Port)		/* Port Index (e.g. MAC_1) */
 	int		Ret = 0;
 
 	if (pAC->GIni.GIYukonLite &&
-		pAC->GIni.GIChipRev == CHIP_REV_YU_LITE_A3) {
+		pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
 
 		/* save current power mode */
 		LastMode = pAC->GIni.GP[Port].PPhyPowerState;
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index 5cacc7ad9e7..f15739481d6 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -42,7 +42,7 @@
 #include "skge.h"
 
 #define DRV_NAME		"skge"
-#define DRV_VERSION		"0.7"
+#define DRV_VERSION		"0.8"
 #define PFX			DRV_NAME " "
 
 #define DEFAULT_TX_RING_SIZE	128
@@ -55,7 +55,7 @@
 #define ETH_JUMBO_MTU		9000
 #define TX_WATCHDOG		(5 * HZ)
 #define NAPI_WEIGHT		64
-#define BLINK_HZ		(HZ/4)
+#define BLINK_MS		250
 
 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
@@ -75,7 +75,6 @@ static const struct pci_device_id skge_id_table[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
-	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx  */
 	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
@@ -249,7 +248,7 @@ static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
 	} else {
 		u32 setting;
 
-		switch(ecmd->speed) {
+		switch (ecmd->speed) {
 		case SPEED_1000:
 			if (ecmd->duplex == DUPLEX_FULL)
 				setting = SUPPORTED_1000baseT_Full;
@@ -620,84 +619,98 @@ static int skge_set_coalesce(struct net_device *dev,
 	return 0;
 }
 
-static void skge_led_on(struct skge_hw *hw, int port)
+enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
+static void skge_led(struct skge_port *skge, enum led_mode mode)
 {
+	struct skge_hw *hw = skge->hw;
+	int port = skge->port;
+
+	spin_lock_bh(&hw->phy_lock);
 	if (hw->chip_id == CHIP_ID_GENESIS) {
-		skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
-		skge_write8(hw, B0_LED, LED_STAT_ON);
+		switch (mode) {
+		case LED_MODE_OFF:
+			xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
+			skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
+			skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
+			skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
+			break;
 
-		skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
-		skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
-		skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
+		case LED_MODE_ON:
+			skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
+			skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
 
-		/* For Broadcom Phy only */
-		xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
-	} else {
-		gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
-		gm_phy_write(hw, port, PHY_MARV_LED_OVER,
-				  PHY_M_LED_MO_DUP(MO_LED_ON)  |
-				  PHY_M_LED_MO_10(MO_LED_ON)   |
-				  PHY_M_LED_MO_100(MO_LED_ON)  |
-				  PHY_M_LED_MO_1000(MO_LED_ON) |
-				  PHY_M_LED_MO_RX(MO_LED_ON));
-	}
-}
+			skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
+			skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
 
-static void skge_led_off(struct skge_hw *hw, int port)
-{
-	if (hw->chip_id == CHIP_ID_GENESIS) {
-		skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
-		skge_write8(hw, B0_LED, LED_STAT_OFF);
+			break;
 
-		skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
-		skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
+		case LED_MODE_TST:
+			skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
+			skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
+			skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
 
-		/* Broadcom only */
-		xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
+			xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
+			break;
+		}
 	} else {
-		gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
-		gm_phy_write(hw, port, PHY_MARV_LED_OVER,
-				  PHY_M_LED_MO_DUP(MO_LED_OFF)  |
-				  PHY_M_LED_MO_10(MO_LED_OFF)   |
-				  PHY_M_LED_MO_100(MO_LED_OFF)  |
-				  PHY_M_LED_MO_1000(MO_LED_OFF) |
-				  PHY_M_LED_MO_RX(MO_LED_OFF));
+		switch (mode) {
+		case LED_MODE_OFF:
+			gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
+			gm_phy_write(hw, port, PHY_MARV_LED_OVER,
+				     PHY_M_LED_MO_DUP(MO_LED_OFF)  |
+				     PHY_M_LED_MO_10(MO_LED_OFF)   |
+				     PHY_M_LED_MO_100(MO_LED_OFF)  |
+				     PHY_M_LED_MO_1000(MO_LED_OFF) |
+				     PHY_M_LED_MO_RX(MO_LED_OFF));
+			break;
+		case LED_MODE_ON:
+			gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
+				     PHY_M_LED_PULS_DUR(PULS_170MS) |
+				     PHY_M_LED_BLINK_RT(BLINK_84MS) |
+				     PHY_M_LEDC_TX_CTRL |
+				     PHY_M_LEDC_DP_CTRL);
+		
+			gm_phy_write(hw, port, PHY_MARV_LED_OVER,
+				     PHY_M_LED_MO_RX(MO_LED_OFF) |
+				     (skge->speed == SPEED_100 ?
+				      PHY_M_LED_MO_100(MO_LED_ON) : 0));
+			break;
+		case LED_MODE_TST:
+			gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
+			gm_phy_write(hw, port, PHY_MARV_LED_OVER,
+				     PHY_M_LED_MO_DUP(MO_LED_ON)  |
+				     PHY_M_LED_MO_10(MO_LED_ON)   |
+				     PHY_M_LED_MO_100(MO_LED_ON)  |
+				     PHY_M_LED_MO_1000(MO_LED_ON) |
+				     PHY_M_LED_MO_RX(MO_LED_ON));
+		}
 	}
-}
-
-static void skge_blink_timer(unsigned long data)
-{
-	struct skge_port *skge = (struct skge_port *) data;
-	struct skge_hw *hw = skge->hw;
-	unsigned long flags;
-
-	spin_lock_irqsave(&hw->phy_lock, flags);
-	if (skge->blink_on)
-		skge_led_on(hw, skge->port);
-	else
-		skge_led_off(hw, skge->port);
-	spin_unlock_irqrestore(&hw->phy_lock, flags);
-
-	skge->blink_on = !skge->blink_on;
-	mod_timer(&skge->led_blink, jiffies + BLINK_HZ);
+	spin_unlock_bh(&hw->phy_lock);
 }
 
 /* blink LED's for finding board */
 static int skge_phys_id(struct net_device *dev, u32 data)
 {
 	struct skge_port *skge = netdev_priv(dev);
+	unsigned long ms;
+	enum led_mode mode = LED_MODE_TST;
 
 	if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
-		data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
+		ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
+	else
+		ms = data * 1000;
 
-	/* start blinking */
-	skge->blink_on = 1;
-	mod_timer(&skge->led_blink, jiffies+1);
+	while (ms > 0) {
+		skge_led(skge, mode);
+		mode ^= LED_MODE_TST;
 
-	msleep_interruptible(data * 1000);
-	del_timer_sync(&skge->led_blink);
+		if (msleep_interruptible(BLINK_MS))
+			break;
+		ms -= BLINK_MS;
+	}
 
-	skge_led_off(skge->hw, skge->port);
+	/* back to regular LED state */
+	skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
 
 	return 0;
 }
@@ -1028,7 +1041,7 @@ static void bcom_check_link(struct skge_hw *hw, int port)
 			}
 
 			/* Check Duplex mismatch */
-			switch(aux & PHY_B_AS_AN_RES_MSK) {
+			switch (aux & PHY_B_AS_AN_RES_MSK) {
 			case PHY_B_RES_1000FD:
 				skge->duplex = DUPLEX_FULL;
 				break;
@@ -1099,7 +1112,7 @@ static void bcom_phy_init(struct skge_port *skge, int jumbo)
 	r |=  XM_MMU_NO_PRE;
 	xm_write16(hw, port, XM_MMU_CMD,r);
 
-	switch(id1) {
+	switch (id1) {
 	case PHY_BCOM_ID1_C0:
 		/*
 		 * Workaround BCOM Errata for the C0 type.
@@ -1194,13 +1207,6 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
 	xm_write16(hw, port, XM_STAT_CMD,
 			XM_SC_CLR_RXC | XM_SC_CLR_TXC);
 
-	/* initialize Rx, Tx and Link LED */
-	skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
-	skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
-
-	skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
-	skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
-
 	/* Unreset the XMAC. */
 	skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
 
@@ -1209,7 +1215,6 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
 	 * namely for the 1000baseTX cards that use the XMAC's
 	 * GMII mode.
 	 */
-	spin_lock_bh(&hw->phy_lock);
 	/* Take external Phy out of reset */
 	r = skge_read32(hw, B2_GP_IO);
 	if (port == 0)
@@ -1219,7 +1224,6 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
 
 	skge_write32(hw, B2_GP_IO, r);
 	skge_read32(hw, B2_GP_IO);
-	spin_unlock_bh(&hw->phy_lock);
 
 	/* Enable GMII interfac */
 	xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
@@ -1569,7 +1573,6 @@ static void yukon_init(struct skge_hw *hw, int port)
 {
 	struct skge_port *skge = netdev_priv(hw->dev[port]);
 	u16 ctrl, ct1000, adv;
-	u16 ledctrl, ledover;
 
 	pr_debug("yukon_init\n");
 	if (skge->autoneg == AUTONEG_ENABLE) {
@@ -1641,32 +1644,11 @@ static void yukon_init(struct skge_hw *hw, int port)
 	gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
 	gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
 
-	/* Setup Phy LED's */
-	ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
-	ledover = 0;
-
-	ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
-
-	/* turn off the Rx LED (LED_RX) */
-	ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
-
-	/* disable blink mode (LED_DUPLEX) on collisions */
-	ctrl |= PHY_M_LEDC_DP_CTRL;
-	gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
-
-	if (skge->autoneg == AUTONEG_DISABLE || skge->speed == SPEED_100) {
-		/* turn on 100 Mbps LED (LED_LINK100) */
-		ledover |= PHY_M_LED_MO_100(MO_LED_ON);
-	}
-
-	if (ledover)
-		gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
-
 	/* Enable phy interrupt on autonegotiation complete (or link up) */
 	if (skge->autoneg == AUTONEG_ENABLE)
-		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
+		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
 	else
-		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
+		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
 }
 
 static void yukon_reset(struct skge_hw *hw, int port)
@@ -1691,7 +1673,7 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
 
 	/* WA code for COMA mode -- set PHY reset */
 	if (hw->chip_id == CHIP_ID_YUKON_LITE &&
-	    hw->chip_rev == CHIP_REV_YU_LITE_A3)
+	    hw->chip_rev >= CHIP_REV_YU_LITE_A3)
 		skge_write32(hw, B2_GP_IO,
 			     (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));
 
@@ -1701,7 +1683,7 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
 
 	/* WA code for COMA mode -- clear PHY reset */
 	if (hw->chip_id == CHIP_ID_YUKON_LITE &&
-	    hw->chip_rev == CHIP_REV_YU_LITE_A3)
+	    hw->chip_rev >= CHIP_REV_YU_LITE_A3)
 		skge_write32(hw, B2_GP_IO,
 			     (skge_read32(hw, B2_GP_IO) | GP_DIR_9)
 			     & ~GP_IO_9);
@@ -1745,9 +1727,7 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
 	gma_write16(hw, port, GM_GP_CTRL, reg);
 	skge_read16(hw, GMAC_IRQ_SRC);
 
-	spin_lock_bh(&hw->phy_lock);
 	yukon_init(hw, port);
-	spin_unlock_bh(&hw->phy_lock);
 
 	/* MIB clear */
 	reg = gma_read16(hw, port, GM_PHY_ADDR);
@@ -1796,7 +1776,7 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
 	skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
 	reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
 	if (hw->chip_id == CHIP_ID_YUKON_LITE &&
-	    hw->chip_rev == CHIP_REV_YU_LITE_A3)
+	    hw->chip_rev >= CHIP_REV_YU_LITE_A3)
 		reg &= ~GMF_RX_F_FL_ON;
 	skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
 	skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
@@ -1813,19 +1793,19 @@ static void yukon_stop(struct skge_port *skge)
 	int port = skge->port;
 
 	if (hw->chip_id == CHIP_ID_YUKON_LITE &&
-	    hw->chip_rev == CHIP_REV_YU_LITE_A3) {
+	    hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
 		skge_write32(hw, B2_GP_IO,
 			     skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9);
 	}
 
 	gma_write16(hw, port, GM_GP_CTRL,
 			 gma_read16(hw, port, GM_GP_CTRL)
-			 & ~(GM_GPCR_RX_ENA|GM_GPCR_RX_ENA));
+			 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
 	gma_read16(hw, port, GM_GP_CTRL);
 
 	/* set GPHY Control reset */
-	gma_write32(hw, port, GPHY_CTRL, GPC_RST_SET);
-	gma_write32(hw, port, GMAC_CTRL, GMC_RST_SET);
+	skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
+	skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
 }
 
 static void yukon_get_stats(struct skge_port *skge, u64 *data)
@@ -1856,11 +1836,12 @@ static void yukon_mac_intr(struct skge_hw *hw, int port)
 
 	if (status & GM_IS_RX_FF_OR) {
 		++skge->net_stats.rx_fifo_errors;
-		gma_write8(hw, port, RX_GMF_CTRL_T, GMF_CLI_RX_FO);
+		skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
 	}
+
 	if (status & GM_IS_TX_FF_UR) {
 		++skge->net_stats.tx_fifo_errors;
-		gma_write8(hw, port, TX_GMF_CTRL_T, GMF_CLI_TX_FU);
+		skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
 	}
 
 }
@@ -1896,7 +1877,7 @@ static void yukon_link_up(struct skge_port *skge)
 	reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
 	gma_write16(hw, port, GM_GP_CTRL, reg);
 
-	gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
+	gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
 	skge_link_up(skge);
 }
 
@@ -1904,12 +1885,14 @@ static void yukon_link_down(struct skge_port *skge)
 {
 	struct skge_hw *hw = skge->hw;
 	int port = skge->port;
+	u16 ctrl;
 
 	pr_debug("yukon_link_down\n");
 	gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
-	gm_phy_write(hw, port, GM_GP_CTRL,
-			  gm_phy_read(hw, port, GM_GP_CTRL)
-			  & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA));
+
+	ctrl = gma_read16(hw, port, GM_GP_CTRL);
+	ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
+	gma_write16(hw, port, GM_GP_CTRL, ctrl);
 
 	if (skge->flow_control == FLOW_MODE_REM_SEND) {
 		/* restore Asymmetric Pause bit */
@@ -2097,10 +2080,12 @@ static int skge_up(struct net_device *dev)
 	skge_write32(hw, B0_IMSK, hw->intr_mask);
 
 	/* Initialze MAC */
+	spin_lock_bh(&hw->phy_lock);
 	if (hw->chip_id == CHIP_ID_GENESIS)
 		genesis_mac_init(hw, port);
 	else
 		yukon_mac_init(hw, port);
+	spin_unlock_bh(&hw->phy_lock);
 
 	/* Configure RAMbuffers */
 	chunk = hw->ram_size / ((hw->ports + 1)*2);
@@ -2116,6 +2101,7 @@ static int skge_up(struct net_device *dev)
 	/* Start receiver BMU */
 	wmb();
 	skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
+	skge_led(skge, LED_MODE_ON);
 
 	pr_debug("skge_up completed\n");
 	return 0;
@@ -2140,8 +2126,6 @@ static int skge_down(struct net_device *dev)
 
 	netif_stop_queue(dev);
 
-	del_timer_sync(&skge->led_blink);
-
 	/* Stop transmitter */
 	skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
 	skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
@@ -2175,15 +2159,12 @@ static int skge_down(struct net_device *dev)
 	if (hw->chip_id == CHIP_ID_GENESIS) {
 		skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
 		skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
-		skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_STOP);
-		skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_STOP);
 	} else {
 		skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
 		skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
 	}
 
-	/* turn off led's */
-	skge_write16(hw, B0_LED, LED_STAT_OFF);
+	skge_led(skge, LED_MODE_OFF);
 
 	skge_tx_clean(skge);
 	skge_rx_clean(skge);
@@ -2633,11 +2614,17 @@ static inline void skge_tx_intr(struct net_device *dev)
 	spin_unlock(&skge->tx_lock);
 }
 
+/* Parity errors seem to happen when Genesis is connected to a switch
+ * with no other ports present. Heartbeat error??
+ */
 static void skge_mac_parity(struct skge_hw *hw, int port)
 {
-	printk(KERN_ERR PFX "%s: mac data parity error\n",
-	       hw->dev[port] ? hw->dev[port]->name
-	       : (port == 0 ? "(port A)": "(port B"));
+	struct net_device *dev = hw->dev[port];
+
+	if (dev) {
+		struct skge_port *skge = netdev_priv(dev);
+		++skge->net_stats.tx_heartbeat_errors;
+	}
 
 	if (hw->chip_id == CHIP_ID_GENESIS)
 		skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
@@ -3083,10 +3070,6 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port,
 
 	spin_lock_init(&skge->tx_lock);
 
-	init_timer(&skge->led_blink);
-	skge->led_blink.function = skge_blink_timer;
-	skge->led_blink.data = (unsigned long) skge;
-
 	if (hw->chip_id != CHIP_ID_GENESIS) {
 		dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
 		skge->rx_csum = 1;
diff --git a/drivers/net/skge.h b/drivers/net/skge.h
index fced3d2bc07..b432f1bb816 100644
--- a/drivers/net/skge.h
+++ b/drivers/net/skge.h
@@ -1449,10 +1449,12 @@ enum {
 	PHY_M_IS_DTE_CHANGE	= 1<<2, /* DTE Power Det. Status Changed */
 	PHY_M_IS_POL_CHANGE	= 1<<1, /* Polarity Changed */
 	PHY_M_IS_JABBER		= 1<<0, /* Jabber */
-};
 
-#define PHY_M_DEF_MSK	( PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE | \
-			  PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR)
+	PHY_M_IS_DEF_MSK	= PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE |
+				  PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR,
+
+	PHY_M_IS_AN_MSK		= PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
+};
 
 /*****  PHY_MARV_EXT_CTRL	16 bit r/w	Ext. PHY Specific Ctrl *****/
 enum {
@@ -1509,7 +1511,7 @@ enum {
 	PHY_M_LEDC_TX_C_MSB	= 1<<0, /* Tx Control (MSB, 88E1111 only) */
 };
 
-#define PHY_M_LED_PULS_DUR(x)	(	((x)<<12) & PHY_M_LEDC_PULS_MSK)
+#define PHY_M_LED_PULS_DUR(x)	(((x)<<12) & PHY_M_LEDC_PULS_MSK)
 
 enum {
 	PULS_NO_STR	= 0,/* no pulse stretching */
@@ -1522,7 +1524,7 @@ enum {
 	PULS_1300MS	= 7,/* 1.3 s to 2.7 s */
 };
 
-#define PHY_M_LED_BLINK_RT(x)	(	((x)<<8) & PHY_M_LEDC_BL_R_MSK)
+#define PHY_M_LED_BLINK_RT(x)	(((x)<<8) & PHY_M_LEDC_BL_R_MSK)
 
 enum {
 	BLINK_42MS	= 0,/* 42 ms */
@@ -1602,9 +1604,9 @@ enum {
 	PHY_M_FELP_LED0_MSK = 0xf, /* Bit  3.. 0: LED0 Mask (SPEED) */
 };
 
-#define PHY_M_FELP_LED2_CTRL(x)	(	((x)<<8) & PHY_M_FELP_LED2_MSK)
-#define PHY_M_FELP_LED1_CTRL(x)	(	((x)<<4) & PHY_M_FELP_LED1_MSK)
-#define PHY_M_FELP_LED0_CTRL(x)	(	((x)<<0) & PHY_M_FELP_LED0_MSK)
+#define PHY_M_FELP_LED2_CTRL(x)	(((x)<<8) & PHY_M_FELP_LED2_MSK)
+#define PHY_M_FELP_LED1_CTRL(x)	(((x)<<4) & PHY_M_FELP_LED1_MSK)
+#define PHY_M_FELP_LED0_CTRL(x)	(((x)<<0) & PHY_M_FELP_LED0_MSK)
 
 enum {
 	LED_PAR_CTRL_COLX	= 0x00,
@@ -1640,7 +1642,7 @@ enum {
 	PHY_M_MAC_MD_COPPER	= 5,/* Copper only */
 	PHY_M_MAC_MD_1000BX	= 7,/* 1000Base-X only */
 };
-#define PHY_M_MAC_MODE_SEL(x)	(	((x)<<7) & PHY_M_MAC_MD_MSK)
+#define PHY_M_MAC_MODE_SEL(x)	(((x)<<7) & PHY_M_MAC_MD_MSK)
 
 /*****  PHY_MARV_PHY_CTRL (page 3)		16 bit r/w	LED Control Reg. *****/
 enum {
@@ -1650,10 +1652,10 @@ enum {
 	PHY_M_LEDC_STA0_MSK	= 0xf, /* Bit  3.. 0: STAT0 LED Ctrl. Mask */
 };
 
-#define PHY_M_LEDC_LOS_CTRL(x)	(	((x)<<12) & PHY_M_LEDC_LOS_MSK)
-#define PHY_M_LEDC_INIT_CTRL(x)	(	((x)<<8) & PHY_M_LEDC_INIT_MSK)
-#define PHY_M_LEDC_STA1_CTRL(x)	(	((x)<<4) & PHY_M_LEDC_STA1_MSK)
-#define PHY_M_LEDC_STA0_CTRL(x)	(	((x)<<0) & PHY_M_LEDC_STA0_MSK)
+#define PHY_M_LEDC_LOS_CTRL(x)	(((x)<<12) & PHY_M_LEDC_LOS_MSK)
+#define PHY_M_LEDC_INIT_CTRL(x)	(((x)<<8) & PHY_M_LEDC_INIT_MSK)
+#define PHY_M_LEDC_STA1_CTRL(x)	(((x)<<4) & PHY_M_LEDC_STA1_MSK)
+#define PHY_M_LEDC_STA0_CTRL(x)	(((x)<<0) & PHY_M_LEDC_STA0_MSK)
 
 /* GMAC registers  */
 /* Port Registers */
@@ -2505,8 +2507,6 @@ struct skge_port {
 	dma_addr_t	     dma;
 	unsigned long	     mem_size;
 	unsigned int	     rx_buf_size;
-
-	struct timer_list    led_blink;
 };
 
 
@@ -2606,17 +2606,6 @@ static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
 	skge_write16(hw, SK_GMAC_REG(port,r), v);
 }
 
-static inline void gma_write32(const struct skge_hw *hw, int port, int r, u32 v)
-{
-	skge_write16(hw, SK_GMAC_REG(port, r), (u16) v);
-	skge_write32(hw, SK_GMAC_REG(port, r+4), (u16)(v >> 16));
-}
-
-static inline void gma_write8(const struct skge_hw *hw, int port, int r, u8 v)
-{
-	skge_write8(hw, SK_GMAC_REG(port,r), v);
-}
-
 static inline void gma_set_addr(struct skge_hw *hw, int port, int reg,
 				    const u8 *addr)
 {
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index 7089d86e857..a9b06b8d8e3 100644
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -188,7 +188,7 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
 #define	SMC_IRQ_TRIGGER_TYPE (( \
 		   machine_is_omap_h2() \
 		|| machine_is_omap_h3() \
-		|| (machine_is_omap_innovator() && !cpu_is_omap150()) \
+		|| (machine_is_omap_innovator() && !cpu_is_omap1510()) \
 	) ? IRQT_FALLING : IRQT_RISING)
 
 
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 201a550f0bc..368b8fb1402 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -66,8 +66,8 @@
 
 #define DRV_MODULE_NAME		"tg3"
 #define PFX DRV_MODULE_NAME	": "
-#define DRV_MODULE_VERSION	"3.34"
-#define DRV_MODULE_RELDATE	"July 25, 2005"
+#define DRV_MODULE_VERSION	"3.35"
+#define DRV_MODULE_RELDATE	"August 6, 2005"
 
 #define TG3_DEF_MAC_MODE	0
 #define TG3_DEF_RX_MODE		0
@@ -10421,6 +10421,12 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
 
 	tg3_init_coal(tp);
 
+	/* Now that we have fully setup the chip, save away a snapshot
+	 * of the PCI config space.  We need to restore this after
+	 * GRC_MISC_CFG core clock resets and some resume events.
+	 */
+	pci_save_state(tp->pdev);
+
 	err = register_netdev(dev);
 	if (err) {
 		printk(KERN_ERR PFX "Cannot register net device, "
@@ -10430,12 +10436,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
 
 	pci_set_drvdata(pdev, dev);
 
-	/* Now that we have fully setup the chip, save away a snapshot
-	 * of the PCI config space.  We need to restore this after
-	 * GRC_MISC_CFG core clock resets and some resume events.
-	 */
-	pci_save_state(tp->pdev);
-
 	printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (PCI%s:%s:%s) %sBaseT Ethernet ",
 	       dev->name,
 	       tp->board_part_number,
diff --git a/drivers/net/via-velocity.h b/drivers/net/via-velocity.h
index 1b70b7c9758..d9a774b91dd 100644
--- a/drivers/net/via-velocity.h
+++ b/drivers/net/via-velocity.h
@@ -1414,7 +1414,7 @@ static inline void mac_get_cam(struct mac_regs __iomem * regs, int idx, u8 *addr
  *	the rest of the logic from the result of sleep/wakeup
  */
 
-inline static void mac_wol_reset(struct mac_regs __iomem * regs)
+static inline void mac_wol_reset(struct mac_regs __iomem * regs)
 {
 
 	/* Turn off SWPTAG right after leaving power mode */
@@ -1811,7 +1811,7 @@ struct velocity_info {
  *	CHECK ME: locking
  */
 
-inline static int velocity_get_ip(struct velocity_info *vptr)
+static inline int velocity_get_ip(struct velocity_info *vptr)
 {
 	struct in_device *in_dev = (struct in_device *) vptr->dev->ip_ptr;
 	struct in_ifaddr *ifa;
diff --git a/drivers/net/wireless/airo.c b/drivers/net/wireless/airo.c
index 47f3c5d0203..df20adcd073 100644
--- a/drivers/net/wireless/airo.c
+++ b/drivers/net/wireless/airo.c
@@ -5013,7 +5013,7 @@ static void proc_SSID_on_close( struct inode *inode, struct file *file ) {
 	enable_MAC(ai, &rsp, 1);
 }
 
-inline static u8 hexVal(char c) {
+static inline u8 hexVal(char c) {
 	if (c>='0' && c<='9') return c -= '0';
 	if (c>='a' && c<='f') return c -= 'a'-10;
 	if (c>='A' && c<='F') return c -= 'A'-10;
diff --git a/drivers/net/wireless/orinoco_cs.c b/drivers/net/wireless/orinoco_cs.c
index 368d2f962f6..1cc1492083c 100644
--- a/drivers/net/wireless/orinoco_cs.c
+++ b/drivers/net/wireless/orinoco_cs.c
@@ -621,8 +621,6 @@ static struct pcmcia_device_id orinoco_cs_ids[] = {
 	PCMCIA_DEVICE_MANF_CARD(0x9005, 0x0021),
 	PCMCIA_DEVICE_MANF_CARD(0xc250, 0x0002),
 	PCMCIA_DEVICE_MANF_CARD(0xd601, 0x0002),
-	PCMCIA_DEVICE_MANF_CARD(0xd601, 0x0002),
-	PCMCIA_DEVICE_MANF_CARD(0xd601, 0x0005),
 	PCMCIA_DEVICE_MANF_CARD(0xd601, 0x0005),
 	PCMCIA_DEVICE_PROD_ID12("3Com", "3CRWE737A AirConnect Wireless LAN PC Card", 0x41240e5b, 0x56010af3),
 	PCMCIA_DEVICE_PROD_ID123("Instant Wireless ", " Network PC CARD", "Version 01.02", 0x11d901af, 0x6e9bd926, 0x4b74baa0),
diff --git a/drivers/oprofile/cpu_buffer.c b/drivers/oprofile/cpu_buffer.c
index e9b1772a3a2..026f671ea55 100644
--- a/drivers/oprofile/cpu_buffer.c
+++ b/drivers/oprofile/cpu_buffer.c
@@ -42,8 +42,7 @@ void free_cpu_buffers(void)
 		vfree(cpu_buffer[i].buffer);
 	}
 }
- 
- 
+
 int alloc_cpu_buffers(void)
 {
 	int i;
@@ -74,7 +73,6 @@ fail:
 	free_cpu_buffers();
 	return -ENOMEM;
 }
- 
 
 void start_cpu_work(void)
 {
@@ -93,7 +91,6 @@ void start_cpu_work(void)
 	}
 }
 
-
 void end_cpu_work(void)
 {
 	int i;
@@ -109,7 +106,6 @@ void end_cpu_work(void)
 	flush_scheduled_work();
 }
 
-
 /* Resets the cpu buffer to a sane state. */
 void cpu_buffer_reset(struct oprofile_cpu_buffer * cpu_buf)
 {
@@ -121,7 +117,6 @@ void cpu_buffer_reset(struct oprofile_cpu_buffer * cpu_buf)
 	cpu_buf->last_task = NULL;
 }
 
-
 /* compute number of available slots in cpu_buffer queue */
 static unsigned long nr_available_slots(struct oprofile_cpu_buffer const * b)
 {
@@ -134,7 +129,6 @@ static unsigned long nr_available_slots(struct oprofile_cpu_buffer const * b)
 	return tail + (b->buffer_size - head) - 1;
 }
 
-
 static void increment_head(struct oprofile_cpu_buffer * b)
 {
 	unsigned long new_head = b->head_pos + 1;
@@ -149,10 +143,7 @@ static void increment_head(struct oprofile_cpu_buffer * b)
 		b->head_pos = 0;
 }
 
-
-
-
-inline static void
+static inline void
 add_sample(struct oprofile_cpu_buffer * cpu_buf,
            unsigned long pc, unsigned long event)
 {
@@ -162,14 +153,12 @@ add_sample(struct oprofile_cpu_buffer * cpu_buf,
 	increment_head(cpu_buf);
 }
 
-
-inline static void
+static inline void
 add_code(struct oprofile_cpu_buffer * buffer, unsigned long value)
 {
 	add_sample(buffer, ESCAPE_CODE, value);
 }
 
-
 /* This must be safe from any context. It's safe writing here
  * because of the head/tail separation of the writer and reader
  * of the CPU buffer.
@@ -223,13 +212,11 @@ static int oprofile_begin_trace(struct oprofile_cpu_buffer * cpu_buf)
 	return 1;
 }
 
-
 static void oprofile_end_trace(struct oprofile_cpu_buffer * cpu_buf)
 {
 	cpu_buf->tracing = 0;
 }
 
-
 void oprofile_add_sample(struct pt_regs * const regs, unsigned long event)
 {
 	struct oprofile_cpu_buffer * cpu_buf = &cpu_buffer[smp_processor_id()];
@@ -251,14 +238,12 @@ void oprofile_add_sample(struct pt_regs * const regs, unsigned long event)
 	oprofile_end_trace(cpu_buf);
 }
 
-
 void oprofile_add_pc(unsigned long pc, int is_kernel, unsigned long event)
 {
 	struct oprofile_cpu_buffer * cpu_buf = &cpu_buffer[smp_processor_id()];
 	log_sample(cpu_buf, pc, is_kernel, event);
 }
 
-
 void oprofile_add_trace(unsigned long pc)
 {
 	struct oprofile_cpu_buffer * cpu_buf = &cpu_buffer[smp_processor_id()];
@@ -283,8 +268,6 @@ void oprofile_add_trace(unsigned long pc)
 	add_sample(cpu_buf, pc, 0);
 }
 
-
-
 /*
  * This serves to avoid cpu buffer overflow, and makes sure
  * the task mortuary progresses
diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c
index fedae89d8f7..fb9a11243d2 100644
--- a/drivers/pci/bus.c
+++ b/drivers/pci/bus.c
@@ -60,7 +60,9 @@ pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res,
 			continue;
 
 		/* Ok, try it out.. */
-		ret = allocate_resource(r, res, size, min, -1, align,
+		ret = allocate_resource(r, res, size,
+					r->start ? : min,
+					-1, align,
 					alignf, alignf_data);
 		if (ret == 0)
 			break;
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index df3bdae2040..93e8a878ea9 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -507,7 +507,7 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max
 		pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
 
 		if (!is_cardbus) {
-			child->bridge_ctl = PCI_BRIDGE_CTL_NO_ISA;
+			child->bridge_ctl = bctl | PCI_BRIDGE_CTL_NO_ISA;
 			/*
 			 * Adjust subordinate busnr in parent buses.
 			 * We do this before scanning for children because
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 1521fd5d95c..a9160ad1658 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -373,6 +373,25 @@ static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686_4,	quirk_vt82c686_acpi );
 
+/*
+ * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
+ *	0x88 (128 bytes of power management registers)
+ *	0xd0 (16 bytes of SMB registers)
+ */
+static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
+{
+	u16 pm, smb;
+
+	pci_read_config_word(dev, 0x88, &pm);
+	pm &= PCI_BASE_ADDRESS_IO_MASK;
+	quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES);
+
+	pci_read_config_word(dev, 0xd0, &smb);
+	smb &= PCI_BASE_ADDRESS_IO_MASK;
+	quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1);
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8235,	quirk_vt8235_acpi);
+
 
 #ifdef CONFIG_X86_IO_APIC 
 
@@ -820,6 +839,11 @@ static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
 			case 0x0001: /* Toshiba Satellite A40 */
 				asus_hides_smbus = 1;
 			}
+		if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
+			switch(dev->subsystem_device) {
+			case 0x0001: /* Toshiba Tecra M2 */
+				asus_hides_smbus = 1;
+			}
        } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
                if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)
                        switch(dev->subsystem_device) {
diff --git a/drivers/pci/rom.c b/drivers/pci/rom.c
index 838575e3fac..713c78f3a65 100644
--- a/drivers/pci/rom.c
+++ b/drivers/pci/rom.c
@@ -125,7 +125,9 @@ void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size)
 		image += readw(pds + 16) * 512;
 	} while (!last_image);
 
-	*size = image - rom;
+	/* never return a size larger than the PCI resource window */
+	/* there are known ROMs that get the size wrong */
+	*size = min((size_t)(image - rom), *size);
 
 	return rom;
 }
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 9fe48f712be..a2eebc6eaac 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -51,8 +51,6 @@ pbus_assign_resources_sorted(struct pci_bus *bus)
 	struct resource_list head, *list, *tmp;
 	int idx;
 
-	bus->bridge_ctl &= ~PCI_BRIDGE_CTL_VGA;
-
 	head.next = NULL;
 	list_for_each_entry(dev, &bus->devices, bus_list) {
 		u16 class = dev->class >> 8;
@@ -62,10 +60,6 @@ pbus_assign_resources_sorted(struct pci_bus *bus)
 		    class == PCI_CLASS_BRIDGE_HOST)
 			continue;
 
-		if (class == PCI_CLASS_DISPLAY_VGA ||
-		    class == PCI_CLASS_NOT_DEFINED_VGA)
-			bus->bridge_ctl |= PCI_BRIDGE_CTL_VGA;
-
 		pdev_sort_resources(dev, &head);
 	}
 
@@ -509,12 +503,6 @@ pci_bus_assign_resources(struct pci_bus *bus)
 
 	pbus_assign_resources_sorted(bus);
 
-	if (bus->bridge_ctl & PCI_BRIDGE_CTL_VGA) {
-		/* Propagate presence of the VGA to upstream bridges */
-		for (b = bus; b->parent; b = b->parent) {
-			b->bridge_ctl |= PCI_BRIDGE_CTL_VGA;
-		}
-	}
 	list_for_each_entry(dev, &bus->devices, bus_list) {
 		b = dev->subordinate;
 		if (!b)
diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
index 1ca21d2ba11..84eedc96568 100644
--- a/drivers/pci/setup-res.c
+++ b/drivers/pci/setup-res.c
@@ -33,6 +33,11 @@ pci_update_resource(struct pci_dev *dev, struct resource *res, int resno)
 	u32 new, check, mask;
 	int reg;
 
+	/* Ignore resources for unimplemented BARs and unused resource slots
+	   for 64 bit BARs. */
+	if (!res->flags)
+		return;
+
 	pcibios_resource_to_bus(dev, &region, res);
 
 	pr_debug("  got res [%lx:%lx] bus [%lx:%lx] flags %lx for "
@@ -67,7 +72,7 @@ pci_update_resource(struct pci_dev *dev, struct resource *res, int resno)
 
 	if ((new & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
 	    (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) {
-		new = 0; /* currently everyone zeros the high address */
+		new = region.start >> 16 >> 16;
 		pci_write_config_dword(dev, reg + 4, new);
 		pci_read_config_dword(dev, reg + 4, &check);
 		if (check != new) {
diff --git a/drivers/pcmcia/au1000_generic.c b/drivers/pcmcia/au1000_generic.c
index 0a5c95807cf..470ef756252 100644
--- a/drivers/pcmcia/au1000_generic.c
+++ b/drivers/pcmcia/au1000_generic.c
@@ -388,6 +388,7 @@ int au1x00_pcmcia_socket_probe(struct device *dev, struct pcmcia_low_level *ops,
 		struct au1000_pcmcia_socket *skt = PCMCIA_SOCKET(i);
 		memset(skt, 0, sizeof(*skt));
 
+		skt->socket.resource_ops = &pccard_static_ops;
 		skt->socket.ops = &au1x00_pcmcia_operations;
 		skt->socket.owner = ops->owner;
 		skt->socket.dev.dev = dev;
diff --git a/drivers/pcmcia/cistpl.c b/drivers/pcmcia/cistpl.c
index dd7651ff5b4..3afb682255a 100644
--- a/drivers/pcmcia/cistpl.c
+++ b/drivers/pcmcia/cistpl.c
@@ -88,31 +88,38 @@ EXPORT_SYMBOL(release_cis_mem);
 static void __iomem *
 set_cis_map(struct pcmcia_socket *s, unsigned int card_offset, unsigned int flags)
 {
-    pccard_mem_map *mem = &s->cis_mem;
-    int ret;
+	pccard_mem_map *mem = &s->cis_mem;
+	int ret;
+
+	if (!(s->features & SS_CAP_STATIC_MAP) && (mem->res == NULL)) {
+		mem->res = pcmcia_find_mem_region(0, s->map_size, s->map_size, 0, s);
+		if (mem->res == NULL) {
+			printk(KERN_NOTICE "cs: unable to map card memory!\n");
+			return NULL;
+		}
+		s->cis_virt = NULL;
+	}
 
-    if (!(s->features & SS_CAP_STATIC_MAP) && mem->res == NULL) {
-	mem->res = pcmcia_find_mem_region(0, s->map_size, s->map_size, 0, s);
-	if (mem->res == NULL) {
-	    printk(KERN_NOTICE "cs: unable to map card memory!\n");
-	    return NULL;
+	if (!(s->features & SS_CAP_STATIC_MAP) && (!s->cis_virt))
+		s->cis_virt = ioremap(mem->res->start, s->map_size);
+
+	mem->card_start = card_offset;
+	mem->flags = flags;
+
+	ret = s->ops->set_mem_map(s, mem);
+	if (ret) {
+		iounmap(s->cis_virt);
+		s->cis_virt = NULL;
+		return NULL;
 	}
-	s->cis_virt = ioremap(mem->res->start, s->map_size);
-    }
-    mem->card_start = card_offset;
-    mem->flags = flags;
-    ret = s->ops->set_mem_map(s, mem);
-    if (ret) {
-	iounmap(s->cis_virt);
-	return NULL;
-    }
 
-    if (s->features & SS_CAP_STATIC_MAP) {
-	if (s->cis_virt)
-	    iounmap(s->cis_virt);
-	s->cis_virt = ioremap(mem->static_start, s->map_size);
-    }
-    return s->cis_virt;
+	if (s->features & SS_CAP_STATIC_MAP) {
+		if (s->cis_virt)
+			iounmap(s->cis_virt);
+		s->cis_virt = ioremap(mem->static_start, s->map_size);
+	}
+
+	return s->cis_virt;
 }
 
 /*======================================================================
diff --git a/drivers/pcmcia/ds.c b/drivers/pcmcia/ds.c
index 3e3c6f12bbe..43da2e92d50 100644
--- a/drivers/pcmcia/ds.c
+++ b/drivers/pcmcia/ds.c
@@ -206,8 +206,8 @@ static void pcmcia_check_driver(struct pcmcia_driver *p_drv)
 	u32 hash;
 
 	if (!p_drv->attach || !p_drv->event || !p_drv->detach)
-		printk(KERN_DEBUG "pcmcia: %s does misses a callback function",
-		       p_drv->drv.name);
+		printk(KERN_DEBUG "pcmcia: %s lacks a requisite callback "
+		       "function\n", p_drv->drv.name);
 
 	while (did && did->match_flags) {
 		for (i=0; i<4; i++) {
@@ -589,8 +589,8 @@ static void pcmcia_delayed_add_pseudo_device(void *data)
 static inline void pcmcia_add_pseudo_device(struct pcmcia_socket *s)
 {
 	if (!s->pcmcia_state.device_add_pending) {
-		schedule_work(&s->device_add);
 		s->pcmcia_state.device_add_pending = 1;
+		schedule_work(&s->device_add);
 	}
 	return;
 }
diff --git a/drivers/pcmcia/o2micro.h b/drivers/pcmcia/o2micro.h
index b1f6e3d9ee0..a234ce1967a 100644
--- a/drivers/pcmcia/o2micro.h
+++ b/drivers/pcmcia/o2micro.h
@@ -120,11 +120,16 @@
 #define  O2_MODE_E_LED_OUT	0x08
 #define  O2_MODE_E_SKTA_ACTV	0x10
 
+#define O2_RESERVED1		0x94
+#define O2_RESERVED2		0xD4
+#define O2_RES_READ_PREFETCH	0x02
+#define O2_RES_WRITE_BURST	0x08
+
 static int o2micro_override(struct yenta_socket *socket)
 {
 	/*
-	 * 'reserved' register at 0x94/D4. chaning it to 0xCA (8 bit) enables
-	 * read prefetching which for example makes the RME Hammerfall DSP
+	 * 'reserved' register at 0x94/D4. allows setting read prefetch and write
+	 * bursting. read prefetching for example makes the RME Hammerfall DSP
 	 * working. for some bridges it is at 0x94, for others at 0xD4. it's
 	 * ok to write to both registers on all O2 bridges.
 	 * from Eric Still, 02Micro.
@@ -132,20 +137,35 @@ static int o2micro_override(struct yenta_socket *socket)
 	u8 a, b;
 
 	if (PCI_FUNC(socket->dev->devfn) == 0) {
-		a = config_readb(socket, 0x94);
-		b = config_readb(socket, 0xD4);
+		a = config_readb(socket, O2_RESERVED1);
+		b = config_readb(socket, O2_RESERVED2);
 
 		printk(KERN_INFO "Yenta O2: res at 0x94/0xD4: %02x/%02x\n", a, b);
 
 		switch (socket->dev->device) {
+		/*
+		 * older bridges have problems with both read prefetch and write
+		 * bursting depending on the combination of the chipset, bridge
+		 * and the cardbus card. so disable them to be on the safe side.
+		 */
+		case PCI_DEVICE_ID_O2_6729:
+		case PCI_DEVICE_ID_O2_6730:
+		case PCI_DEVICE_ID_O2_6812:
 		case PCI_DEVICE_ID_O2_6832:
-			printk(KERN_INFO "Yenta O2: old bridge, not enabling read prefetch / write burst\n");
+		case PCI_DEVICE_ID_O2_6836:
+			printk(KERN_INFO "Yenta O2: old bridge, disabling read prefetch/write burst\n");
+			config_writeb(socket, O2_RESERVED1,
+			              a & ~(O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST));
+			config_writeb(socket, O2_RESERVED2,
+			              b & ~(O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST));
 			break;
 
 		default:
 			printk(KERN_INFO "Yenta O2: enabling read prefetch/write burst\n");
-			config_writeb(socket, 0x94, a | 0x0a);
-			config_writeb(socket, 0xD4, b | 0x0a);
+			config_writeb(socket, O2_RESERVED1,
+			              a | O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST);
+			config_writeb(socket, O2_RESERVED2,
+			              b | O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST);
 		}
 	}
 
diff --git a/drivers/pcmcia/pcmcia_resource.c b/drivers/pcmcia/pcmcia_resource.c
index 184f4f88b2a..6f9fdb27640 100644
--- a/drivers/pcmcia/pcmcia_resource.c
+++ b/drivers/pcmcia/pcmcia_resource.c
@@ -800,7 +800,7 @@ int pcmcia_request_irq(struct pcmcia_device *p_dev, irq_req_t *req)
 	} else {
 		int try;
 		u32 mask = s->irq_mask;
-		void *data = NULL;
+		void *data = &p_dev->dev.driver; /* something unique to this device */
 
 		for (try = 0; try < 64; try++) {
 			irq = try % 32;
diff --git a/drivers/pcmcia/yenta_socket.c b/drivers/pcmcia/yenta_socket.c
index 6837491f021..62fd705203f 100644
--- a/drivers/pcmcia/yenta_socket.c
+++ b/drivers/pcmcia/yenta_socket.c
@@ -605,9 +605,8 @@ static int yenta_search_res(struct yenta_socket *socket, struct resource *res,
 
 static void yenta_allocate_res(struct yenta_socket *socket, int nr, unsigned type, int addr_start, int addr_end)
 {
-	struct pci_bus *bus;
 	struct resource *root, *res;
-	u32 start, end;
+	struct pci_bus_region region;
 	unsigned mask;
 
 	res = socket->dev->resource + PCI_BRIDGE_RESOURCES + nr;
@@ -620,15 +619,13 @@ static void yenta_allocate_res(struct yenta_socket *socket, int nr, unsigned typ
 	if (type & IORESOURCE_IO)
 		mask = ~3;
 
-	bus = socket->dev->subordinate;
-	res->name = bus->name;
+	res->name = socket->dev->subordinate->name;
 	res->flags = type;
 
-	start = config_readl(socket, addr_start) & mask;
-	end = config_readl(socket, addr_end) | ~mask;
-	if (start && end > start && !override_bios) {
-		res->start = start;
-		res->end = end;
+	region.start = config_readl(socket, addr_start) & mask;
+	region.end = config_readl(socket, addr_end) | ~mask;
+	if (region.start && region.end > region.start && !override_bios) {
+		pcibios_bus_to_resource(socket->dev, res, &region);
 		root = pci_find_parent_resource(socket->dev, res);
 		if (root && (request_resource(root, res) == 0))
 			return;
@@ -642,6 +639,7 @@ static void yenta_allocate_res(struct yenta_socket *socket, int nr, unsigned typ
 		    (yenta_search_res(socket, res, BRIDGE_IO_MIN))) {
 			config_writel(socket, addr_start, res->start);
 			config_writel(socket, addr_end, res->end);
+			return;
 		}
 	} else {
 		if (type & IORESOURCE_PREFETCH) {
@@ -650,6 +648,7 @@ static void yenta_allocate_res(struct yenta_socket *socket, int nr, unsigned typ
 			    (yenta_search_res(socket, res, BRIDGE_MEM_MIN))) {
 				config_writel(socket, addr_start, res->start);
 				config_writel(socket, addr_end, res->end);
+				return;
 			}
 			/* Approximating prefetchable by non-prefetchable */
 			res->flags = IORESOURCE_MEM;
@@ -659,6 +658,7 @@ static void yenta_allocate_res(struct yenta_socket *socket, int nr, unsigned typ
 		    (yenta_search_res(socket, res, BRIDGE_MEM_MIN))) {
 			config_writel(socket, addr_start, res->start);
 			config_writel(socket, addr_end, res->end);
+			return;
 		}
 	}
 
diff --git a/drivers/pnp/pnpbios/rsparser.c b/drivers/pnp/pnpbios/rsparser.c
index 9001b6f0204..e305bb132c2 100644
--- a/drivers/pnp/pnpbios/rsparser.c
+++ b/drivers/pnp/pnpbios/rsparser.c
@@ -11,7 +11,7 @@
 #ifdef CONFIG_PCI
 #include <linux/pci.h>
 #else
-inline void pcibios_penalize_isa_irq(int irq) {}
+inline void pcibios_penalize_isa_irq(int irq, int active) {}
 #endif /* CONFIG_PCI */
 
 #include "pnpbios.h"
diff --git a/drivers/s390/block/dasd.c b/drivers/s390/block/dasd.c
index 6527ff6f470..d5f53980749 100644
--- a/drivers/s390/block/dasd.c
+++ b/drivers/s390/block/dasd.c
@@ -7,7 +7,7 @@
  * Bugreports.to..: <Linux390@de.ibm.com>
  * (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 1999-2001
  *
- * $Revision: 1.164 $
+ * $Revision: 1.165 $
  */
 
 #include <linux/config.h>
@@ -1740,6 +1740,10 @@ dasd_exit(void)
 	dasd_proc_exit();
 #endif
 	dasd_ioctl_exit();
+        if (dasd_page_cache != NULL) {
+		kmem_cache_destroy(dasd_page_cache);
+		dasd_page_cache = NULL;
+	}
 	dasd_gendisk_exit();
 	dasd_devmap_exit();
 	devfs_remove("dasd");
diff --git a/drivers/s390/block/dasd_fba.c b/drivers/s390/block/dasd_fba.c
index 7963ae343ee..28cb4613b7f 100644
--- a/drivers/s390/block/dasd_fba.c
+++ b/drivers/s390/block/dasd_fba.c
@@ -4,7 +4,7 @@
  * Bugreports.to..: <Linux390@de.ibm.com>
  * (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 1999,2000
  *
- * $Revision: 1.39 $
+ * $Revision: 1.40 $
  */
 
 #include <linux/config.h>
@@ -354,6 +354,8 @@ dasd_fba_build_cp(struct dasd_device * device, struct request *req)
 	}
 	cqr->device = device;
 	cqr->expires = 5 * 60 * HZ;	/* 5 minutes */
+	cqr->retries = 32;
+	cqr->buildclk = get_clock();
 	cqr->status = DASD_CQR_FILLED;
 	return cqr;
 }
diff --git a/drivers/s390/char/tape.h b/drivers/s390/char/tape.h
index d04e6c2c3cc..01d865d9379 100644
--- a/drivers/s390/char/tape.h
+++ b/drivers/s390/char/tape.h
@@ -3,10 +3,11 @@
  *    tape device driver for 3480/3490E/3590 tapes.
  *
  *  S390 and zSeries version
- *    Copyright (C) 2001,2002 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright (C) 2001,2005 IBM Deutschland Entwicklung GmbH, IBM Corporation
  *    Author(s): Carsten Otte <cotte@de.ibm.com>
  *		 Tuan Ngo-Anh <ngoanh@de.ibm.com>
  *		 Martin Schwidefsky <schwidefsky@de.ibm.com>
+ *		 Stefan Bader <shbader@de.ibm.com>
  */
 
 #ifndef _TAPE_H
@@ -111,6 +112,7 @@ enum tape_request_status {
 	TAPE_REQUEST_QUEUED,	/* request is queued to be processed */
 	TAPE_REQUEST_IN_IO,	/* request is currently in IO */
 	TAPE_REQUEST_DONE,	/* request is completed. */
+	TAPE_REQUEST_CANCEL,	/* request should be canceled. */
 };
 
 /* Tape CCW request */
@@ -237,6 +239,9 @@ struct tape_device {
 	/* Block dev frontend data */
 	struct tape_blk_data		blk_data;
 #endif
+
+	/* Function to start or stop the next request later. */
+	struct work_struct		tape_dnr;
 };
 
 /* Externals from tape_core.c */
diff --git a/drivers/s390/char/tape_core.c b/drivers/s390/char/tape_core.c
index 0597aa0e27e..6c52e8307dc 100644
--- a/drivers/s390/char/tape_core.c
+++ b/drivers/s390/char/tape_core.c
@@ -3,11 +3,12 @@
  *    basic function of the tape device driver
  *
  *  S390 and zSeries version
- *    Copyright (C) 2001,2002 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright (C) 2001,2005 IBM Deutschland Entwicklung GmbH, IBM Corporation
  *    Author(s): Carsten Otte <cotte@de.ibm.com>
  *		 Michael Holzheu <holzheu@de.ibm.com>
  *		 Tuan Ngo-Anh <ngoanh@de.ibm.com>
  *		 Martin Schwidefsky <schwidefsky@de.ibm.com>
+ *		 Stefan Bader <shbader@de.ibm.com>
  */
 
 #include <linux/config.h>
@@ -28,7 +29,7 @@
 #define PRINTK_HEADER "TAPE_CORE: "
 
 static void __tape_do_irq (struct ccw_device *, unsigned long, struct irb *);
-static void __tape_remove_request(struct tape_device *, struct tape_request *);
+static void tape_delayed_next_request(void * data);
 
 /*
  * One list to contain all tape devices of all disciplines, so
@@ -257,7 +258,7 @@ tape_med_state_set(struct tape_device *device, enum tape_medium_state newstate)
  * Stop running ccw. Has to be called with the device lock held.
  */
 static inline int
-__tape_halt_io(struct tape_device *device, struct tape_request *request)
+__tape_cancel_io(struct tape_device *device, struct tape_request *request)
 {
 	int retries;
 	int rc;
@@ -270,20 +271,23 @@ __tape_halt_io(struct tape_device *device, struct tape_request *request)
 	for (retries = 0; retries < 5; retries++) {
 		rc = ccw_device_clear(device->cdev, (long) request);
 
-		if (rc == 0) {                     /* Termination successful */
-			request->rc     = -EIO;
-			request->status = TAPE_REQUEST_DONE;
-			return 0;
+		switch (rc) {
+			case 0:
+				request->status	= TAPE_REQUEST_DONE;
+				return 0;
+			case -EBUSY:
+				request->status	= TAPE_REQUEST_CANCEL;
+				schedule_work(&device->tape_dnr);
+				return 0;
+			case -ENODEV:
+				DBF_EXCEPTION(2, "device gone, retry\n");
+				break;
+			case -EIO:
+				DBF_EXCEPTION(2, "I/O error, retry\n");
+				break;
+			default:
+				BUG();
 		}
-
-		if (rc == -ENODEV)
-			DBF_EXCEPTION(2, "device gone, retry\n");
-		else if (rc == -EIO)
-			DBF_EXCEPTION(2, "I/O error, retry\n");
-		else if (rc == -EBUSY)
-			DBF_EXCEPTION(2, "device busy, retry late\n");
-		else
-			BUG();
 	}
 
 	return rc;
@@ -473,6 +477,7 @@ tape_alloc_device(void)
 	*device->modeset_byte = 0;
 	device->first_minor = -1;
 	atomic_set(&device->ref_count, 1);
+	INIT_WORK(&device->tape_dnr, tape_delayed_next_request, device);
 
 	return device;
 }
@@ -708,54 +713,119 @@ tape_free_request (struct tape_request * request)
 	kfree(request);
 }
 
+static inline int
+__tape_start_io(struct tape_device *device, struct tape_request *request)
+{
+	int rc;
+
+#ifdef CONFIG_S390_TAPE_BLOCK
+	if (request->op == TO_BLOCK)
+		device->discipline->check_locate(device, request);
+#endif
+	rc = ccw_device_start(
+		device->cdev,
+		request->cpaddr,
+		(unsigned long) request,
+		0x00,
+		request->options
+	);
+	if (rc == 0) {
+		request->status = TAPE_REQUEST_IN_IO;
+	} else if (rc == -EBUSY) {
+		/* The common I/O subsystem is currently busy. Retry later. */
+		request->status = TAPE_REQUEST_QUEUED;
+		schedule_work(&device->tape_dnr);
+		rc = 0;
+	} else {
+		/* Start failed. Remove request and indicate failure. */
+		DBF_EVENT(1, "tape: start request failed with RC = %i\n", rc);
+	}
+	return rc;
+}
+
 static inline void
-__tape_do_io_list(struct tape_device *device)
+__tape_start_next_request(struct tape_device *device)
 {
 	struct list_head *l, *n;
 	struct tape_request *request;
 	int rc;
 
-	DBF_LH(6, "__tape_do_io_list(%p)\n", device);
+	DBF_LH(6, "__tape_start_next_request(%p)\n", device);
 	/*
 	 * Try to start each request on request queue until one is
 	 * started successful.
 	 */
 	list_for_each_safe(l, n, &device->req_queue) {
 		request = list_entry(l, struct tape_request, list);
-#ifdef CONFIG_S390_TAPE_BLOCK
-		if (request->op == TO_BLOCK)
-			device->discipline->check_locate(device, request);
-#endif
-		rc = ccw_device_start(device->cdev, request->cpaddr,
-				      (unsigned long) request, 0x00,
-				      request->options);
-		if (rc == 0) {
-			request->status = TAPE_REQUEST_IN_IO;
-			break;
+
+		/*
+		 * Avoid race condition if bottom-half was triggered more than
+		 * once.
+		 */
+		if (request->status == TAPE_REQUEST_IN_IO)
+			return;
+
+		/*
+		 * We wanted to cancel the request but the common I/O layer
+		 * was busy at that time. This can only happen if this
+		 * function is called by delayed_next_request.
+		 * Otherwise we start the next request on the queue.
+		 */
+		if (request->status == TAPE_REQUEST_CANCEL) {
+			rc = __tape_cancel_io(device, request);
+		} else {
+			rc = __tape_start_io(device, request);
 		}
-		/* Start failed. Remove request and indicate failure. */
-		DBF_EVENT(1, "tape: DOIO failed with er = %i\n", rc);
+		if (rc == 0)
+			return;
 
-		/* Set ending status and do callback. */
+		/* Set ending status. */
 		request->rc = rc;
 		request->status = TAPE_REQUEST_DONE;
-		__tape_remove_request(device, request);
+
+		/* Remove from request queue. */
+		list_del(&request->list);
+
+		/* Do callback. */
+		if (request->callback != NULL)
+			request->callback(request, request->callback_data);
 	}
 }
 
 static void
-__tape_remove_request(struct tape_device *device, struct tape_request *request)
+tape_delayed_next_request(void *data)
 {
-	/* Remove from request queue. */
-	list_del(&request->list);
+	struct tape_device *	device;
 
-	/* Do callback. */
-	if (request->callback != NULL)
-		request->callback(request, request->callback_data);
+	device = (struct tape_device *) data;
+	DBF_LH(6, "tape_delayed_next_request(%p)\n", device);
+	spin_lock_irq(get_ccwdev_lock(device->cdev));
+	__tape_start_next_request(device);
+	spin_unlock_irq(get_ccwdev_lock(device->cdev));
+}
+
+static inline void
+__tape_end_request(
+	struct tape_device *	device,
+	struct tape_request *	request,
+	int			rc)
+{
+	DBF_LH(6, "__tape_end_request(%p, %p, %i)\n", device, request, rc);
+	if (request) {
+		request->rc = rc;
+		request->status = TAPE_REQUEST_DONE;
+
+		/* Remove from request queue. */
+		list_del(&request->list);
+
+		/* Do callback. */
+		if (request->callback != NULL)
+			request->callback(request, request->callback_data);
+	}
 
 	/* Start next request. */
 	if (!list_empty(&device->req_queue))
-		__tape_do_io_list(device);
+		__tape_start_next_request(device);
 }
 
 /*
@@ -812,7 +882,7 @@ tape_dump_sense_dbf(struct tape_device *device, struct tape_request *request,
  * the device lock held.
  */
 static inline int
-__tape_do_io(struct tape_device *device, struct tape_request *request)
+__tape_start_request(struct tape_device *device, struct tape_request *request)
 {
 	int rc;
 
@@ -837,24 +907,16 @@ __tape_do_io(struct tape_device *device, struct tape_request *request)
 
 	if (list_empty(&device->req_queue)) {
 		/* No other requests are on the queue. Start this one. */
-#ifdef CONFIG_S390_TAPE_BLOCK
-		if (request->op == TO_BLOCK)
-			device->discipline->check_locate(device, request);
-#endif
-		rc = ccw_device_start(device->cdev, request->cpaddr,
-				      (unsigned long) request, 0x00,
-				      request->options);
-		if (rc) {
-			DBF_EVENT(1, "tape: DOIO failed with rc = %i\n", rc);
+		rc = __tape_start_io(device, request);
+		if (rc)
 			return rc;
-		}
+
 		DBF_LH(5, "Request %p added for execution.\n", request);
 		list_add(&request->list, &device->req_queue);
-		request->status = TAPE_REQUEST_IN_IO;
 	} else {
 		DBF_LH(5, "Request %p add to queue.\n", request);
-		list_add_tail(&request->list, &device->req_queue);
 		request->status = TAPE_REQUEST_QUEUED;
+		list_add_tail(&request->list, &device->req_queue);
 	}
 	return 0;
 }
@@ -872,7 +934,7 @@ tape_do_io_async(struct tape_device *device, struct tape_request *request)
 
 	spin_lock_irq(get_ccwdev_lock(device->cdev));
 	/* Add request to request queue and try to start it. */
-	rc = __tape_do_io(device, request);
+	rc = __tape_start_request(device, request);
 	spin_unlock_irq(get_ccwdev_lock(device->cdev));
 	return rc;
 }
@@ -901,7 +963,7 @@ tape_do_io(struct tape_device *device, struct tape_request *request)
 	request->callback = __tape_wake_up;
 	request->callback_data = &wq;
 	/* Add request to request queue and try to start it. */
-	rc = __tape_do_io(device, request);
+	rc = __tape_start_request(device, request);
 	spin_unlock_irq(get_ccwdev_lock(device->cdev));
 	if (rc)
 		return rc;
@@ -935,7 +997,7 @@ tape_do_io_interruptible(struct tape_device *device,
 	/* Setup callback */
 	request->callback = __tape_wake_up_interruptible;
 	request->callback_data = &wq;
-	rc = __tape_do_io(device, request);
+	rc = __tape_start_request(device, request);
 	spin_unlock_irq(get_ccwdev_lock(device->cdev));
 	if (rc)
 		return rc;
@@ -944,36 +1006,27 @@ tape_do_io_interruptible(struct tape_device *device,
 	if (rc != -ERESTARTSYS)
 		/* Request finished normally. */
 		return request->rc;
+
 	/* Interrupted by a signal. We have to stop the current request. */
 	spin_lock_irq(get_ccwdev_lock(device->cdev));
-	rc = __tape_halt_io(device, request);
+	rc = __tape_cancel_io(device, request);
+	spin_unlock_irq(get_ccwdev_lock(device->cdev));
 	if (rc == 0) {
+		/* Wait for the interrupt that acknowledges the halt. */
+		do {
+			rc = wait_event_interruptible(
+				wq,
+				(request->callback == NULL)
+			);
+		} while (rc != -ERESTARTSYS);
+
 		DBF_EVENT(3, "IO stopped on %08x\n", device->cdev_id);
 		rc = -ERESTARTSYS;
 	}
-	spin_unlock_irq(get_ccwdev_lock(device->cdev));
 	return rc;
 }
 
 /*
- * Handle requests that return an i/o error in the irb.
- */
-static inline void
-tape_handle_killed_request(
-	struct tape_device *device,
-	struct tape_request *request)
-{
-	if(request != NULL) {
-		/* Set ending status. FIXME: Should the request be retried? */
-		request->rc = -EIO;
-		request->status = TAPE_REQUEST_DONE;
-		__tape_remove_request(device, request);
-	} else {
-		__tape_do_io_list(device);
-	}
-}
-
-/*
  * Tape interrupt routine, called from the ccw_device layer
  */
 static void
@@ -981,7 +1034,6 @@ __tape_do_irq (struct ccw_device *cdev, unsigned long intparm, struct irb *irb)
 {
 	struct tape_device *device;
 	struct tape_request *request;
-	int final;
 	int rc;
 
 	device = (struct tape_device *) cdev->dev.driver_data;
@@ -996,12 +1048,13 @@ __tape_do_irq (struct ccw_device *cdev, unsigned long intparm, struct irb *irb)
 
 	/* On special conditions irb is an error pointer */
 	if (IS_ERR(irb)) {
+		/* FIXME: What to do with the request? */
 		switch (PTR_ERR(irb)) {
 			case -ETIMEDOUT:
 				PRINT_WARN("(%s): Request timed out\n",
 					cdev->dev.bus_id);
 			case -EIO:
-				tape_handle_killed_request(device, request);
+				__tape_end_request(device, request, -EIO);
 				break;
 			default:
 				PRINT_ERR("(%s): Unexpected i/o error %li\n",
@@ -1011,6 +1064,21 @@ __tape_do_irq (struct ccw_device *cdev, unsigned long intparm, struct irb *irb)
 		return;
 	}
 
+	/*
+	 * If the condition code is not zero and the start function bit is
+	 * still set, this is an deferred error and the last start I/O did
+	 * not succeed. Restart the request now.
+	 */
+	if (irb->scsw.cc != 0 && (irb->scsw.fctl & SCSW_FCTL_START_FUNC)) {
+		PRINT_WARN("(%s): deferred cc=%i. restaring\n",
+			cdev->dev.bus_id,
+			irb->scsw.cc);
+		rc = __tape_start_io(device, request);
+		if (rc)
+			__tape_end_request(device, request, rc);
+		return;
+	}
+
 	/* May be an unsolicited irq */
 	if(request != NULL)
 		request->rescnt = irb->scsw.count;
@@ -1042,7 +1110,7 @@ __tape_do_irq (struct ccw_device *cdev, unsigned long intparm, struct irb *irb)
 	 * To detect these request the state will be set to TAPE_REQUEST_DONE.
 	 */
 	if(request != NULL && request->status == TAPE_REQUEST_DONE) {
-		__tape_remove_request(device, request);
+		__tape_end_request(device, request, -EIO);
 		return;
 	}
 
@@ -1054,51 +1122,34 @@ __tape_do_irq (struct ccw_device *cdev, unsigned long intparm, struct irb *irb)
 	 * rc == TAPE_IO_RETRY: request finished but needs another go.
 	 * rc == TAPE_IO_STOP: request needs to get terminated.
 	 */
-	final = 0;
 	switch (rc) {
-	case TAPE_IO_SUCCESS:
-		/* Upon normal completion the device _is_ online */
-		device->tape_generic_status |= GMT_ONLINE(~0);
-		final = 1;
-		break;
-	case TAPE_IO_PENDING:
-		break;
-	case TAPE_IO_RETRY:
-#ifdef CONFIG_S390_TAPE_BLOCK
-		if (request->op == TO_BLOCK)
-			device->discipline->check_locate(device, request);
-#endif
-		rc = ccw_device_start(cdev, request->cpaddr,
-				      (unsigned long) request, 0x00,
-				      request->options);
-		if (rc) {
-			DBF_EVENT(1, "tape: DOIO failed with er = %i\n", rc);
-			final = 1;
-		}
-		break;
-	case TAPE_IO_STOP:
-		__tape_halt_io(device, request);
-		break;
-	default:
-		if (rc > 0) {
-			DBF_EVENT(6, "xunknownrc\n");
-			PRINT_ERR("Invalid return code from discipline "
-				  "interrupt function.\n");
-			rc = -EIO;
-		}
-		final = 1;
-		break;
-	}
-	if (final) {
-		/* May be an unsolicited irq */
-		if(request != NULL) {
-			/* Set ending status. */
-			request->rc = rc;
-			request->status = TAPE_REQUEST_DONE;
-			__tape_remove_request(device, request);
-		} else {
-			__tape_do_io_list(device);
-		}
+		case TAPE_IO_SUCCESS:
+			/* Upon normal completion the device _is_ online */
+			device->tape_generic_status |= GMT_ONLINE(~0);
+			__tape_end_request(device, request, rc);
+			break;
+		case TAPE_IO_PENDING:
+			break;
+		case TAPE_IO_RETRY:
+			rc = __tape_start_io(device, request);
+			if (rc)
+				__tape_end_request(device, request, rc);
+			break;
+		case TAPE_IO_STOP:
+			rc = __tape_cancel_io(device, request);
+			if (rc)
+				__tape_end_request(device, request, rc);
+			break;
+		default:
+			if (rc > 0) {
+				DBF_EVENT(6, "xunknownrc\n");
+				PRINT_ERR("Invalid return code from discipline "
+				  	"interrupt function.\n");
+				__tape_end_request(device, request, -EIO);
+			} else {
+				__tape_end_request(device, request, rc);
+			}
+			break;
 	}
 }
 
@@ -1191,7 +1242,7 @@ tape_init (void)
 #ifdef DBF_LIKE_HELL
 	debug_set_level(TAPE_DBF_AREA, 6);
 #endif
-	DBF_EVENT(3, "tape init: ($Revision: 1.51 $)\n");
+	DBF_EVENT(3, "tape init: ($Revision: 1.54 $)\n");
 	tape_proc_init();
 	tapechar_init ();
 	tapeblock_init ();
@@ -1216,7 +1267,7 @@ tape_exit(void)
 MODULE_AUTHOR("(C) 2001 IBM Deutschland Entwicklung GmbH by Carsten Otte and "
 	      "Michael Holzheu (cotte@de.ibm.com,holzheu@de.ibm.com)");
 MODULE_DESCRIPTION("Linux on zSeries channel attached "
-		   "tape device driver ($Revision: 1.51 $)");
+		   "tape device driver ($Revision: 1.54 $)");
 MODULE_LICENSE("GPL");
 
 module_init(tape_init);
diff --git a/drivers/s390/char/vmcp.c b/drivers/s390/char/vmcp.c
index 7f11a608a63..8990d8076e7 100644
--- a/drivers/s390/char/vmcp.c
+++ b/drivers/s390/char/vmcp.c
@@ -115,9 +115,9 @@ vmcp_write(struct file *file, const char __user * buff, size_t count,
 		return -ENOMEM;
 	}
 	debug_text_event(vmcp_debug, 1, cmd);
-	session->resp_size = cpcmd(cmd, session->response,
-				   session->bufsize,
-				   &session->resp_code);
+	session->resp_size = __cpcmd(cmd, session->response,
+				     session->bufsize,
+				     &session->resp_code);
 	up(&session->mutex);
 	kfree(cmd);
 	*ppos = 0;		/* reset the file pointer after a command */
diff --git a/drivers/s390/char/vmwatchdog.c b/drivers/s390/char/vmwatchdog.c
index 22cf4fec8da..5473c23fcb5 100644
--- a/drivers/s390/char/vmwatchdog.c
+++ b/drivers/s390/char/vmwatchdog.c
@@ -23,11 +23,7 @@
 static char vmwdt_cmd[MAX_CMDLEN] = "IPL";
 static int vmwdt_conceal;
 
-#ifdef CONFIG_WATCHDOG_NOWAYOUT
-static int vmwdt_nowayout = 1;
-#else
-static int vmwdt_nowayout = 0;
-#endif
+static int vmwdt_nowayout = WATCHDOG_NOWAYOUT;
 
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Arnd Bergmann <arndb@de.ibm.com>");
diff --git a/drivers/s390/cio/chsc.c b/drivers/s390/cio/chsc.c
index b86f94ecd87..fa3c23b80e3 100644
--- a/drivers/s390/cio/chsc.c
+++ b/drivers/s390/cio/chsc.c
@@ -1,7 +1,7 @@
 /*
  *  drivers/s390/cio/chsc.c
  *   S/390 common I/O routines -- channel subsystem call
- *   $Revision: 1.119 $
+ *   $Revision: 1.120 $
  *
  *    Copyright (C) 1999-2002 IBM Deutschland Entwicklung GmbH,
  *			      IBM Corporation
@@ -412,11 +412,7 @@ s390_process_res_acc (u8 chpid, __u16 fla, u32 fla_mask)
 		if (chp_mask == 0) {
 
 			spin_unlock_irq(&sch->lock);
-
-			if (fla_mask != 0)
-				break;
-			else
-				continue;
+			continue;
 		}
 		old_lpm = sch->lpm;
 		sch->lpm = ((sch->schib.pmcw.pim &
@@ -430,7 +426,7 @@ s390_process_res_acc (u8 chpid, __u16 fla, u32 fla_mask)
 
 		spin_unlock_irq(&sch->lock);
 		put_device(&sch->dev);
-		if (fla_mask != 0)
+		if (fla_mask == 0xffff)
 			break;
 	}
 	return rc;
diff --git a/drivers/s390/cio/device_fsm.c b/drivers/s390/cio/device_fsm.c
index 9b7f6f548b1..ee7a05e0c3b 100644
--- a/drivers/s390/cio/device_fsm.c
+++ b/drivers/s390/cio/device_fsm.c
@@ -235,6 +235,9 @@ ccw_device_recog_done(struct ccw_device *cdev, int state)
 		sch->schib.pmcw.pam &
 		sch->schib.pmcw.pom &
 		sch->opm;
+	/* Check since device may again have become not operational. */
+	if (!sch->schib.pmcw.dnv)
+		state = DEV_STATE_NOT_OPER;
 	if (cdev->private->state == DEV_STATE_DISCONNECTED_SENSE_ID)
 		/* Force reprobe on all chpids. */
 		old_lpm = 0;
diff --git a/drivers/s390/cio/device_status.c b/drivers/s390/cio/device_status.c
index 4ab2e0d9500..12a24d4331a 100644
--- a/drivers/s390/cio/device_status.c
+++ b/drivers/s390/cio/device_status.c
@@ -39,15 +39,14 @@ ccw_device_msg_control_check(struct ccw_device *cdev, struct irb *irb)
 		      " ... device %04X on subchannel %04X, dev_stat "
 		      ": %02X sch_stat : %02X\n",
 		      cdev->private->devno, cdev->private->irq,
-		      cdev->private->irb.scsw.dstat,
-		      cdev->private->irb.scsw.cstat);
+		      irb->scsw.dstat, irb->scsw.cstat);
 
 	if (irb->scsw.cc != 3) {
 		char dbf_text[15];
 
 		sprintf(dbf_text, "chk%x", cdev->private->irq);
 		CIO_TRACE_EVENT(0, dbf_text);
-		CIO_HEX_EVENT(0, &cdev->private->irb, sizeof (struct irb));
+		CIO_HEX_EVENT(0, irb, sizeof (struct irb));
 	}
 }
 
diff --git a/drivers/s390/cio/qdio.c b/drivers/s390/cio/qdio.c
index 82194c4eadf..d36258d6665 100644
--- a/drivers/s390/cio/qdio.c
+++ b/drivers/s390/cio/qdio.c
@@ -432,7 +432,7 @@ tiqdio_clear_global_summary(void)
 
 /************************* OUTBOUND ROUTINES *******************************/
 
-inline static int
+static inline int
 qdio_get_outbound_buffer_frontier(struct qdio_q *q)
 {
 	int f,f_mod_no;
@@ -510,7 +510,7 @@ out:
 }
 
 /* all buffers are processed */
-inline static int
+static inline int
 qdio_is_outbound_q_done(struct qdio_q *q)
 {
 	int no_used;
@@ -532,7 +532,7 @@ qdio_is_outbound_q_done(struct qdio_q *q)
 	return (no_used==0);
 }
 
-inline static int
+static inline int
 qdio_has_outbound_q_moved(struct qdio_q *q)
 {
 	int i;
@@ -552,7 +552,7 @@ qdio_has_outbound_q_moved(struct qdio_q *q)
 	}
 }
 
-inline static void
+static inline void
 qdio_kick_outbound_q(struct qdio_q *q)
 {
 	int result;
@@ -641,7 +641,7 @@ qdio_kick_outbound_q(struct qdio_q *q)
 		}
 }
 
-inline static void
+static inline void
 qdio_kick_outbound_handler(struct qdio_q *q)
 {
 	int start, end, real_end, count;
@@ -740,7 +740,7 @@ qdio_outbound_processing(struct qdio_q *q)
 /************************* INBOUND ROUTINES *******************************/
 
 
-inline static int
+static inline int
 qdio_get_inbound_buffer_frontier(struct qdio_q *q)
 {
 	int f,f_mod_no;
@@ -865,7 +865,7 @@ out:
 	return q->first_to_check;
 }
 
-inline static int
+static inline int
 qdio_has_inbound_q_moved(struct qdio_q *q)
 {
 	int i;
@@ -898,7 +898,7 @@ qdio_has_inbound_q_moved(struct qdio_q *q)
 }
 
 /* means, no more buffers to be filled */
-inline static int
+static inline int
 tiqdio_is_inbound_q_done(struct qdio_q *q)
 {
 	int no_used;
@@ -951,7 +951,7 @@ tiqdio_is_inbound_q_done(struct qdio_q *q)
 	return 0;
 }
 
-inline static int
+static inline int
 qdio_is_inbound_q_done(struct qdio_q *q)
 {
 	int no_used;
@@ -1010,7 +1010,7 @@ qdio_is_inbound_q_done(struct qdio_q *q)
 	}
 }
 
-inline static void
+static inline void
 qdio_kick_inbound_handler(struct qdio_q *q)
 {
 	int count, start, end, real_end, i;
diff --git a/drivers/s390/net/qeth.h b/drivers/s390/net/qeth.h
index 008e0a5d2eb..3a0285669ad 100644
--- a/drivers/s390/net/qeth.h
+++ b/drivers/s390/net/qeth.h
@@ -824,7 +824,7 @@ extern struct list_head qeth_notify_list;
 
 #define QETH_CARD_IFNAME(card) (((card)->dev)? (card)->dev->name : "")
 
-inline static __u8
+static inline __u8
 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
 {
 	switch (link_type) {
@@ -835,7 +835,7 @@ qeth_get_ipa_adp_type(enum qeth_link_types link_type)
 	}
 }
 
-inline static int
+static inline int
 qeth_realloc_headroom(struct qeth_card *card, struct sk_buff **skb, int size)
 {
 	struct sk_buff *new_skb = NULL;
@@ -852,6 +852,7 @@ qeth_realloc_headroom(struct qeth_card *card, struct sk_buff **skb, int size)
 	}
 	return 0;
 }
+
 static inline struct sk_buff *
 qeth_pskb_unshare(struct sk_buff *skb, int pri)
 {
@@ -863,8 +864,7 @@ qeth_pskb_unshare(struct sk_buff *skb, int pri)
         return nskb;
 }
 
-
-inline static void *
+static inline void *
 qeth_push_skb(struct qeth_card *card, struct sk_buff **skb, int size)
 {
         void *hdr;
@@ -887,7 +887,7 @@ qeth_push_skb(struct qeth_card *card, struct sk_buff **skb, int size)
 }
 
 
-inline static int
+static inline int
 qeth_get_hlen(__u8 link_type)
 {
 #ifdef CONFIG_QETH_IPV6
@@ -911,7 +911,7 @@ qeth_get_hlen(__u8 link_type)
 #endif /* CONFIG_QETH_IPV6 */
 }
 
-inline static unsigned short
+static inline unsigned short
 qeth_get_netdev_flags(struct qeth_card *card)
 {
 	if (card->options.layer2)
@@ -929,7 +929,7 @@ qeth_get_netdev_flags(struct qeth_card *card)
 	}
 }
 
-inline static int
+static inline int
 qeth_get_initial_mtu_for_card(struct qeth_card * card)
 {
 	switch (card->info.type) {
@@ -950,7 +950,7 @@ qeth_get_initial_mtu_for_card(struct qeth_card * card)
 	}
 }
 
-inline static int
+static inline int
 qeth_get_max_mtu_for_card(int cardtype)
 {
 	switch (cardtype) {
@@ -965,7 +965,7 @@ qeth_get_max_mtu_for_card(int cardtype)
 	}
 }
 
-inline static int
+static inline int
 qeth_get_mtu_out_of_mpc(int cardtype)
 {
 	switch (cardtype) {
@@ -976,7 +976,7 @@ qeth_get_mtu_out_of_mpc(int cardtype)
 	}
 }
 
-inline static int
+static inline int
 qeth_get_mtu_outof_framesize(int framesize)
 {
 	switch (framesize) {
@@ -993,7 +993,7 @@ qeth_get_mtu_outof_framesize(int framesize)
 	}
 }
 
-inline static int
+static inline int
 qeth_mtu_is_valid(struct qeth_card * card, int mtu)
 {
 	switch (card->info.type) {
@@ -1008,7 +1008,7 @@ qeth_mtu_is_valid(struct qeth_card * card, int mtu)
 	}
 }
 
-inline static int
+static inline int
 qeth_get_arphdr_type(int cardtype, int linktype)
 {
 	switch (cardtype) {
@@ -1027,7 +1027,7 @@ qeth_get_arphdr_type(int cardtype, int linktype)
 }
 
 #ifdef CONFIG_QETH_PERF_STATS
-inline static int
+static inline int
 qeth_get_micros(void)
 {
 	return (int) (get_clock() >> 12);
diff --git a/drivers/s390/net/qeth_main.c b/drivers/s390/net/qeth_main.c
index 8f4d2999af8..79c74f3a11f 100644
--- a/drivers/s390/net/qeth_main.c
+++ b/drivers/s390/net/qeth_main.c
@@ -8120,20 +8120,22 @@ static struct notifier_block qeth_ip6_notifier = {
 #endif
 
 static int
-qeth_reboot_event(struct notifier_block *this, unsigned long event, void *ptr)
+__qeth_reboot_event_card(struct device *dev, void *data)
 {
-
-	struct device *entry;
 	struct qeth_card *card;
 
-	down_read(&qeth_ccwgroup_driver.driver.bus->subsys.rwsem);
-	       list_for_each_entry(entry, &qeth_ccwgroup_driver.driver.devices,
-			           driver_list) {
-	               card = (struct qeth_card *) entry->driver_data;
-		       qeth_clear_ip_list(card, 0, 0);
-		       qeth_qdio_clear_card(card, 0);
-	       }
-	up_read(&qeth_ccwgroup_driver.driver.bus->subsys.rwsem);
+	card = (struct qeth_card *) dev->driver_data;
+	qeth_clear_ip_list(card, 0, 0);
+	qeth_qdio_clear_card(card, 0);
+	return 0;
+}
+
+static int
+qeth_reboot_event(struct notifier_block *this, unsigned long event, void *ptr)
+{
+
+	driver_for_each_device(&qeth_ccwgroup_driver.driver, NULL, NULL,
+			       __qeth_reboot_event_card);
 	return NOTIFY_DONE;
 }
 
diff --git a/drivers/s390/net/qeth_proc.c b/drivers/s390/net/qeth_proc.c
index 04719196fd2..f2ccfea8fdb 100644
--- a/drivers/s390/net/qeth_proc.c
+++ b/drivers/s390/net/qeth_proc.c
@@ -27,23 +27,33 @@ const char *VERSION_QETH_PROC_C = "$Revision: 1.13 $";
 #define QETH_PROCFILE_NAME "qeth"
 static struct proc_dir_entry *qeth_procfile;
 
+static int
+qeth_procfile_seq_match(struct device *dev, void *data)
+{
+	return 1;
+}
+
 static void *
 qeth_procfile_seq_start(struct seq_file *s, loff_t *offset)
 {
-	struct list_head *next_card = NULL;
-	int i = 0;
+	struct device *dev;
+	loff_t nr;
 
 	down_read(&qeth_ccwgroup_driver.driver.bus->subsys.rwsem);
 
-	if (*offset == 0)
+	nr = *offset;
+	if (nr == 0)
 		return SEQ_START_TOKEN;
 
-	/* get card at pos *offset */
-	list_for_each(next_card, &qeth_ccwgroup_driver.driver.devices)
-		if (++i == *offset)
-			return next_card;
+	dev = driver_find_device(&qeth_ccwgroup_driver.driver, NULL,
+				 NULL, qeth_procfile_seq_match);
 
-	return NULL;
+	/* get card at pos *offset */
+	nr = *offset;
+	while (nr-- > 1 && dev)
+		dev = driver_find_device(&qeth_ccwgroup_driver.driver, dev,
+					 NULL, qeth_procfile_seq_match);
+	return (void *) dev;
 }
 
 static void
@@ -55,23 +65,21 @@ qeth_procfile_seq_stop(struct seq_file *s, void* it)
 static void *
 qeth_procfile_seq_next(struct seq_file *s, void *it, loff_t *offset)
 {
-	struct list_head *next_card = NULL;
-	struct list_head *current_card;
+	struct device *prev, *next;
 
 	if (it == SEQ_START_TOKEN) {
-		next_card = qeth_ccwgroup_driver.driver.devices.next;
-		if (next_card->next == next_card) /* list empty */
-			return NULL;
-		(*offset)++;
-	} else {
-		current_card = (struct list_head *)it;
-		if (current_card->next == &qeth_ccwgroup_driver.driver.devices)
-			return NULL; /* end of list reached */
-		next_card = current_card->next;
-		(*offset)++;
+		next = driver_find_device(&qeth_ccwgroup_driver.driver,
+					  NULL, NULL, qeth_procfile_seq_match);
+		if (next)
+			(*offset)++;
+		return (void *) next;
 	}
-
-	return next_card;
+	prev = (struct device *) it;
+	next = driver_find_device(&qeth_ccwgroup_driver.driver,
+				  prev, NULL, qeth_procfile_seq_match);
+	if (next)
+		(*offset)++;
+	return (void *) next;
 }
 
 static inline const char *
@@ -126,7 +134,7 @@ qeth_procfile_seq_show(struct seq_file *s, void *it)
 			      "-------------- ---- ------ ---------- ---- "
 			      "---- ----- -----\n");
 	} else {
-		device = list_entry(it, struct device, driver_list);
+		device = (struct device *) it;
 		card = device->driver_data;
 		seq_printf(s, "%s/%s/%s x%02X   %-10s %-14s %-4i ",
 				CARD_RDEV_ID(card),
@@ -180,17 +188,20 @@ static struct proc_dir_entry *qeth_perf_procfile;
 static void *
 qeth_perf_procfile_seq_start(struct seq_file *s, loff_t *offset)
 {
-	struct list_head *next_card = NULL;
-	int i = 0;
+	struct device *dev = NULL;
+	int nr;
 
 	down_read(&qeth_ccwgroup_driver.driver.bus->subsys.rwsem);
 	/* get card at pos *offset */
-	list_for_each(next_card, &qeth_ccwgroup_driver.driver.devices){
-		if (i == *offset)
-			return next_card;
-		i++;
-	}
-	return NULL;
+	dev = driver_find_device(&qeth_ccwgroup_driver.driver, NULL, NULL,
+				 qeth_procfile_seq_match);
+
+	/* get card at pos *offset */
+	nr = *offset;
+	while (nr-- > 1 && dev)
+		dev = driver_find_device(&qeth_ccwgroup_driver.driver, dev,
+					 NULL, qeth_procfile_seq_match);
+	return (void *) dev;
 }
 
 static void
@@ -202,12 +213,14 @@ qeth_perf_procfile_seq_stop(struct seq_file *s, void* it)
 static void *
 qeth_perf_procfile_seq_next(struct seq_file *s, void *it, loff_t *offset)
 {
-	struct list_head *current_card = (struct list_head *)it;
+	struct device *prev, *next;
 
-	if (current_card->next == &qeth_ccwgroup_driver.driver.devices)
-		return NULL; /* end of list reached */
-	(*offset)++;
-	return current_card->next;
+	prev = (struct device *) it;
+	next = driver_find_device(&qeth_ccwgroup_driver.driver, prev,
+				  NULL, qeth_procfile_seq_match);
+	if (next)
+		(*offset)++;
+	return (void *) next;
 }
 
 static int
@@ -216,7 +229,7 @@ qeth_perf_procfile_seq_show(struct seq_file *s, void *it)
 	struct device *device;
 	struct qeth_card *card;
 
-	device = list_entry(it, struct device, driver_list);
+	device = (struct device *) it;
 	card = device->driver_data;
 	seq_printf(s, "For card with devnos %s/%s/%s (%s):\n",
 			CARD_RDEV_ID(card),
@@ -318,8 +331,8 @@ static struct proc_dir_entry *qeth_ipato_procfile;
 static void *
 qeth_ipato_procfile_seq_start(struct seq_file *s, loff_t *offset)
 {
-	struct list_head *next_card = NULL;
-	int i = 0;
+	struct device *dev;
+	loff_t nr;
 
 	down_read(&qeth_ccwgroup_driver.driver.bus->subsys.rwsem);
 	/* TODO: finish this */
@@ -328,13 +341,16 @@ qeth_ipato_procfile_seq_start(struct seq_file *s, loff_t *offset)
 	 * output driver settings then;
 	 * else output setting for respective card
 	 */
+
+	dev = driver_find_device(&qeth_ccwgroup_driver.driver, NULL, NULL,
+				 qeth_procfile_seq_match);
+
 	/* get card at pos *offset */
-	list_for_each(next_card, &qeth_ccwgroup_driver.driver.devices){
-		if (i == *offset)
-			return next_card;
-		i++;
-	}
-	return NULL;
+	nr = *offset;
+	while (nr-- > 1 && dev)
+		dev = driver_find_device(&qeth_ccwgroup_driver.driver, dev,
+					 NULL, qeth_procfile_seq_match);
+	return (void *) dev;
 }
 
 static void
@@ -346,18 +362,14 @@ qeth_ipato_procfile_seq_stop(struct seq_file *s, void* it)
 static void *
 qeth_ipato_procfile_seq_next(struct seq_file *s, void *it, loff_t *offset)
 {
-	struct list_head *current_card = (struct list_head *)it;
+	struct device *prev, *next;
 
-	/* TODO: finish this */
-	/*
-	 * maybe SEQ_SATRT_TOKEN can be returned for offset 0
-	 * output driver settings then;
-	 * else output setting for respective card
-	 */
-	if (current_card->next == &qeth_ccwgroup_driver.driver.devices)
-		return NULL; /* end of list reached */
-	(*offset)++;
-	return current_card->next;
+	prev = (struct device *) it;
+	next = driver_find_device(&qeth_ccwgroup_driver.driver, prev,
+				  NULL, qeth_procfile_seq_match);
+	if (next)
+		(*offset)++;
+	return (void *) next;
 }
 
 static int
@@ -372,7 +384,7 @@ qeth_ipato_procfile_seq_show(struct seq_file *s, void *it)
 	 * output driver settings then;
 	 * else output setting for respective card
 	 */
-	device = list_entry(it, struct device, driver_list);
+	device = (struct device *) it;
 	card = device->driver_data;
 
 	return 0;
diff --git a/drivers/sbus/char/vfc.h b/drivers/sbus/char/vfc.h
index e56a43af0f6..a7782e7da42 100644
--- a/drivers/sbus/char/vfc.h
+++ b/drivers/sbus/char/vfc.h
@@ -129,8 +129,6 @@ struct vfc_dev {
 	struct vfc_regs *phys_regs;
 	unsigned int control_reg;
 	struct semaphore device_lock_sem;
-	struct timer_list poll_timer;
-	wait_queue_head_t poll_wait;
 	int instance;
 	int busy;
 	unsigned long which_io;
diff --git a/drivers/sbus/char/vfc_dev.c b/drivers/sbus/char/vfc_dev.c
index 86ce5413095..7a103698fa3 100644
--- a/drivers/sbus/char/vfc_dev.c
+++ b/drivers/sbus/char/vfc_dev.c
@@ -137,7 +137,6 @@ int init_vfc_devstruct(struct vfc_dev *dev, int instance)
 	dev->instance=instance;
 	init_MUTEX(&dev->device_lock_sem);
 	dev->control_reg=0;
-	init_waitqueue_head(&dev->poll_wait);
 	dev->busy=0;
 	return 0;
 }
diff --git a/drivers/sbus/char/vfc_i2c.c b/drivers/sbus/char/vfc_i2c.c
index 1faf1e75f71..739cad9b19a 100644
--- a/drivers/sbus/char/vfc_i2c.c
+++ b/drivers/sbus/char/vfc_i2c.c
@@ -79,25 +79,10 @@ int vfc_pcf8584_init(struct vfc_dev *dev)
 	return 0;
 }
 
-void vfc_i2c_delay_wakeup(struct vfc_dev *dev) 
-{
-	/* Used to profile code and eliminate too many delays */
-	VFC_I2C_DEBUG_PRINTK(("vfc%d: Delaying\n", dev->instance));
-	wake_up(&dev->poll_wait);
-}
-
 void vfc_i2c_delay_no_busy(struct vfc_dev *dev, unsigned long usecs) 
 {
-	DEFINE_WAIT(wait);
-	init_timer(&dev->poll_timer);
-	dev->poll_timer.expires = jiffies + usecs_to_jiffies(usecs);
-	dev->poll_timer.data=(unsigned long)dev;
-	dev->poll_timer.function=(void *)(unsigned long)vfc_i2c_delay_wakeup;
-	add_timer(&dev->poll_timer);
-	prepare_to_wait(&dev->poll_wait, &wait, TASK_UNINTERRUPTIBLE);
-	schedule();
-	del_timer(&dev->poll_timer);
-	finish_wait(&dev->poll_wait, &wait);
+	set_current_state(TASK_UNINTERRUPTIBLE);
+	schedule_timeout(usecs_to_jiffies(usecs));
 }
 
 void inline vfc_i2c_delay(struct vfc_dev *dev) 
diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig
index 96df148ed96..f1e8c4223ed 100644
--- a/drivers/scsi/Kconfig
+++ b/drivers/scsi/Kconfig
@@ -424,7 +424,7 @@ config SCSI_IN2000
 source "drivers/scsi/megaraid/Kconfig.megaraid"
 
 config SCSI_SATA
-	bool "Serial ATA (SATA) support"
+	tristate "Serial ATA (SATA) support"
 	depends on SCSI
 	help
 	  This driver family supports Serial ATA host controllers
diff --git a/drivers/scsi/NCR53c406a.c b/drivers/scsi/NCR53c406a.c
index b2002ba6e2a..79ae73b2368 100644
--- a/drivers/scsi/NCR53c406a.c
+++ b/drivers/scsi/NCR53c406a.c
@@ -182,13 +182,13 @@ static int irq_probe(void);
 static void *bios_base;
 #endif
 
-#if PORT_BASE
+#ifdef PORT_BASE
 static int port_base = PORT_BASE;
 #else
 static int port_base;
 #endif
 
-#if IRQ_LEV
+#ifdef IRQ_LEV
 static int irq_level = IRQ_LEV;
 #else
 static int irq_level = -1;	/* 0 is 'no irq', so use -1 for 'uninitialized' */
diff --git a/drivers/scsi/aacraid/aacraid.h b/drivers/scsi/aacraid/aacraid.h
index 3a11a536c0d..4ab07861b45 100644
--- a/drivers/scsi/aacraid/aacraid.h
+++ b/drivers/scsi/aacraid/aacraid.h
@@ -15,11 +15,7 @@
 #define AAC_MAX_LUN		(8)
 
 #define AAC_MAX_HOSTPHYSMEMPAGES (0xfffff)
-/*
- *  max_sectors is an unsigned short, otherwise limit is 0x100000000 / 512
- * Linux has starvation problems if we permit larger than 4MB I/O ...
- */
-#define AAC_MAX_32BIT_SGBCOUNT	((unsigned short)8192)
+#define AAC_MAX_32BIT_SGBCOUNT	((unsigned short)512)
 
 /*
  * These macros convert from physical channels to virtual channels
diff --git a/drivers/scsi/aacraid/linit.c b/drivers/scsi/aacraid/linit.c
index c1a4f978fcb..562da90480a 100644
--- a/drivers/scsi/aacraid/linit.c
+++ b/drivers/scsi/aacraid/linit.c
@@ -374,7 +374,8 @@ static int aac_slave_configure(struct scsi_device *sdev)
 	else
 		scsi_adjust_queue_depth(sdev, 0, 1);
 
-	if (host->max_sectors < AAC_MAX_32BIT_SGBCOUNT)
+	if (!(((struct aac_dev *)host->hostdata)->adapter_info.options
+	  & AAC_OPT_NEW_COMM))
 		blk_queue_max_segment_size(sdev->request_queue, 65536);
 
 	return 0;
diff --git a/drivers/scsi/aic7xxx/aic79xx_osm.c b/drivers/scsi/aic7xxx/aic79xx_osm.c
index 6466a184a14..329cb233133 100644
--- a/drivers/scsi/aic7xxx/aic79xx_osm.c
+++ b/drivers/scsi/aic7xxx/aic79xx_osm.c
@@ -1505,7 +1505,7 @@ ahd_linux_dev_reset(Scsi_Cmnd *cmd)
 	memset(recovery_cmd, 0, sizeof(struct scsi_cmnd));
 	recovery_cmd->device = cmd->device;
 	recovery_cmd->scsi_done = ahd_linux_dev_reset_complete;
-#if AHD_DEBUG
+#ifdef AHD_DEBUG
 	if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
 		printf("%s:%d:%d:%d: Device reset called for cmd %p\n",
 		       ahd_name(ahd), cmd->device->channel, cmd->device->id,
diff --git a/drivers/scsi/aic7xxx/aic79xx_pci.c b/drivers/scsi/aic7xxx/aic79xx_pci.c
index 4c3bb7bb842..703f6e44889 100644
--- a/drivers/scsi/aic7xxx/aic79xx_pci.c
+++ b/drivers/scsi/aic7xxx/aic79xx_pci.c
@@ -582,7 +582,7 @@ ahd_check_extport(struct ahd_softc *ahd)
 		}
 	}
 
-#if AHD_DEBUG
+#ifdef AHD_DEBUG
 	if (have_seeprom != 0
 	 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) {
 		uint16_t *sc_data;
diff --git a/drivers/scsi/aic7xxx/aic7xxx_osm.c b/drivers/scsi/aic7xxx/aic7xxx_osm.c
index 116d0f51ca2..687f19e9cf0 100644
--- a/drivers/scsi/aic7xxx/aic7xxx_osm.c
+++ b/drivers/scsi/aic7xxx/aic7xxx_osm.c
@@ -1264,14 +1264,12 @@ ahc_platform_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
 	}
 	switch ((dev->flags & (AHC_DEV_Q_BASIC|AHC_DEV_Q_TAGGED))) {
 	case AHC_DEV_Q_BASIC:
-		scsi_adjust_queue_depth(sdev,
-					MSG_SIMPLE_TASK,
-					dev->openings + dev->active);
+		scsi_set_tag_type(sdev, MSG_SIMPLE_TAG);
+		scsi_activate_tcq(sdev, dev->openings + dev->active);
 		break;
 	case AHC_DEV_Q_TAGGED:
-		scsi_adjust_queue_depth(sdev,
-					MSG_ORDERED_TASK,
-					dev->openings + dev->active);
+		scsi_set_tag_type(sdev, MSG_ORDERED_TAG);
+		scsi_activate_tcq(sdev, dev->openings + dev->active);
 		break;
 	default:
 		/*
@@ -1280,9 +1278,7 @@ ahc_platform_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
 		 * serially on the controller/device.  This should
 		 * remove some latency.
 		 */
-		scsi_adjust_queue_depth(sdev,
-					/*NON-TAGGED*/0,
-					/*queue depth*/2);
+		scsi_deactivate_tcq(sdev, 2);
 		break;
 	}
 }
@@ -1635,9 +1631,9 @@ ahc_send_async(struct ahc_softc *ahc, char channel,
 		spi_period(starget) = tinfo->curr.period;
 		spi_width(starget) = tinfo->curr.width;
 		spi_offset(starget) = tinfo->curr.offset;
-		spi_dt(starget) = tinfo->curr.ppr_options & MSG_EXT_PPR_DT_REQ;
-		spi_qas(starget) = tinfo->curr.ppr_options & MSG_EXT_PPR_QAS_REQ;
-		spi_iu(starget) = tinfo->curr.ppr_options & MSG_EXT_PPR_IU_REQ;
+		spi_dt(starget) = tinfo->curr.ppr_options & MSG_EXT_PPR_DT_REQ ? 1 : 0;
+		spi_qas(starget) = tinfo->curr.ppr_options & MSG_EXT_PPR_QAS_REQ ? 1 : 0;
+		spi_iu(starget) = tinfo->curr.ppr_options & MSG_EXT_PPR_IU_REQ ? 1 : 0;
 		spi_display_xfer_agreement(starget);
 		break;
 	}
@@ -2429,12 +2425,14 @@ static void ahc_linux_set_dt(struct scsi_target *starget, int dt)
 	unsigned int ppr_options = tinfo->goal.ppr_options
 		& ~MSG_EXT_PPR_DT_REQ;
 	unsigned int period = tinfo->goal.period;
+	unsigned int width = tinfo->goal.width;
 	unsigned long flags;
 	struct ahc_syncrate *syncrate;
 
 	if (dt) {
-		period = 9;	/* 12.5ns is the only period valid for DT */
 		ppr_options |= MSG_EXT_PPR_DT_REQ;
+		if (!width)
+			ahc_linux_set_width(starget, 1);
 	} else if (period == 9)
 		period = 10;	/* if resetting DT, period must be >= 25ns */
 
diff --git a/drivers/scsi/aic7xxx/aicasm/aicasm.c b/drivers/scsi/aic7xxx/aicasm/aicasm.c
index c3463948190..f936b691232 100644
--- a/drivers/scsi/aic7xxx/aicasm/aicasm.c
+++ b/drivers/scsi/aic7xxx/aicasm/aicasm.c
@@ -369,7 +369,7 @@ output_code()
 
 		fprintf(ofile, "%s\t0x%02x, 0x%02x, 0x%02x, 0x%02x",
 			cur_instr == STAILQ_FIRST(&seq_program) ? "" : ",\n",
-#if BYTE_ORDER == LITTLE_ENDIAN
+#ifdef __LITTLE_ENDIAN
 			cur_instr->format.bytes[0],
 			cur_instr->format.bytes[1],
 			cur_instr->format.bytes[2],
@@ -613,7 +613,7 @@ output_listing(char *ifilename)
 				line++;
 		}
 		fprintf(listfile, "%03x %02x%02x%02x%02x", instrptr,
-#if BYTE_ORDER == LITTLE_ENDIAN
+#ifdef __LITTLE_ENDIAN
 			cur_instr->format.bytes[0],
 			cur_instr->format.bytes[1],
 			cur_instr->format.bytes[2],
diff --git a/drivers/scsi/aic7xxx/aicasm/aicasm_insformat.h b/drivers/scsi/aic7xxx/aicasm/aicasm_insformat.h
index 3e80f07df49..e64f802bbaa 100644
--- a/drivers/scsi/aic7xxx/aicasm/aicasm_insformat.h
+++ b/drivers/scsi/aic7xxx/aicasm/aicasm_insformat.h
@@ -42,8 +42,10 @@
  * $FreeBSD$
  */
 
+#include <asm/byteorder.h>
+
 struct ins_format1 {
-#if BYTE_ORDER == LITTLE_ENDIAN
+#ifdef __LITTLE_ENDIAN
 	uint32_t	immediate	: 8,
 			source		: 9,
 			destination	: 9,
@@ -61,7 +63,7 @@ struct ins_format1 {
 };
 
 struct ins_format2 {
-#if BYTE_ORDER == LITTLE_ENDIAN
+#ifdef __LITTLE_ENDIAN
 	uint32_t	shift_control	: 8,
 			source		: 9,
 			destination	: 9,
@@ -79,7 +81,7 @@ struct ins_format2 {
 };
 
 struct ins_format3 {
-#if BYTE_ORDER == LITTLE_ENDIAN
+#ifdef __LITTLE_ENDIAN
 	uint32_t	immediate	: 8,
 			source		: 9,
 			address		: 10,
diff --git a/drivers/scsi/ata_piix.c b/drivers/scsi/ata_piix.c
index 3be54643925..a2cfade2c1c 100644
--- a/drivers/scsi/ata_piix.c
+++ b/drivers/scsi/ata_piix.c
@@ -38,6 +38,7 @@ enum {
 	PIIX_IOCFG		= 0x54, /* IDE I/O configuration register */
 	ICH5_PMR		= 0x90, /* port mapping register */
 	ICH5_PCS		= 0x92,	/* port control and status */
+	PIIX_SCC		= 0x0A, /* sub-class code register */
 
 	PIIX_FLAG_AHCI		= (1 << 28), /* AHCI possible */
 	PIIX_FLAG_CHECKINTR	= (1 << 29), /* make sure PCI INTx enabled */
@@ -62,6 +63,8 @@ enum {
 	ich6_sata_rm		= 4,
 	ich7_sata		= 5,
 	esb2_sata		= 6,
+
+	PIIX_AHCI_DEVICE	= 6,
 };
 
 static int piix_init_one (struct pci_dev *pdev,
@@ -574,11 +577,11 @@ static int piix_disable_ahci(struct pci_dev *pdev)
 	addr = pci_resource_start(pdev, AHCI_PCI_BAR);
 	if (!addr || !pci_resource_len(pdev, AHCI_PCI_BAR))
 		return 0;
-	
+
 	mmio = ioremap(addr, 64);
 	if (!mmio)
 		return -ENOMEM;
-	
+
 	tmp = readl(mmio + AHCI_GLOBAL_CTL);
 	if (tmp & AHCI_ENABLE) {
 		tmp &= ~AHCI_ENABLE;
@@ -588,7 +591,7 @@ static int piix_disable_ahci(struct pci_dev *pdev)
 		if (tmp & AHCI_ENABLE)
 			rc = -EIO;
 	}
-	
+
 	iounmap(mmio);
 	return rc;
 }
@@ -626,9 +629,13 @@ static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
 	port_info[1] = NULL;
 
 	if (port_info[0]->host_flags & PIIX_FLAG_AHCI) {
-		int rc = piix_disable_ahci(pdev);
-		if (rc)
-			return rc;
+               u8 tmp;
+               pci_read_config_byte(pdev, PIIX_SCC, &tmp);
+               if (tmp == PIIX_AHCI_DEVICE) {
+                       int rc = piix_disable_ahci(pdev);
+                       if (rc)
+                           return rc;
+               }
 	}
 
 	if (port_info[0]->host_flags & PIIX_FLAG_COMBINED) {
diff --git a/drivers/scsi/dc395x.c b/drivers/scsi/dc395x.c
index ae13c002f60..929170dcd3c 100644
--- a/drivers/scsi/dc395x.c
+++ b/drivers/scsi/dc395x.c
@@ -744,7 +744,7 @@ static void free_tag(struct DeviceCtlBlk *dcb, struct ScsiReqBlk *srb)
 
 
 /* Find cmd in SRB list */
-inline static struct ScsiReqBlk *find_cmd(struct scsi_cmnd *cmd, 
+static inline struct ScsiReqBlk *find_cmd(struct scsi_cmnd *cmd,
 		struct list_head *head)
 {
 	struct ScsiReqBlk *i;
diff --git a/drivers/scsi/dpt/dptsig.h b/drivers/scsi/dpt/dptsig.h
index 95a4cce6c89..4bf44779212 100644
--- a/drivers/scsi/dpt/dptsig.h
+++ b/drivers/scsi/dpt/dptsig.h
@@ -76,7 +76,7 @@ typedef unsigned long sigLONG;
 #endif  /* aix */
 #endif
 /* For the Macintosh */
-#if STRUCTALIGNMENTSUPPORTED
+#ifdef STRUCTALIGNMENTSUPPORTED
 #pragma options align=mac68k
 #endif
 
@@ -332,7 +332,7 @@ typedef struct dpt_sig {
 #endif  /* aix */
 #endif
 /* For the Macintosh */
-#if STRUCTALIGNMENTSUPPORTED
+#ifdef STRUCTALIGNMENTSUPPORTED
 #pragma options align=reset
 #endif
 
diff --git a/drivers/scsi/dtc.c b/drivers/scsi/dtc.c
index ab9de39bb50..897743b2334 100644
--- a/drivers/scsi/dtc.c
+++ b/drivers/scsi/dtc.c
@@ -92,10 +92,6 @@
 
 #define DTC_PUBLIC_RELEASE 2
 
-/*#define DTCDEBUG 0x1*/
-#define DTCDEBUG_INIT	0x1
-#define DTCDEBUG_TRANSFER 0x2
-
 /*
  * The DTC3180 & 3280 boards are memory mapped.
  * 
diff --git a/drivers/scsi/dtc.h b/drivers/scsi/dtc.h
index ed73629eb2f..277cd015ee4 100644
--- a/drivers/scsi/dtc.h
+++ b/drivers/scsi/dtc.h
@@ -28,6 +28,10 @@
 #ifndef DTC3280_H
 #define DTC3280_H
 
+#define DTCDEBUG 0
+#define DTCDEBUG_INIT	0x1
+#define DTCDEBUG_TRANSFER 0x2
+
 static int dtc_abort(Scsi_Cmnd *);
 static int dtc_biosparam(struct scsi_device *, struct block_device *,
 		         sector_t, int*);
diff --git a/drivers/scsi/fdomain.c b/drivers/scsi/fdomain.c
index aecf32dd0bd..3b2a5bf5c43 100644
--- a/drivers/scsi/fdomain.c
+++ b/drivers/scsi/fdomain.c
@@ -570,7 +570,7 @@ static void do_pause(unsigned amount)	/* Pause for amount*10 milliseconds */
 	mdelay(10*amount);
 }
 
-inline static void fdomain_make_bus_idle( void )
+static inline void fdomain_make_bus_idle( void )
 {
    outb(0, port_base + SCSI_Cntl);
    outb(0, port_base + SCSI_Mode_Cntl);
diff --git a/drivers/scsi/ibmvscsi/srp.h b/drivers/scsi/ibmvscsi/srp.h
index 2ae5154fd89..7d8e4c4accb 100644
--- a/drivers/scsi/ibmvscsi/srp.h
+++ b/drivers/scsi/ibmvscsi/srp.h
@@ -35,7 +35,7 @@
 enum srp_types {
 	SRP_LOGIN_REQ_TYPE = 0x00,
 	SRP_LOGIN_RSP_TYPE = 0xC0,
-	SRP_LOGIN_REJ_TYPE = 0x80,
+	SRP_LOGIN_REJ_TYPE = 0xC2,
 	SRP_I_LOGOUT_TYPE = 0x03,
 	SRP_T_LOGOUT_TYPE = 0x80,
 	SRP_TSK_MGMT_TYPE = 0x01,
diff --git a/drivers/scsi/initio.c b/drivers/scsi/initio.c
index 2094d4811d6..ea6f3c0e05d 100644
--- a/drivers/scsi/initio.c
+++ b/drivers/scsi/initio.c
@@ -716,7 +716,7 @@ static int init_tulip(HCS * pCurHcb, SCB * scbp, int tul_num_scb,
 	pCurHcb->HCS_SCSI_ID = i91unvramp->NVM_SCSIInfo[0].NVM_ChSCSIID;
 	pCurHcb->HCS_IdMask = ~(1 << pCurHcb->HCS_SCSI_ID);
 
-#if CHK_PARITY
+#ifdef CHK_PARITY
 	/* Enable parity error response */
 	TUL_WR(pCurHcb->HCS_Base + TUL_PCMD, TUL_RD(pCurHcb->HCS_Base, TUL_PCMD) | 0x40);
 #endif
diff --git a/drivers/scsi/ips.c b/drivers/scsi/ips.c
index 6dfcb4fbccd..4cdd891781b 100644
--- a/drivers/scsi/ips.c
+++ b/drivers/scsi/ips.c
@@ -133,10 +133,12 @@
 /* 6.10.00  - Remove 1G Addressing Limitations                               */
 /* 6.11.xx  - Get VersionInfo buffer off the stack !              DDTS 60401 */
 /* 6.11.xx  - Make Logical Drive Info structure safe for DMA      DDTS 60639 */
-/* 7.10.xx  - Add highmem_io flag in SCSI Templete for 2.4 kernels           */
+/* 7.10.18  - Add highmem_io flag in SCSI Templete for 2.4 kernels           */
 /*          - Fix path/name for scsi_hosts.h include for 2.6 kernels         */
 /*          - Fix sort order of 7k                                           */
 /*          - Remove 3 unused "inline" functions                             */
+/* 7.12.xx  - Use STATIC functions whereever possible                        */
+/*          - Clean up deprecated MODULE_PARM calls                          */
 /*****************************************************************************/
 
 /*
@@ -207,8 +209,8 @@ module_param(ips, charp, 0);
 /*
  * DRIVER_VER
  */
-#define IPS_VERSION_HIGH        "7.10"
-#define IPS_VERSION_LOW         ".18 "
+#define IPS_VERSION_HIGH        "7.12"
+#define IPS_VERSION_LOW         ".02 "
 
 #if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__)
 #warning "This driver has only been tested on the x86/ia64/x86_64 platforms"
diff --git a/drivers/scsi/ips.h b/drivers/scsi/ips.h
index 480e06f4d6a..505e967013d 100644
--- a/drivers/scsi/ips.h
+++ b/drivers/scsi/ips.h
@@ -87,15 +87,14 @@
       #define scsi_set_pci_device(sh,dev) (0)
    #endif
 
-   #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
-   
-      #ifndef irqreturn_t
-         typedef void irqreturn_t;
-      #endif 
-      
+   #ifndef IRQ_NONE
+      typedef void irqreturn_t;
       #define IRQ_NONE
       #define IRQ_HANDLED
       #define IRQ_RETVAL(x)
+   #endif
+   
+   #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
       #define IPS_REGISTER_HOSTS(SHT)      scsi_register_module(MODULE_SCSI_HA,SHT)
       #define IPS_UNREGISTER_HOSTS(SHT)    scsi_unregister_module(MODULE_SCSI_HA,SHT)
       #define IPS_ADD_HOST(shost,device)
@@ -123,6 +122,10 @@
    #ifndef min
       #define min(x,y) ((x) < (y) ? x : y)
    #endif
+   
+   #ifndef __iomem       /* For clean compiles in earlier kernels without __iomem annotations */
+      #define __iomem
+   #endif
 
    #define pci_dma_hi32(a)         ((a >> 16) >> 16)
    #define pci_dma_lo32(a)         (a & 0xffffffff)
@@ -1206,13 +1209,13 @@ typedef struct {
 
 #define IPS_VER_MAJOR 7
 #define IPS_VER_MAJOR_STRING "7"
-#define IPS_VER_MINOR 10
-#define IPS_VER_MINOR_STRING "10"
-#define IPS_VER_BUILD 18
-#define IPS_VER_BUILD_STRING "18"
-#define IPS_VER_STRING "7.10.18"
+#define IPS_VER_MINOR 12
+#define IPS_VER_MINOR_STRING "12"
+#define IPS_VER_BUILD 02
+#define IPS_VER_BUILD_STRING "02"
+#define IPS_VER_STRING "7.12.02"
 #define IPS_RELEASE_ID 0x00020000
-#define IPS_BUILD_IDENT 731
+#define IPS_BUILD_IDENT 761
 #define IPS_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002. All Rights Reserved."
 #define IPS_ADAPTECCOPYRIGHT_STRING "(c) Copyright Adaptec, Inc. 2002 to 2004. All Rights Reserved."
 #define IPS_DELLCOPYRIGHT_STRING "(c) Copyright Dell 2004. All Rights Reserved."
@@ -1223,12 +1226,12 @@ typedef struct {
 #define IPS_VER_SERVERAID2 "2.88.13"
 #define IPS_VER_NAVAJO "2.88.13"
 #define IPS_VER_SERVERAID3 "6.10.24"
-#define IPS_VER_SERVERAID4H "7.10.11"
-#define IPS_VER_SERVERAID4MLx "7.10.18"
-#define IPS_VER_SARASOTA "7.10.18"
-#define IPS_VER_MARCO "7.10.18"
-#define IPS_VER_SEBRING "7.10.18"
-#define IPS_VER_KEYWEST "7.10.18"
+#define IPS_VER_SERVERAID4H "7.12.02"
+#define IPS_VER_SERVERAID4MLx "7.12.02"
+#define IPS_VER_SARASOTA "7.12.02"
+#define IPS_VER_MARCO "7.12.02"
+#define IPS_VER_SEBRING "7.12.02"
+#define IPS_VER_KEYWEST "7.12.02"
 
 /* Compatability IDs for various adapters */
 #define IPS_COMPAT_UNKNOWN ""
diff --git a/drivers/scsi/lpfc/lpfc_compat.h b/drivers/scsi/lpfc/lpfc_compat.h
index 275ba34b3c9..a11f1ae7b98 100644
--- a/drivers/scsi/lpfc/lpfc_compat.h
+++ b/drivers/scsi/lpfc/lpfc_compat.h
@@ -30,8 +30,9 @@ memcpy_toio() and memcpy_fromio() can be used.
 However on a big-endian host, copy 4 bytes at a time,
 using writel() and readl().
  *******************************************************************/
+#include <asm/byteorder.h>
 
-#if __BIG_ENDIAN
+#ifdef __BIG_ENDIAN
 
 static inline void
 lpfc_memcpy_to_slim(void __iomem *dest, void *src, unsigned int bytes)
diff --git a/drivers/scsi/lpfc/lpfc_scsi.h b/drivers/scsi/lpfc/lpfc_scsi.h
index d8fd2010ef4..0fd9ba14e1b 100644
--- a/drivers/scsi/lpfc/lpfc_scsi.h
+++ b/drivers/scsi/lpfc/lpfc_scsi.h
@@ -18,6 +18,8 @@
  * included with this package.                                     *
  *******************************************************************/
 
+#include <asm/byteorder.h>
+
 struct lpfc_hba;
 
 #define list_remove_head(list, entry, type, member)		\
@@ -81,7 +83,7 @@ struct fcp_cmnd {
 	/* # of bits to shift lun id to end up in right
 	 * payload word, little endian = 8, big = 16.
 	 */
-#if __BIG_ENDIAN
+#ifdef __BIG_ENDIAN
 #define FC_LUN_SHIFT         16
 #define FC_ADDR_MODE_SHIFT   24
 #else	/*  __LITTLE_ENDIAN */
diff --git a/drivers/scsi/pas16.c b/drivers/scsi/pas16.c
index 363e0ebd4a3..72bc947e45b 100644
--- a/drivers/scsi/pas16.c
+++ b/drivers/scsi/pas16.c
@@ -2,6 +2,7 @@
 #define PSEUDO_DMA
 #define FOO
 #define UNSAFE  /* Not unsafe for PAS16 -- use it */
+#define PDEBUG 0
 
 /*
  * This driver adapted from Drew Eckhardt's Trantor T128 driver
diff --git a/drivers/scsi/qla2xxx/Kconfig b/drivers/scsi/qla2xxx/Kconfig
index fccecf67423..c1c1c687bcb 100644
--- a/drivers/scsi/qla2xxx/Kconfig
+++ b/drivers/scsi/qla2xxx/Kconfig
@@ -2,12 +2,12 @@ config SCSI_QLA2XXX
 	tristate
 	default (SCSI && PCI)
 	depends on SCSI && PCI
-	select SCSI_FC_ATTRS
 
 config SCSI_QLA21XX
 	tristate "QLogic ISP2100 host adapter family support"
 	depends on SCSI_QLA2XXX
         select SCSI_FC_ATTRS
+	select FW_LOADER
 	---help---
 	This driver supports the QLogic 21xx (ISP2100) host adapter family.
 
@@ -15,6 +15,7 @@ config SCSI_QLA22XX
 	tristate "QLogic ISP2200 host adapter family support"
 	depends on SCSI_QLA2XXX
         select SCSI_FC_ATTRS
+	select FW_LOADER
 	---help---
 	This driver supports the QLogic 22xx (ISP2200) host adapter family.
 
@@ -22,6 +23,7 @@ config SCSI_QLA2300
 	tristate "QLogic ISP2300 host adapter family support"
 	depends on SCSI_QLA2XXX
         select SCSI_FC_ATTRS
+	select FW_LOADER
 	---help---
 	This driver supports the QLogic 2300 (ISP2300 and ISP2312) host
 	adapter family.
@@ -30,6 +32,7 @@ config SCSI_QLA2322
 	tristate "QLogic ISP2322 host adapter family support"
 	depends on SCSI_QLA2XXX
         select SCSI_FC_ATTRS
+	select FW_LOADER
 	---help---
 	This driver supports the QLogic 2322 (ISP2322) host adapter family.
 
@@ -37,6 +40,16 @@ config SCSI_QLA6312
 	tristate "QLogic ISP63xx host adapter family support"
 	depends on SCSI_QLA2XXX
         select SCSI_FC_ATTRS
+	select FW_LOADER
 	---help---
 	This driver supports the QLogic 63xx (ISP6312 and ISP6322) host
 	adapter family.
+
+config SCSI_QLA24XX
+	tristate "QLogic ISP24xx host adapter family support"
+	depends on SCSI_QLA2XXX
+	select SCSI_FC_ATTRS
+	select FW_LOADER
+	---help---
+	This driver supports the QLogic 24xx (ISP2422 and ISP2432) host
+	adapter family.
diff --git a/drivers/scsi/qla2xxx/Makefile b/drivers/scsi/qla2xxx/Makefile
index 982b83604b4..b169687d08f 100644
--- a/drivers/scsi/qla2xxx/Makefile
+++ b/drivers/scsi/qla2xxx/Makefile
@@ -1,6 +1,4 @@
 EXTRA_CFLAGS += -DUNIQUE_FW_NAME
-CONFIG_SCSI_QLA24XX=m
-EXTRA_CFLAGS += -DCONFIG_SCSI_QLA24XX -DCONFIG_SCSI_QLA24XX_MODULE
 
 qla2xxx-y := qla_os.o qla_init.o qla_mbx.o qla_iocb.o qla_isr.o qla_gs.o \
 		qla_dbg.o qla_sup.o qla_rscn.o qla_attr.o
diff --git a/drivers/scsi/scsi_scan.c b/drivers/scsi/scsi_scan.c
index ad3a5b14246..2d3c4ac475f 100644
--- a/drivers/scsi/scsi_scan.c
+++ b/drivers/scsi/scsi_scan.c
@@ -756,7 +756,8 @@ static int scsi_add_lun(struct scsi_device *sdev, char *inq_result, int *bflags)
 	 * register it and tell the rest of the kernel
 	 * about it.
 	 */
-	scsi_sysfs_add_sdev(sdev);
+	if (scsi_sysfs_add_sdev(sdev) != 0)
+		return SCSI_SCAN_NO_RESPONSE;
 
 	return SCSI_SCAN_LUN_PRESENT;
 }
diff --git a/drivers/scsi/st.c b/drivers/scsi/st.c
index 0291a8fb654..0a7839db575 100644
--- a/drivers/scsi/st.c
+++ b/drivers/scsi/st.c
@@ -4149,12 +4149,10 @@ static int __init init_st(void)
 			do_create_driverfs_files();
 			return 0;
 		}
-		if (st_sysfs_class)
-			class_destroy(st_sysfs_class);
 		unregister_chrdev_region(MKDEV(SCSI_TAPE_MAJOR, 0),
-
 					 ST_MAX_TAPE_ENTRIES);
 	}
+	class_destroy(st_sysfs_class);
 
 	printk(KERN_ERR "Unable to get major %d for SCSI tapes\n", SCSI_TAPE_MAJOR);
 	return 1;
@@ -4162,13 +4160,11 @@ static int __init init_st(void)
 
 static void __exit exit_st(void)
 {
-	if (st_sysfs_class)
-		class_destroy(st_sysfs_class);
-	st_sysfs_class = NULL;
 	do_remove_driverfs_files();
 	scsi_unregister_driver(&st_template.gendrv);
 	unregister_chrdev_region(MKDEV(SCSI_TAPE_MAJOR, 0),
 				 ST_MAX_TAPE_ENTRIES);
+	class_destroy(st_sysfs_class);
 	kfree(scsi_tapes);
 	printk(KERN_INFO "st: Unloaded.\n");
 }
diff --git a/drivers/scsi/sym53c8xx_2/sym_hipd.h b/drivers/scsi/sym53c8xx_2/sym_hipd.h
index c55c7a57afa..3131a6bf7ab 100644
--- a/drivers/scsi/sym53c8xx_2/sym_hipd.h
+++ b/drivers/scsi/sym53c8xx_2/sym_hipd.h
@@ -151,6 +151,16 @@
  */
 #define	SYM_CONF_MIN_ASYNC (40)
 
+
+/*
+ * MEMORY ALLOCATOR.
+ */
+
+#define SYM_MEM_WARN	1	/* Warn on failed operations */
+
+#define SYM_MEM_PAGE_ORDER 0	/* 1 PAGE  maximum */
+#define SYM_MEM_CLUSTER_SHIFT	(PAGE_SHIFT+SYM_MEM_PAGE_ORDER)
+#define SYM_MEM_FREE_UNUSED	/* Free unused pages immediately */
 /*
  *  Shortest memory chunk is (1<<SYM_MEM_SHIFT), currently 16.
  *  Actual allocations happen as SYM_MEM_CLUSTER_SIZE sized.
@@ -1192,12 +1202,6 @@ static inline void sym_setup_data_pointers(struct sym_hcb *np,
  *  MEMORY ALLOCATOR.
  */
 
-#define SYM_MEM_PAGE_ORDER 0	/* 1 PAGE  maximum */
-#define SYM_MEM_CLUSTER_SHIFT	(PAGE_SHIFT+SYM_MEM_PAGE_ORDER)
-#define SYM_MEM_FREE_UNUSED	/* Free unused pages immediately */
-
-#define SYM_MEM_WARN	1	/* Warn on failed operations */
-
 #define sym_get_mem_cluster()	\
 	(void *) __get_free_pages(GFP_ATOMIC, SYM_MEM_PAGE_ORDER)
 #define sym_free_mem_cluster(p)	\
diff --git a/drivers/scsi/sym53c8xx_2/sym_nvram.c b/drivers/scsi/sym53c8xx_2/sym_nvram.c
index cd9140e158c..994b7566bca 100644
--- a/drivers/scsi/sym53c8xx_2/sym_nvram.c
+++ b/drivers/scsi/sym53c8xx_2/sym_nvram.c
@@ -367,7 +367,7 @@ static void S24C16_read_byte(struct sym_device *np, u_char *read_data, u_char ac
 	S24C16_write_ack(np, ack_data, gpreg, gpcntl);
 }
 
-#if SYM_CONF_NVRAM_WRITE_SUPPORT
+#ifdef SYM_CONF_NVRAM_WRITE_SUPPORT
 /*
  *  Write 'len' bytes starting at 'offset'.
  */
diff --git a/drivers/scsi/t128.h b/drivers/scsi/t128.h
index 9ad1d68827a..596f3a32a1c 100644
--- a/drivers/scsi/t128.h
+++ b/drivers/scsi/t128.h
@@ -43,6 +43,7 @@
 
 #define T128_PUBLIC_RELEASE 3
 
+#define TDEBUG		0
 #define TDEBUG_INIT	0x1
 #define TDEBUG_TRANSFER 0x2
 
diff --git a/drivers/serial/8250_pci.c b/drivers/serial/8250_pci.c
index 356f5556759..07f05e9d095 100644
--- a/drivers/serial/8250_pci.c
+++ b/drivers/serial/8250_pci.c
@@ -1029,6 +1029,8 @@ enum pci_board_num_t {
 	pbn_b0_2_921600,
 	pbn_b0_4_921600,
 
+	pbn_b0_2_1130000,
+
 	pbn_b0_4_1152000,
 
 	pbn_b0_bt_1_115200,
@@ -1163,6 +1165,14 @@ static struct pci_board pci_boards[] __devinitdata = {
 		.base_baud	= 921600,
 		.uart_offset	= 8,
 	},
+
+	[pbn_b0_2_1130000] = {
+		.flags          = FL_BASE0,
+		.num_ports      = 2,
+		.base_baud      = 1130000,
+		.uart_offset    = 8,
+	},
+
 	[pbn_b0_4_1152000] = {
 		.flags		= FL_BASE0,
 		.num_ports	= 4,
@@ -1988,6 +1998,16 @@ static struct pci_device_id serial_pci_tbl[] = {
 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
 		PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
 		pbn_b0_4_1152000 },
+
+		/*
+		 * The below card is a little controversial since it is the
+		 * subject of a PCI vendor/device ID clash.  (See
+		 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
+		 * For now just used the hex ID 0x950a.
+		 */
+	{	PCI_VENDOR_ID_OXSEMI, 0x950a,
+		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+		pbn_b0_2_1130000 },
 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 		pbn_b0_4_115200 },
diff --git a/drivers/serial/8250_pnp.c b/drivers/serial/8250_pnp.c
index 18c58fb7389..6b321e82caf 100644
--- a/drivers/serial/8250_pnp.c
+++ b/drivers/serial/8250_pnp.c
@@ -394,7 +394,7 @@ static int __devinit serial_pnp_guess_board(struct pnp_dev *dev, int *flags)
 }
 
 static int __devinit
-serial_pnp_probe(struct pnp_dev * dev, const struct pnp_device_id *dev_id)
+serial_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *dev_id)
 {
 	struct uart_port port;
 	int ret, line, flags = dev_id->driver_data;
@@ -406,15 +406,23 @@ serial_pnp_probe(struct pnp_dev * dev, const struct pnp_device_id *dev_id)
 	}
 
 	memset(&port, 0, sizeof(struct uart_port));
-	port.irq = pnp_irq(dev,0);
-	port.iobase = pnp_port_start(dev, 0);
+	port.irq = pnp_irq(dev, 0);
+	if (pnp_port_valid(dev, 0)) {
+		port.iobase = pnp_port_start(dev, 0);
+		port.iotype = UPIO_PORT;
+	} else if (pnp_mem_valid(dev, 0)) {
+		port.mapbase = pnp_mem_start(dev, 0);
+		port.iotype = UPIO_MEM;
+		port.flags = UPF_IOREMAP;
+	} else
+		return -ENODEV;
 
 #ifdef SERIAL_DEBUG_PNP
-	printk("Setup PNP port: port %x, irq %d, type %d\n",
-	       port.iobase, port.irq, port.iotype);
+	printk("Setup PNP port: port %x, mem 0x%lx, irq %d, type %d\n",
+	       port.iobase, port.mapbase, port.irq, port.iotype);
 #endif
 
-	port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
+	port.flags |= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
 	port.uartclk = 1843200;
 	port.dev = &dev->dev;
 
@@ -426,7 +434,7 @@ serial_pnp_probe(struct pnp_dev * dev, const struct pnp_device_id *dev_id)
 
 }
 
-static void __devexit serial_pnp_remove(struct pnp_dev * dev)
+static void __devexit serial_pnp_remove(struct pnp_dev *dev)
 {
 	long line = (long)pnp_get_drvdata(dev);
 	if (line)
diff --git a/drivers/serial/cpm_uart/cpm_uart_cpm1.c b/drivers/serial/cpm_uart/cpm_uart_cpm1.c
index 7911912f50c..8efbd6d1d6a 100644
--- a/drivers/serial/cpm_uart/cpm_uart_cpm1.c
+++ b/drivers/serial/cpm_uart/cpm_uart_cpm1.c
@@ -185,7 +185,7 @@ int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
 	memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
 	    L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
 	if (is_con) {
-		mem_addr = (u8 *) m8xx_cpm_hostalloc(memsz);
+		mem_addr = (u8 *) cpm_dpram_addr(cpm_dpalloc(memsz, 8));
 		dma_addr = 0;
 	} else
 		mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
diff --git a/drivers/serial/jsm/jsm.h b/drivers/serial/jsm/jsm.h
index 5bf3c45521f..18753193f59 100644
--- a/drivers/serial/jsm/jsm.h
+++ b/drivers/serial/jsm/jsm.h
@@ -89,7 +89,7 @@ enum {
 #define WRITEBUFLEN	((4096) + 4)
 #define MYFLIPLEN	N_TTY_BUF_SIZE
 
-#define JSM_VERSION	"jsm: 1.1-1-INKERNEL"
+#define JSM_VERSION	"jsm: 1.2-1-INKERNEL"
 #define JSM_PARTNUM	"40002438_A-INKERNEL"
 
 struct jsm_board;
diff --git a/drivers/serial/jsm/jsm_driver.c b/drivers/serial/jsm/jsm_driver.c
index cc5d21300ed..7e56c782419 100644
--- a/drivers/serial/jsm/jsm_driver.c
+++ b/drivers/serial/jsm/jsm_driver.c
@@ -22,6 +22,7 @@
  * Scott H Kilau <Scott_Kilau@digi.com>
  * Wendy Xiong   <wendyx@us.ltcfwd.linux.ibm.com>
  *
+ *
  ***********************************************************************/
 #include <linux/moduleparam.h>
 #include <linux/pci.h>
@@ -42,7 +43,7 @@ struct uart_driver jsm_uart_driver = {
 	.owner		= THIS_MODULE,
 	.driver_name	= JSM_DRIVER_NAME,
 	.dev_name	= "ttyn",
-	.major		= 253,
+	.major		= 0,
 	.minor		= JSM_MINOR_START,
 	.nr		= NR_PORTS,
 };
diff --git a/drivers/serial/jsm/jsm_neo.c b/drivers/serial/jsm/jsm_neo.c
index 3a11a69feb4..6f22b42d933 100644
--- a/drivers/serial/jsm/jsm_neo.c
+++ b/drivers/serial/jsm/jsm_neo.c
@@ -48,8 +48,9 @@ static inline void neo_pci_posting_flush(struct jsm_board *bd)
 
 static void neo_set_cts_flow_control(struct jsm_channel *ch)
 {
-	u8 ier = readb(&ch->ch_neo_uart->ier);
-	u8 efr = readb(&ch->ch_neo_uart->efr);
+	u8 ier, efr;
+	ier = readb(&ch->ch_neo_uart->ier);
+	efr = readb(&ch->ch_neo_uart->efr);
 
 	jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n");
 
@@ -78,8 +79,9 @@ static void neo_set_cts_flow_control(struct jsm_channel *ch)
 
 static void neo_set_rts_flow_control(struct jsm_channel *ch)
 {
-	u8 ier = readb(&ch->ch_neo_uart->ier);
-	u8 efr = readb(&ch->ch_neo_uart->efr);
+	u8 ier, efr;
+	ier = readb(&ch->ch_neo_uart->ier);
+	efr = readb(&ch->ch_neo_uart->efr);
 
 	jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n");
 
@@ -117,8 +119,9 @@ static void neo_set_rts_flow_control(struct jsm_channel *ch)
 
 static void neo_set_ixon_flow_control(struct jsm_channel *ch)
 {
-	u8 ier = readb(&ch->ch_neo_uart->ier);
-	u8 efr = readb(&ch->ch_neo_uart->efr);
+	u8 ier, efr;
+	ier = readb(&ch->ch_neo_uart->ier);
+	efr = readb(&ch->ch_neo_uart->efr);
 
 	jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n");
 
@@ -153,8 +156,9 @@ static void neo_set_ixon_flow_control(struct jsm_channel *ch)
 
 static void neo_set_ixoff_flow_control(struct jsm_channel *ch)
 {
-	u8 ier = readb(&ch->ch_neo_uart->ier);
-	u8 efr = readb(&ch->ch_neo_uart->efr);
+	u8 ier, efr;
+	ier = readb(&ch->ch_neo_uart->ier);
+	efr = readb(&ch->ch_neo_uart->efr);
 
 	jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n");
 
@@ -190,8 +194,9 @@ static void neo_set_ixoff_flow_control(struct jsm_channel *ch)
 
 static void neo_set_no_input_flow_control(struct jsm_channel *ch)
 {
-	u8 ier = readb(&ch->ch_neo_uart->ier);
-	u8 efr = readb(&ch->ch_neo_uart->efr);
+	u8 ier, efr;
+	ier = readb(&ch->ch_neo_uart->ier);
+	efr = readb(&ch->ch_neo_uart->efr);
 
 	jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n");
 
@@ -228,8 +233,9 @@ static void neo_set_no_input_flow_control(struct jsm_channel *ch)
 
 static void neo_set_no_output_flow_control(struct jsm_channel *ch)
 {
-	u8 ier = readb(&ch->ch_neo_uart->ier);
-	u8 efr = readb(&ch->ch_neo_uart->efr);
+	u8 ier, efr;
+	ier = readb(&ch->ch_neo_uart->ier);
+	efr = readb(&ch->ch_neo_uart->efr);
 
 	jsm_printk(PARAM, INFO, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n");
 
diff --git a/drivers/serial/serial_cs.c b/drivers/serial/serial_cs.c
index de0136cc593..1ae0b381c16 100644
--- a/drivers/serial/serial_cs.c
+++ b/drivers/serial/serial_cs.c
@@ -790,19 +790,19 @@ static struct pcmcia_device_id serial_ids[] = {
 	PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "CEM56", 0x2e3ee845, 0xa650c32a),
 	PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "REM10", 0x2e3ee845, 0x76df1d29),
 	PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "XEM5600", 0x2e3ee845, 0xf1403719),
-	PCMCIA_PFC_DEVICE_PROD_ID12(1, "AnyCom", "Fast Ethernet ", 0x578ba6e7, 0x02d92d1e),
+	PCMCIA_PFC_DEVICE_PROD_ID12(1, "AnyCom", "Fast Ethernet + 56K COMBO", 0x578ba6e7, 0xb0ac62c4),
 	PCMCIA_PFC_DEVICE_PROD_ID12(1, "D-Link", "DME336T", 0x1a424a1c, 0xb23897ff),
 	PCMCIA_PFC_DEVICE_PROD_ID12(1, "Gateway 2000", "XJEM3336", 0xdd9989be, 0x662c394c),
 	PCMCIA_PFC_DEVICE_PROD_ID12(1, "Grey Cell", "GCS3000", 0x2a151fac, 0x48b932ae),
 	PCMCIA_PFC_DEVICE_PROD_ID12(1, "Linksys", "EtherFast 10&100 + 56K PC Card (PCMLM56)", 0x0733cc81, 0xb3765033),
 	PCMCIA_PFC_DEVICE_PROD_ID12(1, "LINKSYS", "PCMLM336", 0xf7cb0b07, 0x7a821b58),
 	PCMCIA_PFC_DEVICE_PROD_ID12(1, "MEGAHERTZ", "XJEM1144/CCEM1144", 0xf510db04, 0x52d21e1e),
-	PCMCIA_PFC_DEVICE_PROD_ID12(1, "Ositech", "Trumpcard", 0x0c2f80cd, 0x0573c29f),
-	PCMCIA_PFC_DEVICE_PROD_ID12(1, "Ositech", "Trumpcard", 0x0c2f80cd, 0x0573c29f),
+	PCMCIA_PFC_DEVICE_PROD_ID12(1, "Ositech", "Trumpcard:Jack of Diamonds Modem+Ethernet", 0xc2f80cd, 0x656947b9),
+	PCMCIA_PFC_DEVICE_PROD_ID12(1, "Ositech", "Trumpcard:Jack of Hearts Modem+Ethernet", 0xc2f80cd, 0xdc9ba5ed),
 	PCMCIA_PFC_DEVICE_PROD_ID12(1, "PCMCIAs", "ComboCard", 0xdcfe12d3, 0xcd8906cc),
 	PCMCIA_PFC_DEVICE_PROD_ID12(1, "PCMCIAs", "LanModem", 0xdcfe12d3, 0xc67c648f),
 	PCMCIA_PFC_DEVICE_PROD_ID12(1, "TDK", "GlobalNetworker 3410/3412", 0x1eae9475, 0xd9a93bed),
-	PCMCIA_PFC_DEVICE_PROD_ID12(1, "Xircom", "CreditCard Ethernet", 0x2e3ee845, 0xc0e778c2),
+	PCMCIA_PFC_DEVICE_PROD_ID12(1, "Xircom", "CreditCard Ethernet+Modem II", 0x2e3ee845, 0xeca401bf),
 	PCMCIA_MFC_DEVICE_MANF_CARD(0, 0x0104, 0x0070),
 	PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x0101, 0x0562),
 	PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x0104, 0x0070),
@@ -840,7 +840,7 @@ static struct pcmcia_device_id serial_ids[] = {
 	PCMCIA_DEVICE_PROD_ID12("Computerboards, Inc.", "PCM-COM422", 0xd0b78f51, 0x7e2d49ed),
 	PCMCIA_DEVICE_PROD_ID12("Dr. Neuhaus", "FURY CARD 14K4", 0x76942813, 0x8b96ce65),
 	PCMCIA_DEVICE_PROD_ID12("Intelligent", "ANGIA FAX/MODEM", 0xb496e65e, 0xf31602a6),
-	PCMCIA_DEVICE_PROD_ID12("Intel", "MODEM 2400", 0x816cc815, 0x23539b80),
+	PCMCIA_DEVICE_PROD_ID12("Intel", "MODEM 2400+", 0x816cc815, 0x412729fb),
 	PCMCIA_DEVICE_PROD_ID12("IOTech Inc ", "PCMCIA Dual RS-232 Serial Port Card", 0x3bd2d898, 0x92abc92f),
 	PCMCIA_DEVICE_PROD_ID12("MACRONIX", "FAX/MODEM", 0x668388b3, 0x3f9bdf2f),
 	PCMCIA_DEVICE_PROD_ID12("Multi-Tech", "MT1432LT", 0x5f73be51, 0x0b3e2383),
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index cd329dd7fb8..85dacc92545 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -20,6 +20,7 @@ config USB_ARCH_HAS_OHCI
 	default y if SA1111
 	default y if ARCH_OMAP
 	default y if ARCH_LH7A404
+	default y if ARCH_S3C2410
 	default y if PXA27x
 	# PPC:
 	default y if STB03xxx
diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c
index adff5a77e31..16ecad30e29 100644
--- a/drivers/usb/class/cdc-acm.c
+++ b/drivers/usb/class/cdc-acm.c
@@ -980,6 +980,9 @@ static struct usb_device_id acm_ids[] = {
 	{ USB_DEVICE(0x0870, 0x0001), /* Metricom GS Modem */
 	.driver_info = NO_UNION_NORMAL, /* has no union descriptor */
 	},
+	{ USB_DEVICE(0x0482, 0x0203), /* KYOCERA AH-K3001V */
+	.driver_info = NO_UNION_NORMAL, /* has no union descriptor */
+	},
 	/* control interfaces with various AT-command sets */
 	{ USB_INTERFACE_INFO(USB_CLASS_COMM, USB_CDC_SUBCLASS_ACM,
 		USB_CDC_ACM_PROTO_AT_V25TER) },
diff --git a/drivers/usb/core/devio.c b/drivers/usb/core/devio.c
index 787c27a63c5..f86bf1454e2 100644
--- a/drivers/usb/core/devio.c
+++ b/drivers/usb/core/devio.c
@@ -569,8 +569,11 @@ static int proc_control(struct dev_state *ps, void __user *arg)
 			free_page((unsigned long)tbuf);
 			return -EINVAL;
 		}
-		snoop(&dev->dev, "control read: bRequest=%02x bRrequestType=%02x wValue=%04x wIndex=%04x\n", 
-			ctrl.bRequest, ctrl.bRequestType, ctrl.wValue, ctrl.wIndex);
+		snoop(&dev->dev, "control read: bRequest=%02x "
+				"bRrequestType=%02x wValue=%04x "
+				"wIndex=%04x wLength=%04x\n",
+			ctrl.bRequest, ctrl.bRequestType, ctrl.wValue,
+				ctrl.wIndex, ctrl.wLength);
 
 		usb_unlock_device(dev);
 		i = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), ctrl.bRequest, ctrl.bRequestType,
@@ -579,11 +582,11 @@ static int proc_control(struct dev_state *ps, void __user *arg)
 		if ((i > 0) && ctrl.wLength) {
 			if (usbfs_snoop) {
 				dev_info(&dev->dev, "control read: data ");
-				for (j = 0; j < ctrl.wLength; ++j)
+				for (j = 0; j < i; ++j)
 					printk ("%02x ", (unsigned char)(tbuf)[j]);
 				printk("\n");
 			}
-			if (copy_to_user(ctrl.data, tbuf, ctrl.wLength)) {
+			if (copy_to_user(ctrl.data, tbuf, i)) {
 				free_page((unsigned long)tbuf);
 				return -EFAULT;
 			}
@@ -595,8 +598,11 @@ static int proc_control(struct dev_state *ps, void __user *arg)
 				return -EFAULT;
 			}
 		}
-		snoop(&dev->dev, "control write: bRequest=%02x bRrequestType=%02x wValue=%04x wIndex=%04x\n", 
-			ctrl.bRequest, ctrl.bRequestType, ctrl.wValue, ctrl.wIndex);
+		snoop(&dev->dev, "control write: bRequest=%02x "
+				"bRrequestType=%02x wValue=%04x "
+				"wIndex=%04x wLength=%04x\n",
+			ctrl.bRequest, ctrl.bRequestType, ctrl.wValue,
+				ctrl.wIndex, ctrl.wLength);
 		if (usbfs_snoop) {
 			dev_info(&dev->dev, "control write: data: ");
 			for (j = 0; j < ctrl.wLength; ++j)
diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
index 8616356f55e..79422a3b07b 100644
--- a/drivers/usb/core/hcd.c
+++ b/drivers/usb/core/hcd.c
@@ -939,9 +939,9 @@ long usb_calc_bus_time (int speed, int is_input, int isoc, int bytecount)
 	case USB_SPEED_HIGH:	/* ISOC or INTR */
 		// FIXME adjust for input vs output
 		if (isoc)
-			tmp = HS_USECS (bytecount);
+			tmp = HS_NSECS_ISO (bytecount);
 		else
-			tmp = HS_USECS_ISO (bytecount);
+			tmp = HS_NSECS (bytecount);
 		return tmp;
 	default:
 		pr_debug ("%s: bogus device speed!\n", usbcore_name);
diff --git a/drivers/usb/core/hcd.h b/drivers/usb/core/hcd.h
index 67db4a999b9..28055f95645 100644
--- a/drivers/usb/core/hcd.h
+++ b/drivers/usb/core/hcd.h
@@ -334,17 +334,19 @@ extern void usb_release_bandwidth (struct usb_device *dev, struct urb *urb,
 extern int usb_check_bandwidth (struct usb_device *dev, struct urb *urb);
 
 /*
- * Ceiling microseconds (typical) for that many bytes at high speed
+ * Ceiling [nano/micro]seconds (typical) for that many bytes at high speed
  * ISO is a bit less, no ACK ... from USB 2.0 spec, 5.11.3 (and needed
  * to preallocate bandwidth)
  */
 #define USB2_HOST_DELAY	5	/* nsec, guess */
-#define HS_USECS(bytes) NS_TO_US ( ((55 * 8 * 2083)/1000) \
+#define HS_NSECS(bytes) ( ((55 * 8 * 2083)/1000) \
 	+ ((2083UL * (3167 + BitTime (bytes)))/1000) \
 	+ USB2_HOST_DELAY)
-#define HS_USECS_ISO(bytes) NS_TO_US ( ((38 * 8 * 2083)/1000) \
+#define HS_NSECS_ISO(bytes) ( ((38 * 8 * 2083)/1000) \
 	+ ((2083UL * (3167 + BitTime (bytes)))/1000) \
 	+ USB2_HOST_DELAY)
+#define HS_USECS(bytes) NS_TO_US (HS_NSECS(bytes))
+#define HS_USECS_ISO(bytes) NS_TO_US (HS_NSECS_ISO(bytes))
 
 extern long usb_calc_bus_time (int speed, int is_input,
 			int isoc, int bytecount);
diff --git a/drivers/usb/core/message.c b/drivers/usb/core/message.c
index a428ef479bd..88d1b376f67 100644
--- a/drivers/usb/core/message.c
+++ b/drivers/usb/core/message.c
@@ -985,8 +985,10 @@ void usb_disable_device(struct usb_device *dev, int skip_ep0)
 		for (i = 0; i < dev->actconfig->desc.bNumInterfaces; i++) {
 			struct usb_interface	*interface;
 
-			/* remove this interface */
+			/* remove this interface if it has been registered */
 			interface = dev->actconfig->interface[i];
+			if (!klist_node_attached(&interface->dev.knode_bus))
+				continue;
 			dev_dbg (&dev->dev, "unregistering interface %s\n",
 				interface->dev.bus_id);
 			usb_remove_sysfs_intf_files(interface);
@@ -1439,7 +1441,7 @@ free_interfaces:
 		}
 	}
 
-	return ret;
+	return 0;
 }
 
 // synchronous request completion model
diff --git a/drivers/usb/host/ehci-dbg.c b/drivers/usb/host/ehci-dbg.c
index 50cb0183107..b01efb6b36f 100644
--- a/drivers/usb/host/ehci-dbg.c
+++ b/drivers/usb/host/ehci-dbg.c
@@ -527,7 +527,7 @@ show_periodic (struct class_device *class_dev, char *buf)
 						p.qh->period,
 						le32_to_cpup (&p.qh->hw_info2)
 							/* uframe masks */
-							& 0xffff,
+							& (QH_CMASK | QH_SMASK),
 						p.qh);
 				size -= temp;
 				next += temp;
diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c
index d74b2d68a50..20df01a79b2 100644
--- a/drivers/usb/host/ehci-q.c
+++ b/drivers/usb/host/ehci-q.c
@@ -222,7 +222,7 @@ __acquires(ehci->lock)
 		struct ehci_qh	*qh = (struct ehci_qh *) urb->hcpriv;
 
 		/* S-mask in a QH means it's an interrupt urb */
-		if ((qh->hw_info2 & __constant_cpu_to_le32 (0x00ff)) != 0) {
+		if ((qh->hw_info2 & __constant_cpu_to_le32 (QH_SMASK)) != 0) {
 
 			/* ... update hc-wide periodic stats (for usbfs) */
 			ehci_to_hcd(ehci)->self.bandwidth_int_reqs--;
@@ -428,7 +428,8 @@ halt:
 			/* should be rare for periodic transfers,
 			 * except maybe high bandwidth ...
 			 */
-			if (qh->period) {
+			if ((__constant_cpu_to_le32 (QH_SMASK)
+					& qh->hw_info2) != 0) {
 				intr_deschedule (ehci, qh);
 				(void) qh_schedule (ehci, qh);
 			} else
@@ -657,8 +658,8 @@ qh_make (
 	 * For control/bulk requests, the HC or TT handles these.
 	 */
 	if (type == PIPE_INTERRUPT) {
-		qh->usecs = usb_calc_bus_time (USB_SPEED_HIGH, is_input, 0,
-				hb_mult (maxp) * max_packet (maxp));
+		qh->usecs = NS_TO_US (usb_calc_bus_time (USB_SPEED_HIGH, is_input, 0,
+				hb_mult (maxp) * max_packet (maxp)));
 		qh->start = NO_FRAME;
 
 		if (urb->dev->speed == USB_SPEED_HIGH) {
diff --git a/drivers/usb/host/ehci-sched.c b/drivers/usb/host/ehci-sched.c
index 9af4f64532a..b56f25864ed 100644
--- a/drivers/usb/host/ehci-sched.c
+++ b/drivers/usb/host/ehci-sched.c
@@ -301,7 +301,7 @@ static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
 
 	dev_dbg (&qh->dev->dev,
 		"link qh%d-%04x/%p start %d [%d/%d us]\n",
-		period, le32_to_cpup (&qh->hw_info2) & 0xffff,
+		period, le32_to_cpup (&qh->hw_info2) & (QH_CMASK | QH_SMASK),
 		qh, qh->start, qh->usecs, qh->c_usecs);
 
 	/* high bandwidth, or otherwise every microframe */
@@ -385,7 +385,8 @@ static void qh_unlink_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
 
 	dev_dbg (&qh->dev->dev,
 		"unlink qh%d-%04x/%p start %d [%d/%d us]\n",
-		qh->period, le32_to_cpup (&qh->hw_info2) & 0xffff,
+		qh->period,
+		le32_to_cpup (&qh->hw_info2) & (QH_CMASK | QH_SMASK),
 		qh, qh->start, qh->usecs, qh->c_usecs);
 
 	/* qh->qh_next still "live" to HC */
@@ -411,7 +412,7 @@ static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
 	 * active high speed queues may need bigger delays...
 	 */
 	if (list_empty (&qh->qtd_list)
-			|| (__constant_cpu_to_le32 (0x0ff << 8)
+			|| (__constant_cpu_to_le32 (QH_CMASK)
 					& qh->hw_info2) != 0)
 		wait = 2;
 	else
@@ -533,7 +534,7 @@ static int qh_schedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
 
 	/* reuse the previous schedule slots, if we can */
 	if (frame < qh->period) {
-		uframe = ffs (le32_to_cpup (&qh->hw_info2) & 0x00ff);
+		uframe = ffs (le32_to_cpup (&qh->hw_info2) & QH_SMASK);
 		status = check_intr_schedule (ehci, frame, --uframe,
 				qh, &c_mask);
 	} else {
@@ -569,10 +570,10 @@ static int qh_schedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
 		qh->start = frame;
 
 		/* reset S-frame and (maybe) C-frame masks */
-		qh->hw_info2 &= __constant_cpu_to_le32 (~0xffff);
+		qh->hw_info2 &= __constant_cpu_to_le32(~(QH_CMASK | QH_SMASK));
 		qh->hw_info2 |= qh->period
 			? cpu_to_le32 (1 << uframe)
-			: __constant_cpu_to_le32 (0xff);
+			: __constant_cpu_to_le32 (QH_SMASK);
 		qh->hw_info2 |= c_mask;
 	} else
 		ehci_dbg (ehci, "reused qh %p schedule\n", qh);
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index 4df49823175..a7542157534 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -385,6 +385,11 @@ struct ehci_qh {
 	__le32			hw_info1;        /* see EHCI 3.6.2 */
 #define	QH_HEAD		0x00008000
 	__le32			hw_info2;        /* see EHCI 3.6.2 */
+#define	QH_SMASK	0x000000ff
+#define	QH_CMASK	0x0000ff00
+#define	QH_HUBADDR	0x007f0000
+#define	QH_HUBPORT	0x3f800000
+#define	QH_MULT		0xc0000000
 	__le32			hw_current;	 /* qtd list - see EHCI 3.6.4 */
 	
 	/* qtd overlay (hardware parts of a struct ehci_qtd) */
diff --git a/drivers/usb/host/isp116x-hcd.c b/drivers/usb/host/isp116x-hcd.c
index 50b1970fe6b..76cb496c583 100644
--- a/drivers/usb/host/isp116x-hcd.c
+++ b/drivers/usb/host/isp116x-hcd.c
@@ -229,9 +229,11 @@ static void preproc_atl_queue(struct isp116x *isp116x)
 	struct isp116x_ep *ep;
 	struct urb *urb;
 	struct ptd *ptd;
-	u16 toggle = 0, dir = PTD_DIR_SETUP, len;
+	u16 len;
 
 	for (ep = isp116x->atl_active; ep; ep = ep->active) {
+		u16 toggle = 0, dir = PTD_DIR_SETUP;
+
 		BUG_ON(list_empty(&ep->hep->urb_list));
 		urb = container_of(ep->hep->urb_list.next,
 				   struct urb, urb_list);
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 68decab280d..56b43f2a0e5 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -887,6 +887,10 @@ MODULE_LICENSE ("GPL");
 #include "ohci-sa1111.c"
 #endif
 
+#ifdef CONFIG_ARCH_S3C2410
+#include "ohci-s3c2410.c"
+#endif
+
 #ifdef CONFIG_ARCH_OMAP
 #include "ohci-omap.c"
 #endif
@@ -909,6 +913,7 @@ MODULE_LICENSE ("GPL");
 
 #if !(defined(CONFIG_PCI) \
       || defined(CONFIG_SA1111) \
+      || defined(CONFIG_ARCH_S3C2410) \
       || defined(CONFIG_ARCH_OMAP) \
       || defined (CONFIG_ARCH_LH7A404) \
       || defined (CONFIG_PXA27x) \
diff --git a/drivers/usb/host/ohci-s3c2410.c b/drivers/usb/host/ohci-s3c2410.c
new file mode 100644
index 00000000000..e9401662503
--- /dev/null
+++ b/drivers/usb/host/ohci-s3c2410.c
@@ -0,0 +1,496 @@
+/*
+ * OHCI HCD (Host Controller Driver) for USB.
+ *
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
+ * (C) Copyright 2002 Hewlett-Packard Company
+ *
+ * USB Bus Glue for Samsung S3C2410
+ *
+ * Written by Christopher Hoover <ch@hpl.hp.com>
+ * Based on fragments of previous driver by Rusell King et al.
+ *
+ * Modified for S3C2410 from ohci-sa1111.c, ohci-omap.c and ohci-lh7a40.c
+ *	by Ben Dooks, <ben@simtec.co.uk>
+ *	Copyright (C) 2004 Simtec Electronics
+ *
+ * Thanks to basprog@mail.ru for updates to newer kernels
+ *
+ * This file is licenced under the GPL.
+*/
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/hardware/clock.h>
+#include <asm/arch/usb-control.h>
+
+#define valid_port(idx) ((idx) == 1 || (idx) == 2)
+
+/* clock device associated with the hcd */
+
+static struct clk *clk;
+
+/* forward definitions */
+
+static void s3c2410_hcd_oc(struct s3c2410_hcd_info *info, int port_oc);
+
+/* conversion functions */
+
+struct s3c2410_hcd_info *to_s3c2410_info(struct usb_hcd *hcd)
+{
+	return hcd->self.controller->platform_data;
+}
+
+static void s3c2410_start_hc(struct platform_device *dev, struct usb_hcd *hcd)
+{
+	struct s3c2410_hcd_info *info = dev->dev.platform_data;
+
+	dev_dbg(&dev->dev, "s3c2410_start_hc:\n");
+	clk_enable(clk);
+
+	if (info != NULL) {
+		info->hcd	= hcd;
+		info->report_oc = s3c2410_hcd_oc;
+
+		if (info->enable_oc != NULL) {
+			(info->enable_oc)(info, 1);
+		}
+	}
+}
+
+static void s3c2410_stop_hc(struct platform_device *dev)
+{
+	struct s3c2410_hcd_info *info = dev->dev.platform_data;
+
+	dev_dbg(&dev->dev, "s3c2410_stop_hc:\n");
+
+	if (info != NULL) {
+		info->report_oc = NULL;
+		info->hcd	= NULL;
+
+		if (info->enable_oc != NULL) {
+			(info->enable_oc)(info, 0);
+		}
+	}
+
+	clk_disable(clk);
+}
+
+/* ohci_s3c2410_hub_status_data
+ *
+ * update the status data from the hub with anything that
+ * has been detected by our system
+*/
+
+static int
+ohci_s3c2410_hub_status_data (struct usb_hcd *hcd, char *buf)
+{
+	struct s3c2410_hcd_info *info = to_s3c2410_info(hcd);
+	struct s3c2410_hcd_port *port;
+	int orig;
+	int portno;
+
+	orig  = ohci_hub_status_data (hcd, buf);
+
+	if (info == NULL)
+		return orig;
+
+	port = &info->port[0];
+
+	/* mark any changed port as changed */
+
+	for (portno = 0; portno < 2; port++, portno++) {
+		if (port->oc_changed == 1 &&
+		    port->flags & S3C_HCDFLG_USED) {
+			dev_dbg(hcd->self.controller,
+				"oc change on port %d\n", portno);
+
+			if (orig < 1)
+				orig = 1;
+
+			buf[0] |= 1<<(portno+1);
+		}
+	}
+
+	return orig;
+}
+
+/* s3c2410_usb_set_power
+ *
+ * configure the power on a port, by calling the platform device
+ * routine registered with the platform device
+*/
+
+static void s3c2410_usb_set_power(struct s3c2410_hcd_info *info,
+				  int port, int to)
+{
+	if (info == NULL)
+		return;
+
+	if (info->power_control != NULL) {
+		info->port[port-1].power = to;
+		(info->power_control)(port, to);
+	}
+}
+
+/* ohci_s3c2410_hub_control
+ *
+ * look at control requests to the hub, and see if we need
+ * to take any action or over-ride the results from the
+ * request.
+*/
+
+static int ohci_s3c2410_hub_control (
+	struct usb_hcd	*hcd,
+	u16		typeReq,
+	u16		wValue,
+	u16		wIndex,
+	char		*buf,
+	u16		wLength)
+{
+	struct s3c2410_hcd_info *info = to_s3c2410_info(hcd);
+	struct usb_hub_descriptor *desc;
+	int ret = -EINVAL;
+	u32 *data = (u32 *)buf;
+
+	dev_dbg(hcd->self.controller,
+		"s3c2410_hub_control(%p,0x%04x,0x%04x,0x%04x,%p,%04x)\n",
+		hcd, typeReq, wValue, wIndex, buf, wLength);
+
+	/* if we are only an humble host without any special capabilites
+	 * process the request straight away and exit */
+
+	if (info == NULL) {
+		ret = ohci_hub_control(hcd, typeReq, wValue,
+				       wIndex, buf, wLength);
+		goto out;
+	}
+
+	/* check the request to see if it needs handling */
+
+	switch (typeReq) {
+	case SetPortFeature:
+		if (wValue == USB_PORT_FEAT_POWER) {
+			dev_dbg(hcd->self.controller, "SetPortFeat: POWER\n");
+			s3c2410_usb_set_power(info, wIndex, 1);
+			goto out;
+		}
+		break;
+
+	case ClearPortFeature:
+		switch (wValue) {
+		case USB_PORT_FEAT_C_OVER_CURRENT:
+			dev_dbg(hcd->self.controller,
+				"ClearPortFeature: C_OVER_CURRENT\n");
+
+			if (valid_port(wIndex)) {
+				info->port[wIndex-1].oc_changed = 0;
+				info->port[wIndex-1].oc_status = 0;
+			}
+
+			goto out;
+
+		case USB_PORT_FEAT_OVER_CURRENT:
+			dev_dbg(hcd->self.controller,
+				"ClearPortFeature: OVER_CURRENT\n");
+
+			if (valid_port(wIndex)) {
+				info->port[wIndex-1].oc_status = 0;
+			}
+
+			goto out;
+
+		case USB_PORT_FEAT_POWER:
+			dev_dbg(hcd->self.controller,
+				"ClearPortFeature: POWER\n");
+
+			if (valid_port(wIndex)) {
+				s3c2410_usb_set_power(info, wIndex, 0);
+				return 0;
+			}
+		}
+		break;
+	}
+
+	ret = ohci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
+	if (ret)
+		goto out;
+
+	switch (typeReq) {
+	case GetHubDescriptor:
+
+		/* update the hub's descriptor */
+
+		desc = (struct usb_hub_descriptor *)buf;
+
+		if (info->power_control == NULL)
+			return ret;
+
+		dev_dbg(hcd->self.controller, "wHubCharacteristics 0x%04x\n",
+			desc->wHubCharacteristics);
+
+		/* remove the old configurations for power-switching, and
+		 * over-current protection, and insert our new configuration
+		 */
+
+		desc->wHubCharacteristics &= ~cpu_to_le16(HUB_CHAR_LPSM);
+		desc->wHubCharacteristics |= cpu_to_le16(0x0001);
+
+		if (info->enable_oc) {
+			desc->wHubCharacteristics &= ~cpu_to_le16(HUB_CHAR_OCPM);
+			desc->wHubCharacteristics |=  cpu_to_le16(0x0008|0x0001);
+		}
+
+		dev_dbg(hcd->self.controller, "wHubCharacteristics after 0x%04x\n",
+			desc->wHubCharacteristics);
+
+		return ret;
+
+	case GetPortStatus:
+		/* check port status */
+
+		dev_dbg(hcd->self.controller, "GetPortStatus(%d)\n", wIndex);
+
+		if (valid_port(wIndex)) {
+			if (info->port[wIndex-1].oc_changed) {
+				*data |= cpu_to_le32(RH_PS_OCIC);
+			}
+
+			if (info->port[wIndex-1].oc_status) {
+				*data |= cpu_to_le32(RH_PS_POCI);
+			}
+		}
+	}
+
+ out:
+	return ret;
+}
+
+/* s3c2410_hcd_oc
+ *
+ * handle an over-current report
+*/
+
+static void s3c2410_hcd_oc(struct s3c2410_hcd_info *info, int port_oc)
+{
+	struct s3c2410_hcd_port *port;
+	struct usb_hcd *hcd;
+	unsigned long flags;
+	int portno;
+
+	if (info == NULL)
+		return;
+
+	port = &info->port[0];
+	hcd = info->hcd;
+
+	local_irq_save(flags);
+
+	for (portno = 0; portno < 2; port++, portno++) {
+		if (port_oc & (1<<portno) &&
+		    port->flags & S3C_HCDFLG_USED) {
+			port->oc_status = 1;
+			port->oc_changed = 1;
+
+			/* ok, once over-current is detected,
+			   the port needs to be powered down */
+			s3c2410_usb_set_power(info, portno+1, 0);
+		}
+	}
+
+	local_irq_restore(flags);
+}
+
+/* may be called without controller electrically present */
+/* may be called with controller, bus, and devices active */
+
+/*
+ * usb_hcd_s3c2410_remove - shutdown processing for HCD
+ * @dev: USB Host Controller being removed
+ * Context: !in_interrupt()
+ *
+ * Reverses the effect of usb_hcd_3c2410_probe(), first invoking
+ * the HCD's stop() method.  It is always called from a thread
+ * context, normally "rmmod", "apmd", or something similar.
+ *
+*/
+
+void usb_hcd_s3c2410_remove (struct usb_hcd *hcd, struct platform_device *dev)
+{
+	usb_remove_hcd(hcd);
+	s3c2410_stop_hc(dev);
+	iounmap(hcd->regs);
+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+	usb_put_hcd(hcd);
+}
+
+/**
+ * usb_hcd_s3c2410_probe - initialize S3C2410-based HCDs
+ * Context: !in_interrupt()
+ *
+ * Allocates basic resources for this USB host controller, and
+ * then invokes the start() method for the HCD associated with it
+ * through the hotplug entry's driver_data.
+ *
+ */
+int usb_hcd_s3c2410_probe (const struct hc_driver *driver,
+			   struct platform_device *dev)
+{
+	struct usb_hcd *hcd = NULL;
+	int retval;
+
+	s3c2410_usb_set_power(dev->dev.platform_data, 0, 1);
+	s3c2410_usb_set_power(dev->dev.platform_data, 1, 1);
+
+	hcd = usb_create_hcd(driver, &dev->dev, "s3c24xx");
+	if (hcd == NULL)
+		return -ENOMEM;
+
+	hcd->rsrc_start = dev->resource[0].start;
+	hcd->rsrc_len   = dev->resource[0].end - dev->resource[0].start + 1;
+
+	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
+		dev_err(&dev->dev, "request_mem_region failed");
+		retval = -EBUSY;
+		goto err0;
+	}
+
+	clk = clk_get(NULL, "usb-host");
+	if (IS_ERR(clk)) {
+		dev_err(&dev->dev, "cannot get usb-host clock\n");
+		retval = -ENOENT;
+		goto err1;
+	}
+
+	clk_use(clk);
+	s3c2410_start_hc(dev, hcd);
+
+	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+	if (!hcd->regs) {
+		dev_err(&dev->dev, "ioremap failed\n");
+		retval = -ENOMEM;
+		goto err2;
+	}
+
+	ohci_hcd_init(hcd_to_ohci(hcd));
+
+	retval = usb_add_hcd(hcd, dev->resource[1].start, SA_INTERRUPT);
+	if (retval != 0)
+		goto err2;
+
+	return 0;
+
+ err2:
+	s3c2410_stop_hc(dev);
+	iounmap(hcd->regs);
+	clk_unuse(clk);
+	clk_put(clk);
+
+ err1:
+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+
+ err0:
+	usb_put_hcd(hcd);
+	return retval;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static int
+ohci_s3c2410_start (struct usb_hcd *hcd)
+{
+	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
+	int ret;
+
+	if ((ret = ohci_init(ohci)) < 0)
+		return ret;
+
+	if ((ret = ohci_run (ohci)) < 0) {
+		err ("can't start %s", hcd->self.bus_name);
+		ohci_stop (hcd);
+		return ret;
+	}
+
+	return 0;
+}
+
+
+static const struct hc_driver ohci_s3c2410_hc_driver = {
+	.description =		hcd_name,
+	.product_desc =		"S3C24XX OHCI",
+	.hcd_priv_size =	sizeof(struct ohci_hcd),
+
+	/*
+	 * generic hardware linkage
+	 */
+	.irq =			ohci_irq,
+	.flags =		HCD_USB11 | HCD_MEMORY,
+
+	/*
+	 * basic lifecycle operations
+	 */
+	.start =		ohci_s3c2410_start,
+	.stop =			ohci_stop,
+
+	/*
+	 * managing i/o requests and associated device resources
+	 */
+	.urb_enqueue =		ohci_urb_enqueue,
+	.urb_dequeue =		ohci_urb_dequeue,
+	.endpoint_disable =	ohci_endpoint_disable,
+
+	/*
+	 * scheduling support
+	 */
+	.get_frame_number =	ohci_get_frame,
+
+	/*
+	 * root hub support
+	 */
+	.hub_status_data =	ohci_s3c2410_hub_status_data,
+	.hub_control =		ohci_s3c2410_hub_control,
+
+#if defined(CONFIG_USB_SUSPEND) && 0
+	.hub_suspend =		ohci_hub_suspend,
+	.hub_resume =		ohci_hub_resume,
+#endif
+};
+
+/* device driver */
+
+static int ohci_hcd_s3c2410_drv_probe(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	return usb_hcd_s3c2410_probe(&ohci_s3c2410_hc_driver, pdev);
+}
+
+static int ohci_hcd_s3c2410_drv_remove(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct usb_hcd *hcd = dev_get_drvdata(dev);
+
+	usb_hcd_s3c2410_remove(hcd, pdev);
+	return 0;
+}
+
+static struct device_driver ohci_hcd_s3c2410_driver = {
+	.name		= "s3c2410-ohci",
+	.bus		= &platform_bus_type,
+	.probe		= ohci_hcd_s3c2410_drv_probe,
+	.remove		= ohci_hcd_s3c2410_drv_remove,
+	/*.suspend	= ohci_hcd_s3c2410_drv_suspend, */
+	/*.resume	= ohci_hcd_s3c2410_drv_resume, */
+};
+
+static int __init ohci_hcd_s3c2410_init (void)
+{
+	return driver_register(&ohci_hcd_s3c2410_driver);
+}
+
+static void __exit ohci_hcd_s3c2410_cleanup (void)
+{
+	driver_unregister(&ohci_hcd_s3c2410_driver);
+}
+
+module_init (ohci_hcd_s3c2410_init);
+module_exit (ohci_hcd_s3c2410_cleanup);
diff --git a/drivers/usb/image/microtek.c b/drivers/usb/image/microtek.c
index 7d21a4f5c42..c84e1486054 100644
--- a/drivers/usb/image/microtek.c
+++ b/drivers/usb/image/microtek.c
@@ -361,8 +361,7 @@ int mts_scsi_queuecommand (Scsi_Cmnd *srb, mts_scsi_cmnd_callback callback );
 static void mts_transfer_cleanup( struct urb *transfer );
 static void mts_do_sg(struct urb * transfer, struct pt_regs *regs);
 
-
-inline static
+static inline
 void mts_int_submit_urb (struct urb* transfer,
 			int pipe,
 			void* data,
diff --git a/drivers/usb/input/acecad.c b/drivers/usb/input/acecad.c
index ebcf7c95580..13532f3e3ef 100644
--- a/drivers/usb/input/acecad.c
+++ b/drivers/usb/input/acecad.c
@@ -31,6 +31,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/usb.h>
+#include <linux/usb_input.h>
 
 /*
  * Version Information
@@ -87,8 +88,8 @@ static void usb_acecad_irq(struct urb *urb, struct pt_regs *regs)
 	if (prox) {
 		int x = data[1] | (data[2] << 8);
 		int y = data[3] | (data[4] << 8);
-		/*Pressure should compute the same way for flair and 302*/
-		int pressure = data[5] | ((int)data[6] << 8);
+		/* Pressure should compute the same way for flair and 302 */
+		int pressure = data[5] | (data[6] << 8);
 		int touch = data[0] & 0x01;
 		int stylus = (data[0] & 0x10) >> 4;
 		int stylus2 = (data[0] & 0x20) >> 5;
@@ -104,9 +105,9 @@ static void usb_acecad_irq(struct urb *urb, struct pt_regs *regs)
 	input_sync(dev);
 
 resubmit:
-	status = usb_submit_urb (urb, GFP_ATOMIC);
+	status = usb_submit_urb(urb, GFP_ATOMIC);
 	if (status)
-		err ("can't resubmit intr, %s-%s/input0, status %d",
+		err("can't resubmit intr, %s-%s/input0, status %d",
 			acecad->usbdev->bus->bus_name, acecad->usbdev->devpath, status);
 }
 
@@ -212,10 +213,7 @@ static int usb_acecad_probe(struct usb_interface *intf, const struct usb_device_
 
 	acecad->dev.name = acecad->name;
 	acecad->dev.phys = acecad->phys;
-	acecad->dev.id.bustype = BUS_USB;
-	acecad->dev.id.vendor = le16_to_cpu(dev->descriptor.idVendor);
-	acecad->dev.id.product = le16_to_cpu(dev->descriptor.idProduct);
-	acecad->dev.id.version = le16_to_cpu(dev->descriptor.bcdDevice);
+	usb_to_input_id(dev, &acecad->dev.id);
 	acecad->dev.dev = &intf->dev;
 
 	usb_fill_int_urb(acecad->irq, dev, pipe,
diff --git a/drivers/usb/input/aiptek.c b/drivers/usb/input/aiptek.c
index 6bb0f25e8e9..cd0cbfe2072 100644
--- a/drivers/usb/input/aiptek.c
+++ b/drivers/usb/input/aiptek.c
@@ -77,6 +77,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/usb.h>
+#include <linux/usb_input.h>
 #include <linux/sched.h>
 #include <asm/uaccess.h>
 #include <asm/unaligned.h>
@@ -2125,10 +2126,7 @@ aiptek_probe(struct usb_interface *intf, const struct usb_device_id *id)
 	aiptek->inputdev.absflat[ABS_WHEEL] = 0;
 	aiptek->inputdev.name = "Aiptek";
 	aiptek->inputdev.phys = aiptek->features.usbPath;
-	aiptek->inputdev.id.bustype = BUS_USB;
-	aiptek->inputdev.id.vendor = le16_to_cpu(usbdev->descriptor.idVendor);
-	aiptek->inputdev.id.product = le16_to_cpu(usbdev->descriptor.idProduct);
-	aiptek->inputdev.id.version = le16_to_cpu(usbdev->descriptor.bcdDevice);
+	usb_to_input_id(usbdev, &aiptek->inputdev.id);
 	aiptek->inputdev.dev = &intf->dev;
 
 	aiptek->usbdev = usbdev;
diff --git a/drivers/usb/input/ati_remote.c b/drivers/usb/input/ati_remote.c
index 654ac454744..fd99681ee48 100644
--- a/drivers/usb/input/ati_remote.c
+++ b/drivers/usb/input/ati_remote.c
@@ -94,6 +94,7 @@
 #include <linux/moduleparam.h>
 #include <linux/input.h>
 #include <linux/usb.h>
+#include <linux/usb_input.h>
 #include <linux/wait.h>
 
 /*
@@ -635,11 +636,8 @@ static void ati_remote_input_init(struct ati_remote *ati_remote)
 	idev->name = ati_remote->name;
 	idev->phys = ati_remote->phys;
 
-	idev->id.bustype = BUS_USB;
-	idev->id.vendor = le16_to_cpu(ati_remote->udev->descriptor.idVendor);
-	idev->id.product = le16_to_cpu(ati_remote->udev->descriptor.idProduct);
-	idev->id.version = le16_to_cpu(ati_remote->udev->descriptor.bcdDevice);
-	idev->dev = &(ati_remote->udev->dev);
+	usb_to_input_id(ati_remote->udev, &idev->id);
+	idev->dev = &ati_remote->udev->dev;
 }
 
 static int ati_remote_initialize(struct ati_remote *ati_remote)
diff --git a/drivers/usb/input/hid-core.c b/drivers/usb/input/hid-core.c
index 2350e7a5ad7..b2cb2b35892 100644
--- a/drivers/usb/input/hid-core.c
+++ b/drivers/usb/input/hid-core.c
@@ -789,12 +789,12 @@ static __inline__ int search(__s32 *array, __s32 value, unsigned n)
 	return -1;
 }
 
-static void hid_process_event(struct hid_device *hid, struct hid_field *field, struct hid_usage *usage, __s32 value, struct pt_regs *regs)
+static void hid_process_event(struct hid_device *hid, struct hid_field *field, struct hid_usage *usage, __s32 value, int interrupt, struct pt_regs *regs)
 {
 	hid_dump_input(usage, value);
 	if (hid->claimed & HID_CLAIMED_INPUT)
 		hidinput_hid_event(hid, field, usage, value, regs);
-	if (hid->claimed & HID_CLAIMED_HIDDEV)
+	if (hid->claimed & HID_CLAIMED_HIDDEV && interrupt)
 		hiddev_hid_event(hid, field, usage, value, regs);
 }
 
@@ -804,7 +804,7 @@ static void hid_process_event(struct hid_device *hid, struct hid_field *field, s
  * reporting to the layer).
  */
 
-static void hid_input_field(struct hid_device *hid, struct hid_field *field, __u8 *data, struct pt_regs *regs)
+static void hid_input_field(struct hid_device *hid, struct hid_field *field, __u8 *data, int interrupt, struct pt_regs *regs)
 {
 	unsigned n;
 	unsigned count = field->report_count;
@@ -831,19 +831,19 @@ static void hid_input_field(struct hid_device *hid, struct hid_field *field, __u
 	for (n = 0; n < count; n++) {
 
 		if (HID_MAIN_ITEM_VARIABLE & field->flags) {
-			hid_process_event(hid, field, &field->usage[n], value[n], regs);
+			hid_process_event(hid, field, &field->usage[n], value[n], interrupt, regs);
 			continue;
 		}
 
 		if (field->value[n] >= min && field->value[n] <= max
 			&& field->usage[field->value[n] - min].hid
 			&& search(value, field->value[n], count))
-				hid_process_event(hid, field, &field->usage[field->value[n] - min], 0, regs);
+				hid_process_event(hid, field, &field->usage[field->value[n] - min], 0, interrupt, regs);
 
 		if (value[n] >= min && value[n] <= max
 			&& field->usage[value[n] - min].hid
 			&& search(field->value, value[n], count))
-				hid_process_event(hid, field, &field->usage[value[n] - min], 1, regs);
+				hid_process_event(hid, field, &field->usage[value[n] - min], 1, interrupt, regs);
 	}
 
 	memcpy(field->value, value, count * sizeof(__s32));
@@ -851,7 +851,7 @@ exit:
 	kfree(value);
 }
 
-static int hid_input_report(int type, struct urb *urb, struct pt_regs *regs)
+static int hid_input_report(int type, struct urb *urb, int interrupt, struct pt_regs *regs)
 {
 	struct hid_device *hid = urb->context;
 	struct hid_report_enum *report_enum = hid->report_enum + type;
@@ -899,7 +899,7 @@ static int hid_input_report(int type, struct urb *urb, struct pt_regs *regs)
 		hiddev_report_event(hid, report);
 
 	for (n = 0; n < report->maxfield; n++)
-		hid_input_field(hid, report->field[n], data, regs);
+		hid_input_field(hid, report->field[n], data, interrupt, regs);
 
 	if (hid->claimed & HID_CLAIMED_INPUT)
 		hidinput_report_event(hid, report);
@@ -918,7 +918,7 @@ static void hid_irq_in(struct urb *urb, struct pt_regs *regs)
 
 	switch (urb->status) {
 		case 0:			/* success */
-			hid_input_report(HID_INPUT_REPORT, urb, regs);
+			hid_input_report(HID_INPUT_REPORT, urb, 1, regs);
 			break;
 		case -ECONNRESET:	/* unlink */
 		case -ENOENT:
@@ -1142,7 +1142,7 @@ static void hid_ctrl(struct urb *urb, struct pt_regs *regs)
 	switch (urb->status) {
 		case 0:			/* success */
 			if (hid->ctrl[hid->ctrltail].dir == USB_DIR_IN)
-				hid_input_report(hid->ctrl[hid->ctrltail].report->type, urb, regs);
+				hid_input_report(hid->ctrl[hid->ctrltail].report->type, urb, 0, regs);
 		case -ESHUTDOWN:	/* unplug */
 		case -EILSEQ:		/* unplug timectrl on uhci */
 			unplug = 1;
@@ -1372,6 +1372,9 @@ void hid_init_reports(struct hid_device *hid)
 #define USB_VENDOR_ID_A4TECH		0x09da
 #define USB_DEVICE_ID_A4TECH_WCP32PU	0x0006
 
+#define USB_VENDOR_ID_AASHIMA		0x06D6
+#define USB_DEVICE_ID_AASHIMA_GAMEPAD	0x0025
+
 #define USB_VENDOR_ID_CYPRESS		0x04b4
 #define USB_DEVICE_ID_CYPRESS_MOUSE	0x0001
 #define USB_DEVICE_ID_CYPRESS_HIDCOM	0x5500
@@ -1548,6 +1551,7 @@ static struct hid_blacklist {
 	{ USB_VENDOR_ID_A4TECH, USB_DEVICE_ID_A4TECH_WCP32PU, HID_QUIRK_2WHEEL_MOUSE_HACK_7 },
 	{ USB_VENDOR_ID_CYPRESS, USB_DEVICE_ID_CYPRESS_MOUSE, HID_QUIRK_2WHEEL_MOUSE_HACK_5 },
 
+	{ USB_VENDOR_ID_AASHIMA, USB_DEVICE_ID_AASHIMA_GAMEPAD, HID_QUIRK_BADPAD },
 	{ USB_VENDOR_ID_ALPS, USB_DEVICE_ID_IBM_GAMEPAD, HID_QUIRK_BADPAD },
 	{ USB_VENDOR_ID_CHIC, USB_DEVICE_ID_CHIC_GAMEPAD, HID_QUIRK_BADPAD },
 	{ USB_VENDOR_ID_HAPP, USB_DEVICE_ID_UGCI_DRIVING, HID_QUIRK_BADPAD | HID_QUIRK_MULTI_INPUT },
diff --git a/drivers/usb/input/hid-input.c b/drivers/usb/input/hid-input.c
index 9ac1e909533..63a4db721f7 100644
--- a/drivers/usb/input/hid-input.c
+++ b/drivers/usb/input/hid-input.c
@@ -31,6 +31,7 @@
 #include <linux/kernel.h>
 #include <linux/input.h>
 #include <linux/usb.h>
+#include <linux/usb_input.h>
 
 #undef DEBUG
 
@@ -397,11 +398,12 @@ ignore:
 
 void hidinput_hid_event(struct hid_device *hid, struct hid_field *field, struct hid_usage *usage, __s32 value, struct pt_regs *regs)
 {
-	struct input_dev *input = &field->hidinput->input;
+	struct input_dev *input;
 	int *quirks = &hid->quirks;
 
-	if (!input)
+	if (!field->hidinput)
 		return;
+	input = &field->hidinput->input;
 
 	input_regs(input, regs);
 
@@ -581,10 +583,7 @@ int hidinput_connect(struct hid_device *hid)
 				hidinput->input.name = hid->name;
 				hidinput->input.phys = hid->phys;
 				hidinput->input.uniq = hid->uniq;
-				hidinput->input.id.bustype = BUS_USB;
-				hidinput->input.id.vendor = le16_to_cpu(dev->descriptor.idVendor);
-				hidinput->input.id.product = le16_to_cpu(dev->descriptor.idProduct);
-				hidinput->input.id.version = le16_to_cpu(dev->descriptor.bcdDevice);
+				usb_to_input_id(dev, &hidinput->input.id);
 				hidinput->input.dev = &hid->intf->dev;
 			}
 
diff --git a/drivers/usb/input/itmtouch.c b/drivers/usb/input/itmtouch.c
index 47dec6a1b34..0dc439f1082 100644
--- a/drivers/usb/input/itmtouch.c
+++ b/drivers/usb/input/itmtouch.c
@@ -53,6 +53,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/usb.h>
+#include <linux/usb_input.h>
 
 /* only an 8 byte buffer necessary for a single packet */
 #define ITM_BUFSIZE			8
@@ -184,10 +185,7 @@ static int itmtouch_probe(struct usb_interface *intf, const struct usb_device_id
 
 	itmtouch->inputdev.name = itmtouch->name;
 	itmtouch->inputdev.phys = itmtouch->phys;
-	itmtouch->inputdev.id.bustype = BUS_USB;
-	itmtouch->inputdev.id.vendor = udev->descriptor.idVendor;
-	itmtouch->inputdev.id.product = udev->descriptor.idProduct;
-	itmtouch->inputdev.id.version = udev->descriptor.bcdDevice;
+	usb_to_input_id(udev, &itmtouch->inputdev.id);
 	itmtouch->inputdev.dev = &intf->dev;
 
 	if (!strlen(itmtouch->name))
diff --git a/drivers/usb/input/kbtab.c b/drivers/usb/input/kbtab.c
index d2f0f90a9bc..b6f6ac8d9c2 100644
--- a/drivers/usb/input/kbtab.c
+++ b/drivers/usb/input/kbtab.c
@@ -4,6 +4,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/usb.h>
+#include <linux/usb_input.h>
 #include <asm/unaligned.h>
 #include <asm/byteorder.h>
 
@@ -167,10 +168,7 @@ static int kbtab_probe(struct usb_interface *intf, const struct usb_device_id *i
 
 	kbtab->dev.name = "KB Gear Tablet";
 	kbtab->dev.phys = kbtab->phys;
-	kbtab->dev.id.bustype = BUS_USB;
-	kbtab->dev.id.vendor = le16_to_cpu(dev->descriptor.idVendor);
-	kbtab->dev.id.product = le16_to_cpu(dev->descriptor.idProduct);
-	kbtab->dev.id.version = le16_to_cpu(dev->descriptor.bcdDevice);
+	usb_to_input_id(dev, &kbtab->dev.id);
 	kbtab->dev.dev = &intf->dev;
 	kbtab->usbdev = dev;
 
diff --git a/drivers/usb/input/mtouchusb.c b/drivers/usb/input/mtouchusb.c
index 09b5cc7c66d..ff9275057a1 100644
--- a/drivers/usb/input/mtouchusb.c
+++ b/drivers/usb/input/mtouchusb.c
@@ -53,6 +53,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/usb.h>
+#include <linux/usb_input.h>
 
 #define MTOUCHUSB_MIN_XC                0x0
 #define MTOUCHUSB_MAX_RAW_XC            0x4000
@@ -232,10 +233,7 @@ static int mtouchusb_probe(struct usb_interface *intf, const struct usb_device_i
 
 	mtouch->input.name = mtouch->name;
 	mtouch->input.phys = mtouch->phys;
-	mtouch->input.id.bustype = BUS_USB;
-	mtouch->input.id.vendor = le16_to_cpu(udev->descriptor.idVendor);
-	mtouch->input.id.product = le16_to_cpu(udev->descriptor.idProduct);
-	mtouch->input.id.version = le16_to_cpu(udev->descriptor.bcdDevice);
+	usb_to_input_id(udev, &mtouch->input.id);
 	mtouch->input.dev = &intf->dev;
 
 	mtouch->input.evbit[0] = BIT(EV_KEY) | BIT(EV_ABS);
diff --git a/drivers/usb/input/powermate.c b/drivers/usb/input/powermate.c
index 3975b309d55..ad4afe7e589 100644
--- a/drivers/usb/input/powermate.c
+++ b/drivers/usb/input/powermate.c
@@ -35,6 +35,7 @@
 #include <linux/init.h>
 #include <linux/spinlock.h>
 #include <linux/usb.h>
+#include <linux/usb_input.h>
 
 #define POWERMATE_VENDOR	0x077d	/* Griffin Technology, Inc. */
 #define POWERMATE_PRODUCT_NEW	0x0410	/* Griffin PowerMate */
@@ -389,10 +390,7 @@ static int powermate_probe(struct usb_interface *intf, const struct usb_device_i
 	pm->input.keybit[LONG(BTN_0)] = BIT(BTN_0);
 	pm->input.relbit[LONG(REL_DIAL)] = BIT(REL_DIAL);
 	pm->input.mscbit[LONG(MSC_PULSELED)] = BIT(MSC_PULSELED);
-	pm->input.id.bustype = BUS_USB;
-	pm->input.id.vendor = le16_to_cpu(udev->descriptor.idVendor);
-	pm->input.id.product = le16_to_cpu(udev->descriptor.idProduct);
-	pm->input.id.version = le16_to_cpu(udev->descriptor.bcdDevice);
+	usb_to_input_id(udev, &pm->input.id);
 	pm->input.event = powermate_input_event;
 	pm->input.dev = &intf->dev;
 	pm->input.phys = pm->phys;
diff --git a/drivers/usb/input/touchkitusb.c b/drivers/usb/input/touchkitusb.c
index 386595ee21c..4276c24a508 100644
--- a/drivers/usb/input/touchkitusb.c
+++ b/drivers/usb/input/touchkitusb.c
@@ -35,7 +35,7 @@
 #define DEBUG
 #endif
 #include <linux/usb.h>
-
+#include <linux/usb_input.h>
 
 #define TOUCHKIT_MIN_XC			0x0
 #define TOUCHKIT_MAX_XC			0x07ff
@@ -202,10 +202,7 @@ static int touchkit_probe(struct usb_interface *intf,
 
 	touchkit->input.name = touchkit->name;
 	touchkit->input.phys = touchkit->phys;
-	touchkit->input.id.bustype = BUS_USB;
-	touchkit->input.id.vendor = le16_to_cpu(udev->descriptor.idVendor);
-	touchkit->input.id.product = le16_to_cpu(udev->descriptor.idProduct);
-	touchkit->input.id.version = le16_to_cpu(udev->descriptor.bcdDevice);
+	usb_to_input_id(udev, &touchkit->input.id);
 	touchkit->input.dev = &intf->dev;
 
 	touchkit->input.evbit[0] = BIT(EV_KEY) | BIT(EV_ABS);
diff --git a/drivers/usb/input/usbkbd.c b/drivers/usb/input/usbkbd.c
index f35db1974c4..28987f15eee 100644
--- a/drivers/usb/input/usbkbd.c
+++ b/drivers/usb/input/usbkbd.c
@@ -32,6 +32,7 @@
 #include <linux/input.h>
 #include <linux/init.h>
 #include <linux/usb.h>
+#include <linux/usb_input.h>
 
 /*
  * Version Information
@@ -288,10 +289,7 @@ static int usb_kbd_probe(struct usb_interface *iface,
 
 	kbd->dev.name = kbd->name;
 	kbd->dev.phys = kbd->phys;
-	kbd->dev.id.bustype = BUS_USB;
-	kbd->dev.id.vendor = le16_to_cpu(dev->descriptor.idVendor);
-	kbd->dev.id.product = le16_to_cpu(dev->descriptor.idProduct);
-	kbd->dev.id.version = le16_to_cpu(dev->descriptor.bcdDevice);
+	usb_to_input_id(dev, &kbd->dev.id);
 	kbd->dev.dev = &iface->dev;
 
 	if (dev->manufacturer)
diff --git a/drivers/usb/input/usbmouse.c b/drivers/usb/input/usbmouse.c
index 1ec41b5effe..4104dec847f 100644
--- a/drivers/usb/input/usbmouse.c
+++ b/drivers/usb/input/usbmouse.c
@@ -32,6 +32,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/usb.h>
+#include <linux/usb_input.h>
 
 /*
  * Version Information
@@ -171,10 +172,7 @@ static int usb_mouse_probe(struct usb_interface * intf, const struct usb_device_
 
 	mouse->dev.name = mouse->name;
 	mouse->dev.phys = mouse->phys;
-	mouse->dev.id.bustype = BUS_USB;
-	mouse->dev.id.vendor = le16_to_cpu(dev->descriptor.idVendor);
-	mouse->dev.id.product = le16_to_cpu(dev->descriptor.idProduct);
-	mouse->dev.id.version = le16_to_cpu(dev->descriptor.bcdDevice);
+	usb_to_input_id(dev, &mouse->dev.id);
 	mouse->dev.dev = &intf->dev;
 
 	if (dev->manufacturer)
diff --git a/drivers/usb/input/wacom.c b/drivers/usb/input/wacom.c
index f6b34af66b3..02412e31a46 100644
--- a/drivers/usb/input/wacom.c
+++ b/drivers/usb/input/wacom.c
@@ -69,6 +69,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/usb.h>
+#include <linux/usb_input.h>
 #include <asm/unaligned.h>
 #include <asm/byteorder.h>
 
@@ -823,10 +824,7 @@ static int wacom_probe(struct usb_interface *intf, const struct usb_device_id *i
 
 	wacom->dev.name = wacom->features->name;
 	wacom->dev.phys = wacom->phys;
-	wacom->dev.id.bustype = BUS_USB;
-	wacom->dev.id.vendor = le16_to_cpu(dev->descriptor.idVendor);
-	wacom->dev.id.product = le16_to_cpu(dev->descriptor.idProduct);
-	wacom->dev.id.version = le16_to_cpu(dev->descriptor.bcdDevice);
+	usb_to_input_id(dev, &wacom->dev.id);
 	wacom->dev.dev = &intf->dev;
 	wacom->usbdev = dev;
 
diff --git a/drivers/usb/input/xpad.c b/drivers/usb/input/xpad.c
index a7fa1b17dcf..18125e0bffa 100644
--- a/drivers/usb/input/xpad.c
+++ b/drivers/usb/input/xpad.c
@@ -62,6 +62,7 @@
 #include <linux/module.h>
 #include <linux/smp_lock.h>
 #include <linux/usb.h>
+#include <linux/usb_input.h>
 
 #define DRIVER_VERSION "v0.0.5"
 #define DRIVER_AUTHOR "Marko Friedemann <mfr@bmx-chemnitz.de>"
@@ -256,10 +257,7 @@ static int xpad_probe(struct usb_interface *intf, const struct usb_device_id *id
 
 	xpad->udev = udev;
 
-	xpad->dev.id.bustype = BUS_USB;
-	xpad->dev.id.vendor = le16_to_cpu(udev->descriptor.idVendor);
-	xpad->dev.id.product = le16_to_cpu(udev->descriptor.idProduct);
-	xpad->dev.id.version = le16_to_cpu(udev->descriptor.bcdDevice);
+	usb_to_input_id(udev, &xpad->dev.id);
 	xpad->dev.dev = &intf->dev;
 	xpad->dev.private = xpad;
 	xpad->dev.name = xpad_device[i].name;
diff --git a/drivers/usb/media/konicawc.c b/drivers/usb/media/konicawc.c
index 08521a2b4f3..20ac9e1069d 100644
--- a/drivers/usb/media/konicawc.c
+++ b/drivers/usb/media/konicawc.c
@@ -16,6 +16,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/input.h>
+#include <linux/usb_input.h>
 
 #include "usbvideo.h"
 
@@ -845,10 +846,7 @@ static int konicawc_probe(struct usb_interface *intf, const struct usb_device_id
 		cam->input.private = cam;
 		cam->input.evbit[0] = BIT(EV_KEY);
 		cam->input.keybit[LONG(BTN_0)] = BIT(BTN_0);
-		cam->input.id.bustype = BUS_USB;
-		cam->input.id.vendor = le16_to_cpu(dev->descriptor.idVendor);
-		cam->input.id.product = le16_to_cpu(dev->descriptor.idProduct);
-		cam->input.id.version = le16_to_cpu(dev->descriptor.bcdDevice);
+		usb_to_input_id(dev, &cam->input.id);
 		input_register_device(&cam->input);
 		
 		usb_make_path(dev, cam->input_physname, 56);
diff --git a/drivers/usb/misc/ldusb.c b/drivers/usb/misc/ldusb.c
index 66ec88354b9..ad17892aac9 100644
--- a/drivers/usb/misc/ldusb.c
+++ b/drivers/usb/misc/ldusb.c
@@ -23,6 +23,7 @@
  *
  * V0.1  (mh) Initial version
  * V0.11 (mh) Added raw support for HID 1.0 devices (no interrupt out endpoint)
+ * V0.12 (mh) Added kmalloc check for string buffer
  */
 
 #include <linux/config.h>
@@ -84,7 +85,7 @@ static struct usb_device_id ld_usb_table [] = {
 	{ }					/* Terminating entry */
 };
 MODULE_DEVICE_TABLE(usb, ld_usb_table);
-MODULE_VERSION("V0.11");
+MODULE_VERSION("V0.12");
 MODULE_AUTHOR("Michael Hund <mhund@ld-didactic.de>");
 MODULE_DESCRIPTION("LD USB Driver");
 MODULE_LICENSE("GPL");
@@ -635,6 +636,10 @@ static int ld_usb_probe(struct usb_interface *intf, const struct usb_device_id *
 	     (le16_to_cpu(udev->descriptor.idProduct) == USB_DEVICE_ID_COM3LAB)) &&
 	    (le16_to_cpu(udev->descriptor.bcdDevice) <= 0x103)) {
 		buffer = kmalloc(256, GFP_KERNEL);
+		if (buffer == NULL) {
+			dev_err(&intf->dev, "Couldn't allocate string buffer\n");
+			goto error;
+		}
 		/* usb_string makes SETUP+STALL to leave always ControlReadLoop */
 		usb_string(udev, 255, buffer, 256);
 		kfree(buffer);
diff --git a/drivers/usb/mon/Kconfig b/drivers/usb/mon/Kconfig
index 777642e26b9..deb9ddffa40 100644
--- a/drivers/usb/mon/Kconfig
+++ b/drivers/usb/mon/Kconfig
@@ -9,9 +9,8 @@ config USB_MON
 	help
 	  If you say Y here, a component which captures the USB traffic
 	  between peripheral-specific drivers and HC drivers will be built.
-	  The USB_MON is similar in spirit and may be compatible with Dave
-	  Harding's USBMon.
+	  For more information, see <file:Documentation/usb/usbmon.txt>.
 
-	  This is somewhat experimental at this time, but it should be safe,
-	  as long as you aren't using modular USB and try to remove this
-	  module.
+	  This is somewhat experimental at this time, but it should be safe.
+
+	  If unsure, say Y.
diff --git a/drivers/usb/mon/Makefile b/drivers/usb/mon/Makefile
index f18d10ce91f..b0015b8a1d1 100644
--- a/drivers/usb/mon/Makefile
+++ b/drivers/usb/mon/Makefile
@@ -4,4 +4,5 @@
 
 usbmon-objs	:= mon_main.o mon_stat.o mon_text.o
 
+# This does not use CONFIG_USB_MON because we want this to use a tristate.
 obj-$(CONFIG_USB)	+= usbmon.o
diff --git a/drivers/usb/net/pegasus.c b/drivers/usb/net/pegasus.c
index 5f4496d8dba..fcd6d3ccef4 100644
--- a/drivers/usb/net/pegasus.c
+++ b/drivers/usb/net/pegasus.c
@@ -59,7 +59,6 @@ static const char driver_name[] = "pegasus";
 
 static int loopback = 0;
 static int mii_mode = 0;
-static int multicast_filter_limit = 32;
 
 static struct usb_eth_dev usb_dev_id[] = {
 #define	PEGASUS_DEV(pn, vid, pid, flags)	\
diff --git a/drivers/usb/net/rtl8150.c b/drivers/usb/net/rtl8150.c
index 626b016addf..59ab40ebb39 100644
--- a/drivers/usb/net/rtl8150.c
+++ b/drivers/usb/net/rtl8150.c
@@ -167,8 +167,6 @@ struct rtl8150 {
 
 typedef struct rtl8150 rtl8150_t;
 
-static unsigned long multicast_filter_limit = 32;
-
 static void fill_skb_pool(rtl8150_t *);
 static void free_skb_pool(rtl8150_t *);
 static inline struct sk_buff *pull_skb(rtl8150_t *);
diff --git a/drivers/usb/net/zd1201.c b/drivers/usb/net/zd1201.c
index 3b387b00573..29cd801eb95 100644
--- a/drivers/usb/net/zd1201.c
+++ b/drivers/usb/net/zd1201.c
@@ -29,6 +29,7 @@ static struct usb_device_id zd1201_table[] = {
 	{USB_DEVICE(0x0ace, 0x1201)}, /* ZyDAS ZD1201 Wireless USB Adapter */
 	{USB_DEVICE(0x050d, 0x6051)}, /* Belkin F5D6051 usb  adapter */
 	{USB_DEVICE(0x0db0, 0x6823)}, /* MSI UB11B usb  adapter */
+	{USB_DEVICE(0x1044, 0x8005)}, /* GIGABYTE GN-WLBZ201 usb adapter */
 	{}
 };
 
diff --git a/drivers/usb/serial/ftdi_sio.c b/drivers/usb/serial/ftdi_sio.c
index 0b03ddab53d..d1964a0c416 100644
--- a/drivers/usb/serial/ftdi_sio.c
+++ b/drivers/usb/serial/ftdi_sio.c
@@ -429,6 +429,9 @@ static struct usb_device_id id_table_combined [] = {
 	{ USB_DEVICE(FTDI_VID, FTDI_4N_GALAXY_DE_2_PID) },
 	{ USB_DEVICE(MOBILITY_VID, MOBILITY_USB_SERIAL_PID) },
 	{ USB_DEVICE(FTDI_VID, FTDI_ACTIVE_ROBOTS_PID) },
+	{ USB_DEVICE(FTDI_VID, FTDI_MHAM_Y6_PID) },
+	{ USB_DEVICE(FTDI_VID, FTDI_MHAM_Y8_PID) },
+	{ USB_DEVICE(EVOLUTION_VID, EVOLUTION_ER1_PID) },
 	{ }						/* Terminating entry */
 };
 
@@ -545,6 +548,7 @@ static struct usb_serial_device_type ftdi_sio_device = {
 
 
 #define WDR_TIMEOUT 5000 /* default urb timeout */
+#define WDR_SHORT_TIMEOUT 1000	/* shorter urb timeout */
 
 /* High and low are for DTR, RTS etc etc */
 #define HIGH 1
@@ -593,62 +597,59 @@ static __u32 ftdi_232bm_baud_to_divisor(int baud)
 	 return(ftdi_232bm_baud_base_to_divisor(baud, 48000000));
 }
 
-static int set_rts(struct usb_serial_port *port, int high_or_low)
+#define set_mctrl(port, set)		update_mctrl((port), (set), 0)
+#define clear_mctrl(port, clear)	update_mctrl((port), 0, (clear))
+
+static int update_mctrl(struct usb_serial_port *port, unsigned int set, unsigned int clear)
 {
 	struct ftdi_private *priv = usb_get_serial_port_data(port);
 	char *buf;
-	unsigned ftdi_high_or_low;
+	unsigned urb_value;
 	int rv;
-	
-	buf = kmalloc(1, GFP_NOIO);
-	if (!buf)
-		return -ENOMEM;
-	
-	if (high_or_low) {
-		ftdi_high_or_low = FTDI_SIO_SET_RTS_HIGH;
-		priv->last_dtr_rts |= TIOCM_RTS;
-	} else {
-		ftdi_high_or_low = FTDI_SIO_SET_RTS_LOW;
-		priv->last_dtr_rts &= ~TIOCM_RTS;
-	}
-	rv = usb_control_msg(port->serial->dev,
-			       usb_sndctrlpipe(port->serial->dev, 0),
-			       FTDI_SIO_SET_MODEM_CTRL_REQUEST, 
-			       FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE,
-			       ftdi_high_or_low, priv->interface, 
-			       buf, 0, WDR_TIMEOUT);
-
-	kfree(buf);
-	return rv;
-}
 
+	if (((set | clear) & (TIOCM_DTR | TIOCM_RTS)) == 0) {
+		dbg("%s - DTR|RTS not being set|cleared", __FUNCTION__);
+		return 0;	/* no change */
+	}
 
-static int set_dtr(struct usb_serial_port *port, int high_or_low)
-{
-	struct ftdi_private *priv = usb_get_serial_port_data(port);
-	char *buf;
-	unsigned ftdi_high_or_low;
-	int rv;
-	
 	buf = kmalloc(1, GFP_NOIO);
-	if (!buf)
+	if (!buf) {
 		return -ENOMEM;
-
-	if (high_or_low) {
-		ftdi_high_or_low = FTDI_SIO_SET_DTR_HIGH;
-		priv->last_dtr_rts |= TIOCM_DTR;
-	} else {
-		ftdi_high_or_low = FTDI_SIO_SET_DTR_LOW;
-		priv->last_dtr_rts &= ~TIOCM_DTR;
 	}
+
+	clear &= ~set;	/* 'set' takes precedence over 'clear' */
+	urb_value = 0;
+	if (clear & TIOCM_DTR)
+		urb_value |= FTDI_SIO_SET_DTR_LOW;
+	if (clear & TIOCM_RTS)
+		urb_value |= FTDI_SIO_SET_RTS_LOW;
+	if (set & TIOCM_DTR)
+		urb_value |= FTDI_SIO_SET_DTR_HIGH;
+	if (set & TIOCM_RTS)
+		urb_value |= FTDI_SIO_SET_RTS_HIGH;
 	rv = usb_control_msg(port->serial->dev,
 			       usb_sndctrlpipe(port->serial->dev, 0),
 			       FTDI_SIO_SET_MODEM_CTRL_REQUEST, 
 			       FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE,
-			       ftdi_high_or_low, priv->interface, 
+			       urb_value, priv->interface,
 			       buf, 0, WDR_TIMEOUT);
 
 	kfree(buf);
+	if (rv < 0) {
+		err("%s Error from MODEM_CTRL urb: DTR %s, RTS %s",
+				__FUNCTION__,
+				(set & TIOCM_DTR) ? "HIGH" :
+				(clear & TIOCM_DTR) ? "LOW" : "unchanged",
+				(set & TIOCM_RTS) ? "HIGH" :
+				(clear & TIOCM_RTS) ? "LOW" : "unchanged");
+	} else {
+		dbg("%s - DTR %s, RTS %s", __FUNCTION__,
+				(set & TIOCM_DTR) ? "HIGH" :
+				(clear & TIOCM_DTR) ? "LOW" : "unchanged",
+				(set & TIOCM_RTS) ? "HIGH" :
+				(clear & TIOCM_RTS) ? "LOW" : "unchanged");
+		priv->last_dtr_rts = (priv->last_dtr_rts & ~clear) | set;
+	}
 	return rv;
 }
 
@@ -681,7 +682,7 @@ static int change_speed(struct usb_serial_port *port)
 			    FTDI_SIO_SET_BAUDRATE_REQUEST,
 			    FTDI_SIO_SET_BAUDRATE_REQUEST_TYPE,
 			    urb_value, urb_index,
-			    buf, 0, 100);
+			    buf, 0, WDR_SHORT_TIMEOUT);
 
 	kfree(buf);
 	return rv;
@@ -1219,12 +1220,7 @@ static int  ftdi_open (struct usb_serial_port *port, struct file *filp)
 	/* FIXME: Flow control might be enabled, so it should be checked -
 	   we have no control of defaults! */
 	/* Turn on RTS and DTR since we are not flow controlling by default */
-	if (set_dtr(port, HIGH) < 0) {
-		err("%s Error from DTR HIGH urb", __FUNCTION__);
-	}
-	if (set_rts(port, HIGH) < 0){
-		err("%s Error from RTS HIGH urb", __FUNCTION__);
-	}
+	set_mctrl(port, TIOCM_DTR | TIOCM_RTS);
 
 	/* Not throttled */
 	spin_lock_irqsave(&priv->rx_lock, flags);
@@ -1274,14 +1270,8 @@ static void ftdi_close (struct usb_serial_port *port, struct file *filp)
 			err("error from flowcontrol urb");
 		}	    
 
-		/* drop DTR */
-		if (set_dtr(port, LOW) < 0){
-			err("Error from DTR LOW urb");
-		}
-		/* drop RTS */
-		if (set_rts(port, LOW) < 0) {
-			err("Error from RTS LOW urb");
-		}
+		/* drop RTS and DTR */
+		clear_mctrl(port, TIOCM_DTR | TIOCM_RTS);
 	} /* Note change no line if hupcl is off */
 
 	/* cancel any scheduled reading */
@@ -1797,7 +1787,7 @@ static void ftdi_set_termios (struct usb_serial_port *port, struct termios *old_
 			    FTDI_SIO_SET_DATA_REQUEST, 
 			    FTDI_SIO_SET_DATA_REQUEST_TYPE,
 			    urb_value , priv->interface,
-			    buf, 0, 100) < 0) {
+			    buf, 0, WDR_SHORT_TIMEOUT) < 0) {
 		err("%s FAILED to set databits/stopbits/parity", __FUNCTION__);
 	}	   
 
@@ -1812,25 +1802,14 @@ static void ftdi_set_termios (struct usb_serial_port *port, struct termios *old_
 			err("%s error from disable flowcontrol urb", __FUNCTION__);
 		}	    
 		/* Drop RTS and DTR */
-		if (set_dtr(port, LOW) < 0){
-			err("%s Error from DTR LOW urb", __FUNCTION__);
-		}
-		if (set_rts(port, LOW) < 0){
-			err("%s Error from RTS LOW urb", __FUNCTION__);
-		}	
-		
+		clear_mctrl(port, TIOCM_DTR | TIOCM_RTS);
 	} else {
 		/* set the baudrate determined before */
 		if (change_speed(port)) {
 			err("%s urb failed to set baurdrate", __FUNCTION__);
 		}
 		/* Ensure  RTS and DTR are raised */
-		else if (set_dtr(port, HIGH) < 0){
-			err("%s Error from DTR HIGH urb", __FUNCTION__);
-		}
-		else if (set_rts(port, HIGH) < 0){
-			err("%s Error from RTS HIGH urb", __FUNCTION__);
-		}	
+		set_mctrl(port, TIOCM_DTR | TIOCM_RTS);
 	}
 
 	/* Set flow control */
@@ -1942,35 +1921,8 @@ static int ftdi_tiocmget (struct usb_serial_port *port, struct file *file)
 
 static int ftdi_tiocmset(struct usb_serial_port *port, struct file * file, unsigned int set, unsigned int clear)
 {
-	int ret;
-	
 	dbg("%s TIOCMSET", __FUNCTION__);
-	if (set & TIOCM_DTR){
-		if ((ret = set_dtr(port, HIGH)) < 0) {
-			err("Urb to set DTR failed");
-			return(ret);
-		}
-	}
-	if (set & TIOCM_RTS) {
-		if ((ret = set_rts(port, HIGH)) < 0){
-			err("Urb to set RTS failed");
-			return(ret);
-		}
-	}
-	
-	if (clear & TIOCM_DTR){
-		if ((ret = set_dtr(port, LOW)) < 0){
-			err("Urb to unset DTR failed");
-			return(ret);
-		}
-	}	
-	if (clear & TIOCM_RTS) {
-		if ((ret = set_rts(port, LOW)) < 0){
-			err("Urb to unset RTS failed");
-			return(ret);
-		}
-	}
-	return(0);
+	return update_mctrl(port, set, clear);
 }
 
 
diff --git a/drivers/usb/serial/ftdi_sio.h b/drivers/usb/serial/ftdi_sio.h
index 8866376823a..9f4342093e8 100644
--- a/drivers/usb/serial/ftdi_sio.h
+++ b/drivers/usb/serial/ftdi_sio.h
@@ -265,10 +265,24 @@
 #define MOBILITY_USB_SERIAL_PID		0x0202	/* EasiDock USB 200 serial */
 
 /*
+ * microHAM product IDs (http://www.microham.com).
+ * Submitted by Justin Burket (KL1RL) <zorton@jtan.com>.
+ */
+#define FTDI_MHAM_Y6_PID 0xEEEA		/* USB-Y6 interface */
+#define FTDI_MHAM_Y8_PID 0xEEEB		/* USB-Y8 interface */
+
+/*
  * Active Robots product ids.
  */
 #define FTDI_ACTIVE_ROBOTS_PID	0xE548	/* USB comms board */
 
+/*
+ * Evolution Robotics products (http://www.evolution.com/).
+ * Submitted by Shawn M. Lavelle.
+ */
+#define EVOLUTION_VID		0xDEEE	/* Vendor ID */
+#define EVOLUTION_ER1_PID	0x0300	/* ER1 Control Module */
+
 /* Commands */
 #define FTDI_SIO_RESET 		0 /* Reset the port */
 #define FTDI_SIO_MODEM_CTRL 	1 /* Set the modem control register */
diff --git a/drivers/usb/usb-skeleton.c b/drivers/usb/usb-skeleton.c
index 6051a646fe6..353f24d45bc 100644
--- a/drivers/usb/usb-skeleton.c
+++ b/drivers/usb/usb-skeleton.c
@@ -257,7 +257,8 @@ static int skel_probe(struct usb_interface *interface, const struct usb_device_i
 		endpoint = &iface_desc->endpoint[i].desc;
 
 		if (!dev->bulk_in_endpointAddr &&
-		    (endpoint->bEndpointAddress & USB_DIR_IN) &&
+		    ((endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
+					== USB_DIR_IN) &&
 		    ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
 					== USB_ENDPOINT_XFER_BULK)) {
 			/* we found a bulk in endpoint */
@@ -272,7 +273,8 @@ static int skel_probe(struct usb_interface *interface, const struct usb_device_i
 		}
 
 		if (!dev->bulk_out_endpointAddr &&
-		    !(endpoint->bEndpointAddress & USB_DIR_OUT) &&
+		    ((endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
+					== USB_DIR_OUT) &&
 		    ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
 					== USB_ENDPOINT_XFER_BULK)) {
 			/* we found a bulk out endpoint */
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 04d3120f723..cde0ed097af 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1399,8 +1399,8 @@ config FB_TX3912
 	  Say Y here to enable kernel support for the on-board framebuffer.
 
 config FB_G364
-	bool
-	depends on MIPS_MAGNUM_4000 || OLIVETTI_M700
+	bool "G364 frame buffer support"
+	depends on (FB = y) && (MIPS_MAGNUM_4000 || OLIVETTI_M700)
  	select FB_CFB_FILLRECT
  	select FB_CFB_COPYAREA
  	select FB_CFB_IMAGEBLIT
diff --git a/drivers/video/aty/radeon_base.c b/drivers/video/aty/radeon_base.c
index 47a6b12bc96..e7e8b52014c 100644
--- a/drivers/video/aty/radeon_base.c
+++ b/drivers/video/aty/radeon_base.c
@@ -2521,6 +2521,11 @@ static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
  
 	radeonfb_pm_exit(rinfo);
 
+	if (rinfo->mon1_EDID)
+		sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
+	if (rinfo->mon2_EDID)
+		sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
+
 #if 0
 	/* restore original state
 	 * 
diff --git a/drivers/video/console/fbcon.c b/drivers/video/console/fbcon.c
index 9dd0fbccf99..35c88bd7ba5 100644
--- a/drivers/video/console/fbcon.c
+++ b/drivers/video/console/fbcon.c
@@ -275,7 +275,8 @@ static void fb_flashcursor(void *private)
 
 	if (!vc || !CON_IS_VISIBLE(vc) ||
 	    fbcon_is_inactive(vc, info) ||
- 	    registered_fb[con2fb_map[vc->vc_num]] != info)
+ 	    registered_fb[con2fb_map[vc->vc_num]] != info ||
+	    vc_cons[ops->currcon].d->vc_deccm != 1)
 		return;
 	acquire_console_sem();
 	p = &fb_display[vc->vc_num];
diff --git a/drivers/video/fbcmap.c b/drivers/video/fbcmap.c
index 4e5ce8f7d65..c32a2a50bfa 100644
--- a/drivers/video/fbcmap.c
+++ b/drivers/video/fbcmap.c
@@ -212,7 +212,7 @@ int fb_cmap_to_user(struct fb_cmap *from, struct fb_cmap_user *to)
 
 int fb_set_cmap(struct fb_cmap *cmap, struct fb_info *info)
 {
-	int i, start;
+	int i, start, rc = 0;
 	u16 *red, *green, *blue, *transp;
 	u_int hred, hgreen, hblue, htransp = 0xffff;
 
@@ -225,75 +225,51 @@ int fb_set_cmap(struct fb_cmap *cmap, struct fb_info *info)
 	if (start < 0 || (!info->fbops->fb_setcolreg &&
 			  !info->fbops->fb_setcmap))
 		return -EINVAL;
-	if (info->fbops->fb_setcmap)
-		return info->fbops->fb_setcmap(cmap, info);
-	for (i = 0; i < cmap->len; i++) {
-		hred = *red++;
-		hgreen = *green++;
-		hblue = *blue++;
-		if (transp)
-			htransp = *transp++;
-		if (info->fbops->fb_setcolreg(start++,
-					      hred, hgreen, hblue, htransp,
-					      info))
-			break;
+	if (info->fbops->fb_setcmap) {
+		rc = info->fbops->fb_setcmap(cmap, info);
+	} else {
+		for (i = 0; i < cmap->len; i++) {
+			hred = *red++;
+			hgreen = *green++;
+			hblue = *blue++;
+			if (transp)
+				htransp = *transp++;
+			if (info->fbops->fb_setcolreg(start++,
+						      hred, hgreen, hblue,
+						      htransp, info))
+				break;
+		}
 	}
-	return 0;
+	if (rc == 0)
+		fb_copy_cmap(cmap, &info->cmap);
+
+	return rc;
 }
 
 int fb_set_user_cmap(struct fb_cmap_user *cmap, struct fb_info *info)
 {
-	int i, start;
-	u16 __user *red, *green, *blue, *transp;
-	u_int hred, hgreen, hblue, htransp = 0xffff;
-
-	red = cmap->red;
-	green = cmap->green;
-	blue = cmap->blue;
-	transp = cmap->transp;
-	start = cmap->start;
+	int rc, size = cmap->len * sizeof(u16);
+	struct fb_cmap umap;
 
-	if (start < 0 || (!info->fbops->fb_setcolreg &&
-			  !info->fbops->fb_setcmap))
+	if (cmap->start < 0 || (!info->fbops->fb_setcolreg &&
+			        !info->fbops->fb_setcmap))
 		return -EINVAL;
 
-	/* If we can batch, do it */
-	if (info->fbops->fb_setcmap && cmap->len > 1) {
-		struct fb_cmap umap;
-		int size = cmap->len * sizeof(u16);
-		int rc;
-
-		memset(&umap, 0, sizeof(struct fb_cmap));
-		rc = fb_alloc_cmap(&umap, cmap->len, transp != NULL);
-		if (rc)
-			return rc;
-		if (copy_from_user(umap.red, red, size) ||
-		    copy_from_user(umap.green, green, size) ||
-		    copy_from_user(umap.blue, blue, size) ||
-		    (transp && copy_from_user(umap.transp, transp, size))) {
-			rc = -EFAULT;
-		}
-		umap.start = start;
-		if (rc == 0)
-			rc = info->fbops->fb_setcmap(&umap, info);
-		fb_dealloc_cmap(&umap);
+	memset(&umap, 0, sizeof(struct fb_cmap));
+	rc = fb_alloc_cmap(&umap, cmap->len, cmap->transp != NULL);
+	if (rc)
 		return rc;
+	if (copy_from_user(umap.red, cmap->red, size) ||
+	    copy_from_user(umap.green, cmap->green, size) ||
+	    copy_from_user(umap.blue, cmap->blue, size) ||
+	    (cmap->transp && copy_from_user(umap.transp, cmap->transp, size))) {
+		fb_dealloc_cmap(&umap);
+		return -EFAULT;
 	}
-
-	for (i = 0; i < cmap->len; i++, red++, blue++, green++) {
-		if (get_user(hred, red) ||
-		    get_user(hgreen, green) ||
-		    get_user(hblue, blue) ||
-		    (transp && get_user(htransp, transp)))
-			return -EFAULT;
-		if (info->fbops->fb_setcolreg(start++,
-					      hred, hgreen, hblue, htransp,
-					      info))
-			return 0;
-		if (transp)
-			transp++;
-	}
-	return 0;
+	umap.start = cmap->start;
+	rc = fb_set_cmap(&umap, info);
+	fb_dealloc_cmap(&umap);
+	return rc;
 }
 
 /**
diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c
index 2222de6ad84..d2e19f6dd72 100644
--- a/drivers/video/fbmem.c
+++ b/drivers/video/fbmem.c
@@ -80,10 +80,12 @@ EXPORT_SYMBOL(fb_get_color_depth);
  */
 void fb_pad_aligned_buffer(u8 *dst, u32 d_pitch, u8 *src, u32 s_pitch, u32 height)
 {
-	int i;
+	int i, j;
 
 	for (i = height; i--; ) {
-		memcpy(dst, src, s_pitch);
+		/* s_pitch is a few bytes at the most, memcpy is suboptimal */
+		for (j = 0; j < s_pitch; j++)
+			dst[j] = src[j];
 		src += s_pitch;
 		dst += d_pitch;
 	}
@@ -1164,6 +1166,7 @@ static void __exit
 fbmem_exit(void)
 {
 	class_destroy(fb_class);
+	unregister_chrdev(FB_MAJOR, "fb");
 }
 
 module_exit(fbmem_exit);
diff --git a/drivers/video/fbmon.c b/drivers/video/fbmon.c
index 6cd1976548d..c2718bb9494 100644
--- a/drivers/video/fbmon.c
+++ b/drivers/video/fbmon.c
@@ -1241,6 +1241,8 @@ int fb_validate_mode(const struct fb_var_screeninfo *var, struct fb_info *info)
 		vtotal *= 2;
 
 	hfreq = pixclock/htotal;
+	hfreq = (hfreq + 500) / 1000 * 1000;
+
 	vfreq = hfreq/vtotal;
 
 	return (vfreq < vfmin || vfreq > vfmax || 
diff --git a/drivers/video/fbsysfs.c b/drivers/video/fbsysfs.c
index ddc9443254d..1147b899f00 100644
--- a/drivers/video/fbsysfs.c
+++ b/drivers/video/fbsysfs.c
@@ -242,10 +242,68 @@ static ssize_t show_virtual(struct class_device *class_device, char *buf)
 			fb_info->var.yres_virtual);
 }
 
-static ssize_t store_cmap(struct class_device *class_device, const char * buf,
+/* Format for cmap is "%02x%c%4x%4x%4x\n" */
+/* %02x entry %c transp %4x red %4x blue %4x green \n */
+/* 256 rows at 16 chars equals 4096, the normal page size */
+/* the code will automatically adjust for different page sizes */
+static ssize_t store_cmap(struct class_device *class_device, const char *buf,
 			  size_t count)
 {
-//	struct fb_info *fb_info = (struct fb_info *)class_get_devdata(class_device);
+	struct fb_info *fb_info = (struct fb_info *)class_get_devdata(class_device);
+	int rc, i, start, length, transp = 0;
+
+	if ((count > PAGE_SIZE) || ((count % 16) != 0))
+		return -EINVAL;
+
+	if (!fb_info->fbops->fb_setcolreg && !fb_info->fbops->fb_setcmap)
+		return -EINVAL;
+
+	sscanf(buf, "%02x", &start);
+	length = count / 16;
+
+	for (i = 0; i < length; i++)
+		if (buf[i * 16 + 2] != ' ')
+			transp = 1;
+
+	/* If we can batch, do it */
+	if (fb_info->fbops->fb_setcmap && length > 1) {
+		struct fb_cmap umap;
+
+		memset(&umap, 0, sizeof(umap));
+		if ((rc = fb_alloc_cmap(&umap, length, transp)))
+			return rc;
+
+		umap.start = start;
+		for (i = 0; i < length; i++) {
+			sscanf(&buf[i * 16 +  3], "%4hx", &umap.red[i]);
+			sscanf(&buf[i * 16 +  7], "%4hx", &umap.blue[i]);
+			sscanf(&buf[i * 16 + 11], "%4hx", &umap.green[i]);
+			if (transp)
+				umap.transp[i] = (buf[i * 16 +  2] != ' ');
+		}
+		rc = fb_info->fbops->fb_setcmap(&umap, fb_info);
+		fb_copy_cmap(&umap, &fb_info->cmap);
+		fb_dealloc_cmap(&umap);
+
+		return rc;
+	}
+	for (i = 0; i < length; i++) {
+		u16 red, blue, green, tsp;
+
+		sscanf(&buf[i * 16 +  3], "%4hx", &red);
+		sscanf(&buf[i * 16 +  7], "%4hx", &blue);
+		sscanf(&buf[i * 16 + 11], "%4hx", &green);
+		tsp = (buf[i * 16 +  2] != ' ');
+		if ((rc = fb_info->fbops->fb_setcolreg(start++,
+				      red, green, blue, tsp, fb_info)))
+			return rc;
+
+		fb_info->cmap.red[i] = red;
+		fb_info->cmap.blue[i] = blue;
+		fb_info->cmap.green[i] = green;
+		if (transp)
+			fb_info->cmap.transp[i] = tsp;
+	}
 	return 0;
 }
 
@@ -253,20 +311,24 @@ static ssize_t show_cmap(struct class_device *class_device, char *buf)
 {
 	struct fb_info *fb_info =
 		(struct fb_info *)class_get_devdata(class_device);
-	unsigned int offset = 0, i;
+	unsigned int i;
 
 	if (!fb_info->cmap.red || !fb_info->cmap.blue ||
-	    !fb_info->cmap.green || !fb_info->cmap.transp)
+	   !fb_info->cmap.green)
+		return -EINVAL;
+
+	if (fb_info->cmap.len > PAGE_SIZE / 16)
 		return -EINVAL;
 
+	/* don't mess with the format, the buffer is PAGE_SIZE */
+	/* 256 entries at 16 chars per line equals 4096 = PAGE_SIZE */
 	for (i = 0; i < fb_info->cmap.len; i++) {
-		offset += snprintf(buf, PAGE_SIZE - offset,
-				   "%d,%d,%d,%d,%d\n", i + fb_info->cmap.start,
-				   fb_info->cmap.red[i], fb_info->cmap.blue[i],
-				   fb_info->cmap.green[i],
-				   fb_info->cmap.transp[i]);
+		snprintf(&buf[ i * 16], PAGE_SIZE - i * 16, "%02x%c%4x%4x%4x\n", i + fb_info->cmap.start,
+			((fb_info->cmap.transp && fb_info->cmap.transp[i]) ? '*' : ' '),
+			fb_info->cmap.red[i], fb_info->cmap.blue[i],
+			fb_info->cmap.green[i]);
 	}
-	return offset;
+	return 16 * fb_info->cmap.len;
 }
 
 static ssize_t store_blank(struct class_device *class_device, const char * buf,
@@ -352,6 +414,13 @@ static ssize_t show_pan(struct class_device *class_device, char *buf)
 			fb_info->var.xoffset);
 }
 
+static ssize_t show_name(struct class_device *class_device, char *buf)
+{
+	struct fb_info *fb_info = (struct fb_info *)class_get_devdata(class_device);
+
+	return snprintf(buf, PAGE_SIZE, "%s\n", fb_info->fix.id);
+}
+
 static struct class_device_attribute class_device_attrs[] = {
 	__ATTR(bits_per_pixel, S_IRUGO|S_IWUSR, show_bpp, store_bpp),
 	__ATTR(blank, S_IRUGO|S_IWUSR, show_blank, store_blank),
@@ -362,6 +431,7 @@ static struct class_device_attribute class_device_attrs[] = {
 	__ATTR(modes, S_IRUGO|S_IWUSR, show_modes, store_modes),
 	__ATTR(pan, S_IRUGO|S_IWUSR, show_pan, store_pan),
 	__ATTR(virtual_size, S_IRUGO|S_IWUSR, show_virtual, store_virtual),
+	__ATTR(name, S_IRUGO, show_name, NULL),
 };
 
 int fb_init_class_device(struct fb_info *fb_info)
diff --git a/drivers/video/modedb.c b/drivers/video/modedb.c
index fbf659b6dab..3edc9f49344 100644
--- a/drivers/video/modedb.c
+++ b/drivers/video/modedb.c
@@ -246,6 +246,11 @@ static const struct fb_videomode modedb[] = {
 	/* 480x300 @ 72 Hz, 48.0 kHz hsync */
 	NULL, 72, 480, 300, 33386, 40, 24, 11, 19, 80, 3,
 	0, FB_VMODE_DOUBLE
+    }, {
+	/* 1920x1200 @ 60 Hz, 74.5 Khz hsync */
+	NULL, 60, 1920, 1200, 5177, 128, 336, 1, 38, 208, 3,
+	FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	FB_VMODE_NONINTERLACED
     },
 };
 
diff --git a/drivers/video/nvidia/nvidia.c b/drivers/video/nvidia/nvidia.c
index b2e6b240786..52b16850a54 100644
--- a/drivers/video/nvidia/nvidia.c
+++ b/drivers/video/nvidia/nvidia.c
@@ -1324,6 +1324,13 @@ static int __devinit nvidia_set_fbinfo(struct fb_info *info)
 
 		fb_videomode_to_var(&nvidiafb_default_var, &modedb);
 		nvidiafb_default_var.bits_per_pixel = 8;
+	} else if (par->fpWidth && par->fpHeight) {
+		char buf[16];
+
+		memset(buf, 0, 16);
+		snprintf(buf, 15, "%dx%d", par->fpWidth, par->fpHeight);
+		fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb,
+			     specs->modedb_len, &modedb, 8);
 	}
 
 	if (mode_option)
diff --git a/drivers/video/pm2fb.c b/drivers/video/pm2fb.c
index 5dceddedf50..42c17efa9fb 100644
--- a/drivers/video/pm2fb.c
+++ b/drivers/video/pm2fb.c
@@ -138,27 +138,27 @@ static struct fb_var_screeninfo pm2fb_var __devinitdata = {
  * Utility functions
  */
 
-inline static u32 RD32(unsigned char __iomem *base, s32 off)
+static inline u32 RD32(unsigned char __iomem *base, s32 off)
 {
 	return fb_readl(base + off);
 }
 
-inline static void WR32(unsigned char __iomem *base, s32 off, u32 v)
+static inline void WR32(unsigned char __iomem *base, s32 off, u32 v)
 {
 	fb_writel(v, base + off);
 }
 
-inline static u32 pm2_RD(struct pm2fb_par* p, s32 off)
+static inline u32 pm2_RD(struct pm2fb_par* p, s32 off)
 {
 	return RD32(p->v_regs, off);
 }
 
-inline static void pm2_WR(struct pm2fb_par* p, s32 off, u32 v)
+static inline void pm2_WR(struct pm2fb_par* p, s32 off, u32 v)
 {
 	WR32(p->v_regs, off, v);
 }
 
-inline static u32 pm2_RDAC_RD(struct pm2fb_par* p, s32 idx)
+static inline u32 pm2_RDAC_RD(struct pm2fb_par* p, s32 idx)
 {
 	int index = PM2R_RD_INDEXED_DATA;
 	switch (p->type) {
@@ -174,7 +174,7 @@ inline static u32 pm2_RDAC_RD(struct pm2fb_par* p, s32 idx)
 	return pm2_RD(p, index);
 }
 
-inline static void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
+static inline void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
 {
 	int index = PM2R_RD_INDEXED_DATA;
 	switch (p->type) {
@@ -190,7 +190,7 @@ inline static void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
 	pm2_WR(p, index, v);
 }
 
-inline static void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
+static inline void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
 {
 	pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
 	mb();
@@ -200,7 +200,7 @@ inline static void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
 #define WAIT_FIFO(p,a)
 #else
-inline static void WAIT_FIFO(struct pm2fb_par* p, u32 a)
+static inline void WAIT_FIFO(struct pm2fb_par* p, u32 a)
 {
 	while( pm2_RD(p, PM2R_IN_FIFO_SPACE) < a );
 	mb();
diff --git a/drivers/video/riva/fbdev.c b/drivers/video/riva/fbdev.c
index 6a9e183be41..ae297e22268 100644
--- a/drivers/video/riva/fbdev.c
+++ b/drivers/video/riva/fbdev.c
@@ -1826,7 +1826,7 @@ static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
 #ifdef CONFIG_PPC_OF
 	if (!riva_get_EDID_OF(info, pdev))
 		printk(PFX "could not retrieve EDID from OF\n");
-#elif CONFIG_FB_RIVA_I2C
+#elif defined(CONFIG_FB_RIVA_I2C)
 	if (!riva_get_EDID_i2c(info))
 		printk(PFX "could not retrieve EDID from DDC/I2C\n");
 #endif
diff --git a/drivers/video/sa1100fb.c b/drivers/video/sa1100fb.c
index 2d29db7ef80..beeec7b5142 100644
--- a/drivers/video/sa1100fb.c
+++ b/drivers/video/sa1100fb.c
@@ -598,7 +598,7 @@ sa1100fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  *    requests for the LCD controller.  If we hit this, it means we're
  *    doing nothing but LCD DMA.
  */
-static unsigned int sa1100fb_display_dma_period(struct fb_var_screeninfo *var)
+static inline unsigned int sa1100fb_display_dma_period(struct fb_var_screeninfo *var)
 {
 	/*
 	 * Period = pixclock * bits_per_byte * bytes_per_transfer
diff --git a/drivers/video/tridentfb.c b/drivers/video/tridentfb.c
index da8004e5d03..698ca9232e7 100644
--- a/drivers/video/tridentfb.c
+++ b/drivers/video/tridentfb.c
@@ -454,13 +454,16 @@ static struct accel_switch accel_image = {
 static void tridentfb_fillrect(struct fb_info * info, const struct fb_fillrect *fr)
 {
 	int bpp = info->var.bits_per_pixel;
-	int col;
+	int col = 0;
 	
 	switch (bpp) {
 		default:
-		case 8: col = fr->color;
+		case 8: col |= fr->color;
+			col |= col << 8;
+			col |= col << 16;
 			break;
 		case 16: col = ((u32 *)(info->pseudo_palette))[fr->color];
+			
 			 break;
 		case 32: col = ((u32 *)(info->pseudo_palette))[fr->color];
 			 break;
@@ -882,8 +885,9 @@ static int tridentfb_set_par(struct fb_info *info)
 
 	write3X4(GraphEngReg, 0x80);	//enable GE for text acceleration
 
-//	if (info->var.accel_flags & FB_ACCELF_TEXT)
-//FIXME		acc->init_accel(info->var.xres,bpp);
+#ifdef CONFIG_FB_TRIDENT_ACCEL	
+	acc->init_accel(info->var.xres,bpp);
+#endif
 	
 	switch (bpp) {
 		case 8:  tmp = 0x00; break;
@@ -900,7 +904,7 @@ static int tridentfb_set_par(struct fb_info *info)
 	write3X4(DRAMControl, tmp);	//both IO,linear enable
 
 	write3X4(InterfaceSel, read3X4(InterfaceSel) | 0x40);
-	write3X4(Performance,0x20);
+	write3X4(Performance,0x92);
 	write3X4(PCIReg,0x07);		//MMIO & PCI read and write burst enable
 
 	/* convert from picoseconds to MHz */
@@ -981,12 +985,14 @@ static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
 		t_outb(green>>10,0x3C9);
 		t_outb(blue>>10,0x3C9);
 
-	} else
-	if (bpp == 16) 			/* RGB 565 */
-			((u32*)info->pseudo_palette)[regno] = (red & 0xF800) |
-			((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
-	else
-	if (bpp == 32)		/* ARGB 8888 */
+	} else if (bpp == 16) {	/* RGB 565 */
+		u32 col;
+
+		col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
+			((blue & 0xF800) >> 11);
+		col |= col << 16;	
+		((u32 *)(info->pseudo_palette))[regno] = col;
+	} else if (bpp == 32)		/* ARGB 8888 */
 		((u32*)info->pseudo_palette)[regno] =
 			((transp & 0xFF00) <<16) 	|
 			((red & 0xFF00) << 8) 		|
diff --git a/drivers/video/vesafb.c b/drivers/video/vesafb.c
index 9ed1a931dd3..a272592b037 100644
--- a/drivers/video/vesafb.c
+++ b/drivers/video/vesafb.c
@@ -45,7 +45,7 @@ static struct fb_fix_screeninfo vesafb_fix __initdata = {
 };
 
 static int             inverse   = 0;
-static int             mtrr      = 1;
+static int             mtrr      = 3; /* default to write-combining */
 static int	       vram_remap __initdata = 0; /* Set amount of memory to be used */
 static int	       vram_total __initdata = 0; /* Set total amount of memory */
 static int             pmi_setpal = 0;	/* pmi for palette changes ??? */
@@ -204,8 +204,8 @@ static int __init vesafb_setup(char *options)
 			pmi_setpal=0;
 		else if (! strcmp(this_opt, "pmipal"))
 			pmi_setpal=1;
-		else if (! strcmp(this_opt, "mtrr"))
-			mtrr=1;
+		else if (! strncmp(this_opt, "mtrr:", 5))
+			mtrr = simple_strtoul(this_opt+5, NULL, 0);
 		else if (! strcmp(this_opt, "nomtrr"))
 			mtrr=0;
 		else if (! strncmp(this_opt, "vtotal:", 7))
@@ -387,14 +387,39 @@ static int __init vesafb_probe(struct device *device)
 
 	if (mtrr) {
 		unsigned int temp_size = size_total;
-		/* Find the largest power-of-two */
-		while (temp_size & (temp_size - 1))
-			temp_size &= (temp_size - 1);
-
-		/* Try and find a power of two to add */
-		while (temp_size > PAGE_SIZE &&
-			mtrr_add(vesafb_fix.smem_start, temp_size, MTRR_TYPE_WRCOMB, 1)==-EINVAL) {
-			temp_size >>= 1;
+		unsigned int type = 0;
+
+		switch (mtrr) {
+		case 1:
+			type = MTRR_TYPE_UNCACHABLE;
+			break;
+		case 2:
+			type = MTRR_TYPE_WRBACK;
+			break;
+		case 3:
+			type = MTRR_TYPE_WRCOMB;
+			break;
+		case 4:
+			type = MTRR_TYPE_WRTHROUGH;
+			break;
+		default:
+			type = 0;
+			break;
+		}
+
+		if (type) {
+			int rc;
+
+			/* Find the largest power-of-two */
+			while (temp_size & (temp_size - 1))
+				temp_size &= (temp_size - 1);
+
+			/* Try and find a power of two to add */
+			do {
+				rc = mtrr_add(vesafb_fix.smem_start, temp_size,
+					      type, 1);
+				temp_size >>= 1;
+			} while (temp_size >= PAGE_SIZE && rc == -EINVAL);
 		}
 	}
 	
diff --git a/drivers/w1/Kconfig b/drivers/w1/Kconfig
index 4f120796273..711b90903e7 100644
--- a/drivers/w1/Kconfig
+++ b/drivers/w1/Kconfig
@@ -30,7 +30,7 @@ config W1_DS9490
 	  This support is also available as a module.  If so, the module
 	  will be called ds9490r.ko.
 
-config W1_DS9490R_BRIDGE
+config W1_DS9490_BRIDGE
 	tristate "DS9490R USB <-> W1 transport layer for 1-wire"
 	depends on W1_DS9490
 	help
diff --git a/fs/Kconfig b/fs/Kconfig
index 5d0c4be43db..e54be705835 100644
--- a/fs/Kconfig
+++ b/fs/Kconfig
@@ -363,12 +363,15 @@ config INOTIFY
 	bool "Inotify file change notification support"
 	default y
 	---help---
-	  Say Y here to enable inotify support and the /dev/inotify character
-	  device.  Inotify is a file change notification system and a
+	  Say Y here to enable inotify support and the associated system
+	  calls.  Inotify is a file change notification system and a
 	  replacement for dnotify.  Inotify fixes numerous shortcomings in
 	  dnotify and introduces several new features.  It allows monitoring
-	  of both files and directories via a single open fd.  Multiple file
-	  events are supported.
+	  of both files and directories via a single open fd.  Other features
+	  include multiple file events, one-shot support, and unmount
+	  notification.
+
+	  For more information, see Documentation/filesystems/inotify.txt
 
 	  If unsure, say Y.
 
diff --git a/fs/autofs4/autofs_i.h b/fs/autofs4/autofs_i.h
index 9c09641ce90..fca83e28edc 100644
--- a/fs/autofs4/autofs_i.h
+++ b/fs/autofs4/autofs_i.h
@@ -92,6 +92,7 @@ struct autofs_wait_queue {
 
 struct autofs_sb_info {
 	u32 magic;
+	struct dentry *root;
 	struct file *pipe;
 	pid_t oz_pgrp;
 	int catatonic;
diff --git a/fs/autofs4/inode.c b/fs/autofs4/inode.c
index 4bb14cc6804..0a3c05d1016 100644
--- a/fs/autofs4/inode.c
+++ b/fs/autofs4/inode.c
@@ -16,6 +16,7 @@
 #include <linux/pagemap.h>
 #include <linux/parser.h>
 #include <linux/bitops.h>
+#include <linux/smp_lock.h>
 #include "autofs_i.h"
 #include <linux/module.h>
 
@@ -76,6 +77,66 @@ void autofs4_free_ino(struct autofs_info *ino)
 	kfree(ino);
 }
 
+/*
+ * Deal with the infamous "Busy inodes after umount ..." message.
+ *
+ * Clean up the dentry tree. This happens with autofs if the user
+ * space program goes away due to a SIGKILL, SIGSEGV etc.
+ */
+static void autofs4_force_release(struct autofs_sb_info *sbi)
+{
+	struct dentry *this_parent = sbi->root;
+	struct list_head *next;
+
+	spin_lock(&dcache_lock);
+repeat:
+	next = this_parent->d_subdirs.next;
+resume:
+	while (next != &this_parent->d_subdirs) {
+		struct dentry *dentry = list_entry(next, struct dentry, d_child);
+
+		/* Negative dentry - don`t care */
+		if (!simple_positive(dentry)) {
+			next = next->next;
+			continue;
+		}
+
+		if (!list_empty(&dentry->d_subdirs)) {
+			this_parent = dentry;
+			goto repeat;
+		}
+
+		next = next->next;
+		spin_unlock(&dcache_lock);
+
+		DPRINTK("dentry %p %.*s",
+			dentry, (int)dentry->d_name.len, dentry->d_name.name);
+
+		dput(dentry);
+		spin_lock(&dcache_lock);
+	}
+
+	if (this_parent != sbi->root) {
+		struct dentry *dentry = this_parent;
+
+		next = this_parent->d_child.next;
+		this_parent = this_parent->d_parent;
+		spin_unlock(&dcache_lock);
+		DPRINTK("parent dentry %p %.*s",
+			dentry, (int)dentry->d_name.len, dentry->d_name.name);
+		dput(dentry);
+		spin_lock(&dcache_lock);
+		goto resume;
+	}
+	spin_unlock(&dcache_lock);
+
+	dput(sbi->root);
+	sbi->root = NULL;
+	shrink_dcache_sb(sbi->sb);
+
+	return;
+}
+
 static void autofs4_put_super(struct super_block *sb)
 {
 	struct autofs_sb_info *sbi = autofs4_sbi(sb);
@@ -85,6 +146,10 @@ static void autofs4_put_super(struct super_block *sb)
 	if ( !sbi->catatonic )
 		autofs4_catatonic_mode(sbi); /* Free wait queues, close pipe */
 
+	/* Clean up and release dangling references */
+	if (sbi)
+		autofs4_force_release(sbi);
+
 	kfree(sbi);
 
 	DPRINTK("shutting down");
@@ -199,6 +264,7 @@ int autofs4_fill_super(struct super_block *s, void *data, int silent)
 
 	s->s_fs_info = sbi;
 	sbi->magic = AUTOFS_SBI_MAGIC;
+	sbi->root = NULL;
 	sbi->catatonic = 0;
 	sbi->exp_timeout = 0;
 	sbi->oz_pgrp = process_group(current);
@@ -267,6 +333,13 @@ int autofs4_fill_super(struct super_block *s, void *data, int silent)
 	sbi->pipe = pipe;
 
 	/*
+	 * Take a reference to the root dentry so we get a chance to
+	 * clean up the dentry tree on umount.
+	 * See autofs4_force_release.
+	 */
+	sbi->root = dget(root);
+
+	/*
 	 * Success! Install the root dentry now to indicate completion.
 	 */
 	s->s_root = root;
diff --git a/fs/bio.c b/fs/bio.c
index ca8f7a850fe..1f2d4649b18 100644
--- a/fs/bio.c
+++ b/fs/bio.c
@@ -248,19 +248,16 @@ inline void __bio_clone(struct bio *bio, struct bio *bio_src)
 {
 	request_queue_t *q = bdev_get_queue(bio_src->bi_bdev);
 
-	memcpy(bio->bi_io_vec, bio_src->bi_io_vec, bio_src->bi_max_vecs * sizeof(struct bio_vec));
+	memcpy(bio->bi_io_vec, bio_src->bi_io_vec,
+		bio_src->bi_max_vecs * sizeof(struct bio_vec));
 
 	bio->bi_sector = bio_src->bi_sector;
 	bio->bi_bdev = bio_src->bi_bdev;
 	bio->bi_flags |= 1 << BIO_CLONED;
 	bio->bi_rw = bio_src->bi_rw;
-
-	/*
-	 * notes -- maybe just leave bi_idx alone. assume identical mapping
-	 * for the clone
-	 */
 	bio->bi_vcnt = bio_src->bi_vcnt;
 	bio->bi_size = bio_src->bi_size;
+	bio->bi_idx = bio_src->bi_idx;
 	bio_phys_segments(q, bio);
 	bio_hw_segments(q, bio);
 }
diff --git a/fs/dcache.c b/fs/dcache.c
index 3aa8a7e980d..a15a2e1f552 100644
--- a/fs/dcache.c
+++ b/fs/dcache.c
@@ -19,6 +19,7 @@
 #include <linux/string.h>
 #include <linux/mm.h>
 #include <linux/fs.h>
+#include <linux/fsnotify.h>
 #include <linux/slab.h>
 #include <linux/init.h>
 #include <linux/smp_lock.h>
@@ -101,6 +102,7 @@ static inline void dentry_iput(struct dentry * dentry)
 		list_del_init(&dentry->d_alias);
 		spin_unlock(&dentry->d_lock);
 		spin_unlock(&dcache_lock);
+		fsnotify_inoderemove(inode);
 		if (dentry->d_op && dentry->d_op->d_iput)
 			dentry->d_op->d_iput(dentry, inode);
 		else
@@ -1165,13 +1167,16 @@ out:
  
 void d_delete(struct dentry * dentry)
 {
+	int isdir = 0;
 	/*
 	 * Are we the only user?
 	 */
 	spin_lock(&dcache_lock);
 	spin_lock(&dentry->d_lock);
+	isdir = S_ISDIR(dentry->d_inode->i_mode);
 	if (atomic_read(&dentry->d_count) == 1) {
 		dentry_iput(dentry);
+		fsnotify_nameremove(dentry, isdir);
 		return;
 	}
 
@@ -1180,6 +1185,8 @@ void d_delete(struct dentry * dentry)
 
 	spin_unlock(&dentry->d_lock);
 	spin_unlock(&dcache_lock);
+
+	fsnotify_nameremove(dentry, isdir);
 }
 
 static void __d_rehash(struct dentry * entry, struct hlist_head *list)
diff --git a/fs/ext2/ialloc.c b/fs/ext2/ialloc.c
index 77e05914921..161f156d98c 100644
--- a/fs/ext2/ialloc.c
+++ b/fs/ext2/ialloc.c
@@ -612,6 +612,7 @@ got:
 	err = ext2_init_acl(inode, dir);
 	if (err) {
 		DQUOT_FREE_INODE(inode);
+		DQUOT_DROP(inode);
 		goto fail2;
 	}
 	mark_inode_dirty(inode);
diff --git a/fs/ext2/xattr.c b/fs/ext2/xattr.c
index 27982b500e8..0099462d427 100644
--- a/fs/ext2/xattr.c
+++ b/fs/ext2/xattr.c
@@ -823,7 +823,7 @@ cleanup:
 void
 ext2_xattr_put_super(struct super_block *sb)
 {
-	mb_cache_shrink(ext2_xattr_cache, sb->s_bdev);
+	mb_cache_shrink(sb->s_bdev);
 }
 
 
diff --git a/fs/ext2/xip.c b/fs/ext2/xip.c
index 0aa5ac159c0..ca7f0031238 100644
--- a/fs/ext2/xip.c
+++ b/fs/ext2/xip.c
@@ -36,7 +36,7 @@ __ext2_get_sector(struct inode *inode, sector_t offset, int create,
 	*result = tmp.b_blocknr;
 
 	/* did we get a sparse block (hole in the file)? */
-	if (!(*result)) {
+	if (!tmp.b_blocknr && !rc) {
 		BUG_ON(create);
 		rc = -ENODATA;
 	}
diff --git a/fs/ext3/ialloc.c b/fs/ext3/ialloc.c
index 1e6f3ea2871..6981bd014ed 100644
--- a/fs/ext3/ialloc.c
+++ b/fs/ext3/ialloc.c
@@ -604,12 +604,14 @@ got:
 	err = ext3_init_acl(handle, inode, dir);
 	if (err) {
 		DQUOT_FREE_INODE(inode);
+		DQUOT_DROP(inode);
 		goto fail2;
   	}
 	err = ext3_mark_inode_dirty(handle, inode);
 	if (err) {
 		ext3_std_error(sb, err);
 		DQUOT_FREE_INODE(inode);
+		DQUOT_DROP(inode);
 		goto fail2;
 	}
 
diff --git a/fs/ext3/xattr.c b/fs/ext3/xattr.c
index 3f9dfa643b1..269c7b92db9 100644
--- a/fs/ext3/xattr.c
+++ b/fs/ext3/xattr.c
@@ -1106,7 +1106,7 @@ cleanup:
 void
 ext3_xattr_put_super(struct super_block *sb)
 {
-	mb_cache_shrink(ext3_xattr_cache, sb->s_bdev);
+	mb_cache_shrink(sb->s_bdev);
 }
 
 /*
diff --git a/fs/fcntl.c b/fs/fcntl.c
index 286a9f8f3d4..6fbc9d8fcc3 100644
--- a/fs/fcntl.c
+++ b/fs/fcntl.c
@@ -288,7 +288,7 @@ static long do_fcntl(int fd, unsigned int cmd, unsigned long arg,
 		break;
 	case F_SETLK:
 	case F_SETLKW:
-		err = fcntl_setlk(filp, cmd, (struct flock __user *) arg);
+		err = fcntl_setlk(fd, filp, cmd, (struct flock __user *) arg);
 		break;
 	case F_GETOWN:
 		/*
@@ -376,7 +376,8 @@ asmlinkage long sys_fcntl64(unsigned int fd, unsigned int cmd, unsigned long arg
 			break;
 		case F_SETLK64:
 		case F_SETLKW64:
-			err = fcntl_setlk64(filp, cmd, (struct flock64 __user *) arg);
+			err = fcntl_setlk64(fd, filp, cmd,
+					(struct flock64 __user *) arg);
 			break;
 		default:
 			err = do_fcntl(fd, cmd, arg, filp);
diff --git a/fs/hfs/bnode.c b/fs/hfs/bnode.c
index 6ad1211f84e..a096c5a5666 100644
--- a/fs/hfs/bnode.c
+++ b/fs/hfs/bnode.c
@@ -480,6 +480,8 @@ void hfs_bnode_put(struct hfs_bnode *node)
 			return;
 		}
 		for (i = 0; i < tree->pages_per_bnode; i++) {
+			if (!node->page[i])
+				continue;
 			mark_page_accessed(node->page[i]);
 #if REF_PAGES
 			put_page(node->page[i]);
diff --git a/fs/hfs/extent.c b/fs/hfs/extent.c
index cbc8510ad22..5ea6b3d45ea 100644
--- a/fs/hfs/extent.c
+++ b/fs/hfs/extent.c
@@ -482,7 +482,8 @@ void hfs_file_truncate(struct inode *inode)
 		page_cache_release(page);
 		mark_inode_dirty(inode);
 		return;
-	}
+	} else if (inode->i_size == HFS_I(inode)->phys_size)
+		return;
 	size = inode->i_size + HFS_SB(sb)->alloc_blksz - 1;
 	blk_cnt = size / HFS_SB(sb)->alloc_blksz;
 	alloc_cnt = HFS_I(inode)->alloc_blocks;
diff --git a/fs/hfsplus/bnode.c b/fs/hfsplus/bnode.c
index 267872e84d7..8868d3b766f 100644
--- a/fs/hfsplus/bnode.c
+++ b/fs/hfsplus/bnode.c
@@ -643,6 +643,8 @@ void hfs_bnode_put(struct hfs_bnode *node)
 			return;
 		}
 		for (i = 0; i < tree->pages_per_bnode; i++) {
+			if (!node->page[i])
+				continue;
 			mark_page_accessed(node->page[i]);
 #if REF_PAGES
 			put_page(node->page[i]);
diff --git a/fs/hfsplus/extents.c b/fs/hfsplus/extents.c
index 376498cc64f..e7235ca79a9 100644
--- a/fs/hfsplus/extents.c
+++ b/fs/hfsplus/extents.c
@@ -461,7 +461,9 @@ void hfsplus_file_truncate(struct inode *inode)
 		page_cache_release(page);
 		mark_inode_dirty(inode);
 		return;
-	}
+	} else if (inode->i_size == HFSPLUS_I(inode).phys_size)
+		return;
+
 	blk_cnt = (inode->i_size + HFSPLUS_SB(sb).alloc_blksz - 1) >> HFSPLUS_SB(sb).alloc_blksz_shift;
 	alloc_cnt = HFSPLUS_I(inode).alloc_blocks;
 	if (blk_cnt == alloc_cnt)
diff --git a/fs/hostfs/hostfs.h b/fs/hostfs/hostfs.h
index c1516d013bf..67bca0d4a33 100644
--- a/fs/hostfs/hostfs.h
+++ b/fs/hostfs/hostfs.h
@@ -69,6 +69,7 @@ extern int read_file(int fd, unsigned long long *offset, char *buf, int len);
 extern int write_file(int fd, unsigned long long *offset, const char *buf,
 		      int len);
 extern int lseek_file(int fd, long long offset, int whence);
+extern int fsync_file(int fd, int datasync);
 extern int file_create(char *name, int ur, int uw, int ux, int gr,
 		       int gw, int gx, int or, int ow, int ox);
 extern int set_attr(const char *file, struct hostfs_iattr *attrs);
diff --git a/fs/hostfs/hostfs_kern.c b/fs/hostfs/hostfs_kern.c
index 88e68caa378..b2d18200a00 100644
--- a/fs/hostfs/hostfs_kern.c
+++ b/fs/hostfs/hostfs_kern.c
@@ -382,7 +382,7 @@ int hostfs_file_open(struct inode *ino, struct file *file)
 
 int hostfs_fsync(struct file *file, struct dentry *dentry, int datasync)
 {
-	return(0);
+	return fsync_file(HOSTFS_I(dentry->d_inode)->fd, datasync);
 }
 
 static struct file_operations hostfs_file_fops = {
diff --git a/fs/hostfs/hostfs_user.c b/fs/hostfs/hostfs_user.c
index 4796e8490f7..b97809deba6 100644
--- a/fs/hostfs/hostfs_user.c
+++ b/fs/hostfs/hostfs_user.c
@@ -153,10 +153,24 @@ int lseek_file(int fd, long long offset, int whence)
 	int ret;
 
 	ret = lseek64(fd, offset, whence);
-	if(ret < 0) return(-errno);
+	if(ret < 0)
+		return(-errno);
 	return(0);
 }
 
+int fsync_file(int fd, int datasync)
+{
+	int ret;
+	if (datasync)
+		ret = fdatasync(fd);
+	else
+		ret = fsync(fd);
+
+	if (ret < 0)
+		return -errno;
+	return 0;
+}
+
 void close_file(void *stream)
 {
 	close(*((int *) stream));
diff --git a/fs/inotify.c b/fs/inotify.c
index a8a714e4814..27ebcac5e07 100644
--- a/fs/inotify.c
+++ b/fs/inotify.c
@@ -90,6 +90,7 @@ struct inotify_device {
 	unsigned int		queue_size;	/* size of the queue (bytes) */
 	unsigned int		event_count;	/* number of pending events */
 	unsigned int		max_events;	/* maximum number of events */
+	u32			last_wd;	/* the last wd allocated */
 };
 
 /*
@@ -352,7 +353,7 @@ static int inotify_dev_get_wd(struct inotify_device *dev,
 	do {
 		if (unlikely(!idr_pre_get(&dev->idr, GFP_KERNEL)))
 			return -ENOSPC;
-		ret = idr_get_new(&dev->idr, watch, &watch->wd);
+		ret = idr_get_new_above(&dev->idr, watch, dev->last_wd, &watch->wd);
 	} while (ret == -EAGAIN);
 
 	return ret;
@@ -401,6 +402,7 @@ static struct inotify_watch *create_watch(struct inotify_device *dev,
 		return ERR_PTR(ret);
 	}
 
+	dev->last_wd = ret;
 	watch->mask = mask;
 	atomic_set(&watch->count, 0);
 	INIT_LIST_HEAD(&watch->d_list);
@@ -899,6 +901,7 @@ asmlinkage long sys_inotify_init(void)
 	dev->queue_size = 0;
 	dev->max_events = inotify_max_queued_events;
 	dev->user = user;
+	dev->last_wd = 0;
 	atomic_set(&dev->count, 0);
 
 	get_inotify_dev(dev);
diff --git a/fs/isofs/compress.c b/fs/isofs/compress.c
index 34a44e45168..4917315db73 100644
--- a/fs/isofs/compress.c
+++ b/fs/isofs/compress.c
@@ -129,8 +129,14 @@ static int zisofs_readpage(struct file *file, struct page *page)
 	cend = le32_to_cpu(*(__le32 *)(bh->b_data + (blockendptr & bufmask)));
 	brelse(bh);
 
+	if (cstart > cend)
+		goto eio;
+		
 	csize = cend-cstart;
 
+	if (csize > deflateBound(1UL << zisofs_block_shift))
+		goto eio;
+
 	/* Now page[] contains an array of pages, any of which can be NULL,
 	   and the locks on which we hold.  We should now read the data and
 	   release the pages.  If the pages are NULL the decompressed data
diff --git a/fs/jffs/intrep.c b/fs/jffs/intrep.c
index fc589ddd076..456d7e6e29c 100644
--- a/fs/jffs/intrep.c
+++ b/fs/jffs/intrep.c
@@ -3397,6 +3397,9 @@ jffs_garbage_collect_thread(void *ptr)
 			siginfo_t info;
 			unsigned long signr = 0;
 
+			if (try_to_freeze())
+				continue;
+
 			spin_lock_irq(&current->sighand->siglock);
 			signr = dequeue_signal(current, &current->blocked, &info);
 			spin_unlock_irq(&current->sighand->siglock);
diff --git a/fs/jfs/jfs_dmap.c b/fs/jfs/jfs_dmap.c
index 0732f206ca6..c739626f5bf 100644
--- a/fs/jfs/jfs_dmap.c
+++ b/fs/jfs/jfs_dmap.c
@@ -75,7 +75,7 @@ static void dbAllocBits(struct bmap * bmp, struct dmap * dp, s64 blkno,
 			int nblocks);
 static void dbSplit(dmtree_t * tp, int leafno, int splitsz, int newval);
 static void dbBackSplit(dmtree_t * tp, int leafno);
-static void dbJoin(dmtree_t * tp, int leafno, int newval);
+static int dbJoin(dmtree_t * tp, int leafno, int newval);
 static void dbAdjTree(dmtree_t * tp, int leafno, int newval);
 static int dbAdjCtl(struct bmap * bmp, s64 blkno, int newval, int alloc,
 		    int level);
@@ -98,8 +98,8 @@ static int dbExtend(struct inode *ip, s64 blkno, s64 nblocks, s64 addnblocks);
 static int dbFindBits(u32 word, int l2nb);
 static int dbFindCtl(struct bmap * bmp, int l2nb, int level, s64 * blkno);
 static int dbFindLeaf(dmtree_t * tp, int l2nb, int *leafidx);
-static void dbFreeBits(struct bmap * bmp, struct dmap * dp, s64 blkno,
-		       int nblocks);
+static int dbFreeBits(struct bmap * bmp, struct dmap * dp, s64 blkno,
+		      int nblocks);
 static int dbFreeDmap(struct bmap * bmp, struct dmap * dp, s64 blkno,
 		      int nblocks);
 static int dbMaxBud(u8 * cp);
@@ -378,6 +378,7 @@ int dbFree(struct inode *ip, s64 blkno, s64 nblocks)
 
 		/* free the blocks. */
 		if ((rc = dbFreeDmap(bmp, dp, blkno, nb))) {
+			jfs_error(ip->i_sb, "dbFree: error in block map\n");
 			release_metapage(mp);
 			IREAD_UNLOCK(ipbmap);
 			return (rc);
@@ -2020,7 +2021,7 @@ static int dbFreeDmap(struct bmap * bmp, struct dmap * dp, s64 blkno,
 		      int nblocks)
 {
 	s8 oldroot;
-	int rc, word;
+	int rc = 0, word;
 
 	/* save the current value of the root (i.e. maximum free string)
 	 * of the dmap tree.
@@ -2028,11 +2029,11 @@ static int dbFreeDmap(struct bmap * bmp, struct dmap * dp, s64 blkno,
 	oldroot = dp->tree.stree[ROOT];
 
 	/* free the specified (blocks) bits */
-	dbFreeBits(bmp, dp, blkno, nblocks);
+	rc = dbFreeBits(bmp, dp, blkno, nblocks);
 
-	/* if the root has not changed, done. */
-	if (dp->tree.stree[ROOT] == oldroot)
-		return (0);
+	/* if error or the root has not changed, done. */
+	if (rc || (dp->tree.stree[ROOT] == oldroot))
+		return (rc);
 
 	/* root changed. bubble the change up to the dmap control pages.
 	 * if the adjustment of the upper level control pages fails,
@@ -2221,15 +2222,16 @@ static void dbAllocBits(struct bmap * bmp, struct dmap * dp, s64 blkno,
  *      blkno	-  starting block number of the bits to be freed.
  *      nblocks	-  number of bits to be freed.
  *
- * RETURN VALUES: none
+ * RETURN VALUES: 0 for success
  *
  * serialization: IREAD_LOCK(ipbmap) or IWRITE_LOCK(ipbmap) held on entry/exit;
  */
-static void dbFreeBits(struct bmap * bmp, struct dmap * dp, s64 blkno,
+static int dbFreeBits(struct bmap * bmp, struct dmap * dp, s64 blkno,
 		       int nblocks)
 {
 	int dbitno, word, rembits, nb, nwords, wbitno, nw, agno;
 	dmtree_t *tp = (dmtree_t *) & dp->tree;
+	int rc = 0;
 	int size;
 
 	/* determine the bit number and word within the dmap of the
@@ -2278,8 +2280,10 @@ static void dbFreeBits(struct bmap * bmp, struct dmap * dp, s64 blkno,
 
 			/* update the leaf for this dmap word.
 			 */
-			dbJoin(tp, word,
-			       dbMaxBud((u8 *) & dp->wmap[word]));
+			rc = dbJoin(tp, word,
+				    dbMaxBud((u8 *) & dp->wmap[word]));
+			if (rc)
+				return rc;
 
 			word += 1;
 		} else {
@@ -2310,7 +2314,9 @@ static void dbFreeBits(struct bmap * bmp, struct dmap * dp, s64 blkno,
 
 				/* update the leaf.
 				 */
-				dbJoin(tp, word, size);
+				rc = dbJoin(tp, word, size);
+				if (rc)
+					return rc;
 
 				/* get the number of dmap words handled.
 				 */
@@ -2357,6 +2363,8 @@ static void dbFreeBits(struct bmap * bmp, struct dmap * dp, s64 blkno,
 	}
 
 	BMAP_UNLOCK(bmp);
+
+	return 0;
 }
 
 
@@ -2464,7 +2472,9 @@ dbAdjCtl(struct bmap * bmp, s64 blkno, int newval, int alloc, int level)
 		}
 		dbSplit((dmtree_t *) dcp, leafno, dcp->budmin, newval);
 	} else {
-		dbJoin((dmtree_t *) dcp, leafno, newval);
+		rc = dbJoin((dmtree_t *) dcp, leafno, newval);
+		if (rc)
+			return rc;
 	}
 
 	/* check if the root of the current dmap control page changed due
@@ -2689,7 +2699,7 @@ static void dbBackSplit(dmtree_t * tp, int leafno)
  *
  * RETURN VALUES: none
  */
-static void dbJoin(dmtree_t * tp, int leafno, int newval)
+static int dbJoin(dmtree_t * tp, int leafno, int newval)
 {
 	int budsz, buddy;
 	s8 *leaf;
@@ -2729,7 +2739,9 @@ static void dbJoin(dmtree_t * tp, int leafno, int newval)
 			if (newval > leaf[buddy])
 				break;
 
-			assert(newval == leaf[buddy]);
+			/* It shouldn't be less */
+			if (newval < leaf[buddy])
+				return -EIO;
 
 			/* check which (leafno or buddy) is the left buddy.
 			 * the left buddy gets to claim the blocks resulting
@@ -2761,6 +2773,8 @@ static void dbJoin(dmtree_t * tp, int leafno, int newval)
 	/* update the leaf value.
 	 */
 	dbAdjTree(tp, leafno, newval);
+
+	return 0;
 }
 
 
diff --git a/fs/jfs/jfs_dtree.c b/fs/jfs/jfs_dtree.c
index 73b5fc7eda8..404f33eae50 100644
--- a/fs/jfs/jfs_dtree.c
+++ b/fs/jfs/jfs_dtree.c
@@ -381,9 +381,12 @@ static u32 add_index(tid_t tid, struct inode *ip, s64 bn, int slot)
 		 * It's time to move the inline table to an external
 		 * page and begin to build the xtree
 		 */
-		if (DQUOT_ALLOC_BLOCK(ip, sbi->nbperpage) ||
-		    dbAlloc(ip, 0, sbi->nbperpage, &xaddr))
-			goto clean_up;	/* No space */
+		if (DQUOT_ALLOC_BLOCK(ip, sbi->nbperpage))
+			goto clean_up;
+		if (dbAlloc(ip, 0, sbi->nbperpage, &xaddr)) {
+			DQUOT_FREE_BLOCK(ip, sbi->nbperpage);
+			goto clean_up;
+		}
 
 		/*
 		 * Save the table, we're going to overwrite it with the
@@ -397,13 +400,15 @@ static u32 add_index(tid_t tid, struct inode *ip, s64 bn, int slot)
 		xtInitRoot(tid, ip);
 
 		/*
-		 * Allocate the first block & add it to the xtree
+		 * Add the first block to the xtree
 		 */
 		if (xtInsert(tid, ip, 0, 0, sbi->nbperpage, &xaddr, 0)) {
 			/* This really shouldn't fail */
 			jfs_warn("add_index: xtInsert failed!");
 			memcpy(&jfs_ip->i_dirtable, temp_table,
 			       sizeof (temp_table));
+			dbFree(ip, xaddr, sbi->nbperpage);
+			DQUOT_FREE_BLOCK(ip, sbi->nbperpage);
 			goto clean_up;
 		}
 		ip->i_size = PSIZE;
diff --git a/fs/jfs/jfs_logmgr.c b/fs/jfs/jfs_logmgr.c
index 79d07624bfe..22815e88e7c 100644
--- a/fs/jfs/jfs_logmgr.c
+++ b/fs/jfs/jfs_logmgr.c
@@ -1030,7 +1030,8 @@ static int lmLogSync(struct jfs_log * log, int nosyncwait)
 	 * starting until all current transactions are completed
 	 * by setting syncbarrier flag.
 	 */
-	if (written > LOGSYNC_BARRIER(logsize) && logsize > 32 * LOGPSIZE) {
+	if (!test_bit(log_SYNCBARRIER, &log->flag) &&
+	    (written > LOGSYNC_BARRIER(logsize)) && log->active) {
 		set_bit(log_SYNCBARRIER, &log->flag);
 		jfs_info("log barrier on: lsn=0x%x syncpt=0x%x", lsn,
 			 log->syncpt);
diff --git a/fs/jfs/jfs_metapage.c b/fs/jfs/jfs_metapage.c
index 6c5485d16c3..13d7e3f1feb 100644
--- a/fs/jfs/jfs_metapage.c
+++ b/fs/jfs/jfs_metapage.c
@@ -561,7 +561,6 @@ static int metapage_releasepage(struct page *page, int gfp_mask)
 			dump_mem("page", page, sizeof(struct page));
 			dump_stack();
 		}
-		WARN_ON(mp->lsn);
 		if (mp->lsn)
 			remove_from_logsync(mp);
 		remove_metapage(page, mp);
@@ -641,7 +640,7 @@ struct metapage *__get_metapage(struct inode *inode, unsigned long lblock,
 	} else {
 		page = read_cache_page(mapping, page_index,
 			    (filler_t *)mapping->a_ops->readpage, NULL);
-		if (IS_ERR(page)) {
+		if (IS_ERR(page) || !PageUptodate(page)) {
 			jfs_err("read_cache_page failed!");
 			return NULL;
 		}
@@ -783,14 +782,6 @@ void release_metapage(struct metapage * mp)
 	if (test_bit(META_discard, &mp->flag) && !mp->count) {
 		clear_page_dirty(page);
 		ClearPageUptodate(page);
-#ifdef _NOT_YET
-		if (page->mapping) {
-		/* Remove from page cache and page cache reference */
-			remove_from_page_cache(page);
-			page_cache_release(page);
-			metapage_releasepage(page, 0);
-		}
-#endif
 	}
 #else
 	/* Try to keep metapages from using up too much memory */
diff --git a/fs/locks.c b/fs/locks.c
index 29fa5da6c11..11956b6179f 100644
--- a/fs/locks.c
+++ b/fs/locks.c
@@ -1591,7 +1591,8 @@ out:
 /* Apply the lock described by l to an open file descriptor.
  * This implements both the F_SETLK and F_SETLKW commands of fcntl().
  */
-int fcntl_setlk(struct file *filp, unsigned int cmd, struct flock __user *l)
+int fcntl_setlk(unsigned int fd, struct file *filp, unsigned int cmd,
+		struct flock __user *l)
 {
 	struct file_lock *file_lock = locks_alloc_lock();
 	struct flock flock;
@@ -1620,6 +1621,7 @@ int fcntl_setlk(struct file *filp, unsigned int cmd, struct flock __user *l)
 		goto out;
 	}
 
+again:
 	error = flock_to_posix_lock(filp, file_lock, &flock);
 	if (error)
 		goto out;
@@ -1648,25 +1650,33 @@ int fcntl_setlk(struct file *filp, unsigned int cmd, struct flock __user *l)
 	if (error)
 		goto out;
 
-	if (filp->f_op && filp->f_op->lock != NULL) {
+	if (filp->f_op && filp->f_op->lock != NULL)
 		error = filp->f_op->lock(filp, cmd, file_lock);
-		goto out;
-	}
+	else {
+		for (;;) {
+			error = __posix_lock_file(inode, file_lock);
+			if ((error != -EAGAIN) || (cmd == F_SETLK))
+				break;
+			error = wait_event_interruptible(file_lock->fl_wait,
+					!file_lock->fl_next);
+			if (!error)
+				continue;
 
-	for (;;) {
-		error = __posix_lock_file(inode, file_lock);
-		if ((error != -EAGAIN) || (cmd == F_SETLK))
+			locks_delete_block(file_lock);
 			break;
-		error = wait_event_interruptible(file_lock->fl_wait,
-				!file_lock->fl_next);
-		if (!error)
-			continue;
+		}
+	}
 
-		locks_delete_block(file_lock);
-		break;
+	/*
+	 * Attempt to detect a close/fcntl race and recover by
+	 * releasing the lock that was just acquired.
+	 */
+	if (!error && fcheck(fd) != filp && flock.l_type != F_UNLCK) {
+		flock.l_type = F_UNLCK;
+		goto again;
 	}
 
- out:
+out:
 	locks_free_lock(file_lock);
 	return error;
 }
@@ -1724,7 +1734,8 @@ out:
 /* Apply the lock described by l to an open file descriptor.
  * This implements both the F_SETLK and F_SETLKW commands of fcntl().
  */
-int fcntl_setlk64(struct file *filp, unsigned int cmd, struct flock64 __user *l)
+int fcntl_setlk64(unsigned int fd, struct file *filp, unsigned int cmd,
+		struct flock64 __user *l)
 {
 	struct file_lock *file_lock = locks_alloc_lock();
 	struct flock64 flock;
@@ -1753,6 +1764,7 @@ int fcntl_setlk64(struct file *filp, unsigned int cmd, struct flock64 __user *l)
 		goto out;
 	}
 
+again:
 	error = flock64_to_posix_lock(filp, file_lock, &flock);
 	if (error)
 		goto out;
@@ -1781,22 +1793,30 @@ int fcntl_setlk64(struct file *filp, unsigned int cmd, struct flock64 __user *l)
 	if (error)
 		goto out;
 
-	if (filp->f_op && filp->f_op->lock != NULL) {
+	if (filp->f_op && filp->f_op->lock != NULL)
 		error = filp->f_op->lock(filp, cmd, file_lock);
-		goto out;
-	}
+	else {
+		for (;;) {
+			error = __posix_lock_file(inode, file_lock);
+			if ((error != -EAGAIN) || (cmd == F_SETLK64))
+				break;
+			error = wait_event_interruptible(file_lock->fl_wait,
+					!file_lock->fl_next);
+			if (!error)
+				continue;
 
-	for (;;) {
-		error = __posix_lock_file(inode, file_lock);
-		if ((error != -EAGAIN) || (cmd == F_SETLK64))
+			locks_delete_block(file_lock);
 			break;
-		error = wait_event_interruptible(file_lock->fl_wait,
-				!file_lock->fl_next);
-		if (!error)
-			continue;
+		}
+	}
 
-		locks_delete_block(file_lock);
-		break;
+	/*
+	 * Attempt to detect a close/fcntl race and recover by
+	 * releasing the lock that was just acquired.
+	 */
+	if (!error && fcheck(fd) != filp && flock.l_type != F_UNLCK) {
+		flock.l_type = F_UNLCK;
+		goto again;
 	}
 
 out:
@@ -1888,12 +1908,7 @@ void locks_remove_flock(struct file *filp)
 
 	while ((fl = *before) != NULL) {
 		if (fl->fl_file == filp) {
-			/*
-			 * We might have a POSIX lock that was created at the same time
-			 * the filp was closed for the last time. Just remove that too,
-			 * regardless of ownership, since nobody can own it.
-			 */
-			if (IS_FLOCK(fl) || IS_POSIX(fl)) {
+			if (IS_FLOCK(fl)) {
 				locks_delete_lock(before);
 				continue;
 			}
diff --git a/fs/mbcache.c b/fs/mbcache.c
index c7170b9221a..b002a088857 100644
--- a/fs/mbcache.c
+++ b/fs/mbcache.c
@@ -316,11 +316,10 @@ fail:
  * currently in use cannot be freed, and thus remain in the cache. All others
  * are freed.
  *
- * @cache: which cache to shrink
  * @bdev: which device's cache entries to shrink
  */
 void
-mb_cache_shrink(struct mb_cache *cache, struct block_device *bdev)
+mb_cache_shrink(struct block_device *bdev)
 {
 	LIST_HEAD(free_list);
 	struct list_head *l, *ltmp;
diff --git a/fs/namei.c b/fs/namei.c
index e252b12d39b..264e232addd 100644
--- a/fs/namei.c
+++ b/fs/namei.c
@@ -1801,7 +1801,6 @@ int vfs_rmdir(struct inode *dir, struct dentry *dentry)
 	}
 	up(&dentry->d_inode->i_sem);
 	if (!error) {
-		fsnotify_rmdir(dentry, dentry->d_inode, dir);
 		d_delete(dentry);
 	}
 	dput(dentry);
@@ -1874,7 +1873,6 @@ int vfs_unlink(struct inode *dir, struct dentry *dentry)
 
 	/* We don't d_delete() NFS sillyrenamed files--they still exist. */
 	if (!error && !(dentry->d_flags & DCACHE_NFSFS_RENAMED)) {
-		fsnotify_unlink(dentry, dir);
 		d_delete(dentry);
 	}
 
@@ -2218,7 +2216,7 @@ int vfs_rename(struct inode *old_dir, struct dentry *old_dentry,
 		error = vfs_rename_other(old_dir,old_dentry,new_dir,new_dentry);
 	if (!error) {
 		const char *new_name = old_dentry->d_name.name;
-		fsnotify_move(old_dir, new_dir, old_name, new_name, is_dir);
+		fsnotify_move(old_dir, new_dir, old_name, new_name, is_dir, new_dentry->d_inode);
 	}
 	fsnotify_oldname_free(old_name);
 
diff --git a/fs/namespace.c b/fs/namespace.c
index 587eb0d707e..79bd8a46e1e 100644
--- a/fs/namespace.c
+++ b/fs/namespace.c
@@ -160,7 +160,7 @@ clone_mnt(struct vfsmount *old, struct dentry *root)
 		mnt->mnt_root = dget(root);
 		mnt->mnt_mountpoint = mnt->mnt_root;
 		mnt->mnt_parent = mnt;
-		mnt->mnt_namespace = old->mnt_namespace;
+		mnt->mnt_namespace = current->namespace;
 
 		/* stick the duplicate mount on the same expiry list
 		 * as the original if that was on one */
diff --git a/fs/ntfs/sysctl.h b/fs/ntfs/sysctl.h
index df749cc0aac..c8064cae8f1 100644
--- a/fs/ntfs/sysctl.h
+++ b/fs/ntfs/sysctl.h
@@ -26,7 +26,7 @@
 
 #include <linux/config.h>
 
-#if (DEBUG && CONFIG_SYSCTL)
+#if defined(DEBUG) && defined(CONFIG_SYSCTL)
 
 extern int ntfs_sysctl(int add);
 
diff --git a/fs/reiserfs/inode.c b/fs/reiserfs/inode.c
index 1aaf2c7d44e..d9f614a5773 100644
--- a/fs/reiserfs/inode.c
+++ b/fs/reiserfs/inode.c
@@ -1980,7 +1980,17 @@ int reiserfs_new_inode(struct reiserfs_transaction_handle *th,
       out_inserted_sd:
 	inode->i_nlink = 0;
 	th->t_trans_id = 0;	/* so the caller can't use this handle later */
-	iput(inode);
+
+	/* If we were inheriting an ACL, we need to release the lock so that
+	 * iput doesn't deadlock in reiserfs_delete_xattrs. The locking
+	 * code really needs to be reworked, but this will take care of it
+	 * for now. -jeffm */
+	if (REISERFS_I(dir)->i_acl_default) {
+		reiserfs_write_unlock_xattrs(dir->i_sb);
+		iput(inode);
+		reiserfs_write_lock_xattrs(dir->i_sb);
+	} else
+		iput(inode);
 	return err;
 }
 
diff --git a/fs/reiserfs/journal.c b/fs/reiserfs/journal.c
index c66c27ec410..ca7989b04be 100644
--- a/fs/reiserfs/journal.c
+++ b/fs/reiserfs/journal.c
@@ -556,14 +556,14 @@ static inline void insert_journal_hash(struct reiserfs_journal_cnode **table,
 }
 
 /* lock the current transaction */
-inline static void lock_journal(struct super_block *p_s_sb)
+static inline void lock_journal(struct super_block *p_s_sb)
 {
 	PROC_INFO_INC(p_s_sb, journal.lock_journal);
 	down(&SB_JOURNAL(p_s_sb)->j_lock);
 }
 
 /* unlock the current transaction */
-inline static void unlock_journal(struct super_block *p_s_sb)
+static inline void unlock_journal(struct super_block *p_s_sb)
 {
 	up(&SB_JOURNAL(p_s_sb)->j_lock);
 }
diff --git a/fs/reiserfs/xattr.c b/fs/reiserfs/xattr.c
index e386d3db305..87ac9dc8b38 100644
--- a/fs/reiserfs/xattr.c
+++ b/fs/reiserfs/xattr.c
@@ -39,7 +39,6 @@
 #include <linux/xattr.h>
 #include <linux/reiserfs_xattr.h>
 #include <linux/reiserfs_acl.h>
-#include <linux/mbcache.h>
 #include <asm/uaccess.h>
 #include <asm/checksum.h>
 #include <linux/smp_lock.h>
diff --git a/fs/sysfs/file.c b/fs/sysfs/file.c
index 335288b9be0..4013d7905e8 100644
--- a/fs/sysfs/file.c
+++ b/fs/sysfs/file.c
@@ -437,8 +437,8 @@ int sysfs_chmod_file(struct kobject *kobj, struct attribute *attr, mode_t mode)
 {
 	struct dentry *dir = kobj->dentry;
 	struct dentry *victim;
-	struct sysfs_dirent *sd;
-	umode_t umode = (mode & S_IALLUGO) | S_IFREG;
+	struct inode * inode;
+	struct iattr newattrs;
 	int res = -ENOENT;
 
 	down(&dir->d_inode->i_sem);
@@ -446,13 +446,15 @@ int sysfs_chmod_file(struct kobject *kobj, struct attribute *attr, mode_t mode)
 	if (!IS_ERR(victim)) {
 		if (victim->d_inode &&
 		    (victim->d_parent->d_inode == dir->d_inode)) {
-			sd = victim->d_fsdata;
-			attr->mode = mode;
-			sd->s_mode = umode;
-			victim->d_inode->i_mode = umode;
-			dput(victim);
-			res = 0;
+			inode = victim->d_inode;
+			down(&inode->i_sem);
+			newattrs.ia_mode = (mode & S_IALLUGO) |
+						(inode->i_mode & ~S_IALLUGO);
+			newattrs.ia_valid = ATTR_MODE | ATTR_CTIME;
+			res = notify_change(victim, &newattrs);
+			up(&inode->i_sem);
 		}
+		dput(victim);
 	}
 	up(&dir->d_inode->i_sem);
 
diff --git a/fs/sysfs/inode.c b/fs/sysfs/inode.c
index 8de13bafaa7..d727dc96063 100644
--- a/fs/sysfs/inode.c
+++ b/fs/sysfs/inode.c
@@ -85,7 +85,7 @@ int sysfs_setattr(struct dentry * dentry, struct iattr * iattr)
 
 		if (!in_group_p(inode->i_gid) && !capable(CAP_FSETID))
 			mode &= ~S_ISGID;
-		sd_iattr->ia_mode = mode;
+		sd_iattr->ia_mode = sd->s_mode = mode;
 	}
 
 	return error;
diff --git a/include/acpi/acpi_drivers.h b/include/acpi/acpi_drivers.h
index caeaa71a566..579fe191b7e 100644
--- a/include/acpi/acpi_drivers.h
+++ b/include/acpi/acpi_drivers.h
@@ -56,8 +56,9 @@
 /* ACPI PCI Interrupt Link (pci_link.c) */
 
 int acpi_irq_penalty_init (void);
-int acpi_pci_link_get_irq (acpi_handle handle, int index, int *edge_level,
+int acpi_pci_link_allocate_irq (acpi_handle handle, int index, int *edge_level,
 	int *active_high_low, char **name);
+int acpi_pci_link_free_irq(acpi_handle handle);
 
 /* ACPI PCI Interrupt Routing (pci_irq.c) */
 
diff --git a/include/asm-alpha/pci.h b/include/asm-alpha/pci.h
index 28957697e59..f681e675b82 100644
--- a/include/asm-alpha/pci.h
+++ b/include/asm-alpha/pci.h
@@ -251,6 +251,9 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 extern void pcibios_resource_to_bus(struct pci_dev *, struct pci_bus_region *,
 				    struct resource *);
 
+extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+				    struct pci_bus_region *region);
+
 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
 
 static inline int pci_proc_domain(struct pci_bus *bus)
diff --git a/include/asm-alpha/unistd.h b/include/asm-alpha/unistd.h
index 535bc425f24..ef25b658511 100644
--- a/include/asm-alpha/unistd.h
+++ b/include/asm-alpha/unistd.h
@@ -377,8 +377,13 @@
 #define __NR_add_key			439
 #define __NR_request_key		440
 #define __NR_keyctl			441
+#define __NR_ioprio_set			442
+#define __NR_ioprio_get			443
+#define __NR_inotify_init		444
+#define __NR_inotify_add_watch		445
+#define __NR_inotify_rm_watch		446
 
-#define NR_SYSCALLS			442
+#define NR_SYSCALLS			447
 
 #if defined(__GNUC__)
 
diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h
index c1adc6b3e86..aad7aad026b 100644
--- a/include/asm-arm/bitops.h
+++ b/include/asm-arm/bitops.h
@@ -229,6 +229,7 @@ extern int _find_next_zero_bit_be(const void * p, int size, int offset);
 extern int _find_first_bit_be(const unsigned long *p, unsigned size);
 extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
 
+#ifndef CONFIG_SMP
 /*
  * The __* form of bitops are non-atomic and may be reordered.
  */
@@ -241,6 +242,10 @@ extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
 	(__builtin_constant_p(nr) ?		\
 	 ____atomic_##name(nr, p) :		\
 	 _##name##_be(nr,p))
+#else
+#define ATOMIC_BITOP_LE(name,nr,p)	_##name##_le(nr,p)
+#define ATOMIC_BITOP_BE(name,nr,p)	_##name##_be(nr,p)
+#endif
 
 #define NONATOMIC_BITOP(name,nr,p)		\
 	(____nonatomic_##name(nr, p))
diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h
index b28f1c95dd6..38ea5899a58 100644
--- a/include/asm-arm/pci.h
+++ b/include/asm-arm/pci.h
@@ -60,6 +60,10 @@ extern void
 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 			 struct resource *res);
 
+extern void
+pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+			struct pci_bus_region *region);
+
 static inline void pcibios_add_platform_entries(struct pci_dev *dev)
 {
 }
diff --git a/include/asm-cris/arch-v10/atomic.h b/include/asm-cris/arch-v10/atomic.h
new file mode 100644
index 00000000000..6ef5e7d0902
--- /dev/null
+++ b/include/asm-cris/arch-v10/atomic.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_CRIS_ARCH_ATOMIC__
+#define __ASM_CRIS_ARCH_ATOMIC__
+
+#define cris_atomic_save(addr, flags) local_irq_save(flags);
+#define cris_atomic_restore(addr, flags) local_irq_restore(flags);
+
+#endif
diff --git a/include/asm-cris/arch-v10/bitops.h b/include/asm-cris/arch-v10/bitops.h
index 21b7ae8c9bb..b73f5396e5a 100644
--- a/include/asm-cris/arch-v10/bitops.h
+++ b/include/asm-cris/arch-v10/bitops.h
@@ -51,7 +51,7 @@ extern inline unsigned long ffz(unsigned long w)
  *
  * Undefined if no bit exists, so code should check against 0 first.
  */
-extern __inline__ unsigned long __ffs(unsigned long word)
+extern inline unsigned long __ffs(unsigned long word)
 {
 	return cris_swapnwbrlz(~word);
 }
diff --git a/include/asm-cris/arch-v10/dma.h b/include/asm-cris/arch-v10/dma.h
index 9e078b9bc93..ecb9dba6fa4 100644
--- a/include/asm-cris/arch-v10/dma.h
+++ b/include/asm-cris/arch-v10/dma.h
@@ -44,3 +44,31 @@
 #define USB_RX_DMA_NBR 9
 
 #endif
+
+enum dma_owner
+{
+  dma_eth,
+  dma_ser0,
+  dma_ser1, /* Async and sync */
+  dma_ser2,
+  dma_ser3, /* Async and sync */
+  dma_ata,
+  dma_par0,
+  dma_par1,
+  dma_ext0,
+  dma_ext1,
+  dma_int6,
+  dma_int7,
+  dma_usb,
+  dma_scsi0,
+  dma_scsi1
+};
+
+/* Masks used by cris_request_dma options: */
+#define DMA_VERBOSE_ON_ERROR    (1<<0)
+#define DMA_PANIC_ON_ERROR     ((1<<1)|DMA_VERBOSE_ON_ERROR)
+
+int cris_request_dma(unsigned int dmanr, const char * device_id,
+                     unsigned options, enum dma_owner owner);
+
+void cris_free_dma(unsigned int dmanr, const char * device_id);
diff --git a/include/asm-cris/arch-v10/elf.h b/include/asm-cris/arch-v10/elf.h
index 2a2201ca538..1c38ee728b1 100644
--- a/include/asm-cris/arch-v10/elf.h
+++ b/include/asm-cris/arch-v10/elf.h
@@ -1,6 +1,16 @@
 #ifndef __ASMCRIS_ARCH_ELF_H
 #define __ASMCRIS_ARCH_ELF_H
 
+#define ELF_MACH EF_CRIS_VARIANT_ANY_V0_V10
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x)			\
+ ((x)->e_machine == EM_CRIS			\
+  && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_ANY_V0_V10	\
+      || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32))))
+
 /*
  * ELF register definitions..
  */
diff --git a/include/asm-cris/arch-v10/ide.h b/include/asm-cris/arch-v10/ide.h
new file mode 100644
index 00000000000..8cf2d7cb22a
--- /dev/null
+++ b/include/asm-cris/arch-v10/ide.h
@@ -0,0 +1,99 @@
+/*
+ *  linux/include/asm-cris/ide.h
+ *
+ *  Copyright (C) 2000, 2001, 2002  Axis Communications AB
+ *
+ *  Authors:    Bjorn Wesen
+ *
+ */
+
+/*
+ *  This file contains the ETRAX 100LX specific IDE code.
+ */
+
+#ifndef __ASMCRIS_IDE_H
+#define __ASMCRIS_IDE_H
+
+#ifdef __KERNEL__
+
+#include <asm/arch/svinto.h>
+#include <asm/io.h>
+#include <asm-generic/ide_iops.h>
+
+
+/* ETRAX 100 can support 4 IDE busses on the same pins (serialized) */
+
+#define MAX_HWIFS	4
+
+extern __inline__ int ide_default_irq(unsigned long base)
+{
+	/* all IDE busses share the same IRQ, number 4.
+	 * this has the side-effect that ide-probe.c will cluster our 4 interfaces
+	 * together in a hwgroup, and will serialize accesses. this is good, because
+	 * we can't access more than one interface at the same time on ETRAX100.
+	 */
+	return 4;
+}
+
+extern __inline__ unsigned long ide_default_io_base(int index)
+{
+	/* we have no real I/O base address per interface, since all go through the
+	 * same register. but in a bitfield in that register, we have the i/f number.
+	 * so we can use the io_base to remember that bitfield.
+	 */
+	static const unsigned long io_bases[MAX_HWIFS] = {
+		IO_FIELD(R_ATA_CTRL_DATA, sel, 0),
+		IO_FIELD(R_ATA_CTRL_DATA, sel, 1),
+		IO_FIELD(R_ATA_CTRL_DATA, sel, 2),
+		IO_FIELD(R_ATA_CTRL_DATA, sel, 3)
+	};
+	return io_bases[index];
+}
+
+/* this is called once for each interface, to setup the port addresses. data_port is the result
+ * of the ide_default_io_base call above. ctrl_port will be 0, but that is don't care for us.
+ */
+
+extern __inline__ void ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port, unsigned long ctrl_port, int *irq)
+{
+	int i;
+
+	/* fill in ports for ATA addresses 0 to 7 */
+
+	for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
+		hw->io_ports[i] = data_port |
+			IO_FIELD(R_ATA_CTRL_DATA, addr, i) |
+			IO_STATE(R_ATA_CTRL_DATA, cs0, active);
+	}
+
+	/* the IDE control register is at ATA address 6, with CS1 active instead of CS0 */
+
+	hw->io_ports[IDE_CONTROL_OFFSET] = data_port |
+			IO_FIELD(R_ATA_CTRL_DATA, addr, 6) |
+			IO_STATE(R_ATA_CTRL_DATA, cs1, active);
+
+	/* whats this for ? */
+
+	hw->io_ports[IDE_IRQ_OFFSET] = 0;
+}
+
+extern __inline__ void ide_init_default_hwifs(void)
+{
+	hw_regs_t hw;
+	int index;
+
+	for(index = 0; index < MAX_HWIFS; index++) {
+		ide_init_hwif_ports(&hw, ide_default_io_base(index), 0, NULL);
+		hw.irq = ide_default_irq(ide_default_io_base(index));
+		ide_register_hw(&hw, NULL);
+	}
+}
+
+/* some configuration options we don't need */
+
+#undef SUPPORT_VLB_SYNC
+#define SUPPORT_VLB_SYNC 0
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASMCRIS_IDE_H */
diff --git a/include/asm-cris/arch-v10/io.h b/include/asm-cris/arch-v10/io.h
index 0bc38a0313c..dd39198ec67 100644
--- a/include/asm-cris/arch-v10/io.h
+++ b/include/asm-cris/arch-v10/io.h
@@ -6,6 +6,7 @@
 
 /* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */
 
+extern unsigned long gen_config_ii_shadow;
 extern unsigned long port_g_data_shadow;
 extern unsigned char port_pa_dir_shadow;
 extern unsigned char port_pa_data_shadow;
diff --git a/include/asm-cris/arch-v10/io_interface_mux.h b/include/asm-cris/arch-v10/io_interface_mux.h
new file mode 100644
index 00000000000..d9250008088
--- /dev/null
+++ b/include/asm-cris/arch-v10/io_interface_mux.h
@@ -0,0 +1,75 @@
+/* IO interface mux allocator for ETRAX100LX.
+ * Copyright 2004, Axis Communications AB
+ * $Id: io_interface_mux.h,v 1.1 2004/12/13 12:21:53 starvik Exp $
+ */
+
+
+#ifndef _IO_INTERFACE_MUX_H
+#define _IO_INTERFACE_MUX_H
+
+
+/* C.f. ETRAX100LX Designer's Reference 20.9 */
+
+/* The order in enum must match the order of interfaces[] in
+ * io_interface_mux.c */
+enum cris_io_interface {
+	/* Begin Non-multiplexed interfaces */
+	if_eth = 0,
+	if_serial_0,
+	/* End Non-multiplexed interfaces */
+	if_serial_1,
+	if_serial_2,
+	if_serial_3,
+	if_sync_serial_1,
+	if_sync_serial_3,
+	if_shared_ram,
+	if_shared_ram_w,
+	if_par_0,
+	if_par_1,
+	if_par_w,
+	if_scsi8_0,
+	if_scsi8_1,
+	if_scsi_w,
+	if_ata,
+	if_csp,
+	if_i2c,
+	if_usb_1,
+	if_usb_2,
+	/* GPIO pins */
+	if_gpio_grp_a,
+	if_gpio_grp_b,
+	if_gpio_grp_c,
+	if_gpio_grp_d,
+	if_gpio_grp_e,
+	if_gpio_grp_f,
+	if_max_interfaces,
+	if_unclaimed
+};
+
+int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id);
+
+void cris_free_io_interface(enum cris_io_interface ioif);
+
+/* port can be 'a', 'b' or 'g' */
+int cris_io_interface_allocate_pins(const enum cris_io_interface ioif,
+				    const char port,
+				    const unsigned start_bit,
+				    const unsigned stop_bit);
+
+/* port can be 'a', 'b' or 'g' */
+int cris_io_interface_free_pins(const enum cris_io_interface ioif,
+                                const char port,
+                                const unsigned start_bit,
+                                const unsigned stop_bit);
+
+int cris_io_interface_register_watcher(void (*notify)(const unsigned int gpio_in_available,
+						      const unsigned int gpio_out_available,
+						      const unsigned char pa_available,
+						      const unsigned char pb_available));
+
+void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available,
+						     const unsigned int gpio_out_available,
+                                                     const unsigned char pa_available,
+						     const unsigned char pb_available));
+
+#endif /* _IO_INTERFACE_MUX_H */
diff --git a/include/asm-cris/arch-v10/irq.h b/include/asm-cris/arch-v10/irq.h
index a2a6e1533ea..4fa8945b026 100644
--- a/include/asm-cris/arch-v10/irq.h
+++ b/include/asm-cris/arch-v10/irq.h
@@ -74,12 +74,9 @@ struct etrax_interrupt_vector {
 };
 
 extern struct etrax_interrupt_vector *etrax_irv;
-void set_int_vector(int n, irqvectptr addr, irqvectptr saddr);
+void set_int_vector(int n, irqvectptr addr);
 void set_break_vector(int n, irqvectptr addr);
 
-#define mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr));
-#define unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr));
-
 #define __STR(x) #x
 #define STR(x) __STR(x)
  
@@ -121,26 +118,17 @@ void set_break_vector(int n, irqvectptr addr);
 
 #define BUILD_IRQ(nr,mask) \
 void IRQ_NAME(nr); \
-void sIRQ_NAME(nr); \
-void BAD_IRQ_NAME(nr); \
 __asm__ ( \
           ".text\n\t" \
           "IRQ" #nr "_interrupt:\n\t" \
 	  SAVE_ALL \
-	  "sIRQ" #nr "_interrupt:\n\t" /* shortcut for the multiple irq handler */ \
 	  BLOCK_IRQ(mask,nr) /* this must be done to prevent irq loops when we ei later */ \
 	  "moveq "#nr",$r10\n\t" \
 	  "move.d $sp,$r11\n\t" \
 	  "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \
 	  UNBLOCK_IRQ(mask) \
 	  "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \
-	  "jump ret_from_intr\n\t" \
-          "bad_IRQ" #nr "_interrupt:\n\t" \
-	  "push $r0\n\t" \
-	  BLOCK_IRQ(mask,nr) \
-	  "pop $r0\n\t" \
-          "reti\n\t" \
-          "nop\n");
+	  "jump ret_from_intr\n\t");
 
 /* This is subtle. The timer interrupt is crucial and it should not be disabled for 
  * too long. However, if it had been a normal interrupt as per BUILD_IRQ, it would
@@ -159,23 +147,14 @@ __asm__ ( \
 
 #define BUILD_TIMER_IRQ(nr,mask) \
 void IRQ_NAME(nr); \
-void sIRQ_NAME(nr); \
-void BAD_IRQ_NAME(nr); \
 __asm__ ( \
           ".text\n\t" \
           "IRQ" #nr "_interrupt:\n\t" \
 	  SAVE_ALL \
-	  "sIRQ" #nr "_interrupt:\n\t" /* shortcut for the multiple irq handler */ \
 	  "moveq "#nr",$r10\n\t" \
 	  "move.d $sp,$r11\n\t" \
 	  "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \
 	  "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \
-	  "jump ret_from_intr\n\t" \
-          "bad_IRQ" #nr "_interrupt:\n\t" \
-	  "push $r0\n\t" \
-	  BLOCK_IRQ(mask,nr) \
-	  "pop $r0\n\t" \
-          "reti\n\t" \
-          "nop\n");
+	  "jump ret_from_intr\n\t");
 
 #endif
diff --git a/include/asm-cris/arch-v10/memmap.h b/include/asm-cris/arch-v10/memmap.h
new file mode 100644
index 00000000000..13f3b971407
--- /dev/null
+++ b/include/asm-cris/arch-v10/memmap.h
@@ -0,0 +1,22 @@
+#ifndef _ASM_ARCH_MEMMAP_H
+#define _ASM_ARCH_MEMMAP_H
+
+#define MEM_CSE0_START (0x00000000)
+#define MEM_CSE0_SIZE (0x04000000)
+#define MEM_CSE1_START (0x04000000)
+#define MEM_CSE1_SIZE (0x04000000)
+#define MEM_CSR0_START (0x08000000)
+#define MEM_CSR1_START (0x0c000000)
+#define MEM_CSP0_START (0x10000000)
+#define MEM_CSP1_START (0x14000000)
+#define MEM_CSP2_START (0x18000000)
+#define MEM_CSP3_START (0x1c000000)
+#define MEM_CSP4_START (0x20000000)
+#define MEM_CSP5_START (0x24000000)
+#define MEM_CSP6_START (0x28000000)
+#define MEM_CSP7_START (0x2c000000)
+#define MEM_DRAM_START (0x40000000)
+
+#define MEM_NON_CACHEABLE (0x80000000)
+
+#endif
diff --git a/include/asm-cris/arch-v10/mmu.h b/include/asm-cris/arch-v10/mmu.h
index d18aa00e50b..df84f1716e6 100644
--- a/include/asm-cris/arch-v10/mmu.h
+++ b/include/asm-cris/arch-v10/mmu.h
@@ -7,7 +7,10 @@
 
 /* type used in struct mm to couple an MMU context to an active mm */
 
-typedef unsigned int mm_context_t;
+typedef struct
+{
+  unsigned int page_id;
+} mm_context_t;
 
 /* kernel memory segments */
 
diff --git a/include/asm-cris/arch-v10/offset.h b/include/asm-cris/arch-v10/offset.h
index fcbd77eab28..675b51d8563 100644
--- a/include/asm-cris/arch-v10/offset.h
+++ b/include/asm-cris/arch-v10/offset.h
@@ -25,7 +25,7 @@
 #define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */
 #define THREAD_dccr 8 /* offsetof(struct thread_struct, dccr) */
 
-#define TASK_pid 133 /* offsetof(struct task_struct, pid) */
+#define TASK_pid 141 /* offsetof(struct task_struct, pid) */
 
 #define LCLONE_VM 256 /* CLONE_VM */
 #define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */
diff --git a/include/asm-cris/arch-v10/processor.h b/include/asm-cris/arch-v10/processor.h
index 9355d8675a5..e23df8dc96e 100644
--- a/include/asm-cris/arch-v10/processor.h
+++ b/include/asm-cris/arch-v10/processor.h
@@ -59,4 +59,12 @@ struct thread_struct {
 	wrusp(usp);           \
 } while(0)
 
+/* Called when handling a kernel bus fault fixup.
+ *
+ * After a fixup we do not want to return by restoring the CPU-state
+ * anymore, so switch frame-types (see ptrace.h)
+ */
+#define arch_fixup(regs) \
+   regs->frametype = CRIS_FRAME_NORMAL;
+
 #endif
diff --git a/include/asm-cris/arch-v10/system.h b/include/asm-cris/arch-v10/system.h
index 781ca30229a..6cc35642b8a 100644
--- a/include/asm-cris/arch-v10/system.h
+++ b/include/asm-cris/arch-v10/system.h
@@ -11,6 +11,8 @@ extern inline unsigned long rdvr(void) {
 	return vr;
 }
 
+#define cris_machine_name "cris"
+
 /* read/write the user-mode stackpointer */
 
 extern inline unsigned long rdusp(void) {
diff --git a/include/asm-cris/arch-v32/arbiter.h b/include/asm-cris/arch-v32/arbiter.h
new file mode 100644
index 00000000000..dba3c285cac
--- /dev/null
+++ b/include/asm-cris/arch-v32/arbiter.h
@@ -0,0 +1,30 @@
+#ifndef _ASM_CRIS_ARCH_ARBITER_H
+#define _ASM_CRIS_ARCH_ARBITER_H
+
+#define EXT_REGION 0
+#define INT_REGION 1
+
+typedef void (watch_callback)(void);
+
+enum
+{
+  arbiter_all_dmas = 0x3ff,
+  arbiter_cpu = 0xc00,
+  arbiter_all_clients = 0x3fff
+};
+
+enum
+{
+  arbiter_all_read = 0x55,
+  arbiter_all_write = 0xaa,
+  arbiter_all_accesses = 0xff
+};
+
+int crisv32_arbiter_allocate_bandwith(int client, int region,
+                                      unsigned long bandwidth);
+int crisv32_arbiter_watch(unsigned long start, unsigned long size,
+                          unsigned long clients, unsigned long accesses,
+                          watch_callback* cb);
+int crisv32_arbiter_unwatch(int id);
+
+#endif
diff --git a/include/asm-cris/arch-v32/atomic.h b/include/asm-cris/arch-v32/atomic.h
new file mode 100644
index 00000000000..bbfb7a5ae31
--- /dev/null
+++ b/include/asm-cris/arch-v32/atomic.h
@@ -0,0 +1,36 @@
+#ifndef __ASM_CRIS_ARCH_ATOMIC__
+#define __ASM_CRIS_ARCH_ATOMIC__
+
+#include <asm/system.h>
+
+extern void cris_spin_unlock(void *l, int val);
+extern void cris_spin_lock(void *l);
+extern int cris_spin_trylock(void* l);
+
+#ifndef CONFIG_SMP
+#define cris_atomic_save(addr, flags) local_irq_save(flags);
+#define cris_atomic_restore(addr, flags) local_irq_restore(flags);
+#else
+
+extern spinlock_t cris_atomic_locks[];
+#define LOCK_COUNT 128
+#define HASH_ADDR(a) (((int)a) & 127)
+
+#define cris_atomic_save(addr, flags) \
+  local_irq_save(flags); \
+  cris_spin_lock((void*)&cris_atomic_locks[HASH_ADDR(addr)].lock);
+
+#define cris_atomic_restore(addr, flags) \
+  { \
+    spinlock_t *lock = (void*)&cris_atomic_locks[HASH_ADDR(addr)]; \
+    __asm__ volatile ("move.d %1,%0" \
+	                  : "=m" (lock->lock) \
+			  : "r" (1) \
+			  : "memory"); \
+    local_irq_restore(flags); \
+  }
+
+#endif
+
+#endif
+
diff --git a/include/asm-cris/arch-v32/bitops.h b/include/asm-cris/arch-v32/bitops.h
new file mode 100644
index 00000000000..e40a58d3b86
--- /dev/null
+++ b/include/asm-cris/arch-v32/bitops.h
@@ -0,0 +1,64 @@
+#ifndef _ASM_CRIS_ARCH_BITOPS_H
+#define _ASM_CRIS_ARCH_BITOPS_H
+
+/*
+ * Helper functions for the core of the ff[sz] functions. They compute the
+ * number of leading zeroes of a bits-in-byte, byte-in-word and
+ * word-in-dword-swapped number. They differ in that the first function also
+ * inverts all bits in the input.
+ */
+
+extern inline unsigned long
+cris_swapnwbrlz(unsigned long w)
+{
+	unsigned long res;
+
+	__asm__ __volatile__ ("swapnwbr %0\n\t"
+			      "lz %0,%0"
+			      : "=r" (res) : "0" (w));
+
+	return res;
+}
+
+extern inline unsigned long
+cris_swapwbrlz(unsigned long w)
+{
+	unsigned long res;
+
+	__asm__ __volatile__ ("swapwbr %0\n\t"
+			      "lz %0,%0"
+			      : "=r" (res) : "0" (w));
+
+	return res;
+}
+
+/*
+ * Find First Zero in word. Undefined if no zero exist, so the caller should
+ * check against ~0 first.
+ */
+extern inline unsigned long
+ffz(unsigned long w)
+{
+	return cris_swapnwbrlz(w);
+}
+
+/*
+ * Find First Set bit in word. Undefined if no 1 exist, so the caller
+ * should check against 0 first.
+ */
+extern inline unsigned long
+__ffs(unsigned long w)
+{
+	return cris_swapnwbrlz(~w);
+}
+
+/*
+ * Find First Bit that is set.
+ */
+extern inline unsigned long
+kernel_ffs(unsigned long w)
+{
+	return w ? cris_swapwbrlz (w) + 1 : 0;
+}
+
+#endif /* _ASM_CRIS_ARCH_BITOPS_H */
diff --git a/include/asm-cris/arch-v32/byteorder.h b/include/asm-cris/arch-v32/byteorder.h
new file mode 100644
index 00000000000..74846ee6cf9
--- /dev/null
+++ b/include/asm-cris/arch-v32/byteorder.h
@@ -0,0 +1,20 @@
+#ifndef _ASM_CRIS_ARCH_BYTEORDER_H
+#define _ASM_CRIS_ARCH_BYTEORDER_H
+
+#include <asm/types.h>
+
+extern __inline__ __const__ __u32
+___arch__swab32(__u32 x)
+{
+	__asm__ __volatile__ ("swapwb %0" : "=r" (x) : "0" (x));
+	return (x);
+}
+
+extern __inline__ __const__ __u16
+___arch__swab16(__u16 x)
+{
+	__asm__ __volatile__ ("swapb %0" : "=r" (x) : "0" (x));
+	return (x);
+}
+
+#endif /* _ASM_CRIS_ARCH_BYTEORDER_H */
diff --git a/include/asm-cris/arch-v32/cache.h b/include/asm-cris/arch-v32/cache.h
new file mode 100644
index 00000000000..4fed8d62ccc
--- /dev/null
+++ b/include/asm-cris/arch-v32/cache.h
@@ -0,0 +1,9 @@
+#ifndef _ASM_CRIS_ARCH_CACHE_H
+#define _ASM_CRIS_ARCH_CACHE_H
+
+/* A cache-line is 32 bytes. */
+#define L1_CACHE_BYTES 32
+#define L1_CACHE_SHIFT 5
+#define L1_CACHE_SHIFT_MAX 5
+
+#endif /* _ASM_CRIS_ARCH_CACHE_H */
diff --git a/include/asm-cris/arch-v32/checksum.h b/include/asm-cris/arch-v32/checksum.h
new file mode 100644
index 00000000000..a1d6b2a6cc4
--- /dev/null
+++ b/include/asm-cris/arch-v32/checksum.h
@@ -0,0 +1,29 @@
+#ifndef _ASM_CRIS_ARCH_CHECKSUM_H
+#define _ASM_CRIS_ARCH_CHECKSUM_H
+
+/*
+ * Check values used in TCP/UDP headers.
+ *
+ * The gain of doing this in assembler instead of C, is that C doesn't
+ * generate carry-additions for the 32-bit components of the
+ * checksum. Which means it would be necessary to split all those into
+ * 16-bit components and then add.
+ */
+extern inline unsigned int
+csum_tcpudp_nofold(unsigned long saddr, unsigned long daddr,
+		   unsigned short len, unsigned short proto, unsigned int sum)
+{
+	int res;
+
+	__asm__ __volatile__ ("add.d %2, %0\n\t"
+			      "addc %3, %0\n\t"
+			      "addc %4, %0\n\t"
+			      "addc 0, %0\n\t"
+			      : "=r" (res)
+			      : "0" (sum), "r" (daddr), "r" (saddr), \
+			      "r" ((ntohs(len) << 16) + (proto << 8)));
+
+	return res;
+}
+
+#endif /* _ASM_CRIS_ARCH_CHECKSUM_H */
diff --git a/include/asm-cris/arch-v32/cryptocop.h b/include/asm-cris/arch-v32/cryptocop.h
new file mode 100644
index 00000000000..dfa1f66fb98
--- /dev/null
+++ b/include/asm-cris/arch-v32/cryptocop.h
@@ -0,0 +1,272 @@
+/*
+ * The device /dev/cryptocop is accessible using this driver using
+ * CRYPTOCOP_MAJOR (254) and minor number 0.
+ */
+
+#ifndef CRYPTOCOP_H
+#define CRYPTOCOP_H
+
+#include <linux/uio.h>
+
+
+#define CRYPTOCOP_SESSION_ID_NONE (0)
+
+typedef unsigned long long int cryptocop_session_id;
+
+/* cryptocop ioctls */
+#define ETRAXCRYPTOCOP_IOCTYPE         (250)
+
+#define CRYPTOCOP_IO_CREATE_SESSION    _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 1, struct strcop_session_op)
+#define CRYPTOCOP_IO_CLOSE_SESSION     _IOW(ETRAXCRYPTOCOP_IOCTYPE, 2, struct strcop_session_op)
+#define CRYPTOCOP_IO_PROCESS_OP        _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 3, struct strcop_crypto_op)
+#define CRYPTOCOP_IO_MAXNR             (3)
+
+typedef enum {
+	cryptocop_cipher_des = 0,
+	cryptocop_cipher_3des = 1,
+	cryptocop_cipher_aes = 2,
+	cryptocop_cipher_m2m = 3, /* mem2mem is essentially a NULL cipher with blocklength=1 */
+	cryptocop_cipher_none
+} cryptocop_cipher_type;
+
+typedef enum {
+	cryptocop_digest_sha1 = 0,
+	cryptocop_digest_md5 = 1,
+	cryptocop_digest_none
+} cryptocop_digest_type;
+
+typedef enum {
+	cryptocop_csum_le = 0,
+	cryptocop_csum_be = 1,
+	cryptocop_csum_none
+} cryptocop_csum_type;
+
+typedef enum {
+	cryptocop_cipher_mode_ecb = 0,
+	cryptocop_cipher_mode_cbc,
+	cryptocop_cipher_mode_none
+} cryptocop_cipher_mode;
+
+typedef enum {
+	cryptocop_3des_eee = 0,
+	cryptocop_3des_eed = 1,
+	cryptocop_3des_ede = 2,
+	cryptocop_3des_edd = 3,
+	cryptocop_3des_dee = 4,
+	cryptocop_3des_ded = 5,
+	cryptocop_3des_dde = 6,
+	cryptocop_3des_ddd = 7
+} cryptocop_3des_mode;
+
+/* Usermode accessible (ioctl) operations. */
+struct strcop_session_op{
+	cryptocop_session_id    ses_id;
+
+	cryptocop_cipher_type   cipher; /* AES, DES, 3DES, m2m, none */
+
+	cryptocop_cipher_mode   cmode; /* ECB, CBC, none */
+	cryptocop_3des_mode     des3_mode;
+
+	cryptocop_digest_type   digest; /* MD5, SHA1, none */
+
+	cryptocop_csum_type     csum;   /* BE, LE, none */
+
+	unsigned char           *key;
+	size_t                  keylen;
+};
+
+#define CRYPTOCOP_CSUM_LENGTH         (2)
+#define CRYPTOCOP_MAX_DIGEST_LENGTH   (20)  /* SHA-1 20, MD5 16 */
+#define CRYPTOCOP_MAX_IV_LENGTH       (16)  /* (3)DES==8, AES == 16 */
+#define CRYPTOCOP_MAX_KEY_LENGTH      (32)
+
+struct strcop_crypto_op{
+	cryptocop_session_id ses_id;
+
+	/* Indata. */
+	unsigned char            *indata;
+	size_t                   inlen; /* Total indata length. */
+
+	/* Cipher configuration. */
+	unsigned char            do_cipher:1;
+	unsigned char            decrypt:1; /* 1 == decrypt, 0 == encrypt */
+	unsigned char            cipher_explicit:1;
+	size_t                   cipher_start;
+	size_t                   cipher_len;
+	/* cipher_iv is used if do_cipher and cipher_explicit and the cipher
+	   mode is CBC.  The length is controlled by the type of cipher,
+	   e.g. DES/3DES 8 octets and AES 16 octets. */
+	unsigned char            cipher_iv[CRYPTOCOP_MAX_IV_LENGTH];
+	/* Outdata. */
+	unsigned char            *cipher_outdata;
+	size_t                   cipher_outlen;
+
+	/* digest configuration. */
+	unsigned char            do_digest:1;
+	size_t                   digest_start;
+	size_t                   digest_len;
+	/* Outdata.  The actual length is determined by the type of the digest. */
+	unsigned char            digest[CRYPTOCOP_MAX_DIGEST_LENGTH];
+
+	/* Checksum configuration. */
+	unsigned char            do_csum:1;
+	size_t                   csum_start;
+	size_t                   csum_len;
+	/* Outdata. */
+	unsigned char            csum[CRYPTOCOP_CSUM_LENGTH];
+};
+
+
+
+#ifdef __KERNEL__
+
+/********** The API to use from inside the kernel. ************/
+
+#include <asm/arch/hwregs/dma.h>
+
+typedef enum {
+	cryptocop_alg_csum = 0,
+	cryptocop_alg_mem2mem,
+	cryptocop_alg_md5,
+	cryptocop_alg_sha1,
+	cryptocop_alg_des,
+	cryptocop_alg_3des,
+	cryptocop_alg_aes,
+	cryptocop_no_alg,
+} cryptocop_algorithm;
+
+typedef u8 cryptocop_tfrm_id;
+
+
+struct cryptocop_operation;
+
+typedef void (cryptocop_callback)(struct cryptocop_operation*, void*);
+
+struct cryptocop_transform_init {
+	cryptocop_algorithm    alg;
+	/* Keydata for ciphers. */
+	unsigned char          key[CRYPTOCOP_MAX_KEY_LENGTH];
+	unsigned int           keylen;
+	cryptocop_cipher_mode  cipher_mode;
+	cryptocop_3des_mode    tdes_mode;
+	cryptocop_csum_type    csum_mode; /* cryptocop_csum_none is not allowed when alg==cryptocop_alg_csum */
+
+	cryptocop_tfrm_id tid; /* Locally unique in session; assigned by user, checked by driver. */
+	struct cryptocop_transform_init *next;
+};
+
+
+typedef enum {
+	cryptocop_source_dma = 0,
+	cryptocop_source_des,
+	cryptocop_source_3des,
+	cryptocop_source_aes,
+	cryptocop_source_md5,
+	cryptocop_source_sha1,
+	cryptocop_source_csum,
+	cryptocop_source_none,
+} cryptocop_source;
+
+
+struct cryptocop_desc_cfg {
+	cryptocop_tfrm_id tid;
+	cryptocop_source src;
+	unsigned int last:1; /* Last use of this transform in the operation.  Will push outdata when encountered. */
+	struct cryptocop_desc_cfg *next;
+};
+
+struct cryptocop_desc {
+	size_t length;
+	struct cryptocop_desc_cfg *cfg;
+	struct cryptocop_desc *next;
+};
+
+
+/* Flags for cryptocop_tfrm_cfg */
+#define CRYPTOCOP_NO_FLAG     (0x00)
+#define CRYPTOCOP_ENCRYPT     (0x01)
+#define CRYPTOCOP_DECRYPT     (0x02)
+#define CRYPTOCOP_EXPLICIT_IV (0x04)
+
+struct cryptocop_tfrm_cfg {
+	cryptocop_tfrm_id tid;
+
+	unsigned int flags; /* DECRYPT, ENCRYPT, EXPLICIT_IV */
+
+	/* CBC initialisation vector for cihers. */
+	u8 iv[CRYPTOCOP_MAX_IV_LENGTH];
+
+	/* The position in output where to write the transform output.  The order
+	   in which the driver writes the output is unspecified, hence if several
+	   transforms write on the same positions in the output the result is
+	   unspecified. */
+	size_t inject_ix;
+
+	struct cryptocop_tfrm_cfg *next;
+};
+
+
+
+struct cryptocop_dma_list_operation{
+	/* The consumer can provide DMA lists to send to the co-processor.  'use_dmalists' in
+	   struct cryptocop_operation must be set for the driver to use them.  outlist,
+	   out_data_buf, inlist and in_data_buf must all be physical addresses since they will
+	   be loaded to DMA . */
+	dma_descr_data *outlist; /* Out from memory to the co-processor. */
+	char           *out_data_buf;
+	dma_descr_data *inlist; /* In from the co-processor to memory. */
+	char           *in_data_buf;
+
+	cryptocop_3des_mode tdes_mode;
+	cryptocop_csum_type csum_mode;
+};
+
+
+struct cryptocop_tfrm_operation{
+	/* Operation configuration, if not 'use_dmalists' is set. */
+	struct cryptocop_tfrm_cfg *tfrm_cfg;
+	struct cryptocop_desc *desc;
+
+	struct iovec *indata;
+	size_t incount;
+	size_t inlen; /* Total inlength. */
+
+	struct iovec *outdata;
+	size_t outcount;
+	size_t outlen; /* Total outlength. */
+};
+
+
+struct cryptocop_operation {
+	cryptocop_callback *cb;
+	void *cb_data;
+
+	cryptocop_session_id sid;
+
+	/* The status of the operation when returned to consumer. */
+	int operation_status; /* 0, -EAGAIN */
+
+	/* Flags */
+	unsigned int use_dmalists:1;  /* Use outlist and inlist instead of the desc/tfrm_cfg configuration. */
+	unsigned int in_interrupt:1;  /* Set if inserting job from interrupt context. */
+	unsigned int fast_callback:1; /* Set if fast callback wanted, i.e. from interrupt context. */
+
+	union{
+		struct cryptocop_dma_list_operation list_op;
+		struct cryptocop_tfrm_operation tfrm_op;
+	};
+};
+
+
+int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag);
+int cryptocop_free_session(cryptocop_session_id sid);
+
+int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation);
+
+int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation);
+
+int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation);
+
+#endif /* __KERNEL__ */
+
+#endif /* CRYPTOCOP_H */
diff --git a/include/asm-cris/arch-v32/delay.h b/include/asm-cris/arch-v32/delay.h
new file mode 100644
index 00000000000..f36f7f760e8
--- /dev/null
+++ b/include/asm-cris/arch-v32/delay.h
@@ -0,0 +1,18 @@
+#ifndef _ASM_CRIS_ARCH_DELAY_H
+#define _ASM_CRIS_ARCH_DELAY_H
+
+extern __inline__ void
+__delay(int loops)
+{
+	__asm__ __volatile__ (
+		"move.d %0, $r9\n\t"
+		"beq 2f\n\t"
+		"subq 1, $r9\n\t"
+		"1:\n\t"
+		"bne 1b\n\t"
+		"subq 1, $r9\n"
+		"2:"
+		: : "g" (loops) : "r9");
+}
+
+#endif /* _ASM_CRIS_ARCH_DELAY_H */
diff --git a/include/asm-cris/arch-v32/dma.h b/include/asm-cris/arch-v32/dma.h
new file mode 100644
index 00000000000..3674081389f
--- /dev/null
+++ b/include/asm-cris/arch-v32/dma.h
@@ -0,0 +1,79 @@
+#ifndef _ASM_ARCH_CRIS_DMA_H
+#define _ASM_ARCH_CRIS_DMA_H
+
+/* Defines for using and allocating dma channels. */
+
+#define MAX_DMA_CHANNELS	10
+
+#define NETWORK_ETH0_TX_DMA_NBR 0	/* Ethernet 0 out. */
+#define NETWORK_ETH0 RX_DMA_NBR 1	/* Ethernet 0 in. */
+
+#define IO_PROC_DMA0_TX_DMA_NBR 2	/* IO processor DMA0 out. */
+#define IO_PROC_DMA0_RX_DMA_NBR 3	/* IO processor DMA0 in. */
+
+#define ATA_TX_DMA_NBR 2		/* ATA interface out. */
+#define ATA_RX_DMA_NBR 3		/* ATA interface in. */
+
+#define ASYNC_SER2_TX_DMA_NBR 2		/* Asynchronous serial port 2 out. */
+#define ASYNC_SER2_RX_DMA_NBR 3		/* Asynchronous serial port 2 in. */
+
+#define IO_PROC_DMA1_TX_DMA_NBR 4	/* IO processor DMA1 out. */
+#define IO_PROC_DMA1_RX_DMA_NBR 5	/* IO processor DMA1 in. */
+
+#define ASYNC_SER1_TX_DMA_NBR 4		/* Asynchronous serial port 1 out. */
+#define ASYNC_SER1_RX_DMA_NBR 5		/* Asynchronous serial port 1 in. */
+
+#define SYNC_SER0_TX_DMA_NBR 4		/* Synchronous serial port 0 out. */
+#define SYNC_SER0_RX_DMA_NBR 5		/* Synchronous serial port 0 in. */
+
+#define EXTDMA0_TX_DMA_NBR 6		/* External DMA 0 out. */
+#define EXTDMA1_RX_DMA_NBR 7		/* External DMA 1 in. */
+
+#define ASYNC_SER0_TX_DMA_NBR 6		/* Asynchronous serial port 0 out. */
+#define ASYNC_SER0_RX_DMA_NBR 7		/* Asynchronous serial port 0 in. */
+
+#define SYNC_SER1_TX_DMA_NBR 6		/* Synchronous serial port 1 out. */
+#define SYNC_SER1_RX_DMA_NBR 7		/* Synchronous serial port 1 in. */
+
+#define NETWORK_ETH1_TX_DMA_NBR 6	/* Ethernet 1 out. */
+#define NETWORK_ETH1_RX_DMA_NBR 7	/* Ethernet 1 in. */
+
+#define EXTDMA2_TX_DMA_NBR 8		/* External DMA 2 out. */
+#define EXTDMA3_RX_DMA_NBR 9		/* External DMA 3 in. */
+
+#define STRCOP_TX_DMA_NBR 8		/* Stream co-processor out. */
+#define STRCOP_RX_DMA_NBR 9		/* Stream co-processor in. */
+
+#define ASYNC_SER3_TX_DMA_NBR 8		/* Asynchronous serial port 3 out. */
+#define ASYNC_SER3_RX_DMA_NBR 9		/* Asynchronous serial port 3 in. */
+
+enum dma_owner
+{
+  dma_eth0,
+  dma_eth1,
+  dma_iop0,
+  dma_iop1,
+  dma_ser0,
+  dma_ser1,
+  dma_ser2,
+  dma_ser3,
+  dma_sser0,
+  dma_sser1,
+  dma_ata,
+  dma_strp,
+  dma_ext0,
+  dma_ext1,
+  dma_ext2,
+  dma_ext3
+};
+
+int crisv32_request_dma(unsigned int dmanr, const char * device_id,
+                        unsigned options, unsigned bandwidth, enum dma_owner owner);
+void crisv32_free_dma(unsigned int dmanr);
+
+/* Masks used by crisv32_request_dma options: */
+#define DMA_VERBOSE_ON_ERROR 1
+#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
+#define DMA_INT_MEM 4
+
+#endif /* _ASM_ARCH_CRIS_DMA_H */
diff --git a/include/asm-cris/arch-v32/elf.h b/include/asm-cris/arch-v32/elf.h
new file mode 100644
index 00000000000..1324e505a4d
--- /dev/null
+++ b/include/asm-cris/arch-v32/elf.h
@@ -0,0 +1,73 @@
+#ifndef _ASM_CRIS_ELF_H
+#define _ASM_CRIS_ELF_H
+
+#define ELF_CORE_EFLAGS EF_CRIS_VARIANT_V32
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x)			\
+ ((x)->e_machine == EM_CRIS			\
+  && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_V32	\
+      || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32))))
+
+/* CRISv32 ELF register definitions. */
+
+#include <asm/ptrace.h>
+
+/* Explicitly zero out registers to increase determinism. */
+#define ELF_PLAT_INIT(_r, load_addr)    do { \
+        (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \
+        (_r)->r9 = 0;  (_r)->r8 = 0;  (_r)->r7 = 0;  (_r)->r6 = 0;  \
+        (_r)->r5 = 0;  (_r)->r4 = 0;  (_r)->r3 = 0;  (_r)->r2 = 0;  \
+        (_r)->r1 = 0;  (_r)->r0 = 0;  (_r)->mof = 0; (_r)->srp = 0; \
+        (_r)->acr = 0; \
+} while (0)
+
+/*
+ * An executable for which elf_read_implies_exec() returns TRUE will
+ * have the READ_IMPLIES_EXEC personality flag set automatically.
+ */
+#define elf_read_implies_exec_binary(ex, have_pt_gnu_stack)	(!(have_pt_gnu_stack))
+
+/*
+ * This is basically a pt_regs with the additional definition
+ * of the stack pointer since it's needed in a core dump.
+ * pr_regs is a elf_gregset_t and should be filled according
+ * to the layout of user_regs_struct.
+ */
+#define ELF_CORE_COPY_REGS(pr_reg, regs)                   \
+        pr_reg[0] = regs->r0;                              \
+        pr_reg[1] = regs->r1;                              \
+        pr_reg[2] = regs->r2;                              \
+        pr_reg[3] = regs->r3;                              \
+        pr_reg[4] = regs->r4;                              \
+        pr_reg[5] = regs->r5;                              \
+        pr_reg[6] = regs->r6;                              \
+        pr_reg[7] = regs->r7;                              \
+        pr_reg[8] = regs->r8;                              \
+        pr_reg[9] = regs->r9;                              \
+        pr_reg[10] = regs->r10;                            \
+        pr_reg[11] = regs->r11;                            \
+        pr_reg[12] = regs->r12;                            \
+        pr_reg[13] = regs->r13;                            \
+        pr_reg[14] = rdusp();               /* SP */       \
+        pr_reg[15] = regs->acr;             /* ACR */      \
+        pr_reg[16] = 0;                     /* BZ */       \
+        pr_reg[17] = rdvr();                /* VR */       \
+        pr_reg[18] = 0;                     /* PID */      \
+        pr_reg[19] = regs->srs;             /* SRS */      \
+        pr_reg[20] = 0;                     /* WZ */       \
+        pr_reg[21] = regs->exs;             /* EXS */      \
+        pr_reg[22] = regs->eda;             /* EDA */      \
+        pr_reg[23] = regs->mof;             /* MOF */      \
+        pr_reg[24] = 0;                     /* DZ */       \
+        pr_reg[25] = 0;                     /* EBP */      \
+        pr_reg[26] = regs->erp;             /* ERP */      \
+        pr_reg[27] = regs->srp;             /* SRP */      \
+        pr_reg[28] = 0;                     /* NRP */      \
+        pr_reg[29] = regs->ccs;             /* CCS */      \
+        pr_reg[30] = rdusp();               /* USP */      \
+        pr_reg[31] = regs->spc;             /* SPC */      \
+
+#endif /* _ASM_CRIS_ELF_H */
diff --git a/include/asm-cris/arch-v32/hwregs/Makefile b/include/asm-cris/arch-v32/hwregs/Makefile
new file mode 100644
index 00000000000..c9160f9949a
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/Makefile
@@ -0,0 +1,187 @@
+# $Id: Makefile,v 1.8 2004/01/07 21:16:18 johana Exp $
+# Makefile to generate or copy the latest register definitions
+# and related datastructures and helpermacros.
+# The offical place for these files is at:
+RELEASE ?= r1_alfa5
+OFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/
+
+# which is updated on each new release.
+INCL_ASMFILES   =
+INCL_FILES      = ata_defs.h
+INCL_FILES     += bif_core_defs.h
+INCL_ASMFILES  += bif_core_defs_asm.h
+INCL_FILES     += bif_slave_defs.h
+#INCL_FILES     += bif_slave_ext_defs.h
+INCL_FILES     += config_defs.h
+INCL_ASMFILES  += config_defs_asm.h
+INCL_FILES     += cpu_vect.h
+#INCL_FILES     += cris_defs.h
+#INCL_FILES     += cris_supp_reg.h # In handcrafted supp_reg.h
+INCL_FILES     += dma.h
+INCL_FILES     += dma_defs.h
+INCL_FILES     += eth_defs.h
+INCL_FILES     += extmem_defs.h
+INCL_FILES     += gio_defs.h
+INCL_ASMFILES  += gio_defs_asm.h
+INCL_FILES     += intr_vect.h
+INCL_FILES     += intr_vect_defs.h
+INCL_ASMFILES  += intr_vect_defs_asm.h
+INCL_FILES     += marb_bp_defs.h
+INCL_FILES     += marb_defs.h
+INCL_ASMFILES  += mmu_defs_asm.h
+#INCL_FILES     += mmu_supp_reg.h # In handcrafted supp_reg.h
+#INCL_FILES     += par_defs.h # No useful content
+INCL_FILES     += pinmux_defs.h
+INCL_FILES     += reg_map.h
+INCL_ASMFILES  += reg_map_asm.h
+INCL_FILES     += reg_rdwr.h
+INCL_FILES     += ser_defs.h
+#INCL_FILES     += spec_reg.h # In handcrafted supp_reg.h
+INCL_FILES     += sser_defs.h
+INCL_FILES     += strcop_defs.h
+#INCL_FILES     += strcop.h # Where is this?
+INCL_FILES     += strmux_defs.h
+#INCL_FILES     += supp_reg.h # Handcrafted instead
+INCL_FILES     += timer_defs.h
+
+REGDESC =
+REGDESC += $(BASEDIR)/io/ata/rtl/ata_regs.r
+REGDESC += $(BASEDIR)/io/bif/rtl/bif_core_regs.r
+REGDESC += $(BASEDIR)/io/bif/rtl/bif_slave_regs.r
+#REGDESC += $(BASEDIR)/io/bif/sw/bif_slave_ext_regs.r
+REGDESC += $(DESIGNDIR)/top/rtl/config_regs.r
+REGDESC += $(BASEDIR)/mod/dma_common/rtl/dma_regdes.r
+REGDESC += $(BASEDIR)/io/eth/rtl/eth_regs.r
+REGDESC += $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r
+REGDESC += $(DESIGNDIR)/gio/rtl/gio_regs.r
+REGDESC += $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
+REGDESC += $(BASEDIR)/core/memarb/rtl/guinness/marb_top.r
+REGDESC += $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r
+#REGDESC += $(BASEDIR)/io/par_port/rtl/par_regs.r
+REGDESC += $(BASEDIR)/io/pinmux/rtl/guinness/pinmux_regs.r
+REGDESC += $(BASEDIR)/io/ser/rtl/ser_regs.r
+REGDESC += $(BASEDIR)/core/strcop/rtl/strcop_regs.r
+REGDESC += $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r
+REGDESC += $(BASEDIR)/io/timer/rtl/timer_regs.r
+#REGDESC += $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r
+
+
+BASEDIR = /n/asic/design
+DESIGNDIR = /n/asic/projects/guinness/design
+RDES2C = /n/asic/bin/rdes2c
+RDES2C = /n/asic/design/tools/rdesc/rdes2c
+RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr
+RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt
+
+## all    - Just print help - you probably want to do 'make gen'
+all: help
+
+# Disable implicit rule that may generate deleted files from RCS/ directory.
+%.r:
+
+%.h:
+
+## help   - This help
+help:
+	@grep '^## ' Makefile
+
+## gen    - Generate include files
+gen: $(INCL_FILES) $(INCL_ASMFILES)
+
+ata_defs.h: $(BASEDIR)/io/ata/rtl/ata_regs.r
+	$(RDES2C) $<
+config_defs.h: $(DESIGNDIR)/top/rtl/config_regs.r
+	$(RDES2C) $<
+config_defs_asm.h: $(DESIGNDIR)/top/rtl/config_regs.r
+	$(RDES2C) -asm $<
+# Can't generate cpu_vect.h yet
+#cpu_vect.h: $(DESIGNDIR)/top/rtl/cpu_vect.r # ????
+#	$(RDES2INTR) $<
+cpu_vect.h: $(OFFICIAL_INCDIR)cpu_vect.h
+	cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
+dma_defs.h: $(BASEDIR)/core/dma/rtl/common/dma_regdes.r
+	$(RDES2C) $<
+$(BASEDIR)/core/dma/sw/dma.h:
+dma.h: $(BASEDIR)/core/dma/sw/dma.h
+	cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
+eth_defs.h: $(BASEDIR)/io/eth/rtl/eth_regs.r
+	$(RDES2C) $<
+extmem_defs.h: $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r
+	$(RDES2C) $<
+gio_defs.h: $(DESIGNDIR)/gio/rtl/gio_regs.r
+	$(RDES2C) $<
+intr_vect_defs.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
+	$(RDES2C) $<
+intr_vect_defs_asm.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
+	$(RDES2C) -asm $<
+# Can't generate intr_vect.h yet
+#intr_vect.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
+#	$(RDES2INTR) $<
+intr_vect.h: $(OFFICIAL_INCDIR)intr_vect.h
+	cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
+mmu_defs_asm.h: $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r
+	$(RDES2C) -asm $<
+par_defs.h: $(BASEDIR)/io/par_port/rtl/par_regs.r
+	$(RDES2C) $<
+
+# From /n/asic/projects/guinness/design/
+reg_map.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap
+	$(RDES2C) -base 0xb0000000 $^
+reg_map_asm.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap
+	$(RDES2C) -base 0xb0000000 -asm -outfile $@ $^
+
+reg_rdwr.h: $(DESIGNDIR)/top/sw/include/reg_rdwr.h
+	cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
+
+ser_defs.h: $(BASEDIR)/io/ser/rtl/ser_regs.r
+	$(RDES2C) $<
+strcop_defs.h: $(BASEDIR)/core/strcop/rtl/strcop_regs.r
+	$(RDES2C) $<
+strcop.h: $(BASEDIR)/core/strcop/rtl/strcop.h
+	cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
+strmux_defs.h: $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r
+	$(RDES2C) $<
+timer_defs.h: $(BASEDIR)/io/timer/rtl/timer_regs.r
+	$(RDES2C) $<
+usb_defs.h: $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r
+	$(RDES2C) $<
+
+## copy   - Copy files from official location
+copy:
+	@for HFILE in $(INCL_FILES); do \
+		echo "  $$HFILE"; \
+		cat $(OFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
+	done
+	@for HFILE in $(INCL_ASMFILES); do \
+		echo "  $$HFILE"; \
+		cat $(OFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
+	done
+## ls_official - List official location
+ls_official:
+	(cd $(OFFICIAL_INCDIR); ls -l *.h )
+
+## diff_official - Diff current directory with official location
+diff_official:
+	diff . $(OFFICIAL_INCDIR)
+
+## doc    - Generate .axw files from register description.
+doc: $(REGDESC)
+	for RDES in $^; do \
+		$(RDES2TXT) $$RDES; \
+	done
+
+.PHONY: axw
+## %.axw  - Generate the specified .axw file (doesn't work for all files
+##          due to inconsistent naming ir .r files.
+%.axw: axw
+	@for RDES in $(REGDESC); do \
+		if echo "$$RDES" | grep $* ; then \
+		  $(RDES2TXT) $$RDES; \
+		fi \
+	done
+
+.PHONY: clean
+## clean  - Remove .h files and .axw files.
+clean:
+	rm -rf $(INCL_FILES) *.axw
+
diff --git a/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h
new file mode 100644
index 00000000000..866191418f9
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h
@@ -0,0 +1,222 @@
+#ifndef __ata_defs_asm_h
+#define __ata_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/ata/rtl/ata_regs.r
+ *     id:           ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp
+ *     last modfied: Mon Apr 11 16:06:25 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ata_defs_asm.h ../../inst/ata/rtl/ata_regs.r
+ *      id: $Id: ata_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_ctrl0, scope ata, type rw */
+#define reg_ata_rw_ctrl0___pio_hold___lsb 0
+#define reg_ata_rw_ctrl0___pio_hold___width 6
+#define reg_ata_rw_ctrl0___pio_strb___lsb 6
+#define reg_ata_rw_ctrl0___pio_strb___width 6
+#define reg_ata_rw_ctrl0___pio_setup___lsb 12
+#define reg_ata_rw_ctrl0___pio_setup___width 6
+#define reg_ata_rw_ctrl0___dma_hold___lsb 18
+#define reg_ata_rw_ctrl0___dma_hold___width 6
+#define reg_ata_rw_ctrl0___dma_strb___lsb 24
+#define reg_ata_rw_ctrl0___dma_strb___width 6
+#define reg_ata_rw_ctrl0___rst___lsb 30
+#define reg_ata_rw_ctrl0___rst___width 1
+#define reg_ata_rw_ctrl0___rst___bit 30
+#define reg_ata_rw_ctrl0___en___lsb 31
+#define reg_ata_rw_ctrl0___en___width 1
+#define reg_ata_rw_ctrl0___en___bit 31
+#define reg_ata_rw_ctrl0_offset 12
+
+/* Register rw_ctrl1, scope ata, type rw */
+#define reg_ata_rw_ctrl1___udma_tcyc___lsb 0
+#define reg_ata_rw_ctrl1___udma_tcyc___width 4
+#define reg_ata_rw_ctrl1___udma_tdvs___lsb 4
+#define reg_ata_rw_ctrl1___udma_tdvs___width 4
+#define reg_ata_rw_ctrl1_offset 16
+
+/* Register rw_ctrl2, scope ata, type rw */
+#define reg_ata_rw_ctrl2___data___lsb 0
+#define reg_ata_rw_ctrl2___data___width 16
+#define reg_ata_rw_ctrl2___dma_size___lsb 19
+#define reg_ata_rw_ctrl2___dma_size___width 1
+#define reg_ata_rw_ctrl2___dma_size___bit 19
+#define reg_ata_rw_ctrl2___multi___lsb 20
+#define reg_ata_rw_ctrl2___multi___width 1
+#define reg_ata_rw_ctrl2___multi___bit 20
+#define reg_ata_rw_ctrl2___hsh___lsb 21
+#define reg_ata_rw_ctrl2___hsh___width 2
+#define reg_ata_rw_ctrl2___trf_mode___lsb 23
+#define reg_ata_rw_ctrl2___trf_mode___width 1
+#define reg_ata_rw_ctrl2___trf_mode___bit 23
+#define reg_ata_rw_ctrl2___rw___lsb 24
+#define reg_ata_rw_ctrl2___rw___width 1
+#define reg_ata_rw_ctrl2___rw___bit 24
+#define reg_ata_rw_ctrl2___addr___lsb 25
+#define reg_ata_rw_ctrl2___addr___width 3
+#define reg_ata_rw_ctrl2___cs0___lsb 28
+#define reg_ata_rw_ctrl2___cs0___width 1
+#define reg_ata_rw_ctrl2___cs0___bit 28
+#define reg_ata_rw_ctrl2___cs1___lsb 29
+#define reg_ata_rw_ctrl2___cs1___width 1
+#define reg_ata_rw_ctrl2___cs1___bit 29
+#define reg_ata_rw_ctrl2___sel___lsb 30
+#define reg_ata_rw_ctrl2___sel___width 2
+#define reg_ata_rw_ctrl2_offset 0
+
+/* Register rs_stat_data, scope ata, type rs */
+#define reg_ata_rs_stat_data___data___lsb 0
+#define reg_ata_rs_stat_data___data___width 16
+#define reg_ata_rs_stat_data___dav___lsb 16
+#define reg_ata_rs_stat_data___dav___width 1
+#define reg_ata_rs_stat_data___dav___bit 16
+#define reg_ata_rs_stat_data___busy___lsb 17
+#define reg_ata_rs_stat_data___busy___width 1
+#define reg_ata_rs_stat_data___busy___bit 17
+#define reg_ata_rs_stat_data_offset 4
+
+/* Register r_stat_data, scope ata, type r */
+#define reg_ata_r_stat_data___data___lsb 0
+#define reg_ata_r_stat_data___data___width 16
+#define reg_ata_r_stat_data___dav___lsb 16
+#define reg_ata_r_stat_data___dav___width 1
+#define reg_ata_r_stat_data___dav___bit 16
+#define reg_ata_r_stat_data___busy___lsb 17
+#define reg_ata_r_stat_data___busy___width 1
+#define reg_ata_r_stat_data___busy___bit 17
+#define reg_ata_r_stat_data_offset 8
+
+/* Register rw_trf_cnt, scope ata, type rw */
+#define reg_ata_rw_trf_cnt___cnt___lsb 0
+#define reg_ata_rw_trf_cnt___cnt___width 17
+#define reg_ata_rw_trf_cnt_offset 20
+
+/* Register r_stat_misc, scope ata, type r */
+#define reg_ata_r_stat_misc___crc___lsb 0
+#define reg_ata_r_stat_misc___crc___width 16
+#define reg_ata_r_stat_misc_offset 24
+
+/* Register rw_intr_mask, scope ata, type rw */
+#define reg_ata_rw_intr_mask___bus0___lsb 0
+#define reg_ata_rw_intr_mask___bus0___width 1
+#define reg_ata_rw_intr_mask___bus0___bit 0
+#define reg_ata_rw_intr_mask___bus1___lsb 1
+#define reg_ata_rw_intr_mask___bus1___width 1
+#define reg_ata_rw_intr_mask___bus1___bit 1
+#define reg_ata_rw_intr_mask___bus2___lsb 2
+#define reg_ata_rw_intr_mask___bus2___width 1
+#define reg_ata_rw_intr_mask___bus2___bit 2
+#define reg_ata_rw_intr_mask___bus3___lsb 3
+#define reg_ata_rw_intr_mask___bus3___width 1
+#define reg_ata_rw_intr_mask___bus3___bit 3
+#define reg_ata_rw_intr_mask_offset 28
+
+/* Register rw_ack_intr, scope ata, type rw */
+#define reg_ata_rw_ack_intr___bus0___lsb 0
+#define reg_ata_rw_ack_intr___bus0___width 1
+#define reg_ata_rw_ack_intr___bus0___bit 0
+#define reg_ata_rw_ack_intr___bus1___lsb 1
+#define reg_ata_rw_ack_intr___bus1___width 1
+#define reg_ata_rw_ack_intr___bus1___bit 1
+#define reg_ata_rw_ack_intr___bus2___lsb 2
+#define reg_ata_rw_ack_intr___bus2___width 1
+#define reg_ata_rw_ack_intr___bus2___bit 2
+#define reg_ata_rw_ack_intr___bus3___lsb 3
+#define reg_ata_rw_ack_intr___bus3___width 1
+#define reg_ata_rw_ack_intr___bus3___bit 3
+#define reg_ata_rw_ack_intr_offset 32
+
+/* Register r_intr, scope ata, type r */
+#define reg_ata_r_intr___bus0___lsb 0
+#define reg_ata_r_intr___bus0___width 1
+#define reg_ata_r_intr___bus0___bit 0
+#define reg_ata_r_intr___bus1___lsb 1
+#define reg_ata_r_intr___bus1___width 1
+#define reg_ata_r_intr___bus1___bit 1
+#define reg_ata_r_intr___bus2___lsb 2
+#define reg_ata_r_intr___bus2___width 1
+#define reg_ata_r_intr___bus2___bit 2
+#define reg_ata_r_intr___bus3___lsb 3
+#define reg_ata_r_intr___bus3___width 1
+#define reg_ata_r_intr___bus3___bit 3
+#define reg_ata_r_intr_offset 36
+
+/* Register r_masked_intr, scope ata, type r */
+#define reg_ata_r_masked_intr___bus0___lsb 0
+#define reg_ata_r_masked_intr___bus0___width 1
+#define reg_ata_r_masked_intr___bus0___bit 0
+#define reg_ata_r_masked_intr___bus1___lsb 1
+#define reg_ata_r_masked_intr___bus1___width 1
+#define reg_ata_r_masked_intr___bus1___bit 1
+#define reg_ata_r_masked_intr___bus2___lsb 2
+#define reg_ata_r_masked_intr___bus2___width 1
+#define reg_ata_r_masked_intr___bus2___bit 2
+#define reg_ata_r_masked_intr___bus3___lsb 3
+#define reg_ata_r_masked_intr___bus3___width 1
+#define reg_ata_r_masked_intr___bus3___bit 3
+#define reg_ata_r_masked_intr_offset 40
+
+
+/* Constants */
+#define regk_ata_active                           0x00000001
+#define regk_ata_byte                             0x00000001
+#define regk_ata_data                             0x00000001
+#define regk_ata_dma                              0x00000001
+#define regk_ata_inactive                         0x00000000
+#define regk_ata_no                               0x00000000
+#define regk_ata_nodata                           0x00000000
+#define regk_ata_pio                              0x00000000
+#define regk_ata_rd                               0x00000001
+#define regk_ata_reg                              0x00000000
+#define regk_ata_rw_ctrl0_default                 0x00000000
+#define regk_ata_rw_ctrl2_default                 0x00000000
+#define regk_ata_rw_intr_mask_default             0x00000000
+#define regk_ata_udma                             0x00000002
+#define regk_ata_word                             0x00000000
+#define regk_ata_wr                               0x00000000
+#define regk_ata_yes                              0x00000001
+#endif /* __ata_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h
new file mode 100644
index 00000000000..c686cb33562
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/bif_core_defs_asm.h
@@ -0,0 +1,319 @@
+#ifndef __bif_core_defs_asm_h
+#define __bif_core_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/bif/rtl/bif_core_regs.r
+ *     id:           bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
+ *     last modfied: Mon Apr 11 16:06:33 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r
+ *      id: $Id: bif_core_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_grp1_cfg, scope bif_core, type rw */
+#define reg_bif_core_rw_grp1_cfg___lw___lsb 0
+#define reg_bif_core_rw_grp1_cfg___lw___width 6
+#define reg_bif_core_rw_grp1_cfg___ew___lsb 6
+#define reg_bif_core_rw_grp1_cfg___ew___width 3
+#define reg_bif_core_rw_grp1_cfg___zw___lsb 9
+#define reg_bif_core_rw_grp1_cfg___zw___width 3
+#define reg_bif_core_rw_grp1_cfg___aw___lsb 12
+#define reg_bif_core_rw_grp1_cfg___aw___width 2
+#define reg_bif_core_rw_grp1_cfg___dw___lsb 14
+#define reg_bif_core_rw_grp1_cfg___dw___width 2
+#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16
+#define reg_bif_core_rw_grp1_cfg___ewb___width 2
+#define reg_bif_core_rw_grp1_cfg___bw___lsb 18
+#define reg_bif_core_rw_grp1_cfg___bw___width 1
+#define reg_bif_core_rw_grp1_cfg___bw___bit 18
+#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19
+#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1
+#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19
+#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20
+#define reg_bif_core_rw_grp1_cfg___erc_en___width 1
+#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20
+#define reg_bif_core_rw_grp1_cfg___mode___lsb 21
+#define reg_bif_core_rw_grp1_cfg___mode___width 1
+#define reg_bif_core_rw_grp1_cfg___mode___bit 21
+#define reg_bif_core_rw_grp1_cfg_offset 0
+
+/* Register rw_grp2_cfg, scope bif_core, type rw */
+#define reg_bif_core_rw_grp2_cfg___lw___lsb 0
+#define reg_bif_core_rw_grp2_cfg___lw___width 6
+#define reg_bif_core_rw_grp2_cfg___ew___lsb 6
+#define reg_bif_core_rw_grp2_cfg___ew___width 3
+#define reg_bif_core_rw_grp2_cfg___zw___lsb 9
+#define reg_bif_core_rw_grp2_cfg___zw___width 3
+#define reg_bif_core_rw_grp2_cfg___aw___lsb 12
+#define reg_bif_core_rw_grp2_cfg___aw___width 2
+#define reg_bif_core_rw_grp2_cfg___dw___lsb 14
+#define reg_bif_core_rw_grp2_cfg___dw___width 2
+#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16
+#define reg_bif_core_rw_grp2_cfg___ewb___width 2
+#define reg_bif_core_rw_grp2_cfg___bw___lsb 18
+#define reg_bif_core_rw_grp2_cfg___bw___width 1
+#define reg_bif_core_rw_grp2_cfg___bw___bit 18
+#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19
+#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1
+#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19
+#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20
+#define reg_bif_core_rw_grp2_cfg___erc_en___width 1
+#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20
+#define reg_bif_core_rw_grp2_cfg___mode___lsb 21
+#define reg_bif_core_rw_grp2_cfg___mode___width 1
+#define reg_bif_core_rw_grp2_cfg___mode___bit 21
+#define reg_bif_core_rw_grp2_cfg_offset 4
+
+/* Register rw_grp3_cfg, scope bif_core, type rw */
+#define reg_bif_core_rw_grp3_cfg___lw___lsb 0
+#define reg_bif_core_rw_grp3_cfg___lw___width 6
+#define reg_bif_core_rw_grp3_cfg___ew___lsb 6
+#define reg_bif_core_rw_grp3_cfg___ew___width 3
+#define reg_bif_core_rw_grp3_cfg___zw___lsb 9
+#define reg_bif_core_rw_grp3_cfg___zw___width 3
+#define reg_bif_core_rw_grp3_cfg___aw___lsb 12
+#define reg_bif_core_rw_grp3_cfg___aw___width 2
+#define reg_bif_core_rw_grp3_cfg___dw___lsb 14
+#define reg_bif_core_rw_grp3_cfg___dw___width 2
+#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16
+#define reg_bif_core_rw_grp3_cfg___ewb___width 2
+#define reg_bif_core_rw_grp3_cfg___bw___lsb 18
+#define reg_bif_core_rw_grp3_cfg___bw___width 1
+#define reg_bif_core_rw_grp3_cfg___bw___bit 18
+#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19
+#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1
+#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19
+#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20
+#define reg_bif_core_rw_grp3_cfg___erc_en___width 1
+#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20
+#define reg_bif_core_rw_grp3_cfg___mode___lsb 21
+#define reg_bif_core_rw_grp3_cfg___mode___width 1
+#define reg_bif_core_rw_grp3_cfg___mode___bit 21
+#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24
+#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2
+#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26
+#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2
+#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28
+#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2
+#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30
+#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2
+#define reg_bif_core_rw_grp3_cfg_offset 8
+
+/* Register rw_grp4_cfg, scope bif_core, type rw */
+#define reg_bif_core_rw_grp4_cfg___lw___lsb 0
+#define reg_bif_core_rw_grp4_cfg___lw___width 6
+#define reg_bif_core_rw_grp4_cfg___ew___lsb 6
+#define reg_bif_core_rw_grp4_cfg___ew___width 3
+#define reg_bif_core_rw_grp4_cfg___zw___lsb 9
+#define reg_bif_core_rw_grp4_cfg___zw___width 3
+#define reg_bif_core_rw_grp4_cfg___aw___lsb 12
+#define reg_bif_core_rw_grp4_cfg___aw___width 2
+#define reg_bif_core_rw_grp4_cfg___dw___lsb 14
+#define reg_bif_core_rw_grp4_cfg___dw___width 2
+#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16
+#define reg_bif_core_rw_grp4_cfg___ewb___width 2
+#define reg_bif_core_rw_grp4_cfg___bw___lsb 18
+#define reg_bif_core_rw_grp4_cfg___bw___width 1
+#define reg_bif_core_rw_grp4_cfg___bw___bit 18
+#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19
+#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1
+#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19
+#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20
+#define reg_bif_core_rw_grp4_cfg___erc_en___width 1
+#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20
+#define reg_bif_core_rw_grp4_cfg___mode___lsb 21
+#define reg_bif_core_rw_grp4_cfg___mode___width 1
+#define reg_bif_core_rw_grp4_cfg___mode___bit 21
+#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26
+#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2
+#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28
+#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2
+#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30
+#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2
+#define reg_bif_core_rw_grp4_cfg_offset 12
+
+/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
+#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0
+#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5
+#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5
+#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3
+#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8
+#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1
+#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8
+#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9
+#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1
+#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9
+#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10
+#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3
+#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13
+#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1
+#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13
+#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14
+#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1
+#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14
+#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15
+#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5
+#define reg_bif_core_rw_sdram_cfg_grp0_offset 16
+
+/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
+#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0
+#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5
+#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5
+#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3
+#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8
+#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1
+#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8
+#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9
+#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1
+#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9
+#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10
+#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3
+#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13
+#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1
+#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13
+#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14
+#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1
+#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14
+#define reg_bif_core_rw_sdram_cfg_grp1_offset 20
+
+/* Register rw_sdram_timing, scope bif_core, type rw */
+#define reg_bif_core_rw_sdram_timing___cl___lsb 0
+#define reg_bif_core_rw_sdram_timing___cl___width 3
+#define reg_bif_core_rw_sdram_timing___rcd___lsb 3
+#define reg_bif_core_rw_sdram_timing___rcd___width 3
+#define reg_bif_core_rw_sdram_timing___rp___lsb 6
+#define reg_bif_core_rw_sdram_timing___rp___width 3
+#define reg_bif_core_rw_sdram_timing___rc___lsb 9
+#define reg_bif_core_rw_sdram_timing___rc___width 2
+#define reg_bif_core_rw_sdram_timing___dpl___lsb 11
+#define reg_bif_core_rw_sdram_timing___dpl___width 2
+#define reg_bif_core_rw_sdram_timing___pde___lsb 13
+#define reg_bif_core_rw_sdram_timing___pde___width 1
+#define reg_bif_core_rw_sdram_timing___pde___bit 13
+#define reg_bif_core_rw_sdram_timing___ref___lsb 14
+#define reg_bif_core_rw_sdram_timing___ref___width 2
+#define reg_bif_core_rw_sdram_timing___cpd___lsb 16
+#define reg_bif_core_rw_sdram_timing___cpd___width 1
+#define reg_bif_core_rw_sdram_timing___cpd___bit 16
+#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17
+#define reg_bif_core_rw_sdram_timing___sdcke___width 1
+#define reg_bif_core_rw_sdram_timing___sdcke___bit 17
+#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18
+#define reg_bif_core_rw_sdram_timing___sdclk___width 1
+#define reg_bif_core_rw_sdram_timing___sdclk___bit 18
+#define reg_bif_core_rw_sdram_timing_offset 24
+
+/* Register rw_sdram_cmd, scope bif_core, type rw */
+#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0
+#define reg_bif_core_rw_sdram_cmd___cmd___width 3
+#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3
+#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15
+#define reg_bif_core_rw_sdram_cmd_offset 28
+
+/* Register rs_sdram_ref_stat, scope bif_core, type rs */
+#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0
+#define reg_bif_core_rs_sdram_ref_stat___ok___width 1
+#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0
+#define reg_bif_core_rs_sdram_ref_stat_offset 32
+
+/* Register r_sdram_ref_stat, scope bif_core, type r */
+#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0
+#define reg_bif_core_r_sdram_ref_stat___ok___width 1
+#define reg_bif_core_r_sdram_ref_stat___ok___bit 0
+#define reg_bif_core_r_sdram_ref_stat_offset 36
+
+
+/* Constants */
+#define regk_bif_core_bank2                       0x00000000
+#define regk_bif_core_bank4                       0x00000001
+#define regk_bif_core_bit10                       0x0000000a
+#define regk_bif_core_bit11                       0x0000000b
+#define regk_bif_core_bit12                       0x0000000c
+#define regk_bif_core_bit13                       0x0000000d
+#define regk_bif_core_bit14                       0x0000000e
+#define regk_bif_core_bit15                       0x0000000f
+#define regk_bif_core_bit16                       0x00000010
+#define regk_bif_core_bit17                       0x00000011
+#define regk_bif_core_bit18                       0x00000012
+#define regk_bif_core_bit19                       0x00000013
+#define regk_bif_core_bit20                       0x00000014
+#define regk_bif_core_bit21                       0x00000015
+#define regk_bif_core_bit22                       0x00000016
+#define regk_bif_core_bit23                       0x00000017
+#define regk_bif_core_bit24                       0x00000018
+#define regk_bif_core_bit25                       0x00000019
+#define regk_bif_core_bit26                       0x0000001a
+#define regk_bif_core_bit27                       0x0000001b
+#define regk_bif_core_bit28                       0x0000001c
+#define regk_bif_core_bit29                       0x0000001d
+#define regk_bif_core_bit9                        0x00000009
+#define regk_bif_core_bw16                        0x00000001
+#define regk_bif_core_bw32                        0x00000000
+#define regk_bif_core_bwe                         0x00000000
+#define regk_bif_core_cwe                         0x00000001
+#define regk_bif_core_e15us                       0x00000001
+#define regk_bif_core_e7800ns                     0x00000002
+#define regk_bif_core_grp0                        0x00000000
+#define regk_bif_core_grp1                        0x00000001
+#define regk_bif_core_mrs                         0x00000003
+#define regk_bif_core_no                          0x00000000
+#define regk_bif_core_none                        0x00000000
+#define regk_bif_core_nop                         0x00000000
+#define regk_bif_core_off                         0x00000000
+#define regk_bif_core_pre                         0x00000002
+#define regk_bif_core_r_sdram_ref_stat_default    0x00000001
+#define regk_bif_core_rd                          0x00000002
+#define regk_bif_core_ref                         0x00000001
+#define regk_bif_core_rs_sdram_ref_stat_default   0x00000001
+#define regk_bif_core_rw_grp1_cfg_default         0x000006cf
+#define regk_bif_core_rw_grp2_cfg_default         0x000006cf
+#define regk_bif_core_rw_grp3_cfg_default         0x000006cf
+#define regk_bif_core_rw_grp4_cfg_default         0x000006cf
+#define regk_bif_core_rw_sdram_cfg_grp1_default   0x00000000
+#define regk_bif_core_slf                         0x00000004
+#define regk_bif_core_wr                          0x00000001
+#define regk_bif_core_yes                         0x00000001
+#endif /* __bif_core_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h
new file mode 100644
index 00000000000..71532aa1816
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/bif_dma_defs_asm.h
@@ -0,0 +1,495 @@
+#ifndef __bif_dma_defs_asm_h
+#define __bif_dma_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/bif/rtl/bif_dma_regs.r
+ *     id:           bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
+ *     last modfied: Mon Apr 11 16:06:33 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_dma_defs_asm.h ../../inst/bif/rtl/bif_dma_regs.r
+ *      id: $Id: bif_dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_ch0_ctrl, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch0_ctrl___bw___lsb 0
+#define reg_bif_dma_rw_ch0_ctrl___bw___width 2
+#define reg_bif_dma_rw_ch0_ctrl___burst_len___lsb 2
+#define reg_bif_dma_rw_ch0_ctrl___burst_len___width 1
+#define reg_bif_dma_rw_ch0_ctrl___burst_len___bit 2
+#define reg_bif_dma_rw_ch0_ctrl___cont___lsb 3
+#define reg_bif_dma_rw_ch0_ctrl___cont___width 1
+#define reg_bif_dma_rw_ch0_ctrl___cont___bit 3
+#define reg_bif_dma_rw_ch0_ctrl___end_pad___lsb 4
+#define reg_bif_dma_rw_ch0_ctrl___end_pad___width 1
+#define reg_bif_dma_rw_ch0_ctrl___end_pad___bit 4
+#define reg_bif_dma_rw_ch0_ctrl___cnt___lsb 5
+#define reg_bif_dma_rw_ch0_ctrl___cnt___width 1
+#define reg_bif_dma_rw_ch0_ctrl___cnt___bit 5
+#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___lsb 6
+#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___width 3
+#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___lsb 9
+#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___width 2
+#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___lsb 11
+#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___width 3
+#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___lsb 14
+#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___width 2
+#define reg_bif_dma_rw_ch0_ctrl___bus_mode___lsb 16
+#define reg_bif_dma_rw_ch0_ctrl___bus_mode___width 2
+#define reg_bif_dma_rw_ch0_ctrl___rate_en___lsb 18
+#define reg_bif_dma_rw_ch0_ctrl___rate_en___width 1
+#define reg_bif_dma_rw_ch0_ctrl___rate_en___bit 18
+#define reg_bif_dma_rw_ch0_ctrl___wr_all___lsb 19
+#define reg_bif_dma_rw_ch0_ctrl___wr_all___width 1
+#define reg_bif_dma_rw_ch0_ctrl___wr_all___bit 19
+#define reg_bif_dma_rw_ch0_ctrl_offset 0
+
+/* Register rw_ch0_addr, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch0_addr___addr___lsb 0
+#define reg_bif_dma_rw_ch0_addr___addr___width 32
+#define reg_bif_dma_rw_ch0_addr_offset 4
+
+/* Register rw_ch0_start, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch0_start___run___lsb 0
+#define reg_bif_dma_rw_ch0_start___run___width 1
+#define reg_bif_dma_rw_ch0_start___run___bit 0
+#define reg_bif_dma_rw_ch0_start_offset 8
+
+/* Register rw_ch0_cnt, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch0_cnt___start_cnt___lsb 0
+#define reg_bif_dma_rw_ch0_cnt___start_cnt___width 16
+#define reg_bif_dma_rw_ch0_cnt_offset 12
+
+/* Register r_ch0_stat, scope bif_dma, type r */
+#define reg_bif_dma_r_ch0_stat___cnt___lsb 0
+#define reg_bif_dma_r_ch0_stat___cnt___width 16
+#define reg_bif_dma_r_ch0_stat___run___lsb 31
+#define reg_bif_dma_r_ch0_stat___run___width 1
+#define reg_bif_dma_r_ch0_stat___run___bit 31
+#define reg_bif_dma_r_ch0_stat_offset 16
+
+/* Register rw_ch1_ctrl, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch1_ctrl___bw___lsb 0
+#define reg_bif_dma_rw_ch1_ctrl___bw___width 2
+#define reg_bif_dma_rw_ch1_ctrl___burst_len___lsb 2
+#define reg_bif_dma_rw_ch1_ctrl___burst_len___width 1
+#define reg_bif_dma_rw_ch1_ctrl___burst_len___bit 2
+#define reg_bif_dma_rw_ch1_ctrl___cont___lsb 3
+#define reg_bif_dma_rw_ch1_ctrl___cont___width 1
+#define reg_bif_dma_rw_ch1_ctrl___cont___bit 3
+#define reg_bif_dma_rw_ch1_ctrl___end_discard___lsb 4
+#define reg_bif_dma_rw_ch1_ctrl___end_discard___width 1
+#define reg_bif_dma_rw_ch1_ctrl___end_discard___bit 4
+#define reg_bif_dma_rw_ch1_ctrl___cnt___lsb 5
+#define reg_bif_dma_rw_ch1_ctrl___cnt___width 1
+#define reg_bif_dma_rw_ch1_ctrl___cnt___bit 5
+#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___lsb 6
+#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___width 3
+#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___lsb 9
+#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___width 2
+#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___lsb 11
+#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___width 3
+#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___lsb 14
+#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___width 2
+#define reg_bif_dma_rw_ch1_ctrl___bus_mode___lsb 16
+#define reg_bif_dma_rw_ch1_ctrl___bus_mode___width 2
+#define reg_bif_dma_rw_ch1_ctrl___rate_en___lsb 18
+#define reg_bif_dma_rw_ch1_ctrl___rate_en___width 1
+#define reg_bif_dma_rw_ch1_ctrl___rate_en___bit 18
+#define reg_bif_dma_rw_ch1_ctrl_offset 32
+
+/* Register rw_ch1_addr, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch1_addr___addr___lsb 0
+#define reg_bif_dma_rw_ch1_addr___addr___width 32
+#define reg_bif_dma_rw_ch1_addr_offset 36
+
+/* Register rw_ch1_start, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch1_start___run___lsb 0
+#define reg_bif_dma_rw_ch1_start___run___width 1
+#define reg_bif_dma_rw_ch1_start___run___bit 0
+#define reg_bif_dma_rw_ch1_start_offset 40
+
+/* Register rw_ch1_cnt, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch1_cnt___start_cnt___lsb 0
+#define reg_bif_dma_rw_ch1_cnt___start_cnt___width 16
+#define reg_bif_dma_rw_ch1_cnt_offset 44
+
+/* Register r_ch1_stat, scope bif_dma, type r */
+#define reg_bif_dma_r_ch1_stat___cnt___lsb 0
+#define reg_bif_dma_r_ch1_stat___cnt___width 16
+#define reg_bif_dma_r_ch1_stat___run___lsb 31
+#define reg_bif_dma_r_ch1_stat___run___width 1
+#define reg_bif_dma_r_ch1_stat___run___bit 31
+#define reg_bif_dma_r_ch1_stat_offset 48
+
+/* Register rw_ch2_ctrl, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch2_ctrl___bw___lsb 0
+#define reg_bif_dma_rw_ch2_ctrl___bw___width 2
+#define reg_bif_dma_rw_ch2_ctrl___burst_len___lsb 2
+#define reg_bif_dma_rw_ch2_ctrl___burst_len___width 1
+#define reg_bif_dma_rw_ch2_ctrl___burst_len___bit 2
+#define reg_bif_dma_rw_ch2_ctrl___cont___lsb 3
+#define reg_bif_dma_rw_ch2_ctrl___cont___width 1
+#define reg_bif_dma_rw_ch2_ctrl___cont___bit 3
+#define reg_bif_dma_rw_ch2_ctrl___end_pad___lsb 4
+#define reg_bif_dma_rw_ch2_ctrl___end_pad___width 1
+#define reg_bif_dma_rw_ch2_ctrl___end_pad___bit 4
+#define reg_bif_dma_rw_ch2_ctrl___cnt___lsb 5
+#define reg_bif_dma_rw_ch2_ctrl___cnt___width 1
+#define reg_bif_dma_rw_ch2_ctrl___cnt___bit 5
+#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___lsb 6
+#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___width 3
+#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___lsb 9
+#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___width 2
+#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___lsb 11
+#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___width 3
+#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___lsb 14
+#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___width 2
+#define reg_bif_dma_rw_ch2_ctrl___bus_mode___lsb 16
+#define reg_bif_dma_rw_ch2_ctrl___bus_mode___width 2
+#define reg_bif_dma_rw_ch2_ctrl___rate_en___lsb 18
+#define reg_bif_dma_rw_ch2_ctrl___rate_en___width 1
+#define reg_bif_dma_rw_ch2_ctrl___rate_en___bit 18
+#define reg_bif_dma_rw_ch2_ctrl___wr_all___lsb 19
+#define reg_bif_dma_rw_ch2_ctrl___wr_all___width 1
+#define reg_bif_dma_rw_ch2_ctrl___wr_all___bit 19
+#define reg_bif_dma_rw_ch2_ctrl_offset 64
+
+/* Register rw_ch2_addr, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch2_addr___addr___lsb 0
+#define reg_bif_dma_rw_ch2_addr___addr___width 32
+#define reg_bif_dma_rw_ch2_addr_offset 68
+
+/* Register rw_ch2_start, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch2_start___run___lsb 0
+#define reg_bif_dma_rw_ch2_start___run___width 1
+#define reg_bif_dma_rw_ch2_start___run___bit 0
+#define reg_bif_dma_rw_ch2_start_offset 72
+
+/* Register rw_ch2_cnt, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch2_cnt___start_cnt___lsb 0
+#define reg_bif_dma_rw_ch2_cnt___start_cnt___width 16
+#define reg_bif_dma_rw_ch2_cnt_offset 76
+
+/* Register r_ch2_stat, scope bif_dma, type r */
+#define reg_bif_dma_r_ch2_stat___cnt___lsb 0
+#define reg_bif_dma_r_ch2_stat___cnt___width 16
+#define reg_bif_dma_r_ch2_stat___run___lsb 31
+#define reg_bif_dma_r_ch2_stat___run___width 1
+#define reg_bif_dma_r_ch2_stat___run___bit 31
+#define reg_bif_dma_r_ch2_stat_offset 80
+
+/* Register rw_ch3_ctrl, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch3_ctrl___bw___lsb 0
+#define reg_bif_dma_rw_ch3_ctrl___bw___width 2
+#define reg_bif_dma_rw_ch3_ctrl___burst_len___lsb 2
+#define reg_bif_dma_rw_ch3_ctrl___burst_len___width 1
+#define reg_bif_dma_rw_ch3_ctrl___burst_len___bit 2
+#define reg_bif_dma_rw_ch3_ctrl___cont___lsb 3
+#define reg_bif_dma_rw_ch3_ctrl___cont___width 1
+#define reg_bif_dma_rw_ch3_ctrl___cont___bit 3
+#define reg_bif_dma_rw_ch3_ctrl___end_discard___lsb 4
+#define reg_bif_dma_rw_ch3_ctrl___end_discard___width 1
+#define reg_bif_dma_rw_ch3_ctrl___end_discard___bit 4
+#define reg_bif_dma_rw_ch3_ctrl___cnt___lsb 5
+#define reg_bif_dma_rw_ch3_ctrl___cnt___width 1
+#define reg_bif_dma_rw_ch3_ctrl___cnt___bit 5
+#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___lsb 6
+#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___width 3
+#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___lsb 9
+#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___width 2
+#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___lsb 11
+#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___width 3
+#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___lsb 14
+#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___width 2
+#define reg_bif_dma_rw_ch3_ctrl___bus_mode___lsb 16
+#define reg_bif_dma_rw_ch3_ctrl___bus_mode___width 2
+#define reg_bif_dma_rw_ch3_ctrl___rate_en___lsb 18
+#define reg_bif_dma_rw_ch3_ctrl___rate_en___width 1
+#define reg_bif_dma_rw_ch3_ctrl___rate_en___bit 18
+#define reg_bif_dma_rw_ch3_ctrl_offset 96
+
+/* Register rw_ch3_addr, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch3_addr___addr___lsb 0
+#define reg_bif_dma_rw_ch3_addr___addr___width 32
+#define reg_bif_dma_rw_ch3_addr_offset 100
+
+/* Register rw_ch3_start, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch3_start___run___lsb 0
+#define reg_bif_dma_rw_ch3_start___run___width 1
+#define reg_bif_dma_rw_ch3_start___run___bit 0
+#define reg_bif_dma_rw_ch3_start_offset 104
+
+/* Register rw_ch3_cnt, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ch3_cnt___start_cnt___lsb 0
+#define reg_bif_dma_rw_ch3_cnt___start_cnt___width 16
+#define reg_bif_dma_rw_ch3_cnt_offset 108
+
+/* Register r_ch3_stat, scope bif_dma, type r */
+#define reg_bif_dma_r_ch3_stat___cnt___lsb 0
+#define reg_bif_dma_r_ch3_stat___cnt___width 16
+#define reg_bif_dma_r_ch3_stat___run___lsb 31
+#define reg_bif_dma_r_ch3_stat___run___width 1
+#define reg_bif_dma_r_ch3_stat___run___bit 31
+#define reg_bif_dma_r_ch3_stat_offset 112
+
+/* Register rw_intr_mask, scope bif_dma, type rw */
+#define reg_bif_dma_rw_intr_mask___ext_dma0___lsb 0
+#define reg_bif_dma_rw_intr_mask___ext_dma0___width 1
+#define reg_bif_dma_rw_intr_mask___ext_dma0___bit 0
+#define reg_bif_dma_rw_intr_mask___ext_dma1___lsb 1
+#define reg_bif_dma_rw_intr_mask___ext_dma1___width 1
+#define reg_bif_dma_rw_intr_mask___ext_dma1___bit 1
+#define reg_bif_dma_rw_intr_mask___ext_dma2___lsb 2
+#define reg_bif_dma_rw_intr_mask___ext_dma2___width 1
+#define reg_bif_dma_rw_intr_mask___ext_dma2___bit 2
+#define reg_bif_dma_rw_intr_mask___ext_dma3___lsb 3
+#define reg_bif_dma_rw_intr_mask___ext_dma3___width 1
+#define reg_bif_dma_rw_intr_mask___ext_dma3___bit 3
+#define reg_bif_dma_rw_intr_mask_offset 128
+
+/* Register rw_ack_intr, scope bif_dma, type rw */
+#define reg_bif_dma_rw_ack_intr___ext_dma0___lsb 0
+#define reg_bif_dma_rw_ack_intr___ext_dma0___width 1
+#define reg_bif_dma_rw_ack_intr___ext_dma0___bit 0
+#define reg_bif_dma_rw_ack_intr___ext_dma1___lsb 1
+#define reg_bif_dma_rw_ack_intr___ext_dma1___width 1
+#define reg_bif_dma_rw_ack_intr___ext_dma1___bit 1
+#define reg_bif_dma_rw_ack_intr___ext_dma2___lsb 2
+#define reg_bif_dma_rw_ack_intr___ext_dma2___width 1
+#define reg_bif_dma_rw_ack_intr___ext_dma2___bit 2
+#define reg_bif_dma_rw_ack_intr___ext_dma3___lsb 3
+#define reg_bif_dma_rw_ack_intr___ext_dma3___width 1
+#define reg_bif_dma_rw_ack_intr___ext_dma3___bit 3
+#define reg_bif_dma_rw_ack_intr_offset 132
+
+/* Register r_intr, scope bif_dma, type r */
+#define reg_bif_dma_r_intr___ext_dma0___lsb 0
+#define reg_bif_dma_r_intr___ext_dma0___width 1
+#define reg_bif_dma_r_intr___ext_dma0___bit 0
+#define reg_bif_dma_r_intr___ext_dma1___lsb 1
+#define reg_bif_dma_r_intr___ext_dma1___width 1
+#define reg_bif_dma_r_intr___ext_dma1___bit 1
+#define reg_bif_dma_r_intr___ext_dma2___lsb 2
+#define reg_bif_dma_r_intr___ext_dma2___width 1
+#define reg_bif_dma_r_intr___ext_dma2___bit 2
+#define reg_bif_dma_r_intr___ext_dma3___lsb 3
+#define reg_bif_dma_r_intr___ext_dma3___width 1
+#define reg_bif_dma_r_intr___ext_dma3___bit 3
+#define reg_bif_dma_r_intr_offset 136
+
+/* Register r_masked_intr, scope bif_dma, type r */
+#define reg_bif_dma_r_masked_intr___ext_dma0___lsb 0
+#define reg_bif_dma_r_masked_intr___ext_dma0___width 1
+#define reg_bif_dma_r_masked_intr___ext_dma0___bit 0
+#define reg_bif_dma_r_masked_intr___ext_dma1___lsb 1
+#define reg_bif_dma_r_masked_intr___ext_dma1___width 1
+#define reg_bif_dma_r_masked_intr___ext_dma1___bit 1
+#define reg_bif_dma_r_masked_intr___ext_dma2___lsb 2
+#define reg_bif_dma_r_masked_intr___ext_dma2___width 1
+#define reg_bif_dma_r_masked_intr___ext_dma2___bit 2
+#define reg_bif_dma_r_masked_intr___ext_dma3___lsb 3
+#define reg_bif_dma_r_masked_intr___ext_dma3___width 1
+#define reg_bif_dma_r_masked_intr___ext_dma3___bit 3
+#define reg_bif_dma_r_masked_intr_offset 140
+
+/* Register rw_pin0_cfg, scope bif_dma, type rw */
+#define reg_bif_dma_rw_pin0_cfg___master_ch___lsb 0
+#define reg_bif_dma_rw_pin0_cfg___master_ch___width 2
+#define reg_bif_dma_rw_pin0_cfg___master_mode___lsb 2
+#define reg_bif_dma_rw_pin0_cfg___master_mode___width 3
+#define reg_bif_dma_rw_pin0_cfg___slave_ch___lsb 5
+#define reg_bif_dma_rw_pin0_cfg___slave_ch___width 2
+#define reg_bif_dma_rw_pin0_cfg___slave_mode___lsb 7
+#define reg_bif_dma_rw_pin0_cfg___slave_mode___width 3
+#define reg_bif_dma_rw_pin0_cfg_offset 160
+
+/* Register rw_pin1_cfg, scope bif_dma, type rw */
+#define reg_bif_dma_rw_pin1_cfg___master_ch___lsb 0
+#define reg_bif_dma_rw_pin1_cfg___master_ch___width 2
+#define reg_bif_dma_rw_pin1_cfg___master_mode___lsb 2
+#define reg_bif_dma_rw_pin1_cfg___master_mode___width 3
+#define reg_bif_dma_rw_pin1_cfg___slave_ch___lsb 5
+#define reg_bif_dma_rw_pin1_cfg___slave_ch___width 2
+#define reg_bif_dma_rw_pin1_cfg___slave_mode___lsb 7
+#define reg_bif_dma_rw_pin1_cfg___slave_mode___width 3
+#define reg_bif_dma_rw_pin1_cfg_offset 164
+
+/* Register rw_pin2_cfg, scope bif_dma, type rw */
+#define reg_bif_dma_rw_pin2_cfg___master_ch___lsb 0
+#define reg_bif_dma_rw_pin2_cfg___master_ch___width 2
+#define reg_bif_dma_rw_pin2_cfg___master_mode___lsb 2
+#define reg_bif_dma_rw_pin2_cfg___master_mode___width 3
+#define reg_bif_dma_rw_pin2_cfg___slave_ch___lsb 5
+#define reg_bif_dma_rw_pin2_cfg___slave_ch___width 2
+#define reg_bif_dma_rw_pin2_cfg___slave_mode___lsb 7
+#define reg_bif_dma_rw_pin2_cfg___slave_mode___width 3
+#define reg_bif_dma_rw_pin2_cfg_offset 168
+
+/* Register rw_pin3_cfg, scope bif_dma, type rw */
+#define reg_bif_dma_rw_pin3_cfg___master_ch___lsb 0
+#define reg_bif_dma_rw_pin3_cfg___master_ch___width 2
+#define reg_bif_dma_rw_pin3_cfg___master_mode___lsb 2
+#define reg_bif_dma_rw_pin3_cfg___master_mode___width 3
+#define reg_bif_dma_rw_pin3_cfg___slave_ch___lsb 5
+#define reg_bif_dma_rw_pin3_cfg___slave_ch___width 2
+#define reg_bif_dma_rw_pin3_cfg___slave_mode___lsb 7
+#define reg_bif_dma_rw_pin3_cfg___slave_mode___width 3
+#define reg_bif_dma_rw_pin3_cfg_offset 172
+
+/* Register rw_pin4_cfg, scope bif_dma, type rw */
+#define reg_bif_dma_rw_pin4_cfg___master_ch___lsb 0
+#define reg_bif_dma_rw_pin4_cfg___master_ch___width 2
+#define reg_bif_dma_rw_pin4_cfg___master_mode___lsb 2
+#define reg_bif_dma_rw_pin4_cfg___master_mode___width 3
+#define reg_bif_dma_rw_pin4_cfg___slave_ch___lsb 5
+#define reg_bif_dma_rw_pin4_cfg___slave_ch___width 2
+#define reg_bif_dma_rw_pin4_cfg___slave_mode___lsb 7
+#define reg_bif_dma_rw_pin4_cfg___slave_mode___width 3
+#define reg_bif_dma_rw_pin4_cfg_offset 176
+
+/* Register rw_pin5_cfg, scope bif_dma, type rw */
+#define reg_bif_dma_rw_pin5_cfg___master_ch___lsb 0
+#define reg_bif_dma_rw_pin5_cfg___master_ch___width 2
+#define reg_bif_dma_rw_pin5_cfg___master_mode___lsb 2
+#define reg_bif_dma_rw_pin5_cfg___master_mode___width 3
+#define reg_bif_dma_rw_pin5_cfg___slave_ch___lsb 5
+#define reg_bif_dma_rw_pin5_cfg___slave_ch___width 2
+#define reg_bif_dma_rw_pin5_cfg___slave_mode___lsb 7
+#define reg_bif_dma_rw_pin5_cfg___slave_mode___width 3
+#define reg_bif_dma_rw_pin5_cfg_offset 180
+
+/* Register rw_pin6_cfg, scope bif_dma, type rw */
+#define reg_bif_dma_rw_pin6_cfg___master_ch___lsb 0
+#define reg_bif_dma_rw_pin6_cfg___master_ch___width 2
+#define reg_bif_dma_rw_pin6_cfg___master_mode___lsb 2
+#define reg_bif_dma_rw_pin6_cfg___master_mode___width 3
+#define reg_bif_dma_rw_pin6_cfg___slave_ch___lsb 5
+#define reg_bif_dma_rw_pin6_cfg___slave_ch___width 2
+#define reg_bif_dma_rw_pin6_cfg___slave_mode___lsb 7
+#define reg_bif_dma_rw_pin6_cfg___slave_mode___width 3
+#define reg_bif_dma_rw_pin6_cfg_offset 184
+
+/* Register rw_pin7_cfg, scope bif_dma, type rw */
+#define reg_bif_dma_rw_pin7_cfg___master_ch___lsb 0
+#define reg_bif_dma_rw_pin7_cfg___master_ch___width 2
+#define reg_bif_dma_rw_pin7_cfg___master_mode___lsb 2
+#define reg_bif_dma_rw_pin7_cfg___master_mode___width 3
+#define reg_bif_dma_rw_pin7_cfg___slave_ch___lsb 5
+#define reg_bif_dma_rw_pin7_cfg___slave_ch___width 2
+#define reg_bif_dma_rw_pin7_cfg___slave_mode___lsb 7
+#define reg_bif_dma_rw_pin7_cfg___slave_mode___width 3
+#define reg_bif_dma_rw_pin7_cfg_offset 188
+
+/* Register r_pin_stat, scope bif_dma, type r */
+#define reg_bif_dma_r_pin_stat___pin0___lsb 0
+#define reg_bif_dma_r_pin_stat___pin0___width 1
+#define reg_bif_dma_r_pin_stat___pin0___bit 0
+#define reg_bif_dma_r_pin_stat___pin1___lsb 1
+#define reg_bif_dma_r_pin_stat___pin1___width 1
+#define reg_bif_dma_r_pin_stat___pin1___bit 1
+#define reg_bif_dma_r_pin_stat___pin2___lsb 2
+#define reg_bif_dma_r_pin_stat___pin2___width 1
+#define reg_bif_dma_r_pin_stat___pin2___bit 2
+#define reg_bif_dma_r_pin_stat___pin3___lsb 3
+#define reg_bif_dma_r_pin_stat___pin3___width 1
+#define reg_bif_dma_r_pin_stat___pin3___bit 3
+#define reg_bif_dma_r_pin_stat___pin4___lsb 4
+#define reg_bif_dma_r_pin_stat___pin4___width 1
+#define reg_bif_dma_r_pin_stat___pin4___bit 4
+#define reg_bif_dma_r_pin_stat___pin5___lsb 5
+#define reg_bif_dma_r_pin_stat___pin5___width 1
+#define reg_bif_dma_r_pin_stat___pin5___bit 5
+#define reg_bif_dma_r_pin_stat___pin6___lsb 6
+#define reg_bif_dma_r_pin_stat___pin6___width 1
+#define reg_bif_dma_r_pin_stat___pin6___bit 6
+#define reg_bif_dma_r_pin_stat___pin7___lsb 7
+#define reg_bif_dma_r_pin_stat___pin7___width 1
+#define reg_bif_dma_r_pin_stat___pin7___bit 7
+#define reg_bif_dma_r_pin_stat_offset 192
+
+
+/* Constants */
+#define regk_bif_dma_as_master                    0x00000001
+#define regk_bif_dma_as_slave                     0x00000001
+#define regk_bif_dma_burst1                       0x00000000
+#define regk_bif_dma_burst8                       0x00000001
+#define regk_bif_dma_bw16                         0x00000001
+#define regk_bif_dma_bw32                         0x00000002
+#define regk_bif_dma_bw8                          0x00000000
+#define regk_bif_dma_dack                         0x00000006
+#define regk_bif_dma_dack_inv                     0x00000007
+#define regk_bif_dma_force                        0x00000001
+#define regk_bif_dma_hi                           0x00000003
+#define regk_bif_dma_inv                          0x00000003
+#define regk_bif_dma_lo                           0x00000002
+#define regk_bif_dma_master                       0x00000001
+#define regk_bif_dma_no                           0x00000000
+#define regk_bif_dma_norm                         0x00000002
+#define regk_bif_dma_off                          0x00000000
+#define regk_bif_dma_rw_ch0_ctrl_default          0x00000000
+#define regk_bif_dma_rw_ch0_start_default         0x00000000
+#define regk_bif_dma_rw_ch1_ctrl_default          0x00000000
+#define regk_bif_dma_rw_ch1_start_default         0x00000000
+#define regk_bif_dma_rw_ch2_ctrl_default          0x00000000
+#define regk_bif_dma_rw_ch2_start_default         0x00000000
+#define regk_bif_dma_rw_ch3_ctrl_default          0x00000000
+#define regk_bif_dma_rw_ch3_start_default         0x00000000
+#define regk_bif_dma_rw_intr_mask_default         0x00000000
+#define regk_bif_dma_rw_pin0_cfg_default          0x00000000
+#define regk_bif_dma_rw_pin1_cfg_default          0x00000000
+#define regk_bif_dma_rw_pin2_cfg_default          0x00000000
+#define regk_bif_dma_rw_pin3_cfg_default          0x00000000
+#define regk_bif_dma_rw_pin4_cfg_default          0x00000000
+#define regk_bif_dma_rw_pin5_cfg_default          0x00000000
+#define regk_bif_dma_rw_pin6_cfg_default          0x00000000
+#define regk_bif_dma_rw_pin7_cfg_default          0x00000000
+#define regk_bif_dma_slave                        0x00000002
+#define regk_bif_dma_sreq                         0x00000006
+#define regk_bif_dma_sreq_inv                     0x00000007
+#define regk_bif_dma_tc                           0x00000004
+#define regk_bif_dma_tc_inv                       0x00000005
+#define regk_bif_dma_yes                          0x00000001
+#endif /* __bif_dma_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h
new file mode 100644
index 00000000000..031f33a365b
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/bif_slave_defs_asm.h
@@ -0,0 +1,249 @@
+#ifndef __bif_slave_defs_asm_h
+#define __bif_slave_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/bif/rtl/bif_slave_regs.r
+ *     id:           bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp
+ *     last modfied: Mon Apr 11 16:06:34 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_slave_defs_asm.h ../../inst/bif/rtl/bif_slave_regs.r
+ *      id: $Id: bif_slave_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_slave_cfg, scope bif_slave, type rw */
+#define reg_bif_slave_rw_slave_cfg___slave_id___lsb 0
+#define reg_bif_slave_rw_slave_cfg___slave_id___width 3
+#define reg_bif_slave_rw_slave_cfg___use_slave_id___lsb 3
+#define reg_bif_slave_rw_slave_cfg___use_slave_id___width 1
+#define reg_bif_slave_rw_slave_cfg___use_slave_id___bit 3
+#define reg_bif_slave_rw_slave_cfg___boot_rdy___lsb 4
+#define reg_bif_slave_rw_slave_cfg___boot_rdy___width 1
+#define reg_bif_slave_rw_slave_cfg___boot_rdy___bit 4
+#define reg_bif_slave_rw_slave_cfg___loopback___lsb 5
+#define reg_bif_slave_rw_slave_cfg___loopback___width 1
+#define reg_bif_slave_rw_slave_cfg___loopback___bit 5
+#define reg_bif_slave_rw_slave_cfg___dis___lsb 6
+#define reg_bif_slave_rw_slave_cfg___dis___width 1
+#define reg_bif_slave_rw_slave_cfg___dis___bit 6
+#define reg_bif_slave_rw_slave_cfg_offset 0
+
+/* Register r_slave_mode, scope bif_slave, type r */
+#define reg_bif_slave_r_slave_mode___ch0_mode___lsb 0
+#define reg_bif_slave_r_slave_mode___ch0_mode___width 1
+#define reg_bif_slave_r_slave_mode___ch0_mode___bit 0
+#define reg_bif_slave_r_slave_mode___ch1_mode___lsb 1
+#define reg_bif_slave_r_slave_mode___ch1_mode___width 1
+#define reg_bif_slave_r_slave_mode___ch1_mode___bit 1
+#define reg_bif_slave_r_slave_mode___ch2_mode___lsb 2
+#define reg_bif_slave_r_slave_mode___ch2_mode___width 1
+#define reg_bif_slave_r_slave_mode___ch2_mode___bit 2
+#define reg_bif_slave_r_slave_mode___ch3_mode___lsb 3
+#define reg_bif_slave_r_slave_mode___ch3_mode___width 1
+#define reg_bif_slave_r_slave_mode___ch3_mode___bit 3
+#define reg_bif_slave_r_slave_mode_offset 4
+
+/* Register rw_ch0_cfg, scope bif_slave, type rw */
+#define reg_bif_slave_rw_ch0_cfg___rd_hold___lsb 0
+#define reg_bif_slave_rw_ch0_cfg___rd_hold___width 2
+#define reg_bif_slave_rw_ch0_cfg___access_mode___lsb 2
+#define reg_bif_slave_rw_ch0_cfg___access_mode___width 1
+#define reg_bif_slave_rw_ch0_cfg___access_mode___bit 2
+#define reg_bif_slave_rw_ch0_cfg___access_ctrl___lsb 3
+#define reg_bif_slave_rw_ch0_cfg___access_ctrl___width 1
+#define reg_bif_slave_rw_ch0_cfg___access_ctrl___bit 3
+#define reg_bif_slave_rw_ch0_cfg___data_cs___lsb 4
+#define reg_bif_slave_rw_ch0_cfg___data_cs___width 2
+#define reg_bif_slave_rw_ch0_cfg_offset 16
+
+/* Register rw_ch1_cfg, scope bif_slave, type rw */
+#define reg_bif_slave_rw_ch1_cfg___rd_hold___lsb 0
+#define reg_bif_slave_rw_ch1_cfg___rd_hold___width 2
+#define reg_bif_slave_rw_ch1_cfg___access_mode___lsb 2
+#define reg_bif_slave_rw_ch1_cfg___access_mode___width 1
+#define reg_bif_slave_rw_ch1_cfg___access_mode___bit 2
+#define reg_bif_slave_rw_ch1_cfg___access_ctrl___lsb 3
+#define reg_bif_slave_rw_ch1_cfg___access_ctrl___width 1
+#define reg_bif_slave_rw_ch1_cfg___access_ctrl___bit 3
+#define reg_bif_slave_rw_ch1_cfg___data_cs___lsb 4
+#define reg_bif_slave_rw_ch1_cfg___data_cs___width 2
+#define reg_bif_slave_rw_ch1_cfg_offset 20
+
+/* Register rw_ch2_cfg, scope bif_slave, type rw */
+#define reg_bif_slave_rw_ch2_cfg___rd_hold___lsb 0
+#define reg_bif_slave_rw_ch2_cfg___rd_hold___width 2
+#define reg_bif_slave_rw_ch2_cfg___access_mode___lsb 2
+#define reg_bif_slave_rw_ch2_cfg___access_mode___width 1
+#define reg_bif_slave_rw_ch2_cfg___access_mode___bit 2
+#define reg_bif_slave_rw_ch2_cfg___access_ctrl___lsb 3
+#define reg_bif_slave_rw_ch2_cfg___access_ctrl___width 1
+#define reg_bif_slave_rw_ch2_cfg___access_ctrl___bit 3
+#define reg_bif_slave_rw_ch2_cfg___data_cs___lsb 4
+#define reg_bif_slave_rw_ch2_cfg___data_cs___width 2
+#define reg_bif_slave_rw_ch2_cfg_offset 24
+
+/* Register rw_ch3_cfg, scope bif_slave, type rw */
+#define reg_bif_slave_rw_ch3_cfg___rd_hold___lsb 0
+#define reg_bif_slave_rw_ch3_cfg___rd_hold___width 2
+#define reg_bif_slave_rw_ch3_cfg___access_mode___lsb 2
+#define reg_bif_slave_rw_ch3_cfg___access_mode___width 1
+#define reg_bif_slave_rw_ch3_cfg___access_mode___bit 2
+#define reg_bif_slave_rw_ch3_cfg___access_ctrl___lsb 3
+#define reg_bif_slave_rw_ch3_cfg___access_ctrl___width 1
+#define reg_bif_slave_rw_ch3_cfg___access_ctrl___bit 3
+#define reg_bif_slave_rw_ch3_cfg___data_cs___lsb 4
+#define reg_bif_slave_rw_ch3_cfg___data_cs___width 2
+#define reg_bif_slave_rw_ch3_cfg_offset 28
+
+/* Register rw_arb_cfg, scope bif_slave, type rw */
+#define reg_bif_slave_rw_arb_cfg___brin_mode___lsb 0
+#define reg_bif_slave_rw_arb_cfg___brin_mode___width 1
+#define reg_bif_slave_rw_arb_cfg___brin_mode___bit 0
+#define reg_bif_slave_rw_arb_cfg___brout_mode___lsb 1
+#define reg_bif_slave_rw_arb_cfg___brout_mode___width 3
+#define reg_bif_slave_rw_arb_cfg___bg_mode___lsb 4
+#define reg_bif_slave_rw_arb_cfg___bg_mode___width 3
+#define reg_bif_slave_rw_arb_cfg___release___lsb 7
+#define reg_bif_slave_rw_arb_cfg___release___width 2
+#define reg_bif_slave_rw_arb_cfg___acquire___lsb 9
+#define reg_bif_slave_rw_arb_cfg___acquire___width 1
+#define reg_bif_slave_rw_arb_cfg___acquire___bit 9
+#define reg_bif_slave_rw_arb_cfg___settle_time___lsb 10
+#define reg_bif_slave_rw_arb_cfg___settle_time___width 2
+#define reg_bif_slave_rw_arb_cfg___dram_ctrl___lsb 12
+#define reg_bif_slave_rw_arb_cfg___dram_ctrl___width 1
+#define reg_bif_slave_rw_arb_cfg___dram_ctrl___bit 12
+#define reg_bif_slave_rw_arb_cfg_offset 32
+
+/* Register r_arb_stat, scope bif_slave, type r */
+#define reg_bif_slave_r_arb_stat___init_mode___lsb 0
+#define reg_bif_slave_r_arb_stat___init_mode___width 1
+#define reg_bif_slave_r_arb_stat___init_mode___bit 0
+#define reg_bif_slave_r_arb_stat___mode___lsb 1
+#define reg_bif_slave_r_arb_stat___mode___width 1
+#define reg_bif_slave_r_arb_stat___mode___bit 1
+#define reg_bif_slave_r_arb_stat___brin___lsb 2
+#define reg_bif_slave_r_arb_stat___brin___width 1
+#define reg_bif_slave_r_arb_stat___brin___bit 2
+#define reg_bif_slave_r_arb_stat___brout___lsb 3
+#define reg_bif_slave_r_arb_stat___brout___width 1
+#define reg_bif_slave_r_arb_stat___brout___bit 3
+#define reg_bif_slave_r_arb_stat___bg___lsb 4
+#define reg_bif_slave_r_arb_stat___bg___width 1
+#define reg_bif_slave_r_arb_stat___bg___bit 4
+#define reg_bif_slave_r_arb_stat_offset 36
+
+/* Register rw_intr_mask, scope bif_slave, type rw */
+#define reg_bif_slave_rw_intr_mask___bus_release___lsb 0
+#define reg_bif_slave_rw_intr_mask___bus_release___width 1
+#define reg_bif_slave_rw_intr_mask___bus_release___bit 0
+#define reg_bif_slave_rw_intr_mask___bus_acquire___lsb 1
+#define reg_bif_slave_rw_intr_mask___bus_acquire___width 1
+#define reg_bif_slave_rw_intr_mask___bus_acquire___bit 1
+#define reg_bif_slave_rw_intr_mask_offset 64
+
+/* Register rw_ack_intr, scope bif_slave, type rw */
+#define reg_bif_slave_rw_ack_intr___bus_release___lsb 0
+#define reg_bif_slave_rw_ack_intr___bus_release___width 1
+#define reg_bif_slave_rw_ack_intr___bus_release___bit 0
+#define reg_bif_slave_rw_ack_intr___bus_acquire___lsb 1
+#define reg_bif_slave_rw_ack_intr___bus_acquire___width 1
+#define reg_bif_slave_rw_ack_intr___bus_acquire___bit 1
+#define reg_bif_slave_rw_ack_intr_offset 68
+
+/* Register r_intr, scope bif_slave, type r */
+#define reg_bif_slave_r_intr___bus_release___lsb 0
+#define reg_bif_slave_r_intr___bus_release___width 1
+#define reg_bif_slave_r_intr___bus_release___bit 0
+#define reg_bif_slave_r_intr___bus_acquire___lsb 1
+#define reg_bif_slave_r_intr___bus_acquire___width 1
+#define reg_bif_slave_r_intr___bus_acquire___bit 1
+#define reg_bif_slave_r_intr_offset 72
+
+/* Register r_masked_intr, scope bif_slave, type r */
+#define reg_bif_slave_r_masked_intr___bus_release___lsb 0
+#define reg_bif_slave_r_masked_intr___bus_release___width 1
+#define reg_bif_slave_r_masked_intr___bus_release___bit 0
+#define reg_bif_slave_r_masked_intr___bus_acquire___lsb 1
+#define reg_bif_slave_r_masked_intr___bus_acquire___width 1
+#define reg_bif_slave_r_masked_intr___bus_acquire___bit 1
+#define reg_bif_slave_r_masked_intr_offset 76
+
+
+/* Constants */
+#define regk_bif_slave_active_hi                  0x00000003
+#define regk_bif_slave_active_lo                  0x00000002
+#define regk_bif_slave_addr                       0x00000000
+#define regk_bif_slave_always                     0x00000001
+#define regk_bif_slave_at_idle                    0x00000002
+#define regk_bif_slave_burst_end                  0x00000003
+#define regk_bif_slave_dma                        0x00000001
+#define regk_bif_slave_hi                         0x00000003
+#define regk_bif_slave_inv                        0x00000001
+#define regk_bif_slave_lo                         0x00000002
+#define regk_bif_slave_local                      0x00000001
+#define regk_bif_slave_master                     0x00000000
+#define regk_bif_slave_mode_reg                   0x00000001
+#define regk_bif_slave_no                         0x00000000
+#define regk_bif_slave_norm                       0x00000000
+#define regk_bif_slave_on_access                  0x00000000
+#define regk_bif_slave_rw_arb_cfg_default         0x00000000
+#define regk_bif_slave_rw_ch0_cfg_default         0x00000000
+#define regk_bif_slave_rw_ch1_cfg_default         0x00000000
+#define regk_bif_slave_rw_ch2_cfg_default         0x00000000
+#define regk_bif_slave_rw_ch3_cfg_default         0x00000000
+#define regk_bif_slave_rw_intr_mask_default       0x00000000
+#define regk_bif_slave_rw_slave_cfg_default       0x00000000
+#define regk_bif_slave_shared                     0x00000000
+#define regk_bif_slave_slave                      0x00000001
+#define regk_bif_slave_t0ns                       0x00000003
+#define regk_bif_slave_t10ns                      0x00000002
+#define regk_bif_slave_t20ns                      0x00000003
+#define regk_bif_slave_t30ns                      0x00000002
+#define regk_bif_slave_t40ns                      0x00000001
+#define regk_bif_slave_t50ns                      0x00000000
+#define regk_bif_slave_yes                        0x00000001
+#define regk_bif_slave_z                          0x00000004
+#endif /* __bif_slave_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h
new file mode 100644
index 00000000000..e98476332e1
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/config_defs_asm.h
@@ -0,0 +1,131 @@
+#ifndef __config_defs_asm_h
+#define __config_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../rtl/config_regs.r
+ *     id:           config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
+ *     last modfied: Thu Mar  4 12:34:39 2004
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r
+ *      id: $Id: config_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register r_bootsel, scope config, type r */
+#define reg_config_r_bootsel___boot_mode___lsb 0
+#define reg_config_r_bootsel___boot_mode___width 3
+#define reg_config_r_bootsel___full_duplex___lsb 3
+#define reg_config_r_bootsel___full_duplex___width 1
+#define reg_config_r_bootsel___full_duplex___bit 3
+#define reg_config_r_bootsel___user___lsb 4
+#define reg_config_r_bootsel___user___width 1
+#define reg_config_r_bootsel___user___bit 4
+#define reg_config_r_bootsel___pll___lsb 5
+#define reg_config_r_bootsel___pll___width 1
+#define reg_config_r_bootsel___pll___bit 5
+#define reg_config_r_bootsel___flash_bw___lsb 6
+#define reg_config_r_bootsel___flash_bw___width 1
+#define reg_config_r_bootsel___flash_bw___bit 6
+#define reg_config_r_bootsel_offset 0
+
+/* Register rw_clk_ctrl, scope config, type rw */
+#define reg_config_rw_clk_ctrl___pll___lsb 0
+#define reg_config_rw_clk_ctrl___pll___width 1
+#define reg_config_rw_clk_ctrl___pll___bit 0
+#define reg_config_rw_clk_ctrl___cpu___lsb 1
+#define reg_config_rw_clk_ctrl___cpu___width 1
+#define reg_config_rw_clk_ctrl___cpu___bit 1
+#define reg_config_rw_clk_ctrl___iop___lsb 2
+#define reg_config_rw_clk_ctrl___iop___width 1
+#define reg_config_rw_clk_ctrl___iop___bit 2
+#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3
+#define reg_config_rw_clk_ctrl___dma01_eth0___width 1
+#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3
+#define reg_config_rw_clk_ctrl___dma23___lsb 4
+#define reg_config_rw_clk_ctrl___dma23___width 1
+#define reg_config_rw_clk_ctrl___dma23___bit 4
+#define reg_config_rw_clk_ctrl___dma45___lsb 5
+#define reg_config_rw_clk_ctrl___dma45___width 1
+#define reg_config_rw_clk_ctrl___dma45___bit 5
+#define reg_config_rw_clk_ctrl___dma67___lsb 6
+#define reg_config_rw_clk_ctrl___dma67___width 1
+#define reg_config_rw_clk_ctrl___dma67___bit 6
+#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7
+#define reg_config_rw_clk_ctrl___dma89_strcop___width 1
+#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7
+#define reg_config_rw_clk_ctrl___bif___lsb 8
+#define reg_config_rw_clk_ctrl___bif___width 1
+#define reg_config_rw_clk_ctrl___bif___bit 8
+#define reg_config_rw_clk_ctrl___fix_io___lsb 9
+#define reg_config_rw_clk_ctrl___fix_io___width 1
+#define reg_config_rw_clk_ctrl___fix_io___bit 9
+#define reg_config_rw_clk_ctrl_offset 4
+
+/* Register rw_pad_ctrl, scope config, type rw */
+#define reg_config_rw_pad_ctrl___usb_susp___lsb 0
+#define reg_config_rw_pad_ctrl___usb_susp___width 1
+#define reg_config_rw_pad_ctrl___usb_susp___bit 0
+#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1
+#define reg_config_rw_pad_ctrl___phyrst_n___width 1
+#define reg_config_rw_pad_ctrl___phyrst_n___bit 1
+#define reg_config_rw_pad_ctrl_offset 8
+
+
+/* Constants */
+#define regk_config_bw16                          0x00000000
+#define regk_config_bw32                          0x00000001
+#define regk_config_master                        0x00000005
+#define regk_config_nand                          0x00000003
+#define regk_config_net_rx                        0x00000001
+#define regk_config_net_tx_rx                     0x00000002
+#define regk_config_no                            0x00000000
+#define regk_config_none                          0x00000007
+#define regk_config_nor                           0x00000000
+#define regk_config_rw_clk_ctrl_default           0x00000002
+#define regk_config_rw_pad_ctrl_default           0x00000000
+#define regk_config_ser                           0x00000004
+#define regk_config_slave                         0x00000006
+#define regk_config_yes                           0x00000001
+#endif /* __config_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h b/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h
new file mode 100644
index 00000000000..8370aee8a14
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/cpu_vect.h
@@ -0,0 +1,41 @@
+/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
+ from ../../inst/crisp/doc/cpu_vect.r
+version . */
+
+#ifndef _______INST_CRISP_DOC_CPU_VECT_R
+#define _______INST_CRISP_DOC_CPU_VECT_R
+#define NMI_INTR_VECT	0x00
+#define RESERVED_1_INTR_VECT	0x01
+#define RESERVED_2_INTR_VECT	0x02
+#define SINGLE_STEP_INTR_VECT	0x03
+#define INSTR_TLB_REFILL_INTR_VECT	0x04
+#define INSTR_TLB_INV_INTR_VECT	0x05
+#define INSTR_TLB_ACC_INTR_VECT	0x06
+#define TLB_EX_INTR_VECT	0x07
+#define DATA_TLB_REFILL_INTR_VECT	0x08
+#define DATA_TLB_INV_INTR_VECT	0x09
+#define DATA_TLB_ACC_INTR_VECT	0x0a
+#define DATA_TLB_WE_INTR_VECT	0x0b
+#define HW_BP_INTR_VECT	0x0c
+#define RESERVED_D_INTR_VECT	0x0d
+#define RESERVED_E_INTR_VECT	0x0e
+#define RESERVED_F_INTR_VECT	0x0f
+#define BREAK_0_INTR_VECT	0x10
+#define BREAK_1_INTR_VECT	0x11
+#define BREAK_2_INTR_VECT	0x12
+#define BREAK_3_INTR_VECT	0x13
+#define BREAK_4_INTR_VECT	0x14
+#define BREAK_5_INTR_VECT	0x15
+#define BREAK_6_INTR_VECT	0x16
+#define BREAK_7_INTR_VECT	0x17
+#define BREAK_8_INTR_VECT	0x18
+#define BREAK_9_INTR_VECT	0x19
+#define BREAK_10_INTR_VECT	0x1a
+#define BREAK_11_INTR_VECT	0x1b
+#define BREAK_12_INTR_VECT	0x1c
+#define BREAK_13_INTR_VECT	0x1d
+#define BREAK_14_INTR_VECT	0x1e
+#define BREAK_15_INTR_VECT	0x1f
+#define MULTIPLE_INTR_VECT	0x30
+
+#endif
diff --git a/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h
new file mode 100644
index 00000000000..7f768db272e
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/cris_defs_asm.h
@@ -0,0 +1,114 @@
+#ifndef __cris_defs_asm_h
+#define __cris_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/crisp/doc/cris.r
+ *     id:           cris.r,v 1.6 2004/05/05 07:41:12 perz Exp
+ *     last modfied: Mon Apr 11 16:06:39 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/cris_defs_asm.h ../../inst/crisp/doc/cris.r
+ *      id: $Id: cris_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_gc_cfg, scope cris, type rw */
+#define reg_cris_rw_gc_cfg___ic___lsb 0
+#define reg_cris_rw_gc_cfg___ic___width 1
+#define reg_cris_rw_gc_cfg___ic___bit 0
+#define reg_cris_rw_gc_cfg___dc___lsb 1
+#define reg_cris_rw_gc_cfg___dc___width 1
+#define reg_cris_rw_gc_cfg___dc___bit 1
+#define reg_cris_rw_gc_cfg___im___lsb 2
+#define reg_cris_rw_gc_cfg___im___width 1
+#define reg_cris_rw_gc_cfg___im___bit 2
+#define reg_cris_rw_gc_cfg___dm___lsb 3
+#define reg_cris_rw_gc_cfg___dm___width 1
+#define reg_cris_rw_gc_cfg___dm___bit 3
+#define reg_cris_rw_gc_cfg___gb___lsb 4
+#define reg_cris_rw_gc_cfg___gb___width 1
+#define reg_cris_rw_gc_cfg___gb___bit 4
+#define reg_cris_rw_gc_cfg___gk___lsb 5
+#define reg_cris_rw_gc_cfg___gk___width 1
+#define reg_cris_rw_gc_cfg___gk___bit 5
+#define reg_cris_rw_gc_cfg___gp___lsb 6
+#define reg_cris_rw_gc_cfg___gp___width 1
+#define reg_cris_rw_gc_cfg___gp___bit 6
+#define reg_cris_rw_gc_cfg_offset 0
+
+/* Register rw_gc_ccs, scope cris, type rw */
+#define reg_cris_rw_gc_ccs_offset 4
+
+/* Register rw_gc_srs, scope cris, type rw */
+#define reg_cris_rw_gc_srs___srs___lsb 0
+#define reg_cris_rw_gc_srs___srs___width 8
+#define reg_cris_rw_gc_srs_offset 8
+
+/* Register rw_gc_nrp, scope cris, type rw */
+#define reg_cris_rw_gc_nrp_offset 12
+
+/* Register rw_gc_exs, scope cris, type rw */
+#define reg_cris_rw_gc_exs_offset 16
+
+/* Register rw_gc_eda, scope cris, type rw */
+#define reg_cris_rw_gc_eda_offset 20
+
+/* Register rw_gc_r0, scope cris, type rw */
+#define reg_cris_rw_gc_r0_offset 32
+
+/* Register rw_gc_r1, scope cris, type rw */
+#define reg_cris_rw_gc_r1_offset 36
+
+/* Register rw_gc_r2, scope cris, type rw */
+#define reg_cris_rw_gc_r2_offset 40
+
+/* Register rw_gc_r3, scope cris, type rw */
+#define reg_cris_rw_gc_r3_offset 44
+
+
+/* Constants */
+#define regk_cris_no                              0x00000000
+#define regk_cris_rw_gc_cfg_default               0x00000000
+#define regk_cris_yes                             0x00000001
+#endif /* __cris_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h b/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h
new file mode 100644
index 00000000000..7d3689a6f80
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/cris_supp_reg.h
@@ -0,0 +1,10 @@
+#define RW_GC_CFG	0
+#define RW_GC_CCS	1
+#define RW_GC_SRS	2
+#define RW_GC_NRP	3
+#define RW_GC_EXS	4
+#define RW_GC_EDA	5
+#define RW_GC_R0	8
+#define RW_GC_R1	9
+#define RW_GC_R2	10
+#define RW_GC_R3	11
diff --git a/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h
new file mode 100644
index 00000000000..0cb71bc127a
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/dma_defs_asm.h
@@ -0,0 +1,368 @@
+#ifndef __dma_defs_asm_h
+#define __dma_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
+ *     id:           dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp
+ *     last modfied: Mon Apr 11 16:06:51 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/dma_defs_asm.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
+ *      id: $Id: dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_data, scope dma, type rw */
+#define reg_dma_rw_data_offset 0
+
+/* Register rw_data_next, scope dma, type rw */
+#define reg_dma_rw_data_next_offset 4
+
+/* Register rw_data_buf, scope dma, type rw */
+#define reg_dma_rw_data_buf_offset 8
+
+/* Register rw_data_ctrl, scope dma, type rw */
+#define reg_dma_rw_data_ctrl___eol___lsb 0
+#define reg_dma_rw_data_ctrl___eol___width 1
+#define reg_dma_rw_data_ctrl___eol___bit 0
+#define reg_dma_rw_data_ctrl___out_eop___lsb 3
+#define reg_dma_rw_data_ctrl___out_eop___width 1
+#define reg_dma_rw_data_ctrl___out_eop___bit 3
+#define reg_dma_rw_data_ctrl___intr___lsb 4
+#define reg_dma_rw_data_ctrl___intr___width 1
+#define reg_dma_rw_data_ctrl___intr___bit 4
+#define reg_dma_rw_data_ctrl___wait___lsb 5
+#define reg_dma_rw_data_ctrl___wait___width 1
+#define reg_dma_rw_data_ctrl___wait___bit 5
+#define reg_dma_rw_data_ctrl_offset 12
+
+/* Register rw_data_stat, scope dma, type rw */
+#define reg_dma_rw_data_stat___in_eop___lsb 3
+#define reg_dma_rw_data_stat___in_eop___width 1
+#define reg_dma_rw_data_stat___in_eop___bit 3
+#define reg_dma_rw_data_stat_offset 16
+
+/* Register rw_data_md, scope dma, type rw */
+#define reg_dma_rw_data_md___md___lsb 0
+#define reg_dma_rw_data_md___md___width 16
+#define reg_dma_rw_data_md_offset 20
+
+/* Register rw_data_md_s, scope dma, type rw */
+#define reg_dma_rw_data_md_s___md_s___lsb 0
+#define reg_dma_rw_data_md_s___md_s___width 16
+#define reg_dma_rw_data_md_s_offset 24
+
+/* Register rw_data_after, scope dma, type rw */
+#define reg_dma_rw_data_after_offset 28
+
+/* Register rw_ctxt, scope dma, type rw */
+#define reg_dma_rw_ctxt_offset 32
+
+/* Register rw_ctxt_next, scope dma, type rw */
+#define reg_dma_rw_ctxt_next_offset 36
+
+/* Register rw_ctxt_ctrl, scope dma, type rw */
+#define reg_dma_rw_ctxt_ctrl___eol___lsb 0
+#define reg_dma_rw_ctxt_ctrl___eol___width 1
+#define reg_dma_rw_ctxt_ctrl___eol___bit 0
+#define reg_dma_rw_ctxt_ctrl___intr___lsb 4
+#define reg_dma_rw_ctxt_ctrl___intr___width 1
+#define reg_dma_rw_ctxt_ctrl___intr___bit 4
+#define reg_dma_rw_ctxt_ctrl___store_mode___lsb 6
+#define reg_dma_rw_ctxt_ctrl___store_mode___width 1
+#define reg_dma_rw_ctxt_ctrl___store_mode___bit 6
+#define reg_dma_rw_ctxt_ctrl___en___lsb 7
+#define reg_dma_rw_ctxt_ctrl___en___width 1
+#define reg_dma_rw_ctxt_ctrl___en___bit 7
+#define reg_dma_rw_ctxt_ctrl_offset 40
+
+/* Register rw_ctxt_stat, scope dma, type rw */
+#define reg_dma_rw_ctxt_stat___dis___lsb 7
+#define reg_dma_rw_ctxt_stat___dis___width 1
+#define reg_dma_rw_ctxt_stat___dis___bit 7
+#define reg_dma_rw_ctxt_stat_offset 44
+
+/* Register rw_ctxt_md0, scope dma, type rw */
+#define reg_dma_rw_ctxt_md0___md0___lsb 0
+#define reg_dma_rw_ctxt_md0___md0___width 16
+#define reg_dma_rw_ctxt_md0_offset 48
+
+/* Register rw_ctxt_md0_s, scope dma, type rw */
+#define reg_dma_rw_ctxt_md0_s___md0_s___lsb 0
+#define reg_dma_rw_ctxt_md0_s___md0_s___width 16
+#define reg_dma_rw_ctxt_md0_s_offset 52
+
+/* Register rw_ctxt_md1, scope dma, type rw */
+#define reg_dma_rw_ctxt_md1_offset 56
+
+/* Register rw_ctxt_md1_s, scope dma, type rw */
+#define reg_dma_rw_ctxt_md1_s_offset 60
+
+/* Register rw_ctxt_md2, scope dma, type rw */
+#define reg_dma_rw_ctxt_md2_offset 64
+
+/* Register rw_ctxt_md2_s, scope dma, type rw */
+#define reg_dma_rw_ctxt_md2_s_offset 68
+
+/* Register rw_ctxt_md3, scope dma, type rw */
+#define reg_dma_rw_ctxt_md3_offset 72
+
+/* Register rw_ctxt_md3_s, scope dma, type rw */
+#define reg_dma_rw_ctxt_md3_s_offset 76
+
+/* Register rw_ctxt_md4, scope dma, type rw */
+#define reg_dma_rw_ctxt_md4_offset 80
+
+/* Register rw_ctxt_md4_s, scope dma, type rw */
+#define reg_dma_rw_ctxt_md4_s_offset 84
+
+/* Register rw_saved_data, scope dma, type rw */
+#define reg_dma_rw_saved_data_offset 88
+
+/* Register rw_saved_data_buf, scope dma, type rw */
+#define reg_dma_rw_saved_data_buf_offset 92
+
+/* Register rw_group, scope dma, type rw */
+#define reg_dma_rw_group_offset 96
+
+/* Register rw_group_next, scope dma, type rw */
+#define reg_dma_rw_group_next_offset 100
+
+/* Register rw_group_ctrl, scope dma, type rw */
+#define reg_dma_rw_group_ctrl___eol___lsb 0
+#define reg_dma_rw_group_ctrl___eol___width 1
+#define reg_dma_rw_group_ctrl___eol___bit 0
+#define reg_dma_rw_group_ctrl___tol___lsb 1
+#define reg_dma_rw_group_ctrl___tol___width 1
+#define reg_dma_rw_group_ctrl___tol___bit 1
+#define reg_dma_rw_group_ctrl___bol___lsb 2
+#define reg_dma_rw_group_ctrl___bol___width 1
+#define reg_dma_rw_group_ctrl___bol___bit 2
+#define reg_dma_rw_group_ctrl___intr___lsb 4
+#define reg_dma_rw_group_ctrl___intr___width 1
+#define reg_dma_rw_group_ctrl___intr___bit 4
+#define reg_dma_rw_group_ctrl___en___lsb 7
+#define reg_dma_rw_group_ctrl___en___width 1
+#define reg_dma_rw_group_ctrl___en___bit 7
+#define reg_dma_rw_group_ctrl_offset 104
+
+/* Register rw_group_stat, scope dma, type rw */
+#define reg_dma_rw_group_stat___dis___lsb 7
+#define reg_dma_rw_group_stat___dis___width 1
+#define reg_dma_rw_group_stat___dis___bit 7
+#define reg_dma_rw_group_stat_offset 108
+
+/* Register rw_group_md, scope dma, type rw */
+#define reg_dma_rw_group_md___md___lsb 0
+#define reg_dma_rw_group_md___md___width 16
+#define reg_dma_rw_group_md_offset 112
+
+/* Register rw_group_md_s, scope dma, type rw */
+#define reg_dma_rw_group_md_s___md_s___lsb 0
+#define reg_dma_rw_group_md_s___md_s___width 16
+#define reg_dma_rw_group_md_s_offset 116
+
+/* Register rw_group_up, scope dma, type rw */
+#define reg_dma_rw_group_up_offset 120
+
+/* Register rw_group_down, scope dma, type rw */
+#define reg_dma_rw_group_down_offset 124
+
+/* Register rw_cmd, scope dma, type rw */
+#define reg_dma_rw_cmd___cont_data___lsb 0
+#define reg_dma_rw_cmd___cont_data___width 1
+#define reg_dma_rw_cmd___cont_data___bit 0
+#define reg_dma_rw_cmd_offset 128
+
+/* Register rw_cfg, scope dma, type rw */
+#define reg_dma_rw_cfg___en___lsb 0
+#define reg_dma_rw_cfg___en___width 1
+#define reg_dma_rw_cfg___en___bit 0
+#define reg_dma_rw_cfg___stop___lsb 1
+#define reg_dma_rw_cfg___stop___width 1
+#define reg_dma_rw_cfg___stop___bit 1
+#define reg_dma_rw_cfg_offset 132
+
+/* Register rw_stat, scope dma, type rw */
+#define reg_dma_rw_stat___mode___lsb 0
+#define reg_dma_rw_stat___mode___width 5
+#define reg_dma_rw_stat___list_state___lsb 5
+#define reg_dma_rw_stat___list_state___width 3
+#define reg_dma_rw_stat___stream_cmd_src___lsb 8
+#define reg_dma_rw_stat___stream_cmd_src___width 8
+#define reg_dma_rw_stat___buf___lsb 24
+#define reg_dma_rw_stat___buf___width 8
+#define reg_dma_rw_stat_offset 136
+
+/* Register rw_intr_mask, scope dma, type rw */
+#define reg_dma_rw_intr_mask___group___lsb 0
+#define reg_dma_rw_intr_mask___group___width 1
+#define reg_dma_rw_intr_mask___group___bit 0
+#define reg_dma_rw_intr_mask___ctxt___lsb 1
+#define reg_dma_rw_intr_mask___ctxt___width 1
+#define reg_dma_rw_intr_mask___ctxt___bit 1
+#define reg_dma_rw_intr_mask___data___lsb 2
+#define reg_dma_rw_intr_mask___data___width 1
+#define reg_dma_rw_intr_mask___data___bit 2
+#define reg_dma_rw_intr_mask___in_eop___lsb 3
+#define reg_dma_rw_intr_mask___in_eop___width 1
+#define reg_dma_rw_intr_mask___in_eop___bit 3
+#define reg_dma_rw_intr_mask___stream_cmd___lsb 4
+#define reg_dma_rw_intr_mask___stream_cmd___width 1
+#define reg_dma_rw_intr_mask___stream_cmd___bit 4
+#define reg_dma_rw_intr_mask_offset 140
+
+/* Register rw_ack_intr, scope dma, type rw */
+#define reg_dma_rw_ack_intr___group___lsb 0
+#define reg_dma_rw_ack_intr___group___width 1
+#define reg_dma_rw_ack_intr___group___bit 0
+#define reg_dma_rw_ack_intr___ctxt___lsb 1
+#define reg_dma_rw_ack_intr___ctxt___width 1
+#define reg_dma_rw_ack_intr___ctxt___bit 1
+#define reg_dma_rw_ack_intr___data___lsb 2
+#define reg_dma_rw_ack_intr___data___width 1
+#define reg_dma_rw_ack_intr___data___bit 2
+#define reg_dma_rw_ack_intr___in_eop___lsb 3
+#define reg_dma_rw_ack_intr___in_eop___width 1
+#define reg_dma_rw_ack_intr___in_eop___bit 3
+#define reg_dma_rw_ack_intr___stream_cmd___lsb 4
+#define reg_dma_rw_ack_intr___stream_cmd___width 1
+#define reg_dma_rw_ack_intr___stream_cmd___bit 4
+#define reg_dma_rw_ack_intr_offset 144
+
+/* Register r_intr, scope dma, type r */
+#define reg_dma_r_intr___group___lsb 0
+#define reg_dma_r_intr___group___width 1
+#define reg_dma_r_intr___group___bit 0
+#define reg_dma_r_intr___ctxt___lsb 1
+#define reg_dma_r_intr___ctxt___width 1
+#define reg_dma_r_intr___ctxt___bit 1
+#define reg_dma_r_intr___data___lsb 2
+#define reg_dma_r_intr___data___width 1
+#define reg_dma_r_intr___data___bit 2
+#define reg_dma_r_intr___in_eop___lsb 3
+#define reg_dma_r_intr___in_eop___width 1
+#define reg_dma_r_intr___in_eop___bit 3
+#define reg_dma_r_intr___stream_cmd___lsb 4
+#define reg_dma_r_intr___stream_cmd___width 1
+#define reg_dma_r_intr___stream_cmd___bit 4
+#define reg_dma_r_intr_offset 148
+
+/* Register r_masked_intr, scope dma, type r */
+#define reg_dma_r_masked_intr___group___lsb 0
+#define reg_dma_r_masked_intr___group___width 1
+#define reg_dma_r_masked_intr___group___bit 0
+#define reg_dma_r_masked_intr___ctxt___lsb 1
+#define reg_dma_r_masked_intr___ctxt___width 1
+#define reg_dma_r_masked_intr___ctxt___bit 1
+#define reg_dma_r_masked_intr___data___lsb 2
+#define reg_dma_r_masked_intr___data___width 1
+#define reg_dma_r_masked_intr___data___bit 2
+#define reg_dma_r_masked_intr___in_eop___lsb 3
+#define reg_dma_r_masked_intr___in_eop___width 1
+#define reg_dma_r_masked_intr___in_eop___bit 3
+#define reg_dma_r_masked_intr___stream_cmd___lsb 4
+#define reg_dma_r_masked_intr___stream_cmd___width 1
+#define reg_dma_r_masked_intr___stream_cmd___bit 4
+#define reg_dma_r_masked_intr_offset 152
+
+/* Register rw_stream_cmd, scope dma, type rw */
+#define reg_dma_rw_stream_cmd___cmd___lsb 0
+#define reg_dma_rw_stream_cmd___cmd___width 10
+#define reg_dma_rw_stream_cmd___n___lsb 16
+#define reg_dma_rw_stream_cmd___n___width 8
+#define reg_dma_rw_stream_cmd___busy___lsb 31
+#define reg_dma_rw_stream_cmd___busy___width 1
+#define reg_dma_rw_stream_cmd___busy___bit 31
+#define reg_dma_rw_stream_cmd_offset 156
+
+
+/* Constants */
+#define regk_dma_ack_pkt                          0x00000100
+#define regk_dma_anytime                          0x00000001
+#define regk_dma_array                            0x00000008
+#define regk_dma_burst                            0x00000020
+#define regk_dma_client                           0x00000002
+#define regk_dma_copy_next                        0x00000010
+#define regk_dma_copy_up                          0x00000020
+#define regk_dma_data_at_eol                      0x00000001
+#define regk_dma_dis_c                            0x00000010
+#define regk_dma_dis_g                            0x00000020
+#define regk_dma_idle                             0x00000001
+#define regk_dma_intern                           0x00000004
+#define regk_dma_load_c                           0x00000200
+#define regk_dma_load_c_n                         0x00000280
+#define regk_dma_load_c_next                      0x00000240
+#define regk_dma_load_d                           0x00000140
+#define regk_dma_load_g                           0x00000300
+#define regk_dma_load_g_down                      0x000003c0
+#define regk_dma_load_g_next                      0x00000340
+#define regk_dma_load_g_up                        0x00000380
+#define regk_dma_next_en                          0x00000010
+#define regk_dma_next_pkt                         0x00000010
+#define regk_dma_no                               0x00000000
+#define regk_dma_only_at_wait                     0x00000000
+#define regk_dma_restore                          0x00000020
+#define regk_dma_rst                              0x00000001
+#define regk_dma_running                          0x00000004
+#define regk_dma_rw_cfg_default                   0x00000000
+#define regk_dma_rw_cmd_default                   0x00000000
+#define regk_dma_rw_intr_mask_default             0x00000000
+#define regk_dma_rw_stat_default                  0x00000101
+#define regk_dma_rw_stream_cmd_default            0x00000000
+#define regk_dma_save_down                        0x00000020
+#define regk_dma_save_up                          0x00000020
+#define regk_dma_set_reg                          0x00000050
+#define regk_dma_set_w_size1                      0x00000190
+#define regk_dma_set_w_size2                      0x000001a0
+#define regk_dma_set_w_size4                      0x000001c0
+#define regk_dma_stopped                          0x00000002
+#define regk_dma_store_c                          0x00000002
+#define regk_dma_store_descr                      0x00000000
+#define regk_dma_store_g                          0x00000004
+#define regk_dma_store_md                         0x00000001
+#define regk_dma_sw                               0x00000008
+#define regk_dma_update_down                      0x00000020
+#define regk_dma_yes                              0x00000001
+#endif /* __dma_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h
new file mode 100644
index 00000000000..c9f49864831
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h
@@ -0,0 +1,498 @@
+#ifndef __eth_defs_asm_h
+#define __eth_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/eth/rtl/eth_regs.r
+ *     id:           eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp
+ *     last modfied: Mon Apr 11 16:07:03 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/eth_defs_asm.h ../../inst/eth/rtl/eth_regs.r
+ *      id: $Id: eth_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_ma0_lo, scope eth, type rw */
+#define reg_eth_rw_ma0_lo___addr___lsb 0
+#define reg_eth_rw_ma0_lo___addr___width 32
+#define reg_eth_rw_ma0_lo_offset 0
+
+/* Register rw_ma0_hi, scope eth, type rw */
+#define reg_eth_rw_ma0_hi___addr___lsb 0
+#define reg_eth_rw_ma0_hi___addr___width 16
+#define reg_eth_rw_ma0_hi_offset 4
+
+/* Register rw_ma1_lo, scope eth, type rw */
+#define reg_eth_rw_ma1_lo___addr___lsb 0
+#define reg_eth_rw_ma1_lo___addr___width 32
+#define reg_eth_rw_ma1_lo_offset 8
+
+/* Register rw_ma1_hi, scope eth, type rw */
+#define reg_eth_rw_ma1_hi___addr___lsb 0
+#define reg_eth_rw_ma1_hi___addr___width 16
+#define reg_eth_rw_ma1_hi_offset 12
+
+/* Register rw_ga_lo, scope eth, type rw */
+#define reg_eth_rw_ga_lo___table___lsb 0
+#define reg_eth_rw_ga_lo___table___width 32
+#define reg_eth_rw_ga_lo_offset 16
+
+/* Register rw_ga_hi, scope eth, type rw */
+#define reg_eth_rw_ga_hi___table___lsb 0
+#define reg_eth_rw_ga_hi___table___width 32
+#define reg_eth_rw_ga_hi_offset 20
+
+/* Register rw_gen_ctrl, scope eth, type rw */
+#define reg_eth_rw_gen_ctrl___en___lsb 0
+#define reg_eth_rw_gen_ctrl___en___width 1
+#define reg_eth_rw_gen_ctrl___en___bit 0
+#define reg_eth_rw_gen_ctrl___phy___lsb 1
+#define reg_eth_rw_gen_ctrl___phy___width 2
+#define reg_eth_rw_gen_ctrl___protocol___lsb 3
+#define reg_eth_rw_gen_ctrl___protocol___width 1
+#define reg_eth_rw_gen_ctrl___protocol___bit 3
+#define reg_eth_rw_gen_ctrl___loopback___lsb 4
+#define reg_eth_rw_gen_ctrl___loopback___width 1
+#define reg_eth_rw_gen_ctrl___loopback___bit 4
+#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___lsb 5
+#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___width 1
+#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___bit 5
+#define reg_eth_rw_gen_ctrl_offset 24
+
+/* Register rw_rec_ctrl, scope eth, type rw */
+#define reg_eth_rw_rec_ctrl___ma0___lsb 0
+#define reg_eth_rw_rec_ctrl___ma0___width 1
+#define reg_eth_rw_rec_ctrl___ma0___bit 0
+#define reg_eth_rw_rec_ctrl___ma1___lsb 1
+#define reg_eth_rw_rec_ctrl___ma1___width 1
+#define reg_eth_rw_rec_ctrl___ma1___bit 1
+#define reg_eth_rw_rec_ctrl___individual___lsb 2
+#define reg_eth_rw_rec_ctrl___individual___width 1
+#define reg_eth_rw_rec_ctrl___individual___bit 2
+#define reg_eth_rw_rec_ctrl___broadcast___lsb 3
+#define reg_eth_rw_rec_ctrl___broadcast___width 1
+#define reg_eth_rw_rec_ctrl___broadcast___bit 3
+#define reg_eth_rw_rec_ctrl___undersize___lsb 4
+#define reg_eth_rw_rec_ctrl___undersize___width 1
+#define reg_eth_rw_rec_ctrl___undersize___bit 4
+#define reg_eth_rw_rec_ctrl___oversize___lsb 5
+#define reg_eth_rw_rec_ctrl___oversize___width 1
+#define reg_eth_rw_rec_ctrl___oversize___bit 5
+#define reg_eth_rw_rec_ctrl___bad_crc___lsb 6
+#define reg_eth_rw_rec_ctrl___bad_crc___width 1
+#define reg_eth_rw_rec_ctrl___bad_crc___bit 6
+#define reg_eth_rw_rec_ctrl___duplex___lsb 7
+#define reg_eth_rw_rec_ctrl___duplex___width 1
+#define reg_eth_rw_rec_ctrl___duplex___bit 7
+#define reg_eth_rw_rec_ctrl___max_size___lsb 8
+#define reg_eth_rw_rec_ctrl___max_size___width 1
+#define reg_eth_rw_rec_ctrl___max_size___bit 8
+#define reg_eth_rw_rec_ctrl_offset 28
+
+/* Register rw_tr_ctrl, scope eth, type rw */
+#define reg_eth_rw_tr_ctrl___crc___lsb 0
+#define reg_eth_rw_tr_ctrl___crc___width 1
+#define reg_eth_rw_tr_ctrl___crc___bit 0
+#define reg_eth_rw_tr_ctrl___pad___lsb 1
+#define reg_eth_rw_tr_ctrl___pad___width 1
+#define reg_eth_rw_tr_ctrl___pad___bit 1
+#define reg_eth_rw_tr_ctrl___retry___lsb 2
+#define reg_eth_rw_tr_ctrl___retry___width 1
+#define reg_eth_rw_tr_ctrl___retry___bit 2
+#define reg_eth_rw_tr_ctrl___ignore_col___lsb 3
+#define reg_eth_rw_tr_ctrl___ignore_col___width 1
+#define reg_eth_rw_tr_ctrl___ignore_col___bit 3
+#define reg_eth_rw_tr_ctrl___cancel___lsb 4
+#define reg_eth_rw_tr_ctrl___cancel___width 1
+#define reg_eth_rw_tr_ctrl___cancel___bit 4
+#define reg_eth_rw_tr_ctrl___hsh_delay___lsb 5
+#define reg_eth_rw_tr_ctrl___hsh_delay___width 1
+#define reg_eth_rw_tr_ctrl___hsh_delay___bit 5
+#define reg_eth_rw_tr_ctrl___ignore_crs___lsb 6
+#define reg_eth_rw_tr_ctrl___ignore_crs___width 1
+#define reg_eth_rw_tr_ctrl___ignore_crs___bit 6
+#define reg_eth_rw_tr_ctrl_offset 32
+
+/* Register rw_clr_err, scope eth, type rw */
+#define reg_eth_rw_clr_err___clr___lsb 0
+#define reg_eth_rw_clr_err___clr___width 1
+#define reg_eth_rw_clr_err___clr___bit 0
+#define reg_eth_rw_clr_err_offset 36
+
+/* Register rw_mgm_ctrl, scope eth, type rw */
+#define reg_eth_rw_mgm_ctrl___mdio___lsb 0
+#define reg_eth_rw_mgm_ctrl___mdio___width 1
+#define reg_eth_rw_mgm_ctrl___mdio___bit 0
+#define reg_eth_rw_mgm_ctrl___mdoe___lsb 1
+#define reg_eth_rw_mgm_ctrl___mdoe___width 1
+#define reg_eth_rw_mgm_ctrl___mdoe___bit 1
+#define reg_eth_rw_mgm_ctrl___mdc___lsb 2
+#define reg_eth_rw_mgm_ctrl___mdc___width 1
+#define reg_eth_rw_mgm_ctrl___mdc___bit 2
+#define reg_eth_rw_mgm_ctrl___phyclk___lsb 3
+#define reg_eth_rw_mgm_ctrl___phyclk___width 1
+#define reg_eth_rw_mgm_ctrl___phyclk___bit 3
+#define reg_eth_rw_mgm_ctrl___txdata___lsb 4
+#define reg_eth_rw_mgm_ctrl___txdata___width 4
+#define reg_eth_rw_mgm_ctrl___txen___lsb 8
+#define reg_eth_rw_mgm_ctrl___txen___width 1
+#define reg_eth_rw_mgm_ctrl___txen___bit 8
+#define reg_eth_rw_mgm_ctrl_offset 40
+
+/* Register r_stat, scope eth, type r */
+#define reg_eth_r_stat___mdio___lsb 0
+#define reg_eth_r_stat___mdio___width 1
+#define reg_eth_r_stat___mdio___bit 0
+#define reg_eth_r_stat___exc_col___lsb 1
+#define reg_eth_r_stat___exc_col___width 1
+#define reg_eth_r_stat___exc_col___bit 1
+#define reg_eth_r_stat___urun___lsb 2
+#define reg_eth_r_stat___urun___width 1
+#define reg_eth_r_stat___urun___bit 2
+#define reg_eth_r_stat___phyclk___lsb 3
+#define reg_eth_r_stat___phyclk___width 1
+#define reg_eth_r_stat___phyclk___bit 3
+#define reg_eth_r_stat___txdata___lsb 4
+#define reg_eth_r_stat___txdata___width 4
+#define reg_eth_r_stat___txen___lsb 8
+#define reg_eth_r_stat___txen___width 1
+#define reg_eth_r_stat___txen___bit 8
+#define reg_eth_r_stat___col___lsb 9
+#define reg_eth_r_stat___col___width 1
+#define reg_eth_r_stat___col___bit 9
+#define reg_eth_r_stat___crs___lsb 10
+#define reg_eth_r_stat___crs___width 1
+#define reg_eth_r_stat___crs___bit 10
+#define reg_eth_r_stat___txclk___lsb 11
+#define reg_eth_r_stat___txclk___width 1
+#define reg_eth_r_stat___txclk___bit 11
+#define reg_eth_r_stat___rxdata___lsb 12
+#define reg_eth_r_stat___rxdata___width 4
+#define reg_eth_r_stat___rxer___lsb 16
+#define reg_eth_r_stat___rxer___width 1
+#define reg_eth_r_stat___rxer___bit 16
+#define reg_eth_r_stat___rxdv___lsb 17
+#define reg_eth_r_stat___rxdv___width 1
+#define reg_eth_r_stat___rxdv___bit 17
+#define reg_eth_r_stat___rxclk___lsb 18
+#define reg_eth_r_stat___rxclk___width 1
+#define reg_eth_r_stat___rxclk___bit 18
+#define reg_eth_r_stat_offset 44
+
+/* Register rs_rec_cnt, scope eth, type rs */
+#define reg_eth_rs_rec_cnt___crc_err___lsb 0
+#define reg_eth_rs_rec_cnt___crc_err___width 8
+#define reg_eth_rs_rec_cnt___align_err___lsb 8
+#define reg_eth_rs_rec_cnt___align_err___width 8
+#define reg_eth_rs_rec_cnt___oversize___lsb 16
+#define reg_eth_rs_rec_cnt___oversize___width 8
+#define reg_eth_rs_rec_cnt___congestion___lsb 24
+#define reg_eth_rs_rec_cnt___congestion___width 8
+#define reg_eth_rs_rec_cnt_offset 48
+
+/* Register r_rec_cnt, scope eth, type r */
+#define reg_eth_r_rec_cnt___crc_err___lsb 0
+#define reg_eth_r_rec_cnt___crc_err___width 8
+#define reg_eth_r_rec_cnt___align_err___lsb 8
+#define reg_eth_r_rec_cnt___align_err___width 8
+#define reg_eth_r_rec_cnt___oversize___lsb 16
+#define reg_eth_r_rec_cnt___oversize___width 8
+#define reg_eth_r_rec_cnt___congestion___lsb 24
+#define reg_eth_r_rec_cnt___congestion___width 8
+#define reg_eth_r_rec_cnt_offset 52
+
+/* Register rs_tr_cnt, scope eth, type rs */
+#define reg_eth_rs_tr_cnt___single_col___lsb 0
+#define reg_eth_rs_tr_cnt___single_col___width 8
+#define reg_eth_rs_tr_cnt___mult_col___lsb 8
+#define reg_eth_rs_tr_cnt___mult_col___width 8
+#define reg_eth_rs_tr_cnt___late_col___lsb 16
+#define reg_eth_rs_tr_cnt___late_col___width 8
+#define reg_eth_rs_tr_cnt___deferred___lsb 24
+#define reg_eth_rs_tr_cnt___deferred___width 8
+#define reg_eth_rs_tr_cnt_offset 56
+
+/* Register r_tr_cnt, scope eth, type r */
+#define reg_eth_r_tr_cnt___single_col___lsb 0
+#define reg_eth_r_tr_cnt___single_col___width 8
+#define reg_eth_r_tr_cnt___mult_col___lsb 8
+#define reg_eth_r_tr_cnt___mult_col___width 8
+#define reg_eth_r_tr_cnt___late_col___lsb 16
+#define reg_eth_r_tr_cnt___late_col___width 8
+#define reg_eth_r_tr_cnt___deferred___lsb 24
+#define reg_eth_r_tr_cnt___deferred___width 8
+#define reg_eth_r_tr_cnt_offset 60
+
+/* Register rs_phy_cnt, scope eth, type rs */
+#define reg_eth_rs_phy_cnt___carrier_loss___lsb 0
+#define reg_eth_rs_phy_cnt___carrier_loss___width 8
+#define reg_eth_rs_phy_cnt___sqe_err___lsb 8
+#define reg_eth_rs_phy_cnt___sqe_err___width 8
+#define reg_eth_rs_phy_cnt_offset 64
+
+/* Register r_phy_cnt, scope eth, type r */
+#define reg_eth_r_phy_cnt___carrier_loss___lsb 0
+#define reg_eth_r_phy_cnt___carrier_loss___width 8
+#define reg_eth_r_phy_cnt___sqe_err___lsb 8
+#define reg_eth_r_phy_cnt___sqe_err___width 8
+#define reg_eth_r_phy_cnt_offset 68
+
+/* Register rw_test_ctrl, scope eth, type rw */
+#define reg_eth_rw_test_ctrl___snmp_inc___lsb 0
+#define reg_eth_rw_test_ctrl___snmp_inc___width 1
+#define reg_eth_rw_test_ctrl___snmp_inc___bit 0
+#define reg_eth_rw_test_ctrl___snmp___lsb 1
+#define reg_eth_rw_test_ctrl___snmp___width 1
+#define reg_eth_rw_test_ctrl___snmp___bit 1
+#define reg_eth_rw_test_ctrl___backoff___lsb 2
+#define reg_eth_rw_test_ctrl___backoff___width 1
+#define reg_eth_rw_test_ctrl___backoff___bit 2
+#define reg_eth_rw_test_ctrl_offset 72
+
+/* Register rw_intr_mask, scope eth, type rw */
+#define reg_eth_rw_intr_mask___crc___lsb 0
+#define reg_eth_rw_intr_mask___crc___width 1
+#define reg_eth_rw_intr_mask___crc___bit 0
+#define reg_eth_rw_intr_mask___align___lsb 1
+#define reg_eth_rw_intr_mask___align___width 1
+#define reg_eth_rw_intr_mask___align___bit 1
+#define reg_eth_rw_intr_mask___oversize___lsb 2
+#define reg_eth_rw_intr_mask___oversize___width 1
+#define reg_eth_rw_intr_mask___oversize___bit 2
+#define reg_eth_rw_intr_mask___congestion___lsb 3
+#define reg_eth_rw_intr_mask___congestion___width 1
+#define reg_eth_rw_intr_mask___congestion___bit 3
+#define reg_eth_rw_intr_mask___single_col___lsb 4
+#define reg_eth_rw_intr_mask___single_col___width 1
+#define reg_eth_rw_intr_mask___single_col___bit 4
+#define reg_eth_rw_intr_mask___mult_col___lsb 5
+#define reg_eth_rw_intr_mask___mult_col___width 1
+#define reg_eth_rw_intr_mask___mult_col___bit 5
+#define reg_eth_rw_intr_mask___late_col___lsb 6
+#define reg_eth_rw_intr_mask___late_col___width 1
+#define reg_eth_rw_intr_mask___late_col___bit 6
+#define reg_eth_rw_intr_mask___deferred___lsb 7
+#define reg_eth_rw_intr_mask___deferred___width 1
+#define reg_eth_rw_intr_mask___deferred___bit 7
+#define reg_eth_rw_intr_mask___carrier_loss___lsb 8
+#define reg_eth_rw_intr_mask___carrier_loss___width 1
+#define reg_eth_rw_intr_mask___carrier_loss___bit 8
+#define reg_eth_rw_intr_mask___sqe_test_err___lsb 9
+#define reg_eth_rw_intr_mask___sqe_test_err___width 1
+#define reg_eth_rw_intr_mask___sqe_test_err___bit 9
+#define reg_eth_rw_intr_mask___orun___lsb 10
+#define reg_eth_rw_intr_mask___orun___width 1
+#define reg_eth_rw_intr_mask___orun___bit 10
+#define reg_eth_rw_intr_mask___urun___lsb 11
+#define reg_eth_rw_intr_mask___urun___width 1
+#define reg_eth_rw_intr_mask___urun___bit 11
+#define reg_eth_rw_intr_mask___excessive_col___lsb 12
+#define reg_eth_rw_intr_mask___excessive_col___width 1
+#define reg_eth_rw_intr_mask___excessive_col___bit 12
+#define reg_eth_rw_intr_mask___mdio___lsb 13
+#define reg_eth_rw_intr_mask___mdio___width 1
+#define reg_eth_rw_intr_mask___mdio___bit 13
+#define reg_eth_rw_intr_mask_offset 76
+
+/* Register rw_ack_intr, scope eth, type rw */
+#define reg_eth_rw_ack_intr___crc___lsb 0
+#define reg_eth_rw_ack_intr___crc___width 1
+#define reg_eth_rw_ack_intr___crc___bit 0
+#define reg_eth_rw_ack_intr___align___lsb 1
+#define reg_eth_rw_ack_intr___align___width 1
+#define reg_eth_rw_ack_intr___align___bit 1
+#define reg_eth_rw_ack_intr___oversize___lsb 2
+#define reg_eth_rw_ack_intr___oversize___width 1
+#define reg_eth_rw_ack_intr___oversize___bit 2
+#define reg_eth_rw_ack_intr___congestion___lsb 3
+#define reg_eth_rw_ack_intr___congestion___width 1
+#define reg_eth_rw_ack_intr___congestion___bit 3
+#define reg_eth_rw_ack_intr___single_col___lsb 4
+#define reg_eth_rw_ack_intr___single_col___width 1
+#define reg_eth_rw_ack_intr___single_col___bit 4
+#define reg_eth_rw_ack_intr___mult_col___lsb 5
+#define reg_eth_rw_ack_intr___mult_col___width 1
+#define reg_eth_rw_ack_intr___mult_col___bit 5
+#define reg_eth_rw_ack_intr___late_col___lsb 6
+#define reg_eth_rw_ack_intr___late_col___width 1
+#define reg_eth_rw_ack_intr___late_col___bit 6
+#define reg_eth_rw_ack_intr___deferred___lsb 7
+#define reg_eth_rw_ack_intr___deferred___width 1
+#define reg_eth_rw_ack_intr___deferred___bit 7
+#define reg_eth_rw_ack_intr___carrier_loss___lsb 8
+#define reg_eth_rw_ack_intr___carrier_loss___width 1
+#define reg_eth_rw_ack_intr___carrier_loss___bit 8
+#define reg_eth_rw_ack_intr___sqe_test_err___lsb 9
+#define reg_eth_rw_ack_intr___sqe_test_err___width 1
+#define reg_eth_rw_ack_intr___sqe_test_err___bit 9
+#define reg_eth_rw_ack_intr___orun___lsb 10
+#define reg_eth_rw_ack_intr___orun___width 1
+#define reg_eth_rw_ack_intr___orun___bit 10
+#define reg_eth_rw_ack_intr___urun___lsb 11
+#define reg_eth_rw_ack_intr___urun___width 1
+#define reg_eth_rw_ack_intr___urun___bit 11
+#define reg_eth_rw_ack_intr___excessive_col___lsb 12
+#define reg_eth_rw_ack_intr___excessive_col___width 1
+#define reg_eth_rw_ack_intr___excessive_col___bit 12
+#define reg_eth_rw_ack_intr___mdio___lsb 13
+#define reg_eth_rw_ack_intr___mdio___width 1
+#define reg_eth_rw_ack_intr___mdio___bit 13
+#define reg_eth_rw_ack_intr_offset 80
+
+/* Register r_intr, scope eth, type r */
+#define reg_eth_r_intr___crc___lsb 0
+#define reg_eth_r_intr___crc___width 1
+#define reg_eth_r_intr___crc___bit 0
+#define reg_eth_r_intr___align___lsb 1
+#define reg_eth_r_intr___align___width 1
+#define reg_eth_r_intr___align___bit 1
+#define reg_eth_r_intr___oversize___lsb 2
+#define reg_eth_r_intr___oversize___width 1
+#define reg_eth_r_intr___oversize___bit 2
+#define reg_eth_r_intr___congestion___lsb 3
+#define reg_eth_r_intr___congestion___width 1
+#define reg_eth_r_intr___congestion___bit 3
+#define reg_eth_r_intr___single_col___lsb 4
+#define reg_eth_r_intr___single_col___width 1
+#define reg_eth_r_intr___single_col___bit 4
+#define reg_eth_r_intr___mult_col___lsb 5
+#define reg_eth_r_intr___mult_col___width 1
+#define reg_eth_r_intr___mult_col___bit 5
+#define reg_eth_r_intr___late_col___lsb 6
+#define reg_eth_r_intr___late_col___width 1
+#define reg_eth_r_intr___late_col___bit 6
+#define reg_eth_r_intr___deferred___lsb 7
+#define reg_eth_r_intr___deferred___width 1
+#define reg_eth_r_intr___deferred___bit 7
+#define reg_eth_r_intr___carrier_loss___lsb 8
+#define reg_eth_r_intr___carrier_loss___width 1
+#define reg_eth_r_intr___carrier_loss___bit 8
+#define reg_eth_r_intr___sqe_test_err___lsb 9
+#define reg_eth_r_intr___sqe_test_err___width 1
+#define reg_eth_r_intr___sqe_test_err___bit 9
+#define reg_eth_r_intr___orun___lsb 10
+#define reg_eth_r_intr___orun___width 1
+#define reg_eth_r_intr___orun___bit 10
+#define reg_eth_r_intr___urun___lsb 11
+#define reg_eth_r_intr___urun___width 1
+#define reg_eth_r_intr___urun___bit 11
+#define reg_eth_r_intr___excessive_col___lsb 12
+#define reg_eth_r_intr___excessive_col___width 1
+#define reg_eth_r_intr___excessive_col___bit 12
+#define reg_eth_r_intr___mdio___lsb 13
+#define reg_eth_r_intr___mdio___width 1
+#define reg_eth_r_intr___mdio___bit 13
+#define reg_eth_r_intr_offset 84
+
+/* Register r_masked_intr, scope eth, type r */
+#define reg_eth_r_masked_intr___crc___lsb 0
+#define reg_eth_r_masked_intr___crc___width 1
+#define reg_eth_r_masked_intr___crc___bit 0
+#define reg_eth_r_masked_intr___align___lsb 1
+#define reg_eth_r_masked_intr___align___width 1
+#define reg_eth_r_masked_intr___align___bit 1
+#define reg_eth_r_masked_intr___oversize___lsb 2
+#define reg_eth_r_masked_intr___oversize___width 1
+#define reg_eth_r_masked_intr___oversize___bit 2
+#define reg_eth_r_masked_intr___congestion___lsb 3
+#define reg_eth_r_masked_intr___congestion___width 1
+#define reg_eth_r_masked_intr___congestion___bit 3
+#define reg_eth_r_masked_intr___single_col___lsb 4
+#define reg_eth_r_masked_intr___single_col___width 1
+#define reg_eth_r_masked_intr___single_col___bit 4
+#define reg_eth_r_masked_intr___mult_col___lsb 5
+#define reg_eth_r_masked_intr___mult_col___width 1
+#define reg_eth_r_masked_intr___mult_col___bit 5
+#define reg_eth_r_masked_intr___late_col___lsb 6
+#define reg_eth_r_masked_intr___late_col___width 1
+#define reg_eth_r_masked_intr___late_col___bit 6
+#define reg_eth_r_masked_intr___deferred___lsb 7
+#define reg_eth_r_masked_intr___deferred___width 1
+#define reg_eth_r_masked_intr___deferred___bit 7
+#define reg_eth_r_masked_intr___carrier_loss___lsb 8
+#define reg_eth_r_masked_intr___carrier_loss___width 1
+#define reg_eth_r_masked_intr___carrier_loss___bit 8
+#define reg_eth_r_masked_intr___sqe_test_err___lsb 9
+#define reg_eth_r_masked_intr___sqe_test_err___width 1
+#define reg_eth_r_masked_intr___sqe_test_err___bit 9
+#define reg_eth_r_masked_intr___orun___lsb 10
+#define reg_eth_r_masked_intr___orun___width 1
+#define reg_eth_r_masked_intr___orun___bit 10
+#define reg_eth_r_masked_intr___urun___lsb 11
+#define reg_eth_r_masked_intr___urun___width 1
+#define reg_eth_r_masked_intr___urun___bit 11
+#define reg_eth_r_masked_intr___excessive_col___lsb 12
+#define reg_eth_r_masked_intr___excessive_col___width 1
+#define reg_eth_r_masked_intr___excessive_col___bit 12
+#define reg_eth_r_masked_intr___mdio___lsb 13
+#define reg_eth_r_masked_intr___mdio___width 1
+#define reg_eth_r_masked_intr___mdio___bit 13
+#define reg_eth_r_masked_intr_offset 88
+
+
+/* Constants */
+#define regk_eth_discard                          0x00000000
+#define regk_eth_ether                            0x00000000
+#define regk_eth_full                             0x00000001
+#define regk_eth_half                             0x00000000
+#define regk_eth_hsh                              0x00000001
+#define regk_eth_mii                              0x00000001
+#define regk_eth_mii_clk                          0x00000000
+#define regk_eth_mii_rec                          0x00000002
+#define regk_eth_no                               0x00000000
+#define regk_eth_rec                              0x00000001
+#define regk_eth_rw_ga_hi_default                 0x00000000
+#define regk_eth_rw_ga_lo_default                 0x00000000
+#define regk_eth_rw_gen_ctrl_default              0x00000000
+#define regk_eth_rw_intr_mask_default             0x00000000
+#define regk_eth_rw_ma0_hi_default                0x00000000
+#define regk_eth_rw_ma0_lo_default                0x00000000
+#define regk_eth_rw_ma1_hi_default                0x00000000
+#define regk_eth_rw_ma1_lo_default                0x00000000
+#define regk_eth_rw_mgm_ctrl_default              0x00000000
+#define regk_eth_rw_test_ctrl_default             0x00000000
+#define regk_eth_size1518                         0x00000000
+#define regk_eth_size1522                         0x00000001
+#define regk_eth_yes                              0x00000001
+#endif /* __eth_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h
new file mode 100644
index 00000000000..35356bc0862
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/gio_defs_asm.h
@@ -0,0 +1,276 @@
+#ifndef __gio_defs_asm_h
+#define __gio_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/gio/rtl/gio_regs.r
+ *     id:           gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
+ *     last modfied: Mon Apr 11 16:07:47 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r
+ *      id: $Id: gio_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_pa_dout, scope gio, type rw */
+#define reg_gio_rw_pa_dout___data___lsb 0
+#define reg_gio_rw_pa_dout___data___width 8
+#define reg_gio_rw_pa_dout_offset 0
+
+/* Register r_pa_din, scope gio, type r */
+#define reg_gio_r_pa_din___data___lsb 0
+#define reg_gio_r_pa_din___data___width 8
+#define reg_gio_r_pa_din_offset 4
+
+/* Register rw_pa_oe, scope gio, type rw */
+#define reg_gio_rw_pa_oe___oe___lsb 0
+#define reg_gio_rw_pa_oe___oe___width 8
+#define reg_gio_rw_pa_oe_offset 8
+
+/* Register rw_intr_cfg, scope gio, type rw */
+#define reg_gio_rw_intr_cfg___pa0___lsb 0
+#define reg_gio_rw_intr_cfg___pa0___width 3
+#define reg_gio_rw_intr_cfg___pa1___lsb 3
+#define reg_gio_rw_intr_cfg___pa1___width 3
+#define reg_gio_rw_intr_cfg___pa2___lsb 6
+#define reg_gio_rw_intr_cfg___pa2___width 3
+#define reg_gio_rw_intr_cfg___pa3___lsb 9
+#define reg_gio_rw_intr_cfg___pa3___width 3
+#define reg_gio_rw_intr_cfg___pa4___lsb 12
+#define reg_gio_rw_intr_cfg___pa4___width 3
+#define reg_gio_rw_intr_cfg___pa5___lsb 15
+#define reg_gio_rw_intr_cfg___pa5___width 3
+#define reg_gio_rw_intr_cfg___pa6___lsb 18
+#define reg_gio_rw_intr_cfg___pa6___width 3
+#define reg_gio_rw_intr_cfg___pa7___lsb 21
+#define reg_gio_rw_intr_cfg___pa7___width 3
+#define reg_gio_rw_intr_cfg_offset 12
+
+/* Register rw_intr_mask, scope gio, type rw */
+#define reg_gio_rw_intr_mask___pa0___lsb 0
+#define reg_gio_rw_intr_mask___pa0___width 1
+#define reg_gio_rw_intr_mask___pa0___bit 0
+#define reg_gio_rw_intr_mask___pa1___lsb 1
+#define reg_gio_rw_intr_mask___pa1___width 1
+#define reg_gio_rw_intr_mask___pa1___bit 1
+#define reg_gio_rw_intr_mask___pa2___lsb 2
+#define reg_gio_rw_intr_mask___pa2___width 1
+#define reg_gio_rw_intr_mask___pa2___bit 2
+#define reg_gio_rw_intr_mask___pa3___lsb 3
+#define reg_gio_rw_intr_mask___pa3___width 1
+#define reg_gio_rw_intr_mask___pa3___bit 3
+#define reg_gio_rw_intr_mask___pa4___lsb 4
+#define reg_gio_rw_intr_mask___pa4___width 1
+#define reg_gio_rw_intr_mask___pa4___bit 4
+#define reg_gio_rw_intr_mask___pa5___lsb 5
+#define reg_gio_rw_intr_mask___pa5___width 1
+#define reg_gio_rw_intr_mask___pa5___bit 5
+#define reg_gio_rw_intr_mask___pa6___lsb 6
+#define reg_gio_rw_intr_mask___pa6___width 1
+#define reg_gio_rw_intr_mask___pa6___bit 6
+#define reg_gio_rw_intr_mask___pa7___lsb 7
+#define reg_gio_rw_intr_mask___pa7___width 1
+#define reg_gio_rw_intr_mask___pa7___bit 7
+#define reg_gio_rw_intr_mask_offset 16
+
+/* Register rw_ack_intr, scope gio, type rw */
+#define reg_gio_rw_ack_intr___pa0___lsb 0
+#define reg_gio_rw_ack_intr___pa0___width 1
+#define reg_gio_rw_ack_intr___pa0___bit 0
+#define reg_gio_rw_ack_intr___pa1___lsb 1
+#define reg_gio_rw_ack_intr___pa1___width 1
+#define reg_gio_rw_ack_intr___pa1___bit 1
+#define reg_gio_rw_ack_intr___pa2___lsb 2
+#define reg_gio_rw_ack_intr___pa2___width 1
+#define reg_gio_rw_ack_intr___pa2___bit 2
+#define reg_gio_rw_ack_intr___pa3___lsb 3
+#define reg_gio_rw_ack_intr___pa3___width 1
+#define reg_gio_rw_ack_intr___pa3___bit 3
+#define reg_gio_rw_ack_intr___pa4___lsb 4
+#define reg_gio_rw_ack_intr___pa4___width 1
+#define reg_gio_rw_ack_intr___pa4___bit 4
+#define reg_gio_rw_ack_intr___pa5___lsb 5
+#define reg_gio_rw_ack_intr___pa5___width 1
+#define reg_gio_rw_ack_intr___pa5___bit 5
+#define reg_gio_rw_ack_intr___pa6___lsb 6
+#define reg_gio_rw_ack_intr___pa6___width 1
+#define reg_gio_rw_ack_intr___pa6___bit 6
+#define reg_gio_rw_ack_intr___pa7___lsb 7
+#define reg_gio_rw_ack_intr___pa7___width 1
+#define reg_gio_rw_ack_intr___pa7___bit 7
+#define reg_gio_rw_ack_intr_offset 20
+
+/* Register r_intr, scope gio, type r */
+#define reg_gio_r_intr___pa0___lsb 0
+#define reg_gio_r_intr___pa0___width 1
+#define reg_gio_r_intr___pa0___bit 0
+#define reg_gio_r_intr___pa1___lsb 1
+#define reg_gio_r_intr___pa1___width 1
+#define reg_gio_r_intr___pa1___bit 1
+#define reg_gio_r_intr___pa2___lsb 2
+#define reg_gio_r_intr___pa2___width 1
+#define reg_gio_r_intr___pa2___bit 2
+#define reg_gio_r_intr___pa3___lsb 3
+#define reg_gio_r_intr___pa3___width 1
+#define reg_gio_r_intr___pa3___bit 3
+#define reg_gio_r_intr___pa4___lsb 4
+#define reg_gio_r_intr___pa4___width 1
+#define reg_gio_r_intr___pa4___bit 4
+#define reg_gio_r_intr___pa5___lsb 5
+#define reg_gio_r_intr___pa5___width 1
+#define reg_gio_r_intr___pa5___bit 5
+#define reg_gio_r_intr___pa6___lsb 6
+#define reg_gio_r_intr___pa6___width 1
+#define reg_gio_r_intr___pa6___bit 6
+#define reg_gio_r_intr___pa7___lsb 7
+#define reg_gio_r_intr___pa7___width 1
+#define reg_gio_r_intr___pa7___bit 7
+#define reg_gio_r_intr_offset 24
+
+/* Register r_masked_intr, scope gio, type r */
+#define reg_gio_r_masked_intr___pa0___lsb 0
+#define reg_gio_r_masked_intr___pa0___width 1
+#define reg_gio_r_masked_intr___pa0___bit 0
+#define reg_gio_r_masked_intr___pa1___lsb 1
+#define reg_gio_r_masked_intr___pa1___width 1
+#define reg_gio_r_masked_intr___pa1___bit 1
+#define reg_gio_r_masked_intr___pa2___lsb 2
+#define reg_gio_r_masked_intr___pa2___width 1
+#define reg_gio_r_masked_intr___pa2___bit 2
+#define reg_gio_r_masked_intr___pa3___lsb 3
+#define reg_gio_r_masked_intr___pa3___width 1
+#define reg_gio_r_masked_intr___pa3___bit 3
+#define reg_gio_r_masked_intr___pa4___lsb 4
+#define reg_gio_r_masked_intr___pa4___width 1
+#define reg_gio_r_masked_intr___pa4___bit 4
+#define reg_gio_r_masked_intr___pa5___lsb 5
+#define reg_gio_r_masked_intr___pa5___width 1
+#define reg_gio_r_masked_intr___pa5___bit 5
+#define reg_gio_r_masked_intr___pa6___lsb 6
+#define reg_gio_r_masked_intr___pa6___width 1
+#define reg_gio_r_masked_intr___pa6___bit 6
+#define reg_gio_r_masked_intr___pa7___lsb 7
+#define reg_gio_r_masked_intr___pa7___width 1
+#define reg_gio_r_masked_intr___pa7___bit 7
+#define reg_gio_r_masked_intr_offset 28
+
+/* Register rw_pb_dout, scope gio, type rw */
+#define reg_gio_rw_pb_dout___data___lsb 0
+#define reg_gio_rw_pb_dout___data___width 18
+#define reg_gio_rw_pb_dout_offset 32
+
+/* Register r_pb_din, scope gio, type r */
+#define reg_gio_r_pb_din___data___lsb 0
+#define reg_gio_r_pb_din___data___width 18
+#define reg_gio_r_pb_din_offset 36
+
+/* Register rw_pb_oe, scope gio, type rw */
+#define reg_gio_rw_pb_oe___oe___lsb 0
+#define reg_gio_rw_pb_oe___oe___width 18
+#define reg_gio_rw_pb_oe_offset 40
+
+/* Register rw_pc_dout, scope gio, type rw */
+#define reg_gio_rw_pc_dout___data___lsb 0
+#define reg_gio_rw_pc_dout___data___width 18
+#define reg_gio_rw_pc_dout_offset 48
+
+/* Register r_pc_din, scope gio, type r */
+#define reg_gio_r_pc_din___data___lsb 0
+#define reg_gio_r_pc_din___data___width 18
+#define reg_gio_r_pc_din_offset 52
+
+/* Register rw_pc_oe, scope gio, type rw */
+#define reg_gio_rw_pc_oe___oe___lsb 0
+#define reg_gio_rw_pc_oe___oe___width 18
+#define reg_gio_rw_pc_oe_offset 56
+
+/* Register rw_pd_dout, scope gio, type rw */
+#define reg_gio_rw_pd_dout___data___lsb 0
+#define reg_gio_rw_pd_dout___data___width 18
+#define reg_gio_rw_pd_dout_offset 64
+
+/* Register r_pd_din, scope gio, type r */
+#define reg_gio_r_pd_din___data___lsb 0
+#define reg_gio_r_pd_din___data___width 18
+#define reg_gio_r_pd_din_offset 68
+
+/* Register rw_pd_oe, scope gio, type rw */
+#define reg_gio_rw_pd_oe___oe___lsb 0
+#define reg_gio_rw_pd_oe___oe___width 18
+#define reg_gio_rw_pd_oe_offset 72
+
+/* Register rw_pe_dout, scope gio, type rw */
+#define reg_gio_rw_pe_dout___data___lsb 0
+#define reg_gio_rw_pe_dout___data___width 18
+#define reg_gio_rw_pe_dout_offset 80
+
+/* Register r_pe_din, scope gio, type r */
+#define reg_gio_r_pe_din___data___lsb 0
+#define reg_gio_r_pe_din___data___width 18
+#define reg_gio_r_pe_din_offset 84
+
+/* Register rw_pe_oe, scope gio, type rw */
+#define reg_gio_rw_pe_oe___oe___lsb 0
+#define reg_gio_rw_pe_oe___oe___width 18
+#define reg_gio_rw_pe_oe_offset 88
+
+
+/* Constants */
+#define regk_gio_anyedge                          0x00000007
+#define regk_gio_hi                               0x00000001
+#define regk_gio_lo                               0x00000002
+#define regk_gio_negedge                          0x00000006
+#define regk_gio_no                               0x00000000
+#define regk_gio_off                              0x00000000
+#define regk_gio_posedge                          0x00000005
+#define regk_gio_rw_intr_cfg_default              0x00000000
+#define regk_gio_rw_intr_mask_default             0x00000000
+#define regk_gio_rw_pa_oe_default                 0x00000000
+#define regk_gio_rw_pb_oe_default                 0x00000000
+#define regk_gio_rw_pc_oe_default                 0x00000000
+#define regk_gio_rw_pd_oe_default                 0x00000000
+#define regk_gio_rw_pe_oe_default                 0x00000000
+#define regk_gio_set                              0x00000003
+#define regk_gio_yes                              0x00000001
+#endif /* __gio_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h b/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h
new file mode 100644
index 00000000000..c8315905c57
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/intr_vect.h
@@ -0,0 +1,38 @@
+/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
+ from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
+version . */
+
+#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
+#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
+#define MEMARB_INTR_VECT	0x31
+#define GEN_IO_INTR_VECT	0x32
+#define IOP0_INTR_VECT	0x33
+#define IOP1_INTR_VECT	0x34
+#define IOP2_INTR_VECT	0x35
+#define IOP3_INTR_VECT	0x36
+#define DMA0_INTR_VECT	0x37
+#define DMA1_INTR_VECT	0x38
+#define DMA2_INTR_VECT	0x39
+#define DMA3_INTR_VECT	0x3a
+#define DMA4_INTR_VECT	0x3b
+#define DMA5_INTR_VECT	0x3c
+#define DMA6_INTR_VECT	0x3d
+#define DMA7_INTR_VECT	0x3e
+#define DMA8_INTR_VECT	0x3f
+#define DMA9_INTR_VECT	0x40
+#define ATA_INTR_VECT	0x41
+#define SSER0_INTR_VECT	0x42
+#define SSER1_INTR_VECT	0x43
+#define SER0_INTR_VECT	0x44
+#define SER1_INTR_VECT	0x45
+#define SER2_INTR_VECT	0x46
+#define SER3_INTR_VECT	0x47
+#define P21_INTR_VECT	0x48
+#define ETH0_INTR_VECT	0x49
+#define ETH1_INTR_VECT	0x4a
+#define TIMER_INTR_VECT	0x4b
+#define BIF_ARB_INTR_VECT	0x4c
+#define BIF_DMA_INTR_VECT	0x4d
+#define EXT_INTR_VECT	0x4e
+
+#endif
diff --git a/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h
new file mode 100644
index 00000000000..6df2a433b02
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/intr_vect_defs_asm.h
@@ -0,0 +1,355 @@
+#ifndef __intr_vect_defs_asm_h
+#define __intr_vect_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/intr_vect/rtl/guinness/ivmask.config.r
+ *     id:           ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp
+ *     last modfied: Mon Apr 11 16:08:03 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/intr_vect_defs_asm.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
+ *      id: $Id: intr_vect_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_mask, scope intr_vect, type rw */
+#define reg_intr_vect_rw_mask___memarb___lsb 0
+#define reg_intr_vect_rw_mask___memarb___width 1
+#define reg_intr_vect_rw_mask___memarb___bit 0
+#define reg_intr_vect_rw_mask___gen_io___lsb 1
+#define reg_intr_vect_rw_mask___gen_io___width 1
+#define reg_intr_vect_rw_mask___gen_io___bit 1
+#define reg_intr_vect_rw_mask___iop0___lsb 2
+#define reg_intr_vect_rw_mask___iop0___width 1
+#define reg_intr_vect_rw_mask___iop0___bit 2
+#define reg_intr_vect_rw_mask___iop1___lsb 3
+#define reg_intr_vect_rw_mask___iop1___width 1
+#define reg_intr_vect_rw_mask___iop1___bit 3
+#define reg_intr_vect_rw_mask___iop2___lsb 4
+#define reg_intr_vect_rw_mask___iop2___width 1
+#define reg_intr_vect_rw_mask___iop2___bit 4
+#define reg_intr_vect_rw_mask___iop3___lsb 5
+#define reg_intr_vect_rw_mask___iop3___width 1
+#define reg_intr_vect_rw_mask___iop3___bit 5
+#define reg_intr_vect_rw_mask___dma0___lsb 6
+#define reg_intr_vect_rw_mask___dma0___width 1
+#define reg_intr_vect_rw_mask___dma0___bit 6
+#define reg_intr_vect_rw_mask___dma1___lsb 7
+#define reg_intr_vect_rw_mask___dma1___width 1
+#define reg_intr_vect_rw_mask___dma1___bit 7
+#define reg_intr_vect_rw_mask___dma2___lsb 8
+#define reg_intr_vect_rw_mask___dma2___width 1
+#define reg_intr_vect_rw_mask___dma2___bit 8
+#define reg_intr_vect_rw_mask___dma3___lsb 9
+#define reg_intr_vect_rw_mask___dma3___width 1
+#define reg_intr_vect_rw_mask___dma3___bit 9
+#define reg_intr_vect_rw_mask___dma4___lsb 10
+#define reg_intr_vect_rw_mask___dma4___width 1
+#define reg_intr_vect_rw_mask___dma4___bit 10
+#define reg_intr_vect_rw_mask___dma5___lsb 11
+#define reg_intr_vect_rw_mask___dma5___width 1
+#define reg_intr_vect_rw_mask___dma5___bit 11
+#define reg_intr_vect_rw_mask___dma6___lsb 12
+#define reg_intr_vect_rw_mask___dma6___width 1
+#define reg_intr_vect_rw_mask___dma6___bit 12
+#define reg_intr_vect_rw_mask___dma7___lsb 13
+#define reg_intr_vect_rw_mask___dma7___width 1
+#define reg_intr_vect_rw_mask___dma7___bit 13
+#define reg_intr_vect_rw_mask___dma8___lsb 14
+#define reg_intr_vect_rw_mask___dma8___width 1
+#define reg_intr_vect_rw_mask___dma8___bit 14
+#define reg_intr_vect_rw_mask___dma9___lsb 15
+#define reg_intr_vect_rw_mask___dma9___width 1
+#define reg_intr_vect_rw_mask___dma9___bit 15
+#define reg_intr_vect_rw_mask___ata___lsb 16
+#define reg_intr_vect_rw_mask___ata___width 1
+#define reg_intr_vect_rw_mask___ata___bit 16
+#define reg_intr_vect_rw_mask___sser0___lsb 17
+#define reg_intr_vect_rw_mask___sser0___width 1
+#define reg_intr_vect_rw_mask___sser0___bit 17
+#define reg_intr_vect_rw_mask___sser1___lsb 18
+#define reg_intr_vect_rw_mask___sser1___width 1
+#define reg_intr_vect_rw_mask___sser1___bit 18
+#define reg_intr_vect_rw_mask___ser0___lsb 19
+#define reg_intr_vect_rw_mask___ser0___width 1
+#define reg_intr_vect_rw_mask___ser0___bit 19
+#define reg_intr_vect_rw_mask___ser1___lsb 20
+#define reg_intr_vect_rw_mask___ser1___width 1
+#define reg_intr_vect_rw_mask___ser1___bit 20
+#define reg_intr_vect_rw_mask___ser2___lsb 21
+#define reg_intr_vect_rw_mask___ser2___width 1
+#define reg_intr_vect_rw_mask___ser2___bit 21
+#define reg_intr_vect_rw_mask___ser3___lsb 22
+#define reg_intr_vect_rw_mask___ser3___width 1
+#define reg_intr_vect_rw_mask___ser3___bit 22
+#define reg_intr_vect_rw_mask___p21___lsb 23
+#define reg_intr_vect_rw_mask___p21___width 1
+#define reg_intr_vect_rw_mask___p21___bit 23
+#define reg_intr_vect_rw_mask___eth0___lsb 24
+#define reg_intr_vect_rw_mask___eth0___width 1
+#define reg_intr_vect_rw_mask___eth0___bit 24
+#define reg_intr_vect_rw_mask___eth1___lsb 25
+#define reg_intr_vect_rw_mask___eth1___width 1
+#define reg_intr_vect_rw_mask___eth1___bit 25
+#define reg_intr_vect_rw_mask___timer___lsb 26
+#define reg_intr_vect_rw_mask___timer___width 1
+#define reg_intr_vect_rw_mask___timer___bit 26
+#define reg_intr_vect_rw_mask___bif_arb___lsb 27
+#define reg_intr_vect_rw_mask___bif_arb___width 1
+#define reg_intr_vect_rw_mask___bif_arb___bit 27
+#define reg_intr_vect_rw_mask___bif_dma___lsb 28
+#define reg_intr_vect_rw_mask___bif_dma___width 1
+#define reg_intr_vect_rw_mask___bif_dma___bit 28
+#define reg_intr_vect_rw_mask___ext___lsb 29
+#define reg_intr_vect_rw_mask___ext___width 1
+#define reg_intr_vect_rw_mask___ext___bit 29
+#define reg_intr_vect_rw_mask_offset 0
+
+/* Register r_vect, scope intr_vect, type r */
+#define reg_intr_vect_r_vect___memarb___lsb 0
+#define reg_intr_vect_r_vect___memarb___width 1
+#define reg_intr_vect_r_vect___memarb___bit 0
+#define reg_intr_vect_r_vect___gen_io___lsb 1
+#define reg_intr_vect_r_vect___gen_io___width 1
+#define reg_intr_vect_r_vect___gen_io___bit 1
+#define reg_intr_vect_r_vect___iop0___lsb 2
+#define reg_intr_vect_r_vect___iop0___width 1
+#define reg_intr_vect_r_vect___iop0___bit 2
+#define reg_intr_vect_r_vect___iop1___lsb 3
+#define reg_intr_vect_r_vect___iop1___width 1
+#define reg_intr_vect_r_vect___iop1___bit 3
+#define reg_intr_vect_r_vect___iop2___lsb 4
+#define reg_intr_vect_r_vect___iop2___width 1
+#define reg_intr_vect_r_vect___iop2___bit 4
+#define reg_intr_vect_r_vect___iop3___lsb 5
+#define reg_intr_vect_r_vect___iop3___width 1
+#define reg_intr_vect_r_vect___iop3___bit 5
+#define reg_intr_vect_r_vect___dma0___lsb 6
+#define reg_intr_vect_r_vect___dma0___width 1
+#define reg_intr_vect_r_vect___dma0___bit 6
+#define reg_intr_vect_r_vect___dma1___lsb 7
+#define reg_intr_vect_r_vect___dma1___width 1
+#define reg_intr_vect_r_vect___dma1___bit 7
+#define reg_intr_vect_r_vect___dma2___lsb 8
+#define reg_intr_vect_r_vect___dma2___width 1
+#define reg_intr_vect_r_vect___dma2___bit 8
+#define reg_intr_vect_r_vect___dma3___lsb 9
+#define reg_intr_vect_r_vect___dma3___width 1
+#define reg_intr_vect_r_vect___dma3___bit 9
+#define reg_intr_vect_r_vect___dma4___lsb 10
+#define reg_intr_vect_r_vect___dma4___width 1
+#define reg_intr_vect_r_vect___dma4___bit 10
+#define reg_intr_vect_r_vect___dma5___lsb 11
+#define reg_intr_vect_r_vect___dma5___width 1
+#define reg_intr_vect_r_vect___dma5___bit 11
+#define reg_intr_vect_r_vect___dma6___lsb 12
+#define reg_intr_vect_r_vect___dma6___width 1
+#define reg_intr_vect_r_vect___dma6___bit 12
+#define reg_intr_vect_r_vect___dma7___lsb 13
+#define reg_intr_vect_r_vect___dma7___width 1
+#define reg_intr_vect_r_vect___dma7___bit 13
+#define reg_intr_vect_r_vect___dma8___lsb 14
+#define reg_intr_vect_r_vect___dma8___width 1
+#define reg_intr_vect_r_vect___dma8___bit 14
+#define reg_intr_vect_r_vect___dma9___lsb 15
+#define reg_intr_vect_r_vect___dma9___width 1
+#define reg_intr_vect_r_vect___dma9___bit 15
+#define reg_intr_vect_r_vect___ata___lsb 16
+#define reg_intr_vect_r_vect___ata___width 1
+#define reg_intr_vect_r_vect___ata___bit 16
+#define reg_intr_vect_r_vect___sser0___lsb 17
+#define reg_intr_vect_r_vect___sser0___width 1
+#define reg_intr_vect_r_vect___sser0___bit 17
+#define reg_intr_vect_r_vect___sser1___lsb 18
+#define reg_intr_vect_r_vect___sser1___width 1
+#define reg_intr_vect_r_vect___sser1___bit 18
+#define reg_intr_vect_r_vect___ser0___lsb 19
+#define reg_intr_vect_r_vect___ser0___width 1
+#define reg_intr_vect_r_vect___ser0___bit 19
+#define reg_intr_vect_r_vect___ser1___lsb 20
+#define reg_intr_vect_r_vect___ser1___width 1
+#define reg_intr_vect_r_vect___ser1___bit 20
+#define reg_intr_vect_r_vect___ser2___lsb 21
+#define reg_intr_vect_r_vect___ser2___width 1
+#define reg_intr_vect_r_vect___ser2___bit 21
+#define reg_intr_vect_r_vect___ser3___lsb 22
+#define reg_intr_vect_r_vect___ser3___width 1
+#define reg_intr_vect_r_vect___ser3___bit 22
+#define reg_intr_vect_r_vect___p21___lsb 23
+#define reg_intr_vect_r_vect___p21___width 1
+#define reg_intr_vect_r_vect___p21___bit 23
+#define reg_intr_vect_r_vect___eth0___lsb 24
+#define reg_intr_vect_r_vect___eth0___width 1
+#define reg_intr_vect_r_vect___eth0___bit 24
+#define reg_intr_vect_r_vect___eth1___lsb 25
+#define reg_intr_vect_r_vect___eth1___width 1
+#define reg_intr_vect_r_vect___eth1___bit 25
+#define reg_intr_vect_r_vect___timer___lsb 26
+#define reg_intr_vect_r_vect___timer___width 1
+#define reg_intr_vect_r_vect___timer___bit 26
+#define reg_intr_vect_r_vect___bif_arb___lsb 27
+#define reg_intr_vect_r_vect___bif_arb___width 1
+#define reg_intr_vect_r_vect___bif_arb___bit 27
+#define reg_intr_vect_r_vect___bif_dma___lsb 28
+#define reg_intr_vect_r_vect___bif_dma___width 1
+#define reg_intr_vect_r_vect___bif_dma___bit 28
+#define reg_intr_vect_r_vect___ext___lsb 29
+#define reg_intr_vect_r_vect___ext___width 1
+#define reg_intr_vect_r_vect___ext___bit 29
+#define reg_intr_vect_r_vect_offset 4
+
+/* Register r_masked_vect, scope intr_vect, type r */
+#define reg_intr_vect_r_masked_vect___memarb___lsb 0
+#define reg_intr_vect_r_masked_vect___memarb___width 1
+#define reg_intr_vect_r_masked_vect___memarb___bit 0
+#define reg_intr_vect_r_masked_vect___gen_io___lsb 1
+#define reg_intr_vect_r_masked_vect___gen_io___width 1
+#define reg_intr_vect_r_masked_vect___gen_io___bit 1
+#define reg_intr_vect_r_masked_vect___iop0___lsb 2
+#define reg_intr_vect_r_masked_vect___iop0___width 1
+#define reg_intr_vect_r_masked_vect___iop0___bit 2
+#define reg_intr_vect_r_masked_vect___iop1___lsb 3
+#define reg_intr_vect_r_masked_vect___iop1___width 1
+#define reg_intr_vect_r_masked_vect___iop1___bit 3
+#define reg_intr_vect_r_masked_vect___iop2___lsb 4
+#define reg_intr_vect_r_masked_vect___iop2___width 1
+#define reg_intr_vect_r_masked_vect___iop2___bit 4
+#define reg_intr_vect_r_masked_vect___iop3___lsb 5
+#define reg_intr_vect_r_masked_vect___iop3___width 1
+#define reg_intr_vect_r_masked_vect___iop3___bit 5
+#define reg_intr_vect_r_masked_vect___dma0___lsb 6
+#define reg_intr_vect_r_masked_vect___dma0___width 1
+#define reg_intr_vect_r_masked_vect___dma0___bit 6
+#define reg_intr_vect_r_masked_vect___dma1___lsb 7
+#define reg_intr_vect_r_masked_vect___dma1___width 1
+#define reg_intr_vect_r_masked_vect___dma1___bit 7
+#define reg_intr_vect_r_masked_vect___dma2___lsb 8
+#define reg_intr_vect_r_masked_vect___dma2___width 1
+#define reg_intr_vect_r_masked_vect___dma2___bit 8
+#define reg_intr_vect_r_masked_vect___dma3___lsb 9
+#define reg_intr_vect_r_masked_vect___dma3___width 1
+#define reg_intr_vect_r_masked_vect___dma3___bit 9
+#define reg_intr_vect_r_masked_vect___dma4___lsb 10
+#define reg_intr_vect_r_masked_vect___dma4___width 1
+#define reg_intr_vect_r_masked_vect___dma4___bit 10
+#define reg_intr_vect_r_masked_vect___dma5___lsb 11
+#define reg_intr_vect_r_masked_vect___dma5___width 1
+#define reg_intr_vect_r_masked_vect___dma5___bit 11
+#define reg_intr_vect_r_masked_vect___dma6___lsb 12
+#define reg_intr_vect_r_masked_vect___dma6___width 1
+#define reg_intr_vect_r_masked_vect___dma6___bit 12
+#define reg_intr_vect_r_masked_vect___dma7___lsb 13
+#define reg_intr_vect_r_masked_vect___dma7___width 1
+#define reg_intr_vect_r_masked_vect___dma7___bit 13
+#define reg_intr_vect_r_masked_vect___dma8___lsb 14
+#define reg_intr_vect_r_masked_vect___dma8___width 1
+#define reg_intr_vect_r_masked_vect___dma8___bit 14
+#define reg_intr_vect_r_masked_vect___dma9___lsb 15
+#define reg_intr_vect_r_masked_vect___dma9___width 1
+#define reg_intr_vect_r_masked_vect___dma9___bit 15
+#define reg_intr_vect_r_masked_vect___ata___lsb 16
+#define reg_intr_vect_r_masked_vect___ata___width 1
+#define reg_intr_vect_r_masked_vect___ata___bit 16
+#define reg_intr_vect_r_masked_vect___sser0___lsb 17
+#define reg_intr_vect_r_masked_vect___sser0___width 1
+#define reg_intr_vect_r_masked_vect___sser0___bit 17
+#define reg_intr_vect_r_masked_vect___sser1___lsb 18
+#define reg_intr_vect_r_masked_vect___sser1___width 1
+#define reg_intr_vect_r_masked_vect___sser1___bit 18
+#define reg_intr_vect_r_masked_vect___ser0___lsb 19
+#define reg_intr_vect_r_masked_vect___ser0___width 1
+#define reg_intr_vect_r_masked_vect___ser0___bit 19
+#define reg_intr_vect_r_masked_vect___ser1___lsb 20
+#define reg_intr_vect_r_masked_vect___ser1___width 1
+#define reg_intr_vect_r_masked_vect___ser1___bit 20
+#define reg_intr_vect_r_masked_vect___ser2___lsb 21
+#define reg_intr_vect_r_masked_vect___ser2___width 1
+#define reg_intr_vect_r_masked_vect___ser2___bit 21
+#define reg_intr_vect_r_masked_vect___ser3___lsb 22
+#define reg_intr_vect_r_masked_vect___ser3___width 1
+#define reg_intr_vect_r_masked_vect___ser3___bit 22
+#define reg_intr_vect_r_masked_vect___p21___lsb 23
+#define reg_intr_vect_r_masked_vect___p21___width 1
+#define reg_intr_vect_r_masked_vect___p21___bit 23
+#define reg_intr_vect_r_masked_vect___eth0___lsb 24
+#define reg_intr_vect_r_masked_vect___eth0___width 1
+#define reg_intr_vect_r_masked_vect___eth0___bit 24
+#define reg_intr_vect_r_masked_vect___eth1___lsb 25
+#define reg_intr_vect_r_masked_vect___eth1___width 1
+#define reg_intr_vect_r_masked_vect___eth1___bit 25
+#define reg_intr_vect_r_masked_vect___timer___lsb 26
+#define reg_intr_vect_r_masked_vect___timer___width 1
+#define reg_intr_vect_r_masked_vect___timer___bit 26
+#define reg_intr_vect_r_masked_vect___bif_arb___lsb 27
+#define reg_intr_vect_r_masked_vect___bif_arb___width 1
+#define reg_intr_vect_r_masked_vect___bif_arb___bit 27
+#define reg_intr_vect_r_masked_vect___bif_dma___lsb 28
+#define reg_intr_vect_r_masked_vect___bif_dma___width 1
+#define reg_intr_vect_r_masked_vect___bif_dma___bit 28
+#define reg_intr_vect_r_masked_vect___ext___lsb 29
+#define reg_intr_vect_r_masked_vect___ext___width 1
+#define reg_intr_vect_r_masked_vect___ext___bit 29
+#define reg_intr_vect_r_masked_vect_offset 8
+
+/* Register r_nmi, scope intr_vect, type r */
+#define reg_intr_vect_r_nmi___ext___lsb 0
+#define reg_intr_vect_r_nmi___ext___width 1
+#define reg_intr_vect_r_nmi___ext___bit 0
+#define reg_intr_vect_r_nmi___watchdog___lsb 1
+#define reg_intr_vect_r_nmi___watchdog___width 1
+#define reg_intr_vect_r_nmi___watchdog___bit 1
+#define reg_intr_vect_r_nmi_offset 12
+
+/* Register r_guru, scope intr_vect, type r */
+#define reg_intr_vect_r_guru___jtag___lsb 0
+#define reg_intr_vect_r_guru___jtag___width 1
+#define reg_intr_vect_r_guru___jtag___bit 0
+#define reg_intr_vect_r_guru_offset 16
+
+
+/* Constants */
+#define regk_intr_vect_off                        0x00000000
+#define regk_intr_vect_on                         0x00000001
+#define regk_intr_vect_rw_mask_default            0x00000000
+#endif /* __intr_vect_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h
new file mode 100644
index 00000000000..0c808405484
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/irq_nmi_defs_asm.h
@@ -0,0 +1,69 @@
+#ifndef __irq_nmi_defs_asm_h
+#define __irq_nmi_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../mod/irq_nmi.r
+ *     id:           <not found>
+ *     last modfied: Thu Jan 22 09:22:43 2004
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/irq_nmi_defs_asm.h ../../mod/irq_nmi.r
+ *      id: $Id: irq_nmi_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cmd, scope irq_nmi, type rw */
+#define reg_irq_nmi_rw_cmd___delay___lsb 0
+#define reg_irq_nmi_rw_cmd___delay___width 16
+#define reg_irq_nmi_rw_cmd___op___lsb 16
+#define reg_irq_nmi_rw_cmd___op___width 2
+#define reg_irq_nmi_rw_cmd_offset 0
+
+
+/* Constants */
+#define regk_irq_nmi_ack_irq                      0x00000002
+#define regk_irq_nmi_ack_nmi                      0x00000003
+#define regk_irq_nmi_irq                          0x00000000
+#define regk_irq_nmi_nmi                          0x00000001
+#endif /* __irq_nmi_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h
new file mode 100644
index 00000000000..45400eb8d38
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/marb_defs_asm.h
@@ -0,0 +1,579 @@
+#ifndef __marb_defs_asm_h
+#define __marb_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/memarb/rtl/guinness/marb_top.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:12:16 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r
+ *      id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+#define STRIDE_marb_rw_int_slots 4
+/* Register rw_int_slots, scope marb, type rw */
+#define reg_marb_rw_int_slots___owner___lsb 0
+#define reg_marb_rw_int_slots___owner___width 4
+#define reg_marb_rw_int_slots_offset 0
+
+#define STRIDE_marb_rw_ext_slots 4
+/* Register rw_ext_slots, scope marb, type rw */
+#define reg_marb_rw_ext_slots___owner___lsb 0
+#define reg_marb_rw_ext_slots___owner___width 4
+#define reg_marb_rw_ext_slots_offset 256
+
+#define STRIDE_marb_rw_regs_slots 4
+/* Register rw_regs_slots, scope marb, type rw */
+#define reg_marb_rw_regs_slots___owner___lsb 0
+#define reg_marb_rw_regs_slots___owner___width 4
+#define reg_marb_rw_regs_slots_offset 512
+
+/* Register rw_intr_mask, scope marb, type rw */
+#define reg_marb_rw_intr_mask___bp0___lsb 0
+#define reg_marb_rw_intr_mask___bp0___width 1
+#define reg_marb_rw_intr_mask___bp0___bit 0
+#define reg_marb_rw_intr_mask___bp1___lsb 1
+#define reg_marb_rw_intr_mask___bp1___width 1
+#define reg_marb_rw_intr_mask___bp1___bit 1
+#define reg_marb_rw_intr_mask___bp2___lsb 2
+#define reg_marb_rw_intr_mask___bp2___width 1
+#define reg_marb_rw_intr_mask___bp2___bit 2
+#define reg_marb_rw_intr_mask___bp3___lsb 3
+#define reg_marb_rw_intr_mask___bp3___width 1
+#define reg_marb_rw_intr_mask___bp3___bit 3
+#define reg_marb_rw_intr_mask_offset 528
+
+/* Register rw_ack_intr, scope marb, type rw */
+#define reg_marb_rw_ack_intr___bp0___lsb 0
+#define reg_marb_rw_ack_intr___bp0___width 1
+#define reg_marb_rw_ack_intr___bp0___bit 0
+#define reg_marb_rw_ack_intr___bp1___lsb 1
+#define reg_marb_rw_ack_intr___bp1___width 1
+#define reg_marb_rw_ack_intr___bp1___bit 1
+#define reg_marb_rw_ack_intr___bp2___lsb 2
+#define reg_marb_rw_ack_intr___bp2___width 1
+#define reg_marb_rw_ack_intr___bp2___bit 2
+#define reg_marb_rw_ack_intr___bp3___lsb 3
+#define reg_marb_rw_ack_intr___bp3___width 1
+#define reg_marb_rw_ack_intr___bp3___bit 3
+#define reg_marb_rw_ack_intr_offset 532
+
+/* Register r_intr, scope marb, type r */
+#define reg_marb_r_intr___bp0___lsb 0
+#define reg_marb_r_intr___bp0___width 1
+#define reg_marb_r_intr___bp0___bit 0
+#define reg_marb_r_intr___bp1___lsb 1
+#define reg_marb_r_intr___bp1___width 1
+#define reg_marb_r_intr___bp1___bit 1
+#define reg_marb_r_intr___bp2___lsb 2
+#define reg_marb_r_intr___bp2___width 1
+#define reg_marb_r_intr___bp2___bit 2
+#define reg_marb_r_intr___bp3___lsb 3
+#define reg_marb_r_intr___bp3___width 1
+#define reg_marb_r_intr___bp3___bit 3
+#define reg_marb_r_intr_offset 536
+
+/* Register r_masked_intr, scope marb, type r */
+#define reg_marb_r_masked_intr___bp0___lsb 0
+#define reg_marb_r_masked_intr___bp0___width 1
+#define reg_marb_r_masked_intr___bp0___bit 0
+#define reg_marb_r_masked_intr___bp1___lsb 1
+#define reg_marb_r_masked_intr___bp1___width 1
+#define reg_marb_r_masked_intr___bp1___bit 1
+#define reg_marb_r_masked_intr___bp2___lsb 2
+#define reg_marb_r_masked_intr___bp2___width 1
+#define reg_marb_r_masked_intr___bp2___bit 2
+#define reg_marb_r_masked_intr___bp3___lsb 3
+#define reg_marb_r_masked_intr___bp3___width 1
+#define reg_marb_r_masked_intr___bp3___bit 3
+#define reg_marb_r_masked_intr_offset 540
+
+/* Register rw_stop_mask, scope marb, type rw */
+#define reg_marb_rw_stop_mask___dma0___lsb 0
+#define reg_marb_rw_stop_mask___dma0___width 1
+#define reg_marb_rw_stop_mask___dma0___bit 0
+#define reg_marb_rw_stop_mask___dma1___lsb 1
+#define reg_marb_rw_stop_mask___dma1___width 1
+#define reg_marb_rw_stop_mask___dma1___bit 1
+#define reg_marb_rw_stop_mask___dma2___lsb 2
+#define reg_marb_rw_stop_mask___dma2___width 1
+#define reg_marb_rw_stop_mask___dma2___bit 2
+#define reg_marb_rw_stop_mask___dma3___lsb 3
+#define reg_marb_rw_stop_mask___dma3___width 1
+#define reg_marb_rw_stop_mask___dma3___bit 3
+#define reg_marb_rw_stop_mask___dma4___lsb 4
+#define reg_marb_rw_stop_mask___dma4___width 1
+#define reg_marb_rw_stop_mask___dma4___bit 4
+#define reg_marb_rw_stop_mask___dma5___lsb 5
+#define reg_marb_rw_stop_mask___dma5___width 1
+#define reg_marb_rw_stop_mask___dma5___bit 5
+#define reg_marb_rw_stop_mask___dma6___lsb 6
+#define reg_marb_rw_stop_mask___dma6___width 1
+#define reg_marb_rw_stop_mask___dma6___bit 6
+#define reg_marb_rw_stop_mask___dma7___lsb 7
+#define reg_marb_rw_stop_mask___dma7___width 1
+#define reg_marb_rw_stop_mask___dma7___bit 7
+#define reg_marb_rw_stop_mask___dma8___lsb 8
+#define reg_marb_rw_stop_mask___dma8___width 1
+#define reg_marb_rw_stop_mask___dma8___bit 8
+#define reg_marb_rw_stop_mask___dma9___lsb 9
+#define reg_marb_rw_stop_mask___dma9___width 1
+#define reg_marb_rw_stop_mask___dma9___bit 9
+#define reg_marb_rw_stop_mask___cpui___lsb 10
+#define reg_marb_rw_stop_mask___cpui___width 1
+#define reg_marb_rw_stop_mask___cpui___bit 10
+#define reg_marb_rw_stop_mask___cpud___lsb 11
+#define reg_marb_rw_stop_mask___cpud___width 1
+#define reg_marb_rw_stop_mask___cpud___bit 11
+#define reg_marb_rw_stop_mask___iop___lsb 12
+#define reg_marb_rw_stop_mask___iop___width 1
+#define reg_marb_rw_stop_mask___iop___bit 12
+#define reg_marb_rw_stop_mask___slave___lsb 13
+#define reg_marb_rw_stop_mask___slave___width 1
+#define reg_marb_rw_stop_mask___slave___bit 13
+#define reg_marb_rw_stop_mask_offset 544
+
+/* Register r_stopped, scope marb, type r */
+#define reg_marb_r_stopped___dma0___lsb 0
+#define reg_marb_r_stopped___dma0___width 1
+#define reg_marb_r_stopped___dma0___bit 0
+#define reg_marb_r_stopped___dma1___lsb 1
+#define reg_marb_r_stopped___dma1___width 1
+#define reg_marb_r_stopped___dma1___bit 1
+#define reg_marb_r_stopped___dma2___lsb 2
+#define reg_marb_r_stopped___dma2___width 1
+#define reg_marb_r_stopped___dma2___bit 2
+#define reg_marb_r_stopped___dma3___lsb 3
+#define reg_marb_r_stopped___dma3___width 1
+#define reg_marb_r_stopped___dma3___bit 3
+#define reg_marb_r_stopped___dma4___lsb 4
+#define reg_marb_r_stopped___dma4___width 1
+#define reg_marb_r_stopped___dma4___bit 4
+#define reg_marb_r_stopped___dma5___lsb 5
+#define reg_marb_r_stopped___dma5___width 1
+#define reg_marb_r_stopped___dma5___bit 5
+#define reg_marb_r_stopped___dma6___lsb 6
+#define reg_marb_r_stopped___dma6___width 1
+#define reg_marb_r_stopped___dma6___bit 6
+#define reg_marb_r_stopped___dma7___lsb 7
+#define reg_marb_r_stopped___dma7___width 1
+#define reg_marb_r_stopped___dma7___bit 7
+#define reg_marb_r_stopped___dma8___lsb 8
+#define reg_marb_r_stopped___dma8___width 1
+#define reg_marb_r_stopped___dma8___bit 8
+#define reg_marb_r_stopped___dma9___lsb 9
+#define reg_marb_r_stopped___dma9___width 1
+#define reg_marb_r_stopped___dma9___bit 9
+#define reg_marb_r_stopped___cpui___lsb 10
+#define reg_marb_r_stopped___cpui___width 1
+#define reg_marb_r_stopped___cpui___bit 10
+#define reg_marb_r_stopped___cpud___lsb 11
+#define reg_marb_r_stopped___cpud___width 1
+#define reg_marb_r_stopped___cpud___bit 11
+#define reg_marb_r_stopped___iop___lsb 12
+#define reg_marb_r_stopped___iop___width 1
+#define reg_marb_r_stopped___iop___bit 12
+#define reg_marb_r_stopped___slave___lsb 13
+#define reg_marb_r_stopped___slave___width 1
+#define reg_marb_r_stopped___slave___bit 13
+#define reg_marb_r_stopped_offset 548
+
+/* Register rw_no_snoop, scope marb, type rw */
+#define reg_marb_rw_no_snoop___dma0___lsb 0
+#define reg_marb_rw_no_snoop___dma0___width 1
+#define reg_marb_rw_no_snoop___dma0___bit 0
+#define reg_marb_rw_no_snoop___dma1___lsb 1
+#define reg_marb_rw_no_snoop___dma1___width 1
+#define reg_marb_rw_no_snoop___dma1___bit 1
+#define reg_marb_rw_no_snoop___dma2___lsb 2
+#define reg_marb_rw_no_snoop___dma2___width 1
+#define reg_marb_rw_no_snoop___dma2___bit 2
+#define reg_marb_rw_no_snoop___dma3___lsb 3
+#define reg_marb_rw_no_snoop___dma3___width 1
+#define reg_marb_rw_no_snoop___dma3___bit 3
+#define reg_marb_rw_no_snoop___dma4___lsb 4
+#define reg_marb_rw_no_snoop___dma4___width 1
+#define reg_marb_rw_no_snoop___dma4___bit 4
+#define reg_marb_rw_no_snoop___dma5___lsb 5
+#define reg_marb_rw_no_snoop___dma5___width 1
+#define reg_marb_rw_no_snoop___dma5___bit 5
+#define reg_marb_rw_no_snoop___dma6___lsb 6
+#define reg_marb_rw_no_snoop___dma6___width 1
+#define reg_marb_rw_no_snoop___dma6___bit 6
+#define reg_marb_rw_no_snoop___dma7___lsb 7
+#define reg_marb_rw_no_snoop___dma7___width 1
+#define reg_marb_rw_no_snoop___dma7___bit 7
+#define reg_marb_rw_no_snoop___dma8___lsb 8
+#define reg_marb_rw_no_snoop___dma8___width 1
+#define reg_marb_rw_no_snoop___dma8___bit 8
+#define reg_marb_rw_no_snoop___dma9___lsb 9
+#define reg_marb_rw_no_snoop___dma9___width 1
+#define reg_marb_rw_no_snoop___dma9___bit 9
+#define reg_marb_rw_no_snoop___cpui___lsb 10
+#define reg_marb_rw_no_snoop___cpui___width 1
+#define reg_marb_rw_no_snoop___cpui___bit 10
+#define reg_marb_rw_no_snoop___cpud___lsb 11
+#define reg_marb_rw_no_snoop___cpud___width 1
+#define reg_marb_rw_no_snoop___cpud___bit 11
+#define reg_marb_rw_no_snoop___iop___lsb 12
+#define reg_marb_rw_no_snoop___iop___width 1
+#define reg_marb_rw_no_snoop___iop___bit 12
+#define reg_marb_rw_no_snoop___slave___lsb 13
+#define reg_marb_rw_no_snoop___slave___width 1
+#define reg_marb_rw_no_snoop___slave___bit 13
+#define reg_marb_rw_no_snoop_offset 832
+
+/* Register rw_no_snoop_rq, scope marb, type rw */
+#define reg_marb_rw_no_snoop_rq___cpui___lsb 10
+#define reg_marb_rw_no_snoop_rq___cpui___width 1
+#define reg_marb_rw_no_snoop_rq___cpui___bit 10
+#define reg_marb_rw_no_snoop_rq___cpud___lsb 11
+#define reg_marb_rw_no_snoop_rq___cpud___width 1
+#define reg_marb_rw_no_snoop_rq___cpud___bit 11
+#define reg_marb_rw_no_snoop_rq_offset 836
+
+
+/* Constants */
+#define regk_marb_cpud                            0x0000000b
+#define regk_marb_cpui                            0x0000000a
+#define regk_marb_dma0                            0x00000000
+#define regk_marb_dma1                            0x00000001
+#define regk_marb_dma2                            0x00000002
+#define regk_marb_dma3                            0x00000003
+#define regk_marb_dma4                            0x00000004
+#define regk_marb_dma5                            0x00000005
+#define regk_marb_dma6                            0x00000006
+#define regk_marb_dma7                            0x00000007
+#define regk_marb_dma8                            0x00000008
+#define regk_marb_dma9                            0x00000009
+#define regk_marb_iop                             0x0000000c
+#define regk_marb_no                              0x00000000
+#define regk_marb_r_stopped_default               0x00000000
+#define regk_marb_rw_ext_slots_default            0x00000000
+#define regk_marb_rw_ext_slots_size               0x00000040
+#define regk_marb_rw_int_slots_default            0x00000000
+#define regk_marb_rw_int_slots_size               0x00000040
+#define regk_marb_rw_intr_mask_default            0x00000000
+#define regk_marb_rw_no_snoop_default             0x00000000
+#define regk_marb_rw_no_snoop_rq_default          0x00000000
+#define regk_marb_rw_regs_slots_default           0x00000000
+#define regk_marb_rw_regs_slots_size              0x00000004
+#define regk_marb_rw_stop_mask_default            0x00000000
+#define regk_marb_slave                           0x0000000d
+#define regk_marb_yes                             0x00000001
+#endif /* __marb_defs_asm_h */
+#ifndef __marb_bp_defs_asm_h
+#define __marb_bp_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/memarb/rtl/guinness/marb_top.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:12:16 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r
+ *      id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_first_addr, scope marb_bp, type rw */
+#define reg_marb_bp_rw_first_addr_offset 0
+
+/* Register rw_last_addr, scope marb_bp, type rw */
+#define reg_marb_bp_rw_last_addr_offset 4
+
+/* Register rw_op, scope marb_bp, type rw */
+#define reg_marb_bp_rw_op___rd___lsb 0
+#define reg_marb_bp_rw_op___rd___width 1
+#define reg_marb_bp_rw_op___rd___bit 0
+#define reg_marb_bp_rw_op___wr___lsb 1
+#define reg_marb_bp_rw_op___wr___width 1
+#define reg_marb_bp_rw_op___wr___bit 1
+#define reg_marb_bp_rw_op___rd_excl___lsb 2
+#define reg_marb_bp_rw_op___rd_excl___width 1
+#define reg_marb_bp_rw_op___rd_excl___bit 2
+#define reg_marb_bp_rw_op___pri_wr___lsb 3
+#define reg_marb_bp_rw_op___pri_wr___width 1
+#define reg_marb_bp_rw_op___pri_wr___bit 3
+#define reg_marb_bp_rw_op___us_rd___lsb 4
+#define reg_marb_bp_rw_op___us_rd___width 1
+#define reg_marb_bp_rw_op___us_rd___bit 4
+#define reg_marb_bp_rw_op___us_wr___lsb 5
+#define reg_marb_bp_rw_op___us_wr___width 1
+#define reg_marb_bp_rw_op___us_wr___bit 5
+#define reg_marb_bp_rw_op___us_rd_excl___lsb 6
+#define reg_marb_bp_rw_op___us_rd_excl___width 1
+#define reg_marb_bp_rw_op___us_rd_excl___bit 6
+#define reg_marb_bp_rw_op___us_pri_wr___lsb 7
+#define reg_marb_bp_rw_op___us_pri_wr___width 1
+#define reg_marb_bp_rw_op___us_pri_wr___bit 7
+#define reg_marb_bp_rw_op_offset 8
+
+/* Register rw_clients, scope marb_bp, type rw */
+#define reg_marb_bp_rw_clients___dma0___lsb 0
+#define reg_marb_bp_rw_clients___dma0___width 1
+#define reg_marb_bp_rw_clients___dma0___bit 0
+#define reg_marb_bp_rw_clients___dma1___lsb 1
+#define reg_marb_bp_rw_clients___dma1___width 1
+#define reg_marb_bp_rw_clients___dma1___bit 1
+#define reg_marb_bp_rw_clients___dma2___lsb 2
+#define reg_marb_bp_rw_clients___dma2___width 1
+#define reg_marb_bp_rw_clients___dma2___bit 2
+#define reg_marb_bp_rw_clients___dma3___lsb 3
+#define reg_marb_bp_rw_clients___dma3___width 1
+#define reg_marb_bp_rw_clients___dma3___bit 3
+#define reg_marb_bp_rw_clients___dma4___lsb 4
+#define reg_marb_bp_rw_clients___dma4___width 1
+#define reg_marb_bp_rw_clients___dma4___bit 4
+#define reg_marb_bp_rw_clients___dma5___lsb 5
+#define reg_marb_bp_rw_clients___dma5___width 1
+#define reg_marb_bp_rw_clients___dma5___bit 5
+#define reg_marb_bp_rw_clients___dma6___lsb 6
+#define reg_marb_bp_rw_clients___dma6___width 1
+#define reg_marb_bp_rw_clients___dma6___bit 6
+#define reg_marb_bp_rw_clients___dma7___lsb 7
+#define reg_marb_bp_rw_clients___dma7___width 1
+#define reg_marb_bp_rw_clients___dma7___bit 7
+#define reg_marb_bp_rw_clients___dma8___lsb 8
+#define reg_marb_bp_rw_clients___dma8___width 1
+#define reg_marb_bp_rw_clients___dma8___bit 8
+#define reg_marb_bp_rw_clients___dma9___lsb 9
+#define reg_marb_bp_rw_clients___dma9___width 1
+#define reg_marb_bp_rw_clients___dma9___bit 9
+#define reg_marb_bp_rw_clients___cpui___lsb 10
+#define reg_marb_bp_rw_clients___cpui___width 1
+#define reg_marb_bp_rw_clients___cpui___bit 10
+#define reg_marb_bp_rw_clients___cpud___lsb 11
+#define reg_marb_bp_rw_clients___cpud___width 1
+#define reg_marb_bp_rw_clients___cpud___bit 11
+#define reg_marb_bp_rw_clients___iop___lsb 12
+#define reg_marb_bp_rw_clients___iop___width 1
+#define reg_marb_bp_rw_clients___iop___bit 12
+#define reg_marb_bp_rw_clients___slave___lsb 13
+#define reg_marb_bp_rw_clients___slave___width 1
+#define reg_marb_bp_rw_clients___slave___bit 13
+#define reg_marb_bp_rw_clients_offset 12
+
+/* Register rw_options, scope marb_bp, type rw */
+#define reg_marb_bp_rw_options___wrap___lsb 0
+#define reg_marb_bp_rw_options___wrap___width 1
+#define reg_marb_bp_rw_options___wrap___bit 0
+#define reg_marb_bp_rw_options_offset 16
+
+/* Register r_brk_addr, scope marb_bp, type r */
+#define reg_marb_bp_r_brk_addr_offset 20
+
+/* Register r_brk_op, scope marb_bp, type r */
+#define reg_marb_bp_r_brk_op___rd___lsb 0
+#define reg_marb_bp_r_brk_op___rd___width 1
+#define reg_marb_bp_r_brk_op___rd___bit 0
+#define reg_marb_bp_r_brk_op___wr___lsb 1
+#define reg_marb_bp_r_brk_op___wr___width 1
+#define reg_marb_bp_r_brk_op___wr___bit 1
+#define reg_marb_bp_r_brk_op___rd_excl___lsb 2
+#define reg_marb_bp_r_brk_op___rd_excl___width 1
+#define reg_marb_bp_r_brk_op___rd_excl___bit 2
+#define reg_marb_bp_r_brk_op___pri_wr___lsb 3
+#define reg_marb_bp_r_brk_op___pri_wr___width 1
+#define reg_marb_bp_r_brk_op___pri_wr___bit 3
+#define reg_marb_bp_r_brk_op___us_rd___lsb 4
+#define reg_marb_bp_r_brk_op___us_rd___width 1
+#define reg_marb_bp_r_brk_op___us_rd___bit 4
+#define reg_marb_bp_r_brk_op___us_wr___lsb 5
+#define reg_marb_bp_r_brk_op___us_wr___width 1
+#define reg_marb_bp_r_brk_op___us_wr___bit 5
+#define reg_marb_bp_r_brk_op___us_rd_excl___lsb 6
+#define reg_marb_bp_r_brk_op___us_rd_excl___width 1
+#define reg_marb_bp_r_brk_op___us_rd_excl___bit 6
+#define reg_marb_bp_r_brk_op___us_pri_wr___lsb 7
+#define reg_marb_bp_r_brk_op___us_pri_wr___width 1
+#define reg_marb_bp_r_brk_op___us_pri_wr___bit 7
+#define reg_marb_bp_r_brk_op_offset 24
+
+/* Register r_brk_clients, scope marb_bp, type r */
+#define reg_marb_bp_r_brk_clients___dma0___lsb 0
+#define reg_marb_bp_r_brk_clients___dma0___width 1
+#define reg_marb_bp_r_brk_clients___dma0___bit 0
+#define reg_marb_bp_r_brk_clients___dma1___lsb 1
+#define reg_marb_bp_r_brk_clients___dma1___width 1
+#define reg_marb_bp_r_brk_clients___dma1___bit 1
+#define reg_marb_bp_r_brk_clients___dma2___lsb 2
+#define reg_marb_bp_r_brk_clients___dma2___width 1
+#define reg_marb_bp_r_brk_clients___dma2___bit 2
+#define reg_marb_bp_r_brk_clients___dma3___lsb 3
+#define reg_marb_bp_r_brk_clients___dma3___width 1
+#define reg_marb_bp_r_brk_clients___dma3___bit 3
+#define reg_marb_bp_r_brk_clients___dma4___lsb 4
+#define reg_marb_bp_r_brk_clients___dma4___width 1
+#define reg_marb_bp_r_brk_clients___dma4___bit 4
+#define reg_marb_bp_r_brk_clients___dma5___lsb 5
+#define reg_marb_bp_r_brk_clients___dma5___width 1
+#define reg_marb_bp_r_brk_clients___dma5___bit 5
+#define reg_marb_bp_r_brk_clients___dma6___lsb 6
+#define reg_marb_bp_r_brk_clients___dma6___width 1
+#define reg_marb_bp_r_brk_clients___dma6___bit 6
+#define reg_marb_bp_r_brk_clients___dma7___lsb 7
+#define reg_marb_bp_r_brk_clients___dma7___width 1
+#define reg_marb_bp_r_brk_clients___dma7___bit 7
+#define reg_marb_bp_r_brk_clients___dma8___lsb 8
+#define reg_marb_bp_r_brk_clients___dma8___width 1
+#define reg_marb_bp_r_brk_clients___dma8___bit 8
+#define reg_marb_bp_r_brk_clients___dma9___lsb 9
+#define reg_marb_bp_r_brk_clients___dma9___width 1
+#define reg_marb_bp_r_brk_clients___dma9___bit 9
+#define reg_marb_bp_r_brk_clients___cpui___lsb 10
+#define reg_marb_bp_r_brk_clients___cpui___width 1
+#define reg_marb_bp_r_brk_clients___cpui___bit 10
+#define reg_marb_bp_r_brk_clients___cpud___lsb 11
+#define reg_marb_bp_r_brk_clients___cpud___width 1
+#define reg_marb_bp_r_brk_clients___cpud___bit 11
+#define reg_marb_bp_r_brk_clients___iop___lsb 12
+#define reg_marb_bp_r_brk_clients___iop___width 1
+#define reg_marb_bp_r_brk_clients___iop___bit 12
+#define reg_marb_bp_r_brk_clients___slave___lsb 13
+#define reg_marb_bp_r_brk_clients___slave___width 1
+#define reg_marb_bp_r_brk_clients___slave___bit 13
+#define reg_marb_bp_r_brk_clients_offset 28
+
+/* Register r_brk_first_client, scope marb_bp, type r */
+#define reg_marb_bp_r_brk_first_client___dma0___lsb 0
+#define reg_marb_bp_r_brk_first_client___dma0___width 1
+#define reg_marb_bp_r_brk_first_client___dma0___bit 0
+#define reg_marb_bp_r_brk_first_client___dma1___lsb 1
+#define reg_marb_bp_r_brk_first_client___dma1___width 1
+#define reg_marb_bp_r_brk_first_client___dma1___bit 1
+#define reg_marb_bp_r_brk_first_client___dma2___lsb 2
+#define reg_marb_bp_r_brk_first_client___dma2___width 1
+#define reg_marb_bp_r_brk_first_client___dma2___bit 2
+#define reg_marb_bp_r_brk_first_client___dma3___lsb 3
+#define reg_marb_bp_r_brk_first_client___dma3___width 1
+#define reg_marb_bp_r_brk_first_client___dma3___bit 3
+#define reg_marb_bp_r_brk_first_client___dma4___lsb 4
+#define reg_marb_bp_r_brk_first_client___dma4___width 1
+#define reg_marb_bp_r_brk_first_client___dma4___bit 4
+#define reg_marb_bp_r_brk_first_client___dma5___lsb 5
+#define reg_marb_bp_r_brk_first_client___dma5___width 1
+#define reg_marb_bp_r_brk_first_client___dma5___bit 5
+#define reg_marb_bp_r_brk_first_client___dma6___lsb 6
+#define reg_marb_bp_r_brk_first_client___dma6___width 1
+#define reg_marb_bp_r_brk_first_client___dma6___bit 6
+#define reg_marb_bp_r_brk_first_client___dma7___lsb 7
+#define reg_marb_bp_r_brk_first_client___dma7___width 1
+#define reg_marb_bp_r_brk_first_client___dma7___bit 7
+#define reg_marb_bp_r_brk_first_client___dma8___lsb 8
+#define reg_marb_bp_r_brk_first_client___dma8___width 1
+#define reg_marb_bp_r_brk_first_client___dma8___bit 8
+#define reg_marb_bp_r_brk_first_client___dma9___lsb 9
+#define reg_marb_bp_r_brk_first_client___dma9___width 1
+#define reg_marb_bp_r_brk_first_client___dma9___bit 9
+#define reg_marb_bp_r_brk_first_client___cpui___lsb 10
+#define reg_marb_bp_r_brk_first_client___cpui___width 1
+#define reg_marb_bp_r_brk_first_client___cpui___bit 10
+#define reg_marb_bp_r_brk_first_client___cpud___lsb 11
+#define reg_marb_bp_r_brk_first_client___cpud___width 1
+#define reg_marb_bp_r_brk_first_client___cpud___bit 11
+#define reg_marb_bp_r_brk_first_client___iop___lsb 12
+#define reg_marb_bp_r_brk_first_client___iop___width 1
+#define reg_marb_bp_r_brk_first_client___iop___bit 12
+#define reg_marb_bp_r_brk_first_client___slave___lsb 13
+#define reg_marb_bp_r_brk_first_client___slave___width 1
+#define reg_marb_bp_r_brk_first_client___slave___bit 13
+#define reg_marb_bp_r_brk_first_client_offset 32
+
+/* Register r_brk_size, scope marb_bp, type r */
+#define reg_marb_bp_r_brk_size_offset 36
+
+/* Register rw_ack, scope marb_bp, type rw */
+#define reg_marb_bp_rw_ack_offset 40
+
+
+/* Constants */
+#define regk_marb_bp_no                           0x00000000
+#define regk_marb_bp_rw_op_default                0x00000000
+#define regk_marb_bp_rw_options_default           0x00000000
+#define regk_marb_bp_yes                          0x00000001
+#endif /* __marb_bp_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h
new file mode 100644
index 00000000000..505b7a16d87
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/mmu_defs_asm.h
@@ -0,0 +1,212 @@
+#ifndef __mmu_defs_asm_h
+#define __mmu_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/mmu/doc/mmu_regs.r
+ *     id:           mmu_regs.r,v 1.12 2004/05/06 13:48:45 mikaeln Exp
+ *     last modfied: Mon Apr 11 17:03:20 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/mmu_defs_asm.h ../../inst/mmu/doc/mmu_regs.r
+ *      id: $Id: mmu_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_mm_cfg, scope mmu, type rw */
+#define reg_mmu_rw_mm_cfg___seg_0___lsb 0
+#define reg_mmu_rw_mm_cfg___seg_0___width 1
+#define reg_mmu_rw_mm_cfg___seg_0___bit 0
+#define reg_mmu_rw_mm_cfg___seg_1___lsb 1
+#define reg_mmu_rw_mm_cfg___seg_1___width 1
+#define reg_mmu_rw_mm_cfg___seg_1___bit 1
+#define reg_mmu_rw_mm_cfg___seg_2___lsb 2
+#define reg_mmu_rw_mm_cfg___seg_2___width 1
+#define reg_mmu_rw_mm_cfg___seg_2___bit 2
+#define reg_mmu_rw_mm_cfg___seg_3___lsb 3
+#define reg_mmu_rw_mm_cfg___seg_3___width 1
+#define reg_mmu_rw_mm_cfg___seg_3___bit 3
+#define reg_mmu_rw_mm_cfg___seg_4___lsb 4
+#define reg_mmu_rw_mm_cfg___seg_4___width 1
+#define reg_mmu_rw_mm_cfg___seg_4___bit 4
+#define reg_mmu_rw_mm_cfg___seg_5___lsb 5
+#define reg_mmu_rw_mm_cfg___seg_5___width 1
+#define reg_mmu_rw_mm_cfg___seg_5___bit 5
+#define reg_mmu_rw_mm_cfg___seg_6___lsb 6
+#define reg_mmu_rw_mm_cfg___seg_6___width 1
+#define reg_mmu_rw_mm_cfg___seg_6___bit 6
+#define reg_mmu_rw_mm_cfg___seg_7___lsb 7
+#define reg_mmu_rw_mm_cfg___seg_7___width 1
+#define reg_mmu_rw_mm_cfg___seg_7___bit 7
+#define reg_mmu_rw_mm_cfg___seg_8___lsb 8
+#define reg_mmu_rw_mm_cfg___seg_8___width 1
+#define reg_mmu_rw_mm_cfg___seg_8___bit 8
+#define reg_mmu_rw_mm_cfg___seg_9___lsb 9
+#define reg_mmu_rw_mm_cfg___seg_9___width 1
+#define reg_mmu_rw_mm_cfg___seg_9___bit 9
+#define reg_mmu_rw_mm_cfg___seg_a___lsb 10
+#define reg_mmu_rw_mm_cfg___seg_a___width 1
+#define reg_mmu_rw_mm_cfg___seg_a___bit 10
+#define reg_mmu_rw_mm_cfg___seg_b___lsb 11
+#define reg_mmu_rw_mm_cfg___seg_b___width 1
+#define reg_mmu_rw_mm_cfg___seg_b___bit 11
+#define reg_mmu_rw_mm_cfg___seg_c___lsb 12
+#define reg_mmu_rw_mm_cfg___seg_c___width 1
+#define reg_mmu_rw_mm_cfg___seg_c___bit 12
+#define reg_mmu_rw_mm_cfg___seg_d___lsb 13
+#define reg_mmu_rw_mm_cfg___seg_d___width 1
+#define reg_mmu_rw_mm_cfg___seg_d___bit 13
+#define reg_mmu_rw_mm_cfg___seg_e___lsb 14
+#define reg_mmu_rw_mm_cfg___seg_e___width 1
+#define reg_mmu_rw_mm_cfg___seg_e___bit 14
+#define reg_mmu_rw_mm_cfg___seg_f___lsb 15
+#define reg_mmu_rw_mm_cfg___seg_f___width 1
+#define reg_mmu_rw_mm_cfg___seg_f___bit 15
+#define reg_mmu_rw_mm_cfg___inv___lsb 16
+#define reg_mmu_rw_mm_cfg___inv___width 1
+#define reg_mmu_rw_mm_cfg___inv___bit 16
+#define reg_mmu_rw_mm_cfg___ex___lsb 17
+#define reg_mmu_rw_mm_cfg___ex___width 1
+#define reg_mmu_rw_mm_cfg___ex___bit 17
+#define reg_mmu_rw_mm_cfg___acc___lsb 18
+#define reg_mmu_rw_mm_cfg___acc___width 1
+#define reg_mmu_rw_mm_cfg___acc___bit 18
+#define reg_mmu_rw_mm_cfg___we___lsb 19
+#define reg_mmu_rw_mm_cfg___we___width 1
+#define reg_mmu_rw_mm_cfg___we___bit 19
+#define reg_mmu_rw_mm_cfg_offset 0
+
+/* Register rw_mm_kbase_lo, scope mmu, type rw */
+#define reg_mmu_rw_mm_kbase_lo___base_0___lsb 0
+#define reg_mmu_rw_mm_kbase_lo___base_0___width 4
+#define reg_mmu_rw_mm_kbase_lo___base_1___lsb 4
+#define reg_mmu_rw_mm_kbase_lo___base_1___width 4
+#define reg_mmu_rw_mm_kbase_lo___base_2___lsb 8
+#define reg_mmu_rw_mm_kbase_lo___base_2___width 4
+#define reg_mmu_rw_mm_kbase_lo___base_3___lsb 12
+#define reg_mmu_rw_mm_kbase_lo___base_3___width 4
+#define reg_mmu_rw_mm_kbase_lo___base_4___lsb 16
+#define reg_mmu_rw_mm_kbase_lo___base_4___width 4
+#define reg_mmu_rw_mm_kbase_lo___base_5___lsb 20
+#define reg_mmu_rw_mm_kbase_lo___base_5___width 4
+#define reg_mmu_rw_mm_kbase_lo___base_6___lsb 24
+#define reg_mmu_rw_mm_kbase_lo___base_6___width 4
+#define reg_mmu_rw_mm_kbase_lo___base_7___lsb 28
+#define reg_mmu_rw_mm_kbase_lo___base_7___width 4
+#define reg_mmu_rw_mm_kbase_lo_offset 4
+
+/* Register rw_mm_kbase_hi, scope mmu, type rw */
+#define reg_mmu_rw_mm_kbase_hi___base_8___lsb 0
+#define reg_mmu_rw_mm_kbase_hi___base_8___width 4
+#define reg_mmu_rw_mm_kbase_hi___base_9___lsb 4
+#define reg_mmu_rw_mm_kbase_hi___base_9___width 4
+#define reg_mmu_rw_mm_kbase_hi___base_a___lsb 8
+#define reg_mmu_rw_mm_kbase_hi___base_a___width 4
+#define reg_mmu_rw_mm_kbase_hi___base_b___lsb 12
+#define reg_mmu_rw_mm_kbase_hi___base_b___width 4
+#define reg_mmu_rw_mm_kbase_hi___base_c___lsb 16
+#define reg_mmu_rw_mm_kbase_hi___base_c___width 4
+#define reg_mmu_rw_mm_kbase_hi___base_d___lsb 20
+#define reg_mmu_rw_mm_kbase_hi___base_d___width 4
+#define reg_mmu_rw_mm_kbase_hi___base_e___lsb 24
+#define reg_mmu_rw_mm_kbase_hi___base_e___width 4
+#define reg_mmu_rw_mm_kbase_hi___base_f___lsb 28
+#define reg_mmu_rw_mm_kbase_hi___base_f___width 4
+#define reg_mmu_rw_mm_kbase_hi_offset 8
+
+/* Register r_mm_cause, scope mmu, type r */
+#define reg_mmu_r_mm_cause___pid___lsb 0
+#define reg_mmu_r_mm_cause___pid___width 8
+#define reg_mmu_r_mm_cause___op___lsb 8
+#define reg_mmu_r_mm_cause___op___width 2
+#define reg_mmu_r_mm_cause___vpn___lsb 13
+#define reg_mmu_r_mm_cause___vpn___width 19
+#define reg_mmu_r_mm_cause_offset 12
+
+/* Register rw_mm_tlb_sel, scope mmu, type rw */
+#define reg_mmu_rw_mm_tlb_sel___idx___lsb 0
+#define reg_mmu_rw_mm_tlb_sel___idx___width 4
+#define reg_mmu_rw_mm_tlb_sel___set___lsb 4
+#define reg_mmu_rw_mm_tlb_sel___set___width 2
+#define reg_mmu_rw_mm_tlb_sel_offset 16
+
+/* Register rw_mm_tlb_lo, scope mmu, type rw */
+#define reg_mmu_rw_mm_tlb_lo___x___lsb 0
+#define reg_mmu_rw_mm_tlb_lo___x___width 1
+#define reg_mmu_rw_mm_tlb_lo___x___bit 0
+#define reg_mmu_rw_mm_tlb_lo___w___lsb 1
+#define reg_mmu_rw_mm_tlb_lo___w___width 1
+#define reg_mmu_rw_mm_tlb_lo___w___bit 1
+#define reg_mmu_rw_mm_tlb_lo___k___lsb 2
+#define reg_mmu_rw_mm_tlb_lo___k___width 1
+#define reg_mmu_rw_mm_tlb_lo___k___bit 2
+#define reg_mmu_rw_mm_tlb_lo___v___lsb 3
+#define reg_mmu_rw_mm_tlb_lo___v___width 1
+#define reg_mmu_rw_mm_tlb_lo___v___bit 3
+#define reg_mmu_rw_mm_tlb_lo___g___lsb 4
+#define reg_mmu_rw_mm_tlb_lo___g___width 1
+#define reg_mmu_rw_mm_tlb_lo___g___bit 4
+#define reg_mmu_rw_mm_tlb_lo___pfn___lsb 13
+#define reg_mmu_rw_mm_tlb_lo___pfn___width 19
+#define reg_mmu_rw_mm_tlb_lo_offset 20
+
+/* Register rw_mm_tlb_hi, scope mmu, type rw */
+#define reg_mmu_rw_mm_tlb_hi___pid___lsb 0
+#define reg_mmu_rw_mm_tlb_hi___pid___width 8
+#define reg_mmu_rw_mm_tlb_hi___vpn___lsb 13
+#define reg_mmu_rw_mm_tlb_hi___vpn___width 19
+#define reg_mmu_rw_mm_tlb_hi_offset 24
+
+
+/* Constants */
+#define regk_mmu_execute                          0x00000000
+#define regk_mmu_flush                            0x00000003
+#define regk_mmu_linear                           0x00000001
+#define regk_mmu_no                               0x00000000
+#define regk_mmu_off                              0x00000000
+#define regk_mmu_on                               0x00000001
+#define regk_mmu_page                             0x00000000
+#define regk_mmu_read                             0x00000001
+#define regk_mmu_write                            0x00000002
+#define regk_mmu_yes                              0x00000001
+#endif /* __mmu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h b/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h
new file mode 100644
index 00000000000..339500bf3bc
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/mmu_supp_reg.h
@@ -0,0 +1,7 @@
+#define RW_MM_CFG	0
+#define RW_MM_KBASE_LO	1
+#define RW_MM_KBASE_HI	2
+#define R_MM_CAUSE	3
+#define RW_MM_TLB_SEL	4
+#define RW_MM_TLB_LO	5
+#define RW_MM_TLB_HI	6
diff --git a/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h
new file mode 100644
index 00000000000..13c725e4c77
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h
@@ -0,0 +1,632 @@
+#ifndef __pinmux_defs_asm_h
+#define __pinmux_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/pinmux/rtl/guinness/pinmux_regs.r
+ *     id:           pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp
+ *     last modfied: Mon Apr 11 16:09:11 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
+ *      id: $Id: pinmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_pa, scope pinmux, type rw */
+#define reg_pinmux_rw_pa___pa0___lsb 0
+#define reg_pinmux_rw_pa___pa0___width 1
+#define reg_pinmux_rw_pa___pa0___bit 0
+#define reg_pinmux_rw_pa___pa1___lsb 1
+#define reg_pinmux_rw_pa___pa1___width 1
+#define reg_pinmux_rw_pa___pa1___bit 1
+#define reg_pinmux_rw_pa___pa2___lsb 2
+#define reg_pinmux_rw_pa___pa2___width 1
+#define reg_pinmux_rw_pa___pa2___bit 2
+#define reg_pinmux_rw_pa___pa3___lsb 3
+#define reg_pinmux_rw_pa___pa3___width 1
+#define reg_pinmux_rw_pa___pa3___bit 3
+#define reg_pinmux_rw_pa___pa4___lsb 4
+#define reg_pinmux_rw_pa___pa4___width 1
+#define reg_pinmux_rw_pa___pa4___bit 4
+#define reg_pinmux_rw_pa___pa5___lsb 5
+#define reg_pinmux_rw_pa___pa5___width 1
+#define reg_pinmux_rw_pa___pa5___bit 5
+#define reg_pinmux_rw_pa___pa6___lsb 6
+#define reg_pinmux_rw_pa___pa6___width 1
+#define reg_pinmux_rw_pa___pa6___bit 6
+#define reg_pinmux_rw_pa___pa7___lsb 7
+#define reg_pinmux_rw_pa___pa7___width 1
+#define reg_pinmux_rw_pa___pa7___bit 7
+#define reg_pinmux_rw_pa___csp2_n___lsb 8
+#define reg_pinmux_rw_pa___csp2_n___width 1
+#define reg_pinmux_rw_pa___csp2_n___bit 8
+#define reg_pinmux_rw_pa___csp3_n___lsb 9
+#define reg_pinmux_rw_pa___csp3_n___width 1
+#define reg_pinmux_rw_pa___csp3_n___bit 9
+#define reg_pinmux_rw_pa___csp5_n___lsb 10
+#define reg_pinmux_rw_pa___csp5_n___width 1
+#define reg_pinmux_rw_pa___csp5_n___bit 10
+#define reg_pinmux_rw_pa___csp6_n___lsb 11
+#define reg_pinmux_rw_pa___csp6_n___width 1
+#define reg_pinmux_rw_pa___csp6_n___bit 11
+#define reg_pinmux_rw_pa___hsh4___lsb 12
+#define reg_pinmux_rw_pa___hsh4___width 1
+#define reg_pinmux_rw_pa___hsh4___bit 12
+#define reg_pinmux_rw_pa___hsh5___lsb 13
+#define reg_pinmux_rw_pa___hsh5___width 1
+#define reg_pinmux_rw_pa___hsh5___bit 13
+#define reg_pinmux_rw_pa___hsh6___lsb 14
+#define reg_pinmux_rw_pa___hsh6___width 1
+#define reg_pinmux_rw_pa___hsh6___bit 14
+#define reg_pinmux_rw_pa___hsh7___lsb 15
+#define reg_pinmux_rw_pa___hsh7___width 1
+#define reg_pinmux_rw_pa___hsh7___bit 15
+#define reg_pinmux_rw_pa_offset 0
+
+/* Register rw_hwprot, scope pinmux, type rw */
+#define reg_pinmux_rw_hwprot___ser1___lsb 0
+#define reg_pinmux_rw_hwprot___ser1___width 1
+#define reg_pinmux_rw_hwprot___ser1___bit 0
+#define reg_pinmux_rw_hwprot___ser2___lsb 1
+#define reg_pinmux_rw_hwprot___ser2___width 1
+#define reg_pinmux_rw_hwprot___ser2___bit 1
+#define reg_pinmux_rw_hwprot___ser3___lsb 2
+#define reg_pinmux_rw_hwprot___ser3___width 1
+#define reg_pinmux_rw_hwprot___ser3___bit 2
+#define reg_pinmux_rw_hwprot___sser0___lsb 3
+#define reg_pinmux_rw_hwprot___sser0___width 1
+#define reg_pinmux_rw_hwprot___sser0___bit 3
+#define reg_pinmux_rw_hwprot___sser1___lsb 4
+#define reg_pinmux_rw_hwprot___sser1___width 1
+#define reg_pinmux_rw_hwprot___sser1___bit 4
+#define reg_pinmux_rw_hwprot___ata0___lsb 5
+#define reg_pinmux_rw_hwprot___ata0___width 1
+#define reg_pinmux_rw_hwprot___ata0___bit 5
+#define reg_pinmux_rw_hwprot___ata1___lsb 6
+#define reg_pinmux_rw_hwprot___ata1___width 1
+#define reg_pinmux_rw_hwprot___ata1___bit 6
+#define reg_pinmux_rw_hwprot___ata2___lsb 7
+#define reg_pinmux_rw_hwprot___ata2___width 1
+#define reg_pinmux_rw_hwprot___ata2___bit 7
+#define reg_pinmux_rw_hwprot___ata3___lsb 8
+#define reg_pinmux_rw_hwprot___ata3___width 1
+#define reg_pinmux_rw_hwprot___ata3___bit 8
+#define reg_pinmux_rw_hwprot___ata___lsb 9
+#define reg_pinmux_rw_hwprot___ata___width 1
+#define reg_pinmux_rw_hwprot___ata___bit 9
+#define reg_pinmux_rw_hwprot___eth1___lsb 10
+#define reg_pinmux_rw_hwprot___eth1___width 1
+#define reg_pinmux_rw_hwprot___eth1___bit 10
+#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11
+#define reg_pinmux_rw_hwprot___eth1_mgm___width 1
+#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11
+#define reg_pinmux_rw_hwprot___timer___lsb 12
+#define reg_pinmux_rw_hwprot___timer___width 1
+#define reg_pinmux_rw_hwprot___timer___bit 12
+#define reg_pinmux_rw_hwprot___p21___lsb 13
+#define reg_pinmux_rw_hwprot___p21___width 1
+#define reg_pinmux_rw_hwprot___p21___bit 13
+#define reg_pinmux_rw_hwprot_offset 4
+
+/* Register rw_pb_gio, scope pinmux, type rw */
+#define reg_pinmux_rw_pb_gio___pb0___lsb 0
+#define reg_pinmux_rw_pb_gio___pb0___width 1
+#define reg_pinmux_rw_pb_gio___pb0___bit 0
+#define reg_pinmux_rw_pb_gio___pb1___lsb 1
+#define reg_pinmux_rw_pb_gio___pb1___width 1
+#define reg_pinmux_rw_pb_gio___pb1___bit 1
+#define reg_pinmux_rw_pb_gio___pb2___lsb 2
+#define reg_pinmux_rw_pb_gio___pb2___width 1
+#define reg_pinmux_rw_pb_gio___pb2___bit 2
+#define reg_pinmux_rw_pb_gio___pb3___lsb 3
+#define reg_pinmux_rw_pb_gio___pb3___width 1
+#define reg_pinmux_rw_pb_gio___pb3___bit 3
+#define reg_pinmux_rw_pb_gio___pb4___lsb 4
+#define reg_pinmux_rw_pb_gio___pb4___width 1
+#define reg_pinmux_rw_pb_gio___pb4___bit 4
+#define reg_pinmux_rw_pb_gio___pb5___lsb 5
+#define reg_pinmux_rw_pb_gio___pb5___width 1
+#define reg_pinmux_rw_pb_gio___pb5___bit 5
+#define reg_pinmux_rw_pb_gio___pb6___lsb 6
+#define reg_pinmux_rw_pb_gio___pb6___width 1
+#define reg_pinmux_rw_pb_gio___pb6___bit 6
+#define reg_pinmux_rw_pb_gio___pb7___lsb 7
+#define reg_pinmux_rw_pb_gio___pb7___width 1
+#define reg_pinmux_rw_pb_gio___pb7___bit 7
+#define reg_pinmux_rw_pb_gio___pb8___lsb 8
+#define reg_pinmux_rw_pb_gio___pb8___width 1
+#define reg_pinmux_rw_pb_gio___pb8___bit 8
+#define reg_pinmux_rw_pb_gio___pb9___lsb 9
+#define reg_pinmux_rw_pb_gio___pb9___width 1
+#define reg_pinmux_rw_pb_gio___pb9___bit 9
+#define reg_pinmux_rw_pb_gio___pb10___lsb 10
+#define reg_pinmux_rw_pb_gio___pb10___width 1
+#define reg_pinmux_rw_pb_gio___pb10___bit 10
+#define reg_pinmux_rw_pb_gio___pb11___lsb 11
+#define reg_pinmux_rw_pb_gio___pb11___width 1
+#define reg_pinmux_rw_pb_gio___pb11___bit 11
+#define reg_pinmux_rw_pb_gio___pb12___lsb 12
+#define reg_pinmux_rw_pb_gio___pb12___width 1
+#define reg_pinmux_rw_pb_gio___pb12___bit 12
+#define reg_pinmux_rw_pb_gio___pb13___lsb 13
+#define reg_pinmux_rw_pb_gio___pb13___width 1
+#define reg_pinmux_rw_pb_gio___pb13___bit 13
+#define reg_pinmux_rw_pb_gio___pb14___lsb 14
+#define reg_pinmux_rw_pb_gio___pb14___width 1
+#define reg_pinmux_rw_pb_gio___pb14___bit 14
+#define reg_pinmux_rw_pb_gio___pb15___lsb 15
+#define reg_pinmux_rw_pb_gio___pb15___width 1
+#define reg_pinmux_rw_pb_gio___pb15___bit 15
+#define reg_pinmux_rw_pb_gio___pb16___lsb 16
+#define reg_pinmux_rw_pb_gio___pb16___width 1
+#define reg_pinmux_rw_pb_gio___pb16___bit 16
+#define reg_pinmux_rw_pb_gio___pb17___lsb 17
+#define reg_pinmux_rw_pb_gio___pb17___width 1
+#define reg_pinmux_rw_pb_gio___pb17___bit 17
+#define reg_pinmux_rw_pb_gio_offset 8
+
+/* Register rw_pb_iop, scope pinmux, type rw */
+#define reg_pinmux_rw_pb_iop___pb0___lsb 0
+#define reg_pinmux_rw_pb_iop___pb0___width 1
+#define reg_pinmux_rw_pb_iop___pb0___bit 0
+#define reg_pinmux_rw_pb_iop___pb1___lsb 1
+#define reg_pinmux_rw_pb_iop___pb1___width 1
+#define reg_pinmux_rw_pb_iop___pb1___bit 1
+#define reg_pinmux_rw_pb_iop___pb2___lsb 2
+#define reg_pinmux_rw_pb_iop___pb2___width 1
+#define reg_pinmux_rw_pb_iop___pb2___bit 2
+#define reg_pinmux_rw_pb_iop___pb3___lsb 3
+#define reg_pinmux_rw_pb_iop___pb3___width 1
+#define reg_pinmux_rw_pb_iop___pb3___bit 3
+#define reg_pinmux_rw_pb_iop___pb4___lsb 4
+#define reg_pinmux_rw_pb_iop___pb4___width 1
+#define reg_pinmux_rw_pb_iop___pb4___bit 4
+#define reg_pinmux_rw_pb_iop___pb5___lsb 5
+#define reg_pinmux_rw_pb_iop___pb5___width 1
+#define reg_pinmux_rw_pb_iop___pb5___bit 5
+#define reg_pinmux_rw_pb_iop___pb6___lsb 6
+#define reg_pinmux_rw_pb_iop___pb6___width 1
+#define reg_pinmux_rw_pb_iop___pb6___bit 6
+#define reg_pinmux_rw_pb_iop___pb7___lsb 7
+#define reg_pinmux_rw_pb_iop___pb7___width 1
+#define reg_pinmux_rw_pb_iop___pb7___bit 7
+#define reg_pinmux_rw_pb_iop___pb8___lsb 8
+#define reg_pinmux_rw_pb_iop___pb8___width 1
+#define reg_pinmux_rw_pb_iop___pb8___bit 8
+#define reg_pinmux_rw_pb_iop___pb9___lsb 9
+#define reg_pinmux_rw_pb_iop___pb9___width 1
+#define reg_pinmux_rw_pb_iop___pb9___bit 9
+#define reg_pinmux_rw_pb_iop___pb10___lsb 10
+#define reg_pinmux_rw_pb_iop___pb10___width 1
+#define reg_pinmux_rw_pb_iop___pb10___bit 10
+#define reg_pinmux_rw_pb_iop___pb11___lsb 11
+#define reg_pinmux_rw_pb_iop___pb11___width 1
+#define reg_pinmux_rw_pb_iop___pb11___bit 11
+#define reg_pinmux_rw_pb_iop___pb12___lsb 12
+#define reg_pinmux_rw_pb_iop___pb12___width 1
+#define reg_pinmux_rw_pb_iop___pb12___bit 12
+#define reg_pinmux_rw_pb_iop___pb13___lsb 13
+#define reg_pinmux_rw_pb_iop___pb13___width 1
+#define reg_pinmux_rw_pb_iop___pb13___bit 13
+#define reg_pinmux_rw_pb_iop___pb14___lsb 14
+#define reg_pinmux_rw_pb_iop___pb14___width 1
+#define reg_pinmux_rw_pb_iop___pb14___bit 14
+#define reg_pinmux_rw_pb_iop___pb15___lsb 15
+#define reg_pinmux_rw_pb_iop___pb15___width 1
+#define reg_pinmux_rw_pb_iop___pb15___bit 15
+#define reg_pinmux_rw_pb_iop___pb16___lsb 16
+#define reg_pinmux_rw_pb_iop___pb16___width 1
+#define reg_pinmux_rw_pb_iop___pb16___bit 16
+#define reg_pinmux_rw_pb_iop___pb17___lsb 17
+#define reg_pinmux_rw_pb_iop___pb17___width 1
+#define reg_pinmux_rw_pb_iop___pb17___bit 17
+#define reg_pinmux_rw_pb_iop_offset 12
+
+/* Register rw_pc_gio, scope pinmux, type rw */
+#define reg_pinmux_rw_pc_gio___pc0___lsb 0
+#define reg_pinmux_rw_pc_gio___pc0___width 1
+#define reg_pinmux_rw_pc_gio___pc0___bit 0
+#define reg_pinmux_rw_pc_gio___pc1___lsb 1
+#define reg_pinmux_rw_pc_gio___pc1___width 1
+#define reg_pinmux_rw_pc_gio___pc1___bit 1
+#define reg_pinmux_rw_pc_gio___pc2___lsb 2
+#define reg_pinmux_rw_pc_gio___pc2___width 1
+#define reg_pinmux_rw_pc_gio___pc2___bit 2
+#define reg_pinmux_rw_pc_gio___pc3___lsb 3
+#define reg_pinmux_rw_pc_gio___pc3___width 1
+#define reg_pinmux_rw_pc_gio___pc3___bit 3
+#define reg_pinmux_rw_pc_gio___pc4___lsb 4
+#define reg_pinmux_rw_pc_gio___pc4___width 1
+#define reg_pinmux_rw_pc_gio___pc4___bit 4
+#define reg_pinmux_rw_pc_gio___pc5___lsb 5
+#define reg_pinmux_rw_pc_gio___pc5___width 1
+#define reg_pinmux_rw_pc_gio___pc5___bit 5
+#define reg_pinmux_rw_pc_gio___pc6___lsb 6
+#define reg_pinmux_rw_pc_gio___pc6___width 1
+#define reg_pinmux_rw_pc_gio___pc6___bit 6
+#define reg_pinmux_rw_pc_gio___pc7___lsb 7
+#define reg_pinmux_rw_pc_gio___pc7___width 1
+#define reg_pinmux_rw_pc_gio___pc7___bit 7
+#define reg_pinmux_rw_pc_gio___pc8___lsb 8
+#define reg_pinmux_rw_pc_gio___pc8___width 1
+#define reg_pinmux_rw_pc_gio___pc8___bit 8
+#define reg_pinmux_rw_pc_gio___pc9___lsb 9
+#define reg_pinmux_rw_pc_gio___pc9___width 1
+#define reg_pinmux_rw_pc_gio___pc9___bit 9
+#define reg_pinmux_rw_pc_gio___pc10___lsb 10
+#define reg_pinmux_rw_pc_gio___pc10___width 1
+#define reg_pinmux_rw_pc_gio___pc10___bit 10
+#define reg_pinmux_rw_pc_gio___pc11___lsb 11
+#define reg_pinmux_rw_pc_gio___pc11___width 1
+#define reg_pinmux_rw_pc_gio___pc11___bit 11
+#define reg_pinmux_rw_pc_gio___pc12___lsb 12
+#define reg_pinmux_rw_pc_gio___pc12___width 1
+#define reg_pinmux_rw_pc_gio___pc12___bit 12
+#define reg_pinmux_rw_pc_gio___pc13___lsb 13
+#define reg_pinmux_rw_pc_gio___pc13___width 1
+#define reg_pinmux_rw_pc_gio___pc13___bit 13
+#define reg_pinmux_rw_pc_gio___pc14___lsb 14
+#define reg_pinmux_rw_pc_gio___pc14___width 1
+#define reg_pinmux_rw_pc_gio___pc14___bit 14
+#define reg_pinmux_rw_pc_gio___pc15___lsb 15
+#define reg_pinmux_rw_pc_gio___pc15___width 1
+#define reg_pinmux_rw_pc_gio___pc15___bit 15
+#define reg_pinmux_rw_pc_gio___pc16___lsb 16
+#define reg_pinmux_rw_pc_gio___pc16___width 1
+#define reg_pinmux_rw_pc_gio___pc16___bit 16
+#define reg_pinmux_rw_pc_gio___pc17___lsb 17
+#define reg_pinmux_rw_pc_gio___pc17___width 1
+#define reg_pinmux_rw_pc_gio___pc17___bit 17
+#define reg_pinmux_rw_pc_gio_offset 16
+
+/* Register rw_pc_iop, scope pinmux, type rw */
+#define reg_pinmux_rw_pc_iop___pc0___lsb 0
+#define reg_pinmux_rw_pc_iop___pc0___width 1
+#define reg_pinmux_rw_pc_iop___pc0___bit 0
+#define reg_pinmux_rw_pc_iop___pc1___lsb 1
+#define reg_pinmux_rw_pc_iop___pc1___width 1
+#define reg_pinmux_rw_pc_iop___pc1___bit 1
+#define reg_pinmux_rw_pc_iop___pc2___lsb 2
+#define reg_pinmux_rw_pc_iop___pc2___width 1
+#define reg_pinmux_rw_pc_iop___pc2___bit 2
+#define reg_pinmux_rw_pc_iop___pc3___lsb 3
+#define reg_pinmux_rw_pc_iop___pc3___width 1
+#define reg_pinmux_rw_pc_iop___pc3___bit 3
+#define reg_pinmux_rw_pc_iop___pc4___lsb 4
+#define reg_pinmux_rw_pc_iop___pc4___width 1
+#define reg_pinmux_rw_pc_iop___pc4___bit 4
+#define reg_pinmux_rw_pc_iop___pc5___lsb 5
+#define reg_pinmux_rw_pc_iop___pc5___width 1
+#define reg_pinmux_rw_pc_iop___pc5___bit 5
+#define reg_pinmux_rw_pc_iop___pc6___lsb 6
+#define reg_pinmux_rw_pc_iop___pc6___width 1
+#define reg_pinmux_rw_pc_iop___pc6___bit 6
+#define reg_pinmux_rw_pc_iop___pc7___lsb 7
+#define reg_pinmux_rw_pc_iop___pc7___width 1
+#define reg_pinmux_rw_pc_iop___pc7___bit 7
+#define reg_pinmux_rw_pc_iop___pc8___lsb 8
+#define reg_pinmux_rw_pc_iop___pc8___width 1
+#define reg_pinmux_rw_pc_iop___pc8___bit 8
+#define reg_pinmux_rw_pc_iop___pc9___lsb 9
+#define reg_pinmux_rw_pc_iop___pc9___width 1
+#define reg_pinmux_rw_pc_iop___pc9___bit 9
+#define reg_pinmux_rw_pc_iop___pc10___lsb 10
+#define reg_pinmux_rw_pc_iop___pc10___width 1
+#define reg_pinmux_rw_pc_iop___pc10___bit 10
+#define reg_pinmux_rw_pc_iop___pc11___lsb 11
+#define reg_pinmux_rw_pc_iop___pc11___width 1
+#define reg_pinmux_rw_pc_iop___pc11___bit 11
+#define reg_pinmux_rw_pc_iop___pc12___lsb 12
+#define reg_pinmux_rw_pc_iop___pc12___width 1
+#define reg_pinmux_rw_pc_iop___pc12___bit 12
+#define reg_pinmux_rw_pc_iop___pc13___lsb 13
+#define reg_pinmux_rw_pc_iop___pc13___width 1
+#define reg_pinmux_rw_pc_iop___pc13___bit 13
+#define reg_pinmux_rw_pc_iop___pc14___lsb 14
+#define reg_pinmux_rw_pc_iop___pc14___width 1
+#define reg_pinmux_rw_pc_iop___pc14___bit 14
+#define reg_pinmux_rw_pc_iop___pc15___lsb 15
+#define reg_pinmux_rw_pc_iop___pc15___width 1
+#define reg_pinmux_rw_pc_iop___pc15___bit 15
+#define reg_pinmux_rw_pc_iop___pc16___lsb 16
+#define reg_pinmux_rw_pc_iop___pc16___width 1
+#define reg_pinmux_rw_pc_iop___pc16___bit 16
+#define reg_pinmux_rw_pc_iop___pc17___lsb 17
+#define reg_pinmux_rw_pc_iop___pc17___width 1
+#define reg_pinmux_rw_pc_iop___pc17___bit 17
+#define reg_pinmux_rw_pc_iop_offset 20
+
+/* Register rw_pd_gio, scope pinmux, type rw */
+#define reg_pinmux_rw_pd_gio___pd0___lsb 0
+#define reg_pinmux_rw_pd_gio___pd0___width 1
+#define reg_pinmux_rw_pd_gio___pd0___bit 0
+#define reg_pinmux_rw_pd_gio___pd1___lsb 1
+#define reg_pinmux_rw_pd_gio___pd1___width 1
+#define reg_pinmux_rw_pd_gio___pd1___bit 1
+#define reg_pinmux_rw_pd_gio___pd2___lsb 2
+#define reg_pinmux_rw_pd_gio___pd2___width 1
+#define reg_pinmux_rw_pd_gio___pd2___bit 2
+#define reg_pinmux_rw_pd_gio___pd3___lsb 3
+#define reg_pinmux_rw_pd_gio___pd3___width 1
+#define reg_pinmux_rw_pd_gio___pd3___bit 3
+#define reg_pinmux_rw_pd_gio___pd4___lsb 4
+#define reg_pinmux_rw_pd_gio___pd4___width 1
+#define reg_pinmux_rw_pd_gio___pd4___bit 4
+#define reg_pinmux_rw_pd_gio___pd5___lsb 5
+#define reg_pinmux_rw_pd_gio___pd5___width 1
+#define reg_pinmux_rw_pd_gio___pd5___bit 5
+#define reg_pinmux_rw_pd_gio___pd6___lsb 6
+#define reg_pinmux_rw_pd_gio___pd6___width 1
+#define reg_pinmux_rw_pd_gio___pd6___bit 6
+#define reg_pinmux_rw_pd_gio___pd7___lsb 7
+#define reg_pinmux_rw_pd_gio___pd7___width 1
+#define reg_pinmux_rw_pd_gio___pd7___bit 7
+#define reg_pinmux_rw_pd_gio___pd8___lsb 8
+#define reg_pinmux_rw_pd_gio___pd8___width 1
+#define reg_pinmux_rw_pd_gio___pd8___bit 8
+#define reg_pinmux_rw_pd_gio___pd9___lsb 9
+#define reg_pinmux_rw_pd_gio___pd9___width 1
+#define reg_pinmux_rw_pd_gio___pd9___bit 9
+#define reg_pinmux_rw_pd_gio___pd10___lsb 10
+#define reg_pinmux_rw_pd_gio___pd10___width 1
+#define reg_pinmux_rw_pd_gio___pd10___bit 10
+#define reg_pinmux_rw_pd_gio___pd11___lsb 11
+#define reg_pinmux_rw_pd_gio___pd11___width 1
+#define reg_pinmux_rw_pd_gio___pd11___bit 11
+#define reg_pinmux_rw_pd_gio___pd12___lsb 12
+#define reg_pinmux_rw_pd_gio___pd12___width 1
+#define reg_pinmux_rw_pd_gio___pd12___bit 12
+#define reg_pinmux_rw_pd_gio___pd13___lsb 13
+#define reg_pinmux_rw_pd_gio___pd13___width 1
+#define reg_pinmux_rw_pd_gio___pd13___bit 13
+#define reg_pinmux_rw_pd_gio___pd14___lsb 14
+#define reg_pinmux_rw_pd_gio___pd14___width 1
+#define reg_pinmux_rw_pd_gio___pd14___bit 14
+#define reg_pinmux_rw_pd_gio___pd15___lsb 15
+#define reg_pinmux_rw_pd_gio___pd15___width 1
+#define reg_pinmux_rw_pd_gio___pd15___bit 15
+#define reg_pinmux_rw_pd_gio___pd16___lsb 16
+#define reg_pinmux_rw_pd_gio___pd16___width 1
+#define reg_pinmux_rw_pd_gio___pd16___bit 16
+#define reg_pinmux_rw_pd_gio___pd17___lsb 17
+#define reg_pinmux_rw_pd_gio___pd17___width 1
+#define reg_pinmux_rw_pd_gio___pd17___bit 17
+#define reg_pinmux_rw_pd_gio_offset 24
+
+/* Register rw_pd_iop, scope pinmux, type rw */
+#define reg_pinmux_rw_pd_iop___pd0___lsb 0
+#define reg_pinmux_rw_pd_iop___pd0___width 1
+#define reg_pinmux_rw_pd_iop___pd0___bit 0
+#define reg_pinmux_rw_pd_iop___pd1___lsb 1
+#define reg_pinmux_rw_pd_iop___pd1___width 1
+#define reg_pinmux_rw_pd_iop___pd1___bit 1
+#define reg_pinmux_rw_pd_iop___pd2___lsb 2
+#define reg_pinmux_rw_pd_iop___pd2___width 1
+#define reg_pinmux_rw_pd_iop___pd2___bit 2
+#define reg_pinmux_rw_pd_iop___pd3___lsb 3
+#define reg_pinmux_rw_pd_iop___pd3___width 1
+#define reg_pinmux_rw_pd_iop___pd3___bit 3
+#define reg_pinmux_rw_pd_iop___pd4___lsb 4
+#define reg_pinmux_rw_pd_iop___pd4___width 1
+#define reg_pinmux_rw_pd_iop___pd4___bit 4
+#define reg_pinmux_rw_pd_iop___pd5___lsb 5
+#define reg_pinmux_rw_pd_iop___pd5___width 1
+#define reg_pinmux_rw_pd_iop___pd5___bit 5
+#define reg_pinmux_rw_pd_iop___pd6___lsb 6
+#define reg_pinmux_rw_pd_iop___pd6___width 1
+#define reg_pinmux_rw_pd_iop___pd6___bit 6
+#define reg_pinmux_rw_pd_iop___pd7___lsb 7
+#define reg_pinmux_rw_pd_iop___pd7___width 1
+#define reg_pinmux_rw_pd_iop___pd7___bit 7
+#define reg_pinmux_rw_pd_iop___pd8___lsb 8
+#define reg_pinmux_rw_pd_iop___pd8___width 1
+#define reg_pinmux_rw_pd_iop___pd8___bit 8
+#define reg_pinmux_rw_pd_iop___pd9___lsb 9
+#define reg_pinmux_rw_pd_iop___pd9___width 1
+#define reg_pinmux_rw_pd_iop___pd9___bit 9
+#define reg_pinmux_rw_pd_iop___pd10___lsb 10
+#define reg_pinmux_rw_pd_iop___pd10___width 1
+#define reg_pinmux_rw_pd_iop___pd10___bit 10
+#define reg_pinmux_rw_pd_iop___pd11___lsb 11
+#define reg_pinmux_rw_pd_iop___pd11___width 1
+#define reg_pinmux_rw_pd_iop___pd11___bit 11
+#define reg_pinmux_rw_pd_iop___pd12___lsb 12
+#define reg_pinmux_rw_pd_iop___pd12___width 1
+#define reg_pinmux_rw_pd_iop___pd12___bit 12
+#define reg_pinmux_rw_pd_iop___pd13___lsb 13
+#define reg_pinmux_rw_pd_iop___pd13___width 1
+#define reg_pinmux_rw_pd_iop___pd13___bit 13
+#define reg_pinmux_rw_pd_iop___pd14___lsb 14
+#define reg_pinmux_rw_pd_iop___pd14___width 1
+#define reg_pinmux_rw_pd_iop___pd14___bit 14
+#define reg_pinmux_rw_pd_iop___pd15___lsb 15
+#define reg_pinmux_rw_pd_iop___pd15___width 1
+#define reg_pinmux_rw_pd_iop___pd15___bit 15
+#define reg_pinmux_rw_pd_iop___pd16___lsb 16
+#define reg_pinmux_rw_pd_iop___pd16___width 1
+#define reg_pinmux_rw_pd_iop___pd16___bit 16
+#define reg_pinmux_rw_pd_iop___pd17___lsb 17
+#define reg_pinmux_rw_pd_iop___pd17___width 1
+#define reg_pinmux_rw_pd_iop___pd17___bit 17
+#define reg_pinmux_rw_pd_iop_offset 28
+
+/* Register rw_pe_gio, scope pinmux, type rw */
+#define reg_pinmux_rw_pe_gio___pe0___lsb 0
+#define reg_pinmux_rw_pe_gio___pe0___width 1
+#define reg_pinmux_rw_pe_gio___pe0___bit 0
+#define reg_pinmux_rw_pe_gio___pe1___lsb 1
+#define reg_pinmux_rw_pe_gio___pe1___width 1
+#define reg_pinmux_rw_pe_gio___pe1___bit 1
+#define reg_pinmux_rw_pe_gio___pe2___lsb 2
+#define reg_pinmux_rw_pe_gio___pe2___width 1
+#define reg_pinmux_rw_pe_gio___pe2___bit 2
+#define reg_pinmux_rw_pe_gio___pe3___lsb 3
+#define reg_pinmux_rw_pe_gio___pe3___width 1
+#define reg_pinmux_rw_pe_gio___pe3___bit 3
+#define reg_pinmux_rw_pe_gio___pe4___lsb 4
+#define reg_pinmux_rw_pe_gio___pe4___width 1
+#define reg_pinmux_rw_pe_gio___pe4___bit 4
+#define reg_pinmux_rw_pe_gio___pe5___lsb 5
+#define reg_pinmux_rw_pe_gio___pe5___width 1
+#define reg_pinmux_rw_pe_gio___pe5___bit 5
+#define reg_pinmux_rw_pe_gio___pe6___lsb 6
+#define reg_pinmux_rw_pe_gio___pe6___width 1
+#define reg_pinmux_rw_pe_gio___pe6___bit 6
+#define reg_pinmux_rw_pe_gio___pe7___lsb 7
+#define reg_pinmux_rw_pe_gio___pe7___width 1
+#define reg_pinmux_rw_pe_gio___pe7___bit 7
+#define reg_pinmux_rw_pe_gio___pe8___lsb 8
+#define reg_pinmux_rw_pe_gio___pe8___width 1
+#define reg_pinmux_rw_pe_gio___pe8___bit 8
+#define reg_pinmux_rw_pe_gio___pe9___lsb 9
+#define reg_pinmux_rw_pe_gio___pe9___width 1
+#define reg_pinmux_rw_pe_gio___pe9___bit 9
+#define reg_pinmux_rw_pe_gio___pe10___lsb 10
+#define reg_pinmux_rw_pe_gio___pe10___width 1
+#define reg_pinmux_rw_pe_gio___pe10___bit 10
+#define reg_pinmux_rw_pe_gio___pe11___lsb 11
+#define reg_pinmux_rw_pe_gio___pe11___width 1
+#define reg_pinmux_rw_pe_gio___pe11___bit 11
+#define reg_pinmux_rw_pe_gio___pe12___lsb 12
+#define reg_pinmux_rw_pe_gio___pe12___width 1
+#define reg_pinmux_rw_pe_gio___pe12___bit 12
+#define reg_pinmux_rw_pe_gio___pe13___lsb 13
+#define reg_pinmux_rw_pe_gio___pe13___width 1
+#define reg_pinmux_rw_pe_gio___pe13___bit 13
+#define reg_pinmux_rw_pe_gio___pe14___lsb 14
+#define reg_pinmux_rw_pe_gio___pe14___width 1
+#define reg_pinmux_rw_pe_gio___pe14___bit 14
+#define reg_pinmux_rw_pe_gio___pe15___lsb 15
+#define reg_pinmux_rw_pe_gio___pe15___width 1
+#define reg_pinmux_rw_pe_gio___pe15___bit 15
+#define reg_pinmux_rw_pe_gio___pe16___lsb 16
+#define reg_pinmux_rw_pe_gio___pe16___width 1
+#define reg_pinmux_rw_pe_gio___pe16___bit 16
+#define reg_pinmux_rw_pe_gio___pe17___lsb 17
+#define reg_pinmux_rw_pe_gio___pe17___width 1
+#define reg_pinmux_rw_pe_gio___pe17___bit 17
+#define reg_pinmux_rw_pe_gio_offset 32
+
+/* Register rw_pe_iop, scope pinmux, type rw */
+#define reg_pinmux_rw_pe_iop___pe0___lsb 0
+#define reg_pinmux_rw_pe_iop___pe0___width 1
+#define reg_pinmux_rw_pe_iop___pe0___bit 0
+#define reg_pinmux_rw_pe_iop___pe1___lsb 1
+#define reg_pinmux_rw_pe_iop___pe1___width 1
+#define reg_pinmux_rw_pe_iop___pe1___bit 1
+#define reg_pinmux_rw_pe_iop___pe2___lsb 2
+#define reg_pinmux_rw_pe_iop___pe2___width 1
+#define reg_pinmux_rw_pe_iop___pe2___bit 2
+#define reg_pinmux_rw_pe_iop___pe3___lsb 3
+#define reg_pinmux_rw_pe_iop___pe3___width 1
+#define reg_pinmux_rw_pe_iop___pe3___bit 3
+#define reg_pinmux_rw_pe_iop___pe4___lsb 4
+#define reg_pinmux_rw_pe_iop___pe4___width 1
+#define reg_pinmux_rw_pe_iop___pe4___bit 4
+#define reg_pinmux_rw_pe_iop___pe5___lsb 5
+#define reg_pinmux_rw_pe_iop___pe5___width 1
+#define reg_pinmux_rw_pe_iop___pe5___bit 5
+#define reg_pinmux_rw_pe_iop___pe6___lsb 6
+#define reg_pinmux_rw_pe_iop___pe6___width 1
+#define reg_pinmux_rw_pe_iop___pe6___bit 6
+#define reg_pinmux_rw_pe_iop___pe7___lsb 7
+#define reg_pinmux_rw_pe_iop___pe7___width 1
+#define reg_pinmux_rw_pe_iop___pe7___bit 7
+#define reg_pinmux_rw_pe_iop___pe8___lsb 8
+#define reg_pinmux_rw_pe_iop___pe8___width 1
+#define reg_pinmux_rw_pe_iop___pe8___bit 8
+#define reg_pinmux_rw_pe_iop___pe9___lsb 9
+#define reg_pinmux_rw_pe_iop___pe9___width 1
+#define reg_pinmux_rw_pe_iop___pe9___bit 9
+#define reg_pinmux_rw_pe_iop___pe10___lsb 10
+#define reg_pinmux_rw_pe_iop___pe10___width 1
+#define reg_pinmux_rw_pe_iop___pe10___bit 10
+#define reg_pinmux_rw_pe_iop___pe11___lsb 11
+#define reg_pinmux_rw_pe_iop___pe11___width 1
+#define reg_pinmux_rw_pe_iop___pe11___bit 11
+#define reg_pinmux_rw_pe_iop___pe12___lsb 12
+#define reg_pinmux_rw_pe_iop___pe12___width 1
+#define reg_pinmux_rw_pe_iop___pe12___bit 12
+#define reg_pinmux_rw_pe_iop___pe13___lsb 13
+#define reg_pinmux_rw_pe_iop___pe13___width 1
+#define reg_pinmux_rw_pe_iop___pe13___bit 13
+#define reg_pinmux_rw_pe_iop___pe14___lsb 14
+#define reg_pinmux_rw_pe_iop___pe14___width 1
+#define reg_pinmux_rw_pe_iop___pe14___bit 14
+#define reg_pinmux_rw_pe_iop___pe15___lsb 15
+#define reg_pinmux_rw_pe_iop___pe15___width 1
+#define reg_pinmux_rw_pe_iop___pe15___bit 15
+#define reg_pinmux_rw_pe_iop___pe16___lsb 16
+#define reg_pinmux_rw_pe_iop___pe16___width 1
+#define reg_pinmux_rw_pe_iop___pe16___bit 16
+#define reg_pinmux_rw_pe_iop___pe17___lsb 17
+#define reg_pinmux_rw_pe_iop___pe17___width 1
+#define reg_pinmux_rw_pe_iop___pe17___bit 17
+#define reg_pinmux_rw_pe_iop_offset 36
+
+/* Register rw_usb_phy, scope pinmux, type rw */
+#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0
+#define reg_pinmux_rw_usb_phy___en_usb0___width 1
+#define reg_pinmux_rw_usb_phy___en_usb0___bit 0
+#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1
+#define reg_pinmux_rw_usb_phy___en_usb1___width 1
+#define reg_pinmux_rw_usb_phy___en_usb1___bit 1
+#define reg_pinmux_rw_usb_phy_offset 40
+
+
+/* Constants */
+#define regk_pinmux_no                            0x00000000
+#define regk_pinmux_rw_hwprot_default             0x00000000
+#define regk_pinmux_rw_pa_default                 0x00000000
+#define regk_pinmux_rw_pb_gio_default             0x00000000
+#define regk_pinmux_rw_pb_iop_default             0x00000000
+#define regk_pinmux_rw_pc_gio_default             0x00000000
+#define regk_pinmux_rw_pc_iop_default             0x00000000
+#define regk_pinmux_rw_pd_gio_default             0x00000000
+#define regk_pinmux_rw_pd_iop_default             0x00000000
+#define regk_pinmux_rw_pe_gio_default             0x00000000
+#define regk_pinmux_rw_pe_iop_default             0x00000000
+#define regk_pinmux_rw_usb_phy_default            0x00000000
+#define regk_pinmux_yes                           0x00000001
+#endif /* __pinmux_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h b/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h
new file mode 100644
index 00000000000..76959b70cd2
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h
@@ -0,0 +1,96 @@
+#ifndef __reg_map_h
+#define __reg_map_h
+
+/*
+ * This file is autogenerated from
+ *   file:            ../../mod/fakereg.rmap
+ *     id:            fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp
+ *     last modified: Wed Feb 11 20:53:25 2004
+ *   file:            ../../rtl/global.rmap
+ *     id:            global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp
+ *     last modified: Mon Aug 18 17:08:23 2003
+ *   file:            ../../mod/modreg.rmap
+ *     id:            modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp
+ *     last modified: Fri Feb 20 16:40:04 2004
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
+ *      id: $Id: reg_map_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+#define regi_artpec_mod                           0xb7044000
+#define regi_ata                                  0xb0032000
+#define regi_ata_mod                              0xb7006000
+#define regi_barber                               0xb701a000
+#define regi_bif_core                             0xb0014000
+#define regi_bif_dma                              0xb0016000
+#define regi_bif_slave                            0xb0018000
+#define regi_bif_slave_ext                        0xac000000
+#define regi_bus_master                           0xb703c000
+#define regi_config                               0xb003c000
+#define regi_dma0                                 0xb0000000
+#define regi_dma1                                 0xb0002000
+#define regi_dma2                                 0xb0004000
+#define regi_dma3                                 0xb0006000
+#define regi_dma4                                 0xb0008000
+#define regi_dma5                                 0xb000a000
+#define regi_dma6                                 0xb000c000
+#define regi_dma7                                 0xb000e000
+#define regi_dma8                                 0xb0010000
+#define regi_dma9                                 0xb0012000
+#define regi_eth0                                 0xb0034000
+#define regi_eth1                                 0xb0036000
+#define regi_eth_mod                              0xb7004000
+#define regi_eth_mod1                             0xb701c000
+#define regi_eth_strmod                           0xb7008000
+#define regi_eth_strmod1                          0xb7032000
+#define regi_ext_dma                              0xb703a000
+#define regi_ext_mem                              0xb7046000
+#define regi_gen_io                               0xb7016000
+#define regi_gio                                  0xb001a000
+#define regi_hook                                 0xb7000000
+#define regi_iop                                  0xb0020000
+#define regi_irq                                  0xb001c000
+#define regi_irq_nmi                              0xb701e000
+#define regi_marb                                 0xb003e000
+#define regi_marb_bp0                             0xb003e240
+#define regi_marb_bp1                             0xb003e280
+#define regi_marb_bp2                             0xb003e2c0
+#define regi_marb_bp3                             0xb003e300
+#define regi_nand_mod                             0xb7014000
+#define regi_p21                                  0xb002e000
+#define regi_p21_mod                              0xb7042000
+#define regi_pci_mod                              0xb7010000
+#define regi_pin_test                             0xb7018000
+#define regi_pinmux                               0xb0038000
+#define regi_sdram_chk                            0xb703e000
+#define regi_sdram_mod                            0xb7012000
+#define regi_ser0                                 0xb0026000
+#define regi_ser1                                 0xb0028000
+#define regi_ser2                                 0xb002a000
+#define regi_ser3                                 0xb002c000
+#define regi_ser_mod0                             0xb7020000
+#define regi_ser_mod1                             0xb7022000
+#define regi_ser_mod2                             0xb7024000
+#define regi_ser_mod3                             0xb7026000
+#define regi_smif_stat                            0xb700e000
+#define regi_sser0                                0xb0022000
+#define regi_sser1                                0xb0024000
+#define regi_sser_mod0                            0xb700a000
+#define regi_sser_mod1                            0xb700c000
+#define regi_strcop                               0xb0030000
+#define regi_strmux                               0xb003a000
+#define regi_strmux_tst                           0xb7040000
+#define regi_tap                                  0xb7002000
+#define regi_timer                                0xb001e000
+#define regi_timer_mod                            0xb7034000
+#define regi_trace                                0xb0040000
+#define regi_usb0                                 0xb7028000
+#define regi_usb1                                 0xb702a000
+#define regi_usb2                                 0xb702c000
+#define regi_usb3                                 0xb702e000
+#define regi_usb_dev                              0xb7030000
+#define regi_utmi_mod0                            0xb7036000
+#define regi_utmi_mod1                            0xb7038000
+#endif /* __reg_map_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h
new file mode 100644
index 00000000000..10246f49fb2
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/rt_trace_defs_asm.h
@@ -0,0 +1,142 @@
+#ifndef __rt_trace_defs_asm_h
+#define __rt_trace_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/rt_trace/rtl/rt_regs.r
+ *     id:           rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp
+ *     last modfied: Mon Apr 11 16:09:14 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/rt_trace_defs_asm.h ../../inst/rt_trace/rtl/rt_regs.r
+ *      id: $Id: rt_trace_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope rt_trace, type rw */
+#define reg_rt_trace_rw_cfg___en___lsb 0
+#define reg_rt_trace_rw_cfg___en___width 1
+#define reg_rt_trace_rw_cfg___en___bit 0
+#define reg_rt_trace_rw_cfg___mode___lsb 1
+#define reg_rt_trace_rw_cfg___mode___width 1
+#define reg_rt_trace_rw_cfg___mode___bit 1
+#define reg_rt_trace_rw_cfg___owner___lsb 2
+#define reg_rt_trace_rw_cfg___owner___width 1
+#define reg_rt_trace_rw_cfg___owner___bit 2
+#define reg_rt_trace_rw_cfg___wp___lsb 3
+#define reg_rt_trace_rw_cfg___wp___width 1
+#define reg_rt_trace_rw_cfg___wp___bit 3
+#define reg_rt_trace_rw_cfg___stall___lsb 4
+#define reg_rt_trace_rw_cfg___stall___width 1
+#define reg_rt_trace_rw_cfg___stall___bit 4
+#define reg_rt_trace_rw_cfg___wp_start___lsb 8
+#define reg_rt_trace_rw_cfg___wp_start___width 7
+#define reg_rt_trace_rw_cfg___wp_stop___lsb 16
+#define reg_rt_trace_rw_cfg___wp_stop___width 7
+#define reg_rt_trace_rw_cfg_offset 0
+
+/* Register rw_tap_ctrl, scope rt_trace, type rw */
+#define reg_rt_trace_rw_tap_ctrl___ack_data___lsb 0
+#define reg_rt_trace_rw_tap_ctrl___ack_data___width 1
+#define reg_rt_trace_rw_tap_ctrl___ack_data___bit 0
+#define reg_rt_trace_rw_tap_ctrl___ack_guru___lsb 1
+#define reg_rt_trace_rw_tap_ctrl___ack_guru___width 1
+#define reg_rt_trace_rw_tap_ctrl___ack_guru___bit 1
+#define reg_rt_trace_rw_tap_ctrl_offset 4
+
+/* Register r_tap_stat, scope rt_trace, type r */
+#define reg_rt_trace_r_tap_stat___dav___lsb 0
+#define reg_rt_trace_r_tap_stat___dav___width 1
+#define reg_rt_trace_r_tap_stat___dav___bit 0
+#define reg_rt_trace_r_tap_stat___empty___lsb 1
+#define reg_rt_trace_r_tap_stat___empty___width 1
+#define reg_rt_trace_r_tap_stat___empty___bit 1
+#define reg_rt_trace_r_tap_stat_offset 8
+
+/* Register rw_tap_data, scope rt_trace, type rw */
+#define reg_rt_trace_rw_tap_data_offset 12
+
+/* Register rw_tap_hdata, scope rt_trace, type rw */
+#define reg_rt_trace_rw_tap_hdata___op___lsb 0
+#define reg_rt_trace_rw_tap_hdata___op___width 4
+#define reg_rt_trace_rw_tap_hdata___sub_op___lsb 4
+#define reg_rt_trace_rw_tap_hdata___sub_op___width 4
+#define reg_rt_trace_rw_tap_hdata_offset 16
+
+/* Register r_redir, scope rt_trace, type r */
+#define reg_rt_trace_r_redir_offset 20
+
+
+/* Constants */
+#define regk_rt_trace_brk                         0x0000000c
+#define regk_rt_trace_dbg                         0x00000003
+#define regk_rt_trace_dbgdi                       0x00000004
+#define regk_rt_trace_dbgdo                       0x00000005
+#define regk_rt_trace_gmode                       0x00000000
+#define regk_rt_trace_no                          0x00000000
+#define regk_rt_trace_nop                         0x00000000
+#define regk_rt_trace_normal                      0x00000000
+#define regk_rt_trace_rdmem                       0x00000007
+#define regk_rt_trace_rdmemb                      0x00000009
+#define regk_rt_trace_rdpreg                      0x00000002
+#define regk_rt_trace_rdreg                       0x00000001
+#define regk_rt_trace_rdsreg                      0x00000003
+#define regk_rt_trace_redir                       0x00000006
+#define regk_rt_trace_ret                         0x0000000b
+#define regk_rt_trace_rw_cfg_default              0x00000000
+#define regk_rt_trace_trcfg                       0x00000001
+#define regk_rt_trace_wp                          0x00000001
+#define regk_rt_trace_wp0                         0x00000001
+#define regk_rt_trace_wp1                         0x00000002
+#define regk_rt_trace_wp2                         0x00000004
+#define regk_rt_trace_wp3                         0x00000008
+#define regk_rt_trace_wp4                         0x00000010
+#define regk_rt_trace_wp5                         0x00000020
+#define regk_rt_trace_wp6                         0x00000040
+#define regk_rt_trace_wrmem                       0x00000008
+#define regk_rt_trace_wrmemb                      0x0000000a
+#define regk_rt_trace_wrpreg                      0x00000005
+#define regk_rt_trace_wrreg                       0x00000004
+#define regk_rt_trace_wrsreg                      0x00000006
+#define regk_rt_trace_yes                         0x00000001
+#endif /* __rt_trace_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h
new file mode 100644
index 00000000000..4a2808bdf39
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/ser_defs_asm.h
@@ -0,0 +1,359 @@
+#ifndef __ser_defs_asm_h
+#define __ser_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/ser/rtl/ser_regs.r
+ *     id:           ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp
+ *     last modfied: Mon Apr 11 16:09:21 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ser_defs_asm.h ../../inst/ser/rtl/ser_regs.r
+ *      id: $Id: ser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_tr_ctrl, scope ser, type rw */
+#define reg_ser_rw_tr_ctrl___base_freq___lsb 0
+#define reg_ser_rw_tr_ctrl___base_freq___width 3
+#define reg_ser_rw_tr_ctrl___en___lsb 3
+#define reg_ser_rw_tr_ctrl___en___width 1
+#define reg_ser_rw_tr_ctrl___en___bit 3
+#define reg_ser_rw_tr_ctrl___par___lsb 4
+#define reg_ser_rw_tr_ctrl___par___width 2
+#define reg_ser_rw_tr_ctrl___par_en___lsb 6
+#define reg_ser_rw_tr_ctrl___par_en___width 1
+#define reg_ser_rw_tr_ctrl___par_en___bit 6
+#define reg_ser_rw_tr_ctrl___data_bits___lsb 7
+#define reg_ser_rw_tr_ctrl___data_bits___width 1
+#define reg_ser_rw_tr_ctrl___data_bits___bit 7
+#define reg_ser_rw_tr_ctrl___stop_bits___lsb 8
+#define reg_ser_rw_tr_ctrl___stop_bits___width 1
+#define reg_ser_rw_tr_ctrl___stop_bits___bit 8
+#define reg_ser_rw_tr_ctrl___stop___lsb 9
+#define reg_ser_rw_tr_ctrl___stop___width 1
+#define reg_ser_rw_tr_ctrl___stop___bit 9
+#define reg_ser_rw_tr_ctrl___rts_delay___lsb 10
+#define reg_ser_rw_tr_ctrl___rts_delay___width 3
+#define reg_ser_rw_tr_ctrl___rts_setup___lsb 13
+#define reg_ser_rw_tr_ctrl___rts_setup___width 1
+#define reg_ser_rw_tr_ctrl___rts_setup___bit 13
+#define reg_ser_rw_tr_ctrl___auto_rts___lsb 14
+#define reg_ser_rw_tr_ctrl___auto_rts___width 1
+#define reg_ser_rw_tr_ctrl___auto_rts___bit 14
+#define reg_ser_rw_tr_ctrl___txd___lsb 15
+#define reg_ser_rw_tr_ctrl___txd___width 1
+#define reg_ser_rw_tr_ctrl___txd___bit 15
+#define reg_ser_rw_tr_ctrl___auto_cts___lsb 16
+#define reg_ser_rw_tr_ctrl___auto_cts___width 1
+#define reg_ser_rw_tr_ctrl___auto_cts___bit 16
+#define reg_ser_rw_tr_ctrl_offset 0
+
+/* Register rw_tr_dma_en, scope ser, type rw */
+#define reg_ser_rw_tr_dma_en___en___lsb 0
+#define reg_ser_rw_tr_dma_en___en___width 1
+#define reg_ser_rw_tr_dma_en___en___bit 0
+#define reg_ser_rw_tr_dma_en_offset 4
+
+/* Register rw_rec_ctrl, scope ser, type rw */
+#define reg_ser_rw_rec_ctrl___base_freq___lsb 0
+#define reg_ser_rw_rec_ctrl___base_freq___width 3
+#define reg_ser_rw_rec_ctrl___en___lsb 3
+#define reg_ser_rw_rec_ctrl___en___width 1
+#define reg_ser_rw_rec_ctrl___en___bit 3
+#define reg_ser_rw_rec_ctrl___par___lsb 4
+#define reg_ser_rw_rec_ctrl___par___width 2
+#define reg_ser_rw_rec_ctrl___par_en___lsb 6
+#define reg_ser_rw_rec_ctrl___par_en___width 1
+#define reg_ser_rw_rec_ctrl___par_en___bit 6
+#define reg_ser_rw_rec_ctrl___data_bits___lsb 7
+#define reg_ser_rw_rec_ctrl___data_bits___width 1
+#define reg_ser_rw_rec_ctrl___data_bits___bit 7
+#define reg_ser_rw_rec_ctrl___dma_mode___lsb 8
+#define reg_ser_rw_rec_ctrl___dma_mode___width 1
+#define reg_ser_rw_rec_ctrl___dma_mode___bit 8
+#define reg_ser_rw_rec_ctrl___dma_err___lsb 9
+#define reg_ser_rw_rec_ctrl___dma_err___width 1
+#define reg_ser_rw_rec_ctrl___dma_err___bit 9
+#define reg_ser_rw_rec_ctrl___sampling___lsb 10
+#define reg_ser_rw_rec_ctrl___sampling___width 1
+#define reg_ser_rw_rec_ctrl___sampling___bit 10
+#define reg_ser_rw_rec_ctrl___timeout___lsb 11
+#define reg_ser_rw_rec_ctrl___timeout___width 3
+#define reg_ser_rw_rec_ctrl___auto_eop___lsb 14
+#define reg_ser_rw_rec_ctrl___auto_eop___width 1
+#define reg_ser_rw_rec_ctrl___auto_eop___bit 14
+#define reg_ser_rw_rec_ctrl___half_duplex___lsb 15
+#define reg_ser_rw_rec_ctrl___half_duplex___width 1
+#define reg_ser_rw_rec_ctrl___half_duplex___bit 15
+#define reg_ser_rw_rec_ctrl___rts_n___lsb 16
+#define reg_ser_rw_rec_ctrl___rts_n___width 1
+#define reg_ser_rw_rec_ctrl___rts_n___bit 16
+#define reg_ser_rw_rec_ctrl___loopback___lsb 17
+#define reg_ser_rw_rec_ctrl___loopback___width 1
+#define reg_ser_rw_rec_ctrl___loopback___bit 17
+#define reg_ser_rw_rec_ctrl_offset 8
+
+/* Register rw_tr_baud_div, scope ser, type rw */
+#define reg_ser_rw_tr_baud_div___div___lsb 0
+#define reg_ser_rw_tr_baud_div___div___width 16
+#define reg_ser_rw_tr_baud_div_offset 12
+
+/* Register rw_rec_baud_div, scope ser, type rw */
+#define reg_ser_rw_rec_baud_div___div___lsb 0
+#define reg_ser_rw_rec_baud_div___div___width 16
+#define reg_ser_rw_rec_baud_div_offset 16
+
+/* Register rw_xoff, scope ser, type rw */
+#define reg_ser_rw_xoff___chr___lsb 0
+#define reg_ser_rw_xoff___chr___width 8
+#define reg_ser_rw_xoff___automatic___lsb 8
+#define reg_ser_rw_xoff___automatic___width 1
+#define reg_ser_rw_xoff___automatic___bit 8
+#define reg_ser_rw_xoff_offset 20
+
+/* Register rw_xoff_clr, scope ser, type rw */
+#define reg_ser_rw_xoff_clr___clr___lsb 0
+#define reg_ser_rw_xoff_clr___clr___width 1
+#define reg_ser_rw_xoff_clr___clr___bit 0
+#define reg_ser_rw_xoff_clr_offset 24
+
+/* Register rw_dout, scope ser, type rw */
+#define reg_ser_rw_dout___data___lsb 0
+#define reg_ser_rw_dout___data___width 8
+#define reg_ser_rw_dout_offset 28
+
+/* Register rs_stat_din, scope ser, type rs */
+#define reg_ser_rs_stat_din___data___lsb 0
+#define reg_ser_rs_stat_din___data___width 8
+#define reg_ser_rs_stat_din___dav___lsb 16
+#define reg_ser_rs_stat_din___dav___width 1
+#define reg_ser_rs_stat_din___dav___bit 16
+#define reg_ser_rs_stat_din___framing_err___lsb 17
+#define reg_ser_rs_stat_din___framing_err___width 1
+#define reg_ser_rs_stat_din___framing_err___bit 17
+#define reg_ser_rs_stat_din___par_err___lsb 18
+#define reg_ser_rs_stat_din___par_err___width 1
+#define reg_ser_rs_stat_din___par_err___bit 18
+#define reg_ser_rs_stat_din___orun___lsb 19
+#define reg_ser_rs_stat_din___orun___width 1
+#define reg_ser_rs_stat_din___orun___bit 19
+#define reg_ser_rs_stat_din___rec_err___lsb 20
+#define reg_ser_rs_stat_din___rec_err___width 1
+#define reg_ser_rs_stat_din___rec_err___bit 20
+#define reg_ser_rs_stat_din___rxd___lsb 21
+#define reg_ser_rs_stat_din___rxd___width 1
+#define reg_ser_rs_stat_din___rxd___bit 21
+#define reg_ser_rs_stat_din___tr_idle___lsb 22
+#define reg_ser_rs_stat_din___tr_idle___width 1
+#define reg_ser_rs_stat_din___tr_idle___bit 22
+#define reg_ser_rs_stat_din___tr_empty___lsb 23
+#define reg_ser_rs_stat_din___tr_empty___width 1
+#define reg_ser_rs_stat_din___tr_empty___bit 23
+#define reg_ser_rs_stat_din___tr_rdy___lsb 24
+#define reg_ser_rs_stat_din___tr_rdy___width 1
+#define reg_ser_rs_stat_din___tr_rdy___bit 24
+#define reg_ser_rs_stat_din___cts_n___lsb 25
+#define reg_ser_rs_stat_din___cts_n___width 1
+#define reg_ser_rs_stat_din___cts_n___bit 25
+#define reg_ser_rs_stat_din___xoff_detect___lsb 26
+#define reg_ser_rs_stat_din___xoff_detect___width 1
+#define reg_ser_rs_stat_din___xoff_detect___bit 26
+#define reg_ser_rs_stat_din___rts_n___lsb 27
+#define reg_ser_rs_stat_din___rts_n___width 1
+#define reg_ser_rs_stat_din___rts_n___bit 27
+#define reg_ser_rs_stat_din___txd___lsb 28
+#define reg_ser_rs_stat_din___txd___width 1
+#define reg_ser_rs_stat_din___txd___bit 28
+#define reg_ser_rs_stat_din_offset 32
+
+/* Register r_stat_din, scope ser, type r */
+#define reg_ser_r_stat_din___data___lsb 0
+#define reg_ser_r_stat_din___data___width 8
+#define reg_ser_r_stat_din___dav___lsb 16
+#define reg_ser_r_stat_din___dav___width 1
+#define reg_ser_r_stat_din___dav___bit 16
+#define reg_ser_r_stat_din___framing_err___lsb 17
+#define reg_ser_r_stat_din___framing_err___width 1
+#define reg_ser_r_stat_din___framing_err___bit 17
+#define reg_ser_r_stat_din___par_err___lsb 18
+#define reg_ser_r_stat_din___par_err___width 1
+#define reg_ser_r_stat_din___par_err___bit 18
+#define reg_ser_r_stat_din___orun___lsb 19
+#define reg_ser_r_stat_din___orun___width 1
+#define reg_ser_r_stat_din___orun___bit 19
+#define reg_ser_r_stat_din___rec_err___lsb 20
+#define reg_ser_r_stat_din___rec_err___width 1
+#define reg_ser_r_stat_din___rec_err___bit 20
+#define reg_ser_r_stat_din___rxd___lsb 21
+#define reg_ser_r_stat_din___rxd___width 1
+#define reg_ser_r_stat_din___rxd___bit 21
+#define reg_ser_r_stat_din___tr_idle___lsb 22
+#define reg_ser_r_stat_din___tr_idle___width 1
+#define reg_ser_r_stat_din___tr_idle___bit 22
+#define reg_ser_r_stat_din___tr_empty___lsb 23
+#define reg_ser_r_stat_din___tr_empty___width 1
+#define reg_ser_r_stat_din___tr_empty___bit 23
+#define reg_ser_r_stat_din___tr_rdy___lsb 24
+#define reg_ser_r_stat_din___tr_rdy___width 1
+#define reg_ser_r_stat_din___tr_rdy___bit 24
+#define reg_ser_r_stat_din___cts_n___lsb 25
+#define reg_ser_r_stat_din___cts_n___width 1
+#define reg_ser_r_stat_din___cts_n___bit 25
+#define reg_ser_r_stat_din___xoff_detect___lsb 26
+#define reg_ser_r_stat_din___xoff_detect___width 1
+#define reg_ser_r_stat_din___xoff_detect___bit 26
+#define reg_ser_r_stat_din___rts_n___lsb 27
+#define reg_ser_r_stat_din___rts_n___width 1
+#define reg_ser_r_stat_din___rts_n___bit 27
+#define reg_ser_r_stat_din___txd___lsb 28
+#define reg_ser_r_stat_din___txd___width 1
+#define reg_ser_r_stat_din___txd___bit 28
+#define reg_ser_r_stat_din_offset 36
+
+/* Register rw_rec_eop, scope ser, type rw */
+#define reg_ser_rw_rec_eop___set___lsb 0
+#define reg_ser_rw_rec_eop___set___width 1
+#define reg_ser_rw_rec_eop___set___bit 0
+#define reg_ser_rw_rec_eop_offset 40
+
+/* Register rw_intr_mask, scope ser, type rw */
+#define reg_ser_rw_intr_mask___tr_rdy___lsb 0
+#define reg_ser_rw_intr_mask___tr_rdy___width 1
+#define reg_ser_rw_intr_mask___tr_rdy___bit 0
+#define reg_ser_rw_intr_mask___tr_empty___lsb 1
+#define reg_ser_rw_intr_mask___tr_empty___width 1
+#define reg_ser_rw_intr_mask___tr_empty___bit 1
+#define reg_ser_rw_intr_mask___tr_idle___lsb 2
+#define reg_ser_rw_intr_mask___tr_idle___width 1
+#define reg_ser_rw_intr_mask___tr_idle___bit 2
+#define reg_ser_rw_intr_mask___dav___lsb 3
+#define reg_ser_rw_intr_mask___dav___width 1
+#define reg_ser_rw_intr_mask___dav___bit 3
+#define reg_ser_rw_intr_mask_offset 44
+
+/* Register rw_ack_intr, scope ser, type rw */
+#define reg_ser_rw_ack_intr___tr_rdy___lsb 0
+#define reg_ser_rw_ack_intr___tr_rdy___width 1
+#define reg_ser_rw_ack_intr___tr_rdy___bit 0
+#define reg_ser_rw_ack_intr___tr_empty___lsb 1
+#define reg_ser_rw_ack_intr___tr_empty___width 1
+#define reg_ser_rw_ack_intr___tr_empty___bit 1
+#define reg_ser_rw_ack_intr___tr_idle___lsb 2
+#define reg_ser_rw_ack_intr___tr_idle___width 1
+#define reg_ser_rw_ack_intr___tr_idle___bit 2
+#define reg_ser_rw_ack_intr___dav___lsb 3
+#define reg_ser_rw_ack_intr___dav___width 1
+#define reg_ser_rw_ack_intr___dav___bit 3
+#define reg_ser_rw_ack_intr_offset 48
+
+/* Register r_intr, scope ser, type r */
+#define reg_ser_r_intr___tr_rdy___lsb 0
+#define reg_ser_r_intr___tr_rdy___width 1
+#define reg_ser_r_intr___tr_rdy___bit 0
+#define reg_ser_r_intr___tr_empty___lsb 1
+#define reg_ser_r_intr___tr_empty___width 1
+#define reg_ser_r_intr___tr_empty___bit 1
+#define reg_ser_r_intr___tr_idle___lsb 2
+#define reg_ser_r_intr___tr_idle___width 1
+#define reg_ser_r_intr___tr_idle___bit 2
+#define reg_ser_r_intr___dav___lsb 3
+#define reg_ser_r_intr___dav___width 1
+#define reg_ser_r_intr___dav___bit 3
+#define reg_ser_r_intr_offset 52
+
+/* Register r_masked_intr, scope ser, type r */
+#define reg_ser_r_masked_intr___tr_rdy___lsb 0
+#define reg_ser_r_masked_intr___tr_rdy___width 1
+#define reg_ser_r_masked_intr___tr_rdy___bit 0
+#define reg_ser_r_masked_intr___tr_empty___lsb 1
+#define reg_ser_r_masked_intr___tr_empty___width 1
+#define reg_ser_r_masked_intr___tr_empty___bit 1
+#define reg_ser_r_masked_intr___tr_idle___lsb 2
+#define reg_ser_r_masked_intr___tr_idle___width 1
+#define reg_ser_r_masked_intr___tr_idle___bit 2
+#define reg_ser_r_masked_intr___dav___lsb 3
+#define reg_ser_r_masked_intr___dav___width 1
+#define reg_ser_r_masked_intr___dav___bit 3
+#define reg_ser_r_masked_intr_offset 56
+
+
+/* Constants */
+#define regk_ser_active                           0x00000000
+#define regk_ser_bits1                            0x00000000
+#define regk_ser_bits2                            0x00000001
+#define regk_ser_bits7                            0x00000001
+#define regk_ser_bits8                            0x00000000
+#define regk_ser_del0_5                           0x00000000
+#define regk_ser_del1                             0x00000001
+#define regk_ser_del1_5                           0x00000002
+#define regk_ser_del2                             0x00000003
+#define regk_ser_del2_5                           0x00000004
+#define regk_ser_del3                             0x00000005
+#define regk_ser_del3_5                           0x00000006
+#define regk_ser_del4                             0x00000007
+#define regk_ser_even                             0x00000000
+#define regk_ser_ext                              0x00000001
+#define regk_ser_f100                             0x00000007
+#define regk_ser_f29_493                          0x00000004
+#define regk_ser_f32                              0x00000005
+#define regk_ser_f32_768                          0x00000006
+#define regk_ser_ignore                           0x00000001
+#define regk_ser_inactive                         0x00000001
+#define regk_ser_majority                         0x00000001
+#define regk_ser_mark                             0x00000002
+#define regk_ser_middle                           0x00000000
+#define regk_ser_no                               0x00000000
+#define regk_ser_odd                              0x00000001
+#define regk_ser_off                              0x00000000
+#define regk_ser_rw_intr_mask_default             0x00000000
+#define regk_ser_rw_rec_baud_div_default          0x00000000
+#define regk_ser_rw_rec_ctrl_default              0x00010000
+#define regk_ser_rw_tr_baud_div_default           0x00000000
+#define regk_ser_rw_tr_ctrl_default               0x00008000
+#define regk_ser_rw_tr_dma_en_default             0x00000000
+#define regk_ser_rw_xoff_default                  0x00000000
+#define regk_ser_space                            0x00000003
+#define regk_ser_stop                             0x00000000
+#define regk_ser_yes                              0x00000001
+#endif /* __ser_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h
new file mode 100644
index 00000000000..27d4d91b3ab
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/sser_defs_asm.h
@@ -0,0 +1,462 @@
+#ifndef __sser_defs_asm_h
+#define __sser_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/syncser/rtl/sser_regs.r
+ *     id:           sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp
+ *     last modfied: Mon Apr 11 16:09:48 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/sser_defs_asm.h ../../inst/syncser/rtl/sser_regs.r
+ *      id: $Id: sser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope sser, type rw */
+#define reg_sser_rw_cfg___clk_div___lsb 0
+#define reg_sser_rw_cfg___clk_div___width 16
+#define reg_sser_rw_cfg___base_freq___lsb 16
+#define reg_sser_rw_cfg___base_freq___width 3
+#define reg_sser_rw_cfg___gate_clk___lsb 19
+#define reg_sser_rw_cfg___gate_clk___width 1
+#define reg_sser_rw_cfg___gate_clk___bit 19
+#define reg_sser_rw_cfg___clkgate_ctrl___lsb 20
+#define reg_sser_rw_cfg___clkgate_ctrl___width 1
+#define reg_sser_rw_cfg___clkgate_ctrl___bit 20
+#define reg_sser_rw_cfg___clkgate_in___lsb 21
+#define reg_sser_rw_cfg___clkgate_in___width 1
+#define reg_sser_rw_cfg___clkgate_in___bit 21
+#define reg_sser_rw_cfg___clk_dir___lsb 22
+#define reg_sser_rw_cfg___clk_dir___width 1
+#define reg_sser_rw_cfg___clk_dir___bit 22
+#define reg_sser_rw_cfg___clk_od_mode___lsb 23
+#define reg_sser_rw_cfg___clk_od_mode___width 1
+#define reg_sser_rw_cfg___clk_od_mode___bit 23
+#define reg_sser_rw_cfg___out_clk_pol___lsb 24
+#define reg_sser_rw_cfg___out_clk_pol___width 1
+#define reg_sser_rw_cfg___out_clk_pol___bit 24
+#define reg_sser_rw_cfg___out_clk_src___lsb 25
+#define reg_sser_rw_cfg___out_clk_src___width 2
+#define reg_sser_rw_cfg___clk_in_sel___lsb 27
+#define reg_sser_rw_cfg___clk_in_sel___width 1
+#define reg_sser_rw_cfg___clk_in_sel___bit 27
+#define reg_sser_rw_cfg___hold_pol___lsb 28
+#define reg_sser_rw_cfg___hold_pol___width 1
+#define reg_sser_rw_cfg___hold_pol___bit 28
+#define reg_sser_rw_cfg___prepare___lsb 29
+#define reg_sser_rw_cfg___prepare___width 1
+#define reg_sser_rw_cfg___prepare___bit 29
+#define reg_sser_rw_cfg___en___lsb 30
+#define reg_sser_rw_cfg___en___width 1
+#define reg_sser_rw_cfg___en___bit 30
+#define reg_sser_rw_cfg_offset 0
+
+/* Register rw_frm_cfg, scope sser, type rw */
+#define reg_sser_rw_frm_cfg___wordrate___lsb 0
+#define reg_sser_rw_frm_cfg___wordrate___width 10
+#define reg_sser_rw_frm_cfg___rec_delay___lsb 10
+#define reg_sser_rw_frm_cfg___rec_delay___width 3
+#define reg_sser_rw_frm_cfg___tr_delay___lsb 13
+#define reg_sser_rw_frm_cfg___tr_delay___width 3
+#define reg_sser_rw_frm_cfg___early_wend___lsb 16
+#define reg_sser_rw_frm_cfg___early_wend___width 1
+#define reg_sser_rw_frm_cfg___early_wend___bit 16
+#define reg_sser_rw_frm_cfg___level___lsb 17
+#define reg_sser_rw_frm_cfg___level___width 2
+#define reg_sser_rw_frm_cfg___type___lsb 19
+#define reg_sser_rw_frm_cfg___type___width 1
+#define reg_sser_rw_frm_cfg___type___bit 19
+#define reg_sser_rw_frm_cfg___clk_pol___lsb 20
+#define reg_sser_rw_frm_cfg___clk_pol___width 1
+#define reg_sser_rw_frm_cfg___clk_pol___bit 20
+#define reg_sser_rw_frm_cfg___fr_in_rxclk___lsb 21
+#define reg_sser_rw_frm_cfg___fr_in_rxclk___width 1
+#define reg_sser_rw_frm_cfg___fr_in_rxclk___bit 21
+#define reg_sser_rw_frm_cfg___clk_src___lsb 22
+#define reg_sser_rw_frm_cfg___clk_src___width 1
+#define reg_sser_rw_frm_cfg___clk_src___bit 22
+#define reg_sser_rw_frm_cfg___out_off___lsb 23
+#define reg_sser_rw_frm_cfg___out_off___width 1
+#define reg_sser_rw_frm_cfg___out_off___bit 23
+#define reg_sser_rw_frm_cfg___out_on___lsb 24
+#define reg_sser_rw_frm_cfg___out_on___width 1
+#define reg_sser_rw_frm_cfg___out_on___bit 24
+#define reg_sser_rw_frm_cfg___frame_pin_dir___lsb 25
+#define reg_sser_rw_frm_cfg___frame_pin_dir___width 1
+#define reg_sser_rw_frm_cfg___frame_pin_dir___bit 25
+#define reg_sser_rw_frm_cfg___frame_pin_use___lsb 26
+#define reg_sser_rw_frm_cfg___frame_pin_use___width 2
+#define reg_sser_rw_frm_cfg___status_pin_dir___lsb 28
+#define reg_sser_rw_frm_cfg___status_pin_dir___width 1
+#define reg_sser_rw_frm_cfg___status_pin_dir___bit 28
+#define reg_sser_rw_frm_cfg___status_pin_use___lsb 29
+#define reg_sser_rw_frm_cfg___status_pin_use___width 2
+#define reg_sser_rw_frm_cfg_offset 4
+
+/* Register rw_tr_cfg, scope sser, type rw */
+#define reg_sser_rw_tr_cfg___tr_en___lsb 0
+#define reg_sser_rw_tr_cfg___tr_en___width 1
+#define reg_sser_rw_tr_cfg___tr_en___bit 0
+#define reg_sser_rw_tr_cfg___stop___lsb 1
+#define reg_sser_rw_tr_cfg___stop___width 1
+#define reg_sser_rw_tr_cfg___stop___bit 1
+#define reg_sser_rw_tr_cfg___urun_stop___lsb 2
+#define reg_sser_rw_tr_cfg___urun_stop___width 1
+#define reg_sser_rw_tr_cfg___urun_stop___bit 2
+#define reg_sser_rw_tr_cfg___eop_stop___lsb 3
+#define reg_sser_rw_tr_cfg___eop_stop___width 1
+#define reg_sser_rw_tr_cfg___eop_stop___bit 3
+#define reg_sser_rw_tr_cfg___sample_size___lsb 4
+#define reg_sser_rw_tr_cfg___sample_size___width 6
+#define reg_sser_rw_tr_cfg___sh_dir___lsb 10
+#define reg_sser_rw_tr_cfg___sh_dir___width 1
+#define reg_sser_rw_tr_cfg___sh_dir___bit 10
+#define reg_sser_rw_tr_cfg___clk_pol___lsb 11
+#define reg_sser_rw_tr_cfg___clk_pol___width 1
+#define reg_sser_rw_tr_cfg___clk_pol___bit 11
+#define reg_sser_rw_tr_cfg___clk_src___lsb 12
+#define reg_sser_rw_tr_cfg___clk_src___width 1
+#define reg_sser_rw_tr_cfg___clk_src___bit 12
+#define reg_sser_rw_tr_cfg___use_dma___lsb 13
+#define reg_sser_rw_tr_cfg___use_dma___width 1
+#define reg_sser_rw_tr_cfg___use_dma___bit 13
+#define reg_sser_rw_tr_cfg___mode___lsb 14
+#define reg_sser_rw_tr_cfg___mode___width 2
+#define reg_sser_rw_tr_cfg___frm_src___lsb 16
+#define reg_sser_rw_tr_cfg___frm_src___width 1
+#define reg_sser_rw_tr_cfg___frm_src___bit 16
+#define reg_sser_rw_tr_cfg___use60958___lsb 17
+#define reg_sser_rw_tr_cfg___use60958___width 1
+#define reg_sser_rw_tr_cfg___use60958___bit 17
+#define reg_sser_rw_tr_cfg___iec60958_ckdiv___lsb 18
+#define reg_sser_rw_tr_cfg___iec60958_ckdiv___width 2
+#define reg_sser_rw_tr_cfg___rate_ctrl___lsb 20
+#define reg_sser_rw_tr_cfg___rate_ctrl___width 1
+#define reg_sser_rw_tr_cfg___rate_ctrl___bit 20
+#define reg_sser_rw_tr_cfg___use_md___lsb 21
+#define reg_sser_rw_tr_cfg___use_md___width 1
+#define reg_sser_rw_tr_cfg___use_md___bit 21
+#define reg_sser_rw_tr_cfg___dual_i2s___lsb 22
+#define reg_sser_rw_tr_cfg___dual_i2s___width 1
+#define reg_sser_rw_tr_cfg___dual_i2s___bit 22
+#define reg_sser_rw_tr_cfg___data_pin_use___lsb 23
+#define reg_sser_rw_tr_cfg___data_pin_use___width 2
+#define reg_sser_rw_tr_cfg___od_mode___lsb 25
+#define reg_sser_rw_tr_cfg___od_mode___width 1
+#define reg_sser_rw_tr_cfg___od_mode___bit 25
+#define reg_sser_rw_tr_cfg___bulk_wspace___lsb 26
+#define reg_sser_rw_tr_cfg___bulk_wspace___width 2
+#define reg_sser_rw_tr_cfg_offset 8
+
+/* Register rw_rec_cfg, scope sser, type rw */
+#define reg_sser_rw_rec_cfg___rec_en___lsb 0
+#define reg_sser_rw_rec_cfg___rec_en___width 1
+#define reg_sser_rw_rec_cfg___rec_en___bit 0
+#define reg_sser_rw_rec_cfg___force_eop___lsb 1
+#define reg_sser_rw_rec_cfg___force_eop___width 1
+#define reg_sser_rw_rec_cfg___force_eop___bit 1
+#define reg_sser_rw_rec_cfg___stop___lsb 2
+#define reg_sser_rw_rec_cfg___stop___width 1
+#define reg_sser_rw_rec_cfg___stop___bit 2
+#define reg_sser_rw_rec_cfg___orun_stop___lsb 3
+#define reg_sser_rw_rec_cfg___orun_stop___width 1
+#define reg_sser_rw_rec_cfg___orun_stop___bit 3
+#define reg_sser_rw_rec_cfg___eop_stop___lsb 4
+#define reg_sser_rw_rec_cfg___eop_stop___width 1
+#define reg_sser_rw_rec_cfg___eop_stop___bit 4
+#define reg_sser_rw_rec_cfg___sample_size___lsb 5
+#define reg_sser_rw_rec_cfg___sample_size___width 6
+#define reg_sser_rw_rec_cfg___sh_dir___lsb 11
+#define reg_sser_rw_rec_cfg___sh_dir___width 1
+#define reg_sser_rw_rec_cfg___sh_dir___bit 11
+#define reg_sser_rw_rec_cfg___clk_pol___lsb 12
+#define reg_sser_rw_rec_cfg___clk_pol___width 1
+#define reg_sser_rw_rec_cfg___clk_pol___bit 12
+#define reg_sser_rw_rec_cfg___clk_src___lsb 13
+#define reg_sser_rw_rec_cfg___clk_src___width 1
+#define reg_sser_rw_rec_cfg___clk_src___bit 13
+#define reg_sser_rw_rec_cfg___use_dma___lsb 14
+#define reg_sser_rw_rec_cfg___use_dma___width 1
+#define reg_sser_rw_rec_cfg___use_dma___bit 14
+#define reg_sser_rw_rec_cfg___mode___lsb 15
+#define reg_sser_rw_rec_cfg___mode___width 2
+#define reg_sser_rw_rec_cfg___frm_src___lsb 17
+#define reg_sser_rw_rec_cfg___frm_src___width 2
+#define reg_sser_rw_rec_cfg___use60958___lsb 19
+#define reg_sser_rw_rec_cfg___use60958___width 1
+#define reg_sser_rw_rec_cfg___use60958___bit 19
+#define reg_sser_rw_rec_cfg___iec60958_ui_len___lsb 20
+#define reg_sser_rw_rec_cfg___iec60958_ui_len___width 5
+#define reg_sser_rw_rec_cfg___slave2_en___lsb 25
+#define reg_sser_rw_rec_cfg___slave2_en___width 1
+#define reg_sser_rw_rec_cfg___slave2_en___bit 25
+#define reg_sser_rw_rec_cfg___slave3_en___lsb 26
+#define reg_sser_rw_rec_cfg___slave3_en___width 1
+#define reg_sser_rw_rec_cfg___slave3_en___bit 26
+#define reg_sser_rw_rec_cfg___fifo_thr___lsb 27
+#define reg_sser_rw_rec_cfg___fifo_thr___width 2
+#define reg_sser_rw_rec_cfg_offset 12
+
+/* Register rw_tr_data, scope sser, type rw */
+#define reg_sser_rw_tr_data___data___lsb 0
+#define reg_sser_rw_tr_data___data___width 16
+#define reg_sser_rw_tr_data___md___lsb 16
+#define reg_sser_rw_tr_data___md___width 1
+#define reg_sser_rw_tr_data___md___bit 16
+#define reg_sser_rw_tr_data_offset 16
+
+/* Register r_rec_data, scope sser, type r */
+#define reg_sser_r_rec_data___data___lsb 0
+#define reg_sser_r_rec_data___data___width 16
+#define reg_sser_r_rec_data___md___lsb 16
+#define reg_sser_r_rec_data___md___width 1
+#define reg_sser_r_rec_data___md___bit 16
+#define reg_sser_r_rec_data___ext_clk___lsb 17
+#define reg_sser_r_rec_data___ext_clk___width 1
+#define reg_sser_r_rec_data___ext_clk___bit 17
+#define reg_sser_r_rec_data___status_in___lsb 18
+#define reg_sser_r_rec_data___status_in___width 1
+#define reg_sser_r_rec_data___status_in___bit 18
+#define reg_sser_r_rec_data___frame_in___lsb 19
+#define reg_sser_r_rec_data___frame_in___width 1
+#define reg_sser_r_rec_data___frame_in___bit 19
+#define reg_sser_r_rec_data___din___lsb 20
+#define reg_sser_r_rec_data___din___width 1
+#define reg_sser_r_rec_data___din___bit 20
+#define reg_sser_r_rec_data___data_in___lsb 21
+#define reg_sser_r_rec_data___data_in___width 1
+#define reg_sser_r_rec_data___data_in___bit 21
+#define reg_sser_r_rec_data___clk_in___lsb 22
+#define reg_sser_r_rec_data___clk_in___width 1
+#define reg_sser_r_rec_data___clk_in___bit 22
+#define reg_sser_r_rec_data_offset 20
+
+/* Register rw_extra, scope sser, type rw */
+#define reg_sser_rw_extra___clkoff_cycles___lsb 0
+#define reg_sser_rw_extra___clkoff_cycles___width 20
+#define reg_sser_rw_extra___clkoff_en___lsb 20
+#define reg_sser_rw_extra___clkoff_en___width 1
+#define reg_sser_rw_extra___clkoff_en___bit 20
+#define reg_sser_rw_extra___clkon_en___lsb 21
+#define reg_sser_rw_extra___clkon_en___width 1
+#define reg_sser_rw_extra___clkon_en___bit 21
+#define reg_sser_rw_extra___dout_delay___lsb 22
+#define reg_sser_rw_extra___dout_delay___width 5
+#define reg_sser_rw_extra_offset 24
+
+/* Register rw_intr_mask, scope sser, type rw */
+#define reg_sser_rw_intr_mask___trdy___lsb 0
+#define reg_sser_rw_intr_mask___trdy___width 1
+#define reg_sser_rw_intr_mask___trdy___bit 0
+#define reg_sser_rw_intr_mask___rdav___lsb 1
+#define reg_sser_rw_intr_mask___rdav___width 1
+#define reg_sser_rw_intr_mask___rdav___bit 1
+#define reg_sser_rw_intr_mask___tidle___lsb 2
+#define reg_sser_rw_intr_mask___tidle___width 1
+#define reg_sser_rw_intr_mask___tidle___bit 2
+#define reg_sser_rw_intr_mask___rstop___lsb 3
+#define reg_sser_rw_intr_mask___rstop___width 1
+#define reg_sser_rw_intr_mask___rstop___bit 3
+#define reg_sser_rw_intr_mask___urun___lsb 4
+#define reg_sser_rw_intr_mask___urun___width 1
+#define reg_sser_rw_intr_mask___urun___bit 4
+#define reg_sser_rw_intr_mask___orun___lsb 5
+#define reg_sser_rw_intr_mask___orun___width 1
+#define reg_sser_rw_intr_mask___orun___bit 5
+#define reg_sser_rw_intr_mask___md_rec___lsb 6
+#define reg_sser_rw_intr_mask___md_rec___width 1
+#define reg_sser_rw_intr_mask___md_rec___bit 6
+#define reg_sser_rw_intr_mask___md_sent___lsb 7
+#define reg_sser_rw_intr_mask___md_sent___width 1
+#define reg_sser_rw_intr_mask___md_sent___bit 7
+#define reg_sser_rw_intr_mask___r958err___lsb 8
+#define reg_sser_rw_intr_mask___r958err___width 1
+#define reg_sser_rw_intr_mask___r958err___bit 8
+#define reg_sser_rw_intr_mask_offset 28
+
+/* Register rw_ack_intr, scope sser, type rw */
+#define reg_sser_rw_ack_intr___trdy___lsb 0
+#define reg_sser_rw_ack_intr___trdy___width 1
+#define reg_sser_rw_ack_intr___trdy___bit 0
+#define reg_sser_rw_ack_intr___rdav___lsb 1
+#define reg_sser_rw_ack_intr___rdav___width 1
+#define reg_sser_rw_ack_intr___rdav___bit 1
+#define reg_sser_rw_ack_intr___tidle___lsb 2
+#define reg_sser_rw_ack_intr___tidle___width 1
+#define reg_sser_rw_ack_intr___tidle___bit 2
+#define reg_sser_rw_ack_intr___rstop___lsb 3
+#define reg_sser_rw_ack_intr___rstop___width 1
+#define reg_sser_rw_ack_intr___rstop___bit 3
+#define reg_sser_rw_ack_intr___urun___lsb 4
+#define reg_sser_rw_ack_intr___urun___width 1
+#define reg_sser_rw_ack_intr___urun___bit 4
+#define reg_sser_rw_ack_intr___orun___lsb 5
+#define reg_sser_rw_ack_intr___orun___width 1
+#define reg_sser_rw_ack_intr___orun___bit 5
+#define reg_sser_rw_ack_intr___md_rec___lsb 6
+#define reg_sser_rw_ack_intr___md_rec___width 1
+#define reg_sser_rw_ack_intr___md_rec___bit 6
+#define reg_sser_rw_ack_intr___md_sent___lsb 7
+#define reg_sser_rw_ack_intr___md_sent___width 1
+#define reg_sser_rw_ack_intr___md_sent___bit 7
+#define reg_sser_rw_ack_intr___r958err___lsb 8
+#define reg_sser_rw_ack_intr___r958err___width 1
+#define reg_sser_rw_ack_intr___r958err___bit 8
+#define reg_sser_rw_ack_intr_offset 32
+
+/* Register r_intr, scope sser, type r */
+#define reg_sser_r_intr___trdy___lsb 0
+#define reg_sser_r_intr___trdy___width 1
+#define reg_sser_r_intr___trdy___bit 0
+#define reg_sser_r_intr___rdav___lsb 1
+#define reg_sser_r_intr___rdav___width 1
+#define reg_sser_r_intr___rdav___bit 1
+#define reg_sser_r_intr___tidle___lsb 2
+#define reg_sser_r_intr___tidle___width 1
+#define reg_sser_r_intr___tidle___bit 2
+#define reg_sser_r_intr___rstop___lsb 3
+#define reg_sser_r_intr___rstop___width 1
+#define reg_sser_r_intr___rstop___bit 3
+#define reg_sser_r_intr___urun___lsb 4
+#define reg_sser_r_intr___urun___width 1
+#define reg_sser_r_intr___urun___bit 4
+#define reg_sser_r_intr___orun___lsb 5
+#define reg_sser_r_intr___orun___width 1
+#define reg_sser_r_intr___orun___bit 5
+#define reg_sser_r_intr___md_rec___lsb 6
+#define reg_sser_r_intr___md_rec___width 1
+#define reg_sser_r_intr___md_rec___bit 6
+#define reg_sser_r_intr___md_sent___lsb 7
+#define reg_sser_r_intr___md_sent___width 1
+#define reg_sser_r_intr___md_sent___bit 7
+#define reg_sser_r_intr___r958err___lsb 8
+#define reg_sser_r_intr___r958err___width 1
+#define reg_sser_r_intr___r958err___bit 8
+#define reg_sser_r_intr_offset 36
+
+/* Register r_masked_intr, scope sser, type r */
+#define reg_sser_r_masked_intr___trdy___lsb 0
+#define reg_sser_r_masked_intr___trdy___width 1
+#define reg_sser_r_masked_intr___trdy___bit 0
+#define reg_sser_r_masked_intr___rdav___lsb 1
+#define reg_sser_r_masked_intr___rdav___width 1
+#define reg_sser_r_masked_intr___rdav___bit 1
+#define reg_sser_r_masked_intr___tidle___lsb 2
+#define reg_sser_r_masked_intr___tidle___width 1
+#define reg_sser_r_masked_intr___tidle___bit 2
+#define reg_sser_r_masked_intr___rstop___lsb 3
+#define reg_sser_r_masked_intr___rstop___width 1
+#define reg_sser_r_masked_intr___rstop___bit 3
+#define reg_sser_r_masked_intr___urun___lsb 4
+#define reg_sser_r_masked_intr___urun___width 1
+#define reg_sser_r_masked_intr___urun___bit 4
+#define reg_sser_r_masked_intr___orun___lsb 5
+#define reg_sser_r_masked_intr___orun___width 1
+#define reg_sser_r_masked_intr___orun___bit 5
+#define reg_sser_r_masked_intr___md_rec___lsb 6
+#define reg_sser_r_masked_intr___md_rec___width 1
+#define reg_sser_r_masked_intr___md_rec___bit 6
+#define reg_sser_r_masked_intr___md_sent___lsb 7
+#define reg_sser_r_masked_intr___md_sent___width 1
+#define reg_sser_r_masked_intr___md_sent___bit 7
+#define reg_sser_r_masked_intr___r958err___lsb 8
+#define reg_sser_r_masked_intr___r958err___width 1
+#define reg_sser_r_masked_intr___r958err___bit 8
+#define reg_sser_r_masked_intr_offset 40
+
+
+/* Constants */
+#define regk_sser_both                            0x00000002
+#define regk_sser_bulk                            0x00000001
+#define regk_sser_clk100                          0x00000000
+#define regk_sser_clk_in                          0x00000000
+#define regk_sser_const0                          0x00000003
+#define regk_sser_dout                            0x00000002
+#define regk_sser_edge                            0x00000000
+#define regk_sser_ext                             0x00000001
+#define regk_sser_ext_clk                         0x00000001
+#define regk_sser_f100                            0x00000000
+#define regk_sser_f29_493                         0x00000004
+#define regk_sser_f32                             0x00000005
+#define regk_sser_f32_768                         0x00000006
+#define regk_sser_frm                             0x00000003
+#define regk_sser_gio0                            0x00000000
+#define regk_sser_gio1                            0x00000001
+#define regk_sser_hispeed                         0x00000001
+#define regk_sser_hold                            0x00000002
+#define regk_sser_in                              0x00000000
+#define regk_sser_inf                             0x00000003
+#define regk_sser_intern                          0x00000000
+#define regk_sser_intern_clk                      0x00000001
+#define regk_sser_intern_tb                       0x00000000
+#define regk_sser_iso                             0x00000000
+#define regk_sser_level                           0x00000001
+#define regk_sser_lospeed                         0x00000000
+#define regk_sser_lsbfirst                        0x00000000
+#define regk_sser_msbfirst                        0x00000001
+#define regk_sser_neg                             0x00000001
+#define regk_sser_neg_lo                          0x00000000
+#define regk_sser_no                              0x00000000
+#define regk_sser_no_clk                          0x00000007
+#define regk_sser_nojitter                        0x00000002
+#define regk_sser_out                             0x00000001
+#define regk_sser_pos                             0x00000000
+#define regk_sser_pos_hi                          0x00000001
+#define regk_sser_rec                             0x00000000
+#define regk_sser_rw_cfg_default                  0x00000000
+#define regk_sser_rw_extra_default                0x00000000
+#define regk_sser_rw_frm_cfg_default              0x00000000
+#define regk_sser_rw_intr_mask_default            0x00000000
+#define regk_sser_rw_rec_cfg_default              0x00000000
+#define regk_sser_rw_tr_cfg_default               0x01800000
+#define regk_sser_rw_tr_data_default              0x00000000
+#define regk_sser_thr16                           0x00000001
+#define regk_sser_thr32                           0x00000002
+#define regk_sser_thr8                            0x00000000
+#define regk_sser_tr                              0x00000001
+#define regk_sser_ts_out                          0x00000003
+#define regk_sser_tx_bulk                         0x00000002
+#define regk_sser_wiresave                        0x00000002
+#define regk_sser_yes                             0x00000001
+#endif /* __sser_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h
new file mode 100644
index 00000000000..55083e6aec9
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/strcop_defs_asm.h
@@ -0,0 +1,84 @@
+#ifndef __strcop_defs_asm_h
+#define __strcop_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/strcop/rtl/strcop_regs.r
+ *     id:           strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp
+ *     last modfied: Mon Apr 11 16:09:38 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strcop_defs_asm.h ../../inst/strcop/rtl/strcop_regs.r
+ *      id: $Id: strcop_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope strcop, type rw */
+#define reg_strcop_rw_cfg___td3___lsb 0
+#define reg_strcop_rw_cfg___td3___width 1
+#define reg_strcop_rw_cfg___td3___bit 0
+#define reg_strcop_rw_cfg___td2___lsb 1
+#define reg_strcop_rw_cfg___td2___width 1
+#define reg_strcop_rw_cfg___td2___bit 1
+#define reg_strcop_rw_cfg___td1___lsb 2
+#define reg_strcop_rw_cfg___td1___width 1
+#define reg_strcop_rw_cfg___td1___bit 2
+#define reg_strcop_rw_cfg___ipend___lsb 3
+#define reg_strcop_rw_cfg___ipend___width 1
+#define reg_strcop_rw_cfg___ipend___bit 3
+#define reg_strcop_rw_cfg___ignore_sync___lsb 4
+#define reg_strcop_rw_cfg___ignore_sync___width 1
+#define reg_strcop_rw_cfg___ignore_sync___bit 4
+#define reg_strcop_rw_cfg___en___lsb 5
+#define reg_strcop_rw_cfg___en___width 1
+#define reg_strcop_rw_cfg___en___bit 5
+#define reg_strcop_rw_cfg_offset 0
+
+
+/* Constants */
+#define regk_strcop_big                           0x00000001
+#define regk_strcop_d                             0x00000001
+#define regk_strcop_e                             0x00000000
+#define regk_strcop_little                        0x00000000
+#define regk_strcop_rw_cfg_default                0x00000002
+#endif /* __strcop_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h
new file mode 100644
index 00000000000..69b299920f7
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/strmux_defs_asm.h
@@ -0,0 +1,100 @@
+#ifndef __strmux_defs_asm_h
+#define __strmux_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/strmux/rtl/guinness/strmux_regs.r
+ *     id:           strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp
+ *     last modfied: Mon Apr 11 16:09:43 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strmux_defs_asm.h ../../inst/strmux/rtl/guinness/strmux_regs.r
+ *      id: $Id: strmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope strmux, type rw */
+#define reg_strmux_rw_cfg___dma0___lsb 0
+#define reg_strmux_rw_cfg___dma0___width 3
+#define reg_strmux_rw_cfg___dma1___lsb 3
+#define reg_strmux_rw_cfg___dma1___width 3
+#define reg_strmux_rw_cfg___dma2___lsb 6
+#define reg_strmux_rw_cfg___dma2___width 3
+#define reg_strmux_rw_cfg___dma3___lsb 9
+#define reg_strmux_rw_cfg___dma3___width 3
+#define reg_strmux_rw_cfg___dma4___lsb 12
+#define reg_strmux_rw_cfg___dma4___width 3
+#define reg_strmux_rw_cfg___dma5___lsb 15
+#define reg_strmux_rw_cfg___dma5___width 3
+#define reg_strmux_rw_cfg___dma6___lsb 18
+#define reg_strmux_rw_cfg___dma6___width 3
+#define reg_strmux_rw_cfg___dma7___lsb 21
+#define reg_strmux_rw_cfg___dma7___width 3
+#define reg_strmux_rw_cfg___dma8___lsb 24
+#define reg_strmux_rw_cfg___dma8___width 3
+#define reg_strmux_rw_cfg___dma9___lsb 27
+#define reg_strmux_rw_cfg___dma9___width 3
+#define reg_strmux_rw_cfg_offset 0
+
+
+/* Constants */
+#define regk_strmux_ata                           0x00000003
+#define regk_strmux_eth0                          0x00000001
+#define regk_strmux_eth1                          0x00000004
+#define regk_strmux_ext0                          0x00000001
+#define regk_strmux_ext1                          0x00000001
+#define regk_strmux_ext2                          0x00000001
+#define regk_strmux_ext3                          0x00000001
+#define regk_strmux_iop0                          0x00000002
+#define regk_strmux_iop1                          0x00000001
+#define regk_strmux_off                           0x00000000
+#define regk_strmux_p21                           0x00000004
+#define regk_strmux_rw_cfg_default                0x00000000
+#define regk_strmux_ser0                          0x00000002
+#define regk_strmux_ser1                          0x00000002
+#define regk_strmux_ser2                          0x00000004
+#define regk_strmux_ser3                          0x00000003
+#define regk_strmux_sser0                         0x00000003
+#define regk_strmux_sser1                         0x00000003
+#define regk_strmux_strcop                        0x00000002
+#endif /* __strmux_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h b/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h
new file mode 100644
index 00000000000..43146021fc1
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/asm/timer_defs_asm.h
@@ -0,0 +1,229 @@
+#ifndef __timer_defs_asm_h
+#define __timer_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/timer/rtl/timer_regs.r
+ *     id:           timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
+ *     last modfied: Mon Apr 11 16:09:53 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r
+ *      id: $Id: timer_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_tmr0_div, scope timer, type rw */
+#define reg_timer_rw_tmr0_div_offset 0
+
+/* Register r_tmr0_data, scope timer, type r */
+#define reg_timer_r_tmr0_data_offset 4
+
+/* Register rw_tmr0_ctrl, scope timer, type rw */
+#define reg_timer_rw_tmr0_ctrl___op___lsb 0
+#define reg_timer_rw_tmr0_ctrl___op___width 2
+#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
+#define reg_timer_rw_tmr0_ctrl___freq___width 3
+#define reg_timer_rw_tmr0_ctrl_offset 8
+
+/* Register rw_tmr1_div, scope timer, type rw */
+#define reg_timer_rw_tmr1_div_offset 16
+
+/* Register r_tmr1_data, scope timer, type r */
+#define reg_timer_r_tmr1_data_offset 20
+
+/* Register rw_tmr1_ctrl, scope timer, type rw */
+#define reg_timer_rw_tmr1_ctrl___op___lsb 0
+#define reg_timer_rw_tmr1_ctrl___op___width 2
+#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
+#define reg_timer_rw_tmr1_ctrl___freq___width 3
+#define reg_timer_rw_tmr1_ctrl_offset 24
+
+/* Register rs_cnt_data, scope timer, type rs */
+#define reg_timer_rs_cnt_data___tmr___lsb 0
+#define reg_timer_rs_cnt_data___tmr___width 24
+#define reg_timer_rs_cnt_data___cnt___lsb 24
+#define reg_timer_rs_cnt_data___cnt___width 8
+#define reg_timer_rs_cnt_data_offset 32
+
+/* Register r_cnt_data, scope timer, type r */
+#define reg_timer_r_cnt_data___tmr___lsb 0
+#define reg_timer_r_cnt_data___tmr___width 24
+#define reg_timer_r_cnt_data___cnt___lsb 24
+#define reg_timer_r_cnt_data___cnt___width 8
+#define reg_timer_r_cnt_data_offset 36
+
+/* Register rw_cnt_cfg, scope timer, type rw */
+#define reg_timer_rw_cnt_cfg___clk___lsb 0
+#define reg_timer_rw_cnt_cfg___clk___width 2
+#define reg_timer_rw_cnt_cfg_offset 40
+
+/* Register rw_trig, scope timer, type rw */
+#define reg_timer_rw_trig_offset 48
+
+/* Register rw_trig_cfg, scope timer, type rw */
+#define reg_timer_rw_trig_cfg___tmr___lsb 0
+#define reg_timer_rw_trig_cfg___tmr___width 2
+#define reg_timer_rw_trig_cfg_offset 52
+
+/* Register r_time, scope timer, type r */
+#define reg_timer_r_time_offset 56
+
+/* Register rw_out, scope timer, type rw */
+#define reg_timer_rw_out___tmr___lsb 0
+#define reg_timer_rw_out___tmr___width 2
+#define reg_timer_rw_out_offset 60
+
+/* Register rw_wd_ctrl, scope timer, type rw */
+#define reg_timer_rw_wd_ctrl___cnt___lsb 0
+#define reg_timer_rw_wd_ctrl___cnt___width 8
+#define reg_timer_rw_wd_ctrl___cmd___lsb 8
+#define reg_timer_rw_wd_ctrl___cmd___width 1
+#define reg_timer_rw_wd_ctrl___cmd___bit 8
+#define reg_timer_rw_wd_ctrl___key___lsb 9
+#define reg_timer_rw_wd_ctrl___key___width 7
+#define reg_timer_rw_wd_ctrl_offset 64
+
+/* Register r_wd_stat, scope timer, type r */
+#define reg_timer_r_wd_stat___cnt___lsb 0
+#define reg_timer_r_wd_stat___cnt___width 8
+#define reg_timer_r_wd_stat___cmd___lsb 8
+#define reg_timer_r_wd_stat___cmd___width 1
+#define reg_timer_r_wd_stat___cmd___bit 8
+#define reg_timer_r_wd_stat_offset 68
+
+/* Register rw_intr_mask, scope timer, type rw */
+#define reg_timer_rw_intr_mask___tmr0___lsb 0
+#define reg_timer_rw_intr_mask___tmr0___width 1
+#define reg_timer_rw_intr_mask___tmr0___bit 0
+#define reg_timer_rw_intr_mask___tmr1___lsb 1
+#define reg_timer_rw_intr_mask___tmr1___width 1
+#define reg_timer_rw_intr_mask___tmr1___bit 1
+#define reg_timer_rw_intr_mask___cnt___lsb 2
+#define reg_timer_rw_intr_mask___cnt___width 1
+#define reg_timer_rw_intr_mask___cnt___bit 2
+#define reg_timer_rw_intr_mask___trig___lsb 3
+#define reg_timer_rw_intr_mask___trig___width 1
+#define reg_timer_rw_intr_mask___trig___bit 3
+#define reg_timer_rw_intr_mask_offset 72
+
+/* Register rw_ack_intr, scope timer, type rw */
+#define reg_timer_rw_ack_intr___tmr0___lsb 0
+#define reg_timer_rw_ack_intr___tmr0___width 1
+#define reg_timer_rw_ack_intr___tmr0___bit 0
+#define reg_timer_rw_ack_intr___tmr1___lsb 1
+#define reg_timer_rw_ack_intr___tmr1___width 1
+#define reg_timer_rw_ack_intr___tmr1___bit 1
+#define reg_timer_rw_ack_intr___cnt___lsb 2
+#define reg_timer_rw_ack_intr___cnt___width 1
+#define reg_timer_rw_ack_intr___cnt___bit 2
+#define reg_timer_rw_ack_intr___trig___lsb 3
+#define reg_timer_rw_ack_intr___trig___width 1
+#define reg_timer_rw_ack_intr___trig___bit 3
+#define reg_timer_rw_ack_intr_offset 76
+
+/* Register r_intr, scope timer, type r */
+#define reg_timer_r_intr___tmr0___lsb 0
+#define reg_timer_r_intr___tmr0___width 1
+#define reg_timer_r_intr___tmr0___bit 0
+#define reg_timer_r_intr___tmr1___lsb 1
+#define reg_timer_r_intr___tmr1___width 1
+#define reg_timer_r_intr___tmr1___bit 1
+#define reg_timer_r_intr___cnt___lsb 2
+#define reg_timer_r_intr___cnt___width 1
+#define reg_timer_r_intr___cnt___bit 2
+#define reg_timer_r_intr___trig___lsb 3
+#define reg_timer_r_intr___trig___width 1
+#define reg_timer_r_intr___trig___bit 3
+#define reg_timer_r_intr_offset 80
+
+/* Register r_masked_intr, scope timer, type r */
+#define reg_timer_r_masked_intr___tmr0___lsb 0
+#define reg_timer_r_masked_intr___tmr0___width 1
+#define reg_timer_r_masked_intr___tmr0___bit 0
+#define reg_timer_r_masked_intr___tmr1___lsb 1
+#define reg_timer_r_masked_intr___tmr1___width 1
+#define reg_timer_r_masked_intr___tmr1___bit 1
+#define reg_timer_r_masked_intr___cnt___lsb 2
+#define reg_timer_r_masked_intr___cnt___width 1
+#define reg_timer_r_masked_intr___cnt___bit 2
+#define reg_timer_r_masked_intr___trig___lsb 3
+#define reg_timer_r_masked_intr___trig___width 1
+#define reg_timer_r_masked_intr___trig___bit 3
+#define reg_timer_r_masked_intr_offset 84
+
+/* Register rw_test, scope timer, type rw */
+#define reg_timer_rw_test___dis___lsb 0
+#define reg_timer_rw_test___dis___width 1
+#define reg_timer_rw_test___dis___bit 0
+#define reg_timer_rw_test___en___lsb 1
+#define reg_timer_rw_test___en___width 1
+#define reg_timer_rw_test___en___bit 1
+#define reg_timer_rw_test_offset 88
+
+
+/* Constants */
+#define regk_timer_ext                            0x00000001
+#define regk_timer_f100                           0x00000007
+#define regk_timer_f29_493                        0x00000004
+#define regk_timer_f32                            0x00000005
+#define regk_timer_f32_768                        0x00000006
+#define regk_timer_hold                           0x00000001
+#define regk_timer_ld                             0x00000000
+#define regk_timer_no                             0x00000000
+#define regk_timer_off                            0x00000000
+#define regk_timer_run                            0x00000002
+#define regk_timer_rw_cnt_cfg_default             0x00000000
+#define regk_timer_rw_intr_mask_default           0x00000000
+#define regk_timer_rw_out_default                 0x00000000
+#define regk_timer_rw_test_default                0x00000000
+#define regk_timer_rw_tmr0_ctrl_default           0x00000000
+#define regk_timer_rw_tmr1_ctrl_default           0x00000000
+#define regk_timer_rw_trig_cfg_default            0x00000000
+#define regk_timer_start                          0x00000001
+#define regk_timer_stop                           0x00000000
+#define regk_timer_time                           0x00000001
+#define regk_timer_tmr0                           0x00000002
+#define regk_timer_tmr1                           0x00000003
+#define regk_timer_yes                            0x00000001
+#endif /* __timer_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/ata_defs.h b/include/asm-cris/arch-v32/hwregs/ata_defs.h
new file mode 100644
index 00000000000..43b6643ff0d
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/ata_defs.h
@@ -0,0 +1,222 @@
+#ifndef __ata_defs_h
+#define __ata_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/ata/rtl/ata_regs.r
+ *     id:           ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp
+ *     last modfied: Mon Apr 11 16:06:25 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r
+ *      id: $Id: ata_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope ata */
+
+/* Register rw_ctrl0, scope ata, type rw */
+typedef struct {
+  unsigned int pio_hold  : 6;
+  unsigned int pio_strb  : 6;
+  unsigned int pio_setup : 6;
+  unsigned int dma_hold  : 6;
+  unsigned int dma_strb  : 6;
+  unsigned int rst       : 1;
+  unsigned int en        : 1;
+} reg_ata_rw_ctrl0;
+#define REG_RD_ADDR_ata_rw_ctrl0 12
+#define REG_WR_ADDR_ata_rw_ctrl0 12
+
+/* Register rw_ctrl1, scope ata, type rw */
+typedef struct {
+  unsigned int udma_tcyc : 4;
+  unsigned int udma_tdvs : 4;
+  unsigned int dummy1    : 24;
+} reg_ata_rw_ctrl1;
+#define REG_RD_ADDR_ata_rw_ctrl1 16
+#define REG_WR_ADDR_ata_rw_ctrl1 16
+
+/* Register rw_ctrl2, scope ata, type rw */
+typedef struct {
+  unsigned int data     : 16;
+  unsigned int dummy1   : 3;
+  unsigned int dma_size : 1;
+  unsigned int multi    : 1;
+  unsigned int hsh      : 2;
+  unsigned int trf_mode : 1;
+  unsigned int rw       : 1;
+  unsigned int addr     : 3;
+  unsigned int cs0      : 1;
+  unsigned int cs1      : 1;
+  unsigned int sel      : 2;
+} reg_ata_rw_ctrl2;
+#define REG_RD_ADDR_ata_rw_ctrl2 0
+#define REG_WR_ADDR_ata_rw_ctrl2 0
+
+/* Register rs_stat_data, scope ata, type rs */
+typedef struct {
+  unsigned int data : 16;
+  unsigned int dav  : 1;
+  unsigned int busy : 1;
+  unsigned int dummy1 : 14;
+} reg_ata_rs_stat_data;
+#define REG_RD_ADDR_ata_rs_stat_data 4
+
+/* Register r_stat_data, scope ata, type r */
+typedef struct {
+  unsigned int data : 16;
+  unsigned int dav  : 1;
+  unsigned int busy : 1;
+  unsigned int dummy1 : 14;
+} reg_ata_r_stat_data;
+#define REG_RD_ADDR_ata_r_stat_data 8
+
+/* Register rw_trf_cnt, scope ata, type rw */
+typedef struct {
+  unsigned int cnt : 17;
+  unsigned int dummy1 : 15;
+} reg_ata_rw_trf_cnt;
+#define REG_RD_ADDR_ata_rw_trf_cnt 20
+#define REG_WR_ADDR_ata_rw_trf_cnt 20
+
+/* Register r_stat_misc, scope ata, type r */
+typedef struct {
+  unsigned int crc : 16;
+  unsigned int dummy1 : 16;
+} reg_ata_r_stat_misc;
+#define REG_RD_ADDR_ata_r_stat_misc 24
+
+/* Register rw_intr_mask, scope ata, type rw */
+typedef struct {
+  unsigned int bus0 : 1;
+  unsigned int bus1 : 1;
+  unsigned int bus2 : 1;
+  unsigned int bus3 : 1;
+  unsigned int dummy1 : 28;
+} reg_ata_rw_intr_mask;
+#define REG_RD_ADDR_ata_rw_intr_mask 28
+#define REG_WR_ADDR_ata_rw_intr_mask 28
+
+/* Register rw_ack_intr, scope ata, type rw */
+typedef struct {
+  unsigned int bus0 : 1;
+  unsigned int bus1 : 1;
+  unsigned int bus2 : 1;
+  unsigned int bus3 : 1;
+  unsigned int dummy1 : 28;
+} reg_ata_rw_ack_intr;
+#define REG_RD_ADDR_ata_rw_ack_intr 32
+#define REG_WR_ADDR_ata_rw_ack_intr 32
+
+/* Register r_intr, scope ata, type r */
+typedef struct {
+  unsigned int bus0 : 1;
+  unsigned int bus1 : 1;
+  unsigned int bus2 : 1;
+  unsigned int bus3 : 1;
+  unsigned int dummy1 : 28;
+} reg_ata_r_intr;
+#define REG_RD_ADDR_ata_r_intr 36
+
+/* Register r_masked_intr, scope ata, type r */
+typedef struct {
+  unsigned int bus0 : 1;
+  unsigned int bus1 : 1;
+  unsigned int bus2 : 1;
+  unsigned int bus3 : 1;
+  unsigned int dummy1 : 28;
+} reg_ata_r_masked_intr;
+#define REG_RD_ADDR_ata_r_masked_intr 40
+
+
+/* Constants */
+enum {
+  regk_ata_active                          = 0x00000001,
+  regk_ata_byte                            = 0x00000001,
+  regk_ata_data                            = 0x00000001,
+  regk_ata_dma                             = 0x00000001,
+  regk_ata_inactive                        = 0x00000000,
+  regk_ata_no                              = 0x00000000,
+  regk_ata_nodata                          = 0x00000000,
+  regk_ata_pio                             = 0x00000000,
+  regk_ata_rd                              = 0x00000001,
+  regk_ata_reg                             = 0x00000000,
+  regk_ata_rw_ctrl0_default                = 0x00000000,
+  regk_ata_rw_ctrl2_default                = 0x00000000,
+  regk_ata_rw_intr_mask_default            = 0x00000000,
+  regk_ata_udma                            = 0x00000002,
+  regk_ata_word                            = 0x00000000,
+  regk_ata_wr                              = 0x00000000,
+  regk_ata_yes                             = 0x00000001
+};
+#endif /* __ata_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/bif_core_defs.h b/include/asm-cris/arch-v32/hwregs/bif_core_defs.h
new file mode 100644
index 00000000000..a56608b5035
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/bif_core_defs.h
@@ -0,0 +1,284 @@
+#ifndef __bif_core_defs_h
+#define __bif_core_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/bif/rtl/bif_core_regs.r
+ *     id:           bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
+ *     last modfied: Mon Apr 11 16:06:33 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r
+ *      id: $Id: bif_core_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope bif_core */
+
+/* Register rw_grp1_cfg, scope bif_core, type rw */
+typedef struct {
+  unsigned int lw        : 6;
+  unsigned int ew        : 3;
+  unsigned int zw        : 3;
+  unsigned int aw        : 2;
+  unsigned int dw        : 2;
+  unsigned int ewb       : 2;
+  unsigned int bw        : 1;
+  unsigned int wr_extend : 1;
+  unsigned int erc_en    : 1;
+  unsigned int mode      : 1;
+  unsigned int dummy1    : 10;
+} reg_bif_core_rw_grp1_cfg;
+#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0
+#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0
+
+/* Register rw_grp2_cfg, scope bif_core, type rw */
+typedef struct {
+  unsigned int lw        : 6;
+  unsigned int ew        : 3;
+  unsigned int zw        : 3;
+  unsigned int aw        : 2;
+  unsigned int dw        : 2;
+  unsigned int ewb       : 2;
+  unsigned int bw        : 1;
+  unsigned int wr_extend : 1;
+  unsigned int erc_en    : 1;
+  unsigned int mode      : 1;
+  unsigned int dummy1    : 10;
+} reg_bif_core_rw_grp2_cfg;
+#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4
+#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4
+
+/* Register rw_grp3_cfg, scope bif_core, type rw */
+typedef struct {
+  unsigned int lw         : 6;
+  unsigned int ew         : 3;
+  unsigned int zw         : 3;
+  unsigned int aw         : 2;
+  unsigned int dw         : 2;
+  unsigned int ewb        : 2;
+  unsigned int bw         : 1;
+  unsigned int wr_extend  : 1;
+  unsigned int erc_en     : 1;
+  unsigned int mode       : 1;
+  unsigned int dummy1     : 2;
+  unsigned int gated_csp0 : 2;
+  unsigned int gated_csp1 : 2;
+  unsigned int gated_csp2 : 2;
+  unsigned int gated_csp3 : 2;
+} reg_bif_core_rw_grp3_cfg;
+#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8
+#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8
+
+/* Register rw_grp4_cfg, scope bif_core, type rw */
+typedef struct {
+  unsigned int lw         : 6;
+  unsigned int ew         : 3;
+  unsigned int zw         : 3;
+  unsigned int aw         : 2;
+  unsigned int dw         : 2;
+  unsigned int ewb        : 2;
+  unsigned int bw         : 1;
+  unsigned int wr_extend  : 1;
+  unsigned int erc_en     : 1;
+  unsigned int mode       : 1;
+  unsigned int dummy1     : 4;
+  unsigned int gated_csp4 : 2;
+  unsigned int gated_csp5 : 2;
+  unsigned int gated_csp6 : 2;
+} reg_bif_core_rw_grp4_cfg;
+#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12
+#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12
+
+/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
+typedef struct {
+  unsigned int bank_sel : 5;
+  unsigned int ca       : 3;
+  unsigned int type     : 1;
+  unsigned int bw       : 1;
+  unsigned int sh       : 3;
+  unsigned int wmm      : 1;
+  unsigned int sh16     : 1;
+  unsigned int grp_sel  : 5;
+  unsigned int dummy1   : 12;
+} reg_bif_core_rw_sdram_cfg_grp0;
+#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16
+#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16
+
+/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
+typedef struct {
+  unsigned int bank_sel : 5;
+  unsigned int ca       : 3;
+  unsigned int type     : 1;
+  unsigned int bw       : 1;
+  unsigned int sh       : 3;
+  unsigned int wmm      : 1;
+  unsigned int sh16     : 1;
+  unsigned int dummy1   : 17;
+} reg_bif_core_rw_sdram_cfg_grp1;
+#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20
+#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20
+
+/* Register rw_sdram_timing, scope bif_core, type rw */
+typedef struct {
+  unsigned int cl    : 3;
+  unsigned int rcd   : 3;
+  unsigned int rp    : 3;
+  unsigned int rc    : 2;
+  unsigned int dpl   : 2;
+  unsigned int pde   : 1;
+  unsigned int ref   : 2;
+  unsigned int cpd   : 1;
+  unsigned int sdcke : 1;
+  unsigned int sdclk : 1;
+  unsigned int dummy1 : 13;
+} reg_bif_core_rw_sdram_timing;
+#define REG_RD_ADDR_bif_core_rw_sdram_timing 24
+#define REG_WR_ADDR_bif_core_rw_sdram_timing 24
+
+/* Register rw_sdram_cmd, scope bif_core, type rw */
+typedef struct {
+  unsigned int cmd      : 3;
+  unsigned int mrs_data : 15;
+  unsigned int dummy1   : 14;
+} reg_bif_core_rw_sdram_cmd;
+#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28
+#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28
+
+/* Register rs_sdram_ref_stat, scope bif_core, type rs */
+typedef struct {
+  unsigned int ok : 1;
+  unsigned int dummy1 : 31;
+} reg_bif_core_rs_sdram_ref_stat;
+#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32
+
+/* Register r_sdram_ref_stat, scope bif_core, type r */
+typedef struct {
+  unsigned int ok : 1;
+  unsigned int dummy1 : 31;
+} reg_bif_core_r_sdram_ref_stat;
+#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36
+
+
+/* Constants */
+enum {
+  regk_bif_core_bank2                      = 0x00000000,
+  regk_bif_core_bank4                      = 0x00000001,
+  regk_bif_core_bit10                      = 0x0000000a,
+  regk_bif_core_bit11                      = 0x0000000b,
+  regk_bif_core_bit12                      = 0x0000000c,
+  regk_bif_core_bit13                      = 0x0000000d,
+  regk_bif_core_bit14                      = 0x0000000e,
+  regk_bif_core_bit15                      = 0x0000000f,
+  regk_bif_core_bit16                      = 0x00000010,
+  regk_bif_core_bit17                      = 0x00000011,
+  regk_bif_core_bit18                      = 0x00000012,
+  regk_bif_core_bit19                      = 0x00000013,
+  regk_bif_core_bit20                      = 0x00000014,
+  regk_bif_core_bit21                      = 0x00000015,
+  regk_bif_core_bit22                      = 0x00000016,
+  regk_bif_core_bit23                      = 0x00000017,
+  regk_bif_core_bit24                      = 0x00000018,
+  regk_bif_core_bit25                      = 0x00000019,
+  regk_bif_core_bit26                      = 0x0000001a,
+  regk_bif_core_bit27                      = 0x0000001b,
+  regk_bif_core_bit28                      = 0x0000001c,
+  regk_bif_core_bit29                      = 0x0000001d,
+  regk_bif_core_bit9                       = 0x00000009,
+  regk_bif_core_bw16                       = 0x00000001,
+  regk_bif_core_bw32                       = 0x00000000,
+  regk_bif_core_bwe                        = 0x00000000,
+  regk_bif_core_cwe                        = 0x00000001,
+  regk_bif_core_e15us                      = 0x00000001,
+  regk_bif_core_e7800ns                    = 0x00000002,
+  regk_bif_core_grp0                       = 0x00000000,
+  regk_bif_core_grp1                       = 0x00000001,
+  regk_bif_core_mrs                        = 0x00000003,
+  regk_bif_core_no                         = 0x00000000,
+  regk_bif_core_none                       = 0x00000000,
+  regk_bif_core_nop                        = 0x00000000,
+  regk_bif_core_off                        = 0x00000000,
+  regk_bif_core_pre                        = 0x00000002,
+  regk_bif_core_r_sdram_ref_stat_default   = 0x00000001,
+  regk_bif_core_rd                         = 0x00000002,
+  regk_bif_core_ref                        = 0x00000001,
+  regk_bif_core_rs_sdram_ref_stat_default  = 0x00000001,
+  regk_bif_core_rw_grp1_cfg_default        = 0x000006cf,
+  regk_bif_core_rw_grp2_cfg_default        = 0x000006cf,
+  regk_bif_core_rw_grp3_cfg_default        = 0x000006cf,
+  regk_bif_core_rw_grp4_cfg_default        = 0x000006cf,
+  regk_bif_core_rw_sdram_cfg_grp1_default  = 0x00000000,
+  regk_bif_core_slf                        = 0x00000004,
+  regk_bif_core_wr                         = 0x00000001,
+  regk_bif_core_yes                        = 0x00000001
+};
+#endif /* __bif_core_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h b/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h
new file mode 100644
index 00000000000..b931c1aab67
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/bif_dma_defs.h
@@ -0,0 +1,473 @@
+#ifndef __bif_dma_defs_h
+#define __bif_dma_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/bif/rtl/bif_dma_regs.r
+ *     id:           bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
+ *     last modfied: Mon Apr 11 16:06:33 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r
+ *      id: $Id: bif_dma_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope bif_dma */
+
+/* Register rw_ch0_ctrl, scope bif_dma, type rw */
+typedef struct {
+  unsigned int bw         : 2;
+  unsigned int burst_len  : 1;
+  unsigned int cont       : 1;
+  unsigned int end_pad    : 1;
+  unsigned int cnt        : 1;
+  unsigned int dreq_pin   : 3;
+  unsigned int dreq_mode  : 2;
+  unsigned int tc_in_pin  : 3;
+  unsigned int tc_in_mode : 2;
+  unsigned int bus_mode   : 2;
+  unsigned int rate_en    : 1;
+  unsigned int wr_all     : 1;
+  unsigned int dummy1     : 12;
+} reg_bif_dma_rw_ch0_ctrl;
+#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0
+#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0
+
+/* Register rw_ch0_addr, scope bif_dma, type rw */
+typedef struct {
+  unsigned int addr : 32;
+} reg_bif_dma_rw_ch0_addr;
+#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4
+#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4
+
+/* Register rw_ch0_start, scope bif_dma, type rw */
+typedef struct {
+  unsigned int run : 1;
+  unsigned int dummy1 : 31;
+} reg_bif_dma_rw_ch0_start;
+#define REG_RD_ADDR_bif_dma_rw_ch0_start 8
+#define REG_WR_ADDR_bif_dma_rw_ch0_start 8
+
+/* Register rw_ch0_cnt, scope bif_dma, type rw */
+typedef struct {
+  unsigned int start_cnt : 16;
+  unsigned int dummy1    : 16;
+} reg_bif_dma_rw_ch0_cnt;
+#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12
+#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12
+
+/* Register r_ch0_stat, scope bif_dma, type r */
+typedef struct {
+  unsigned int cnt : 16;
+  unsigned int dummy1 : 15;
+  unsigned int run : 1;
+} reg_bif_dma_r_ch0_stat;
+#define REG_RD_ADDR_bif_dma_r_ch0_stat 16
+
+/* Register rw_ch1_ctrl, scope bif_dma, type rw */
+typedef struct {
+  unsigned int bw          : 2;
+  unsigned int burst_len   : 1;
+  unsigned int cont        : 1;
+  unsigned int end_discard : 1;
+  unsigned int cnt         : 1;
+  unsigned int dreq_pin    : 3;
+  unsigned int dreq_mode   : 2;
+  unsigned int tc_in_pin   : 3;
+  unsigned int tc_in_mode  : 2;
+  unsigned int bus_mode    : 2;
+  unsigned int rate_en     : 1;
+  unsigned int dummy1      : 13;
+} reg_bif_dma_rw_ch1_ctrl;
+#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32
+#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32
+
+/* Register rw_ch1_addr, scope bif_dma, type rw */
+typedef struct {
+  unsigned int addr : 32;
+} reg_bif_dma_rw_ch1_addr;
+#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36
+#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36
+
+/* Register rw_ch1_start, scope bif_dma, type rw */
+typedef struct {
+  unsigned int run : 1;
+  unsigned int dummy1 : 31;
+} reg_bif_dma_rw_ch1_start;
+#define REG_RD_ADDR_bif_dma_rw_ch1_start 40
+#define REG_WR_ADDR_bif_dma_rw_ch1_start 40
+
+/* Register rw_ch1_cnt, scope bif_dma, type rw */
+typedef struct {
+  unsigned int start_cnt : 16;
+  unsigned int dummy1    : 16;
+} reg_bif_dma_rw_ch1_cnt;
+#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44
+#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44
+
+/* Register r_ch1_stat, scope bif_dma, type r */
+typedef struct {
+  unsigned int cnt : 16;
+  unsigned int dummy1 : 15;
+  unsigned int run : 1;
+} reg_bif_dma_r_ch1_stat;
+#define REG_RD_ADDR_bif_dma_r_ch1_stat 48
+
+/* Register rw_ch2_ctrl, scope bif_dma, type rw */
+typedef struct {
+  unsigned int bw         : 2;
+  unsigned int burst_len  : 1;
+  unsigned int cont       : 1;
+  unsigned int end_pad    : 1;
+  unsigned int cnt        : 1;
+  unsigned int dreq_pin   : 3;
+  unsigned int dreq_mode  : 2;
+  unsigned int tc_in_pin  : 3;
+  unsigned int tc_in_mode : 2;
+  unsigned int bus_mode   : 2;
+  unsigned int rate_en    : 1;
+  unsigned int wr_all     : 1;
+  unsigned int dummy1     : 12;
+} reg_bif_dma_rw_ch2_ctrl;
+#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64
+#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64
+
+/* Register rw_ch2_addr, scope bif_dma, type rw */
+typedef struct {
+  unsigned int addr : 32;
+} reg_bif_dma_rw_ch2_addr;
+#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68
+#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68
+
+/* Register rw_ch2_start, scope bif_dma, type rw */
+typedef struct {
+  unsigned int run : 1;
+  unsigned int dummy1 : 31;
+} reg_bif_dma_rw_ch2_start;
+#define REG_RD_ADDR_bif_dma_rw_ch2_start 72
+#define REG_WR_ADDR_bif_dma_rw_ch2_start 72
+
+/* Register rw_ch2_cnt, scope bif_dma, type rw */
+typedef struct {
+  unsigned int start_cnt : 16;
+  unsigned int dummy1    : 16;
+} reg_bif_dma_rw_ch2_cnt;
+#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76
+#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76
+
+/* Register r_ch2_stat, scope bif_dma, type r */
+typedef struct {
+  unsigned int cnt : 16;
+  unsigned int dummy1 : 15;
+  unsigned int run : 1;
+} reg_bif_dma_r_ch2_stat;
+#define REG_RD_ADDR_bif_dma_r_ch2_stat 80
+
+/* Register rw_ch3_ctrl, scope bif_dma, type rw */
+typedef struct {
+  unsigned int bw          : 2;
+  unsigned int burst_len   : 1;
+  unsigned int cont        : 1;
+  unsigned int end_discard : 1;
+  unsigned int cnt         : 1;
+  unsigned int dreq_pin    : 3;
+  unsigned int dreq_mode   : 2;
+  unsigned int tc_in_pin   : 3;
+  unsigned int tc_in_mode  : 2;
+  unsigned int bus_mode    : 2;
+  unsigned int rate_en     : 1;
+  unsigned int dummy1      : 13;
+} reg_bif_dma_rw_ch3_ctrl;
+#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96
+#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96
+
+/* Register rw_ch3_addr, scope bif_dma, type rw */
+typedef struct {
+  unsigned int addr : 32;
+} reg_bif_dma_rw_ch3_addr;
+#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100
+#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100
+
+/* Register rw_ch3_start, scope bif_dma, type rw */
+typedef struct {
+  unsigned int run : 1;
+  unsigned int dummy1 : 31;
+} reg_bif_dma_rw_ch3_start;
+#define REG_RD_ADDR_bif_dma_rw_ch3_start 104
+#define REG_WR_ADDR_bif_dma_rw_ch3_start 104
+
+/* Register rw_ch3_cnt, scope bif_dma, type rw */
+typedef struct {
+  unsigned int start_cnt : 16;
+  unsigned int dummy1    : 16;
+} reg_bif_dma_rw_ch3_cnt;
+#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108
+#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108
+
+/* Register r_ch3_stat, scope bif_dma, type r */
+typedef struct {
+  unsigned int cnt : 16;
+  unsigned int dummy1 : 15;
+  unsigned int run : 1;
+} reg_bif_dma_r_ch3_stat;
+#define REG_RD_ADDR_bif_dma_r_ch3_stat 112
+
+/* Register rw_intr_mask, scope bif_dma, type rw */
+typedef struct {
+  unsigned int ext_dma0 : 1;
+  unsigned int ext_dma1 : 1;
+  unsigned int ext_dma2 : 1;
+  unsigned int ext_dma3 : 1;
+  unsigned int dummy1   : 28;
+} reg_bif_dma_rw_intr_mask;
+#define REG_RD_ADDR_bif_dma_rw_intr_mask 128
+#define REG_WR_ADDR_bif_dma_rw_intr_mask 128
+
+/* Register rw_ack_intr, scope bif_dma, type rw */
+typedef struct {
+  unsigned int ext_dma0 : 1;
+  unsigned int ext_dma1 : 1;
+  unsigned int ext_dma2 : 1;
+  unsigned int ext_dma3 : 1;
+  unsigned int dummy1   : 28;
+} reg_bif_dma_rw_ack_intr;
+#define REG_RD_ADDR_bif_dma_rw_ack_intr 132
+#define REG_WR_ADDR_bif_dma_rw_ack_intr 132
+
+/* Register r_intr, scope bif_dma, type r */
+typedef struct {
+  unsigned int ext_dma0 : 1;
+  unsigned int ext_dma1 : 1;
+  unsigned int ext_dma2 : 1;
+  unsigned int ext_dma3 : 1;
+  unsigned int dummy1   : 28;
+} reg_bif_dma_r_intr;
+#define REG_RD_ADDR_bif_dma_r_intr 136
+
+/* Register r_masked_intr, scope bif_dma, type r */
+typedef struct {
+  unsigned int ext_dma0 : 1;
+  unsigned int ext_dma1 : 1;
+  unsigned int ext_dma2 : 1;
+  unsigned int ext_dma3 : 1;
+  unsigned int dummy1   : 28;
+} reg_bif_dma_r_masked_intr;
+#define REG_RD_ADDR_bif_dma_r_masked_intr 140
+
+/* Register rw_pin0_cfg, scope bif_dma, type rw */
+typedef struct {
+  unsigned int master_ch   : 2;
+  unsigned int master_mode : 3;
+  unsigned int slave_ch    : 2;
+  unsigned int slave_mode  : 3;
+  unsigned int dummy1      : 22;
+} reg_bif_dma_rw_pin0_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160
+#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160
+
+/* Register rw_pin1_cfg, scope bif_dma, type rw */
+typedef struct {
+  unsigned int master_ch   : 2;
+  unsigned int master_mode : 3;
+  unsigned int slave_ch    : 2;
+  unsigned int slave_mode  : 3;
+  unsigned int dummy1      : 22;
+} reg_bif_dma_rw_pin1_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164
+#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164
+
+/* Register rw_pin2_cfg, scope bif_dma, type rw */
+typedef struct {
+  unsigned int master_ch   : 2;
+  unsigned int master_mode : 3;
+  unsigned int slave_ch    : 2;
+  unsigned int slave_mode  : 3;
+  unsigned int dummy1      : 22;
+} reg_bif_dma_rw_pin2_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168
+#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168
+
+/* Register rw_pin3_cfg, scope bif_dma, type rw */
+typedef struct {
+  unsigned int master_ch   : 2;
+  unsigned int master_mode : 3;
+  unsigned int slave_ch    : 2;
+  unsigned int slave_mode  : 3;
+  unsigned int dummy1      : 22;
+} reg_bif_dma_rw_pin3_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172
+#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172
+
+/* Register rw_pin4_cfg, scope bif_dma, type rw */
+typedef struct {
+  unsigned int master_ch   : 2;
+  unsigned int master_mode : 3;
+  unsigned int slave_ch    : 2;
+  unsigned int slave_mode  : 3;
+  unsigned int dummy1      : 22;
+} reg_bif_dma_rw_pin4_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176
+#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176
+
+/* Register rw_pin5_cfg, scope bif_dma, type rw */
+typedef struct {
+  unsigned int master_ch   : 2;
+  unsigned int master_mode : 3;
+  unsigned int slave_ch    : 2;
+  unsigned int slave_mode  : 3;
+  unsigned int dummy1      : 22;
+} reg_bif_dma_rw_pin5_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180
+#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180
+
+/* Register rw_pin6_cfg, scope bif_dma, type rw */
+typedef struct {
+  unsigned int master_ch   : 2;
+  unsigned int master_mode : 3;
+  unsigned int slave_ch    : 2;
+  unsigned int slave_mode  : 3;
+  unsigned int dummy1      : 22;
+} reg_bif_dma_rw_pin6_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184
+#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184
+
+/* Register rw_pin7_cfg, scope bif_dma, type rw */
+typedef struct {
+  unsigned int master_ch   : 2;
+  unsigned int master_mode : 3;
+  unsigned int slave_ch    : 2;
+  unsigned int slave_mode  : 3;
+  unsigned int dummy1      : 22;
+} reg_bif_dma_rw_pin7_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188
+#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188
+
+/* Register r_pin_stat, scope bif_dma, type r */
+typedef struct {
+  unsigned int pin0 : 1;
+  unsigned int pin1 : 1;
+  unsigned int pin2 : 1;
+  unsigned int pin3 : 1;
+  unsigned int pin4 : 1;
+  unsigned int pin5 : 1;
+  unsigned int pin6 : 1;
+  unsigned int pin7 : 1;
+  unsigned int dummy1 : 24;
+} reg_bif_dma_r_pin_stat;
+#define REG_RD_ADDR_bif_dma_r_pin_stat 192
+
+
+/* Constants */
+enum {
+  regk_bif_dma_as_master                   = 0x00000001,
+  regk_bif_dma_as_slave                    = 0x00000001,
+  regk_bif_dma_burst1                      = 0x00000000,
+  regk_bif_dma_burst8                      = 0x00000001,
+  regk_bif_dma_bw16                        = 0x00000001,
+  regk_bif_dma_bw32                        = 0x00000002,
+  regk_bif_dma_bw8                         = 0x00000000,
+  regk_bif_dma_dack                        = 0x00000006,
+  regk_bif_dma_dack_inv                    = 0x00000007,
+  regk_bif_dma_force                       = 0x00000001,
+  regk_bif_dma_hi                          = 0x00000003,
+  regk_bif_dma_inv                         = 0x00000003,
+  regk_bif_dma_lo                          = 0x00000002,
+  regk_bif_dma_master                      = 0x00000001,
+  regk_bif_dma_no                          = 0x00000000,
+  regk_bif_dma_norm                        = 0x00000002,
+  regk_bif_dma_off                         = 0x00000000,
+  regk_bif_dma_rw_ch0_ctrl_default         = 0x00000000,
+  regk_bif_dma_rw_ch0_start_default        = 0x00000000,
+  regk_bif_dma_rw_ch1_ctrl_default         = 0x00000000,
+  regk_bif_dma_rw_ch1_start_default        = 0x00000000,
+  regk_bif_dma_rw_ch2_ctrl_default         = 0x00000000,
+  regk_bif_dma_rw_ch2_start_default        = 0x00000000,
+  regk_bif_dma_rw_ch3_ctrl_default         = 0x00000000,
+  regk_bif_dma_rw_ch3_start_default        = 0x00000000,
+  regk_bif_dma_rw_intr_mask_default        = 0x00000000,
+  regk_bif_dma_rw_pin0_cfg_default         = 0x00000000,
+  regk_bif_dma_rw_pin1_cfg_default         = 0x00000000,
+  regk_bif_dma_rw_pin2_cfg_default         = 0x00000000,
+  regk_bif_dma_rw_pin3_cfg_default         = 0x00000000,
+  regk_bif_dma_rw_pin4_cfg_default         = 0x00000000,
+  regk_bif_dma_rw_pin5_cfg_default         = 0x00000000,
+  regk_bif_dma_rw_pin6_cfg_default         = 0x00000000,
+  regk_bif_dma_rw_pin7_cfg_default         = 0x00000000,
+  regk_bif_dma_slave                       = 0x00000002,
+  regk_bif_dma_sreq                        = 0x00000006,
+  regk_bif_dma_sreq_inv                    = 0x00000007,
+  regk_bif_dma_tc                          = 0x00000004,
+  regk_bif_dma_tc_inv                      = 0x00000005,
+  regk_bif_dma_yes                         = 0x00000001
+};
+#endif /* __bif_dma_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h b/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h
new file mode 100644
index 00000000000..d18fc3c9f56
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/bif_slave_defs.h
@@ -0,0 +1,249 @@
+#ifndef __bif_slave_defs_h
+#define __bif_slave_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/bif/rtl/bif_slave_regs.r
+ *     id:           bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp
+ *     last modfied: Mon Apr 11 16:06:34 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r
+ *      id: $Id: bif_slave_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope bif_slave */
+
+/* Register rw_slave_cfg, scope bif_slave, type rw */
+typedef struct {
+  unsigned int slave_id     : 3;
+  unsigned int use_slave_id : 1;
+  unsigned int boot_rdy     : 1;
+  unsigned int loopback     : 1;
+  unsigned int dis          : 1;
+  unsigned int dummy1       : 25;
+} reg_bif_slave_rw_slave_cfg;
+#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0
+#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0
+
+/* Register r_slave_mode, scope bif_slave, type r */
+typedef struct {
+  unsigned int ch0_mode : 1;
+  unsigned int ch1_mode : 1;
+  unsigned int ch2_mode : 1;
+  unsigned int ch3_mode : 1;
+  unsigned int dummy1   : 28;
+} reg_bif_slave_r_slave_mode;
+#define REG_RD_ADDR_bif_slave_r_slave_mode 4
+
+/* Register rw_ch0_cfg, scope bif_slave, type rw */
+typedef struct {
+  unsigned int rd_hold     : 2;
+  unsigned int access_mode : 1;
+  unsigned int access_ctrl : 1;
+  unsigned int data_cs     : 2;
+  unsigned int dummy1      : 26;
+} reg_bif_slave_rw_ch0_cfg;
+#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16
+#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16
+
+/* Register rw_ch1_cfg, scope bif_slave, type rw */
+typedef struct {
+  unsigned int rd_hold     : 2;
+  unsigned int access_mode : 1;
+  unsigned int access_ctrl : 1;
+  unsigned int data_cs     : 2;
+  unsigned int dummy1      : 26;
+} reg_bif_slave_rw_ch1_cfg;
+#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20
+#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20
+
+/* Register rw_ch2_cfg, scope bif_slave, type rw */
+typedef struct {
+  unsigned int rd_hold     : 2;
+  unsigned int access_mode : 1;
+  unsigned int access_ctrl : 1;
+  unsigned int data_cs     : 2;
+  unsigned int dummy1      : 26;
+} reg_bif_slave_rw_ch2_cfg;
+#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24
+#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24
+
+/* Register rw_ch3_cfg, scope bif_slave, type rw */
+typedef struct {
+  unsigned int rd_hold     : 2;
+  unsigned int access_mode : 1;
+  unsigned int access_ctrl : 1;
+  unsigned int data_cs     : 2;
+  unsigned int dummy1      : 26;
+} reg_bif_slave_rw_ch3_cfg;
+#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28
+#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28
+
+/* Register rw_arb_cfg, scope bif_slave, type rw */
+typedef struct {
+  unsigned int brin_mode   : 1;
+  unsigned int brout_mode  : 3;
+  unsigned int bg_mode     : 3;
+  unsigned int release     : 2;
+  unsigned int acquire     : 1;
+  unsigned int settle_time : 2;
+  unsigned int dram_ctrl   : 1;
+  unsigned int dummy1      : 19;
+} reg_bif_slave_rw_arb_cfg;
+#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32
+#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32
+
+/* Register r_arb_stat, scope bif_slave, type r */
+typedef struct {
+  unsigned int init_mode : 1;
+  unsigned int mode      : 1;
+  unsigned int brin      : 1;
+  unsigned int brout     : 1;
+  unsigned int bg        : 1;
+  unsigned int dummy1    : 27;
+} reg_bif_slave_r_arb_stat;
+#define REG_RD_ADDR_bif_slave_r_arb_stat 36
+
+/* Register rw_intr_mask, scope bif_slave, type rw */
+typedef struct {
+  unsigned int bus_release : 1;
+  unsigned int bus_acquire : 1;
+  unsigned int dummy1      : 30;
+} reg_bif_slave_rw_intr_mask;
+#define REG_RD_ADDR_bif_slave_rw_intr_mask 64
+#define REG_WR_ADDR_bif_slave_rw_intr_mask 64
+
+/* Register rw_ack_intr, scope bif_slave, type rw */
+typedef struct {
+  unsigned int bus_release : 1;
+  unsigned int bus_acquire : 1;
+  unsigned int dummy1      : 30;
+} reg_bif_slave_rw_ack_intr;
+#define REG_RD_ADDR_bif_slave_rw_ack_intr 68
+#define REG_WR_ADDR_bif_slave_rw_ack_intr 68
+
+/* Register r_intr, scope bif_slave, type r */
+typedef struct {
+  unsigned int bus_release : 1;
+  unsigned int bus_acquire : 1;
+  unsigned int dummy1      : 30;
+} reg_bif_slave_r_intr;
+#define REG_RD_ADDR_bif_slave_r_intr 72
+
+/* Register r_masked_intr, scope bif_slave, type r */
+typedef struct {
+  unsigned int bus_release : 1;
+  unsigned int bus_acquire : 1;
+  unsigned int dummy1      : 30;
+} reg_bif_slave_r_masked_intr;
+#define REG_RD_ADDR_bif_slave_r_masked_intr 76
+
+
+/* Constants */
+enum {
+  regk_bif_slave_active_hi                 = 0x00000003,
+  regk_bif_slave_active_lo                 = 0x00000002,
+  regk_bif_slave_addr                      = 0x00000000,
+  regk_bif_slave_always                    = 0x00000001,
+  regk_bif_slave_at_idle                   = 0x00000002,
+  regk_bif_slave_burst_end                 = 0x00000003,
+  regk_bif_slave_dma                       = 0x00000001,
+  regk_bif_slave_hi                        = 0x00000003,
+  regk_bif_slave_inv                       = 0x00000001,
+  regk_bif_slave_lo                        = 0x00000002,
+  regk_bif_slave_local                     = 0x00000001,
+  regk_bif_slave_master                    = 0x00000000,
+  regk_bif_slave_mode_reg                  = 0x00000001,
+  regk_bif_slave_no                        = 0x00000000,
+  regk_bif_slave_norm                      = 0x00000000,
+  regk_bif_slave_on_access                 = 0x00000000,
+  regk_bif_slave_rw_arb_cfg_default        = 0x00000000,
+  regk_bif_slave_rw_ch0_cfg_default        = 0x00000000,
+  regk_bif_slave_rw_ch1_cfg_default        = 0x00000000,
+  regk_bif_slave_rw_ch2_cfg_default        = 0x00000000,
+  regk_bif_slave_rw_ch3_cfg_default        = 0x00000000,
+  regk_bif_slave_rw_intr_mask_default      = 0x00000000,
+  regk_bif_slave_rw_slave_cfg_default      = 0x00000000,
+  regk_bif_slave_shared                    = 0x00000000,
+  regk_bif_slave_slave                     = 0x00000001,
+  regk_bif_slave_t0ns                      = 0x00000003,
+  regk_bif_slave_t10ns                     = 0x00000002,
+  regk_bif_slave_t20ns                     = 0x00000003,
+  regk_bif_slave_t30ns                     = 0x00000002,
+  regk_bif_slave_t40ns                     = 0x00000001,
+  regk_bif_slave_t50ns                     = 0x00000000,
+  regk_bif_slave_yes                       = 0x00000001,
+  regk_bif_slave_z                         = 0x00000004
+};
+#endif /* __bif_slave_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/config_defs.h b/include/asm-cris/arch-v32/hwregs/config_defs.h
new file mode 100644
index 00000000000..45457a4e381
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/config_defs.h
@@ -0,0 +1,142 @@
+#ifndef __config_defs_h
+#define __config_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../rtl/config_regs.r
+ *     id:           config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
+ *     last modfied: Thu Mar  4 12:34:39 2004
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r
+ *      id: $Id: config_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope config */
+
+/* Register r_bootsel, scope config, type r */
+typedef struct {
+  unsigned int boot_mode   : 3;
+  unsigned int full_duplex : 1;
+  unsigned int user        : 1;
+  unsigned int pll         : 1;
+  unsigned int flash_bw    : 1;
+  unsigned int dummy1      : 25;
+} reg_config_r_bootsel;
+#define REG_RD_ADDR_config_r_bootsel 0
+
+/* Register rw_clk_ctrl, scope config, type rw */
+typedef struct {
+  unsigned int pll          : 1;
+  unsigned int cpu          : 1;
+  unsigned int iop          : 1;
+  unsigned int dma01_eth0   : 1;
+  unsigned int dma23        : 1;
+  unsigned int dma45        : 1;
+  unsigned int dma67        : 1;
+  unsigned int dma89_strcop : 1;
+  unsigned int bif          : 1;
+  unsigned int fix_io       : 1;
+  unsigned int dummy1       : 22;
+} reg_config_rw_clk_ctrl;
+#define REG_RD_ADDR_config_rw_clk_ctrl 4
+#define REG_WR_ADDR_config_rw_clk_ctrl 4
+
+/* Register rw_pad_ctrl, scope config, type rw */
+typedef struct {
+  unsigned int usb_susp : 1;
+  unsigned int phyrst_n : 1;
+  unsigned int dummy1   : 30;
+} reg_config_rw_pad_ctrl;
+#define REG_RD_ADDR_config_rw_pad_ctrl 8
+#define REG_WR_ADDR_config_rw_pad_ctrl 8
+
+
+/* Constants */
+enum {
+  regk_config_bw16                         = 0x00000000,
+  regk_config_bw32                         = 0x00000001,
+  regk_config_master                       = 0x00000005,
+  regk_config_nand                         = 0x00000003,
+  regk_config_net_rx                       = 0x00000001,
+  regk_config_net_tx_rx                    = 0x00000002,
+  regk_config_no                           = 0x00000000,
+  regk_config_none                         = 0x00000007,
+  regk_config_nor                          = 0x00000000,
+  regk_config_rw_clk_ctrl_default          = 0x00000002,
+  regk_config_rw_pad_ctrl_default          = 0x00000000,
+  regk_config_ser                          = 0x00000004,
+  regk_config_slave                        = 0x00000006,
+  regk_config_yes                          = 0x00000001
+};
+#endif /* __config_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/cpu_vect.h b/include/asm-cris/arch-v32/hwregs/cpu_vect.h
new file mode 100644
index 00000000000..8370aee8a14
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/cpu_vect.h
@@ -0,0 +1,41 @@
+/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
+ from ../../inst/crisp/doc/cpu_vect.r
+version . */
+
+#ifndef _______INST_CRISP_DOC_CPU_VECT_R
+#define _______INST_CRISP_DOC_CPU_VECT_R
+#define NMI_INTR_VECT	0x00
+#define RESERVED_1_INTR_VECT	0x01
+#define RESERVED_2_INTR_VECT	0x02
+#define SINGLE_STEP_INTR_VECT	0x03
+#define INSTR_TLB_REFILL_INTR_VECT	0x04
+#define INSTR_TLB_INV_INTR_VECT	0x05
+#define INSTR_TLB_ACC_INTR_VECT	0x06
+#define TLB_EX_INTR_VECT	0x07
+#define DATA_TLB_REFILL_INTR_VECT	0x08
+#define DATA_TLB_INV_INTR_VECT	0x09
+#define DATA_TLB_ACC_INTR_VECT	0x0a
+#define DATA_TLB_WE_INTR_VECT	0x0b
+#define HW_BP_INTR_VECT	0x0c
+#define RESERVED_D_INTR_VECT	0x0d
+#define RESERVED_E_INTR_VECT	0x0e
+#define RESERVED_F_INTR_VECT	0x0f
+#define BREAK_0_INTR_VECT	0x10
+#define BREAK_1_INTR_VECT	0x11
+#define BREAK_2_INTR_VECT	0x12
+#define BREAK_3_INTR_VECT	0x13
+#define BREAK_4_INTR_VECT	0x14
+#define BREAK_5_INTR_VECT	0x15
+#define BREAK_6_INTR_VECT	0x16
+#define BREAK_7_INTR_VECT	0x17
+#define BREAK_8_INTR_VECT	0x18
+#define BREAK_9_INTR_VECT	0x19
+#define BREAK_10_INTR_VECT	0x1a
+#define BREAK_11_INTR_VECT	0x1b
+#define BREAK_12_INTR_VECT	0x1c
+#define BREAK_13_INTR_VECT	0x1d
+#define BREAK_14_INTR_VECT	0x1e
+#define BREAK_15_INTR_VECT	0x1f
+#define MULTIPLE_INTR_VECT	0x30
+
+#endif
diff --git a/include/asm-cris/arch-v32/hwregs/dma.h b/include/asm-cris/arch-v32/hwregs/dma.h
new file mode 100644
index 00000000000..c31832d3d6b
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/dma.h
@@ -0,0 +1,128 @@
+/* $Id: dma.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
+ *
+ * DMA C definitions and help macros
+ *
+ */
+
+#ifndef dma_h
+#define dma_h
+
+/* registers */ /* Really needed, since both are listed in sw.list? */
+#include "dma_defs.h"
+
+
+/* descriptors */
+
+// ------------------------------------------------------------ dma_descr_group
+typedef struct dma_descr_group {
+  struct dma_descr_group       *next;
+  unsigned                      eol        : 1;
+  unsigned                      tol        : 1;
+  unsigned                      bol        : 1;
+  unsigned                                 : 1;
+  unsigned                      intr       : 1;
+  unsigned                                 : 2;
+  unsigned                      en         : 1;
+  unsigned                                 : 7;
+  unsigned                      dis        : 1;
+  unsigned                      md         : 16;
+  struct dma_descr_group       *up;
+  union {
+    struct dma_descr_context   *context;
+    struct dma_descr_group     *group;
+  }                             down;
+} dma_descr_group;
+
+// ---------------------------------------------------------- dma_descr_context
+typedef struct dma_descr_context {
+  struct dma_descr_context     *next;
+  unsigned                      eol        : 1;
+  unsigned                                 : 3;
+  unsigned                      intr       : 1;
+  unsigned                                 : 1;
+  unsigned                      store_mode : 1;
+  unsigned                      en         : 1;
+  unsigned                                 : 7;
+  unsigned                      dis        : 1;
+  unsigned                      md0        : 16;
+  unsigned                      md1;
+  unsigned                      md2;
+  unsigned                      md3;
+  unsigned                      md4;
+  struct dma_descr_data        *saved_data;
+  char                         *saved_data_buf;
+} dma_descr_context;
+
+// ------------------------------------------------------------- dma_descr_data
+typedef struct dma_descr_data {
+  struct dma_descr_data        *next;
+  char                         *buf;
+  unsigned                      eol        : 1;
+  unsigned                                 : 2;
+  unsigned                      out_eop    : 1;
+  unsigned                      intr       : 1;
+  unsigned                      wait       : 1;
+  unsigned                                 : 2;
+  unsigned                                 : 3;
+  unsigned                      in_eop     : 1;
+  unsigned                                 : 4;
+  unsigned                      md         : 16;
+  char                         *after;
+} dma_descr_data;
+
+// --------------------------------------------------------------------- macros
+
+// enable DMA channel
+#define DMA_ENABLE( inst ) \
+   do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\
+        e.en = regk_dma_yes; \
+        REG_WR( dma, inst, rw_cfg, e); } while( 0 )
+
+// reset DMA channel
+#define DMA_RESET( inst ) \
+   do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\
+        r.en = regk_dma_no; \
+        REG_WR( dma, inst, rw_cfg, r); } while( 0 )
+
+// stop DMA channel
+#define DMA_STOP( inst ) \
+   do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\
+        s.stop = regk_dma_yes; \
+        REG_WR( dma, inst, rw_cfg, s); } while( 0 )
+
+// continue DMA channel operation
+#define DMA_CONTINUE( inst ) \
+   do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\
+        c.stop = regk_dma_no; \
+        REG_WR( dma, inst, rw_cfg, c); } while( 0 )
+
+// give stream command
+#define DMA_WR_CMD( inst, cmd_par ) \
+   do { reg_dma_rw_stream_cmd r = {0}; \
+        do { r = REG_RD( dma, inst, rw_stream_cmd ); } while( r.busy ); \
+        r.cmd = (cmd_par); \
+        REG_WR( dma, inst, rw_stream_cmd, r ); \
+      } while( 0 )
+
+// load: g,c,d:burst
+#define DMA_START_GROUP( inst, group_descr ) \
+   do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \
+        DMA_WR_CMD( inst, regk_dma_load_g ); \
+        DMA_WR_CMD( inst, regk_dma_load_c ); \
+        DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
+      } while( 0 )
+
+// load: c,d:burst
+#define DMA_START_CONTEXT( inst, ctx_descr ) \
+   do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \
+        DMA_WR_CMD( inst, regk_dma_load_c ); \
+        DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
+      } while( 0 )
+
+// if the DMA is at the end of the data list, the last data descr is reloaded
+#define DMA_CONTINUE_DATA( inst ) \
+do { reg_dma_rw_cmd c = {0}; \
+     c.cont_data = regk_dma_yes;\
+     REG_WR( dma, inst, rw_cmd, c ); } while( 0 )
+
+#endif
diff --git a/include/asm-cris/arch-v32/hwregs/dma_defs.h b/include/asm-cris/arch-v32/hwregs/dma_defs.h
new file mode 100644
index 00000000000..48ac8cef7eb
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/dma_defs.h
@@ -0,0 +1,436 @@
+#ifndef __dma_defs_h
+#define __dma_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
+ *     id:           dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp
+ *     last modfied: Mon Apr 11 16:06:51 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
+ *      id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope dma */
+
+/* Register rw_data, scope dma, type rw */
+typedef unsigned int reg_dma_rw_data;
+#define REG_RD_ADDR_dma_rw_data 0
+#define REG_WR_ADDR_dma_rw_data 0
+
+/* Register rw_data_next, scope dma, type rw */
+typedef unsigned int reg_dma_rw_data_next;
+#define REG_RD_ADDR_dma_rw_data_next 4
+#define REG_WR_ADDR_dma_rw_data_next 4
+
+/* Register rw_data_buf, scope dma, type rw */
+typedef unsigned int reg_dma_rw_data_buf;
+#define REG_RD_ADDR_dma_rw_data_buf 8
+#define REG_WR_ADDR_dma_rw_data_buf 8
+
+/* Register rw_data_ctrl, scope dma, type rw */
+typedef struct {
+  unsigned int eol     : 1;
+  unsigned int dummy1  : 2;
+  unsigned int out_eop : 1;
+  unsigned int intr    : 1;
+  unsigned int wait    : 1;
+  unsigned int dummy2  : 26;
+} reg_dma_rw_data_ctrl;
+#define REG_RD_ADDR_dma_rw_data_ctrl 12
+#define REG_WR_ADDR_dma_rw_data_ctrl 12
+
+/* Register rw_data_stat, scope dma, type rw */
+typedef struct {
+  unsigned int dummy1 : 3;
+  unsigned int in_eop : 1;
+  unsigned int dummy2 : 28;
+} reg_dma_rw_data_stat;
+#define REG_RD_ADDR_dma_rw_data_stat 16
+#define REG_WR_ADDR_dma_rw_data_stat 16
+
+/* Register rw_data_md, scope dma, type rw */
+typedef struct {
+  unsigned int md : 16;
+  unsigned int dummy1 : 16;
+} reg_dma_rw_data_md;
+#define REG_RD_ADDR_dma_rw_data_md 20
+#define REG_WR_ADDR_dma_rw_data_md 20
+
+/* Register rw_data_md_s, scope dma, type rw */
+typedef struct {
+  unsigned int md_s : 16;
+  unsigned int dummy1 : 16;
+} reg_dma_rw_data_md_s;
+#define REG_RD_ADDR_dma_rw_data_md_s 24
+#define REG_WR_ADDR_dma_rw_data_md_s 24
+
+/* Register rw_data_after, scope dma, type rw */
+typedef unsigned int reg_dma_rw_data_after;
+#define REG_RD_ADDR_dma_rw_data_after 28
+#define REG_WR_ADDR_dma_rw_data_after 28
+
+/* Register rw_ctxt, scope dma, type rw */
+typedef unsigned int reg_dma_rw_ctxt;
+#define REG_RD_ADDR_dma_rw_ctxt 32
+#define REG_WR_ADDR_dma_rw_ctxt 32
+
+/* Register rw_ctxt_next, scope dma, type rw */
+typedef unsigned int reg_dma_rw_ctxt_next;
+#define REG_RD_ADDR_dma_rw_ctxt_next 36
+#define REG_WR_ADDR_dma_rw_ctxt_next 36
+
+/* Register rw_ctxt_ctrl, scope dma, type rw */
+typedef struct {
+  unsigned int eol        : 1;
+  unsigned int dummy1     : 3;
+  unsigned int intr       : 1;
+  unsigned int dummy2     : 1;
+  unsigned int store_mode : 1;
+  unsigned int en         : 1;
+  unsigned int dummy3     : 24;
+} reg_dma_rw_ctxt_ctrl;
+#define REG_RD_ADDR_dma_rw_ctxt_ctrl 40
+#define REG_WR_ADDR_dma_rw_ctxt_ctrl 40
+
+/* Register rw_ctxt_stat, scope dma, type rw */
+typedef struct {
+  unsigned int dummy1 : 7;
+  unsigned int dis : 1;
+  unsigned int dummy2 : 24;
+} reg_dma_rw_ctxt_stat;
+#define REG_RD_ADDR_dma_rw_ctxt_stat 44
+#define REG_WR_ADDR_dma_rw_ctxt_stat 44
+
+/* Register rw_ctxt_md0, scope dma, type rw */
+typedef struct {
+  unsigned int md0 : 16;
+  unsigned int dummy1 : 16;
+} reg_dma_rw_ctxt_md0;
+#define REG_RD_ADDR_dma_rw_ctxt_md0 48
+#define REG_WR_ADDR_dma_rw_ctxt_md0 48
+
+/* Register rw_ctxt_md0_s, scope dma, type rw */
+typedef struct {
+  unsigned int md0_s : 16;
+  unsigned int dummy1 : 16;
+} reg_dma_rw_ctxt_md0_s;
+#define REG_RD_ADDR_dma_rw_ctxt_md0_s 52
+#define REG_WR_ADDR_dma_rw_ctxt_md0_s 52
+
+/* Register rw_ctxt_md1, scope dma, type rw */
+typedef unsigned int reg_dma_rw_ctxt_md1;
+#define REG_RD_ADDR_dma_rw_ctxt_md1 56
+#define REG_WR_ADDR_dma_rw_ctxt_md1 56
+
+/* Register rw_ctxt_md1_s, scope dma, type rw */
+typedef unsigned int reg_dma_rw_ctxt_md1_s;
+#define REG_RD_ADDR_dma_rw_ctxt_md1_s 60
+#define REG_WR_ADDR_dma_rw_ctxt_md1_s 60
+
+/* Register rw_ctxt_md2, scope dma, type rw */
+typedef unsigned int reg_dma_rw_ctxt_md2;
+#define REG_RD_ADDR_dma_rw_ctxt_md2 64
+#define REG_WR_ADDR_dma_rw_ctxt_md2 64
+
+/* Register rw_ctxt_md2_s, scope dma, type rw */
+typedef unsigned int reg_dma_rw_ctxt_md2_s;
+#define REG_RD_ADDR_dma_rw_ctxt_md2_s 68
+#define REG_WR_ADDR_dma_rw_ctxt_md2_s 68
+
+/* Register rw_ctxt_md3, scope dma, type rw */
+typedef unsigned int reg_dma_rw_ctxt_md3;
+#define REG_RD_ADDR_dma_rw_ctxt_md3 72
+#define REG_WR_ADDR_dma_rw_ctxt_md3 72
+
+/* Register rw_ctxt_md3_s, scope dma, type rw */
+typedef unsigned int reg_dma_rw_ctxt_md3_s;
+#define REG_RD_ADDR_dma_rw_ctxt_md3_s 76
+#define REG_WR_ADDR_dma_rw_ctxt_md3_s 76
+
+/* Register rw_ctxt_md4, scope dma, type rw */
+typedef unsigned int reg_dma_rw_ctxt_md4;
+#define REG_RD_ADDR_dma_rw_ctxt_md4 80
+#define REG_WR_ADDR_dma_rw_ctxt_md4 80
+
+/* Register rw_ctxt_md4_s, scope dma, type rw */
+typedef unsigned int reg_dma_rw_ctxt_md4_s;
+#define REG_RD_ADDR_dma_rw_ctxt_md4_s 84
+#define REG_WR_ADDR_dma_rw_ctxt_md4_s 84
+
+/* Register rw_saved_data, scope dma, type rw */
+typedef unsigned int reg_dma_rw_saved_data;
+#define REG_RD_ADDR_dma_rw_saved_data 88
+#define REG_WR_ADDR_dma_rw_saved_data 88
+
+/* Register rw_saved_data_buf, scope dma, type rw */
+typedef unsigned int reg_dma_rw_saved_data_buf;
+#define REG_RD_ADDR_dma_rw_saved_data_buf 92
+#define REG_WR_ADDR_dma_rw_saved_data_buf 92
+
+/* Register rw_group, scope dma, type rw */
+typedef unsigned int reg_dma_rw_group;
+#define REG_RD_ADDR_dma_rw_group 96
+#define REG_WR_ADDR_dma_rw_group 96
+
+/* Register rw_group_next, scope dma, type rw */
+typedef unsigned int reg_dma_rw_group_next;
+#define REG_RD_ADDR_dma_rw_group_next 100
+#define REG_WR_ADDR_dma_rw_group_next 100
+
+/* Register rw_group_ctrl, scope dma, type rw */
+typedef struct {
+  unsigned int eol  : 1;
+  unsigned int tol  : 1;
+  unsigned int bol  : 1;
+  unsigned int dummy1 : 1;
+  unsigned int intr : 1;
+  unsigned int dummy2 : 2;
+  unsigned int en   : 1;
+  unsigned int dummy3 : 24;
+} reg_dma_rw_group_ctrl;
+#define REG_RD_ADDR_dma_rw_group_ctrl 104
+#define REG_WR_ADDR_dma_rw_group_ctrl 104
+
+/* Register rw_group_stat, scope dma, type rw */
+typedef struct {
+  unsigned int dummy1 : 7;
+  unsigned int dis : 1;
+  unsigned int dummy2 : 24;
+} reg_dma_rw_group_stat;
+#define REG_RD_ADDR_dma_rw_group_stat 108
+#define REG_WR_ADDR_dma_rw_group_stat 108
+
+/* Register rw_group_md, scope dma, type rw */
+typedef struct {
+  unsigned int md : 16;
+  unsigned int dummy1 : 16;
+} reg_dma_rw_group_md;
+#define REG_RD_ADDR_dma_rw_group_md 112
+#define REG_WR_ADDR_dma_rw_group_md 112
+
+/* Register rw_group_md_s, scope dma, type rw */
+typedef struct {
+  unsigned int md_s : 16;
+  unsigned int dummy1 : 16;
+} reg_dma_rw_group_md_s;
+#define REG_RD_ADDR_dma_rw_group_md_s 116
+#define REG_WR_ADDR_dma_rw_group_md_s 116
+
+/* Register rw_group_up, scope dma, type rw */
+typedef unsigned int reg_dma_rw_group_up;
+#define REG_RD_ADDR_dma_rw_group_up 120
+#define REG_WR_ADDR_dma_rw_group_up 120
+
+/* Register rw_group_down, scope dma, type rw */
+typedef unsigned int reg_dma_rw_group_down;
+#define REG_RD_ADDR_dma_rw_group_down 124
+#define REG_WR_ADDR_dma_rw_group_down 124
+
+/* Register rw_cmd, scope dma, type rw */
+typedef struct {
+  unsigned int cont_data : 1;
+  unsigned int dummy1    : 31;
+} reg_dma_rw_cmd;
+#define REG_RD_ADDR_dma_rw_cmd 128
+#define REG_WR_ADDR_dma_rw_cmd 128
+
+/* Register rw_cfg, scope dma, type rw */
+typedef struct {
+  unsigned int en   : 1;
+  unsigned int stop : 1;
+  unsigned int dummy1 : 30;
+} reg_dma_rw_cfg;
+#define REG_RD_ADDR_dma_rw_cfg 132
+#define REG_WR_ADDR_dma_rw_cfg 132
+
+/* Register rw_stat, scope dma, type rw */
+typedef struct {
+  unsigned int mode           : 5;
+  unsigned int list_state     : 3;
+  unsigned int stream_cmd_src : 8;
+  unsigned int dummy1         : 8;
+  unsigned int buf            : 8;
+} reg_dma_rw_stat;
+#define REG_RD_ADDR_dma_rw_stat 136
+#define REG_WR_ADDR_dma_rw_stat 136
+
+/* Register rw_intr_mask, scope dma, type rw */
+typedef struct {
+  unsigned int group      : 1;
+  unsigned int ctxt       : 1;
+  unsigned int data       : 1;
+  unsigned int in_eop     : 1;
+  unsigned int stream_cmd : 1;
+  unsigned int dummy1     : 27;
+} reg_dma_rw_intr_mask;
+#define REG_RD_ADDR_dma_rw_intr_mask 140
+#define REG_WR_ADDR_dma_rw_intr_mask 140
+
+/* Register rw_ack_intr, scope dma, type rw */
+typedef struct {
+  unsigned int group      : 1;
+  unsigned int ctxt       : 1;
+  unsigned int data       : 1;
+  unsigned int in_eop     : 1;
+  unsigned int stream_cmd : 1;
+  unsigned int dummy1     : 27;
+} reg_dma_rw_ack_intr;
+#define REG_RD_ADDR_dma_rw_ack_intr 144
+#define REG_WR_ADDR_dma_rw_ack_intr 144
+
+/* Register r_intr, scope dma, type r */
+typedef struct {
+  unsigned int group      : 1;
+  unsigned int ctxt       : 1;
+  unsigned int data       : 1;
+  unsigned int in_eop     : 1;
+  unsigned int stream_cmd : 1;
+  unsigned int dummy1     : 27;
+} reg_dma_r_intr;
+#define REG_RD_ADDR_dma_r_intr 148
+
+/* Register r_masked_intr, scope dma, type r */
+typedef struct {
+  unsigned int group      : 1;
+  unsigned int ctxt       : 1;
+  unsigned int data       : 1;
+  unsigned int in_eop     : 1;
+  unsigned int stream_cmd : 1;
+  unsigned int dummy1     : 27;
+} reg_dma_r_masked_intr;
+#define REG_RD_ADDR_dma_r_masked_intr 152
+
+/* Register rw_stream_cmd, scope dma, type rw */
+typedef struct {
+  unsigned int cmd  : 10;
+  unsigned int dummy1 : 6;
+  unsigned int n    : 8;
+  unsigned int dummy2 : 7;
+  unsigned int busy : 1;
+} reg_dma_rw_stream_cmd;
+#define REG_RD_ADDR_dma_rw_stream_cmd 156
+#define REG_WR_ADDR_dma_rw_stream_cmd 156
+
+
+/* Constants */
+enum {
+  regk_dma_ack_pkt                         = 0x00000100,
+  regk_dma_anytime                         = 0x00000001,
+  regk_dma_array                           = 0x00000008,
+  regk_dma_burst                           = 0x00000020,
+  regk_dma_client                          = 0x00000002,
+  regk_dma_copy_next                       = 0x00000010,
+  regk_dma_copy_up                         = 0x00000020,
+  regk_dma_data_at_eol                     = 0x00000001,
+  regk_dma_dis_c                           = 0x00000010,
+  regk_dma_dis_g                           = 0x00000020,
+  regk_dma_idle                            = 0x00000001,
+  regk_dma_intern                          = 0x00000004,
+  regk_dma_load_c                          = 0x00000200,
+  regk_dma_load_c_n                        = 0x00000280,
+  regk_dma_load_c_next                     = 0x00000240,
+  regk_dma_load_d                          = 0x00000140,
+  regk_dma_load_g                          = 0x00000300,
+  regk_dma_load_g_down                     = 0x000003c0,
+  regk_dma_load_g_next                     = 0x00000340,
+  regk_dma_load_g_up                       = 0x00000380,
+  regk_dma_next_en                         = 0x00000010,
+  regk_dma_next_pkt                        = 0x00000010,
+  regk_dma_no                              = 0x00000000,
+  regk_dma_only_at_wait                    = 0x00000000,
+  regk_dma_restore                         = 0x00000020,
+  regk_dma_rst                             = 0x00000001,
+  regk_dma_running                         = 0x00000004,
+  regk_dma_rw_cfg_default                  = 0x00000000,
+  regk_dma_rw_cmd_default                  = 0x00000000,
+  regk_dma_rw_intr_mask_default            = 0x00000000,
+  regk_dma_rw_stat_default                 = 0x00000101,
+  regk_dma_rw_stream_cmd_default           = 0x00000000,
+  regk_dma_save_down                       = 0x00000020,
+  regk_dma_save_up                         = 0x00000020,
+  regk_dma_set_reg                         = 0x00000050,
+  regk_dma_set_w_size1                     = 0x00000190,
+  regk_dma_set_w_size2                     = 0x000001a0,
+  regk_dma_set_w_size4                     = 0x000001c0,
+  regk_dma_stopped                         = 0x00000002,
+  regk_dma_store_c                         = 0x00000002,
+  regk_dma_store_descr                     = 0x00000000,
+  regk_dma_store_g                         = 0x00000004,
+  regk_dma_store_md                        = 0x00000001,
+  regk_dma_sw                              = 0x00000008,
+  regk_dma_update_down                     = 0x00000020,
+  regk_dma_yes                             = 0x00000001
+};
+#endif /* __dma_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/eth_defs.h b/include/asm-cris/arch-v32/hwregs/eth_defs.h
new file mode 100644
index 00000000000..1196d7cc783
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/eth_defs.h
@@ -0,0 +1,384 @@
+#ifndef __eth_defs_h
+#define __eth_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/eth/rtl/eth_regs.r
+ *     id:           eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp
+ *     last modfied: Mon Apr 11 16:07:03 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile eth_defs.h ../../inst/eth/rtl/eth_regs.r
+ *      id: $Id: eth_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope eth */
+
+/* Register rw_ma0_lo, scope eth, type rw */
+typedef struct {
+  unsigned int addr : 32;
+} reg_eth_rw_ma0_lo;
+#define REG_RD_ADDR_eth_rw_ma0_lo 0
+#define REG_WR_ADDR_eth_rw_ma0_lo 0
+
+/* Register rw_ma0_hi, scope eth, type rw */
+typedef struct {
+  unsigned int addr : 16;
+  unsigned int dummy1 : 16;
+} reg_eth_rw_ma0_hi;
+#define REG_RD_ADDR_eth_rw_ma0_hi 4
+#define REG_WR_ADDR_eth_rw_ma0_hi 4
+
+/* Register rw_ma1_lo, scope eth, type rw */
+typedef struct {
+  unsigned int addr : 32;
+} reg_eth_rw_ma1_lo;
+#define REG_RD_ADDR_eth_rw_ma1_lo 8
+#define REG_WR_ADDR_eth_rw_ma1_lo 8
+
+/* Register rw_ma1_hi, scope eth, type rw */
+typedef struct {
+  unsigned int addr : 16;
+  unsigned int dummy1 : 16;
+} reg_eth_rw_ma1_hi;
+#define REG_RD_ADDR_eth_rw_ma1_hi 12
+#define REG_WR_ADDR_eth_rw_ma1_hi 12
+
+/* Register rw_ga_lo, scope eth, type rw */
+typedef struct {
+  unsigned int table : 32;
+} reg_eth_rw_ga_lo;
+#define REG_RD_ADDR_eth_rw_ga_lo 16
+#define REG_WR_ADDR_eth_rw_ga_lo 16
+
+/* Register rw_ga_hi, scope eth, type rw */
+typedef struct {
+  unsigned int table : 32;
+} reg_eth_rw_ga_hi;
+#define REG_RD_ADDR_eth_rw_ga_hi 20
+#define REG_WR_ADDR_eth_rw_ga_hi 20
+
+/* Register rw_gen_ctrl, scope eth, type rw */
+typedef struct {
+  unsigned int en            : 1;
+  unsigned int phy           : 2;
+  unsigned int protocol      : 1;
+  unsigned int loopback      : 1;
+  unsigned int flow_ctrl_dis : 1;
+  unsigned int dummy1        : 26;
+} reg_eth_rw_gen_ctrl;
+#define REG_RD_ADDR_eth_rw_gen_ctrl 24
+#define REG_WR_ADDR_eth_rw_gen_ctrl 24
+
+/* Register rw_rec_ctrl, scope eth, type rw */
+typedef struct {
+  unsigned int ma0        : 1;
+  unsigned int ma1        : 1;
+  unsigned int individual : 1;
+  unsigned int broadcast  : 1;
+  unsigned int undersize  : 1;
+  unsigned int oversize   : 1;
+  unsigned int bad_crc    : 1;
+  unsigned int duplex     : 1;
+  unsigned int max_size   : 1;
+  unsigned int dummy1     : 23;
+} reg_eth_rw_rec_ctrl;
+#define REG_RD_ADDR_eth_rw_rec_ctrl 28
+#define REG_WR_ADDR_eth_rw_rec_ctrl 28
+
+/* Register rw_tr_ctrl, scope eth, type rw */
+typedef struct {
+  unsigned int crc        : 1;
+  unsigned int pad        : 1;
+  unsigned int retry      : 1;
+  unsigned int ignore_col : 1;
+  unsigned int cancel     : 1;
+  unsigned int hsh_delay  : 1;
+  unsigned int ignore_crs : 1;
+  unsigned int dummy1     : 25;
+} reg_eth_rw_tr_ctrl;
+#define REG_RD_ADDR_eth_rw_tr_ctrl 32
+#define REG_WR_ADDR_eth_rw_tr_ctrl 32
+
+/* Register rw_clr_err, scope eth, type rw */
+typedef struct {
+  unsigned int clr : 1;
+  unsigned int dummy1 : 31;
+} reg_eth_rw_clr_err;
+#define REG_RD_ADDR_eth_rw_clr_err 36
+#define REG_WR_ADDR_eth_rw_clr_err 36
+
+/* Register rw_mgm_ctrl, scope eth, type rw */
+typedef struct {
+  unsigned int mdio   : 1;
+  unsigned int mdoe   : 1;
+  unsigned int mdc    : 1;
+  unsigned int phyclk : 1;
+  unsigned int txdata : 4;
+  unsigned int txen   : 1;
+  unsigned int dummy1 : 23;
+} reg_eth_rw_mgm_ctrl;
+#define REG_RD_ADDR_eth_rw_mgm_ctrl 40
+#define REG_WR_ADDR_eth_rw_mgm_ctrl 40
+
+/* Register r_stat, scope eth, type r */
+typedef struct {
+  unsigned int mdio    : 1;
+  unsigned int exc_col : 1;
+  unsigned int urun    : 1;
+  unsigned int phyclk  : 1;
+  unsigned int txdata  : 4;
+  unsigned int txen    : 1;
+  unsigned int col     : 1;
+  unsigned int crs     : 1;
+  unsigned int txclk   : 1;
+  unsigned int rxdata  : 4;
+  unsigned int rxer    : 1;
+  unsigned int rxdv    : 1;
+  unsigned int rxclk   : 1;
+  unsigned int dummy1  : 13;
+} reg_eth_r_stat;
+#define REG_RD_ADDR_eth_r_stat 44
+
+/* Register rs_rec_cnt, scope eth, type rs */
+typedef struct {
+  unsigned int crc_err    : 8;
+  unsigned int align_err  : 8;
+  unsigned int oversize   : 8;
+  unsigned int congestion : 8;
+} reg_eth_rs_rec_cnt;
+#define REG_RD_ADDR_eth_rs_rec_cnt 48
+
+/* Register r_rec_cnt, scope eth, type r */
+typedef struct {
+  unsigned int crc_err    : 8;
+  unsigned int align_err  : 8;
+  unsigned int oversize   : 8;
+  unsigned int congestion : 8;
+} reg_eth_r_rec_cnt;
+#define REG_RD_ADDR_eth_r_rec_cnt 52
+
+/* Register rs_tr_cnt, scope eth, type rs */
+typedef struct {
+  unsigned int single_col : 8;
+  unsigned int mult_col   : 8;
+  unsigned int late_col   : 8;
+  unsigned int deferred   : 8;
+} reg_eth_rs_tr_cnt;
+#define REG_RD_ADDR_eth_rs_tr_cnt 56
+
+/* Register r_tr_cnt, scope eth, type r */
+typedef struct {
+  unsigned int single_col : 8;
+  unsigned int mult_col   : 8;
+  unsigned int late_col   : 8;
+  unsigned int deferred   : 8;
+} reg_eth_r_tr_cnt;
+#define REG_RD_ADDR_eth_r_tr_cnt 60
+
+/* Register rs_phy_cnt, scope eth, type rs */
+typedef struct {
+  unsigned int carrier_loss : 8;
+  unsigned int sqe_err      : 8;
+  unsigned int dummy1       : 16;
+} reg_eth_rs_phy_cnt;
+#define REG_RD_ADDR_eth_rs_phy_cnt 64
+
+/* Register r_phy_cnt, scope eth, type r */
+typedef struct {
+  unsigned int carrier_loss : 8;
+  unsigned int sqe_err      : 8;
+  unsigned int dummy1       : 16;
+} reg_eth_r_phy_cnt;
+#define REG_RD_ADDR_eth_r_phy_cnt 68
+
+/* Register rw_test_ctrl, scope eth, type rw */
+typedef struct {
+  unsigned int snmp_inc : 1;
+  unsigned int snmp     : 1;
+  unsigned int backoff  : 1;
+  unsigned int dummy1   : 29;
+} reg_eth_rw_test_ctrl;
+#define REG_RD_ADDR_eth_rw_test_ctrl 72
+#define REG_WR_ADDR_eth_rw_test_ctrl 72
+
+/* Register rw_intr_mask, scope eth, type rw */
+typedef struct {
+  unsigned int crc           : 1;
+  unsigned int align         : 1;
+  unsigned int oversize      : 1;
+  unsigned int congestion    : 1;
+  unsigned int single_col    : 1;
+  unsigned int mult_col      : 1;
+  unsigned int late_col      : 1;
+  unsigned int deferred      : 1;
+  unsigned int carrier_loss  : 1;
+  unsigned int sqe_test_err  : 1;
+  unsigned int orun          : 1;
+  unsigned int urun          : 1;
+  unsigned int excessive_col : 1;
+  unsigned int mdio          : 1;
+  unsigned int dummy1        : 18;
+} reg_eth_rw_intr_mask;
+#define REG_RD_ADDR_eth_rw_intr_mask 76
+#define REG_WR_ADDR_eth_rw_intr_mask 76
+
+/* Register rw_ack_intr, scope eth, type rw */
+typedef struct {
+  unsigned int crc           : 1;
+  unsigned int align         : 1;
+  unsigned int oversize      : 1;
+  unsigned int congestion    : 1;
+  unsigned int single_col    : 1;
+  unsigned int mult_col      : 1;
+  unsigned int late_col      : 1;
+  unsigned int deferred      : 1;
+  unsigned int carrier_loss  : 1;
+  unsigned int sqe_test_err  : 1;
+  unsigned int orun          : 1;
+  unsigned int urun          : 1;
+  unsigned int excessive_col : 1;
+  unsigned int mdio          : 1;
+  unsigned int dummy1        : 18;
+} reg_eth_rw_ack_intr;
+#define REG_RD_ADDR_eth_rw_ack_intr 80
+#define REG_WR_ADDR_eth_rw_ack_intr 80
+
+/* Register r_intr, scope eth, type r */
+typedef struct {
+  unsigned int crc           : 1;
+  unsigned int align         : 1;
+  unsigned int oversize      : 1;
+  unsigned int congestion    : 1;
+  unsigned int single_col    : 1;
+  unsigned int mult_col      : 1;
+  unsigned int late_col      : 1;
+  unsigned int deferred      : 1;
+  unsigned int carrier_loss  : 1;
+  unsigned int sqe_test_err  : 1;
+  unsigned int orun          : 1;
+  unsigned int urun          : 1;
+  unsigned int excessive_col : 1;
+  unsigned int mdio          : 1;
+  unsigned int dummy1        : 18;
+} reg_eth_r_intr;
+#define REG_RD_ADDR_eth_r_intr 84
+
+/* Register r_masked_intr, scope eth, type r */
+typedef struct {
+  unsigned int crc           : 1;
+  unsigned int align         : 1;
+  unsigned int oversize      : 1;
+  unsigned int congestion    : 1;
+  unsigned int single_col    : 1;
+  unsigned int mult_col      : 1;
+  unsigned int late_col      : 1;
+  unsigned int deferred      : 1;
+  unsigned int carrier_loss  : 1;
+  unsigned int sqe_test_err  : 1;
+  unsigned int orun          : 1;
+  unsigned int urun          : 1;
+  unsigned int excessive_col : 1;
+  unsigned int mdio          : 1;
+  unsigned int dummy1        : 18;
+} reg_eth_r_masked_intr;
+#define REG_RD_ADDR_eth_r_masked_intr 88
+
+
+/* Constants */
+enum {
+  regk_eth_discard                         = 0x00000000,
+  regk_eth_ether                           = 0x00000000,
+  regk_eth_full                            = 0x00000001,
+  regk_eth_half                            = 0x00000000,
+  regk_eth_hsh                             = 0x00000001,
+  regk_eth_mii                             = 0x00000001,
+  regk_eth_mii_clk                         = 0x00000000,
+  regk_eth_mii_rec                         = 0x00000002,
+  regk_eth_no                              = 0x00000000,
+  regk_eth_rec                             = 0x00000001,
+  regk_eth_rw_ga_hi_default                = 0x00000000,
+  regk_eth_rw_ga_lo_default                = 0x00000000,
+  regk_eth_rw_gen_ctrl_default             = 0x00000000,
+  regk_eth_rw_intr_mask_default            = 0x00000000,
+  regk_eth_rw_ma0_hi_default               = 0x00000000,
+  regk_eth_rw_ma0_lo_default               = 0x00000000,
+  regk_eth_rw_ma1_hi_default               = 0x00000000,
+  regk_eth_rw_ma1_lo_default               = 0x00000000,
+  regk_eth_rw_mgm_ctrl_default             = 0x00000000,
+  regk_eth_rw_test_ctrl_default            = 0x00000000,
+  regk_eth_size1518                        = 0x00000000,
+  regk_eth_size1522                        = 0x00000001,
+  regk_eth_yes                             = 0x00000001
+};
+#endif /* __eth_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/extmem_defs.h b/include/asm-cris/arch-v32/hwregs/extmem_defs.h
new file mode 100644
index 00000000000..c47b5ca48ec
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/extmem_defs.h
@@ -0,0 +1,369 @@
+#ifndef __extmem_defs_h
+#define __extmem_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/ext_mem/mod/extmem_regs.r
+ *     id:           extmem_regs.r,v 1.1 2004/02/16 13:29:30 np Exp
+ *     last modfied: Tue Mar 30 22:26:21 2004
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile extmem_defs.h ../../inst/ext_mem/mod/extmem_regs.r
+ *      id: $Id: extmem_defs.h,v 1.5 2004/06/04 07:15:33 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope extmem */
+
+/* Register rw_cse0_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_cse0_cfg;
+#define REG_RD_ADDR_extmem_rw_cse0_cfg 0
+#define REG_WR_ADDR_extmem_rw_cse0_cfg 0
+
+/* Register rw_cse1_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_cse1_cfg;
+#define REG_RD_ADDR_extmem_rw_cse1_cfg 4
+#define REG_WR_ADDR_extmem_rw_cse1_cfg 4
+
+/* Register rw_csr0_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_csr0_cfg;
+#define REG_RD_ADDR_extmem_rw_csr0_cfg 8
+#define REG_WR_ADDR_extmem_rw_csr0_cfg 8
+
+/* Register rw_csr1_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_csr1_cfg;
+#define REG_RD_ADDR_extmem_rw_csr1_cfg 12
+#define REG_WR_ADDR_extmem_rw_csr1_cfg 12
+
+/* Register rw_csp0_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_csp0_cfg;
+#define REG_RD_ADDR_extmem_rw_csp0_cfg 16
+#define REG_WR_ADDR_extmem_rw_csp0_cfg 16
+
+/* Register rw_csp1_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_csp1_cfg;
+#define REG_RD_ADDR_extmem_rw_csp1_cfg 20
+#define REG_WR_ADDR_extmem_rw_csp1_cfg 20
+
+/* Register rw_csp2_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_csp2_cfg;
+#define REG_RD_ADDR_extmem_rw_csp2_cfg 24
+#define REG_WR_ADDR_extmem_rw_csp2_cfg 24
+
+/* Register rw_csp3_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_csp3_cfg;
+#define REG_RD_ADDR_extmem_rw_csp3_cfg 28
+#define REG_WR_ADDR_extmem_rw_csp3_cfg 28
+
+/* Register rw_csp4_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_csp4_cfg;
+#define REG_RD_ADDR_extmem_rw_csp4_cfg 32
+#define REG_WR_ADDR_extmem_rw_csp4_cfg 32
+
+/* Register rw_csp5_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_csp5_cfg;
+#define REG_RD_ADDR_extmem_rw_csp5_cfg 36
+#define REG_WR_ADDR_extmem_rw_csp5_cfg 36
+
+/* Register rw_csp6_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_csp6_cfg;
+#define REG_RD_ADDR_extmem_rw_csp6_cfg 40
+#define REG_WR_ADDR_extmem_rw_csp6_cfg 40
+
+/* Register rw_css_cfg, scope extmem, type rw */
+typedef struct {
+  unsigned int lw     : 6;
+  unsigned int ew     : 3;
+  unsigned int zw     : 3;
+  unsigned int aw     : 2;
+  unsigned int dw     : 2;
+  unsigned int ewb    : 2;
+  unsigned int bw     : 1;
+  unsigned int mode   : 1;
+  unsigned int erc_en : 1;
+  unsigned int dummy1 : 6;
+  unsigned int size   : 3;
+  unsigned int log    : 1;
+  unsigned int en     : 1;
+} reg_extmem_rw_css_cfg;
+#define REG_RD_ADDR_extmem_rw_css_cfg 44
+#define REG_WR_ADDR_extmem_rw_css_cfg 44
+
+/* Register rw_status_handle, scope extmem, type rw */
+typedef struct {
+  unsigned int h : 32;
+} reg_extmem_rw_status_handle;
+#define REG_RD_ADDR_extmem_rw_status_handle 48
+#define REG_WR_ADDR_extmem_rw_status_handle 48
+
+/* Register rw_wait_pin, scope extmem, type rw */
+typedef struct {
+  unsigned int val   : 16;
+  unsigned int dummy1 : 15;
+  unsigned int start : 1;
+} reg_extmem_rw_wait_pin;
+#define REG_RD_ADDR_extmem_rw_wait_pin 52
+#define REG_WR_ADDR_extmem_rw_wait_pin 52
+
+/* Register rw_gated_csp, scope extmem, type rw */
+typedef struct {
+  unsigned int dummy1 : 31;
+  unsigned int en : 1;
+} reg_extmem_rw_gated_csp;
+#define REG_RD_ADDR_extmem_rw_gated_csp 56
+#define REG_WR_ADDR_extmem_rw_gated_csp 56
+
+
+/* Constants */
+enum {
+  regk_extmem_b16                          = 0x00000001,
+  regk_extmem_b32                          = 0x00000000,
+  regk_extmem_bwe                          = 0x00000000,
+  regk_extmem_cwe                          = 0x00000001,
+  regk_extmem_no                           = 0x00000000,
+  regk_extmem_rw_cse0_cfg_default          = 0x000006cf,
+  regk_extmem_rw_cse1_cfg_default          = 0x000006cf,
+  regk_extmem_rw_csp0_cfg_default          = 0x000006cf,
+  regk_extmem_rw_csp1_cfg_default          = 0x000006cf,
+  regk_extmem_rw_csp2_cfg_default          = 0x000006cf,
+  regk_extmem_rw_csp3_cfg_default          = 0x000006cf,
+  regk_extmem_rw_csp4_cfg_default          = 0x000006cf,
+  regk_extmem_rw_csp5_cfg_default          = 0x000006cf,
+  regk_extmem_rw_csp6_cfg_default          = 0x000006cf,
+  regk_extmem_rw_csr0_cfg_default          = 0x000006cf,
+  regk_extmem_rw_csr1_cfg_default          = 0x000006cf,
+  regk_extmem_rw_css_cfg_default           = 0x000006cf,
+  regk_extmem_s128KB                       = 0x00000000,
+  regk_extmem_s16MB                        = 0x00000005,
+  regk_extmem_s1MB                         = 0x00000001,
+  regk_extmem_s2MB                         = 0x00000002,
+  regk_extmem_s32MB                        = 0x00000006,
+  regk_extmem_s4MB                         = 0x00000003,
+  regk_extmem_s64MB                        = 0x00000007,
+  regk_extmem_s8MB                         = 0x00000004,
+  regk_extmem_yes                          = 0x00000001
+};
+#endif /* __extmem_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/gio_defs.h b/include/asm-cris/arch-v32/hwregs/gio_defs.h
new file mode 100644
index 00000000000..3e9a0b25366
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/gio_defs.h
@@ -0,0 +1,295 @@
+#ifndef __gio_defs_h
+#define __gio_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/gio/rtl/gio_regs.r
+ *     id:           gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
+ *     last modfied: Mon Apr 11 16:07:47 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r
+ *      id: $Id: gio_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope gio */
+
+/* Register rw_pa_dout, scope gio, type rw */
+typedef struct {
+  unsigned int data : 8;
+  unsigned int dummy1 : 24;
+} reg_gio_rw_pa_dout;
+#define REG_RD_ADDR_gio_rw_pa_dout 0
+#define REG_WR_ADDR_gio_rw_pa_dout 0
+
+/* Register r_pa_din, scope gio, type r */
+typedef struct {
+  unsigned int data : 8;
+  unsigned int dummy1 : 24;
+} reg_gio_r_pa_din;
+#define REG_RD_ADDR_gio_r_pa_din 4
+
+/* Register rw_pa_oe, scope gio, type rw */
+typedef struct {
+  unsigned int oe : 8;
+  unsigned int dummy1 : 24;
+} reg_gio_rw_pa_oe;
+#define REG_RD_ADDR_gio_rw_pa_oe 8
+#define REG_WR_ADDR_gio_rw_pa_oe 8
+
+/* Register rw_intr_cfg, scope gio, type rw */
+typedef struct {
+  unsigned int pa0 : 3;
+  unsigned int pa1 : 3;
+  unsigned int pa2 : 3;
+  unsigned int pa3 : 3;
+  unsigned int pa4 : 3;
+  unsigned int pa5 : 3;
+  unsigned int pa6 : 3;
+  unsigned int pa7 : 3;
+  unsigned int dummy1 : 8;
+} reg_gio_rw_intr_cfg;
+#define REG_RD_ADDR_gio_rw_intr_cfg 12
+#define REG_WR_ADDR_gio_rw_intr_cfg 12
+
+/* Register rw_intr_mask, scope gio, type rw */
+typedef struct {
+  unsigned int pa0 : 1;
+  unsigned int pa1 : 1;
+  unsigned int pa2 : 1;
+  unsigned int pa3 : 1;
+  unsigned int pa4 : 1;
+  unsigned int pa5 : 1;
+  unsigned int pa6 : 1;
+  unsigned int pa7 : 1;
+  unsigned int dummy1 : 24;
+} reg_gio_rw_intr_mask;
+#define REG_RD_ADDR_gio_rw_intr_mask 16
+#define REG_WR_ADDR_gio_rw_intr_mask 16
+
+/* Register rw_ack_intr, scope gio, type rw */
+typedef struct {
+  unsigned int pa0 : 1;
+  unsigned int pa1 : 1;
+  unsigned int pa2 : 1;
+  unsigned int pa3 : 1;
+  unsigned int pa4 : 1;
+  unsigned int pa5 : 1;
+  unsigned int pa6 : 1;
+  unsigned int pa7 : 1;
+  unsigned int dummy1 : 24;
+} reg_gio_rw_ack_intr;
+#define REG_RD_ADDR_gio_rw_ack_intr 20
+#define REG_WR_ADDR_gio_rw_ack_intr 20
+
+/* Register r_intr, scope gio, type r */
+typedef struct {
+  unsigned int pa0 : 1;
+  unsigned int pa1 : 1;
+  unsigned int pa2 : 1;
+  unsigned int pa3 : 1;
+  unsigned int pa4 : 1;
+  unsigned int pa5 : 1;
+  unsigned int pa6 : 1;
+  unsigned int pa7 : 1;
+  unsigned int dummy1 : 24;
+} reg_gio_r_intr;
+#define REG_RD_ADDR_gio_r_intr 24
+
+/* Register r_masked_intr, scope gio, type r */
+typedef struct {
+  unsigned int pa0 : 1;
+  unsigned int pa1 : 1;
+  unsigned int pa2 : 1;
+  unsigned int pa3 : 1;
+  unsigned int pa4 : 1;
+  unsigned int pa5 : 1;
+  unsigned int pa6 : 1;
+  unsigned int pa7 : 1;
+  unsigned int dummy1 : 24;
+} reg_gio_r_masked_intr;
+#define REG_RD_ADDR_gio_r_masked_intr 28
+
+/* Register rw_pb_dout, scope gio, type rw */
+typedef struct {
+  unsigned int data : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_rw_pb_dout;
+#define REG_RD_ADDR_gio_rw_pb_dout 32
+#define REG_WR_ADDR_gio_rw_pb_dout 32
+
+/* Register r_pb_din, scope gio, type r */
+typedef struct {
+  unsigned int data : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_r_pb_din;
+#define REG_RD_ADDR_gio_r_pb_din 36
+
+/* Register rw_pb_oe, scope gio, type rw */
+typedef struct {
+  unsigned int oe : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_rw_pb_oe;
+#define REG_RD_ADDR_gio_rw_pb_oe 40
+#define REG_WR_ADDR_gio_rw_pb_oe 40
+
+/* Register rw_pc_dout, scope gio, type rw */
+typedef struct {
+  unsigned int data : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_rw_pc_dout;
+#define REG_RD_ADDR_gio_rw_pc_dout 48
+#define REG_WR_ADDR_gio_rw_pc_dout 48
+
+/* Register r_pc_din, scope gio, type r */
+typedef struct {
+  unsigned int data : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_r_pc_din;
+#define REG_RD_ADDR_gio_r_pc_din 52
+
+/* Register rw_pc_oe, scope gio, type rw */
+typedef struct {
+  unsigned int oe : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_rw_pc_oe;
+#define REG_RD_ADDR_gio_rw_pc_oe 56
+#define REG_WR_ADDR_gio_rw_pc_oe 56
+
+/* Register rw_pd_dout, scope gio, type rw */
+typedef struct {
+  unsigned int data : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_rw_pd_dout;
+#define REG_RD_ADDR_gio_rw_pd_dout 64
+#define REG_WR_ADDR_gio_rw_pd_dout 64
+
+/* Register r_pd_din, scope gio, type r */
+typedef struct {
+  unsigned int data : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_r_pd_din;
+#define REG_RD_ADDR_gio_r_pd_din 68
+
+/* Register rw_pd_oe, scope gio, type rw */
+typedef struct {
+  unsigned int oe : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_rw_pd_oe;
+#define REG_RD_ADDR_gio_rw_pd_oe 72
+#define REG_WR_ADDR_gio_rw_pd_oe 72
+
+/* Register rw_pe_dout, scope gio, type rw */
+typedef struct {
+  unsigned int data : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_rw_pe_dout;
+#define REG_RD_ADDR_gio_rw_pe_dout 80
+#define REG_WR_ADDR_gio_rw_pe_dout 80
+
+/* Register r_pe_din, scope gio, type r */
+typedef struct {
+  unsigned int data : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_r_pe_din;
+#define REG_RD_ADDR_gio_r_pe_din 84
+
+/* Register rw_pe_oe, scope gio, type rw */
+typedef struct {
+  unsigned int oe : 18;
+  unsigned int dummy1 : 14;
+} reg_gio_rw_pe_oe;
+#define REG_RD_ADDR_gio_rw_pe_oe 88
+#define REG_WR_ADDR_gio_rw_pe_oe 88
+
+
+/* Constants */
+enum {
+  regk_gio_anyedge                         = 0x00000007,
+  regk_gio_hi                              = 0x00000001,
+  regk_gio_lo                              = 0x00000002,
+  regk_gio_negedge                         = 0x00000006,
+  regk_gio_no                              = 0x00000000,
+  regk_gio_off                             = 0x00000000,
+  regk_gio_posedge                         = 0x00000005,
+  regk_gio_rw_intr_cfg_default             = 0x00000000,
+  regk_gio_rw_intr_mask_default            = 0x00000000,
+  regk_gio_rw_pa_oe_default                = 0x00000000,
+  regk_gio_rw_pb_oe_default                = 0x00000000,
+  regk_gio_rw_pc_oe_default                = 0x00000000,
+  regk_gio_rw_pd_oe_default                = 0x00000000,
+  regk_gio_rw_pe_oe_default                = 0x00000000,
+  regk_gio_set                             = 0x00000003,
+  regk_gio_yes                             = 0x00000001
+};
+#endif /* __gio_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/intr_vect.h b/include/asm-cris/arch-v32/hwregs/intr_vect.h
new file mode 100644
index 00000000000..5c1b28fb205
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/intr_vect.h
@@ -0,0 +1,39 @@
+/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
+ from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
+version . */
+
+#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
+#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
+#define MEMARB_INTR_VECT	0x31
+#define GEN_IO_INTR_VECT	0x32
+#define IOP0_INTR_VECT	0x33
+#define IOP1_INTR_VECT	0x34
+#define IOP2_INTR_VECT	0x35
+#define IOP3_INTR_VECT	0x36
+#define DMA0_INTR_VECT	0x37
+#define DMA1_INTR_VECT	0x38
+#define DMA2_INTR_VECT	0x39
+#define DMA3_INTR_VECT	0x3a
+#define DMA4_INTR_VECT	0x3b
+#define DMA5_INTR_VECT	0x3c
+#define DMA6_INTR_VECT	0x3d
+#define DMA7_INTR_VECT	0x3e
+#define DMA8_INTR_VECT	0x3f
+#define DMA9_INTR_VECT	0x40
+#define ATA_INTR_VECT	0x41
+#define SSER0_INTR_VECT	0x42
+#define SSER1_INTR_VECT	0x43
+#define SER0_INTR_VECT	0x44
+#define SER1_INTR_VECT	0x45
+#define SER2_INTR_VECT	0x46
+#define SER3_INTR_VECT	0x47
+#define P21_INTR_VECT	0x48
+#define ETH0_INTR_VECT	0x49
+#define ETH1_INTR_VECT	0x4a
+#define TIMER_INTR_VECT	0x4b
+#define BIF_ARB_INTR_VECT	0x4c
+#define BIF_DMA_INTR_VECT	0x4d
+#define EXT_INTR_VECT	0x4e
+#define IPI_INTR_VECT	0x4f
+
+#endif
diff --git a/include/asm-cris/arch-v32/hwregs/intr_vect_defs.h b/include/asm-cris/arch-v32/hwregs/intr_vect_defs.h
new file mode 100644
index 00000000000..535aaf1b4b5
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/intr_vect_defs.h
@@ -0,0 +1,225 @@
+#ifndef __intr_vect_defs_h
+#define __intr_vect_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/intr_vect/rtl/guinness/ivmask.config.r
+ *     id:           ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp
+ *     last modfied: Mon Apr 11 16:08:03 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
+ *      id: $Id: intr_vect_defs.h,v 1.8 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope intr_vect */
+
+/* Register rw_mask, scope intr_vect, type rw */
+typedef struct {
+  unsigned int memarb  : 1;
+  unsigned int gen_io  : 1;
+  unsigned int iop0    : 1;
+  unsigned int iop1    : 1;
+  unsigned int iop2    : 1;
+  unsigned int iop3    : 1;
+  unsigned int dma0    : 1;
+  unsigned int dma1    : 1;
+  unsigned int dma2    : 1;
+  unsigned int dma3    : 1;
+  unsigned int dma4    : 1;
+  unsigned int dma5    : 1;
+  unsigned int dma6    : 1;
+  unsigned int dma7    : 1;
+  unsigned int dma8    : 1;
+  unsigned int dma9    : 1;
+  unsigned int ata     : 1;
+  unsigned int sser0   : 1;
+  unsigned int sser1   : 1;
+  unsigned int ser0    : 1;
+  unsigned int ser1    : 1;
+  unsigned int ser2    : 1;
+  unsigned int ser3    : 1;
+  unsigned int p21     : 1;
+  unsigned int eth0    : 1;
+  unsigned int eth1    : 1;
+  unsigned int timer   : 1;
+  unsigned int bif_arb : 1;
+  unsigned int bif_dma : 1;
+  unsigned int ext     : 1;
+  unsigned int dummy1  : 2;
+} reg_intr_vect_rw_mask;
+#define REG_RD_ADDR_intr_vect_rw_mask 0
+#define REG_WR_ADDR_intr_vect_rw_mask 0
+
+/* Register r_vect, scope intr_vect, type r */
+typedef struct {
+  unsigned int memarb  : 1;
+  unsigned int gen_io  : 1;
+  unsigned int iop0    : 1;
+  unsigned int iop1    : 1;
+  unsigned int iop2    : 1;
+  unsigned int iop3    : 1;
+  unsigned int dma0    : 1;
+  unsigned int dma1    : 1;
+  unsigned int dma2    : 1;
+  unsigned int dma3    : 1;
+  unsigned int dma4    : 1;
+  unsigned int dma5    : 1;
+  unsigned int dma6    : 1;
+  unsigned int dma7    : 1;
+  unsigned int dma8    : 1;
+  unsigned int dma9    : 1;
+  unsigned int ata     : 1;
+  unsigned int sser0   : 1;
+  unsigned int sser1   : 1;
+  unsigned int ser0    : 1;
+  unsigned int ser1    : 1;
+  unsigned int ser2    : 1;
+  unsigned int ser3    : 1;
+  unsigned int p21     : 1;
+  unsigned int eth0    : 1;
+  unsigned int eth1    : 1;
+  unsigned int timer   : 1;
+  unsigned int bif_arb : 1;
+  unsigned int bif_dma : 1;
+  unsigned int ext     : 1;
+  unsigned int dummy1  : 2;
+} reg_intr_vect_r_vect;
+#define REG_RD_ADDR_intr_vect_r_vect 4
+
+/* Register r_masked_vect, scope intr_vect, type r */
+typedef struct {
+  unsigned int memarb  : 1;
+  unsigned int gen_io  : 1;
+  unsigned int iop0    : 1;
+  unsigned int iop1    : 1;
+  unsigned int iop2    : 1;
+  unsigned int iop3    : 1;
+  unsigned int dma0    : 1;
+  unsigned int dma1    : 1;
+  unsigned int dma2    : 1;
+  unsigned int dma3    : 1;
+  unsigned int dma4    : 1;
+  unsigned int dma5    : 1;
+  unsigned int dma6    : 1;
+  unsigned int dma7    : 1;
+  unsigned int dma8    : 1;
+  unsigned int dma9    : 1;
+  unsigned int ata     : 1;
+  unsigned int sser0   : 1;
+  unsigned int sser1   : 1;
+  unsigned int ser0    : 1;
+  unsigned int ser1    : 1;
+  unsigned int ser2    : 1;
+  unsigned int ser3    : 1;
+  unsigned int p21     : 1;
+  unsigned int eth0    : 1;
+  unsigned int eth1    : 1;
+  unsigned int timer   : 1;
+  unsigned int bif_arb : 1;
+  unsigned int bif_dma : 1;
+  unsigned int ext     : 1;
+  unsigned int dummy1  : 2;
+} reg_intr_vect_r_masked_vect;
+#define REG_RD_ADDR_intr_vect_r_masked_vect 8
+
+/* Register r_nmi, scope intr_vect, type r */
+typedef struct {
+  unsigned int ext      : 1;
+  unsigned int watchdog : 1;
+  unsigned int dummy1   : 30;
+} reg_intr_vect_r_nmi;
+#define REG_RD_ADDR_intr_vect_r_nmi 12
+
+/* Register r_guru, scope intr_vect, type r */
+typedef struct {
+  unsigned int jtag : 1;
+  unsigned int dummy1 : 31;
+} reg_intr_vect_r_guru;
+#define REG_RD_ADDR_intr_vect_r_guru 16
+
+/* Register rw_ipi, scope intr_vect, type rw */
+typedef struct
+{
+  unsigned int vector;
+} reg_intr_vect_rw_ipi;
+#define REG_RD_ADDR_intr_vect_rw_ipi 20
+#define REG_WR_ADDR_intr_vect_rw_ipi 20
+
+/* Constants */
+enum {
+  regk_intr_vect_off                       = 0x00000000,
+  regk_intr_vect_on                        = 0x00000001,
+  regk_intr_vect_rw_mask_default           = 0x00000000
+};
+#endif /* __intr_vect_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/Makefile b/include/asm-cris/arch-v32/hwregs/iop/Makefile
new file mode 100644
index 00000000000..a90056a095e
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/Makefile
@@ -0,0 +1,146 @@
+# $Id: Makefile,v 1.3 2004/01/07 20:34:55 johana Exp $
+# Makefile to generate or copy the latest register definitions
+# and related datastructures and helpermacros.
+# The offical place for these files is probably at:
+RELEASE ?= r1_alfa5
+IOPOFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/
+
+IOPROCDIR = /n/asic/design/io/io_proc/rtl
+
+IOPROCINCL_FILES =
+IOPROCINCL_FILES2=
+IOPROCINCL_FILES += iop_crc_par_defs.h
+IOPROCINCL_FILES += iop_dmc_in_defs.h
+IOPROCINCL_FILES += iop_dmc_out_defs.h
+IOPROCINCL_FILES += iop_fifo_in_defs.h
+IOPROCINCL_FILES += iop_fifo_in_xtra_defs.h
+IOPROCINCL_FILES += iop_fifo_out_defs.h
+IOPROCINCL_FILES += iop_fifo_out_xtra_defs.h
+IOPROCINCL_FILES += iop_mpu_defs.h
+IOPROCINCL_FILES2+= iop_mpu_macros.h
+IOPROCINCL_FILES2+= iop_reg_space.h
+IOPROCINCL_FILES += iop_sap_in_defs.h
+IOPROCINCL_FILES += iop_sap_out_defs.h
+IOPROCINCL_FILES += iop_scrc_in_defs.h
+IOPROCINCL_FILES += iop_scrc_out_defs.h
+IOPROCINCL_FILES += iop_spu_defs.h
+# in guiness/
+IOPROCINCL_FILES += iop_sw_cfg_defs.h
+IOPROCINCL_FILES += iop_sw_cpu_defs.h
+IOPROCINCL_FILES += iop_sw_mpu_defs.h
+IOPROCINCL_FILES += iop_sw_spu_defs.h
+#
+IOPROCINCL_FILES += iop_timer_grp_defs.h
+IOPROCINCL_FILES += iop_trigger_grp_defs.h
+# in guiness/
+IOPROCINCL_FILES += iop_version_defs.h
+
+IOPROCASMINCL_FILES = $(patsubst %_defs.h,%_defs_asm.h,$(IOPROCINCL_FILES))
+IOPROCASMINCL_FILES+= iop_reg_space_asm.h
+
+
+IOPROCREGDESC =
+IOPROCREGDESC += $(IOPROCDIR)/iop_crc_par.r
+#IOPROCREGDESC += $(IOPROCDIR)/iop_crc_ser.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_in.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_out.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in_xtra.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out_xtra.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_mpu.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_sap_in.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_sap_out.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_in.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_out.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_spu.r
+IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cfg.r
+IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cpu.r
+IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_mpu.r
+IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_spu.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_timer_grp.r
+IOPROCREGDESC += $(IOPROCDIR)/iop_trigger_grp.r
+IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_version.r
+
+
+RDES2C = /n/asic/bin/rdes2c
+RDES2C = /n/asic/design/tools/rdesc/rdes2c
+RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr
+RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt
+
+## all    - Just print help - you probably want to do 'make gen'
+all: help
+
+## help   - This help
+help:
+	@grep '^## ' Makefile
+
+## gen    - Generate include files
+gen: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES)
+	echo "INCL: $(IOPROCINCL_FILES)"
+	echo "INCL2: $(IOPROCINCL_FILES2)"
+	echo "ASMINCL: $(IOPROCASMINCL_FILES)"
+
+# From the official location...
+iop_reg_space.h: $(IOPOFFICIAL_INCDIR)/iop_reg_space.h
+	cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
+iop_mpu_macros.h: $(IOPOFFICIAL_INCDIR)/iop_mpu_macros.h
+	cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
+
+## copy   - Copy files from official location
+copy:
+	@echo "## Copying and fixing iop files ##"
+	@for HFILE in $(IOPROCINCL_FILES); do \
+		echo "  $$HFILE"; \
+		cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
+	done
+	@for HFILE in $(IOPROCINCL_FILES2); do \
+		echo "  $$HFILE"; \
+		cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
+	done
+	@echo "## Copying and fixing iop asm files ##"
+	@for HFILE in $(IOPROCASMINCL_FILES); do \
+		echo "  $$HFILE"; \
+		cat $(IOPOFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > asm/$$HFILE; \
+	done
+
+# I/O processor files:
+## iop    - Generate I/O processor include files
+iop: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES)
+iop_sw_%_defs.h: $(IOPROCDIR)/guinness/iop_sw_%.r
+	$(RDES2C) $<
+iop_version_defs.h: $(IOPROCDIR)/guinness/iop_version.r
+	$(RDES2C) $<
+%_defs.h: $(IOPROCDIR)/%.r
+	$(RDES2C) $<
+%_defs_asm.h: $(IOPROCDIR)/%.r
+	$(RDES2C) -asm $<
+iop_version_defs_asm.h: $(IOPROCDIR)/guinness/iop_version.r
+	$(RDES2C) -asm $<
+
+## doc    - Generate .axw files from register description.
+doc: $(IOPROCREGDESC)
+	for RDES in $^; do \
+		$(RDES2TXT) $$RDES; \
+	done
+
+.PHONY: axw
+## %.axw  - Generate the specified .axw file (doesn't work for all files
+##          due to inconsistent naming of .r files.
+%.axw: axw
+	@for RDES in $(IOPROCREGDESC); do \
+		if echo "$$RDES" | grep $* ; then \
+		  $(RDES2TXT) $$RDES; \
+		fi \
+	done
+
+.PHONY: clean
+## clean  - Remove .h files and .axw files.
+clean:
+	rm -rf $(IOPROCINCL_FILES) *.axw
+
+.PHONY: cleandoc
+## cleandoc  - Remove .axw files.
+cleandoc:
+	rm -rf *.axw
+
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h
new file mode 100644
index 00000000000..a4b58000c16
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_crc_par_defs_asm.h
@@ -0,0 +1,171 @@
+#ifndef __iop_crc_par_defs_asm_h
+#define __iop_crc_par_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_crc_par.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:08:45 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_crc_par_defs_asm.h ../../inst/io_proc/rtl/iop_crc_par.r
+ *      id: $Id: iop_crc_par_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_cfg___mode___lsb 0
+#define reg_iop_crc_par_rw_cfg___mode___width 1
+#define reg_iop_crc_par_rw_cfg___mode___bit 0
+#define reg_iop_crc_par_rw_cfg___crc_out___lsb 1
+#define reg_iop_crc_par_rw_cfg___crc_out___width 1
+#define reg_iop_crc_par_rw_cfg___crc_out___bit 1
+#define reg_iop_crc_par_rw_cfg___rev_out___lsb 2
+#define reg_iop_crc_par_rw_cfg___rev_out___width 1
+#define reg_iop_crc_par_rw_cfg___rev_out___bit 2
+#define reg_iop_crc_par_rw_cfg___inv_out___lsb 3
+#define reg_iop_crc_par_rw_cfg___inv_out___width 1
+#define reg_iop_crc_par_rw_cfg___inv_out___bit 3
+#define reg_iop_crc_par_rw_cfg___trig___lsb 4
+#define reg_iop_crc_par_rw_cfg___trig___width 2
+#define reg_iop_crc_par_rw_cfg___poly___lsb 6
+#define reg_iop_crc_par_rw_cfg___poly___width 3
+#define reg_iop_crc_par_rw_cfg_offset 0
+
+/* Register rw_init_crc, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_init_crc_offset 4
+
+/* Register rw_correct_crc, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_correct_crc_offset 8
+
+/* Register rw_ctrl, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_ctrl___en___lsb 0
+#define reg_iop_crc_par_rw_ctrl___en___width 1
+#define reg_iop_crc_par_rw_ctrl___en___bit 0
+#define reg_iop_crc_par_rw_ctrl_offset 12
+
+/* Register rw_set_last, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_set_last___tr_dif___lsb 0
+#define reg_iop_crc_par_rw_set_last___tr_dif___width 1
+#define reg_iop_crc_par_rw_set_last___tr_dif___bit 0
+#define reg_iop_crc_par_rw_set_last_offset 16
+
+/* Register rw_wr1byte, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_wr1byte___data___lsb 0
+#define reg_iop_crc_par_rw_wr1byte___data___width 8
+#define reg_iop_crc_par_rw_wr1byte_offset 20
+
+/* Register rw_wr2byte, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_wr2byte___data___lsb 0
+#define reg_iop_crc_par_rw_wr2byte___data___width 16
+#define reg_iop_crc_par_rw_wr2byte_offset 24
+
+/* Register rw_wr3byte, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_wr3byte___data___lsb 0
+#define reg_iop_crc_par_rw_wr3byte___data___width 24
+#define reg_iop_crc_par_rw_wr3byte_offset 28
+
+/* Register rw_wr4byte, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_wr4byte___data___lsb 0
+#define reg_iop_crc_par_rw_wr4byte___data___width 32
+#define reg_iop_crc_par_rw_wr4byte_offset 32
+
+/* Register rw_wr1byte_last, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_wr1byte_last___data___lsb 0
+#define reg_iop_crc_par_rw_wr1byte_last___data___width 8
+#define reg_iop_crc_par_rw_wr1byte_last_offset 36
+
+/* Register rw_wr2byte_last, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_wr2byte_last___data___lsb 0
+#define reg_iop_crc_par_rw_wr2byte_last___data___width 16
+#define reg_iop_crc_par_rw_wr2byte_last_offset 40
+
+/* Register rw_wr3byte_last, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_wr3byte_last___data___lsb 0
+#define reg_iop_crc_par_rw_wr3byte_last___data___width 24
+#define reg_iop_crc_par_rw_wr3byte_last_offset 44
+
+/* Register rw_wr4byte_last, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_wr4byte_last___data___lsb 0
+#define reg_iop_crc_par_rw_wr4byte_last___data___width 32
+#define reg_iop_crc_par_rw_wr4byte_last_offset 48
+
+/* Register r_stat, scope iop_crc_par, type r */
+#define reg_iop_crc_par_r_stat___err___lsb 0
+#define reg_iop_crc_par_r_stat___err___width 1
+#define reg_iop_crc_par_r_stat___err___bit 0
+#define reg_iop_crc_par_r_stat___busy___lsb 1
+#define reg_iop_crc_par_r_stat___busy___width 1
+#define reg_iop_crc_par_r_stat___busy___bit 1
+#define reg_iop_crc_par_r_stat_offset 52
+
+/* Register r_sh_reg, scope iop_crc_par, type r */
+#define reg_iop_crc_par_r_sh_reg_offset 56
+
+/* Register r_crc, scope iop_crc_par, type r */
+#define reg_iop_crc_par_r_crc_offset 60
+
+/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */
+#define reg_iop_crc_par_rw_strb_rec_dif_in___last___lsb 0
+#define reg_iop_crc_par_rw_strb_rec_dif_in___last___width 2
+#define reg_iop_crc_par_rw_strb_rec_dif_in_offset 64
+
+
+/* Constants */
+#define regk_iop_crc_par_calc                     0x00000001
+#define regk_iop_crc_par_ccitt                    0x00000002
+#define regk_iop_crc_par_check                    0x00000000
+#define regk_iop_crc_par_crc16                    0x00000001
+#define regk_iop_crc_par_crc32                    0x00000000
+#define regk_iop_crc_par_crc5                     0x00000003
+#define regk_iop_crc_par_crc5_11                  0x00000004
+#define regk_iop_crc_par_dif_in                   0x00000002
+#define regk_iop_crc_par_hi                       0x00000000
+#define regk_iop_crc_par_neg                      0x00000002
+#define regk_iop_crc_par_no                       0x00000000
+#define regk_iop_crc_par_pos                      0x00000001
+#define regk_iop_crc_par_pos_neg                  0x00000003
+#define regk_iop_crc_par_rw_cfg_default           0x00000000
+#define regk_iop_crc_par_rw_ctrl_default          0x00000000
+#define regk_iop_crc_par_yes                      0x00000001
+#endif /* __iop_crc_par_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h
new file mode 100644
index 00000000000..e7d539feccb
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_in_defs_asm.h
@@ -0,0 +1,321 @@
+#ifndef __iop_dmc_in_defs_asm_h
+#define __iop_dmc_in_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_dmc_in.r
+ *     id:           iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:45 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_in_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_in.r
+ *      id: $Id: iop_dmc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_cfg___sth_intr___lsb 0
+#define reg_iop_dmc_in_rw_cfg___sth_intr___width 3
+#define reg_iop_dmc_in_rw_cfg___last_dis_dif___lsb 3
+#define reg_iop_dmc_in_rw_cfg___last_dis_dif___width 1
+#define reg_iop_dmc_in_rw_cfg___last_dis_dif___bit 3
+#define reg_iop_dmc_in_rw_cfg_offset 0
+
+/* Register rw_ctrl, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_ctrl___dif_en___lsb 0
+#define reg_iop_dmc_in_rw_ctrl___dif_en___width 1
+#define reg_iop_dmc_in_rw_ctrl___dif_en___bit 0
+#define reg_iop_dmc_in_rw_ctrl___dif_dis___lsb 1
+#define reg_iop_dmc_in_rw_ctrl___dif_dis___width 1
+#define reg_iop_dmc_in_rw_ctrl___dif_dis___bit 1
+#define reg_iop_dmc_in_rw_ctrl___stream_clr___lsb 2
+#define reg_iop_dmc_in_rw_ctrl___stream_clr___width 1
+#define reg_iop_dmc_in_rw_ctrl___stream_clr___bit 2
+#define reg_iop_dmc_in_rw_ctrl_offset 4
+
+/* Register r_stat, scope iop_dmc_in, type r */
+#define reg_iop_dmc_in_r_stat___dif_en___lsb 0
+#define reg_iop_dmc_in_r_stat___dif_en___width 1
+#define reg_iop_dmc_in_r_stat___dif_en___bit 0
+#define reg_iop_dmc_in_r_stat_offset 8
+
+/* Register rw_stream_cmd, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_stream_cmd___cmd___lsb 0
+#define reg_iop_dmc_in_rw_stream_cmd___cmd___width 10
+#define reg_iop_dmc_in_rw_stream_cmd___n___lsb 16
+#define reg_iop_dmc_in_rw_stream_cmd___n___width 8
+#define reg_iop_dmc_in_rw_stream_cmd_offset 12
+
+/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_stream_wr_data_offset 16
+
+/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_stream_wr_data_last_offset 20
+
+/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_stream_ctrl___eop___lsb 0
+#define reg_iop_dmc_in_rw_stream_ctrl___eop___width 1
+#define reg_iop_dmc_in_rw_stream_ctrl___eop___bit 0
+#define reg_iop_dmc_in_rw_stream_ctrl___wait___lsb 1
+#define reg_iop_dmc_in_rw_stream_ctrl___wait___width 1
+#define reg_iop_dmc_in_rw_stream_ctrl___wait___bit 1
+#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___lsb 2
+#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___width 1
+#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___bit 2
+#define reg_iop_dmc_in_rw_stream_ctrl___size___lsb 3
+#define reg_iop_dmc_in_rw_stream_ctrl___size___width 3
+#define reg_iop_dmc_in_rw_stream_ctrl_offset 24
+
+/* Register r_stream_stat, scope iop_dmc_in, type r */
+#define reg_iop_dmc_in_r_stream_stat___sth___lsb 0
+#define reg_iop_dmc_in_r_stream_stat___sth___width 7
+#define reg_iop_dmc_in_r_stream_stat___full___lsb 16
+#define reg_iop_dmc_in_r_stream_stat___full___width 1
+#define reg_iop_dmc_in_r_stream_stat___full___bit 16
+#define reg_iop_dmc_in_r_stream_stat___last_pkt___lsb 17
+#define reg_iop_dmc_in_r_stream_stat___last_pkt___width 1
+#define reg_iop_dmc_in_r_stream_stat___last_pkt___bit 17
+#define reg_iop_dmc_in_r_stream_stat___data_md_valid___lsb 18
+#define reg_iop_dmc_in_r_stream_stat___data_md_valid___width 1
+#define reg_iop_dmc_in_r_stream_stat___data_md_valid___bit 18
+#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___lsb 19
+#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___width 1
+#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___bit 19
+#define reg_iop_dmc_in_r_stream_stat___group_md_valid___lsb 20
+#define reg_iop_dmc_in_r_stream_stat___group_md_valid___width 1
+#define reg_iop_dmc_in_r_stream_stat___group_md_valid___bit 20
+#define reg_iop_dmc_in_r_stream_stat___stream_busy___lsb 21
+#define reg_iop_dmc_in_r_stream_stat___stream_busy___width 1
+#define reg_iop_dmc_in_r_stream_stat___stream_busy___bit 21
+#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___lsb 22
+#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___width 1
+#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___bit 22
+#define reg_iop_dmc_in_r_stream_stat_offset 28
+
+/* Register r_data_descr, scope iop_dmc_in, type r */
+#define reg_iop_dmc_in_r_data_descr___ctrl___lsb 0
+#define reg_iop_dmc_in_r_data_descr___ctrl___width 8
+#define reg_iop_dmc_in_r_data_descr___stat___lsb 8
+#define reg_iop_dmc_in_r_data_descr___stat___width 8
+#define reg_iop_dmc_in_r_data_descr___md___lsb 16
+#define reg_iop_dmc_in_r_data_descr___md___width 16
+#define reg_iop_dmc_in_r_data_descr_offset 32
+
+/* Register r_ctxt_descr, scope iop_dmc_in, type r */
+#define reg_iop_dmc_in_r_ctxt_descr___ctrl___lsb 0
+#define reg_iop_dmc_in_r_ctxt_descr___ctrl___width 8
+#define reg_iop_dmc_in_r_ctxt_descr___stat___lsb 8
+#define reg_iop_dmc_in_r_ctxt_descr___stat___width 8
+#define reg_iop_dmc_in_r_ctxt_descr___md0___lsb 16
+#define reg_iop_dmc_in_r_ctxt_descr___md0___width 16
+#define reg_iop_dmc_in_r_ctxt_descr_offset 36
+
+/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */
+#define reg_iop_dmc_in_r_ctxt_descr_md1_offset 40
+
+/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */
+#define reg_iop_dmc_in_r_ctxt_descr_md2_offset 44
+
+/* Register r_group_descr, scope iop_dmc_in, type r */
+#define reg_iop_dmc_in_r_group_descr___ctrl___lsb 0
+#define reg_iop_dmc_in_r_group_descr___ctrl___width 8
+#define reg_iop_dmc_in_r_group_descr___stat___lsb 8
+#define reg_iop_dmc_in_r_group_descr___stat___width 8
+#define reg_iop_dmc_in_r_group_descr___md___lsb 16
+#define reg_iop_dmc_in_r_group_descr___md___width 16
+#define reg_iop_dmc_in_r_group_descr_offset 56
+
+/* Register rw_data_descr, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_data_descr___md___lsb 16
+#define reg_iop_dmc_in_rw_data_descr___md___width 16
+#define reg_iop_dmc_in_rw_data_descr_offset 60
+
+/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_ctxt_descr___md0___lsb 16
+#define reg_iop_dmc_in_rw_ctxt_descr___md0___width 16
+#define reg_iop_dmc_in_rw_ctxt_descr_offset 64
+
+/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_ctxt_descr_md1_offset 68
+
+/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_ctxt_descr_md2_offset 72
+
+/* Register rw_group_descr, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_group_descr___md___lsb 16
+#define reg_iop_dmc_in_rw_group_descr___md___width 16
+#define reg_iop_dmc_in_rw_group_descr_offset 84
+
+/* Register rw_intr_mask, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_intr_mask___data_md___lsb 0
+#define reg_iop_dmc_in_rw_intr_mask___data_md___width 1
+#define reg_iop_dmc_in_rw_intr_mask___data_md___bit 0
+#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___lsb 1
+#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___width 1
+#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___bit 1
+#define reg_iop_dmc_in_rw_intr_mask___group_md___lsb 2
+#define reg_iop_dmc_in_rw_intr_mask___group_md___width 1
+#define reg_iop_dmc_in_rw_intr_mask___group_md___bit 2
+#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___lsb 3
+#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___width 1
+#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___bit 3
+#define reg_iop_dmc_in_rw_intr_mask___sth___lsb 4
+#define reg_iop_dmc_in_rw_intr_mask___sth___width 1
+#define reg_iop_dmc_in_rw_intr_mask___sth___bit 4
+#define reg_iop_dmc_in_rw_intr_mask___full___lsb 5
+#define reg_iop_dmc_in_rw_intr_mask___full___width 1
+#define reg_iop_dmc_in_rw_intr_mask___full___bit 5
+#define reg_iop_dmc_in_rw_intr_mask_offset 88
+
+/* Register rw_ack_intr, scope iop_dmc_in, type rw */
+#define reg_iop_dmc_in_rw_ack_intr___data_md___lsb 0
+#define reg_iop_dmc_in_rw_ack_intr___data_md___width 1
+#define reg_iop_dmc_in_rw_ack_intr___data_md___bit 0
+#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___lsb 1
+#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___width 1
+#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___bit 1
+#define reg_iop_dmc_in_rw_ack_intr___group_md___lsb 2
+#define reg_iop_dmc_in_rw_ack_intr___group_md___width 1
+#define reg_iop_dmc_in_rw_ack_intr___group_md___bit 2
+#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___lsb 3
+#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___width 1
+#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___bit 3
+#define reg_iop_dmc_in_rw_ack_intr___sth___lsb 4
+#define reg_iop_dmc_in_rw_ack_intr___sth___width 1
+#define reg_iop_dmc_in_rw_ack_intr___sth___bit 4
+#define reg_iop_dmc_in_rw_ack_intr___full___lsb 5
+#define reg_iop_dmc_in_rw_ack_intr___full___width 1
+#define reg_iop_dmc_in_rw_ack_intr___full___bit 5
+#define reg_iop_dmc_in_rw_ack_intr_offset 92
+
+/* Register r_intr, scope iop_dmc_in, type r */
+#define reg_iop_dmc_in_r_intr___data_md___lsb 0
+#define reg_iop_dmc_in_r_intr___data_md___width 1
+#define reg_iop_dmc_in_r_intr___data_md___bit 0
+#define reg_iop_dmc_in_r_intr___ctxt_md___lsb 1
+#define reg_iop_dmc_in_r_intr___ctxt_md___width 1
+#define reg_iop_dmc_in_r_intr___ctxt_md___bit 1
+#define reg_iop_dmc_in_r_intr___group_md___lsb 2
+#define reg_iop_dmc_in_r_intr___group_md___width 1
+#define reg_iop_dmc_in_r_intr___group_md___bit 2
+#define reg_iop_dmc_in_r_intr___cmd_rdy___lsb 3
+#define reg_iop_dmc_in_r_intr___cmd_rdy___width 1
+#define reg_iop_dmc_in_r_intr___cmd_rdy___bit 3
+#define reg_iop_dmc_in_r_intr___sth___lsb 4
+#define reg_iop_dmc_in_r_intr___sth___width 1
+#define reg_iop_dmc_in_r_intr___sth___bit 4
+#define reg_iop_dmc_in_r_intr___full___lsb 5
+#define reg_iop_dmc_in_r_intr___full___width 1
+#define reg_iop_dmc_in_r_intr___full___bit 5
+#define reg_iop_dmc_in_r_intr_offset 96
+
+/* Register r_masked_intr, scope iop_dmc_in, type r */
+#define reg_iop_dmc_in_r_masked_intr___data_md___lsb 0
+#define reg_iop_dmc_in_r_masked_intr___data_md___width 1
+#define reg_iop_dmc_in_r_masked_intr___data_md___bit 0
+#define reg_iop_dmc_in_r_masked_intr___ctxt_md___lsb 1
+#define reg_iop_dmc_in_r_masked_intr___ctxt_md___width 1
+#define reg_iop_dmc_in_r_masked_intr___ctxt_md___bit 1
+#define reg_iop_dmc_in_r_masked_intr___group_md___lsb 2
+#define reg_iop_dmc_in_r_masked_intr___group_md___width 1
+#define reg_iop_dmc_in_r_masked_intr___group_md___bit 2
+#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___lsb 3
+#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___width 1
+#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___bit 3
+#define reg_iop_dmc_in_r_masked_intr___sth___lsb 4
+#define reg_iop_dmc_in_r_masked_intr___sth___width 1
+#define reg_iop_dmc_in_r_masked_intr___sth___bit 4
+#define reg_iop_dmc_in_r_masked_intr___full___lsb 5
+#define reg_iop_dmc_in_r_masked_intr___full___width 1
+#define reg_iop_dmc_in_r_masked_intr___full___bit 5
+#define reg_iop_dmc_in_r_masked_intr_offset 100
+
+
+/* Constants */
+#define regk_iop_dmc_in_ack_pkt                   0x00000100
+#define regk_iop_dmc_in_array                     0x00000008
+#define regk_iop_dmc_in_burst                     0x00000020
+#define regk_iop_dmc_in_copy_next                 0x00000010
+#define regk_iop_dmc_in_copy_up                   0x00000020
+#define regk_iop_dmc_in_dis_c                     0x00000010
+#define regk_iop_dmc_in_dis_g                     0x00000020
+#define regk_iop_dmc_in_lim1                      0x00000000
+#define regk_iop_dmc_in_lim16                     0x00000004
+#define regk_iop_dmc_in_lim2                      0x00000001
+#define regk_iop_dmc_in_lim32                     0x00000005
+#define regk_iop_dmc_in_lim4                      0x00000002
+#define regk_iop_dmc_in_lim64                     0x00000006
+#define regk_iop_dmc_in_lim8                      0x00000003
+#define regk_iop_dmc_in_load_c                    0x00000200
+#define regk_iop_dmc_in_load_c_n                  0x00000280
+#define regk_iop_dmc_in_load_c_next               0x00000240
+#define regk_iop_dmc_in_load_d                    0x00000140
+#define regk_iop_dmc_in_load_g                    0x00000300
+#define regk_iop_dmc_in_load_g_down               0x000003c0
+#define regk_iop_dmc_in_load_g_next               0x00000340
+#define regk_iop_dmc_in_load_g_up                 0x00000380
+#define regk_iop_dmc_in_next_en                   0x00000010
+#define regk_iop_dmc_in_next_pkt                  0x00000010
+#define regk_iop_dmc_in_no                        0x00000000
+#define regk_iop_dmc_in_restore                   0x00000020
+#define regk_iop_dmc_in_rw_cfg_default            0x00000000
+#define regk_iop_dmc_in_rw_ctxt_descr_default     0x00000000
+#define regk_iop_dmc_in_rw_ctxt_descr_md1_default  0x00000000
+#define regk_iop_dmc_in_rw_ctxt_descr_md2_default  0x00000000
+#define regk_iop_dmc_in_rw_data_descr_default     0x00000000
+#define regk_iop_dmc_in_rw_group_descr_default    0x00000000
+#define regk_iop_dmc_in_rw_intr_mask_default      0x00000000
+#define regk_iop_dmc_in_rw_stream_ctrl_default    0x00000000
+#define regk_iop_dmc_in_save_down                 0x00000020
+#define regk_iop_dmc_in_save_up                   0x00000020
+#define regk_iop_dmc_in_set_reg                   0x00000050
+#define regk_iop_dmc_in_set_w_size1               0x00000190
+#define regk_iop_dmc_in_set_w_size2               0x000001a0
+#define regk_iop_dmc_in_set_w_size4               0x000001c0
+#define regk_iop_dmc_in_store_c                   0x00000002
+#define regk_iop_dmc_in_store_descr               0x00000000
+#define regk_iop_dmc_in_store_g                   0x00000004
+#define regk_iop_dmc_in_store_md                  0x00000001
+#define regk_iop_dmc_in_update_down               0x00000020
+#define regk_iop_dmc_in_yes                       0x00000001
+#endif /* __iop_dmc_in_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h
new file mode 100644
index 00000000000..9fe1a805437
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_dmc_out_defs_asm.h
@@ -0,0 +1,349 @@
+#ifndef __iop_dmc_out_defs_asm_h
+#define __iop_dmc_out_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_dmc_out.r
+ *     id:           iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:45 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_out_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_out.r
+ *      id: $Id: iop_dmc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope iop_dmc_out, type rw */
+#define reg_iop_dmc_out_rw_cfg___trf_lim___lsb 0
+#define reg_iop_dmc_out_rw_cfg___trf_lim___width 16
+#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___lsb 16
+#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___width 1
+#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___bit 16
+#define reg_iop_dmc_out_rw_cfg___dth_intr___lsb 17
+#define reg_iop_dmc_out_rw_cfg___dth_intr___width 3
+#define reg_iop_dmc_out_rw_cfg_offset 0
+
+/* Register rw_ctrl, scope iop_dmc_out, type rw */
+#define reg_iop_dmc_out_rw_ctrl___dif_en___lsb 0
+#define reg_iop_dmc_out_rw_ctrl___dif_en___width 1
+#define reg_iop_dmc_out_rw_ctrl___dif_en___bit 0
+#define reg_iop_dmc_out_rw_ctrl___dif_dis___lsb 1
+#define reg_iop_dmc_out_rw_ctrl___dif_dis___width 1
+#define reg_iop_dmc_out_rw_ctrl___dif_dis___bit 1
+#define reg_iop_dmc_out_rw_ctrl_offset 4
+
+/* Register r_stat, scope iop_dmc_out, type r */
+#define reg_iop_dmc_out_r_stat___dif_en___lsb 0
+#define reg_iop_dmc_out_r_stat___dif_en___width 1
+#define reg_iop_dmc_out_r_stat___dif_en___bit 0
+#define reg_iop_dmc_out_r_stat_offset 8
+
+/* Register rw_stream_cmd, scope iop_dmc_out, type rw */
+#define reg_iop_dmc_out_rw_stream_cmd___cmd___lsb 0
+#define reg_iop_dmc_out_rw_stream_cmd___cmd___width 10
+#define reg_iop_dmc_out_rw_stream_cmd___n___lsb 16
+#define reg_iop_dmc_out_rw_stream_cmd___n___width 8
+#define reg_iop_dmc_out_rw_stream_cmd_offset 12
+
+/* Register rs_stream_data, scope iop_dmc_out, type rs */
+#define reg_iop_dmc_out_rs_stream_data_offset 16
+
+/* Register r_stream_data, scope iop_dmc_out, type r */
+#define reg_iop_dmc_out_r_stream_data_offset 20
+
+/* Register r_stream_stat, scope iop_dmc_out, type r */
+#define reg_iop_dmc_out_r_stream_stat___dth___lsb 0
+#define reg_iop_dmc_out_r_stream_stat___dth___width 7
+#define reg_iop_dmc_out_r_stream_stat___dv___lsb 16
+#define reg_iop_dmc_out_r_stream_stat___dv___width 1
+#define reg_iop_dmc_out_r_stream_stat___dv___bit 16
+#define reg_iop_dmc_out_r_stream_stat___all_avail___lsb 17
+#define reg_iop_dmc_out_r_stream_stat___all_avail___width 1
+#define reg_iop_dmc_out_r_stream_stat___all_avail___bit 17
+#define reg_iop_dmc_out_r_stream_stat___last___lsb 18
+#define reg_iop_dmc_out_r_stream_stat___last___width 1
+#define reg_iop_dmc_out_r_stream_stat___last___bit 18
+#define reg_iop_dmc_out_r_stream_stat___size___lsb 19
+#define reg_iop_dmc_out_r_stream_stat___size___width 3
+#define reg_iop_dmc_out_r_stream_stat___data_md_valid___lsb 22
+#define reg_iop_dmc_out_r_stream_stat___data_md_valid___width 1
+#define reg_iop_dmc_out_r_stream_stat___data_md_valid___bit 22
+#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___lsb 23
+#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___width 1
+#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___bit 23
+#define reg_iop_dmc_out_r_stream_stat___group_md_valid___lsb 24
+#define reg_iop_dmc_out_r_stream_stat___group_md_valid___width 1
+#define reg_iop_dmc_out_r_stream_stat___group_md_valid___bit 24
+#define reg_iop_dmc_out_r_stream_stat___stream_busy___lsb 25
+#define reg_iop_dmc_out_r_stream_stat___stream_busy___width 1
+#define reg_iop_dmc_out_r_stream_stat___stream_busy___bit 25
+#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___lsb 26
+#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___width 1
+#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___bit 26
+#define reg_iop_dmc_out_r_stream_stat___cmd_rq___lsb 27
+#define reg_iop_dmc_out_r_stream_stat___cmd_rq___width 1
+#define reg_iop_dmc_out_r_stream_stat___cmd_rq___bit 27
+#define reg_iop_dmc_out_r_stream_stat_offset 24
+
+/* Register r_data_descr, scope iop_dmc_out, type r */
+#define reg_iop_dmc_out_r_data_descr___ctrl___lsb 0
+#define reg_iop_dmc_out_r_data_descr___ctrl___width 8
+#define reg_iop_dmc_out_r_data_descr___stat___lsb 8
+#define reg_iop_dmc_out_r_data_descr___stat___width 8
+#define reg_iop_dmc_out_r_data_descr___md___lsb 16
+#define reg_iop_dmc_out_r_data_descr___md___width 16
+#define reg_iop_dmc_out_r_data_descr_offset 28
+
+/* Register r_ctxt_descr, scope iop_dmc_out, type r */
+#define reg_iop_dmc_out_r_ctxt_descr___ctrl___lsb 0
+#define reg_iop_dmc_out_r_ctxt_descr___ctrl___width 8
+#define reg_iop_dmc_out_r_ctxt_descr___stat___lsb 8
+#define reg_iop_dmc_out_r_ctxt_descr___stat___width 8
+#define reg_iop_dmc_out_r_ctxt_descr___md0___lsb 16
+#define reg_iop_dmc_out_r_ctxt_descr___md0___width 16
+#define reg_iop_dmc_out_r_ctxt_descr_offset 32
+
+/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */
+#define reg_iop_dmc_out_r_ctxt_descr_md1_offset 36
+
+/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */
+#define reg_iop_dmc_out_r_ctxt_descr_md2_offset 40
+
+/* Register r_group_descr, scope iop_dmc_out, type r */
+#define reg_iop_dmc_out_r_group_descr___ctrl___lsb 0
+#define reg_iop_dmc_out_r_group_descr___ctrl___width 8
+#define reg_iop_dmc_out_r_group_descr___stat___lsb 8
+#define reg_iop_dmc_out_r_group_descr___stat___width 8
+#define reg_iop_dmc_out_r_group_descr___md___lsb 16
+#define reg_iop_dmc_out_r_group_descr___md___width 16
+#define reg_iop_dmc_out_r_group_descr_offset 52
+
+/* Register rw_data_descr, scope iop_dmc_out, type rw */
+#define reg_iop_dmc_out_rw_data_descr___md___lsb 16
+#define reg_iop_dmc_out_rw_data_descr___md___width 16
+#define reg_iop_dmc_out_rw_data_descr_offset 56
+
+/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */
+#define reg_iop_dmc_out_rw_ctxt_descr___md0___lsb 16
+#define reg_iop_dmc_out_rw_ctxt_descr___md0___width 16
+#define reg_iop_dmc_out_rw_ctxt_descr_offset 60
+
+/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */
+#define reg_iop_dmc_out_rw_ctxt_descr_md1_offset 64
+
+/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */
+#define reg_iop_dmc_out_rw_ctxt_descr_md2_offset 68
+
+/* Register rw_group_descr, scope iop_dmc_out, type rw */
+#define reg_iop_dmc_out_rw_group_descr___md___lsb 16
+#define reg_iop_dmc_out_rw_group_descr___md___width 16
+#define reg_iop_dmc_out_rw_group_descr_offset 80
+
+/* Register rw_intr_mask, scope iop_dmc_out, type rw */
+#define reg_iop_dmc_out_rw_intr_mask___data_md___lsb 0
+#define reg_iop_dmc_out_rw_intr_mask___data_md___width 1
+#define reg_iop_dmc_out_rw_intr_mask___data_md___bit 0
+#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___lsb 1
+#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___width 1
+#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___bit 1
+#define reg_iop_dmc_out_rw_intr_mask___group_md___lsb 2
+#define reg_iop_dmc_out_rw_intr_mask___group_md___width 1
+#define reg_iop_dmc_out_rw_intr_mask___group_md___bit 2
+#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___lsb 3
+#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___width 1
+#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___bit 3
+#define reg_iop_dmc_out_rw_intr_mask___dth___lsb 4
+#define reg_iop_dmc_out_rw_intr_mask___dth___width 1
+#define reg_iop_dmc_out_rw_intr_mask___dth___bit 4
+#define reg_iop_dmc_out_rw_intr_mask___dv___lsb 5
+#define reg_iop_dmc_out_rw_intr_mask___dv___width 1
+#define reg_iop_dmc_out_rw_intr_mask___dv___bit 5
+#define reg_iop_dmc_out_rw_intr_mask___last_data___lsb 6
+#define reg_iop_dmc_out_rw_intr_mask___last_data___width 1
+#define reg_iop_dmc_out_rw_intr_mask___last_data___bit 6
+#define reg_iop_dmc_out_rw_intr_mask___trf_lim___lsb 7
+#define reg_iop_dmc_out_rw_intr_mask___trf_lim___width 1
+#define reg_iop_dmc_out_rw_intr_mask___trf_lim___bit 7
+#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___lsb 8
+#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___width 1
+#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___bit 8
+#define reg_iop_dmc_out_rw_intr_mask_offset 84
+
+/* Register rw_ack_intr, scope iop_dmc_out, type rw */
+#define reg_iop_dmc_out_rw_ack_intr___data_md___lsb 0
+#define reg_iop_dmc_out_rw_ack_intr___data_md___width 1
+#define reg_iop_dmc_out_rw_ack_intr___data_md___bit 0
+#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___lsb 1
+#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___width 1
+#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___bit 1
+#define reg_iop_dmc_out_rw_ack_intr___group_md___lsb 2
+#define reg_iop_dmc_out_rw_ack_intr___group_md___width 1
+#define reg_iop_dmc_out_rw_ack_intr___group_md___bit 2
+#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___lsb 3
+#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___width 1
+#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___bit 3
+#define reg_iop_dmc_out_rw_ack_intr___dth___lsb 4
+#define reg_iop_dmc_out_rw_ack_intr___dth___width 1
+#define reg_iop_dmc_out_rw_ack_intr___dth___bit 4
+#define reg_iop_dmc_out_rw_ack_intr___dv___lsb 5
+#define reg_iop_dmc_out_rw_ack_intr___dv___width 1
+#define reg_iop_dmc_out_rw_ack_intr___dv___bit 5
+#define reg_iop_dmc_out_rw_ack_intr___last_data___lsb 6
+#define reg_iop_dmc_out_rw_ack_intr___last_data___width 1
+#define reg_iop_dmc_out_rw_ack_intr___last_data___bit 6
+#define reg_iop_dmc_out_rw_ack_intr___trf_lim___lsb 7
+#define reg_iop_dmc_out_rw_ack_intr___trf_lim___width 1
+#define reg_iop_dmc_out_rw_ack_intr___trf_lim___bit 7
+#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___lsb 8
+#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___width 1
+#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___bit 8
+#define reg_iop_dmc_out_rw_ack_intr_offset 88
+
+/* Register r_intr, scope iop_dmc_out, type r */
+#define reg_iop_dmc_out_r_intr___data_md___lsb 0
+#define reg_iop_dmc_out_r_intr___data_md___width 1
+#define reg_iop_dmc_out_r_intr___data_md___bit 0
+#define reg_iop_dmc_out_r_intr___ctxt_md___lsb 1
+#define reg_iop_dmc_out_r_intr___ctxt_md___width 1
+#define reg_iop_dmc_out_r_intr___ctxt_md___bit 1
+#define reg_iop_dmc_out_r_intr___group_md___lsb 2
+#define reg_iop_dmc_out_r_intr___group_md___width 1
+#define reg_iop_dmc_out_r_intr___group_md___bit 2
+#define reg_iop_dmc_out_r_intr___cmd_rdy___lsb 3
+#define reg_iop_dmc_out_r_intr___cmd_rdy___width 1
+#define reg_iop_dmc_out_r_intr___cmd_rdy___bit 3
+#define reg_iop_dmc_out_r_intr___dth___lsb 4
+#define reg_iop_dmc_out_r_intr___dth___width 1
+#define reg_iop_dmc_out_r_intr___dth___bit 4
+#define reg_iop_dmc_out_r_intr___dv___lsb 5
+#define reg_iop_dmc_out_r_intr___dv___width 1
+#define reg_iop_dmc_out_r_intr___dv___bit 5
+#define reg_iop_dmc_out_r_intr___last_data___lsb 6
+#define reg_iop_dmc_out_r_intr___last_data___width 1
+#define reg_iop_dmc_out_r_intr___last_data___bit 6
+#define reg_iop_dmc_out_r_intr___trf_lim___lsb 7
+#define reg_iop_dmc_out_r_intr___trf_lim___width 1
+#define reg_iop_dmc_out_r_intr___trf_lim___bit 7
+#define reg_iop_dmc_out_r_intr___cmd_rq___lsb 8
+#define reg_iop_dmc_out_r_intr___cmd_rq___width 1
+#define reg_iop_dmc_out_r_intr___cmd_rq___bit 8
+#define reg_iop_dmc_out_r_intr_offset 92
+
+/* Register r_masked_intr, scope iop_dmc_out, type r */
+#define reg_iop_dmc_out_r_masked_intr___data_md___lsb 0
+#define reg_iop_dmc_out_r_masked_intr___data_md___width 1
+#define reg_iop_dmc_out_r_masked_intr___data_md___bit 0
+#define reg_iop_dmc_out_r_masked_intr___ctxt_md___lsb 1
+#define reg_iop_dmc_out_r_masked_intr___ctxt_md___width 1
+#define reg_iop_dmc_out_r_masked_intr___ctxt_md___bit 1
+#define reg_iop_dmc_out_r_masked_intr___group_md___lsb 2
+#define reg_iop_dmc_out_r_masked_intr___group_md___width 1
+#define reg_iop_dmc_out_r_masked_intr___group_md___bit 2
+#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___lsb 3
+#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___width 1
+#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___bit 3
+#define reg_iop_dmc_out_r_masked_intr___dth___lsb 4
+#define reg_iop_dmc_out_r_masked_intr___dth___width 1
+#define reg_iop_dmc_out_r_masked_intr___dth___bit 4
+#define reg_iop_dmc_out_r_masked_intr___dv___lsb 5
+#define reg_iop_dmc_out_r_masked_intr___dv___width 1
+#define reg_iop_dmc_out_r_masked_intr___dv___bit 5
+#define reg_iop_dmc_out_r_masked_intr___last_data___lsb 6
+#define reg_iop_dmc_out_r_masked_intr___last_data___width 1
+#define reg_iop_dmc_out_r_masked_intr___last_data___bit 6
+#define reg_iop_dmc_out_r_masked_intr___trf_lim___lsb 7
+#define reg_iop_dmc_out_r_masked_intr___trf_lim___width 1
+#define reg_iop_dmc_out_r_masked_intr___trf_lim___bit 7
+#define reg_iop_dmc_out_r_masked_intr___cmd_rq___lsb 8
+#define reg_iop_dmc_out_r_masked_intr___cmd_rq___width 1
+#define reg_iop_dmc_out_r_masked_intr___cmd_rq___bit 8
+#define reg_iop_dmc_out_r_masked_intr_offset 96
+
+
+/* Constants */
+#define regk_iop_dmc_out_ack_pkt                  0x00000100
+#define regk_iop_dmc_out_array                    0x00000008
+#define regk_iop_dmc_out_burst                    0x00000020
+#define regk_iop_dmc_out_copy_next                0x00000010
+#define regk_iop_dmc_out_copy_up                  0x00000020
+#define regk_iop_dmc_out_dis_c                    0x00000010
+#define regk_iop_dmc_out_dis_g                    0x00000020
+#define regk_iop_dmc_out_lim1                     0x00000000
+#define regk_iop_dmc_out_lim16                    0x00000004
+#define regk_iop_dmc_out_lim2                     0x00000001
+#define regk_iop_dmc_out_lim32                    0x00000005
+#define regk_iop_dmc_out_lim4                     0x00000002
+#define regk_iop_dmc_out_lim64                    0x00000006
+#define regk_iop_dmc_out_lim8                     0x00000003
+#define regk_iop_dmc_out_load_c                   0x00000200
+#define regk_iop_dmc_out_load_c_n                 0x00000280
+#define regk_iop_dmc_out_load_c_next              0x00000240
+#define regk_iop_dmc_out_load_d                   0x00000140
+#define regk_iop_dmc_out_load_g                   0x00000300
+#define regk_iop_dmc_out_load_g_down              0x000003c0
+#define regk_iop_dmc_out_load_g_next              0x00000340
+#define regk_iop_dmc_out_load_g_up                0x00000380
+#define regk_iop_dmc_out_next_en                  0x00000010
+#define regk_iop_dmc_out_next_pkt                 0x00000010
+#define regk_iop_dmc_out_no                       0x00000000
+#define regk_iop_dmc_out_restore                  0x00000020
+#define regk_iop_dmc_out_rw_cfg_default           0x00000000
+#define regk_iop_dmc_out_rw_ctxt_descr_default    0x00000000
+#define regk_iop_dmc_out_rw_ctxt_descr_md1_default  0x00000000
+#define regk_iop_dmc_out_rw_ctxt_descr_md2_default  0x00000000
+#define regk_iop_dmc_out_rw_data_descr_default    0x00000000
+#define regk_iop_dmc_out_rw_group_descr_default   0x00000000
+#define regk_iop_dmc_out_rw_intr_mask_default     0x00000000
+#define regk_iop_dmc_out_save_down                0x00000020
+#define regk_iop_dmc_out_save_up                  0x00000020
+#define regk_iop_dmc_out_set_reg                  0x00000050
+#define regk_iop_dmc_out_set_w_size1              0x00000190
+#define regk_iop_dmc_out_set_w_size2              0x000001a0
+#define regk_iop_dmc_out_set_w_size4              0x000001c0
+#define regk_iop_dmc_out_store_c                  0x00000002
+#define regk_iop_dmc_out_store_descr              0x00000000
+#define regk_iop_dmc_out_store_g                  0x00000004
+#define regk_iop_dmc_out_store_md                 0x00000001
+#define regk_iop_dmc_out_update_down              0x00000020
+#define regk_iop_dmc_out_yes                      0x00000001
+#endif /* __iop_dmc_out_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h
new file mode 100644
index 00000000000..974dee082f9
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_defs_asm.h
@@ -0,0 +1,234 @@
+#ifndef __iop_fifo_in_defs_asm_h
+#define __iop_fifo_in_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_fifo_in.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:07 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in.r
+ *      id: $Id: iop_fifo_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope iop_fifo_in, type rw */
+#define reg_iop_fifo_in_rw_cfg___avail_lim___lsb 0
+#define reg_iop_fifo_in_rw_cfg___avail_lim___width 3
+#define reg_iop_fifo_in_rw_cfg___byte_order___lsb 3
+#define reg_iop_fifo_in_rw_cfg___byte_order___width 2
+#define reg_iop_fifo_in_rw_cfg___trig___lsb 5
+#define reg_iop_fifo_in_rw_cfg___trig___width 2
+#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___lsb 7
+#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___width 1
+#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___bit 7
+#define reg_iop_fifo_in_rw_cfg___mode___lsb 8
+#define reg_iop_fifo_in_rw_cfg___mode___width 2
+#define reg_iop_fifo_in_rw_cfg_offset 0
+
+/* Register rw_ctrl, scope iop_fifo_in, type rw */
+#define reg_iop_fifo_in_rw_ctrl___dif_in_en___lsb 0
+#define reg_iop_fifo_in_rw_ctrl___dif_in_en___width 1
+#define reg_iop_fifo_in_rw_ctrl___dif_in_en___bit 0
+#define reg_iop_fifo_in_rw_ctrl___dif_out_en___lsb 1
+#define reg_iop_fifo_in_rw_ctrl___dif_out_en___width 1
+#define reg_iop_fifo_in_rw_ctrl___dif_out_en___bit 1
+#define reg_iop_fifo_in_rw_ctrl_offset 4
+
+/* Register r_stat, scope iop_fifo_in, type r */
+#define reg_iop_fifo_in_r_stat___avail_bytes___lsb 0
+#define reg_iop_fifo_in_r_stat___avail_bytes___width 4
+#define reg_iop_fifo_in_r_stat___last___lsb 4
+#define reg_iop_fifo_in_r_stat___last___width 8
+#define reg_iop_fifo_in_r_stat___dif_in_en___lsb 12
+#define reg_iop_fifo_in_r_stat___dif_in_en___width 1
+#define reg_iop_fifo_in_r_stat___dif_in_en___bit 12
+#define reg_iop_fifo_in_r_stat___dif_out_en___lsb 13
+#define reg_iop_fifo_in_r_stat___dif_out_en___width 1
+#define reg_iop_fifo_in_r_stat___dif_out_en___bit 13
+#define reg_iop_fifo_in_r_stat_offset 8
+
+/* Register rs_rd1byte, scope iop_fifo_in, type rs */
+#define reg_iop_fifo_in_rs_rd1byte___data___lsb 0
+#define reg_iop_fifo_in_rs_rd1byte___data___width 8
+#define reg_iop_fifo_in_rs_rd1byte_offset 12
+
+/* Register r_rd1byte, scope iop_fifo_in, type r */
+#define reg_iop_fifo_in_r_rd1byte___data___lsb 0
+#define reg_iop_fifo_in_r_rd1byte___data___width 8
+#define reg_iop_fifo_in_r_rd1byte_offset 16
+
+/* Register rs_rd2byte, scope iop_fifo_in, type rs */
+#define reg_iop_fifo_in_rs_rd2byte___data___lsb 0
+#define reg_iop_fifo_in_rs_rd2byte___data___width 16
+#define reg_iop_fifo_in_rs_rd2byte_offset 20
+
+/* Register r_rd2byte, scope iop_fifo_in, type r */
+#define reg_iop_fifo_in_r_rd2byte___data___lsb 0
+#define reg_iop_fifo_in_r_rd2byte___data___width 16
+#define reg_iop_fifo_in_r_rd2byte_offset 24
+
+/* Register rs_rd3byte, scope iop_fifo_in, type rs */
+#define reg_iop_fifo_in_rs_rd3byte___data___lsb 0
+#define reg_iop_fifo_in_rs_rd3byte___data___width 24
+#define reg_iop_fifo_in_rs_rd3byte_offset 28
+
+/* Register r_rd3byte, scope iop_fifo_in, type r */
+#define reg_iop_fifo_in_r_rd3byte___data___lsb 0
+#define reg_iop_fifo_in_r_rd3byte___data___width 24
+#define reg_iop_fifo_in_r_rd3byte_offset 32
+
+/* Register rs_rd4byte, scope iop_fifo_in, type rs */
+#define reg_iop_fifo_in_rs_rd4byte___data___lsb 0
+#define reg_iop_fifo_in_rs_rd4byte___data___width 32
+#define reg_iop_fifo_in_rs_rd4byte_offset 36
+
+/* Register r_rd4byte, scope iop_fifo_in, type r */
+#define reg_iop_fifo_in_r_rd4byte___data___lsb 0
+#define reg_iop_fifo_in_r_rd4byte___data___width 32
+#define reg_iop_fifo_in_r_rd4byte_offset 40
+
+/* Register rw_set_last, scope iop_fifo_in, type rw */
+#define reg_iop_fifo_in_rw_set_last_offset 44
+
+/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */
+#define reg_iop_fifo_in_rw_strb_dif_in___last___lsb 0
+#define reg_iop_fifo_in_rw_strb_dif_in___last___width 2
+#define reg_iop_fifo_in_rw_strb_dif_in_offset 48
+
+/* Register rw_intr_mask, scope iop_fifo_in, type rw */
+#define reg_iop_fifo_in_rw_intr_mask___urun___lsb 0
+#define reg_iop_fifo_in_rw_intr_mask___urun___width 1
+#define reg_iop_fifo_in_rw_intr_mask___urun___bit 0
+#define reg_iop_fifo_in_rw_intr_mask___last_data___lsb 1
+#define reg_iop_fifo_in_rw_intr_mask___last_data___width 1
+#define reg_iop_fifo_in_rw_intr_mask___last_data___bit 1
+#define reg_iop_fifo_in_rw_intr_mask___dav___lsb 2
+#define reg_iop_fifo_in_rw_intr_mask___dav___width 1
+#define reg_iop_fifo_in_rw_intr_mask___dav___bit 2
+#define reg_iop_fifo_in_rw_intr_mask___avail___lsb 3
+#define reg_iop_fifo_in_rw_intr_mask___avail___width 1
+#define reg_iop_fifo_in_rw_intr_mask___avail___bit 3
+#define reg_iop_fifo_in_rw_intr_mask___orun___lsb 4
+#define reg_iop_fifo_in_rw_intr_mask___orun___width 1
+#define reg_iop_fifo_in_rw_intr_mask___orun___bit 4
+#define reg_iop_fifo_in_rw_intr_mask_offset 52
+
+/* Register rw_ack_intr, scope iop_fifo_in, type rw */
+#define reg_iop_fifo_in_rw_ack_intr___urun___lsb 0
+#define reg_iop_fifo_in_rw_ack_intr___urun___width 1
+#define reg_iop_fifo_in_rw_ack_intr___urun___bit 0
+#define reg_iop_fifo_in_rw_ack_intr___last_data___lsb 1
+#define reg_iop_fifo_in_rw_ack_intr___last_data___width 1
+#define reg_iop_fifo_in_rw_ack_intr___last_data___bit 1
+#define reg_iop_fifo_in_rw_ack_intr___dav___lsb 2
+#define reg_iop_fifo_in_rw_ack_intr___dav___width 1
+#define reg_iop_fifo_in_rw_ack_intr___dav___bit 2
+#define reg_iop_fifo_in_rw_ack_intr___avail___lsb 3
+#define reg_iop_fifo_in_rw_ack_intr___avail___width 1
+#define reg_iop_fifo_in_rw_ack_intr___avail___bit 3
+#define reg_iop_fifo_in_rw_ack_intr___orun___lsb 4
+#define reg_iop_fifo_in_rw_ack_intr___orun___width 1
+#define reg_iop_fifo_in_rw_ack_intr___orun___bit 4
+#define reg_iop_fifo_in_rw_ack_intr_offset 56
+
+/* Register r_intr, scope iop_fifo_in, type r */
+#define reg_iop_fifo_in_r_intr___urun___lsb 0
+#define reg_iop_fifo_in_r_intr___urun___width 1
+#define reg_iop_fifo_in_r_intr___urun___bit 0
+#define reg_iop_fifo_in_r_intr___last_data___lsb 1
+#define reg_iop_fifo_in_r_intr___last_data___width 1
+#define reg_iop_fifo_in_r_intr___last_data___bit 1
+#define reg_iop_fifo_in_r_intr___dav___lsb 2
+#define reg_iop_fifo_in_r_intr___dav___width 1
+#define reg_iop_fifo_in_r_intr___dav___bit 2
+#define reg_iop_fifo_in_r_intr___avail___lsb 3
+#define reg_iop_fifo_in_r_intr___avail___width 1
+#define reg_iop_fifo_in_r_intr___avail___bit 3
+#define reg_iop_fifo_in_r_intr___orun___lsb 4
+#define reg_iop_fifo_in_r_intr___orun___width 1
+#define reg_iop_fifo_in_r_intr___orun___bit 4
+#define reg_iop_fifo_in_r_intr_offset 60
+
+/* Register r_masked_intr, scope iop_fifo_in, type r */
+#define reg_iop_fifo_in_r_masked_intr___urun___lsb 0
+#define reg_iop_fifo_in_r_masked_intr___urun___width 1
+#define reg_iop_fifo_in_r_masked_intr___urun___bit 0
+#define reg_iop_fifo_in_r_masked_intr___last_data___lsb 1
+#define reg_iop_fifo_in_r_masked_intr___last_data___width 1
+#define reg_iop_fifo_in_r_masked_intr___last_data___bit 1
+#define reg_iop_fifo_in_r_masked_intr___dav___lsb 2
+#define reg_iop_fifo_in_r_masked_intr___dav___width 1
+#define reg_iop_fifo_in_r_masked_intr___dav___bit 2
+#define reg_iop_fifo_in_r_masked_intr___avail___lsb 3
+#define reg_iop_fifo_in_r_masked_intr___avail___width 1
+#define reg_iop_fifo_in_r_masked_intr___avail___bit 3
+#define reg_iop_fifo_in_r_masked_intr___orun___lsb 4
+#define reg_iop_fifo_in_r_masked_intr___orun___width 1
+#define reg_iop_fifo_in_r_masked_intr___orun___bit 4
+#define reg_iop_fifo_in_r_masked_intr_offset 64
+
+
+/* Constants */
+#define regk_iop_fifo_in_dif_in                   0x00000002
+#define regk_iop_fifo_in_hi                       0x00000000
+#define regk_iop_fifo_in_neg                      0x00000002
+#define regk_iop_fifo_in_no                       0x00000000
+#define regk_iop_fifo_in_order16                  0x00000001
+#define regk_iop_fifo_in_order24                  0x00000002
+#define regk_iop_fifo_in_order32                  0x00000003
+#define regk_iop_fifo_in_order8                   0x00000000
+#define regk_iop_fifo_in_pos                      0x00000001
+#define regk_iop_fifo_in_pos_neg                  0x00000003
+#define regk_iop_fifo_in_rw_cfg_default           0x00000024
+#define regk_iop_fifo_in_rw_ctrl_default          0x00000000
+#define regk_iop_fifo_in_rw_intr_mask_default     0x00000000
+#define regk_iop_fifo_in_rw_set_last_default      0x00000000
+#define regk_iop_fifo_in_rw_strb_dif_in_default   0x00000000
+#define regk_iop_fifo_in_size16                   0x00000002
+#define regk_iop_fifo_in_size24                   0x00000001
+#define regk_iop_fifo_in_size32                   0x00000000
+#define regk_iop_fifo_in_size8                    0x00000003
+#define regk_iop_fifo_in_yes                      0x00000001
+#endif /* __iop_fifo_in_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h
new file mode 100644
index 00000000000..e00fab0c933
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h
@@ -0,0 +1,155 @@
+#ifndef __iop_fifo_in_extra_defs_asm_h
+#define __iop_fifo_in_extra_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_fifo_in_extra.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:08 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r
+ *      id: $Id: iop_fifo_in_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */
+#define reg_iop_fifo_in_extra_rw_wr_data_offset 0
+
+/* Register r_stat, scope iop_fifo_in_extra, type r */
+#define reg_iop_fifo_in_extra_r_stat___avail_bytes___lsb 0
+#define reg_iop_fifo_in_extra_r_stat___avail_bytes___width 4
+#define reg_iop_fifo_in_extra_r_stat___last___lsb 4
+#define reg_iop_fifo_in_extra_r_stat___last___width 8
+#define reg_iop_fifo_in_extra_r_stat___dif_in_en___lsb 12
+#define reg_iop_fifo_in_extra_r_stat___dif_in_en___width 1
+#define reg_iop_fifo_in_extra_r_stat___dif_in_en___bit 12
+#define reg_iop_fifo_in_extra_r_stat___dif_out_en___lsb 13
+#define reg_iop_fifo_in_extra_r_stat___dif_out_en___width 1
+#define reg_iop_fifo_in_extra_r_stat___dif_out_en___bit 13
+#define reg_iop_fifo_in_extra_r_stat_offset 4
+
+/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */
+#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___lsb 0
+#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___width 2
+#define reg_iop_fifo_in_extra_rw_strb_dif_in_offset 8
+
+/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */
+#define reg_iop_fifo_in_extra_rw_intr_mask___urun___lsb 0
+#define reg_iop_fifo_in_extra_rw_intr_mask___urun___width 1
+#define reg_iop_fifo_in_extra_rw_intr_mask___urun___bit 0
+#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___lsb 1
+#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___width 1
+#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___bit 1
+#define reg_iop_fifo_in_extra_rw_intr_mask___dav___lsb 2
+#define reg_iop_fifo_in_extra_rw_intr_mask___dav___width 1
+#define reg_iop_fifo_in_extra_rw_intr_mask___dav___bit 2
+#define reg_iop_fifo_in_extra_rw_intr_mask___avail___lsb 3
+#define reg_iop_fifo_in_extra_rw_intr_mask___avail___width 1
+#define reg_iop_fifo_in_extra_rw_intr_mask___avail___bit 3
+#define reg_iop_fifo_in_extra_rw_intr_mask___orun___lsb 4
+#define reg_iop_fifo_in_extra_rw_intr_mask___orun___width 1
+#define reg_iop_fifo_in_extra_rw_intr_mask___orun___bit 4
+#define reg_iop_fifo_in_extra_rw_intr_mask_offset 12
+
+/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */
+#define reg_iop_fifo_in_extra_rw_ack_intr___urun___lsb 0
+#define reg_iop_fifo_in_extra_rw_ack_intr___urun___width 1
+#define reg_iop_fifo_in_extra_rw_ack_intr___urun___bit 0
+#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___lsb 1
+#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___width 1
+#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___bit 1
+#define reg_iop_fifo_in_extra_rw_ack_intr___dav___lsb 2
+#define reg_iop_fifo_in_extra_rw_ack_intr___dav___width 1
+#define reg_iop_fifo_in_extra_rw_ack_intr___dav___bit 2
+#define reg_iop_fifo_in_extra_rw_ack_intr___avail___lsb 3
+#define reg_iop_fifo_in_extra_rw_ack_intr___avail___width 1
+#define reg_iop_fifo_in_extra_rw_ack_intr___avail___bit 3
+#define reg_iop_fifo_in_extra_rw_ack_intr___orun___lsb 4
+#define reg_iop_fifo_in_extra_rw_ack_intr___orun___width 1
+#define reg_iop_fifo_in_extra_rw_ack_intr___orun___bit 4
+#define reg_iop_fifo_in_extra_rw_ack_intr_offset 16
+
+/* Register r_intr, scope iop_fifo_in_extra, type r */
+#define reg_iop_fifo_in_extra_r_intr___urun___lsb 0
+#define reg_iop_fifo_in_extra_r_intr___urun___width 1
+#define reg_iop_fifo_in_extra_r_intr___urun___bit 0
+#define reg_iop_fifo_in_extra_r_intr___last_data___lsb 1
+#define reg_iop_fifo_in_extra_r_intr___last_data___width 1
+#define reg_iop_fifo_in_extra_r_intr___last_data___bit 1
+#define reg_iop_fifo_in_extra_r_intr___dav___lsb 2
+#define reg_iop_fifo_in_extra_r_intr___dav___width 1
+#define reg_iop_fifo_in_extra_r_intr___dav___bit 2
+#define reg_iop_fifo_in_extra_r_intr___avail___lsb 3
+#define reg_iop_fifo_in_extra_r_intr___avail___width 1
+#define reg_iop_fifo_in_extra_r_intr___avail___bit 3
+#define reg_iop_fifo_in_extra_r_intr___orun___lsb 4
+#define reg_iop_fifo_in_extra_r_intr___orun___width 1
+#define reg_iop_fifo_in_extra_r_intr___orun___bit 4
+#define reg_iop_fifo_in_extra_r_intr_offset 20
+
+/* Register r_masked_intr, scope iop_fifo_in_extra, type r */
+#define reg_iop_fifo_in_extra_r_masked_intr___urun___lsb 0
+#define reg_iop_fifo_in_extra_r_masked_intr___urun___width 1
+#define reg_iop_fifo_in_extra_r_masked_intr___urun___bit 0
+#define reg_iop_fifo_in_extra_r_masked_intr___last_data___lsb 1
+#define reg_iop_fifo_in_extra_r_masked_intr___last_data___width 1
+#define reg_iop_fifo_in_extra_r_masked_intr___last_data___bit 1
+#define reg_iop_fifo_in_extra_r_masked_intr___dav___lsb 2
+#define reg_iop_fifo_in_extra_r_masked_intr___dav___width 1
+#define reg_iop_fifo_in_extra_r_masked_intr___dav___bit 2
+#define reg_iop_fifo_in_extra_r_masked_intr___avail___lsb 3
+#define reg_iop_fifo_in_extra_r_masked_intr___avail___width 1
+#define reg_iop_fifo_in_extra_r_masked_intr___avail___bit 3
+#define reg_iop_fifo_in_extra_r_masked_intr___orun___lsb 4
+#define reg_iop_fifo_in_extra_r_masked_intr___orun___width 1
+#define reg_iop_fifo_in_extra_r_masked_intr___orun___bit 4
+#define reg_iop_fifo_in_extra_r_masked_intr_offset 24
+
+
+/* Constants */
+#define regk_iop_fifo_in_extra_fifo_in            0x00000002
+#define regk_iop_fifo_in_extra_no                 0x00000000
+#define regk_iop_fifo_in_extra_rw_intr_mask_default  0x00000000
+#define regk_iop_fifo_in_extra_yes                0x00000001
+#endif /* __iop_fifo_in_extra_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h
new file mode 100644
index 00000000000..9ec5f4a826d
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_defs_asm.h
@@ -0,0 +1,254 @@
+#ifndef __iop_fifo_out_defs_asm_h
+#define __iop_fifo_out_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_fifo_out.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:09 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out.r
+ *      id: $Id: iop_fifo_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_cfg___free_lim___lsb 0
+#define reg_iop_fifo_out_rw_cfg___free_lim___width 3
+#define reg_iop_fifo_out_rw_cfg___byte_order___lsb 3
+#define reg_iop_fifo_out_rw_cfg___byte_order___width 2
+#define reg_iop_fifo_out_rw_cfg___trig___lsb 5
+#define reg_iop_fifo_out_rw_cfg___trig___width 2
+#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___lsb 7
+#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___width 1
+#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___bit 7
+#define reg_iop_fifo_out_rw_cfg___mode___lsb 8
+#define reg_iop_fifo_out_rw_cfg___mode___width 2
+#define reg_iop_fifo_out_rw_cfg___delay_out_last___lsb 10
+#define reg_iop_fifo_out_rw_cfg___delay_out_last___width 1
+#define reg_iop_fifo_out_rw_cfg___delay_out_last___bit 10
+#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___lsb 11
+#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___width 1
+#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___bit 11
+#define reg_iop_fifo_out_rw_cfg_offset 0
+
+/* Register rw_ctrl, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_ctrl___dif_in_en___lsb 0
+#define reg_iop_fifo_out_rw_ctrl___dif_in_en___width 1
+#define reg_iop_fifo_out_rw_ctrl___dif_in_en___bit 0
+#define reg_iop_fifo_out_rw_ctrl___dif_out_en___lsb 1
+#define reg_iop_fifo_out_rw_ctrl___dif_out_en___width 1
+#define reg_iop_fifo_out_rw_ctrl___dif_out_en___bit 1
+#define reg_iop_fifo_out_rw_ctrl_offset 4
+
+/* Register r_stat, scope iop_fifo_out, type r */
+#define reg_iop_fifo_out_r_stat___avail_bytes___lsb 0
+#define reg_iop_fifo_out_r_stat___avail_bytes___width 4
+#define reg_iop_fifo_out_r_stat___last___lsb 4
+#define reg_iop_fifo_out_r_stat___last___width 8
+#define reg_iop_fifo_out_r_stat___dif_in_en___lsb 12
+#define reg_iop_fifo_out_r_stat___dif_in_en___width 1
+#define reg_iop_fifo_out_r_stat___dif_in_en___bit 12
+#define reg_iop_fifo_out_r_stat___dif_out_en___lsb 13
+#define reg_iop_fifo_out_r_stat___dif_out_en___width 1
+#define reg_iop_fifo_out_r_stat___dif_out_en___bit 13
+#define reg_iop_fifo_out_r_stat___zero_data_last___lsb 14
+#define reg_iop_fifo_out_r_stat___zero_data_last___width 1
+#define reg_iop_fifo_out_r_stat___zero_data_last___bit 14
+#define reg_iop_fifo_out_r_stat_offset 8
+
+/* Register rw_wr1byte, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_wr1byte___data___lsb 0
+#define reg_iop_fifo_out_rw_wr1byte___data___width 8
+#define reg_iop_fifo_out_rw_wr1byte_offset 12
+
+/* Register rw_wr2byte, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_wr2byte___data___lsb 0
+#define reg_iop_fifo_out_rw_wr2byte___data___width 16
+#define reg_iop_fifo_out_rw_wr2byte_offset 16
+
+/* Register rw_wr3byte, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_wr3byte___data___lsb 0
+#define reg_iop_fifo_out_rw_wr3byte___data___width 24
+#define reg_iop_fifo_out_rw_wr3byte_offset 20
+
+/* Register rw_wr4byte, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_wr4byte___data___lsb 0
+#define reg_iop_fifo_out_rw_wr4byte___data___width 32
+#define reg_iop_fifo_out_rw_wr4byte_offset 24
+
+/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_wr1byte_last___data___lsb 0
+#define reg_iop_fifo_out_rw_wr1byte_last___data___width 8
+#define reg_iop_fifo_out_rw_wr1byte_last_offset 28
+
+/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_wr2byte_last___data___lsb 0
+#define reg_iop_fifo_out_rw_wr2byte_last___data___width 16
+#define reg_iop_fifo_out_rw_wr2byte_last_offset 32
+
+/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_wr3byte_last___data___lsb 0
+#define reg_iop_fifo_out_rw_wr3byte_last___data___width 24
+#define reg_iop_fifo_out_rw_wr3byte_last_offset 36
+
+/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_wr4byte_last___data___lsb 0
+#define reg_iop_fifo_out_rw_wr4byte_last___data___width 32
+#define reg_iop_fifo_out_rw_wr4byte_last_offset 40
+
+/* Register rw_set_last, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_set_last_offset 44
+
+/* Register rs_rd_data, scope iop_fifo_out, type rs */
+#define reg_iop_fifo_out_rs_rd_data_offset 48
+
+/* Register r_rd_data, scope iop_fifo_out, type r */
+#define reg_iop_fifo_out_r_rd_data_offset 52
+
+/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_strb_dif_out_offset 56
+
+/* Register rw_intr_mask, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_intr_mask___urun___lsb 0
+#define reg_iop_fifo_out_rw_intr_mask___urun___width 1
+#define reg_iop_fifo_out_rw_intr_mask___urun___bit 0
+#define reg_iop_fifo_out_rw_intr_mask___last_data___lsb 1
+#define reg_iop_fifo_out_rw_intr_mask___last_data___width 1
+#define reg_iop_fifo_out_rw_intr_mask___last_data___bit 1
+#define reg_iop_fifo_out_rw_intr_mask___dav___lsb 2
+#define reg_iop_fifo_out_rw_intr_mask___dav___width 1
+#define reg_iop_fifo_out_rw_intr_mask___dav___bit 2
+#define reg_iop_fifo_out_rw_intr_mask___free___lsb 3
+#define reg_iop_fifo_out_rw_intr_mask___free___width 1
+#define reg_iop_fifo_out_rw_intr_mask___free___bit 3
+#define reg_iop_fifo_out_rw_intr_mask___orun___lsb 4
+#define reg_iop_fifo_out_rw_intr_mask___orun___width 1
+#define reg_iop_fifo_out_rw_intr_mask___orun___bit 4
+#define reg_iop_fifo_out_rw_intr_mask_offset 60
+
+/* Register rw_ack_intr, scope iop_fifo_out, type rw */
+#define reg_iop_fifo_out_rw_ack_intr___urun___lsb 0
+#define reg_iop_fifo_out_rw_ack_intr___urun___width 1
+#define reg_iop_fifo_out_rw_ack_intr___urun___bit 0
+#define reg_iop_fifo_out_rw_ack_intr___last_data___lsb 1
+#define reg_iop_fifo_out_rw_ack_intr___last_data___width 1
+#define reg_iop_fifo_out_rw_ack_intr___last_data___bit 1
+#define reg_iop_fifo_out_rw_ack_intr___dav___lsb 2
+#define reg_iop_fifo_out_rw_ack_intr___dav___width 1
+#define reg_iop_fifo_out_rw_ack_intr___dav___bit 2
+#define reg_iop_fifo_out_rw_ack_intr___free___lsb 3
+#define reg_iop_fifo_out_rw_ack_intr___free___width 1
+#define reg_iop_fifo_out_rw_ack_intr___free___bit 3
+#define reg_iop_fifo_out_rw_ack_intr___orun___lsb 4
+#define reg_iop_fifo_out_rw_ack_intr___orun___width 1
+#define reg_iop_fifo_out_rw_ack_intr___orun___bit 4
+#define reg_iop_fifo_out_rw_ack_intr_offset 64
+
+/* Register r_intr, scope iop_fifo_out, type r */
+#define reg_iop_fifo_out_r_intr___urun___lsb 0
+#define reg_iop_fifo_out_r_intr___urun___width 1
+#define reg_iop_fifo_out_r_intr___urun___bit 0
+#define reg_iop_fifo_out_r_intr___last_data___lsb 1
+#define reg_iop_fifo_out_r_intr___last_data___width 1
+#define reg_iop_fifo_out_r_intr___last_data___bit 1
+#define reg_iop_fifo_out_r_intr___dav___lsb 2
+#define reg_iop_fifo_out_r_intr___dav___width 1
+#define reg_iop_fifo_out_r_intr___dav___bit 2
+#define reg_iop_fifo_out_r_intr___free___lsb 3
+#define reg_iop_fifo_out_r_intr___free___width 1
+#define reg_iop_fifo_out_r_intr___free___bit 3
+#define reg_iop_fifo_out_r_intr___orun___lsb 4
+#define reg_iop_fifo_out_r_intr___orun___width 1
+#define reg_iop_fifo_out_r_intr___orun___bit 4
+#define reg_iop_fifo_out_r_intr_offset 68
+
+/* Register r_masked_intr, scope iop_fifo_out, type r */
+#define reg_iop_fifo_out_r_masked_intr___urun___lsb 0
+#define reg_iop_fifo_out_r_masked_intr___urun___width 1
+#define reg_iop_fifo_out_r_masked_intr___urun___bit 0
+#define reg_iop_fifo_out_r_masked_intr___last_data___lsb 1
+#define reg_iop_fifo_out_r_masked_intr___last_data___width 1
+#define reg_iop_fifo_out_r_masked_intr___last_data___bit 1
+#define reg_iop_fifo_out_r_masked_intr___dav___lsb 2
+#define reg_iop_fifo_out_r_masked_intr___dav___width 1
+#define reg_iop_fifo_out_r_masked_intr___dav___bit 2
+#define reg_iop_fifo_out_r_masked_intr___free___lsb 3
+#define reg_iop_fifo_out_r_masked_intr___free___width 1
+#define reg_iop_fifo_out_r_masked_intr___free___bit 3
+#define reg_iop_fifo_out_r_masked_intr___orun___lsb 4
+#define reg_iop_fifo_out_r_masked_intr___orun___width 1
+#define reg_iop_fifo_out_r_masked_intr___orun___bit 4
+#define reg_iop_fifo_out_r_masked_intr_offset 72
+
+
+/* Constants */
+#define regk_iop_fifo_out_hi                      0x00000000
+#define regk_iop_fifo_out_neg                     0x00000002
+#define regk_iop_fifo_out_no                      0x00000000
+#define regk_iop_fifo_out_order16                 0x00000001
+#define regk_iop_fifo_out_order24                 0x00000002
+#define regk_iop_fifo_out_order32                 0x00000003
+#define regk_iop_fifo_out_order8                  0x00000000
+#define regk_iop_fifo_out_pos                     0x00000001
+#define regk_iop_fifo_out_pos_neg                 0x00000003
+#define regk_iop_fifo_out_rw_cfg_default          0x00000024
+#define regk_iop_fifo_out_rw_ctrl_default         0x00000000
+#define regk_iop_fifo_out_rw_intr_mask_default    0x00000000
+#define regk_iop_fifo_out_rw_set_last_default     0x00000000
+#define regk_iop_fifo_out_rw_strb_dif_out_default  0x00000000
+#define regk_iop_fifo_out_rw_wr1byte_default      0x00000000
+#define regk_iop_fifo_out_rw_wr1byte_last_default  0x00000000
+#define regk_iop_fifo_out_rw_wr2byte_default      0x00000000
+#define regk_iop_fifo_out_rw_wr2byte_last_default  0x00000000
+#define regk_iop_fifo_out_rw_wr3byte_default      0x00000000
+#define regk_iop_fifo_out_rw_wr3byte_last_default  0x00000000
+#define regk_iop_fifo_out_rw_wr4byte_default      0x00000000
+#define regk_iop_fifo_out_rw_wr4byte_last_default  0x00000000
+#define regk_iop_fifo_out_size16                  0x00000002
+#define regk_iop_fifo_out_size24                  0x00000001
+#define regk_iop_fifo_out_size32                  0x00000000
+#define regk_iop_fifo_out_size8                   0x00000003
+#define regk_iop_fifo_out_yes                     0x00000001
+#endif /* __iop_fifo_out_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h
new file mode 100644
index 00000000000..0f84a50cf77
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h
@@ -0,0 +1,158 @@
+#ifndef __iop_fifo_out_extra_defs_asm_h
+#define __iop_fifo_out_extra_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_fifo_out_extra.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:10 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r
+ *      id: $Id: iop_fifo_out_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */
+#define reg_iop_fifo_out_extra_rs_rd_data_offset 0
+
+/* Register r_rd_data, scope iop_fifo_out_extra, type r */
+#define reg_iop_fifo_out_extra_r_rd_data_offset 4
+
+/* Register r_stat, scope iop_fifo_out_extra, type r */
+#define reg_iop_fifo_out_extra_r_stat___avail_bytes___lsb 0
+#define reg_iop_fifo_out_extra_r_stat___avail_bytes___width 4
+#define reg_iop_fifo_out_extra_r_stat___last___lsb 4
+#define reg_iop_fifo_out_extra_r_stat___last___width 8
+#define reg_iop_fifo_out_extra_r_stat___dif_in_en___lsb 12
+#define reg_iop_fifo_out_extra_r_stat___dif_in_en___width 1
+#define reg_iop_fifo_out_extra_r_stat___dif_in_en___bit 12
+#define reg_iop_fifo_out_extra_r_stat___dif_out_en___lsb 13
+#define reg_iop_fifo_out_extra_r_stat___dif_out_en___width 1
+#define reg_iop_fifo_out_extra_r_stat___dif_out_en___bit 13
+#define reg_iop_fifo_out_extra_r_stat___zero_data_last___lsb 14
+#define reg_iop_fifo_out_extra_r_stat___zero_data_last___width 1
+#define reg_iop_fifo_out_extra_r_stat___zero_data_last___bit 14
+#define reg_iop_fifo_out_extra_r_stat_offset 8
+
+/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */
+#define reg_iop_fifo_out_extra_rw_strb_dif_out_offset 12
+
+/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */
+#define reg_iop_fifo_out_extra_rw_intr_mask___urun___lsb 0
+#define reg_iop_fifo_out_extra_rw_intr_mask___urun___width 1
+#define reg_iop_fifo_out_extra_rw_intr_mask___urun___bit 0
+#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___lsb 1
+#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___width 1
+#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___bit 1
+#define reg_iop_fifo_out_extra_rw_intr_mask___dav___lsb 2
+#define reg_iop_fifo_out_extra_rw_intr_mask___dav___width 1
+#define reg_iop_fifo_out_extra_rw_intr_mask___dav___bit 2
+#define reg_iop_fifo_out_extra_rw_intr_mask___free___lsb 3
+#define reg_iop_fifo_out_extra_rw_intr_mask___free___width 1
+#define reg_iop_fifo_out_extra_rw_intr_mask___free___bit 3
+#define reg_iop_fifo_out_extra_rw_intr_mask___orun___lsb 4
+#define reg_iop_fifo_out_extra_rw_intr_mask___orun___width 1
+#define reg_iop_fifo_out_extra_rw_intr_mask___orun___bit 4
+#define reg_iop_fifo_out_extra_rw_intr_mask_offset 16
+
+/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */
+#define reg_iop_fifo_out_extra_rw_ack_intr___urun___lsb 0
+#define reg_iop_fifo_out_extra_rw_ack_intr___urun___width 1
+#define reg_iop_fifo_out_extra_rw_ack_intr___urun___bit 0
+#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___lsb 1
+#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___width 1
+#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___bit 1
+#define reg_iop_fifo_out_extra_rw_ack_intr___dav___lsb 2
+#define reg_iop_fifo_out_extra_rw_ack_intr___dav___width 1
+#define reg_iop_fifo_out_extra_rw_ack_intr___dav___bit 2
+#define reg_iop_fifo_out_extra_rw_ack_intr___free___lsb 3
+#define reg_iop_fifo_out_extra_rw_ack_intr___free___width 1
+#define reg_iop_fifo_out_extra_rw_ack_intr___free___bit 3
+#define reg_iop_fifo_out_extra_rw_ack_intr___orun___lsb 4
+#define reg_iop_fifo_out_extra_rw_ack_intr___orun___width 1
+#define reg_iop_fifo_out_extra_rw_ack_intr___orun___bit 4
+#define reg_iop_fifo_out_extra_rw_ack_intr_offset 20
+
+/* Register r_intr, scope iop_fifo_out_extra, type r */
+#define reg_iop_fifo_out_extra_r_intr___urun___lsb 0
+#define reg_iop_fifo_out_extra_r_intr___urun___width 1
+#define reg_iop_fifo_out_extra_r_intr___urun___bit 0
+#define reg_iop_fifo_out_extra_r_intr___last_data___lsb 1
+#define reg_iop_fifo_out_extra_r_intr___last_data___width 1
+#define reg_iop_fifo_out_extra_r_intr___last_data___bit 1
+#define reg_iop_fifo_out_extra_r_intr___dav___lsb 2
+#define reg_iop_fifo_out_extra_r_intr___dav___width 1
+#define reg_iop_fifo_out_extra_r_intr___dav___bit 2
+#define reg_iop_fifo_out_extra_r_intr___free___lsb 3
+#define reg_iop_fifo_out_extra_r_intr___free___width 1
+#define reg_iop_fifo_out_extra_r_intr___free___bit 3
+#define reg_iop_fifo_out_extra_r_intr___orun___lsb 4
+#define reg_iop_fifo_out_extra_r_intr___orun___width 1
+#define reg_iop_fifo_out_extra_r_intr___orun___bit 4
+#define reg_iop_fifo_out_extra_r_intr_offset 24
+
+/* Register r_masked_intr, scope iop_fifo_out_extra, type r */
+#define reg_iop_fifo_out_extra_r_masked_intr___urun___lsb 0
+#define reg_iop_fifo_out_extra_r_masked_intr___urun___width 1
+#define reg_iop_fifo_out_extra_r_masked_intr___urun___bit 0
+#define reg_iop_fifo_out_extra_r_masked_intr___last_data___lsb 1
+#define reg_iop_fifo_out_extra_r_masked_intr___last_data___width 1
+#define reg_iop_fifo_out_extra_r_masked_intr___last_data___bit 1
+#define reg_iop_fifo_out_extra_r_masked_intr___dav___lsb 2
+#define reg_iop_fifo_out_extra_r_masked_intr___dav___width 1
+#define reg_iop_fifo_out_extra_r_masked_intr___dav___bit 2
+#define reg_iop_fifo_out_extra_r_masked_intr___free___lsb 3
+#define reg_iop_fifo_out_extra_r_masked_intr___free___width 1
+#define reg_iop_fifo_out_extra_r_masked_intr___free___bit 3
+#define reg_iop_fifo_out_extra_r_masked_intr___orun___lsb 4
+#define reg_iop_fifo_out_extra_r_masked_intr___orun___width 1
+#define reg_iop_fifo_out_extra_r_masked_intr___orun___bit 4
+#define reg_iop_fifo_out_extra_r_masked_intr_offset 28
+
+
+/* Constants */
+#define regk_iop_fifo_out_extra_no                0x00000000
+#define regk_iop_fifo_out_extra_rw_intr_mask_default  0x00000000
+#define regk_iop_fifo_out_extra_yes               0x00000001
+#endif /* __iop_fifo_out_extra_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h
new file mode 100644
index 00000000000..80490c82cc2
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_mpu_defs_asm.h
@@ -0,0 +1,177 @@
+#ifndef __iop_mpu_defs_asm_h
+#define __iop_mpu_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_mpu.r
+ *     id:           iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:45 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_mpu_defs_asm.h ../../inst/io_proc/rtl/iop_mpu.r
+ *      id: $Id: iop_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+#define STRIDE_iop_mpu_rw_r 4
+/* Register rw_r, scope iop_mpu, type rw */
+#define reg_iop_mpu_rw_r_offset 0
+
+/* Register rw_ctrl, scope iop_mpu, type rw */
+#define reg_iop_mpu_rw_ctrl___en___lsb 0
+#define reg_iop_mpu_rw_ctrl___en___width 1
+#define reg_iop_mpu_rw_ctrl___en___bit 0
+#define reg_iop_mpu_rw_ctrl_offset 128
+
+/* Register r_pc, scope iop_mpu, type r */
+#define reg_iop_mpu_r_pc___addr___lsb 0
+#define reg_iop_mpu_r_pc___addr___width 12
+#define reg_iop_mpu_r_pc_offset 132
+
+/* Register r_stat, scope iop_mpu, type r */
+#define reg_iop_mpu_r_stat___instr_reg_busy___lsb 0
+#define reg_iop_mpu_r_stat___instr_reg_busy___width 1
+#define reg_iop_mpu_r_stat___instr_reg_busy___bit 0
+#define reg_iop_mpu_r_stat___intr_busy___lsb 1
+#define reg_iop_mpu_r_stat___intr_busy___width 1
+#define reg_iop_mpu_r_stat___intr_busy___bit 1
+#define reg_iop_mpu_r_stat___intr_vect___lsb 2
+#define reg_iop_mpu_r_stat___intr_vect___width 16
+#define reg_iop_mpu_r_stat_offset 136
+
+/* Register rw_instr, scope iop_mpu, type rw */
+#define reg_iop_mpu_rw_instr_offset 140
+
+/* Register rw_immediate, scope iop_mpu, type rw */
+#define reg_iop_mpu_rw_immediate_offset 144
+
+/* Register r_trace, scope iop_mpu, type r */
+#define reg_iop_mpu_r_trace___intr_vect___lsb 0
+#define reg_iop_mpu_r_trace___intr_vect___width 16
+#define reg_iop_mpu_r_trace___pc___lsb 16
+#define reg_iop_mpu_r_trace___pc___width 12
+#define reg_iop_mpu_r_trace___en___lsb 28
+#define reg_iop_mpu_r_trace___en___width 1
+#define reg_iop_mpu_r_trace___en___bit 28
+#define reg_iop_mpu_r_trace___instr_reg_busy___lsb 29
+#define reg_iop_mpu_r_trace___instr_reg_busy___width 1
+#define reg_iop_mpu_r_trace___instr_reg_busy___bit 29
+#define reg_iop_mpu_r_trace___intr_busy___lsb 30
+#define reg_iop_mpu_r_trace___intr_busy___width 1
+#define reg_iop_mpu_r_trace___intr_busy___bit 30
+#define reg_iop_mpu_r_trace_offset 148
+
+/* Register r_wr_stat, scope iop_mpu, type r */
+#define reg_iop_mpu_r_wr_stat___r0___lsb 0
+#define reg_iop_mpu_r_wr_stat___r0___width 1
+#define reg_iop_mpu_r_wr_stat___r0___bit 0
+#define reg_iop_mpu_r_wr_stat___r1___lsb 1
+#define reg_iop_mpu_r_wr_stat___r1___width 1
+#define reg_iop_mpu_r_wr_stat___r1___bit 1
+#define reg_iop_mpu_r_wr_stat___r2___lsb 2
+#define reg_iop_mpu_r_wr_stat___r2___width 1
+#define reg_iop_mpu_r_wr_stat___r2___bit 2
+#define reg_iop_mpu_r_wr_stat___r3___lsb 3
+#define reg_iop_mpu_r_wr_stat___r3___width 1
+#define reg_iop_mpu_r_wr_stat___r3___bit 3
+#define reg_iop_mpu_r_wr_stat___r4___lsb 4
+#define reg_iop_mpu_r_wr_stat___r4___width 1
+#define reg_iop_mpu_r_wr_stat___r4___bit 4
+#define reg_iop_mpu_r_wr_stat___r5___lsb 5
+#define reg_iop_mpu_r_wr_stat___r5___width 1
+#define reg_iop_mpu_r_wr_stat___r5___bit 5
+#define reg_iop_mpu_r_wr_stat___r6___lsb 6
+#define reg_iop_mpu_r_wr_stat___r6___width 1
+#define reg_iop_mpu_r_wr_stat___r6___bit 6
+#define reg_iop_mpu_r_wr_stat___r7___lsb 7
+#define reg_iop_mpu_r_wr_stat___r7___width 1
+#define reg_iop_mpu_r_wr_stat___r7___bit 7
+#define reg_iop_mpu_r_wr_stat___r8___lsb 8
+#define reg_iop_mpu_r_wr_stat___r8___width 1
+#define reg_iop_mpu_r_wr_stat___r8___bit 8
+#define reg_iop_mpu_r_wr_stat___r9___lsb 9
+#define reg_iop_mpu_r_wr_stat___r9___width 1
+#define reg_iop_mpu_r_wr_stat___r9___bit 9
+#define reg_iop_mpu_r_wr_stat___r10___lsb 10
+#define reg_iop_mpu_r_wr_stat___r10___width 1
+#define reg_iop_mpu_r_wr_stat___r10___bit 10
+#define reg_iop_mpu_r_wr_stat___r11___lsb 11
+#define reg_iop_mpu_r_wr_stat___r11___width 1
+#define reg_iop_mpu_r_wr_stat___r11___bit 11
+#define reg_iop_mpu_r_wr_stat___r12___lsb 12
+#define reg_iop_mpu_r_wr_stat___r12___width 1
+#define reg_iop_mpu_r_wr_stat___r12___bit 12
+#define reg_iop_mpu_r_wr_stat___r13___lsb 13
+#define reg_iop_mpu_r_wr_stat___r13___width 1
+#define reg_iop_mpu_r_wr_stat___r13___bit 13
+#define reg_iop_mpu_r_wr_stat___r14___lsb 14
+#define reg_iop_mpu_r_wr_stat___r14___width 1
+#define reg_iop_mpu_r_wr_stat___r14___bit 14
+#define reg_iop_mpu_r_wr_stat___r15___lsb 15
+#define reg_iop_mpu_r_wr_stat___r15___width 1
+#define reg_iop_mpu_r_wr_stat___r15___bit 15
+#define reg_iop_mpu_r_wr_stat_offset 152
+
+#define STRIDE_iop_mpu_rw_thread 4
+/* Register rw_thread, scope iop_mpu, type rw */
+#define reg_iop_mpu_rw_thread___addr___lsb 0
+#define reg_iop_mpu_rw_thread___addr___width 12
+#define reg_iop_mpu_rw_thread_offset 156
+
+#define STRIDE_iop_mpu_rw_intr 4
+/* Register rw_intr, scope iop_mpu, type rw */
+#define reg_iop_mpu_rw_intr___addr___lsb 0
+#define reg_iop_mpu_rw_intr___addr___width 12
+#define reg_iop_mpu_rw_intr_offset 196
+
+
+/* Constants */
+#define regk_iop_mpu_no                           0x00000000
+#define regk_iop_mpu_r_pc_default                 0x00000000
+#define regk_iop_mpu_rw_ctrl_default              0x00000000
+#define regk_iop_mpu_rw_intr_size                 0x00000010
+#define regk_iop_mpu_rw_r_size                    0x00000010
+#define regk_iop_mpu_rw_thread_default            0x00000000
+#define regk_iop_mpu_rw_thread_size               0x00000004
+#define regk_iop_mpu_yes                          0x00000001
+#endif /* __iop_mpu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h
new file mode 100644
index 00000000000..a20b8857b4d
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_reg_space_asm.h
@@ -0,0 +1,44 @@
+/* Autogenerated Changes here will be lost!
+ * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg
+ */
+#define iop_version 0
+#define iop_fifo_in0_extra 64
+#define iop_fifo_in1_extra 128
+#define iop_fifo_out0_extra 192
+#define iop_fifo_out1_extra 256
+#define iop_trigger_grp0 320
+#define iop_trigger_grp1 384
+#define iop_trigger_grp2 448
+#define iop_trigger_grp3 512
+#define iop_trigger_grp4 576
+#define iop_trigger_grp5 640
+#define iop_trigger_grp6 704
+#define iop_trigger_grp7 768
+#define iop_crc_par0 896
+#define iop_crc_par1 1024
+#define iop_dmc_in0 1152
+#define iop_dmc_in1 1280
+#define iop_dmc_out0 1408
+#define iop_dmc_out1 1536
+#define iop_fifo_in0 1664
+#define iop_fifo_in1 1792
+#define iop_fifo_out0 1920
+#define iop_fifo_out1 2048
+#define iop_scrc_in0 2176
+#define iop_scrc_in1 2304
+#define iop_scrc_out0 2432
+#define iop_scrc_out1 2560
+#define iop_timer_grp0 2688
+#define iop_timer_grp1 2816
+#define iop_timer_grp2 2944
+#define iop_timer_grp3 3072
+#define iop_sap_in 3328
+#define iop_sap_out 3584
+#define iop_spu0 3840
+#define iop_spu1 4096
+#define iop_sw_cfg 4352
+#define iop_sw_cpu 4608
+#define iop_sw_mpu 4864
+#define iop_sw_spu0 5120
+#define iop_sw_spu1 5376
+#define iop_mpu 5632
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h
new file mode 100644
index 00000000000..a4a10ff300b
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_in_defs_asm.h
@@ -0,0 +1,182 @@
+#ifndef __iop_sap_in_defs_asm_h
+#define __iop_sap_in_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_sap_in.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:08:45 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_in_defs_asm.h ../../inst/io_proc/rtl/iop_sap_in.r
+ *      id: $Id: iop_sap_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_bus0_sync, scope iop_sap_in, type rw */
+#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___lsb 0
+#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___width 2
+#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___lsb 2
+#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___width 3
+#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___lsb 5
+#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___width 2
+#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___lsb 7
+#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___width 1
+#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___bit 7
+#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___lsb 8
+#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___width 2
+#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___lsb 10
+#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___width 3
+#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___lsb 13
+#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___width 2
+#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___lsb 15
+#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___width 1
+#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___bit 15
+#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___lsb 16
+#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___width 2
+#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___lsb 18
+#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___width 3
+#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___lsb 21
+#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___width 2
+#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___lsb 23
+#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___width 1
+#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___bit 23
+#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___lsb 24
+#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___width 2
+#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___lsb 26
+#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___width 3
+#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___lsb 29
+#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___width 2
+#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___lsb 31
+#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___width 1
+#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___bit 31
+#define reg_iop_sap_in_rw_bus0_sync_offset 0
+
+/* Register rw_bus1_sync, scope iop_sap_in, type rw */
+#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___lsb 0
+#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___width 2
+#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___lsb 2
+#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___width 3
+#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___lsb 5
+#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___width 2
+#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___lsb 7
+#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___width 1
+#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___bit 7
+#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___lsb 8
+#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___width 2
+#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___lsb 10
+#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___width 3
+#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___lsb 13
+#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___width 2
+#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___lsb 15
+#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___width 1
+#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___bit 15
+#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___lsb 16
+#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___width 2
+#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___lsb 18
+#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___width 3
+#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___lsb 21
+#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___width 2
+#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___lsb 23
+#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___width 1
+#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___bit 23
+#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___lsb 24
+#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___width 2
+#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___lsb 26
+#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___width 3
+#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___lsb 29
+#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___width 2
+#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___lsb 31
+#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___width 1
+#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___bit 31
+#define reg_iop_sap_in_rw_bus1_sync_offset 4
+
+#define STRIDE_iop_sap_in_rw_gio 4
+/* Register rw_gio, scope iop_sap_in, type rw */
+#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0
+#define reg_iop_sap_in_rw_gio___sync_sel___width 2
+#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2
+#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3
+#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5
+#define reg_iop_sap_in_rw_gio___sync_edge___width 2
+#define reg_iop_sap_in_rw_gio___delay___lsb 7
+#define reg_iop_sap_in_rw_gio___delay___width 1
+#define reg_iop_sap_in_rw_gio___delay___bit 7
+#define reg_iop_sap_in_rw_gio___logic___lsb 8
+#define reg_iop_sap_in_rw_gio___logic___width 2
+#define reg_iop_sap_in_rw_gio_offset 8
+
+
+/* Constants */
+#define regk_iop_sap_in_and                       0x00000002
+#define regk_iop_sap_in_ext_clk200                0x00000003
+#define regk_iop_sap_in_gio1                      0x00000000
+#define regk_iop_sap_in_gio13                     0x00000005
+#define regk_iop_sap_in_gio18                     0x00000003
+#define regk_iop_sap_in_gio19                     0x00000004
+#define regk_iop_sap_in_gio21                     0x00000006
+#define regk_iop_sap_in_gio23                     0x00000005
+#define regk_iop_sap_in_gio29                     0x00000007
+#define regk_iop_sap_in_gio5                      0x00000004
+#define regk_iop_sap_in_gio6                      0x00000001
+#define regk_iop_sap_in_gio7                      0x00000002
+#define regk_iop_sap_in_inv                       0x00000001
+#define regk_iop_sap_in_neg                       0x00000002
+#define regk_iop_sap_in_no                        0x00000000
+#define regk_iop_sap_in_no_del_ext_clk200         0x00000001
+#define regk_iop_sap_in_none                      0x00000000
+#define regk_iop_sap_in_or                        0x00000003
+#define regk_iop_sap_in_pos                       0x00000001
+#define regk_iop_sap_in_pos_neg                   0x00000003
+#define regk_iop_sap_in_rw_bus0_sync_default      0x02020202
+#define regk_iop_sap_in_rw_bus1_sync_default      0x02020202
+#define regk_iop_sap_in_rw_gio_default            0x00000002
+#define regk_iop_sap_in_rw_gio_size               0x00000020
+#define regk_iop_sap_in_timer_grp0_tmr3           0x00000006
+#define regk_iop_sap_in_timer_grp1_tmr3           0x00000004
+#define regk_iop_sap_in_timer_grp2_tmr3           0x00000005
+#define regk_iop_sap_in_timer_grp3_tmr3           0x00000007
+#define regk_iop_sap_in_tmr_clk200                0x00000000
+#define regk_iop_sap_in_two_clk200                0x00000002
+#define regk_iop_sap_in_yes                       0x00000001
+#endif /* __iop_sap_in_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h
new file mode 100644
index 00000000000..0ec727f92a2
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sap_out_defs_asm.h
@@ -0,0 +1,346 @@
+#ifndef __iop_sap_out_defs_asm_h
+#define __iop_sap_out_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_sap_out.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_out_defs_asm.h ../../inst/io_proc/rtl/iop_sap_out.r
+ *      id: $Id: iop_sap_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_gen_gated, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0
+#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2
+#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2
+#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2
+#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4
+#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3
+#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7
+#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2
+#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9
+#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2
+#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11
+#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3
+#define reg_iop_sap_out_rw_gen_gated___clk2_src___lsb 14
+#define reg_iop_sap_out_rw_gen_gated___clk2_src___width 2
+#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___lsb 16
+#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___width 2
+#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___lsb 18
+#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___width 3
+#define reg_iop_sap_out_rw_gen_gated___clk3_src___lsb 21
+#define reg_iop_sap_out_rw_gen_gated___clk3_src___width 2
+#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___lsb 23
+#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___width 2
+#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___lsb 25
+#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___width 3
+#define reg_iop_sap_out_rw_gen_gated_offset 0
+
+/* Register rw_bus0, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___lsb 0
+#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___lsb 3
+#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___lsb 5
+#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___bit 5
+#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___lsb 6
+#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___lsb 9
+#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___lsb 11
+#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___bit 11
+#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___lsb 12
+#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___lsb 15
+#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___lsb 17
+#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___bit 17
+#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___lsb 18
+#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___lsb 21
+#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___lsb 23
+#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___bit 23
+#define reg_iop_sap_out_rw_bus0_offset 4
+
+/* Register rw_bus1, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___lsb 0
+#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___lsb 3
+#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___lsb 5
+#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___bit 5
+#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___lsb 6
+#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___lsb 9
+#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___lsb 11
+#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___bit 11
+#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___lsb 12
+#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___lsb 15
+#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___lsb 17
+#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___bit 17
+#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___lsb 18
+#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___lsb 21
+#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___lsb 23
+#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___bit 23
+#define reg_iop_sap_out_rw_bus1_offset 8
+
+/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___lsb 0
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___lsb 3
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___width 3
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___lsb 6
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___lsb 8
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___bit 8
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___lsb 9
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___width 2
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___lsb 11
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___lsb 14
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___width 3
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___lsb 17
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___lsb 19
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___bit 19
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___lsb 20
+#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___width 2
+#define reg_iop_sap_out_rw_bus0_lo_oe_offset 12
+
+/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___lsb 0
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___lsb 3
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___width 3
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___lsb 6
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___lsb 8
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___bit 8
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___lsb 9
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___width 2
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___lsb 11
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___lsb 14
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___width 3
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___lsb 17
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___lsb 19
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___bit 19
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___lsb 20
+#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___width 2
+#define reg_iop_sap_out_rw_bus0_hi_oe_offset 16
+
+/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___lsb 0
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___lsb 3
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___width 3
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___lsb 6
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___lsb 8
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___bit 8
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___lsb 9
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___width 2
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___lsb 11
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___lsb 14
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___width 3
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___lsb 17
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___lsb 19
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___bit 19
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___lsb 20
+#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___width 2
+#define reg_iop_sap_out_rw_bus1_lo_oe_offset 20
+
+/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___lsb 0
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___lsb 3
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___width 3
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___lsb 6
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___lsb 8
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___bit 8
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___lsb 9
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___width 2
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___lsb 11
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___width 3
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___lsb 14
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___width 3
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___lsb 17
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___width 2
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___lsb 19
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___bit 19
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___lsb 20
+#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___width 2
+#define reg_iop_sap_out_rw_bus1_hi_oe_offset 24
+
+#define STRIDE_iop_sap_out_rw_gio 4
+/* Register rw_gio, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0
+#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3
+#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3
+#define reg_iop_sap_out_rw_gio___out_clk_ext___width 4
+#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 7
+#define reg_iop_sap_out_rw_gio___out_gated_clk___width 2
+#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 9
+#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1
+#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 9
+#define reg_iop_sap_out_rw_gio___out_logic___lsb 10
+#define reg_iop_sap_out_rw_gio___out_logic___width 1
+#define reg_iop_sap_out_rw_gio___out_logic___bit 10
+#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 11
+#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3
+#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 14
+#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 3
+#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17
+#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 2
+#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 19
+#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1
+#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 19
+#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20
+#define reg_iop_sap_out_rw_gio___oe_logic___width 2
+#define reg_iop_sap_out_rw_gio_offset 28
+
+
+/* Constants */
+#define regk_iop_sap_out_and                      0x00000002
+#define regk_iop_sap_out_clk0                     0x00000000
+#define regk_iop_sap_out_clk1                     0x00000001
+#define regk_iop_sap_out_clk12                    0x00000002
+#define regk_iop_sap_out_clk2                     0x00000002
+#define regk_iop_sap_out_clk200                   0x00000001
+#define regk_iop_sap_out_clk3                     0x00000003
+#define regk_iop_sap_out_ext                      0x00000003
+#define regk_iop_sap_out_gated                    0x00000004
+#define regk_iop_sap_out_gio1                     0x00000000
+#define regk_iop_sap_out_gio13                    0x00000002
+#define regk_iop_sap_out_gio13_clk                0x0000000c
+#define regk_iop_sap_out_gio15                    0x00000001
+#define regk_iop_sap_out_gio18                    0x00000003
+#define regk_iop_sap_out_gio18_clk                0x0000000d
+#define regk_iop_sap_out_gio1_clk                 0x00000008
+#define regk_iop_sap_out_gio21_clk                0x0000000e
+#define regk_iop_sap_out_gio23                    0x00000002
+#define regk_iop_sap_out_gio29_clk                0x0000000f
+#define regk_iop_sap_out_gio31                    0x00000003
+#define regk_iop_sap_out_gio5                     0x00000001
+#define regk_iop_sap_out_gio5_clk                 0x00000009
+#define regk_iop_sap_out_gio6_clk                 0x0000000a
+#define regk_iop_sap_out_gio7                     0x00000000
+#define regk_iop_sap_out_gio7_clk                 0x0000000b
+#define regk_iop_sap_out_gio_in13                 0x00000001
+#define regk_iop_sap_out_gio_in21                 0x00000002
+#define regk_iop_sap_out_gio_in29                 0x00000003
+#define regk_iop_sap_out_gio_in5                  0x00000000
+#define regk_iop_sap_out_inv                      0x00000001
+#define regk_iop_sap_out_nand                     0x00000003
+#define regk_iop_sap_out_no                       0x00000000
+#define regk_iop_sap_out_none                     0x00000000
+#define regk_iop_sap_out_rw_bus0_default          0x00000000
+#define regk_iop_sap_out_rw_bus0_hi_oe_default    0x00000000
+#define regk_iop_sap_out_rw_bus0_lo_oe_default    0x00000000
+#define regk_iop_sap_out_rw_bus1_default          0x00000000
+#define regk_iop_sap_out_rw_bus1_hi_oe_default    0x00000000
+#define regk_iop_sap_out_rw_bus1_lo_oe_default    0x00000000
+#define regk_iop_sap_out_rw_gen_gated_default     0x00000000
+#define regk_iop_sap_out_rw_gio_default           0x00000000
+#define regk_iop_sap_out_rw_gio_size              0x00000020
+#define regk_iop_sap_out_spu0_gio0                0x00000002
+#define regk_iop_sap_out_spu0_gio1                0x00000003
+#define regk_iop_sap_out_spu0_gio12               0x00000004
+#define regk_iop_sap_out_spu0_gio13               0x00000004
+#define regk_iop_sap_out_spu0_gio14               0x00000004
+#define regk_iop_sap_out_spu0_gio15               0x00000004
+#define regk_iop_sap_out_spu0_gio2                0x00000002
+#define regk_iop_sap_out_spu0_gio3                0x00000003
+#define regk_iop_sap_out_spu0_gio4                0x00000002
+#define regk_iop_sap_out_spu0_gio5                0x00000003
+#define regk_iop_sap_out_spu0_gio6                0x00000002
+#define regk_iop_sap_out_spu0_gio7                0x00000003
+#define regk_iop_sap_out_spu1_gio0                0x00000005
+#define regk_iop_sap_out_spu1_gio1                0x00000006
+#define regk_iop_sap_out_spu1_gio12               0x00000007
+#define regk_iop_sap_out_spu1_gio13               0x00000007
+#define regk_iop_sap_out_spu1_gio14               0x00000007
+#define regk_iop_sap_out_spu1_gio15               0x00000007
+#define regk_iop_sap_out_spu1_gio2                0x00000005
+#define regk_iop_sap_out_spu1_gio3                0x00000006
+#define regk_iop_sap_out_spu1_gio4                0x00000005
+#define regk_iop_sap_out_spu1_gio5                0x00000006
+#define regk_iop_sap_out_spu1_gio6                0x00000005
+#define regk_iop_sap_out_spu1_gio7                0x00000006
+#define regk_iop_sap_out_timer_grp0_tmr2          0x00000004
+#define regk_iop_sap_out_timer_grp1_tmr2          0x00000005
+#define regk_iop_sap_out_timer_grp2_tmr2          0x00000006
+#define regk_iop_sap_out_timer_grp3_tmr2          0x00000007
+#define regk_iop_sap_out_tmr                      0x00000005
+#define regk_iop_sap_out_yes                      0x00000001
+#endif /* __iop_sap_out_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h
new file mode 100644
index 00000000000..2cf5721597f
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_in_defs_asm.h
@@ -0,0 +1,111 @@
+#ifndef __iop_scrc_in_defs_asm_h
+#define __iop_scrc_in_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_scrc_in.r
+ *     id:           iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_in_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_in.r
+ *      id: $Id: iop_scrc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope iop_scrc_in, type rw */
+#define reg_iop_scrc_in_rw_cfg___trig___lsb 0
+#define reg_iop_scrc_in_rw_cfg___trig___width 2
+#define reg_iop_scrc_in_rw_cfg_offset 0
+
+/* Register rw_ctrl, scope iop_scrc_in, type rw */
+#define reg_iop_scrc_in_rw_ctrl___dif_in_en___lsb 0
+#define reg_iop_scrc_in_rw_ctrl___dif_in_en___width 1
+#define reg_iop_scrc_in_rw_ctrl___dif_in_en___bit 0
+#define reg_iop_scrc_in_rw_ctrl_offset 4
+
+/* Register r_stat, scope iop_scrc_in, type r */
+#define reg_iop_scrc_in_r_stat___err___lsb 0
+#define reg_iop_scrc_in_r_stat___err___width 1
+#define reg_iop_scrc_in_r_stat___err___bit 0
+#define reg_iop_scrc_in_r_stat_offset 8
+
+/* Register rw_init_crc, scope iop_scrc_in, type rw */
+#define reg_iop_scrc_in_rw_init_crc_offset 12
+
+/* Register rs_computed_crc, scope iop_scrc_in, type rs */
+#define reg_iop_scrc_in_rs_computed_crc_offset 16
+
+/* Register r_computed_crc, scope iop_scrc_in, type r */
+#define reg_iop_scrc_in_r_computed_crc_offset 20
+
+/* Register rw_crc, scope iop_scrc_in, type rw */
+#define reg_iop_scrc_in_rw_crc_offset 24
+
+/* Register rw_correct_crc, scope iop_scrc_in, type rw */
+#define reg_iop_scrc_in_rw_correct_crc_offset 28
+
+/* Register rw_wr1bit, scope iop_scrc_in, type rw */
+#define reg_iop_scrc_in_rw_wr1bit___data___lsb 0
+#define reg_iop_scrc_in_rw_wr1bit___data___width 2
+#define reg_iop_scrc_in_rw_wr1bit___last___lsb 2
+#define reg_iop_scrc_in_rw_wr1bit___last___width 2
+#define reg_iop_scrc_in_rw_wr1bit_offset 32
+
+
+/* Constants */
+#define regk_iop_scrc_in_dif_in                   0x00000002
+#define regk_iop_scrc_in_hi                       0x00000000
+#define regk_iop_scrc_in_neg                      0x00000002
+#define regk_iop_scrc_in_no                       0x00000000
+#define regk_iop_scrc_in_pos                      0x00000001
+#define regk_iop_scrc_in_pos_neg                  0x00000003
+#define regk_iop_scrc_in_r_computed_crc_default   0x00000000
+#define regk_iop_scrc_in_rs_computed_crc_default  0x00000000
+#define regk_iop_scrc_in_rw_cfg_default           0x00000000
+#define regk_iop_scrc_in_rw_ctrl_default          0x00000000
+#define regk_iop_scrc_in_rw_init_crc_default      0x00000000
+#define regk_iop_scrc_in_set0                     0x00000000
+#define regk_iop_scrc_in_set1                     0x00000001
+#define regk_iop_scrc_in_yes                      0x00000001
+#endif /* __iop_scrc_in_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h
new file mode 100644
index 00000000000..640a25725f2
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_scrc_out_defs_asm.h
@@ -0,0 +1,105 @@
+#ifndef __iop_scrc_out_defs_asm_h
+#define __iop_scrc_out_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_scrc_out.r
+ *     id:           iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_out_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_out.r
+ *      id: $Id: iop_scrc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope iop_scrc_out, type rw */
+#define reg_iop_scrc_out_rw_cfg___trig___lsb 0
+#define reg_iop_scrc_out_rw_cfg___trig___width 2
+#define reg_iop_scrc_out_rw_cfg___inv_crc___lsb 2
+#define reg_iop_scrc_out_rw_cfg___inv_crc___width 1
+#define reg_iop_scrc_out_rw_cfg___inv_crc___bit 2
+#define reg_iop_scrc_out_rw_cfg_offset 0
+
+/* Register rw_ctrl, scope iop_scrc_out, type rw */
+#define reg_iop_scrc_out_rw_ctrl___strb_src___lsb 0
+#define reg_iop_scrc_out_rw_ctrl___strb_src___width 1
+#define reg_iop_scrc_out_rw_ctrl___strb_src___bit 0
+#define reg_iop_scrc_out_rw_ctrl___out_src___lsb 1
+#define reg_iop_scrc_out_rw_ctrl___out_src___width 1
+#define reg_iop_scrc_out_rw_ctrl___out_src___bit 1
+#define reg_iop_scrc_out_rw_ctrl_offset 4
+
+/* Register rw_init_crc, scope iop_scrc_out, type rw */
+#define reg_iop_scrc_out_rw_init_crc_offset 8
+
+/* Register rw_crc, scope iop_scrc_out, type rw */
+#define reg_iop_scrc_out_rw_crc_offset 12
+
+/* Register rw_data, scope iop_scrc_out, type rw */
+#define reg_iop_scrc_out_rw_data___val___lsb 0
+#define reg_iop_scrc_out_rw_data___val___width 1
+#define reg_iop_scrc_out_rw_data___val___bit 0
+#define reg_iop_scrc_out_rw_data_offset 16
+
+/* Register r_computed_crc, scope iop_scrc_out, type r */
+#define reg_iop_scrc_out_r_computed_crc_offset 20
+
+
+/* Constants */
+#define regk_iop_scrc_out_crc                     0x00000001
+#define regk_iop_scrc_out_data                    0x00000000
+#define regk_iop_scrc_out_dif                     0x00000001
+#define regk_iop_scrc_out_hi                      0x00000000
+#define regk_iop_scrc_out_neg                     0x00000002
+#define regk_iop_scrc_out_no                      0x00000000
+#define regk_iop_scrc_out_pos                     0x00000001
+#define regk_iop_scrc_out_pos_neg                 0x00000003
+#define regk_iop_scrc_out_reg                     0x00000000
+#define regk_iop_scrc_out_rw_cfg_default          0x00000000
+#define regk_iop_scrc_out_rw_crc_default          0x00000000
+#define regk_iop_scrc_out_rw_ctrl_default         0x00000000
+#define regk_iop_scrc_out_rw_data_default         0x00000000
+#define regk_iop_scrc_out_rw_init_crc_default     0x00000000
+#define regk_iop_scrc_out_yes                     0x00000001
+#endif /* __iop_scrc_out_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h
new file mode 100644
index 00000000000..bb402c1aa76
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_spu_defs_asm.h
@@ -0,0 +1,573 @@
+#ifndef __iop_spu_defs_asm_h
+#define __iop_spu_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_spu.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_spu_defs_asm.h ../../inst/io_proc/rtl/iop_spu.r
+ *      id: $Id: iop_spu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+#define STRIDE_iop_spu_rw_r 4
+/* Register rw_r, scope iop_spu, type rw */
+#define reg_iop_spu_rw_r_offset 0
+
+/* Register rw_seq_pc, scope iop_spu, type rw */
+#define reg_iop_spu_rw_seq_pc___addr___lsb 0
+#define reg_iop_spu_rw_seq_pc___addr___width 12
+#define reg_iop_spu_rw_seq_pc_offset 64
+
+/* Register rw_fsm_pc, scope iop_spu, type rw */
+#define reg_iop_spu_rw_fsm_pc___addr___lsb 0
+#define reg_iop_spu_rw_fsm_pc___addr___width 12
+#define reg_iop_spu_rw_fsm_pc_offset 68
+
+/* Register rw_ctrl, scope iop_spu, type rw */
+#define reg_iop_spu_rw_ctrl___fsm___lsb 0
+#define reg_iop_spu_rw_ctrl___fsm___width 1
+#define reg_iop_spu_rw_ctrl___fsm___bit 0
+#define reg_iop_spu_rw_ctrl___en___lsb 1
+#define reg_iop_spu_rw_ctrl___en___width 1
+#define reg_iop_spu_rw_ctrl___en___bit 1
+#define reg_iop_spu_rw_ctrl_offset 72
+
+/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */
+#define reg_iop_spu_rw_fsm_inputs3_0___val0___lsb 0
+#define reg_iop_spu_rw_fsm_inputs3_0___val0___width 5
+#define reg_iop_spu_rw_fsm_inputs3_0___src0___lsb 5
+#define reg_iop_spu_rw_fsm_inputs3_0___src0___width 3
+#define reg_iop_spu_rw_fsm_inputs3_0___val1___lsb 8
+#define reg_iop_spu_rw_fsm_inputs3_0___val1___width 5
+#define reg_iop_spu_rw_fsm_inputs3_0___src1___lsb 13
+#define reg_iop_spu_rw_fsm_inputs3_0___src1___width 3
+#define reg_iop_spu_rw_fsm_inputs3_0___val2___lsb 16
+#define reg_iop_spu_rw_fsm_inputs3_0___val2___width 5
+#define reg_iop_spu_rw_fsm_inputs3_0___src2___lsb 21
+#define reg_iop_spu_rw_fsm_inputs3_0___src2___width 3
+#define reg_iop_spu_rw_fsm_inputs3_0___val3___lsb 24
+#define reg_iop_spu_rw_fsm_inputs3_0___val3___width 5
+#define reg_iop_spu_rw_fsm_inputs3_0___src3___lsb 29
+#define reg_iop_spu_rw_fsm_inputs3_0___src3___width 3
+#define reg_iop_spu_rw_fsm_inputs3_0_offset 76
+
+/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */
+#define reg_iop_spu_rw_fsm_inputs7_4___val4___lsb 0
+#define reg_iop_spu_rw_fsm_inputs7_4___val4___width 5
+#define reg_iop_spu_rw_fsm_inputs7_4___src4___lsb 5
+#define reg_iop_spu_rw_fsm_inputs7_4___src4___width 3
+#define reg_iop_spu_rw_fsm_inputs7_4___val5___lsb 8
+#define reg_iop_spu_rw_fsm_inputs7_4___val5___width 5
+#define reg_iop_spu_rw_fsm_inputs7_4___src5___lsb 13
+#define reg_iop_spu_rw_fsm_inputs7_4___src5___width 3
+#define reg_iop_spu_rw_fsm_inputs7_4___val6___lsb 16
+#define reg_iop_spu_rw_fsm_inputs7_4___val6___width 5
+#define reg_iop_spu_rw_fsm_inputs7_4___src6___lsb 21
+#define reg_iop_spu_rw_fsm_inputs7_4___src6___width 3
+#define reg_iop_spu_rw_fsm_inputs7_4___val7___lsb 24
+#define reg_iop_spu_rw_fsm_inputs7_4___val7___width 5
+#define reg_iop_spu_rw_fsm_inputs7_4___src7___lsb 29
+#define reg_iop_spu_rw_fsm_inputs7_4___src7___width 3
+#define reg_iop_spu_rw_fsm_inputs7_4_offset 80
+
+/* Register rw_gio_out, scope iop_spu, type rw */
+#define reg_iop_spu_rw_gio_out_offset 84
+
+/* Register rw_bus0_out, scope iop_spu, type rw */
+#define reg_iop_spu_rw_bus0_out_offset 88
+
+/* Register rw_bus1_out, scope iop_spu, type rw */
+#define reg_iop_spu_rw_bus1_out_offset 92
+
+/* Register r_gio_in, scope iop_spu, type r */
+#define reg_iop_spu_r_gio_in_offset 96
+
+/* Register r_bus0_in, scope iop_spu, type r */
+#define reg_iop_spu_r_bus0_in_offset 100
+
+/* Register r_bus1_in, scope iop_spu, type r */
+#define reg_iop_spu_r_bus1_in_offset 104
+
+/* Register rw_gio_out_set, scope iop_spu, type rw */
+#define reg_iop_spu_rw_gio_out_set_offset 108
+
+/* Register rw_gio_out_clr, scope iop_spu, type rw */
+#define reg_iop_spu_rw_gio_out_clr_offset 112
+
+/* Register rs_wr_stat, scope iop_spu, type rs */
+#define reg_iop_spu_rs_wr_stat___r0___lsb 0
+#define reg_iop_spu_rs_wr_stat___r0___width 1
+#define reg_iop_spu_rs_wr_stat___r0___bit 0
+#define reg_iop_spu_rs_wr_stat___r1___lsb 1
+#define reg_iop_spu_rs_wr_stat___r1___width 1
+#define reg_iop_spu_rs_wr_stat___r1___bit 1
+#define reg_iop_spu_rs_wr_stat___r2___lsb 2
+#define reg_iop_spu_rs_wr_stat___r2___width 1
+#define reg_iop_spu_rs_wr_stat___r2___bit 2
+#define reg_iop_spu_rs_wr_stat___r3___lsb 3
+#define reg_iop_spu_rs_wr_stat___r3___width 1
+#define reg_iop_spu_rs_wr_stat___r3___bit 3
+#define reg_iop_spu_rs_wr_stat___r4___lsb 4
+#define reg_iop_spu_rs_wr_stat___r4___width 1
+#define reg_iop_spu_rs_wr_stat___r4___bit 4
+#define reg_iop_spu_rs_wr_stat___r5___lsb 5
+#define reg_iop_spu_rs_wr_stat___r5___width 1
+#define reg_iop_spu_rs_wr_stat___r5___bit 5
+#define reg_iop_spu_rs_wr_stat___r6___lsb 6
+#define reg_iop_spu_rs_wr_stat___r6___width 1
+#define reg_iop_spu_rs_wr_stat___r6___bit 6
+#define reg_iop_spu_rs_wr_stat___r7___lsb 7
+#define reg_iop_spu_rs_wr_stat___r7___width 1
+#define reg_iop_spu_rs_wr_stat___r7___bit 7
+#define reg_iop_spu_rs_wr_stat___r8___lsb 8
+#define reg_iop_spu_rs_wr_stat___r8___width 1
+#define reg_iop_spu_rs_wr_stat___r8___bit 8
+#define reg_iop_spu_rs_wr_stat___r9___lsb 9
+#define reg_iop_spu_rs_wr_stat___r9___width 1
+#define reg_iop_spu_rs_wr_stat___r9___bit 9
+#define reg_iop_spu_rs_wr_stat___r10___lsb 10
+#define reg_iop_spu_rs_wr_stat___r10___width 1
+#define reg_iop_spu_rs_wr_stat___r10___bit 10
+#define reg_iop_spu_rs_wr_stat___r11___lsb 11
+#define reg_iop_spu_rs_wr_stat___r11___width 1
+#define reg_iop_spu_rs_wr_stat___r11___bit 11
+#define reg_iop_spu_rs_wr_stat___r12___lsb 12
+#define reg_iop_spu_rs_wr_stat___r12___width 1
+#define reg_iop_spu_rs_wr_stat___r12___bit 12
+#define reg_iop_spu_rs_wr_stat___r13___lsb 13
+#define reg_iop_spu_rs_wr_stat___r13___width 1
+#define reg_iop_spu_rs_wr_stat___r13___bit 13
+#define reg_iop_spu_rs_wr_stat___r14___lsb 14
+#define reg_iop_spu_rs_wr_stat___r14___width 1
+#define reg_iop_spu_rs_wr_stat___r14___bit 14
+#define reg_iop_spu_rs_wr_stat___r15___lsb 15
+#define reg_iop_spu_rs_wr_stat___r15___width 1
+#define reg_iop_spu_rs_wr_stat___r15___bit 15
+#define reg_iop_spu_rs_wr_stat_offset 116
+
+/* Register r_wr_stat, scope iop_spu, type r */
+#define reg_iop_spu_r_wr_stat___r0___lsb 0
+#define reg_iop_spu_r_wr_stat___r0___width 1
+#define reg_iop_spu_r_wr_stat___r0___bit 0
+#define reg_iop_spu_r_wr_stat___r1___lsb 1
+#define reg_iop_spu_r_wr_stat___r1___width 1
+#define reg_iop_spu_r_wr_stat___r1___bit 1
+#define reg_iop_spu_r_wr_stat___r2___lsb 2
+#define reg_iop_spu_r_wr_stat___r2___width 1
+#define reg_iop_spu_r_wr_stat___r2___bit 2
+#define reg_iop_spu_r_wr_stat___r3___lsb 3
+#define reg_iop_spu_r_wr_stat___r3___width 1
+#define reg_iop_spu_r_wr_stat___r3___bit 3
+#define reg_iop_spu_r_wr_stat___r4___lsb 4
+#define reg_iop_spu_r_wr_stat___r4___width 1
+#define reg_iop_spu_r_wr_stat___r4___bit 4
+#define reg_iop_spu_r_wr_stat___r5___lsb 5
+#define reg_iop_spu_r_wr_stat___r5___width 1
+#define reg_iop_spu_r_wr_stat___r5___bit 5
+#define reg_iop_spu_r_wr_stat___r6___lsb 6
+#define reg_iop_spu_r_wr_stat___r6___width 1
+#define reg_iop_spu_r_wr_stat___r6___bit 6
+#define reg_iop_spu_r_wr_stat___r7___lsb 7
+#define reg_iop_spu_r_wr_stat___r7___width 1
+#define reg_iop_spu_r_wr_stat___r7___bit 7
+#define reg_iop_spu_r_wr_stat___r8___lsb 8
+#define reg_iop_spu_r_wr_stat___r8___width 1
+#define reg_iop_spu_r_wr_stat___r8___bit 8
+#define reg_iop_spu_r_wr_stat___r9___lsb 9
+#define reg_iop_spu_r_wr_stat___r9___width 1
+#define reg_iop_spu_r_wr_stat___r9___bit 9
+#define reg_iop_spu_r_wr_stat___r10___lsb 10
+#define reg_iop_spu_r_wr_stat___r10___width 1
+#define reg_iop_spu_r_wr_stat___r10___bit 10
+#define reg_iop_spu_r_wr_stat___r11___lsb 11
+#define reg_iop_spu_r_wr_stat___r11___width 1
+#define reg_iop_spu_r_wr_stat___r11___bit 11
+#define reg_iop_spu_r_wr_stat___r12___lsb 12
+#define reg_iop_spu_r_wr_stat___r12___width 1
+#define reg_iop_spu_r_wr_stat___r12___bit 12
+#define reg_iop_spu_r_wr_stat___r13___lsb 13
+#define reg_iop_spu_r_wr_stat___r13___width 1
+#define reg_iop_spu_r_wr_stat___r13___bit 13
+#define reg_iop_spu_r_wr_stat___r14___lsb 14
+#define reg_iop_spu_r_wr_stat___r14___width 1
+#define reg_iop_spu_r_wr_stat___r14___bit 14
+#define reg_iop_spu_r_wr_stat___r15___lsb 15
+#define reg_iop_spu_r_wr_stat___r15___width 1
+#define reg_iop_spu_r_wr_stat___r15___bit 15
+#define reg_iop_spu_r_wr_stat_offset 120
+
+/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */
+#define reg_iop_spu_r_reg_indexed_by_bus0_in_offset 124
+
+/* Register r_stat_in, scope iop_spu, type r */
+#define reg_iop_spu_r_stat_in___timer_grp_lo___lsb 0
+#define reg_iop_spu_r_stat_in___timer_grp_lo___width 4
+#define reg_iop_spu_r_stat_in___fifo_out_last___lsb 4
+#define reg_iop_spu_r_stat_in___fifo_out_last___width 1
+#define reg_iop_spu_r_stat_in___fifo_out_last___bit 4
+#define reg_iop_spu_r_stat_in___fifo_out_rdy___lsb 5
+#define reg_iop_spu_r_stat_in___fifo_out_rdy___width 1
+#define reg_iop_spu_r_stat_in___fifo_out_rdy___bit 5
+#define reg_iop_spu_r_stat_in___fifo_out_all___lsb 6
+#define reg_iop_spu_r_stat_in___fifo_out_all___width 1
+#define reg_iop_spu_r_stat_in___fifo_out_all___bit 6
+#define reg_iop_spu_r_stat_in___fifo_in_rdy___lsb 7
+#define reg_iop_spu_r_stat_in___fifo_in_rdy___width 1
+#define reg_iop_spu_r_stat_in___fifo_in_rdy___bit 7
+#define reg_iop_spu_r_stat_in___dmc_out_all___lsb 8
+#define reg_iop_spu_r_stat_in___dmc_out_all___width 1
+#define reg_iop_spu_r_stat_in___dmc_out_all___bit 8
+#define reg_iop_spu_r_stat_in___dmc_out_dth___lsb 9
+#define reg_iop_spu_r_stat_in___dmc_out_dth___width 1
+#define reg_iop_spu_r_stat_in___dmc_out_dth___bit 9
+#define reg_iop_spu_r_stat_in___dmc_out_eop___lsb 10
+#define reg_iop_spu_r_stat_in___dmc_out_eop___width 1
+#define reg_iop_spu_r_stat_in___dmc_out_eop___bit 10
+#define reg_iop_spu_r_stat_in___dmc_out_dv___lsb 11
+#define reg_iop_spu_r_stat_in___dmc_out_dv___width 1
+#define reg_iop_spu_r_stat_in___dmc_out_dv___bit 11
+#define reg_iop_spu_r_stat_in___dmc_out_last___lsb 12
+#define reg_iop_spu_r_stat_in___dmc_out_last___width 1
+#define reg_iop_spu_r_stat_in___dmc_out_last___bit 12
+#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___lsb 13
+#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___width 1
+#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___bit 13
+#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___lsb 14
+#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___width 1
+#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___bit 14
+#define reg_iop_spu_r_stat_in___pcrc_correct___lsb 15
+#define reg_iop_spu_r_stat_in___pcrc_correct___width 1
+#define reg_iop_spu_r_stat_in___pcrc_correct___bit 15
+#define reg_iop_spu_r_stat_in___timer_grp_hi___lsb 16
+#define reg_iop_spu_r_stat_in___timer_grp_hi___width 4
+#define reg_iop_spu_r_stat_in___dmc_in_sth___lsb 20
+#define reg_iop_spu_r_stat_in___dmc_in_sth___width 1
+#define reg_iop_spu_r_stat_in___dmc_in_sth___bit 20
+#define reg_iop_spu_r_stat_in___dmc_in_full___lsb 21
+#define reg_iop_spu_r_stat_in___dmc_in_full___width 1
+#define reg_iop_spu_r_stat_in___dmc_in_full___bit 21
+#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___lsb 22
+#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___width 1
+#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___bit 22
+#define reg_iop_spu_r_stat_in___spu_gio_out___lsb 23
+#define reg_iop_spu_r_stat_in___spu_gio_out___width 4
+#define reg_iop_spu_r_stat_in___sync_clk12___lsb 27
+#define reg_iop_spu_r_stat_in___sync_clk12___width 1
+#define reg_iop_spu_r_stat_in___sync_clk12___bit 27
+#define reg_iop_spu_r_stat_in___scrc_out_data___lsb 28
+#define reg_iop_spu_r_stat_in___scrc_out_data___width 1
+#define reg_iop_spu_r_stat_in___scrc_out_data___bit 28
+#define reg_iop_spu_r_stat_in___scrc_in_err___lsb 29
+#define reg_iop_spu_r_stat_in___scrc_in_err___width 1
+#define reg_iop_spu_r_stat_in___scrc_in_err___bit 29
+#define reg_iop_spu_r_stat_in___mc_busy___lsb 30
+#define reg_iop_spu_r_stat_in___mc_busy___width 1
+#define reg_iop_spu_r_stat_in___mc_busy___bit 30
+#define reg_iop_spu_r_stat_in___mc_owned___lsb 31
+#define reg_iop_spu_r_stat_in___mc_owned___width 1
+#define reg_iop_spu_r_stat_in___mc_owned___bit 31
+#define reg_iop_spu_r_stat_in_offset 128
+
+/* Register r_trigger_in, scope iop_spu, type r */
+#define reg_iop_spu_r_trigger_in_offset 132
+
+/* Register r_special_stat, scope iop_spu, type r */
+#define reg_iop_spu_r_special_stat___c_flag___lsb 0
+#define reg_iop_spu_r_special_stat___c_flag___width 1
+#define reg_iop_spu_r_special_stat___c_flag___bit 0
+#define reg_iop_spu_r_special_stat___v_flag___lsb 1
+#define reg_iop_spu_r_special_stat___v_flag___width 1
+#define reg_iop_spu_r_special_stat___v_flag___bit 1
+#define reg_iop_spu_r_special_stat___z_flag___lsb 2
+#define reg_iop_spu_r_special_stat___z_flag___width 1
+#define reg_iop_spu_r_special_stat___z_flag___bit 2
+#define reg_iop_spu_r_special_stat___n_flag___lsb 3
+#define reg_iop_spu_r_special_stat___n_flag___width 1
+#define reg_iop_spu_r_special_stat___n_flag___bit 3
+#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___lsb 4
+#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___width 1
+#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___bit 4
+#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___lsb 5
+#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___width 1
+#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___bit 5
+#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___lsb 6
+#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___width 1
+#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___bit 6
+#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___lsb 7
+#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___width 1
+#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___bit 7
+#define reg_iop_spu_r_special_stat___fsm_in0___lsb 8
+#define reg_iop_spu_r_special_stat___fsm_in0___width 1
+#define reg_iop_spu_r_special_stat___fsm_in0___bit 8
+#define reg_iop_spu_r_special_stat___fsm_in1___lsb 9
+#define reg_iop_spu_r_special_stat___fsm_in1___width 1
+#define reg_iop_spu_r_special_stat___fsm_in1___bit 9
+#define reg_iop_spu_r_special_stat___fsm_in2___lsb 10
+#define reg_iop_spu_r_special_stat___fsm_in2___width 1
+#define reg_iop_spu_r_special_stat___fsm_in2___bit 10
+#define reg_iop_spu_r_special_stat___fsm_in3___lsb 11
+#define reg_iop_spu_r_special_stat___fsm_in3___width 1
+#define reg_iop_spu_r_special_stat___fsm_in3___bit 11
+#define reg_iop_spu_r_special_stat___fsm_in4___lsb 12
+#define reg_iop_spu_r_special_stat___fsm_in4___width 1
+#define reg_iop_spu_r_special_stat___fsm_in4___bit 12
+#define reg_iop_spu_r_special_stat___fsm_in5___lsb 13
+#define reg_iop_spu_r_special_stat___fsm_in5___width 1
+#define reg_iop_spu_r_special_stat___fsm_in5___bit 13
+#define reg_iop_spu_r_special_stat___fsm_in6___lsb 14
+#define reg_iop_spu_r_special_stat___fsm_in6___width 1
+#define reg_iop_spu_r_special_stat___fsm_in6___bit 14
+#define reg_iop_spu_r_special_stat___fsm_in7___lsb 15
+#define reg_iop_spu_r_special_stat___fsm_in7___width 1
+#define reg_iop_spu_r_special_stat___fsm_in7___bit 15
+#define reg_iop_spu_r_special_stat___event0___lsb 16
+#define reg_iop_spu_r_special_stat___event0___width 1
+#define reg_iop_spu_r_special_stat___event0___bit 16
+#define reg_iop_spu_r_special_stat___event1___lsb 17
+#define reg_iop_spu_r_special_stat___event1___width 1
+#define reg_iop_spu_r_special_stat___event1___bit 17
+#define reg_iop_spu_r_special_stat___event2___lsb 18
+#define reg_iop_spu_r_special_stat___event2___width 1
+#define reg_iop_spu_r_special_stat___event2___bit 18
+#define reg_iop_spu_r_special_stat___event3___lsb 19
+#define reg_iop_spu_r_special_stat___event3___width 1
+#define reg_iop_spu_r_special_stat___event3___bit 19
+#define reg_iop_spu_r_special_stat_offset 136
+
+/* Register rw_reg_access, scope iop_spu, type rw */
+#define reg_iop_spu_rw_reg_access___addr___lsb 0
+#define reg_iop_spu_rw_reg_access___addr___width 13
+#define reg_iop_spu_rw_reg_access___imm_hi___lsb 16
+#define reg_iop_spu_rw_reg_access___imm_hi___width 16
+#define reg_iop_spu_rw_reg_access_offset 140
+
+#define STRIDE_iop_spu_rw_event_cfg 4
+/* Register rw_event_cfg, scope iop_spu, type rw */
+#define reg_iop_spu_rw_event_cfg___addr___lsb 0
+#define reg_iop_spu_rw_event_cfg___addr___width 12
+#define reg_iop_spu_rw_event_cfg___src___lsb 12
+#define reg_iop_spu_rw_event_cfg___src___width 2
+#define reg_iop_spu_rw_event_cfg___eq_en___lsb 14
+#define reg_iop_spu_rw_event_cfg___eq_en___width 1
+#define reg_iop_spu_rw_event_cfg___eq_en___bit 14
+#define reg_iop_spu_rw_event_cfg___eq_inv___lsb 15
+#define reg_iop_spu_rw_event_cfg___eq_inv___width 1
+#define reg_iop_spu_rw_event_cfg___eq_inv___bit 15
+#define reg_iop_spu_rw_event_cfg___gt_en___lsb 16
+#define reg_iop_spu_rw_event_cfg___gt_en___width 1
+#define reg_iop_spu_rw_event_cfg___gt_en___bit 16
+#define reg_iop_spu_rw_event_cfg___gt_inv___lsb 17
+#define reg_iop_spu_rw_event_cfg___gt_inv___width 1
+#define reg_iop_spu_rw_event_cfg___gt_inv___bit 17
+#define reg_iop_spu_rw_event_cfg_offset 144
+
+#define STRIDE_iop_spu_rw_event_mask 4
+/* Register rw_event_mask, scope iop_spu, type rw */
+#define reg_iop_spu_rw_event_mask_offset 160
+
+#define STRIDE_iop_spu_rw_event_val 4
+/* Register rw_event_val, scope iop_spu, type rw */
+#define reg_iop_spu_rw_event_val_offset 176
+
+/* Register rw_event_ret, scope iop_spu, type rw */
+#define reg_iop_spu_rw_event_ret___addr___lsb 0
+#define reg_iop_spu_rw_event_ret___addr___width 12
+#define reg_iop_spu_rw_event_ret_offset 192
+
+/* Register r_trace, scope iop_spu, type r */
+#define reg_iop_spu_r_trace___fsm___lsb 0
+#define reg_iop_spu_r_trace___fsm___width 1
+#define reg_iop_spu_r_trace___fsm___bit 0
+#define reg_iop_spu_r_trace___en___lsb 1
+#define reg_iop_spu_r_trace___en___width 1
+#define reg_iop_spu_r_trace___en___bit 1
+#define reg_iop_spu_r_trace___c_flag___lsb 2
+#define reg_iop_spu_r_trace___c_flag___width 1
+#define reg_iop_spu_r_trace___c_flag___bit 2
+#define reg_iop_spu_r_trace___v_flag___lsb 3
+#define reg_iop_spu_r_trace___v_flag___width 1
+#define reg_iop_spu_r_trace___v_flag___bit 3
+#define reg_iop_spu_r_trace___z_flag___lsb 4
+#define reg_iop_spu_r_trace___z_flag___width 1
+#define reg_iop_spu_r_trace___z_flag___bit 4
+#define reg_iop_spu_r_trace___n_flag___lsb 5
+#define reg_iop_spu_r_trace___n_flag___width 1
+#define reg_iop_spu_r_trace___n_flag___bit 5
+#define reg_iop_spu_r_trace___seq_addr___lsb 6
+#define reg_iop_spu_r_trace___seq_addr___width 12
+#define reg_iop_spu_r_trace___fsm_addr___lsb 20
+#define reg_iop_spu_r_trace___fsm_addr___width 12
+#define reg_iop_spu_r_trace_offset 196
+
+/* Register r_fsm_trace, scope iop_spu, type r */
+#define reg_iop_spu_r_fsm_trace___fsm___lsb 0
+#define reg_iop_spu_r_fsm_trace___fsm___width 1
+#define reg_iop_spu_r_fsm_trace___fsm___bit 0
+#define reg_iop_spu_r_fsm_trace___en___lsb 1
+#define reg_iop_spu_r_fsm_trace___en___width 1
+#define reg_iop_spu_r_fsm_trace___en___bit 1
+#define reg_iop_spu_r_fsm_trace___tmr_done___lsb 2
+#define reg_iop_spu_r_fsm_trace___tmr_done___width 1
+#define reg_iop_spu_r_fsm_trace___tmr_done___bit 2
+#define reg_iop_spu_r_fsm_trace___inp0___lsb 3
+#define reg_iop_spu_r_fsm_trace___inp0___width 1
+#define reg_iop_spu_r_fsm_trace___inp0___bit 3
+#define reg_iop_spu_r_fsm_trace___inp1___lsb 4
+#define reg_iop_spu_r_fsm_trace___inp1___width 1
+#define reg_iop_spu_r_fsm_trace___inp1___bit 4
+#define reg_iop_spu_r_fsm_trace___inp2___lsb 5
+#define reg_iop_spu_r_fsm_trace___inp2___width 1
+#define reg_iop_spu_r_fsm_trace___inp2___bit 5
+#define reg_iop_spu_r_fsm_trace___inp3___lsb 6
+#define reg_iop_spu_r_fsm_trace___inp3___width 1
+#define reg_iop_spu_r_fsm_trace___inp3___bit 6
+#define reg_iop_spu_r_fsm_trace___event0___lsb 7
+#define reg_iop_spu_r_fsm_trace___event0___width 1
+#define reg_iop_spu_r_fsm_trace___event0___bit 7
+#define reg_iop_spu_r_fsm_trace___event1___lsb 8
+#define reg_iop_spu_r_fsm_trace___event1___width 1
+#define reg_iop_spu_r_fsm_trace___event1___bit 8
+#define reg_iop_spu_r_fsm_trace___event2___lsb 9
+#define reg_iop_spu_r_fsm_trace___event2___width 1
+#define reg_iop_spu_r_fsm_trace___event2___bit 9
+#define reg_iop_spu_r_fsm_trace___event3___lsb 10
+#define reg_iop_spu_r_fsm_trace___event3___width 1
+#define reg_iop_spu_r_fsm_trace___event3___bit 10
+#define reg_iop_spu_r_fsm_trace___gio_out___lsb 11
+#define reg_iop_spu_r_fsm_trace___gio_out___width 8
+#define reg_iop_spu_r_fsm_trace___fsm_addr___lsb 20
+#define reg_iop_spu_r_fsm_trace___fsm_addr___width 12
+#define reg_iop_spu_r_fsm_trace_offset 200
+
+#define STRIDE_iop_spu_rw_brp 4
+/* Register rw_brp, scope iop_spu, type rw */
+#define reg_iop_spu_rw_brp___addr___lsb 0
+#define reg_iop_spu_rw_brp___addr___width 12
+#define reg_iop_spu_rw_brp___fsm___lsb 12
+#define reg_iop_spu_rw_brp___fsm___width 1
+#define reg_iop_spu_rw_brp___fsm___bit 12
+#define reg_iop_spu_rw_brp___en___lsb 13
+#define reg_iop_spu_rw_brp___en___width 1
+#define reg_iop_spu_rw_brp___en___bit 13
+#define reg_iop_spu_rw_brp_offset 204
+
+
+/* Constants */
+#define regk_iop_spu_attn_hi                      0x00000005
+#define regk_iop_spu_attn_lo                      0x00000005
+#define regk_iop_spu_attn_r0                      0x00000000
+#define regk_iop_spu_attn_r1                      0x00000001
+#define regk_iop_spu_attn_r10                     0x00000002
+#define regk_iop_spu_attn_r11                     0x00000003
+#define regk_iop_spu_attn_r12                     0x00000004
+#define regk_iop_spu_attn_r13                     0x00000005
+#define regk_iop_spu_attn_r14                     0x00000006
+#define regk_iop_spu_attn_r15                     0x00000007
+#define regk_iop_spu_attn_r2                      0x00000002
+#define regk_iop_spu_attn_r3                      0x00000003
+#define regk_iop_spu_attn_r4                      0x00000004
+#define regk_iop_spu_attn_r5                      0x00000005
+#define regk_iop_spu_attn_r6                      0x00000006
+#define regk_iop_spu_attn_r7                      0x00000007
+#define regk_iop_spu_attn_r8                      0x00000000
+#define regk_iop_spu_attn_r9                      0x00000001
+#define regk_iop_spu_c                            0x00000000
+#define regk_iop_spu_flag                         0x00000002
+#define regk_iop_spu_gio_in                       0x00000000
+#define regk_iop_spu_gio_out                      0x00000005
+#define regk_iop_spu_gio_out0                     0x00000008
+#define regk_iop_spu_gio_out1                     0x00000009
+#define regk_iop_spu_gio_out2                     0x0000000a
+#define regk_iop_spu_gio_out3                     0x0000000b
+#define regk_iop_spu_gio_out4                     0x0000000c
+#define regk_iop_spu_gio_out5                     0x0000000d
+#define regk_iop_spu_gio_out6                     0x0000000e
+#define regk_iop_spu_gio_out7                     0x0000000f
+#define regk_iop_spu_n                            0x00000003
+#define regk_iop_spu_no                           0x00000000
+#define regk_iop_spu_r0                           0x00000008
+#define regk_iop_spu_r1                           0x00000009
+#define regk_iop_spu_r10                          0x0000000a
+#define regk_iop_spu_r11                          0x0000000b
+#define regk_iop_spu_r12                          0x0000000c
+#define regk_iop_spu_r13                          0x0000000d
+#define regk_iop_spu_r14                          0x0000000e
+#define regk_iop_spu_r15                          0x0000000f
+#define regk_iop_spu_r2                           0x0000000a
+#define regk_iop_spu_r3                           0x0000000b
+#define regk_iop_spu_r4                           0x0000000c
+#define regk_iop_spu_r5                           0x0000000d
+#define regk_iop_spu_r6                           0x0000000e
+#define regk_iop_spu_r7                           0x0000000f
+#define regk_iop_spu_r8                           0x00000008
+#define regk_iop_spu_r9                           0x00000009
+#define regk_iop_spu_reg_hi                       0x00000002
+#define regk_iop_spu_reg_lo                       0x00000002
+#define regk_iop_spu_rw_brp_default               0x00000000
+#define regk_iop_spu_rw_brp_size                  0x00000004
+#define regk_iop_spu_rw_ctrl_default              0x00000000
+#define regk_iop_spu_rw_event_cfg_size            0x00000004
+#define regk_iop_spu_rw_event_mask_size           0x00000004
+#define regk_iop_spu_rw_event_val_size            0x00000004
+#define regk_iop_spu_rw_gio_out_default           0x00000000
+#define regk_iop_spu_rw_r_size                    0x00000010
+#define regk_iop_spu_rw_reg_access_default        0x00000000
+#define regk_iop_spu_stat_in                      0x00000002
+#define regk_iop_spu_statin_hi                    0x00000004
+#define regk_iop_spu_statin_lo                    0x00000004
+#define regk_iop_spu_trig                         0x00000003
+#define regk_iop_spu_trigger                      0x00000006
+#define regk_iop_spu_v                            0x00000001
+#define regk_iop_spu_wsts_gioout_spec             0x00000001
+#define regk_iop_spu_xor                          0x00000003
+#define regk_iop_spu_xor_bus0_r2_0                0x00000000
+#define regk_iop_spu_xor_bus0m_r2_0               0x00000002
+#define regk_iop_spu_xor_bus1_r3_0                0x00000001
+#define regk_iop_spu_xor_bus1m_r3_0               0x00000003
+#define regk_iop_spu_yes                          0x00000001
+#define regk_iop_spu_z                            0x00000002
+#endif /* __iop_spu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
new file mode 100644
index 00000000000..3be60f9b024
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
@@ -0,0 +1,1052 @@
+#ifndef __iop_sw_cfg_defs_asm_h
+#define __iop_sw_cfg_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:19 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cfg_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
+ *      id: $Id: iop_sw_cfg_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_crc_par0_owner_offset 0
+
+/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_crc_par1_owner_offset 4
+
+/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_dmc_in0_owner_offset 8
+
+/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_dmc_in1_owner_offset 12
+
+/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_dmc_out0_owner_offset 16
+
+/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_dmc_out1_owner_offset 20
+
+/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_fifo_in0_owner_offset 24
+
+/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner_offset 28
+
+/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_fifo_in1_owner_offset 32
+
+/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner_offset 36
+
+/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_fifo_out0_owner_offset 40
+
+/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner_offset 44
+
+/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_fifo_out1_owner_offset 48
+
+/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner_offset 52
+
+/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_sap_in_owner_offset 56
+
+/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_sap_out_owner_offset 60
+
+/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_scrc_in0_owner_offset 64
+
+/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_scrc_in1_owner_offset 68
+
+/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_scrc_out0_owner_offset 72
+
+/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_scrc_out1_owner_offset 76
+
+/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_spu0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_spu0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_spu0_owner_offset 80
+
+/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_spu1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_spu1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_spu1_owner_offset 84
+
+/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 88
+
+/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 92
+
+/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_timer_grp2_owner_offset 96
+
+/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_timer_grp3_owner_offset 100
+
+/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 104
+
+/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 108
+
+/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 112
+
+/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 116
+
+/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 120
+
+/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 124
+
+/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 128
+
+/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 132
+
+/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_bus0_mask___byte0___lsb 0
+#define reg_iop_sw_cfg_rw_bus0_mask___byte0___width 8
+#define reg_iop_sw_cfg_rw_bus0_mask___byte1___lsb 8
+#define reg_iop_sw_cfg_rw_bus0_mask___byte1___width 8
+#define reg_iop_sw_cfg_rw_bus0_mask___byte2___lsb 16
+#define reg_iop_sw_cfg_rw_bus0_mask___byte2___width 8
+#define reg_iop_sw_cfg_rw_bus0_mask___byte3___lsb 24
+#define reg_iop_sw_cfg_rw_bus0_mask___byte3___width 8
+#define reg_iop_sw_cfg_rw_bus0_mask_offset 136
+
+/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___lsb 0
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___width 1
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___bit 0
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___lsb 1
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___width 1
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___bit 1
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___lsb 2
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___width 1
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___bit 2
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___lsb 3
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___width 1
+#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___bit 3
+#define reg_iop_sw_cfg_rw_bus0_oe_mask_offset 140
+
+/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_bus1_mask___byte0___lsb 0
+#define reg_iop_sw_cfg_rw_bus1_mask___byte0___width 8
+#define reg_iop_sw_cfg_rw_bus1_mask___byte1___lsb 8
+#define reg_iop_sw_cfg_rw_bus1_mask___byte1___width 8
+#define reg_iop_sw_cfg_rw_bus1_mask___byte2___lsb 16
+#define reg_iop_sw_cfg_rw_bus1_mask___byte2___width 8
+#define reg_iop_sw_cfg_rw_bus1_mask___byte3___lsb 24
+#define reg_iop_sw_cfg_rw_bus1_mask___byte3___width 8
+#define reg_iop_sw_cfg_rw_bus1_mask_offset 144
+
+/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___lsb 0
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___width 1
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___bit 0
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___lsb 1
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___width 1
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___bit 1
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___lsb 2
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___width 1
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___bit 2
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___lsb 3
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___width 1
+#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___bit 3
+#define reg_iop_sw_cfg_rw_bus1_oe_mask_offset 148
+
+/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0
+#define reg_iop_sw_cfg_rw_gio_mask___val___width 32
+#define reg_iop_sw_cfg_rw_gio_mask_offset 152
+
+/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0
+#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32
+#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 156
+
+/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___lsb 0
+#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___lsb 2
+#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___lsb 4
+#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___lsb 6
+#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___lsb 8
+#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___lsb 10
+#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___lsb 12
+#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___lsb 14
+#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 16
+#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 18
+#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 20
+#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 22
+#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 24
+#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 26
+#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 28
+#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 30
+#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2
+#define reg_iop_sw_cfg_rw_pinmapping_offset 160
+
+/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___lsb 0
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___width 3
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___lsb 3
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___width 3
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___lsb 6
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___width 3
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___lsb 9
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___width 3
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___lsb 12
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___width 3
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___lsb 15
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___width 3
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___lsb 18
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___width 3
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___lsb 21
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___width 3
+#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 164
+
+/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 6
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 10
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 16
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 18
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 22
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 168
+
+/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 6
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 10
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 16
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 18
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 22
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 172
+
+/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 6
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 10
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 16
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 18
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 22
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 176
+
+/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 6
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 10
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 16
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 18
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 22
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 180
+
+/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 6
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 10
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 16
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 18
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 22
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 184
+
+/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 6
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 10
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 16
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 18
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 22
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 188
+
+/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 6
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 10
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 16
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 18
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 22
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 192
+
+/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 6
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 10
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 16
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 18
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 4
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 22
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 2
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 196
+
+/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___lsb 0
+#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___width 2
+#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___lsb 2
+#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___width 2
+#define reg_iop_sw_cfg_rw_spu0_cfg_offset 200
+
+/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___lsb 0
+#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___width 2
+#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___lsb 2
+#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___width 2
+#define reg_iop_sw_cfg_rw_spu1_cfg_offset 204
+
+/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___bit 3
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 4
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___bit 4
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 5
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___bit 5
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 6
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___bit 6
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 7
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___bit 7
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 8
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___bit 8
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 9
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___bit 9
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 10
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___bit 10
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 208
+
+/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___bit 3
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 4
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___bit 4
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 5
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___bit 5
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 6
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___bit 6
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 7
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___bit 7
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 8
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___bit 8
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 9
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___bit 9
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 10
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___bit 10
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 212
+
+/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___lsb 0
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___width 3
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___lsb 3
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___bit 3
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___lsb 4
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___bit 4
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___lsb 5
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___bit 5
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___lsb 6
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___bit 6
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___lsb 7
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___bit 7
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___lsb 8
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___bit 8
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___lsb 9
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___bit 9
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___lsb 10
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___bit 10
+#define reg_iop_sw_cfg_rw_timer_grp2_cfg_offset 216
+
+/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___lsb 0
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___width 3
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___lsb 3
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___bit 3
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___lsb 4
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___bit 4
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___lsb 5
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___bit 5
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___lsb 6
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___width 1
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___bit 6
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___lsb 7
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___bit 7
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___lsb 8
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___bit 8
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___lsb 9
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___bit 9
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___lsb 10
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___width 1
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___bit 10
+#define reg_iop_sw_cfg_rw_timer_grp3_cfg_offset 220
+
+/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 224
+
+/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___lsb 0
+#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___width 1
+#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___bit 0
+#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___lsb 1
+#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___width 5
+#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___lsb 6
+#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___width 3
+#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___lsb 9
+#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___width 3
+#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___lsb 12
+#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___width 2
+#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___lsb 14
+#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___width 4
+#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___lsb 18
+#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___width 1
+#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___bit 18
+#define reg_iop_sw_cfg_rw_pdp0_cfg_offset 228
+
+/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___lsb 0
+#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___width 1
+#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___bit 0
+#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___lsb 1
+#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___width 5
+#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___lsb 6
+#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___width 3
+#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___lsb 9
+#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___width 3
+#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___lsb 12
+#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___width 2
+#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___lsb 14
+#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___width 4
+#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___lsb 18
+#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___width 1
+#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___bit 18
+#define reg_iop_sw_cfg_rw_pdp1_cfg_offset 232
+
+/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___lsb 0
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___width 3
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___lsb 3
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___width 3
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___lsb 6
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___width 3
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___lsb 9
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___width 2
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___lsb 11
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___width 3
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___lsb 14
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___width 3
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___lsb 17
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___width 2
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___lsb 19
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___width 3
+#define reg_iop_sw_cfg_rw_sdp_cfg_offset 236
+
+
+/* Constants */
+#define regk_iop_sw_cfg_a                         0x00000001
+#define regk_iop_sw_cfg_b                         0x00000002
+#define regk_iop_sw_cfg_bus0                      0x00000000
+#define regk_iop_sw_cfg_bus0_rot16                0x00000004
+#define regk_iop_sw_cfg_bus0_rot24                0x00000006
+#define regk_iop_sw_cfg_bus0_rot8                 0x00000002
+#define regk_iop_sw_cfg_bus1                      0x00000001
+#define regk_iop_sw_cfg_bus1_rot16                0x00000005
+#define regk_iop_sw_cfg_bus1_rot24                0x00000007
+#define regk_iop_sw_cfg_bus1_rot8                 0x00000003
+#define regk_iop_sw_cfg_clk12                     0x00000000
+#define regk_iop_sw_cfg_cpu                       0x00000000
+#define regk_iop_sw_cfg_dmc0                      0x00000000
+#define regk_iop_sw_cfg_dmc1                      0x00000001
+#define regk_iop_sw_cfg_gated_clk0                0x00000010
+#define regk_iop_sw_cfg_gated_clk1                0x00000011
+#define regk_iop_sw_cfg_gated_clk2                0x00000012
+#define regk_iop_sw_cfg_gated_clk3                0x00000013
+#define regk_iop_sw_cfg_gio0                      0x00000004
+#define regk_iop_sw_cfg_gio1                      0x00000001
+#define regk_iop_sw_cfg_gio2                      0x00000005
+#define regk_iop_sw_cfg_gio3                      0x00000002
+#define regk_iop_sw_cfg_gio4                      0x00000006
+#define regk_iop_sw_cfg_gio5                      0x00000003
+#define regk_iop_sw_cfg_gio6                      0x00000007
+#define regk_iop_sw_cfg_gio7                      0x00000004
+#define regk_iop_sw_cfg_gio_in0                   0x00000000
+#define regk_iop_sw_cfg_gio_in1                   0x00000001
+#define regk_iop_sw_cfg_gio_in10                  0x00000002
+#define regk_iop_sw_cfg_gio_in11                  0x00000003
+#define regk_iop_sw_cfg_gio_in14                  0x00000004
+#define regk_iop_sw_cfg_gio_in15                  0x00000005
+#define regk_iop_sw_cfg_gio_in18                  0x00000002
+#define regk_iop_sw_cfg_gio_in19                  0x00000003
+#define regk_iop_sw_cfg_gio_in20                  0x00000004
+#define regk_iop_sw_cfg_gio_in21                  0x00000005
+#define regk_iop_sw_cfg_gio_in26                  0x00000006
+#define regk_iop_sw_cfg_gio_in27                  0x00000007
+#define regk_iop_sw_cfg_gio_in28                  0x00000006
+#define regk_iop_sw_cfg_gio_in29                  0x00000007
+#define regk_iop_sw_cfg_gio_in4                   0x00000000
+#define regk_iop_sw_cfg_gio_in5                   0x00000001
+#define regk_iop_sw_cfg_last_timer_grp0_tmr2      0x00000001
+#define regk_iop_sw_cfg_last_timer_grp1_tmr2      0x00000001
+#define regk_iop_sw_cfg_last_timer_grp2_tmr2      0x00000002
+#define regk_iop_sw_cfg_last_timer_grp2_tmr3      0x00000003
+#define regk_iop_sw_cfg_last_timer_grp3_tmr2      0x00000002
+#define regk_iop_sw_cfg_last_timer_grp3_tmr3      0x00000003
+#define regk_iop_sw_cfg_mpu                       0x00000001
+#define regk_iop_sw_cfg_none                      0x00000000
+#define regk_iop_sw_cfg_par0                      0x00000000
+#define regk_iop_sw_cfg_par1                      0x00000001
+#define regk_iop_sw_cfg_pdp_out0                  0x00000002
+#define regk_iop_sw_cfg_pdp_out0_hi               0x00000001
+#define regk_iop_sw_cfg_pdp_out0_hi_rot8          0x00000005
+#define regk_iop_sw_cfg_pdp_out0_lo               0x00000000
+#define regk_iop_sw_cfg_pdp_out0_lo_rot8          0x00000004
+#define regk_iop_sw_cfg_pdp_out1                  0x00000003
+#define regk_iop_sw_cfg_pdp_out1_hi               0x00000003
+#define regk_iop_sw_cfg_pdp_out1_hi_rot8          0x00000005
+#define regk_iop_sw_cfg_pdp_out1_lo               0x00000002
+#define regk_iop_sw_cfg_pdp_out1_lo_rot8          0x00000004
+#define regk_iop_sw_cfg_rw_bus0_mask_default      0x00000000
+#define regk_iop_sw_cfg_rw_bus0_oe_mask_default   0x00000000
+#define regk_iop_sw_cfg_rw_bus1_mask_default      0x00000000
+#define regk_iop_sw_cfg_rw_bus1_oe_mask_default   0x00000000
+#define regk_iop_sw_cfg_rw_bus_out_cfg_default    0x00000000
+#define regk_iop_sw_cfg_rw_crc_par0_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_crc_par1_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_dmc_in0_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_dmc_in1_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_dmc_out0_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_dmc_out1_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_fifo_in0_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_fifo_in1_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_fifo_out0_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_fifo_out1_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_gio_mask_default       0x00000000
+#define regk_iop_sw_cfg_rw_gio_oe_mask_default    0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_pdp0_cfg_default       0x00000000
+#define regk_iop_sw_cfg_rw_pdp1_cfg_default       0x00000000
+#define regk_iop_sw_cfg_rw_pinmapping_default     0x55555555
+#define regk_iop_sw_cfg_rw_sap_in_owner_default   0x00000000
+#define regk_iop_sw_cfg_rw_sap_out_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_scrc_in0_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_scrc_in1_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_scrc_out0_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_scrc_out1_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_sdp_cfg_default        0x00000000
+#define regk_iop_sw_cfg_rw_spu0_cfg_default       0x00000000
+#define regk_iop_sw_cfg_rw_spu0_owner_default     0x00000000
+#define regk_iop_sw_cfg_rw_spu1_cfg_default       0x00000000
+#define regk_iop_sw_cfg_rw_spu1_owner_default     0x00000000
+#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_timer_grp0_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_timer_grp1_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_timer_grp2_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_timer_grp2_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_timer_grp3_cfg_default  0x00000000
+#define regk_iop_sw_cfg_rw_timer_grp3_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default  0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default  0x00000000
+#define regk_iop_sw_cfg_sdp_out0                  0x00000008
+#define regk_iop_sw_cfg_sdp_out1                  0x00000009
+#define regk_iop_sw_cfg_size16                    0x00000002
+#define regk_iop_sw_cfg_size24                    0x00000003
+#define regk_iop_sw_cfg_size32                    0x00000004
+#define regk_iop_sw_cfg_size8                     0x00000001
+#define regk_iop_sw_cfg_spu0                      0x00000002
+#define regk_iop_sw_cfg_spu0_bus_out0_hi          0x00000006
+#define regk_iop_sw_cfg_spu0_bus_out0_lo          0x00000006
+#define regk_iop_sw_cfg_spu0_bus_out1_hi          0x00000007
+#define regk_iop_sw_cfg_spu0_bus_out1_lo          0x00000007
+#define regk_iop_sw_cfg_spu0_g0                   0x0000000e
+#define regk_iop_sw_cfg_spu0_g1                   0x0000000e
+#define regk_iop_sw_cfg_spu0_g2                   0x0000000e
+#define regk_iop_sw_cfg_spu0_g3                   0x0000000e
+#define regk_iop_sw_cfg_spu0_g4                   0x0000000e
+#define regk_iop_sw_cfg_spu0_g5                   0x0000000e
+#define regk_iop_sw_cfg_spu0_g6                   0x0000000e
+#define regk_iop_sw_cfg_spu0_g7                   0x0000000e
+#define regk_iop_sw_cfg_spu0_gio0                 0x00000000
+#define regk_iop_sw_cfg_spu0_gio1                 0x00000001
+#define regk_iop_sw_cfg_spu0_gio2                 0x00000000
+#define regk_iop_sw_cfg_spu0_gio5                 0x00000005
+#define regk_iop_sw_cfg_spu0_gio6                 0x00000006
+#define regk_iop_sw_cfg_spu0_gio7                 0x00000007
+#define regk_iop_sw_cfg_spu0_gio_out0             0x00000008
+#define regk_iop_sw_cfg_spu0_gio_out1             0x00000009
+#define regk_iop_sw_cfg_spu0_gio_out2             0x0000000a
+#define regk_iop_sw_cfg_spu0_gio_out3             0x0000000b
+#define regk_iop_sw_cfg_spu0_gio_out4             0x0000000c
+#define regk_iop_sw_cfg_spu0_gio_out5             0x0000000d
+#define regk_iop_sw_cfg_spu0_gio_out6             0x0000000e
+#define regk_iop_sw_cfg_spu0_gio_out7             0x0000000f
+#define regk_iop_sw_cfg_spu0_gioout0              0x00000000
+#define regk_iop_sw_cfg_spu0_gioout1              0x00000000
+#define regk_iop_sw_cfg_spu0_gioout10             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout11             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout12             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout13             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout14             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout15             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout16             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout17             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout18             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout19             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout2              0x00000002
+#define regk_iop_sw_cfg_spu0_gioout20             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout21             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout22             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout23             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout24             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout25             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout26             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout27             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout28             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout29             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout3              0x00000002
+#define regk_iop_sw_cfg_spu0_gioout30             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout31             0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout4              0x00000004
+#define regk_iop_sw_cfg_spu0_gioout5              0x00000004
+#define regk_iop_sw_cfg_spu0_gioout6              0x00000006
+#define regk_iop_sw_cfg_spu0_gioout7              0x00000006
+#define regk_iop_sw_cfg_spu0_gioout8              0x0000000e
+#define regk_iop_sw_cfg_spu0_gioout9              0x0000000e
+#define regk_iop_sw_cfg_spu1                      0x00000003
+#define regk_iop_sw_cfg_spu1_bus_out0_hi          0x00000006
+#define regk_iop_sw_cfg_spu1_bus_out0_lo          0x00000006
+#define regk_iop_sw_cfg_spu1_bus_out1_hi          0x00000007
+#define regk_iop_sw_cfg_spu1_bus_out1_lo          0x00000007
+#define regk_iop_sw_cfg_spu1_g0                   0x0000000f
+#define regk_iop_sw_cfg_spu1_g1                   0x0000000f
+#define regk_iop_sw_cfg_spu1_g2                   0x0000000f
+#define regk_iop_sw_cfg_spu1_g3                   0x0000000f
+#define regk_iop_sw_cfg_spu1_g4                   0x0000000f
+#define regk_iop_sw_cfg_spu1_g5                   0x0000000f
+#define regk_iop_sw_cfg_spu1_g6                   0x0000000f
+#define regk_iop_sw_cfg_spu1_g7                   0x0000000f
+#define regk_iop_sw_cfg_spu1_gio0                 0x00000002
+#define regk_iop_sw_cfg_spu1_gio1                 0x00000003
+#define regk_iop_sw_cfg_spu1_gio2                 0x00000002
+#define regk_iop_sw_cfg_spu1_gio5                 0x00000005
+#define regk_iop_sw_cfg_spu1_gio6                 0x00000006
+#define regk_iop_sw_cfg_spu1_gio7                 0x00000007
+#define regk_iop_sw_cfg_spu1_gio_out0             0x00000008
+#define regk_iop_sw_cfg_spu1_gio_out1             0x00000009
+#define regk_iop_sw_cfg_spu1_gio_out2             0x0000000a
+#define regk_iop_sw_cfg_spu1_gio_out3             0x0000000b
+#define regk_iop_sw_cfg_spu1_gio_out4             0x0000000c
+#define regk_iop_sw_cfg_spu1_gio_out5             0x0000000d
+#define regk_iop_sw_cfg_spu1_gio_out6             0x0000000e
+#define regk_iop_sw_cfg_spu1_gio_out7             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout0              0x00000001
+#define regk_iop_sw_cfg_spu1_gioout1              0x00000001
+#define regk_iop_sw_cfg_spu1_gioout10             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout11             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout12             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout13             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout14             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout15             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout16             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout17             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout18             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout19             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout2              0x00000003
+#define regk_iop_sw_cfg_spu1_gioout20             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout21             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout22             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout23             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout24             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout25             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout26             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout27             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout28             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout29             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout3              0x00000003
+#define regk_iop_sw_cfg_spu1_gioout30             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout31             0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout4              0x00000005
+#define regk_iop_sw_cfg_spu1_gioout5              0x00000005
+#define regk_iop_sw_cfg_spu1_gioout6              0x00000007
+#define regk_iop_sw_cfg_spu1_gioout7              0x00000007
+#define regk_iop_sw_cfg_spu1_gioout8              0x0000000f
+#define regk_iop_sw_cfg_spu1_gioout9              0x0000000f
+#define regk_iop_sw_cfg_strb_timer_grp0_tmr0      0x00000001
+#define regk_iop_sw_cfg_strb_timer_grp0_tmr1      0x00000002
+#define regk_iop_sw_cfg_strb_timer_grp1_tmr0      0x00000001
+#define regk_iop_sw_cfg_strb_timer_grp1_tmr1      0x00000002
+#define regk_iop_sw_cfg_strb_timer_grp2_tmr0      0x00000003
+#define regk_iop_sw_cfg_strb_timer_grp2_tmr1      0x00000002
+#define regk_iop_sw_cfg_strb_timer_grp3_tmr0      0x00000003
+#define regk_iop_sw_cfg_strb_timer_grp3_tmr1      0x00000002
+#define regk_iop_sw_cfg_timer_grp0                0x00000000
+#define regk_iop_sw_cfg_timer_grp0_rot            0x00000001
+#define regk_iop_sw_cfg_timer_grp0_strb0          0x0000000a
+#define regk_iop_sw_cfg_timer_grp0_strb1          0x0000000a
+#define regk_iop_sw_cfg_timer_grp0_strb2          0x0000000a
+#define regk_iop_sw_cfg_timer_grp0_strb3          0x0000000a
+#define regk_iop_sw_cfg_timer_grp0_tmr0           0x00000004
+#define regk_iop_sw_cfg_timer_grp0_tmr1           0x00000004
+#define regk_iop_sw_cfg_timer_grp1                0x00000000
+#define regk_iop_sw_cfg_timer_grp1_rot            0x00000001
+#define regk_iop_sw_cfg_timer_grp1_strb0          0x0000000b
+#define regk_iop_sw_cfg_timer_grp1_strb1          0x0000000b
+#define regk_iop_sw_cfg_timer_grp1_strb2          0x0000000b
+#define regk_iop_sw_cfg_timer_grp1_strb3          0x0000000b
+#define regk_iop_sw_cfg_timer_grp1_tmr0           0x00000005
+#define regk_iop_sw_cfg_timer_grp1_tmr1           0x00000005
+#define regk_iop_sw_cfg_timer_grp2                0x00000000
+#define regk_iop_sw_cfg_timer_grp2_rot            0x00000001
+#define regk_iop_sw_cfg_timer_grp2_strb0          0x0000000c
+#define regk_iop_sw_cfg_timer_grp2_strb1          0x0000000c
+#define regk_iop_sw_cfg_timer_grp2_strb2          0x0000000c
+#define regk_iop_sw_cfg_timer_grp2_strb3          0x0000000c
+#define regk_iop_sw_cfg_timer_grp2_tmr0           0x00000006
+#define regk_iop_sw_cfg_timer_grp2_tmr1           0x00000006
+#define regk_iop_sw_cfg_timer_grp3                0x00000000
+#define regk_iop_sw_cfg_timer_grp3_rot            0x00000001
+#define regk_iop_sw_cfg_timer_grp3_strb0          0x0000000d
+#define regk_iop_sw_cfg_timer_grp3_strb1          0x0000000d
+#define regk_iop_sw_cfg_timer_grp3_strb2          0x0000000d
+#define regk_iop_sw_cfg_timer_grp3_strb3          0x0000000d
+#define regk_iop_sw_cfg_timer_grp3_tmr0           0x00000007
+#define regk_iop_sw_cfg_timer_grp3_tmr1           0x00000007
+#define regk_iop_sw_cfg_trig0_0                   0x00000000
+#define regk_iop_sw_cfg_trig0_1                   0x00000000
+#define regk_iop_sw_cfg_trig0_2                   0x00000000
+#define regk_iop_sw_cfg_trig0_3                   0x00000000
+#define regk_iop_sw_cfg_trig1_0                   0x00000000
+#define regk_iop_sw_cfg_trig1_1                   0x00000000
+#define regk_iop_sw_cfg_trig1_2                   0x00000000
+#define regk_iop_sw_cfg_trig1_3                   0x00000000
+#define regk_iop_sw_cfg_trig2_0                   0x00000000
+#define regk_iop_sw_cfg_trig2_1                   0x00000000
+#define regk_iop_sw_cfg_trig2_2                   0x00000000
+#define regk_iop_sw_cfg_trig2_3                   0x00000000
+#define regk_iop_sw_cfg_trig3_0                   0x00000000
+#define regk_iop_sw_cfg_trig3_1                   0x00000000
+#define regk_iop_sw_cfg_trig3_2                   0x00000000
+#define regk_iop_sw_cfg_trig3_3                   0x00000000
+#define regk_iop_sw_cfg_trig4_0                   0x00000001
+#define regk_iop_sw_cfg_trig4_1                   0x00000001
+#define regk_iop_sw_cfg_trig4_2                   0x00000001
+#define regk_iop_sw_cfg_trig4_3                   0x00000001
+#define regk_iop_sw_cfg_trig5_0                   0x00000001
+#define regk_iop_sw_cfg_trig5_1                   0x00000001
+#define regk_iop_sw_cfg_trig5_2                   0x00000001
+#define regk_iop_sw_cfg_trig5_3                   0x00000001
+#define regk_iop_sw_cfg_trig6_0                   0x00000001
+#define regk_iop_sw_cfg_trig6_1                   0x00000001
+#define regk_iop_sw_cfg_trig6_2                   0x00000001
+#define regk_iop_sw_cfg_trig6_3                   0x00000001
+#define regk_iop_sw_cfg_trig7_0                   0x00000001
+#define regk_iop_sw_cfg_trig7_1                   0x00000001
+#define regk_iop_sw_cfg_trig7_2                   0x00000001
+#define regk_iop_sw_cfg_trig7_3                   0x00000001
+#endif /* __iop_sw_cfg_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
new file mode 100644
index 00000000000..db347bcba02
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
@@ -0,0 +1,1758 @@
+#ifndef __iop_sw_cpu_defs_asm_h
+#define __iop_sw_cpu_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:19 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
+ *      id: $Id: iop_sw_cpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0
+#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1
+#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0
+#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1
+#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2
+#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3
+#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3
+#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___lsb 6
+#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___width 1
+#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___bit 6
+#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___lsb 7
+#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___width 1
+#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___bit 7
+#define reg_iop_sw_cpu_rw_mc_ctrl_offset 0
+
+/* Register rw_mc_data, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0
+#define reg_iop_sw_cpu_rw_mc_data___val___width 32
+#define reg_iop_sw_cpu_rw_mc_data_offset 4
+
+/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_mc_addr_offset 8
+
+/* Register rs_mc_data, scope iop_sw_cpu, type rs */
+#define reg_iop_sw_cpu_rs_mc_data_offset 12
+
+/* Register r_mc_data, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_mc_data_offset 16
+
+/* Register r_mc_stat, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0
+#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1
+#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0
+#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1
+#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1
+#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1
+#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___lsb 2
+#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___width 1
+#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___bit 2
+#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___lsb 3
+#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___width 1
+#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___bit 3
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 4
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 4
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 5
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 5
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___lsb 6
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___width 1
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___bit 6
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___lsb 7
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___width 1
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___bit 7
+#define reg_iop_sw_cpu_r_mc_stat_offset 20
+
+/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___lsb 0
+#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___width 8
+#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___lsb 8
+#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___width 8
+#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___lsb 16
+#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___width 8
+#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___lsb 24
+#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___width 8
+#define reg_iop_sw_cpu_rw_bus0_clr_mask_offset 24
+
+/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___lsb 0
+#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___width 8
+#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___lsb 8
+#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___width 8
+#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___lsb 16
+#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___width 8
+#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___lsb 24
+#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___width 8
+#define reg_iop_sw_cpu_rw_bus0_set_mask_offset 28
+
+/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___lsb 0
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___width 1
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___bit 0
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___lsb 1
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___width 1
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___bit 1
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___lsb 2
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___width 1
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___bit 2
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___lsb 3
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___width 1
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___bit 3
+#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask_offset 32
+
+/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___lsb 0
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___width 1
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___bit 0
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___lsb 1
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___width 1
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___bit 1
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___lsb 2
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___width 1
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___bit 2
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___lsb 3
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___width 1
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___bit 3
+#define reg_iop_sw_cpu_rw_bus0_oe_set_mask_offset 36
+
+/* Register r_bus0_in, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_bus0_in_offset 40
+
+/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___lsb 0
+#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___width 8
+#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___lsb 8
+#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___width 8
+#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___lsb 16
+#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___width 8
+#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___lsb 24
+#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___width 8
+#define reg_iop_sw_cpu_rw_bus1_clr_mask_offset 44
+
+/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___lsb 0
+#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___width 8
+#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___lsb 8
+#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___width 8
+#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___lsb 16
+#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___width 8
+#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___lsb 24
+#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___width 8
+#define reg_iop_sw_cpu_rw_bus1_set_mask_offset 48
+
+/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___lsb 0
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___width 1
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___bit 0
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___lsb 1
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___width 1
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___bit 1
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___lsb 2
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___width 1
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___bit 2
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___lsb 3
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___width 1
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___bit 3
+#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask_offset 52
+
+/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___lsb 0
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___width 1
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___bit 0
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___lsb 1
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___width 1
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___bit 1
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___lsb 2
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___width 1
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___bit 2
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___lsb 3
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___width 1
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___bit 3
+#define reg_iop_sw_cpu_rw_bus1_oe_set_mask_offset 56
+
+/* Register r_bus1_in, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_bus1_in_offset 60
+
+/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0
+#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32
+#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 64
+
+/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0
+#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32
+#define reg_iop_sw_cpu_rw_gio_set_mask_offset 68
+
+/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0
+#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32
+#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 72
+
+/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0
+#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32
+#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 76
+
+/* Register r_gio_in, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_gio_in_offset 80
+
+/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___lsb 16
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___bit 16
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___lsb 17
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___bit 17
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___lsb 18
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___bit 18
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___lsb 19
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___bit 19
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___lsb 20
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___bit 20
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___lsb 21
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___bit 21
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___lsb 22
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___bit 22
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___lsb 23
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___bit 23
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___lsb 24
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___bit 24
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___lsb 25
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___bit 25
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___lsb 26
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___bit 26
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___lsb 27
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___bit 27
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___lsb 28
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___bit 28
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___lsb 29
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___bit 29
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___lsb 30
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___bit 30
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___lsb 31
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___bit 31
+#define reg_iop_sw_cpu_rw_intr0_mask_offset 84
+
+/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___lsb 16
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___bit 16
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___lsb 17
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___bit 17
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___lsb 18
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___bit 18
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___lsb 19
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___bit 19
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___lsb 20
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___bit 20
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___lsb 21
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___bit 21
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___lsb 22
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___bit 22
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___lsb 23
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___bit 23
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___lsb 24
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___bit 24
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___lsb 25
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___bit 25
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___lsb 26
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___bit 26
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___lsb 27
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___bit 27
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___lsb 28
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___bit 28
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___lsb 29
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___bit 29
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___lsb 30
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___bit 30
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___lsb 31
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___bit 31
+#define reg_iop_sw_cpu_rw_ack_intr0_offset 88
+
+/* Register r_intr0, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0
+#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0
+#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1
+#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1
+#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2
+#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2
+#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3
+#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3
+#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4
+#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4
+#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5
+#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5
+#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6
+#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6
+#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7
+#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7
+#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8
+#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8
+#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9
+#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9
+#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10
+#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10
+#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11
+#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11
+#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12
+#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12
+#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13
+#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13
+#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14
+#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14
+#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15
+#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15
+#define reg_iop_sw_cpu_r_intr0___spu0_0___lsb 16
+#define reg_iop_sw_cpu_r_intr0___spu0_0___width 1
+#define reg_iop_sw_cpu_r_intr0___spu0_0___bit 16
+#define reg_iop_sw_cpu_r_intr0___spu0_1___lsb 17
+#define reg_iop_sw_cpu_r_intr0___spu0_1___width 1
+#define reg_iop_sw_cpu_r_intr0___spu0_1___bit 17
+#define reg_iop_sw_cpu_r_intr0___spu0_2___lsb 18
+#define reg_iop_sw_cpu_r_intr0___spu0_2___width 1
+#define reg_iop_sw_cpu_r_intr0___spu0_2___bit 18
+#define reg_iop_sw_cpu_r_intr0___spu0_3___lsb 19
+#define reg_iop_sw_cpu_r_intr0___spu0_3___width 1
+#define reg_iop_sw_cpu_r_intr0___spu0_3___bit 19
+#define reg_iop_sw_cpu_r_intr0___spu0_4___lsb 20
+#define reg_iop_sw_cpu_r_intr0___spu0_4___width 1
+#define reg_iop_sw_cpu_r_intr0___spu0_4___bit 20
+#define reg_iop_sw_cpu_r_intr0___spu0_5___lsb 21
+#define reg_iop_sw_cpu_r_intr0___spu0_5___width 1
+#define reg_iop_sw_cpu_r_intr0___spu0_5___bit 21
+#define reg_iop_sw_cpu_r_intr0___spu0_6___lsb 22
+#define reg_iop_sw_cpu_r_intr0___spu0_6___width 1
+#define reg_iop_sw_cpu_r_intr0___spu0_6___bit 22
+#define reg_iop_sw_cpu_r_intr0___spu0_7___lsb 23
+#define reg_iop_sw_cpu_r_intr0___spu0_7___width 1
+#define reg_iop_sw_cpu_r_intr0___spu0_7___bit 23
+#define reg_iop_sw_cpu_r_intr0___spu1_8___lsb 24
+#define reg_iop_sw_cpu_r_intr0___spu1_8___width 1
+#define reg_iop_sw_cpu_r_intr0___spu1_8___bit 24
+#define reg_iop_sw_cpu_r_intr0___spu1_9___lsb 25
+#define reg_iop_sw_cpu_r_intr0___spu1_9___width 1
+#define reg_iop_sw_cpu_r_intr0___spu1_9___bit 25
+#define reg_iop_sw_cpu_r_intr0___spu1_10___lsb 26
+#define reg_iop_sw_cpu_r_intr0___spu1_10___width 1
+#define reg_iop_sw_cpu_r_intr0___spu1_10___bit 26
+#define reg_iop_sw_cpu_r_intr0___spu1_11___lsb 27
+#define reg_iop_sw_cpu_r_intr0___spu1_11___width 1
+#define reg_iop_sw_cpu_r_intr0___spu1_11___bit 27
+#define reg_iop_sw_cpu_r_intr0___spu1_12___lsb 28
+#define reg_iop_sw_cpu_r_intr0___spu1_12___width 1
+#define reg_iop_sw_cpu_r_intr0___spu1_12___bit 28
+#define reg_iop_sw_cpu_r_intr0___spu1_13___lsb 29
+#define reg_iop_sw_cpu_r_intr0___spu1_13___width 1
+#define reg_iop_sw_cpu_r_intr0___spu1_13___bit 29
+#define reg_iop_sw_cpu_r_intr0___spu1_14___lsb 30
+#define reg_iop_sw_cpu_r_intr0___spu1_14___width 1
+#define reg_iop_sw_cpu_r_intr0___spu1_14___bit 30
+#define reg_iop_sw_cpu_r_intr0___spu1_15___lsb 31
+#define reg_iop_sw_cpu_r_intr0___spu1_15___width 1
+#define reg_iop_sw_cpu_r_intr0___spu1_15___bit 31
+#define reg_iop_sw_cpu_r_intr0_offset 92
+
+/* Register r_masked_intr0, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___lsb 16
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___bit 16
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___lsb 17
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___bit 17
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___lsb 18
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___bit 18
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___lsb 19
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___bit 19
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___lsb 20
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___bit 20
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___lsb 21
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___bit 21
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___lsb 22
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___bit 22
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___lsb 23
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___bit 23
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___lsb 24
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___bit 24
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___lsb 25
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___bit 25
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___lsb 26
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___bit 26
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___lsb 27
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___bit 27
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___lsb 28
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___bit 28
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___lsb 29
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___bit 29
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___lsb 30
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___bit 30
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___lsb 31
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___bit 31
+#define reg_iop_sw_cpu_r_masked_intr0_offset 96
+
+/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___lsb 16
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___bit 16
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___lsb 17
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___bit 17
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___lsb 18
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___bit 18
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___lsb 19
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___bit 19
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___lsb 20
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___bit 20
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___lsb 21
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___bit 21
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___lsb 22
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___bit 22
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___lsb 23
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___bit 23
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___lsb 24
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___bit 24
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___lsb 25
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___bit 25
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___lsb 26
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___bit 26
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___lsb 27
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___bit 27
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___lsb 28
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___bit 28
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___lsb 29
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___bit 29
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___lsb 30
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___bit 30
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___lsb 31
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___bit 31
+#define reg_iop_sw_cpu_rw_intr1_mask_offset 100
+
+/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___lsb 16
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___bit 16
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___lsb 17
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___bit 17
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___lsb 18
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___bit 18
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___lsb 19
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___bit 19
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___lsb 20
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___bit 20
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___lsb 21
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___bit 21
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___lsb 22
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___bit 22
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___lsb 23
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___bit 23
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___lsb 24
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___bit 24
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___lsb 25
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___bit 25
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___lsb 26
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___bit 26
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___lsb 27
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___bit 27
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___lsb 28
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___bit 28
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___lsb 29
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___bit 29
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___lsb 30
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___bit 30
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___lsb 31
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___bit 31
+#define reg_iop_sw_cpu_rw_ack_intr1_offset 104
+
+/* Register r_intr1, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0
+#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0
+#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1
+#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1
+#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2
+#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2
+#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3
+#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3
+#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4
+#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4
+#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5
+#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5
+#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6
+#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6
+#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7
+#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7
+#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8
+#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8
+#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9
+#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9
+#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10
+#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10
+#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11
+#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11
+#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12
+#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12
+#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13
+#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13
+#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14
+#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14
+#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15
+#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15
+#define reg_iop_sw_cpu_r_intr1___spu0_8___lsb 16
+#define reg_iop_sw_cpu_r_intr1___spu0_8___width 1
+#define reg_iop_sw_cpu_r_intr1___spu0_8___bit 16
+#define reg_iop_sw_cpu_r_intr1___spu0_9___lsb 17
+#define reg_iop_sw_cpu_r_intr1___spu0_9___width 1
+#define reg_iop_sw_cpu_r_intr1___spu0_9___bit 17
+#define reg_iop_sw_cpu_r_intr1___spu0_10___lsb 18
+#define reg_iop_sw_cpu_r_intr1___spu0_10___width 1
+#define reg_iop_sw_cpu_r_intr1___spu0_10___bit 18
+#define reg_iop_sw_cpu_r_intr1___spu0_11___lsb 19
+#define reg_iop_sw_cpu_r_intr1___spu0_11___width 1
+#define reg_iop_sw_cpu_r_intr1___spu0_11___bit 19
+#define reg_iop_sw_cpu_r_intr1___spu0_12___lsb 20
+#define reg_iop_sw_cpu_r_intr1___spu0_12___width 1
+#define reg_iop_sw_cpu_r_intr1___spu0_12___bit 20
+#define reg_iop_sw_cpu_r_intr1___spu0_13___lsb 21
+#define reg_iop_sw_cpu_r_intr1___spu0_13___width 1
+#define reg_iop_sw_cpu_r_intr1___spu0_13___bit 21
+#define reg_iop_sw_cpu_r_intr1___spu0_14___lsb 22
+#define reg_iop_sw_cpu_r_intr1___spu0_14___width 1
+#define reg_iop_sw_cpu_r_intr1___spu0_14___bit 22
+#define reg_iop_sw_cpu_r_intr1___spu0_15___lsb 23
+#define reg_iop_sw_cpu_r_intr1___spu0_15___width 1
+#define reg_iop_sw_cpu_r_intr1___spu0_15___bit 23
+#define reg_iop_sw_cpu_r_intr1___spu1_0___lsb 24
+#define reg_iop_sw_cpu_r_intr1___spu1_0___width 1
+#define reg_iop_sw_cpu_r_intr1___spu1_0___bit 24
+#define reg_iop_sw_cpu_r_intr1___spu1_1___lsb 25
+#define reg_iop_sw_cpu_r_intr1___spu1_1___width 1
+#define reg_iop_sw_cpu_r_intr1___spu1_1___bit 25
+#define reg_iop_sw_cpu_r_intr1___spu1_2___lsb 26
+#define reg_iop_sw_cpu_r_intr1___spu1_2___width 1
+#define reg_iop_sw_cpu_r_intr1___spu1_2___bit 26
+#define reg_iop_sw_cpu_r_intr1___spu1_3___lsb 27
+#define reg_iop_sw_cpu_r_intr1___spu1_3___width 1
+#define reg_iop_sw_cpu_r_intr1___spu1_3___bit 27
+#define reg_iop_sw_cpu_r_intr1___spu1_4___lsb 28
+#define reg_iop_sw_cpu_r_intr1___spu1_4___width 1
+#define reg_iop_sw_cpu_r_intr1___spu1_4___bit 28
+#define reg_iop_sw_cpu_r_intr1___spu1_5___lsb 29
+#define reg_iop_sw_cpu_r_intr1___spu1_5___width 1
+#define reg_iop_sw_cpu_r_intr1___spu1_5___bit 29
+#define reg_iop_sw_cpu_r_intr1___spu1_6___lsb 30
+#define reg_iop_sw_cpu_r_intr1___spu1_6___width 1
+#define reg_iop_sw_cpu_r_intr1___spu1_6___bit 30
+#define reg_iop_sw_cpu_r_intr1___spu1_7___lsb 31
+#define reg_iop_sw_cpu_r_intr1___spu1_7___width 1
+#define reg_iop_sw_cpu_r_intr1___spu1_7___bit 31
+#define reg_iop_sw_cpu_r_intr1_offset 108
+
+/* Register r_masked_intr1, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___lsb 16
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___bit 16
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___lsb 17
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___bit 17
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___lsb 18
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___bit 18
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___lsb 19
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___bit 19
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___lsb 20
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___bit 20
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___lsb 21
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___bit 21
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___lsb 22
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___bit 22
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___lsb 23
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___bit 23
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___lsb 24
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___bit 24
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___lsb 25
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___bit 25
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___lsb 26
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___bit 26
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___lsb 27
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___bit 27
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___lsb 28
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___bit 28
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___lsb 29
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___bit 29
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___lsb 30
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___bit 30
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___lsb 31
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___bit 31
+#define reg_iop_sw_cpu_r_masked_intr1_offset 112
+
+/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___lsb 0
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___bit 0
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___lsb 1
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___bit 1
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___lsb 2
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___bit 2
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___lsb 3
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___bit 3
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___lsb 4
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___bit 4
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___lsb 5
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___bit 5
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___lsb 6
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___bit 6
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___lsb 7
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___bit 7
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___lsb 8
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___bit 8
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___lsb 9
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___bit 9
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___lsb 10
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___bit 10
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___lsb 11
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___bit 11
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___lsb 12
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___bit 12
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___lsb 13
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___bit 13
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___lsb 14
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___bit 14
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___lsb 15
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___bit 15
+#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___lsb 16
+#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___bit 16
+#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___lsb 17
+#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___bit 17
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___lsb 18
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___bit 18
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___lsb 19
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___bit 19
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___lsb 20
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___bit 20
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___lsb 21
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___bit 21
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___lsb 22
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___bit 22
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___lsb 23
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___bit 23
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___lsb 24
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___bit 24
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___lsb 25
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___bit 25
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___lsb 26
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___bit 26
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___lsb 27
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___bit 27
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___lsb 28
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___bit 28
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___lsb 29
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___bit 29
+#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___lsb 30
+#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___bit 30
+#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___lsb 31
+#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___width 1
+#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___bit 31
+#define reg_iop_sw_cpu_rw_intr2_mask_offset 116
+
+/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___lsb 0
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___bit 0
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___lsb 1
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___bit 1
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___lsb 2
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___bit 2
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___lsb 3
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___bit 3
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___lsb 4
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___bit 4
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___lsb 5
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___bit 5
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___lsb 6
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___bit 6
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___lsb 7
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___bit 7
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___lsb 8
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___bit 8
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___lsb 9
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___bit 9
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___lsb 10
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___bit 10
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___lsb 11
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___bit 11
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___lsb 12
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___bit 12
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___lsb 13
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___bit 13
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___lsb 14
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___bit 14
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___lsb 15
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___width 1
+#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___bit 15
+#define reg_iop_sw_cpu_rw_ack_intr2_offset 120
+
+/* Register r_intr2, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_intr2___mpu_0___lsb 0
+#define reg_iop_sw_cpu_r_intr2___mpu_0___width 1
+#define reg_iop_sw_cpu_r_intr2___mpu_0___bit 0
+#define reg_iop_sw_cpu_r_intr2___mpu_1___lsb 1
+#define reg_iop_sw_cpu_r_intr2___mpu_1___width 1
+#define reg_iop_sw_cpu_r_intr2___mpu_1___bit 1
+#define reg_iop_sw_cpu_r_intr2___mpu_2___lsb 2
+#define reg_iop_sw_cpu_r_intr2___mpu_2___width 1
+#define reg_iop_sw_cpu_r_intr2___mpu_2___bit 2
+#define reg_iop_sw_cpu_r_intr2___mpu_3___lsb 3
+#define reg_iop_sw_cpu_r_intr2___mpu_3___width 1
+#define reg_iop_sw_cpu_r_intr2___mpu_3___bit 3
+#define reg_iop_sw_cpu_r_intr2___mpu_4___lsb 4
+#define reg_iop_sw_cpu_r_intr2___mpu_4___width 1
+#define reg_iop_sw_cpu_r_intr2___mpu_4___bit 4
+#define reg_iop_sw_cpu_r_intr2___mpu_5___lsb 5
+#define reg_iop_sw_cpu_r_intr2___mpu_5___width 1
+#define reg_iop_sw_cpu_r_intr2___mpu_5___bit 5
+#define reg_iop_sw_cpu_r_intr2___mpu_6___lsb 6
+#define reg_iop_sw_cpu_r_intr2___mpu_6___width 1
+#define reg_iop_sw_cpu_r_intr2___mpu_6___bit 6
+#define reg_iop_sw_cpu_r_intr2___mpu_7___lsb 7
+#define reg_iop_sw_cpu_r_intr2___mpu_7___width 1
+#define reg_iop_sw_cpu_r_intr2___mpu_7___bit 7
+#define reg_iop_sw_cpu_r_intr2___spu0_0___lsb 8
+#define reg_iop_sw_cpu_r_intr2___spu0_0___width 1
+#define reg_iop_sw_cpu_r_intr2___spu0_0___bit 8
+#define reg_iop_sw_cpu_r_intr2___spu0_1___lsb 9
+#define reg_iop_sw_cpu_r_intr2___spu0_1___width 1
+#define reg_iop_sw_cpu_r_intr2___spu0_1___bit 9
+#define reg_iop_sw_cpu_r_intr2___spu0_2___lsb 10
+#define reg_iop_sw_cpu_r_intr2___spu0_2___width 1
+#define reg_iop_sw_cpu_r_intr2___spu0_2___bit 10
+#define reg_iop_sw_cpu_r_intr2___spu0_3___lsb 11
+#define reg_iop_sw_cpu_r_intr2___spu0_3___width 1
+#define reg_iop_sw_cpu_r_intr2___spu0_3___bit 11
+#define reg_iop_sw_cpu_r_intr2___spu0_4___lsb 12
+#define reg_iop_sw_cpu_r_intr2___spu0_4___width 1
+#define reg_iop_sw_cpu_r_intr2___spu0_4___bit 12
+#define reg_iop_sw_cpu_r_intr2___spu0_5___lsb 13
+#define reg_iop_sw_cpu_r_intr2___spu0_5___width 1
+#define reg_iop_sw_cpu_r_intr2___spu0_5___bit 13
+#define reg_iop_sw_cpu_r_intr2___spu0_6___lsb 14
+#define reg_iop_sw_cpu_r_intr2___spu0_6___width 1
+#define reg_iop_sw_cpu_r_intr2___spu0_6___bit 14
+#define reg_iop_sw_cpu_r_intr2___spu0_7___lsb 15
+#define reg_iop_sw_cpu_r_intr2___spu0_7___width 1
+#define reg_iop_sw_cpu_r_intr2___spu0_7___bit 15
+#define reg_iop_sw_cpu_r_intr2___dmc_in0___lsb 16
+#define reg_iop_sw_cpu_r_intr2___dmc_in0___width 1
+#define reg_iop_sw_cpu_r_intr2___dmc_in0___bit 16
+#define reg_iop_sw_cpu_r_intr2___dmc_out0___lsb 17
+#define reg_iop_sw_cpu_r_intr2___dmc_out0___width 1
+#define reg_iop_sw_cpu_r_intr2___dmc_out0___bit 17
+#define reg_iop_sw_cpu_r_intr2___fifo_in0___lsb 18
+#define reg_iop_sw_cpu_r_intr2___fifo_in0___width 1
+#define reg_iop_sw_cpu_r_intr2___fifo_in0___bit 18
+#define reg_iop_sw_cpu_r_intr2___fifo_out0___lsb 19
+#define reg_iop_sw_cpu_r_intr2___fifo_out0___width 1
+#define reg_iop_sw_cpu_r_intr2___fifo_out0___bit 19
+#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___lsb 20
+#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___width 1
+#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___bit 20
+#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___lsb 21
+#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___width 1
+#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___bit 21
+#define reg_iop_sw_cpu_r_intr2___trigger_grp0___lsb 22
+#define reg_iop_sw_cpu_r_intr2___trigger_grp0___width 1
+#define reg_iop_sw_cpu_r_intr2___trigger_grp0___bit 22
+#define reg_iop_sw_cpu_r_intr2___trigger_grp1___lsb 23
+#define reg_iop_sw_cpu_r_intr2___trigger_grp1___width 1
+#define reg_iop_sw_cpu_r_intr2___trigger_grp1___bit 23
+#define reg_iop_sw_cpu_r_intr2___trigger_grp2___lsb 24
+#define reg_iop_sw_cpu_r_intr2___trigger_grp2___width 1
+#define reg_iop_sw_cpu_r_intr2___trigger_grp2___bit 24
+#define reg_iop_sw_cpu_r_intr2___trigger_grp3___lsb 25
+#define reg_iop_sw_cpu_r_intr2___trigger_grp3___width 1
+#define reg_iop_sw_cpu_r_intr2___trigger_grp3___bit 25
+#define reg_iop_sw_cpu_r_intr2___trigger_grp4___lsb 26
+#define reg_iop_sw_cpu_r_intr2___trigger_grp4___width 1
+#define reg_iop_sw_cpu_r_intr2___trigger_grp4___bit 26
+#define reg_iop_sw_cpu_r_intr2___trigger_grp5___lsb 27
+#define reg_iop_sw_cpu_r_intr2___trigger_grp5___width 1
+#define reg_iop_sw_cpu_r_intr2___trigger_grp5___bit 27
+#define reg_iop_sw_cpu_r_intr2___trigger_grp6___lsb 28
+#define reg_iop_sw_cpu_r_intr2___trigger_grp6___width 1
+#define reg_iop_sw_cpu_r_intr2___trigger_grp6___bit 28
+#define reg_iop_sw_cpu_r_intr2___trigger_grp7___lsb 29
+#define reg_iop_sw_cpu_r_intr2___trigger_grp7___width 1
+#define reg_iop_sw_cpu_r_intr2___trigger_grp7___bit 29
+#define reg_iop_sw_cpu_r_intr2___timer_grp0___lsb 30
+#define reg_iop_sw_cpu_r_intr2___timer_grp0___width 1
+#define reg_iop_sw_cpu_r_intr2___timer_grp0___bit 30
+#define reg_iop_sw_cpu_r_intr2___timer_grp1___lsb 31
+#define reg_iop_sw_cpu_r_intr2___timer_grp1___width 1
+#define reg_iop_sw_cpu_r_intr2___timer_grp1___bit 31
+#define reg_iop_sw_cpu_r_intr2_offset 124
+
+/* Register r_masked_intr2, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___lsb 0
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___bit 0
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___lsb 1
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___bit 1
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___lsb 2
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___bit 2
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___lsb 3
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___bit 3
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___lsb 4
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___bit 4
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___lsb 5
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___bit 5
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___lsb 6
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___bit 6
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___lsb 7
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___bit 7
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___lsb 8
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___bit 8
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___lsb 9
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___bit 9
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___lsb 10
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___bit 10
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___lsb 11
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___bit 11
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___lsb 12
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___bit 12
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___lsb 13
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___bit 13
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___lsb 14
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___bit 14
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___lsb 15
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___bit 15
+#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___lsb 16
+#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___bit 16
+#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___lsb 17
+#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___bit 17
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___lsb 18
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___bit 18
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___lsb 19
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___bit 19
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___lsb 20
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___bit 20
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___lsb 21
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___bit 21
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___lsb 22
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___bit 22
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___lsb 23
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___bit 23
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___lsb 24
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___bit 24
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___lsb 25
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___bit 25
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___lsb 26
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___bit 26
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___lsb 27
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___bit 27
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___lsb 28
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___bit 28
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___lsb 29
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___bit 29
+#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___lsb 30
+#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___bit 30
+#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___lsb 31
+#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___width 1
+#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___bit 31
+#define reg_iop_sw_cpu_r_masked_intr2_offset 128
+
+/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___lsb 0
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___bit 0
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___lsb 1
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___bit 1
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___lsb 2
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___bit 2
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___lsb 3
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___bit 3
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___lsb 4
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___bit 4
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___lsb 5
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___bit 5
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___lsb 6
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___bit 6
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___lsb 7
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___bit 7
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___lsb 8
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___bit 8
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___lsb 9
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___bit 9
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___lsb 10
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___bit 10
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___lsb 11
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___bit 11
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___lsb 12
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___bit 12
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___lsb 13
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___bit 13
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___lsb 14
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___bit 14
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___lsb 15
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___bit 15
+#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___lsb 16
+#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___bit 16
+#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___lsb 17
+#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___bit 17
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___lsb 18
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___bit 18
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___lsb 19
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___bit 19
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___lsb 20
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___bit 20
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___lsb 21
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___bit 21
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___lsb 22
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___bit 22
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___lsb 23
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___bit 23
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___lsb 24
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___bit 24
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___lsb 25
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___bit 25
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___lsb 26
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___bit 26
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___lsb 27
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___bit 27
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___lsb 28
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___bit 28
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___lsb 29
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___bit 29
+#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___lsb 30
+#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___bit 30
+#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___lsb 31
+#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___width 1
+#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___bit 31
+#define reg_iop_sw_cpu_rw_intr3_mask_offset 132
+
+/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___lsb 0
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___bit 0
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___lsb 1
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___bit 1
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___lsb 2
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___bit 2
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___lsb 3
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___bit 3
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___lsb 4
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___bit 4
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___lsb 5
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___bit 5
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___lsb 6
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___bit 6
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___lsb 7
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___bit 7
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___lsb 8
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___bit 8
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___lsb 9
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___bit 9
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___lsb 10
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___bit 10
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___lsb 11
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___bit 11
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___lsb 12
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___bit 12
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___lsb 13
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___bit 13
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___lsb 14
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___bit 14
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___lsb 15
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___width 1
+#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___bit 15
+#define reg_iop_sw_cpu_rw_ack_intr3_offset 136
+
+/* Register r_intr3, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_intr3___mpu_16___lsb 0
+#define reg_iop_sw_cpu_r_intr3___mpu_16___width 1
+#define reg_iop_sw_cpu_r_intr3___mpu_16___bit 0
+#define reg_iop_sw_cpu_r_intr3___mpu_17___lsb 1
+#define reg_iop_sw_cpu_r_intr3___mpu_17___width 1
+#define reg_iop_sw_cpu_r_intr3___mpu_17___bit 1
+#define reg_iop_sw_cpu_r_intr3___mpu_18___lsb 2
+#define reg_iop_sw_cpu_r_intr3___mpu_18___width 1
+#define reg_iop_sw_cpu_r_intr3___mpu_18___bit 2
+#define reg_iop_sw_cpu_r_intr3___mpu_19___lsb 3
+#define reg_iop_sw_cpu_r_intr3___mpu_19___width 1
+#define reg_iop_sw_cpu_r_intr3___mpu_19___bit 3
+#define reg_iop_sw_cpu_r_intr3___mpu_20___lsb 4
+#define reg_iop_sw_cpu_r_intr3___mpu_20___width 1
+#define reg_iop_sw_cpu_r_intr3___mpu_20___bit 4
+#define reg_iop_sw_cpu_r_intr3___mpu_21___lsb 5
+#define reg_iop_sw_cpu_r_intr3___mpu_21___width 1
+#define reg_iop_sw_cpu_r_intr3___mpu_21___bit 5
+#define reg_iop_sw_cpu_r_intr3___mpu_22___lsb 6
+#define reg_iop_sw_cpu_r_intr3___mpu_22___width 1
+#define reg_iop_sw_cpu_r_intr3___mpu_22___bit 6
+#define reg_iop_sw_cpu_r_intr3___mpu_23___lsb 7
+#define reg_iop_sw_cpu_r_intr3___mpu_23___width 1
+#define reg_iop_sw_cpu_r_intr3___mpu_23___bit 7
+#define reg_iop_sw_cpu_r_intr3___spu1_0___lsb 8
+#define reg_iop_sw_cpu_r_intr3___spu1_0___width 1
+#define reg_iop_sw_cpu_r_intr3___spu1_0___bit 8
+#define reg_iop_sw_cpu_r_intr3___spu1_1___lsb 9
+#define reg_iop_sw_cpu_r_intr3___spu1_1___width 1
+#define reg_iop_sw_cpu_r_intr3___spu1_1___bit 9
+#define reg_iop_sw_cpu_r_intr3___spu1_2___lsb 10
+#define reg_iop_sw_cpu_r_intr3___spu1_2___width 1
+#define reg_iop_sw_cpu_r_intr3___spu1_2___bit 10
+#define reg_iop_sw_cpu_r_intr3___spu1_3___lsb 11
+#define reg_iop_sw_cpu_r_intr3___spu1_3___width 1
+#define reg_iop_sw_cpu_r_intr3___spu1_3___bit 11
+#define reg_iop_sw_cpu_r_intr3___spu1_4___lsb 12
+#define reg_iop_sw_cpu_r_intr3___spu1_4___width 1
+#define reg_iop_sw_cpu_r_intr3___spu1_4___bit 12
+#define reg_iop_sw_cpu_r_intr3___spu1_5___lsb 13
+#define reg_iop_sw_cpu_r_intr3___spu1_5___width 1
+#define reg_iop_sw_cpu_r_intr3___spu1_5___bit 13
+#define reg_iop_sw_cpu_r_intr3___spu1_6___lsb 14
+#define reg_iop_sw_cpu_r_intr3___spu1_6___width 1
+#define reg_iop_sw_cpu_r_intr3___spu1_6___bit 14
+#define reg_iop_sw_cpu_r_intr3___spu1_7___lsb 15
+#define reg_iop_sw_cpu_r_intr3___spu1_7___width 1
+#define reg_iop_sw_cpu_r_intr3___spu1_7___bit 15
+#define reg_iop_sw_cpu_r_intr3___dmc_in1___lsb 16
+#define reg_iop_sw_cpu_r_intr3___dmc_in1___width 1
+#define reg_iop_sw_cpu_r_intr3___dmc_in1___bit 16
+#define reg_iop_sw_cpu_r_intr3___dmc_out1___lsb 17
+#define reg_iop_sw_cpu_r_intr3___dmc_out1___width 1
+#define reg_iop_sw_cpu_r_intr3___dmc_out1___bit 17
+#define reg_iop_sw_cpu_r_intr3___fifo_in1___lsb 18
+#define reg_iop_sw_cpu_r_intr3___fifo_in1___width 1
+#define reg_iop_sw_cpu_r_intr3___fifo_in1___bit 18
+#define reg_iop_sw_cpu_r_intr3___fifo_out1___lsb 19
+#define reg_iop_sw_cpu_r_intr3___fifo_out1___width 1
+#define reg_iop_sw_cpu_r_intr3___fifo_out1___bit 19
+#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___lsb 20
+#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___width 1
+#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___bit 20
+#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___lsb 21
+#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___width 1
+#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___bit 21
+#define reg_iop_sw_cpu_r_intr3___trigger_grp0___lsb 22
+#define reg_iop_sw_cpu_r_intr3___trigger_grp0___width 1
+#define reg_iop_sw_cpu_r_intr3___trigger_grp0___bit 22
+#define reg_iop_sw_cpu_r_intr3___trigger_grp1___lsb 23
+#define reg_iop_sw_cpu_r_intr3___trigger_grp1___width 1
+#define reg_iop_sw_cpu_r_intr3___trigger_grp1___bit 23
+#define reg_iop_sw_cpu_r_intr3___trigger_grp2___lsb 24
+#define reg_iop_sw_cpu_r_intr3___trigger_grp2___width 1
+#define reg_iop_sw_cpu_r_intr3___trigger_grp2___bit 24
+#define reg_iop_sw_cpu_r_intr3___trigger_grp3___lsb 25
+#define reg_iop_sw_cpu_r_intr3___trigger_grp3___width 1
+#define reg_iop_sw_cpu_r_intr3___trigger_grp3___bit 25
+#define reg_iop_sw_cpu_r_intr3___trigger_grp4___lsb 26
+#define reg_iop_sw_cpu_r_intr3___trigger_grp4___width 1
+#define reg_iop_sw_cpu_r_intr3___trigger_grp4___bit 26
+#define reg_iop_sw_cpu_r_intr3___trigger_grp5___lsb 27
+#define reg_iop_sw_cpu_r_intr3___trigger_grp5___width 1
+#define reg_iop_sw_cpu_r_intr3___trigger_grp5___bit 27
+#define reg_iop_sw_cpu_r_intr3___trigger_grp6___lsb 28
+#define reg_iop_sw_cpu_r_intr3___trigger_grp6___width 1
+#define reg_iop_sw_cpu_r_intr3___trigger_grp6___bit 28
+#define reg_iop_sw_cpu_r_intr3___trigger_grp7___lsb 29
+#define reg_iop_sw_cpu_r_intr3___trigger_grp7___width 1
+#define reg_iop_sw_cpu_r_intr3___trigger_grp7___bit 29
+#define reg_iop_sw_cpu_r_intr3___timer_grp2___lsb 30
+#define reg_iop_sw_cpu_r_intr3___timer_grp2___width 1
+#define reg_iop_sw_cpu_r_intr3___timer_grp2___bit 30
+#define reg_iop_sw_cpu_r_intr3___timer_grp3___lsb 31
+#define reg_iop_sw_cpu_r_intr3___timer_grp3___width 1
+#define reg_iop_sw_cpu_r_intr3___timer_grp3___bit 31
+#define reg_iop_sw_cpu_r_intr3_offset 140
+
+/* Register r_masked_intr3, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___lsb 0
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___bit 0
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___lsb 1
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___bit 1
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___lsb 2
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___bit 2
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___lsb 3
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___bit 3
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___lsb 4
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___bit 4
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___lsb 5
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___bit 5
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___lsb 6
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___bit 6
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___lsb 7
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___bit 7
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___lsb 8
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___bit 8
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___lsb 9
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___bit 9
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___lsb 10
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___bit 10
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___lsb 11
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___bit 11
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___lsb 12
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___bit 12
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___lsb 13
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___bit 13
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___lsb 14
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___bit 14
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___lsb 15
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___bit 15
+#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___lsb 16
+#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___bit 16
+#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___lsb 17
+#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___bit 17
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___lsb 18
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___bit 18
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___lsb 19
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___bit 19
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___lsb 20
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___bit 20
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___lsb 21
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___bit 21
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___lsb 22
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___bit 22
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___lsb 23
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___bit 23
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___lsb 24
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___bit 24
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___lsb 25
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___bit 25
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___lsb 26
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___bit 26
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___lsb 27
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___bit 27
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___lsb 28
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___bit 28
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___lsb 29
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___bit 29
+#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___lsb 30
+#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___bit 30
+#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___lsb 31
+#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___width 1
+#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___bit 31
+#define reg_iop_sw_cpu_r_masked_intr3_offset 144
+
+
+/* Constants */
+#define regk_iop_sw_cpu_copy                      0x00000000
+#define regk_iop_sw_cpu_no                        0x00000000
+#define regk_iop_sw_cpu_rd                        0x00000002
+#define regk_iop_sw_cpu_reg_copy                  0x00000001
+#define regk_iop_sw_cpu_rw_bus0_clr_mask_default  0x00000000
+#define regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default  0x00000000
+#define regk_iop_sw_cpu_rw_bus0_oe_set_mask_default  0x00000000
+#define regk_iop_sw_cpu_rw_bus0_set_mask_default  0x00000000
+#define regk_iop_sw_cpu_rw_bus1_clr_mask_default  0x00000000
+#define regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default  0x00000000
+#define regk_iop_sw_cpu_rw_bus1_oe_set_mask_default  0x00000000
+#define regk_iop_sw_cpu_rw_bus1_set_mask_default  0x00000000
+#define regk_iop_sw_cpu_rw_gio_clr_mask_default   0x00000000
+#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default  0x00000000
+#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default  0x00000000
+#define regk_iop_sw_cpu_rw_gio_set_mask_default   0x00000000
+#define regk_iop_sw_cpu_rw_intr0_mask_default     0x00000000
+#define regk_iop_sw_cpu_rw_intr1_mask_default     0x00000000
+#define regk_iop_sw_cpu_rw_intr2_mask_default     0x00000000
+#define regk_iop_sw_cpu_rw_intr3_mask_default     0x00000000
+#define regk_iop_sw_cpu_wr                        0x00000003
+#define regk_iop_sw_cpu_yes                       0x00000001
+#endif /* __iop_sw_cpu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
new file mode 100644
index 00000000000..ee7dc0435b5
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
@@ -0,0 +1,1776 @@
+#ifndef __iop_sw_mpu_defs_asm_h
+#define __iop_sw_mpu_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:19 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_mpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
+ *      id: $Id: iop_sw_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0
+#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2
+#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0
+
+/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0
+#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1
+#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0
+#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1
+#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2
+#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3
+#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3
+#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___lsb 6
+#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___width 1
+#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___bit 6
+#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___lsb 7
+#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___width 1
+#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___bit 7
+#define reg_iop_sw_mpu_rw_mc_ctrl_offset 4
+
+/* Register rw_mc_data, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0
+#define reg_iop_sw_mpu_rw_mc_data___val___width 32
+#define reg_iop_sw_mpu_rw_mc_data_offset 8
+
+/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_mc_addr_offset 12
+
+/* Register rs_mc_data, scope iop_sw_mpu, type rs */
+#define reg_iop_sw_mpu_rs_mc_data_offset 16
+
+/* Register r_mc_data, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_mc_data_offset 20
+
+/* Register r_mc_stat, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0
+#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1
+#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0
+#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1
+#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1
+#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1
+#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___lsb 2
+#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___width 1
+#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___bit 2
+#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___lsb 3
+#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___width 1
+#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___bit 3
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 4
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 4
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 5
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 5
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___lsb 6
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___width 1
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___bit 6
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___lsb 7
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___width 1
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___bit 7
+#define reg_iop_sw_mpu_r_mc_stat_offset 24
+
+/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___lsb 0
+#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___width 8
+#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___lsb 8
+#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___width 8
+#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___lsb 16
+#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___width 8
+#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___lsb 24
+#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___width 8
+#define reg_iop_sw_mpu_rw_bus0_clr_mask_offset 28
+
+/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___lsb 0
+#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___width 8
+#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___lsb 8
+#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___width 8
+#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___lsb 16
+#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___width 8
+#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___lsb 24
+#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___width 8
+#define reg_iop_sw_mpu_rw_bus0_set_mask_offset 32
+
+/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___lsb 0
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___width 1
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___bit 0
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___lsb 1
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___width 1
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___bit 1
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___lsb 2
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___width 1
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___bit 2
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___lsb 3
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___width 1
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___bit 3
+#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask_offset 36
+
+/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___lsb 0
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___width 1
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___bit 0
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___lsb 1
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___width 1
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___bit 1
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___lsb 2
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___width 1
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___bit 2
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___lsb 3
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___width 1
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___bit 3
+#define reg_iop_sw_mpu_rw_bus0_oe_set_mask_offset 40
+
+/* Register r_bus0_in, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_bus0_in_offset 44
+
+/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___lsb 0
+#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___width 8
+#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___lsb 8
+#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___width 8
+#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___lsb 16
+#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___width 8
+#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___lsb 24
+#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___width 8
+#define reg_iop_sw_mpu_rw_bus1_clr_mask_offset 48
+
+/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___lsb 0
+#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___width 8
+#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___lsb 8
+#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___width 8
+#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___lsb 16
+#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___width 8
+#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___lsb 24
+#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___width 8
+#define reg_iop_sw_mpu_rw_bus1_set_mask_offset 52
+
+/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___lsb 0
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___width 1
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___bit 0
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___lsb 1
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___width 1
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___bit 1
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___lsb 2
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___width 1
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___bit 2
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___lsb 3
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___width 1
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___bit 3
+#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask_offset 56
+
+/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___lsb 0
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___width 1
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___bit 0
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___lsb 1
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___width 1
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___bit 1
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___lsb 2
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___width 1
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___bit 2
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___lsb 3
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___width 1
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___bit 3
+#define reg_iop_sw_mpu_rw_bus1_oe_set_mask_offset 60
+
+/* Register r_bus1_in, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_bus1_in_offset 64
+
+/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0
+#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32
+#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 68
+
+/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0
+#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32
+#define reg_iop_sw_mpu_rw_gio_set_mask_offset 72
+
+/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0
+#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32
+#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 76
+
+/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0
+#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32
+#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 80
+
+/* Register r_gio_in, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_gio_in_offset 84
+
+/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0
+#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0
+#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2
+#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2
+#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3
+#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3
+#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4
+#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4
+#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5
+#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5
+#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6
+#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6
+#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7
+#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7
+#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8
+#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8
+#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9
+#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9
+#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10
+#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10
+#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11
+#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11
+#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12
+#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12
+#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13
+#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13
+#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14
+#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14
+#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15
+#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15
+#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16
+#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16
+#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17
+#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17
+#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18
+#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18
+#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19
+#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19
+#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20
+#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20
+#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21
+#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21
+#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22
+#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22
+#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23
+#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23
+#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24
+#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24
+#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25
+#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25
+#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26
+#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26
+#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27
+#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27
+#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28
+#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28
+#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29
+#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29
+#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30
+#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30
+#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31
+#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31
+#define reg_iop_sw_mpu_rw_cpu_intr_offset 88
+
+/* Register r_cpu_intr, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0
+#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0
+#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2
+#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2
+#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3
+#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3
+#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4
+#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4
+#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5
+#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5
+#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6
+#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6
+#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7
+#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7
+#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8
+#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8
+#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9
+#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9
+#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10
+#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10
+#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11
+#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11
+#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12
+#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12
+#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13
+#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13
+#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14
+#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14
+#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15
+#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15
+#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16
+#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16
+#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17
+#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17
+#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18
+#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18
+#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19
+#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19
+#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20
+#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20
+#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21
+#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21
+#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22
+#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22
+#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23
+#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23
+#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24
+#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24
+#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25
+#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25
+#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26
+#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26
+#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27
+#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27
+#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28
+#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28
+#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29
+#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29
+#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30
+#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30
+#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31
+#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31
+#define reg_iop_sw_mpu_r_cpu_intr_offset 92
+
+/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___lsb 0
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___bit 0
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___lsb 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___bit 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___lsb 3
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___bit 3
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 4
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___lsb 5
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___bit 5
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___lsb 6
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___bit 6
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___bit 7
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___lsb 8
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___bit 8
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___lsb 9
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___bit 9
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___lsb 11
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___bit 11
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 12
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___lsb 13
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___bit 13
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___lsb 14
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___bit 14
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___bit 15
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___lsb 16
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___bit 16
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___lsb 17
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___bit 17
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___lsb 19
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___bit 19
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___bit 20
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___lsb 21
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___bit 21
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___lsb 22
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___bit 22
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___bit 23
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___lsb 24
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___bit 24
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___lsb 25
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___bit 25
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___lsb 27
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___bit 27
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___bit 28
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___lsb 29
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___bit 29
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___lsb 30
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___bit 30
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___bit 31
+#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 96
+
+/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___lsb 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___bit 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___lsb 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___bit 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___lsb 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___bit 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___lsb 9
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___bit 9
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___lsb 16
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___bit 16
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___lsb 17
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___bit 17
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___lsb 24
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___bit 24
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___lsb 25
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___bit 25
+#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 100
+
+/* Register r_intr_grp0, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___lsb 0
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___bit 0
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___lsb 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___bit 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___lsb 3
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___bit 3
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 4
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___lsb 5
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___bit 5
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___lsb 6
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___bit 6
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___bit 7
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___lsb 8
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___bit 8
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___lsb 9
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___bit 9
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___lsb 11
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___bit 11
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 12
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___lsb 13
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___bit 13
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___lsb 14
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___bit 14
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___bit 15
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___lsb 16
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___bit 16
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___lsb 17
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___bit 17
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___lsb 19
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___bit 19
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___bit 20
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___lsb 21
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___bit 21
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___lsb 22
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___bit 22
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___bit 23
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___lsb 24
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___bit 24
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___lsb 25
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___bit 25
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___lsb 27
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___bit 27
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___bit 28
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___lsb 29
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___bit 29
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___lsb 30
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___bit 30
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___bit 31
+#define reg_iop_sw_mpu_r_intr_grp0_offset 104
+
+/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___lsb 0
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___bit 0
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___lsb 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___bit 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___lsb 3
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___bit 3
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 4
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___lsb 5
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___bit 5
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___lsb 6
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___bit 6
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___bit 7
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___lsb 8
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___bit 8
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___lsb 9
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___bit 9
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___lsb 11
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___bit 11
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 12
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___lsb 13
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___bit 13
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___lsb 14
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___bit 14
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___bit 15
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___lsb 16
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___bit 16
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___lsb 17
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___bit 17
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___lsb 19
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___bit 19
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___bit 20
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___lsb 21
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___bit 21
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___lsb 22
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___bit 22
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___bit 23
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___lsb 24
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___bit 24
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___lsb 25
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___bit 25
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___lsb 27
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___bit 27
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___bit 28
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___lsb 29
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___bit 29
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___lsb 30
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___bit 30
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___bit 31
+#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 108
+
+/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___lsb 0
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___bit 0
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___lsb 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___bit 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 3
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 3
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 4
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___lsb 5
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___bit 5
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___lsb 6
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___bit 6
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___bit 7
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___lsb 8
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___bit 8
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___lsb 9
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___bit 9
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 11
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 11
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 12
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___lsb 13
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___bit 13
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___lsb 14
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___bit 14
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___bit 15
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___lsb 16
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___bit 16
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___lsb 17
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___bit 17
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 19
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 19
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___bit 20
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___lsb 21
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___bit 21
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___lsb 22
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___bit 22
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___bit 23
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___lsb 24
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___bit 24
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___lsb 25
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___bit 25
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 27
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 27
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___bit 28
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___lsb 29
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___bit 29
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___lsb 30
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___bit 30
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___bit 31
+#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 112
+
+/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___lsb 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___bit 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___lsb 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___bit 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___lsb 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___bit 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___lsb 9
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___bit 9
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___lsb 16
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___bit 16
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___lsb 17
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___bit 17
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___lsb 24
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___bit 24
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___lsb 25
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___bit 25
+#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 116
+
+/* Register r_intr_grp1, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___lsb 0
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___bit 0
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___lsb 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___bit 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 3
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 3
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 4
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___lsb 5
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___bit 5
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___lsb 6
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___bit 6
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___bit 7
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___lsb 8
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___bit 8
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___lsb 9
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___bit 9
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 11
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 11
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 12
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___lsb 13
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___bit 13
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___lsb 14
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___bit 14
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___bit 15
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___lsb 16
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___bit 16
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___lsb 17
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___bit 17
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 19
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 19
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___bit 20
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___lsb 21
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___bit 21
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___lsb 22
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___bit 22
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___bit 23
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___lsb 24
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___bit 24
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___lsb 25
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___bit 25
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 27
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 27
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___bit 28
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___lsb 29
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___bit 29
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___lsb 30
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___bit 30
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___bit 31
+#define reg_iop_sw_mpu_r_intr_grp1_offset 120
+
+/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___lsb 0
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___bit 0
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___lsb 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___bit 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 3
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 3
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 4
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___lsb 5
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___bit 5
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___lsb 6
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___bit 6
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___bit 7
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___lsb 8
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___bit 8
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___lsb 9
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___bit 9
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 11
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 11
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 12
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___lsb 13
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___bit 13
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___lsb 14
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___bit 14
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___bit 15
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___lsb 16
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___bit 16
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___lsb 17
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___bit 17
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 19
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 19
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___bit 20
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___lsb 21
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___bit 21
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___lsb 22
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___bit 22
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___bit 23
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___lsb 24
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___bit 24
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___lsb 25
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___bit 25
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 27
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 27
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___bit 28
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___lsb 29
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___bit 29
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___lsb 30
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___bit 30
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___bit 31
+#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 124
+
+/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___lsb 0
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___bit 0
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___lsb 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___bit 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___lsb 3
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___bit 3
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 4
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___lsb 5
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___bit 5
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___lsb 6
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___bit 6
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___bit 7
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___lsb 8
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___bit 8
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___lsb 9
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___bit 9
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___lsb 11
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___bit 11
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 12
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___lsb 13
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___bit 13
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___lsb 14
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___bit 14
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___bit 15
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___lsb 16
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___bit 16
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___lsb 17
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___bit 17
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___lsb 19
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___bit 19
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___bit 20
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___lsb 21
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___bit 21
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___lsb 22
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___bit 22
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___bit 23
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___lsb 24
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___bit 24
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___lsb 25
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___bit 25
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___lsb 27
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___bit 27
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___bit 28
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___lsb 29
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___bit 29
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___lsb 30
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___bit 30
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___bit 31
+#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 128
+
+/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___lsb 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___bit 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___lsb 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___bit 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___lsb 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___bit 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___lsb 9
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___bit 9
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___lsb 16
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___bit 16
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___lsb 17
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___bit 17
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___lsb 24
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___bit 24
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___lsb 25
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___bit 25
+#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 132
+
+/* Register r_intr_grp2, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___lsb 0
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___bit 0
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___lsb 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___bit 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___lsb 3
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___bit 3
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 4
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___lsb 5
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___bit 5
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___lsb 6
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___bit 6
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___bit 7
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___lsb 8
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___bit 8
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___lsb 9
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___bit 9
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___lsb 11
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___bit 11
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 12
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___lsb 13
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___bit 13
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___lsb 14
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___bit 14
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___bit 15
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___lsb 16
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___bit 16
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___lsb 17
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___bit 17
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___lsb 19
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___bit 19
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___bit 20
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___lsb 21
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___bit 21
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___lsb 22
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___bit 22
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___bit 23
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___lsb 24
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___bit 24
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___lsb 25
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___bit 25
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___lsb 27
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___bit 27
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___bit 28
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___lsb 29
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___bit 29
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___lsb 30
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___bit 30
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___bit 31
+#define reg_iop_sw_mpu_r_intr_grp2_offset 136
+
+/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___lsb 0
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___bit 0
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___lsb 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___bit 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___lsb 3
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___bit 3
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 4
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___lsb 5
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___bit 5
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___lsb 6
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___bit 6
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___bit 7
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___lsb 8
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___bit 8
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___lsb 9
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___bit 9
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___lsb 11
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___bit 11
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 12
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___lsb 13
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___bit 13
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___lsb 14
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___bit 14
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___bit 15
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___lsb 16
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___bit 16
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___lsb 17
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___bit 17
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___lsb 19
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___bit 19
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___bit 20
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___lsb 21
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___bit 21
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___lsb 22
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___bit 22
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___bit 23
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___lsb 24
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___bit 24
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___lsb 25
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___bit 25
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___lsb 27
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___bit 27
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___bit 28
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___lsb 29
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___bit 29
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___lsb 30
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___bit 30
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___bit 31
+#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 140
+
+/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___lsb 0
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___bit 0
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___lsb 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___bit 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 3
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 3
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 4
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___lsb 5
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___bit 5
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___lsb 6
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___bit 6
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___bit 7
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___lsb 8
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___bit 8
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___lsb 9
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___bit 9
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 11
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 11
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 12
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___lsb 13
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___bit 13
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___lsb 14
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___bit 14
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___bit 15
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___lsb 16
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___bit 16
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___lsb 17
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___bit 17
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 19
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 19
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___bit 20
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___lsb 21
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___bit 21
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___lsb 22
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___bit 22
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___bit 23
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___lsb 24
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___bit 24
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___lsb 25
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___bit 25
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 27
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 27
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___bit 28
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___lsb 29
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___bit 29
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___lsb 30
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___bit 30
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___bit 31
+#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 144
+
+/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___lsb 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___bit 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___lsb 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___bit 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___lsb 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___bit 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___lsb 9
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___bit 9
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___lsb 16
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___bit 16
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___lsb 17
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___bit 17
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___lsb 24
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___bit 24
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___lsb 25
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___bit 25
+#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 148
+
+/* Register r_intr_grp3, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___lsb 0
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___bit 0
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___lsb 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___bit 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 3
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 3
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 4
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___lsb 5
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___bit 5
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___lsb 6
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___bit 6
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___bit 7
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___lsb 8
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___bit 8
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___lsb 9
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___bit 9
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 11
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 11
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 12
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___lsb 13
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___bit 13
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___lsb 14
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___bit 14
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___bit 15
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___lsb 16
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___bit 16
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___lsb 17
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___bit 17
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 19
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 19
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___bit 20
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___lsb 21
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___bit 21
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___lsb 22
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___bit 22
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___bit 23
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___lsb 24
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___bit 24
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___lsb 25
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___bit 25
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 27
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 27
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___bit 28
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___lsb 29
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___bit 29
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___lsb 30
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___bit 30
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___bit 31
+#define reg_iop_sw_mpu_r_intr_grp3_offset 152
+
+/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___lsb 0
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___bit 0
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___lsb 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___bit 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___lsb 2
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___bit 2
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 3
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 3
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 4
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 4
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___lsb 5
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___bit 5
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___lsb 6
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___bit 6
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___lsb 7
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___bit 7
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___lsb 8
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___bit 8
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___lsb 9
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___bit 9
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___lsb 10
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___bit 10
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 11
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 11
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 12
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 12
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___lsb 13
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___bit 13
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___lsb 14
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___bit 14
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___lsb 15
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___bit 15
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___lsb 16
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___bit 16
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___lsb 17
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___bit 17
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___lsb 18
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___bit 18
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 19
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 19
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___lsb 20
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___bit 20
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___lsb 21
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___bit 21
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___lsb 22
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___bit 22
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___lsb 23
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___bit 23
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___lsb 24
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___bit 24
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___lsb 25
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___bit 25
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___lsb 26
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___bit 26
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 27
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 27
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___lsb 28
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___bit 28
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___lsb 29
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___bit 29
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___lsb 30
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___bit 30
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___lsb 31
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___bit 31
+#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 156
+
+
+/* Constants */
+#define regk_iop_sw_mpu_copy                      0x00000000
+#define regk_iop_sw_mpu_cpu                       0x00000000
+#define regk_iop_sw_mpu_mpu                       0x00000001
+#define regk_iop_sw_mpu_no                        0x00000000
+#define regk_iop_sw_mpu_nop                       0x00000000
+#define regk_iop_sw_mpu_rd                        0x00000002
+#define regk_iop_sw_mpu_reg_copy                  0x00000001
+#define regk_iop_sw_mpu_rw_bus0_clr_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_bus0_oe_set_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_bus0_set_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_bus1_clr_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_bus1_oe_set_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_bus1_set_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_gio_clr_mask_default   0x00000000
+#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_gio_set_mask_default   0x00000000
+#define regk_iop_sw_mpu_rw_intr_grp0_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_intr_grp1_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_intr_grp2_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_intr_grp3_mask_default  0x00000000
+#define regk_iop_sw_mpu_rw_sw_cfg_owner_default   0x00000000
+#define regk_iop_sw_mpu_set                       0x00000001
+#define regk_iop_sw_mpu_spu0                      0x00000002
+#define regk_iop_sw_mpu_spu1                      0x00000003
+#define regk_iop_sw_mpu_wr                        0x00000003
+#define regk_iop_sw_mpu_yes                       0x00000001
+#endif /* __iop_sw_mpu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h
new file mode 100644
index 00000000000..0929f144cfa
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_sw_spu_defs_asm.h
@@ -0,0 +1,691 @@
+#ifndef __iop_sw_spu_defs_asm_h
+#define __iop_sw_spu_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:19 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_spu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
+ *      id: $Id: iop_sw_spu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0
+#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1
+#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0
+#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1
+#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2
+#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3
+#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3
+#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___lsb 6
+#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___width 1
+#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___bit 6
+#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___lsb 7
+#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___width 1
+#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___bit 7
+#define reg_iop_sw_spu_rw_mc_ctrl_offset 0
+
+/* Register rw_mc_data, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_mc_data___val___lsb 0
+#define reg_iop_sw_spu_rw_mc_data___val___width 32
+#define reg_iop_sw_spu_rw_mc_data_offset 4
+
+/* Register rw_mc_addr, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_mc_addr_offset 8
+
+/* Register rs_mc_data, scope iop_sw_spu, type rs */
+#define reg_iop_sw_spu_rs_mc_data_offset 12
+
+/* Register r_mc_data, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_mc_data_offset 16
+
+/* Register r_mc_stat, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0
+#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1
+#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0
+#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1
+#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1
+#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1
+#define reg_iop_sw_spu_r_mc_stat___busy_spu0___lsb 2
+#define reg_iop_sw_spu_r_mc_stat___busy_spu0___width 1
+#define reg_iop_sw_spu_r_mc_stat___busy_spu0___bit 2
+#define reg_iop_sw_spu_r_mc_stat___busy_spu1___lsb 3
+#define reg_iop_sw_spu_r_mc_stat___busy_spu1___width 1
+#define reg_iop_sw_spu_r_mc_stat___busy_spu1___bit 3
+#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 4
+#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1
+#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 4
+#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 5
+#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1
+#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 5
+#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___lsb 6
+#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___width 1
+#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___bit 6
+#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___lsb 7
+#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___width 1
+#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___bit 7
+#define reg_iop_sw_spu_r_mc_stat_offset 20
+
+/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___width 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___lsb 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___width 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___lsb 16
+#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___width 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___lsb 24
+#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___width 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask_offset 24
+
+/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___width 8
+#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___lsb 8
+#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___width 8
+#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___lsb 16
+#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___width 8
+#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___lsb 24
+#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___width 8
+#define reg_iop_sw_spu_rw_bus0_set_mask_offset 28
+
+/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___width 1
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___bit 0
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___lsb 1
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___width 1
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___bit 1
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___lsb 2
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___width 1
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___bit 2
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___lsb 3
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___width 1
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___bit 3
+#define reg_iop_sw_spu_rw_bus0_oe_clr_mask_offset 32
+
+/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___width 1
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___bit 0
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___lsb 1
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___width 1
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___bit 1
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___lsb 2
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___width 1
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___bit 2
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___lsb 3
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___width 1
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___bit 3
+#define reg_iop_sw_spu_rw_bus0_oe_set_mask_offset 36
+
+/* Register r_bus0_in, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_bus0_in_offset 40
+
+/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___width 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___lsb 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___width 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___lsb 16
+#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___width 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___lsb 24
+#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___width 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask_offset 44
+
+/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___width 8
+#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___lsb 8
+#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___width 8
+#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___lsb 16
+#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___width 8
+#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___lsb 24
+#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___width 8
+#define reg_iop_sw_spu_rw_bus1_set_mask_offset 48
+
+/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___width 1
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___bit 0
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___lsb 1
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___width 1
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___bit 1
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___lsb 2
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___width 1
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___bit 2
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___lsb 3
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___width 1
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___bit 3
+#define reg_iop_sw_spu_rw_bus1_oe_clr_mask_offset 52
+
+/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___width 1
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___bit 0
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___lsb 1
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___width 1
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___bit 1
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___lsb 2
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___width 1
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___bit 2
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___lsb 3
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___width 1
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___bit 3
+#define reg_iop_sw_spu_rw_bus1_oe_set_mask_offset 56
+
+/* Register r_bus1_in, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_bus1_in_offset 60
+
+/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32
+#define reg_iop_sw_spu_rw_gio_clr_mask_offset 64
+
+/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32
+#define reg_iop_sw_spu_rw_gio_set_mask_offset 68
+
+/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 72
+
+/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 76
+
+/* Register r_gio_in, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_gio_in_offset 80
+
+/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___width 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___lsb 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___width 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask_lo_offset 84
+
+/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___lsb 0
+#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___width 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___lsb 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___width 8
+#define reg_iop_sw_spu_rw_bus0_clr_mask_hi_offset 88
+
+/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___width 8
+#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___lsb 8
+#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___width 8
+#define reg_iop_sw_spu_rw_bus0_set_mask_lo_offset 92
+
+/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___lsb 0
+#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___width 8
+#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___lsb 8
+#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___width 8
+#define reg_iop_sw_spu_rw_bus0_set_mask_hi_offset 96
+
+/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___width 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___lsb 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___width 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask_lo_offset 100
+
+/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___lsb 0
+#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___width 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___lsb 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___width 8
+#define reg_iop_sw_spu_rw_bus1_clr_mask_hi_offset 104
+
+/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___width 8
+#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___lsb 8
+#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___width 8
+#define reg_iop_sw_spu_rw_bus1_set_mask_lo_offset 108
+
+/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___lsb 0
+#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___width 8
+#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___lsb 8
+#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___width 8
+#define reg_iop_sw_spu_rw_bus1_set_mask_hi_offset 112
+
+/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16
+#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 116
+
+/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16
+#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 120
+
+/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16
+#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 124
+
+/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16
+#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 128
+
+/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 132
+
+/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 136
+
+/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 140
+
+/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 144
+
+/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0
+#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0
+#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2
+#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2
+#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3
+#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3
+#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4
+#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4
+#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5
+#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5
+#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6
+#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6
+#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7
+#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7
+#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8
+#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8
+#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9
+#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9
+#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10
+#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10
+#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11
+#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11
+#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12
+#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12
+#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13
+#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13
+#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14
+#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14
+#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15
+#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15
+#define reg_iop_sw_spu_rw_cpu_intr_offset 148
+
+/* Register r_cpu_intr, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0
+#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0
+#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1
+#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1
+#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2
+#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2
+#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3
+#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3
+#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4
+#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4
+#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5
+#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5
+#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6
+#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6
+#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7
+#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7
+#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8
+#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8
+#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9
+#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9
+#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10
+#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10
+#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11
+#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11
+#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12
+#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12
+#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13
+#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13
+#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14
+#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14
+#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15
+#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15
+#define reg_iop_sw_spu_r_cpu_intr_offset 152
+
+/* Register r_hw_intr, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7
+#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8
+#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1
+#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8
+#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9
+#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1
+#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9
+#define reg_iop_sw_spu_r_hw_intr___timer_grp2___lsb 10
+#define reg_iop_sw_spu_r_hw_intr___timer_grp2___width 1
+#define reg_iop_sw_spu_r_hw_intr___timer_grp2___bit 10
+#define reg_iop_sw_spu_r_hw_intr___timer_grp3___lsb 11
+#define reg_iop_sw_spu_r_hw_intr___timer_grp3___width 1
+#define reg_iop_sw_spu_r_hw_intr___timer_grp3___bit 11
+#define reg_iop_sw_spu_r_hw_intr___fifo_out0___lsb 12
+#define reg_iop_sw_spu_r_hw_intr___fifo_out0___width 1
+#define reg_iop_sw_spu_r_hw_intr___fifo_out0___bit 12
+#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___lsb 13
+#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___width 1
+#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___bit 13
+#define reg_iop_sw_spu_r_hw_intr___fifo_in0___lsb 14
+#define reg_iop_sw_spu_r_hw_intr___fifo_in0___width 1
+#define reg_iop_sw_spu_r_hw_intr___fifo_in0___bit 14
+#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___lsb 15
+#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___width 1
+#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___bit 15
+#define reg_iop_sw_spu_r_hw_intr___fifo_out1___lsb 16
+#define reg_iop_sw_spu_r_hw_intr___fifo_out1___width 1
+#define reg_iop_sw_spu_r_hw_intr___fifo_out1___bit 16
+#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___lsb 17
+#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___width 1
+#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___bit 17
+#define reg_iop_sw_spu_r_hw_intr___fifo_in1___lsb 18
+#define reg_iop_sw_spu_r_hw_intr___fifo_in1___width 1
+#define reg_iop_sw_spu_r_hw_intr___fifo_in1___bit 18
+#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___lsb 19
+#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___width 1
+#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___bit 19
+#define reg_iop_sw_spu_r_hw_intr___dmc_out0___lsb 20
+#define reg_iop_sw_spu_r_hw_intr___dmc_out0___width 1
+#define reg_iop_sw_spu_r_hw_intr___dmc_out0___bit 20
+#define reg_iop_sw_spu_r_hw_intr___dmc_in0___lsb 21
+#define reg_iop_sw_spu_r_hw_intr___dmc_in0___width 1
+#define reg_iop_sw_spu_r_hw_intr___dmc_in0___bit 21
+#define reg_iop_sw_spu_r_hw_intr___dmc_out1___lsb 22
+#define reg_iop_sw_spu_r_hw_intr___dmc_out1___width 1
+#define reg_iop_sw_spu_r_hw_intr___dmc_out1___bit 22
+#define reg_iop_sw_spu_r_hw_intr___dmc_in1___lsb 23
+#define reg_iop_sw_spu_r_hw_intr___dmc_in1___width 1
+#define reg_iop_sw_spu_r_hw_intr___dmc_in1___bit 23
+#define reg_iop_sw_spu_r_hw_intr_offset 156
+
+/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0
+#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0
+#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2
+#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2
+#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3
+#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3
+#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4
+#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4
+#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5
+#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5
+#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6
+#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6
+#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7
+#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7
+#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8
+#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8
+#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9
+#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9
+#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10
+#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10
+#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11
+#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11
+#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12
+#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12
+#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13
+#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13
+#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14
+#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14
+#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15
+#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15
+#define reg_iop_sw_spu_rw_mpu_intr_offset 160
+
+/* Register r_mpu_intr, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0
+#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0
+#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1
+#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1
+#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2
+#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2
+#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3
+#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3
+#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4
+#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4
+#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5
+#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5
+#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6
+#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6
+#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7
+#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7
+#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8
+#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8
+#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9
+#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9
+#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10
+#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10
+#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11
+#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11
+#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12
+#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12
+#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13
+#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13
+#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14
+#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14
+#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15
+#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___lsb 16
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___bit 16
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___lsb 17
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___bit 17
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___lsb 18
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___bit 18
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___lsb 19
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___bit 19
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___lsb 20
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___bit 20
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___lsb 21
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___bit 21
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___lsb 22
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___bit 22
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___lsb 23
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___bit 23
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___lsb 24
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___bit 24
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___lsb 25
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___bit 25
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___lsb 26
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___bit 26
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___lsb 27
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___bit 27
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___lsb 28
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___bit 28
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___lsb 29
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___bit 29
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___lsb 30
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___bit 30
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___lsb 31
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___width 1
+#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___bit 31
+#define reg_iop_sw_spu_r_mpu_intr_offset 164
+
+
+/* Constants */
+#define regk_iop_sw_spu_copy                      0x00000000
+#define regk_iop_sw_spu_no                        0x00000000
+#define regk_iop_sw_spu_nop                       0x00000000
+#define regk_iop_sw_spu_rd                        0x00000002
+#define regk_iop_sw_spu_reg_copy                  0x00000001
+#define regk_iop_sw_spu_rw_bus0_clr_mask_default  0x00000000
+#define regk_iop_sw_spu_rw_bus0_oe_clr_mask_default  0x00000000
+#define regk_iop_sw_spu_rw_bus0_oe_set_mask_default  0x00000000
+#define regk_iop_sw_spu_rw_bus0_set_mask_default  0x00000000
+#define regk_iop_sw_spu_rw_bus1_clr_mask_default  0x00000000
+#define regk_iop_sw_spu_rw_bus1_oe_clr_mask_default  0x00000000
+#define regk_iop_sw_spu_rw_bus1_oe_set_mask_default  0x00000000
+#define regk_iop_sw_spu_rw_bus1_set_mask_default  0x00000000
+#define regk_iop_sw_spu_rw_gio_clr_mask_default   0x00000000
+#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default  0x00000000
+#define regk_iop_sw_spu_rw_gio_oe_set_mask_default  0x00000000
+#define regk_iop_sw_spu_rw_gio_set_mask_default   0x00000000
+#define regk_iop_sw_spu_set                       0x00000001
+#define regk_iop_sw_spu_wr                        0x00000003
+#define regk_iop_sw_spu_yes                       0x00000001
+#endif /* __iop_sw_spu_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h
new file mode 100644
index 00000000000..7129a9a4bed
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_timer_grp_defs_asm.h
@@ -0,0 +1,237 @@
+#ifndef __iop_timer_grp_defs_asm_h
+#define __iop_timer_grp_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_timer_grp.r
+ *     id:           iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_timer_grp_defs_asm.h ../../inst/io_proc/rtl/iop_timer_grp.r
+ *      id: $Id: iop_timer_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope iop_timer_grp, type rw */
+#define reg_iop_timer_grp_rw_cfg___clk_src___lsb 0
+#define reg_iop_timer_grp_rw_cfg___clk_src___width 1
+#define reg_iop_timer_grp_rw_cfg___clk_src___bit 0
+#define reg_iop_timer_grp_rw_cfg___trig___lsb 1
+#define reg_iop_timer_grp_rw_cfg___trig___width 2
+#define reg_iop_timer_grp_rw_cfg___clk_gen_div___lsb 3
+#define reg_iop_timer_grp_rw_cfg___clk_gen_div___width 8
+#define reg_iop_timer_grp_rw_cfg___clk_div___lsb 11
+#define reg_iop_timer_grp_rw_cfg___clk_div___width 8
+#define reg_iop_timer_grp_rw_cfg_offset 0
+
+/* Register rw_half_period, scope iop_timer_grp, type rw */
+#define reg_iop_timer_grp_rw_half_period___quota_lo___lsb 0
+#define reg_iop_timer_grp_rw_half_period___quota_lo___width 15
+#define reg_iop_timer_grp_rw_half_period___quota_hi___lsb 15
+#define reg_iop_timer_grp_rw_half_period___quota_hi___width 15
+#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___lsb 30
+#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___width 1
+#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___bit 30
+#define reg_iop_timer_grp_rw_half_period_offset 4
+
+/* Register rw_half_period_len, scope iop_timer_grp, type rw */
+#define reg_iop_timer_grp_rw_half_period_len_offset 8
+
+#define STRIDE_iop_timer_grp_rw_tmr_cfg 4
+/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */
+#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___lsb 0
+#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___width 3
+#define reg_iop_timer_grp_rw_tmr_cfg___strb___lsb 3
+#define reg_iop_timer_grp_rw_tmr_cfg___strb___width 2
+#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___lsb 5
+#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___width 2
+#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___lsb 7
+#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___width 1
+#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___bit 7
+#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___lsb 8
+#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___width 2
+#define reg_iop_timer_grp_rw_tmr_cfg___inv___lsb 10
+#define reg_iop_timer_grp_rw_tmr_cfg___inv___width 1
+#define reg_iop_timer_grp_rw_tmr_cfg___inv___bit 10
+#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___lsb 11
+#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___width 2
+#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___lsb 13
+#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___width 2
+#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___lsb 15
+#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___width 1
+#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___bit 15
+#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___lsb 16
+#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___width 1
+#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___bit 16
+#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___lsb 17
+#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___width 1
+#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___bit 17
+#define reg_iop_timer_grp_rw_tmr_cfg_offset 12
+
+#define STRIDE_iop_timer_grp_rw_tmr_len 4
+/* Register rw_tmr_len, scope iop_timer_grp, type rw */
+#define reg_iop_timer_grp_rw_tmr_len___val___lsb 0
+#define reg_iop_timer_grp_rw_tmr_len___val___width 16
+#define reg_iop_timer_grp_rw_tmr_len_offset 44
+
+/* Register rw_cmd, scope iop_timer_grp, type rw */
+#define reg_iop_timer_grp_rw_cmd___rst___lsb 0
+#define reg_iop_timer_grp_rw_cmd___rst___width 4
+#define reg_iop_timer_grp_rw_cmd___en___lsb 4
+#define reg_iop_timer_grp_rw_cmd___en___width 4
+#define reg_iop_timer_grp_rw_cmd___dis___lsb 8
+#define reg_iop_timer_grp_rw_cmd___dis___width 4
+#define reg_iop_timer_grp_rw_cmd___strb___lsb 12
+#define reg_iop_timer_grp_rw_cmd___strb___width 4
+#define reg_iop_timer_grp_rw_cmd_offset 60
+
+/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */
+#define reg_iop_timer_grp_r_clk_gen_cnt_offset 64
+
+#define STRIDE_iop_timer_grp_rs_tmr_cnt 8
+/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */
+#define reg_iop_timer_grp_rs_tmr_cnt___val___lsb 0
+#define reg_iop_timer_grp_rs_tmr_cnt___val___width 16
+#define reg_iop_timer_grp_rs_tmr_cnt_offset 68
+
+#define STRIDE_iop_timer_grp_r_tmr_cnt 8
+/* Register r_tmr_cnt, scope iop_timer_grp, type r */
+#define reg_iop_timer_grp_r_tmr_cnt___val___lsb 0
+#define reg_iop_timer_grp_r_tmr_cnt___val___width 16
+#define reg_iop_timer_grp_r_tmr_cnt_offset 72
+
+/* Register rw_intr_mask, scope iop_timer_grp, type rw */
+#define reg_iop_timer_grp_rw_intr_mask___tmr0___lsb 0
+#define reg_iop_timer_grp_rw_intr_mask___tmr0___width 1
+#define reg_iop_timer_grp_rw_intr_mask___tmr0___bit 0
+#define reg_iop_timer_grp_rw_intr_mask___tmr1___lsb 1
+#define reg_iop_timer_grp_rw_intr_mask___tmr1___width 1
+#define reg_iop_timer_grp_rw_intr_mask___tmr1___bit 1
+#define reg_iop_timer_grp_rw_intr_mask___tmr2___lsb 2
+#define reg_iop_timer_grp_rw_intr_mask___tmr2___width 1
+#define reg_iop_timer_grp_rw_intr_mask___tmr2___bit 2
+#define reg_iop_timer_grp_rw_intr_mask___tmr3___lsb 3
+#define reg_iop_timer_grp_rw_intr_mask___tmr3___width 1
+#define reg_iop_timer_grp_rw_intr_mask___tmr3___bit 3
+#define reg_iop_timer_grp_rw_intr_mask_offset 100
+
+/* Register rw_ack_intr, scope iop_timer_grp, type rw */
+#define reg_iop_timer_grp_rw_ack_intr___tmr0___lsb 0
+#define reg_iop_timer_grp_rw_ack_intr___tmr0___width 1
+#define reg_iop_timer_grp_rw_ack_intr___tmr0___bit 0
+#define reg_iop_timer_grp_rw_ack_intr___tmr1___lsb 1
+#define reg_iop_timer_grp_rw_ack_intr___tmr1___width 1
+#define reg_iop_timer_grp_rw_ack_intr___tmr1___bit 1
+#define reg_iop_timer_grp_rw_ack_intr___tmr2___lsb 2
+#define reg_iop_timer_grp_rw_ack_intr___tmr2___width 1
+#define reg_iop_timer_grp_rw_ack_intr___tmr2___bit 2
+#define reg_iop_timer_grp_rw_ack_intr___tmr3___lsb 3
+#define reg_iop_timer_grp_rw_ack_intr___tmr3___width 1
+#define reg_iop_timer_grp_rw_ack_intr___tmr3___bit 3
+#define reg_iop_timer_grp_rw_ack_intr_offset 104
+
+/* Register r_intr, scope iop_timer_grp, type r */
+#define reg_iop_timer_grp_r_intr___tmr0___lsb 0
+#define reg_iop_timer_grp_r_intr___tmr0___width 1
+#define reg_iop_timer_grp_r_intr___tmr0___bit 0
+#define reg_iop_timer_grp_r_intr___tmr1___lsb 1
+#define reg_iop_timer_grp_r_intr___tmr1___width 1
+#define reg_iop_timer_grp_r_intr___tmr1___bit 1
+#define reg_iop_timer_grp_r_intr___tmr2___lsb 2
+#define reg_iop_timer_grp_r_intr___tmr2___width 1
+#define reg_iop_timer_grp_r_intr___tmr2___bit 2
+#define reg_iop_timer_grp_r_intr___tmr3___lsb 3
+#define reg_iop_timer_grp_r_intr___tmr3___width 1
+#define reg_iop_timer_grp_r_intr___tmr3___bit 3
+#define reg_iop_timer_grp_r_intr_offset 108
+
+/* Register r_masked_intr, scope iop_timer_grp, type r */
+#define reg_iop_timer_grp_r_masked_intr___tmr0___lsb 0
+#define reg_iop_timer_grp_r_masked_intr___tmr0___width 1
+#define reg_iop_timer_grp_r_masked_intr___tmr0___bit 0
+#define reg_iop_timer_grp_r_masked_intr___tmr1___lsb 1
+#define reg_iop_timer_grp_r_masked_intr___tmr1___width 1
+#define reg_iop_timer_grp_r_masked_intr___tmr1___bit 1
+#define reg_iop_timer_grp_r_masked_intr___tmr2___lsb 2
+#define reg_iop_timer_grp_r_masked_intr___tmr2___width 1
+#define reg_iop_timer_grp_r_masked_intr___tmr2___bit 2
+#define reg_iop_timer_grp_r_masked_intr___tmr3___lsb 3
+#define reg_iop_timer_grp_r_masked_intr___tmr3___width 1
+#define reg_iop_timer_grp_r_masked_intr___tmr3___bit 3
+#define reg_iop_timer_grp_r_masked_intr_offset 112
+
+
+/* Constants */
+#define regk_iop_timer_grp_clk200                 0x00000000
+#define regk_iop_timer_grp_clk_gen                0x00000002
+#define regk_iop_timer_grp_complete               0x00000002
+#define regk_iop_timer_grp_div_clk200             0x00000001
+#define regk_iop_timer_grp_div_clk_gen            0x00000003
+#define regk_iop_timer_grp_ext                    0x00000001
+#define regk_iop_timer_grp_hi                     0x00000000
+#define regk_iop_timer_grp_long_period            0x00000001
+#define regk_iop_timer_grp_neg                    0x00000002
+#define regk_iop_timer_grp_no                     0x00000000
+#define regk_iop_timer_grp_once                   0x00000003
+#define regk_iop_timer_grp_pause                  0x00000001
+#define regk_iop_timer_grp_pos                    0x00000001
+#define regk_iop_timer_grp_pos_neg                0x00000003
+#define regk_iop_timer_grp_pulse                  0x00000000
+#define regk_iop_timer_grp_r_tmr_cnt_size         0x00000004
+#define regk_iop_timer_grp_rs_tmr_cnt_size        0x00000004
+#define regk_iop_timer_grp_rw_cfg_default         0x00000002
+#define regk_iop_timer_grp_rw_intr_mask_default   0x00000000
+#define regk_iop_timer_grp_rw_tmr_cfg_default0    0x00018000
+#define regk_iop_timer_grp_rw_tmr_cfg_default1    0x0001a900
+#define regk_iop_timer_grp_rw_tmr_cfg_default2    0x0001d200
+#define regk_iop_timer_grp_rw_tmr_cfg_default3    0x0001fb00
+#define regk_iop_timer_grp_rw_tmr_cfg_size        0x00000004
+#define regk_iop_timer_grp_rw_tmr_len_default     0x00000000
+#define regk_iop_timer_grp_rw_tmr_len_size        0x00000004
+#define regk_iop_timer_grp_short_period           0x00000000
+#define regk_iop_timer_grp_stop                   0x00000000
+#define regk_iop_timer_grp_tmr                    0x00000004
+#define regk_iop_timer_grp_toggle                 0x00000001
+#define regk_iop_timer_grp_yes                    0x00000001
+#endif /* __iop_timer_grp_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h
new file mode 100644
index 00000000000..1005d9db80d
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_trigger_grp_defs_asm.h
@@ -0,0 +1,157 @@
+#ifndef __iop_trigger_grp_defs_asm_h
+#define __iop_trigger_grp_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_trigger_grp.r
+ *     id:           iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_trigger_grp_defs_asm.h ../../inst/io_proc/rtl/iop_trigger_grp.r
+ *      id: $Id: iop_trigger_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+#define STRIDE_iop_trigger_grp_rw_cfg 4
+/* Register rw_cfg, scope iop_trigger_grp, type rw */
+#define reg_iop_trigger_grp_rw_cfg___action___lsb 0
+#define reg_iop_trigger_grp_rw_cfg___action___width 2
+#define reg_iop_trigger_grp_rw_cfg___once___lsb 2
+#define reg_iop_trigger_grp_rw_cfg___once___width 1
+#define reg_iop_trigger_grp_rw_cfg___once___bit 2
+#define reg_iop_trigger_grp_rw_cfg___trig___lsb 3
+#define reg_iop_trigger_grp_rw_cfg___trig___width 3
+#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___lsb 6
+#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___width 1
+#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___bit 6
+#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___lsb 7
+#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___width 1
+#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___bit 7
+#define reg_iop_trigger_grp_rw_cfg_offset 0
+
+/* Register rw_cmd, scope iop_trigger_grp, type rw */
+#define reg_iop_trigger_grp_rw_cmd___dis___lsb 0
+#define reg_iop_trigger_grp_rw_cmd___dis___width 4
+#define reg_iop_trigger_grp_rw_cmd___en___lsb 4
+#define reg_iop_trigger_grp_rw_cmd___en___width 4
+#define reg_iop_trigger_grp_rw_cmd_offset 16
+
+/* Register rw_intr_mask, scope iop_trigger_grp, type rw */
+#define reg_iop_trigger_grp_rw_intr_mask___trig0___lsb 0
+#define reg_iop_trigger_grp_rw_intr_mask___trig0___width 1
+#define reg_iop_trigger_grp_rw_intr_mask___trig0___bit 0
+#define reg_iop_trigger_grp_rw_intr_mask___trig1___lsb 1
+#define reg_iop_trigger_grp_rw_intr_mask___trig1___width 1
+#define reg_iop_trigger_grp_rw_intr_mask___trig1___bit 1
+#define reg_iop_trigger_grp_rw_intr_mask___trig2___lsb 2
+#define reg_iop_trigger_grp_rw_intr_mask___trig2___width 1
+#define reg_iop_trigger_grp_rw_intr_mask___trig2___bit 2
+#define reg_iop_trigger_grp_rw_intr_mask___trig3___lsb 3
+#define reg_iop_trigger_grp_rw_intr_mask___trig3___width 1
+#define reg_iop_trigger_grp_rw_intr_mask___trig3___bit 3
+#define reg_iop_trigger_grp_rw_intr_mask_offset 20
+
+/* Register rw_ack_intr, scope iop_trigger_grp, type rw */
+#define reg_iop_trigger_grp_rw_ack_intr___trig0___lsb 0
+#define reg_iop_trigger_grp_rw_ack_intr___trig0___width 1
+#define reg_iop_trigger_grp_rw_ack_intr___trig0___bit 0
+#define reg_iop_trigger_grp_rw_ack_intr___trig1___lsb 1
+#define reg_iop_trigger_grp_rw_ack_intr___trig1___width 1
+#define reg_iop_trigger_grp_rw_ack_intr___trig1___bit 1
+#define reg_iop_trigger_grp_rw_ack_intr___trig2___lsb 2
+#define reg_iop_trigger_grp_rw_ack_intr___trig2___width 1
+#define reg_iop_trigger_grp_rw_ack_intr___trig2___bit 2
+#define reg_iop_trigger_grp_rw_ack_intr___trig3___lsb 3
+#define reg_iop_trigger_grp_rw_ack_intr___trig3___width 1
+#define reg_iop_trigger_grp_rw_ack_intr___trig3___bit 3
+#define reg_iop_trigger_grp_rw_ack_intr_offset 24
+
+/* Register r_intr, scope iop_trigger_grp, type r */
+#define reg_iop_trigger_grp_r_intr___trig0___lsb 0
+#define reg_iop_trigger_grp_r_intr___trig0___width 1
+#define reg_iop_trigger_grp_r_intr___trig0___bit 0
+#define reg_iop_trigger_grp_r_intr___trig1___lsb 1
+#define reg_iop_trigger_grp_r_intr___trig1___width 1
+#define reg_iop_trigger_grp_r_intr___trig1___bit 1
+#define reg_iop_trigger_grp_r_intr___trig2___lsb 2
+#define reg_iop_trigger_grp_r_intr___trig2___width 1
+#define reg_iop_trigger_grp_r_intr___trig2___bit 2
+#define reg_iop_trigger_grp_r_intr___trig3___lsb 3
+#define reg_iop_trigger_grp_r_intr___trig3___width 1
+#define reg_iop_trigger_grp_r_intr___trig3___bit 3
+#define reg_iop_trigger_grp_r_intr_offset 28
+
+/* Register r_masked_intr, scope iop_trigger_grp, type r */
+#define reg_iop_trigger_grp_r_masked_intr___trig0___lsb 0
+#define reg_iop_trigger_grp_r_masked_intr___trig0___width 1
+#define reg_iop_trigger_grp_r_masked_intr___trig0___bit 0
+#define reg_iop_trigger_grp_r_masked_intr___trig1___lsb 1
+#define reg_iop_trigger_grp_r_masked_intr___trig1___width 1
+#define reg_iop_trigger_grp_r_masked_intr___trig1___bit 1
+#define reg_iop_trigger_grp_r_masked_intr___trig2___lsb 2
+#define reg_iop_trigger_grp_r_masked_intr___trig2___width 1
+#define reg_iop_trigger_grp_r_masked_intr___trig2___bit 2
+#define reg_iop_trigger_grp_r_masked_intr___trig3___lsb 3
+#define reg_iop_trigger_grp_r_masked_intr___trig3___width 1
+#define reg_iop_trigger_grp_r_masked_intr___trig3___bit 3
+#define reg_iop_trigger_grp_r_masked_intr_offset 32
+
+
+/* Constants */
+#define regk_iop_trigger_grp_fall                 0x00000002
+#define regk_iop_trigger_grp_fall_lo              0x00000006
+#define regk_iop_trigger_grp_no                   0x00000000
+#define regk_iop_trigger_grp_off                  0x00000000
+#define regk_iop_trigger_grp_pulse                0x00000000
+#define regk_iop_trigger_grp_rise                 0x00000001
+#define regk_iop_trigger_grp_rise_fall            0x00000003
+#define regk_iop_trigger_grp_rise_fall_hi         0x00000007
+#define regk_iop_trigger_grp_rise_fall_lo         0x00000004
+#define regk_iop_trigger_grp_rise_hi              0x00000005
+#define regk_iop_trigger_grp_rw_cfg_default       0x000000c0
+#define regk_iop_trigger_grp_rw_cfg_size          0x00000004
+#define regk_iop_trigger_grp_rw_intr_mask_default  0x00000000
+#define regk_iop_trigger_grp_toggle               0x00000003
+#define regk_iop_trigger_grp_yes                  0x00000001
+#endif /* __iop_trigger_grp_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h
new file mode 100644
index 00000000000..e13feb20a7e
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/asm/iop_version_defs_asm.h
@@ -0,0 +1,64 @@
+#ifndef __iop_version_defs_asm_h
+#define __iop_version_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/guinness/iop_version.r
+ *     id:           iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp
+ *     last modfied: Mon Apr 11 16:08:44 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_version_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_version.r
+ *      id: $Id: iop_version_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register r_version, scope iop_version, type r */
+#define reg_iop_version_r_version___nr___lsb 0
+#define reg_iop_version_r_version___nr___width 8
+#define reg_iop_version_r_version_offset 0
+
+
+/* Constants */
+#define regk_iop_version_v1_0                     0x00000001
+#endif /* __iop_version_defs_asm_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h
new file mode 100644
index 00000000000..90e4785b647
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_crc_par_defs.h
@@ -0,0 +1,232 @@
+#ifndef __iop_crc_par_defs_h
+#define __iop_crc_par_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_crc_par.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:08:45 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_crc_par_defs.h ../../inst/io_proc/rtl/iop_crc_par.r
+ *      id: $Id: iop_crc_par_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_crc_par */
+
+/* Register rw_cfg, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int mode    : 1;
+  unsigned int crc_out : 1;
+  unsigned int rev_out : 1;
+  unsigned int inv_out : 1;
+  unsigned int trig    : 2;
+  unsigned int poly    : 3;
+  unsigned int dummy1  : 23;
+} reg_iop_crc_par_rw_cfg;
+#define REG_RD_ADDR_iop_crc_par_rw_cfg 0
+#define REG_WR_ADDR_iop_crc_par_rw_cfg 0
+
+/* Register rw_init_crc, scope iop_crc_par, type rw */
+typedef unsigned int reg_iop_crc_par_rw_init_crc;
+#define REG_RD_ADDR_iop_crc_par_rw_init_crc 4
+#define REG_WR_ADDR_iop_crc_par_rw_init_crc 4
+
+/* Register rw_correct_crc, scope iop_crc_par, type rw */
+typedef unsigned int reg_iop_crc_par_rw_correct_crc;
+#define REG_RD_ADDR_iop_crc_par_rw_correct_crc 8
+#define REG_WR_ADDR_iop_crc_par_rw_correct_crc 8
+
+/* Register rw_ctrl, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int en : 1;
+  unsigned int dummy1 : 31;
+} reg_iop_crc_par_rw_ctrl;
+#define REG_RD_ADDR_iop_crc_par_rw_ctrl 12
+#define REG_WR_ADDR_iop_crc_par_rw_ctrl 12
+
+/* Register rw_set_last, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int tr_dif : 1;
+  unsigned int dummy1 : 31;
+} reg_iop_crc_par_rw_set_last;
+#define REG_RD_ADDR_iop_crc_par_rw_set_last 16
+#define REG_WR_ADDR_iop_crc_par_rw_set_last 16
+
+/* Register rw_wr1byte, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int data : 8;
+  unsigned int dummy1 : 24;
+} reg_iop_crc_par_rw_wr1byte;
+#define REG_RD_ADDR_iop_crc_par_rw_wr1byte 20
+#define REG_WR_ADDR_iop_crc_par_rw_wr1byte 20
+
+/* Register rw_wr2byte, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int data : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_crc_par_rw_wr2byte;
+#define REG_RD_ADDR_iop_crc_par_rw_wr2byte 24
+#define REG_WR_ADDR_iop_crc_par_rw_wr2byte 24
+
+/* Register rw_wr3byte, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int data : 24;
+  unsigned int dummy1 : 8;
+} reg_iop_crc_par_rw_wr3byte;
+#define REG_RD_ADDR_iop_crc_par_rw_wr3byte 28
+#define REG_WR_ADDR_iop_crc_par_rw_wr3byte 28
+
+/* Register rw_wr4byte, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int data : 32;
+} reg_iop_crc_par_rw_wr4byte;
+#define REG_RD_ADDR_iop_crc_par_rw_wr4byte 32
+#define REG_WR_ADDR_iop_crc_par_rw_wr4byte 32
+
+/* Register rw_wr1byte_last, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int data : 8;
+  unsigned int dummy1 : 24;
+} reg_iop_crc_par_rw_wr1byte_last;
+#define REG_RD_ADDR_iop_crc_par_rw_wr1byte_last 36
+#define REG_WR_ADDR_iop_crc_par_rw_wr1byte_last 36
+
+/* Register rw_wr2byte_last, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int data : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_crc_par_rw_wr2byte_last;
+#define REG_RD_ADDR_iop_crc_par_rw_wr2byte_last 40
+#define REG_WR_ADDR_iop_crc_par_rw_wr2byte_last 40
+
+/* Register rw_wr3byte_last, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int data : 24;
+  unsigned int dummy1 : 8;
+} reg_iop_crc_par_rw_wr3byte_last;
+#define REG_RD_ADDR_iop_crc_par_rw_wr3byte_last 44
+#define REG_WR_ADDR_iop_crc_par_rw_wr3byte_last 44
+
+/* Register rw_wr4byte_last, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int data : 32;
+} reg_iop_crc_par_rw_wr4byte_last;
+#define REG_RD_ADDR_iop_crc_par_rw_wr4byte_last 48
+#define REG_WR_ADDR_iop_crc_par_rw_wr4byte_last 48
+
+/* Register r_stat, scope iop_crc_par, type r */
+typedef struct {
+  unsigned int err  : 1;
+  unsigned int busy : 1;
+  unsigned int dummy1 : 30;
+} reg_iop_crc_par_r_stat;
+#define REG_RD_ADDR_iop_crc_par_r_stat 52
+
+/* Register r_sh_reg, scope iop_crc_par, type r */
+typedef unsigned int reg_iop_crc_par_r_sh_reg;
+#define REG_RD_ADDR_iop_crc_par_r_sh_reg 56
+
+/* Register r_crc, scope iop_crc_par, type r */
+typedef unsigned int reg_iop_crc_par_r_crc;
+#define REG_RD_ADDR_iop_crc_par_r_crc 60
+
+/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */
+typedef struct {
+  unsigned int last : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_crc_par_rw_strb_rec_dif_in;
+#define REG_RD_ADDR_iop_crc_par_rw_strb_rec_dif_in 64
+#define REG_WR_ADDR_iop_crc_par_rw_strb_rec_dif_in 64
+
+
+/* Constants */
+enum {
+  regk_iop_crc_par_calc                    = 0x00000001,
+  regk_iop_crc_par_ccitt                   = 0x00000002,
+  regk_iop_crc_par_check                   = 0x00000000,
+  regk_iop_crc_par_crc16                   = 0x00000001,
+  regk_iop_crc_par_crc32                   = 0x00000000,
+  regk_iop_crc_par_crc5                    = 0x00000003,
+  regk_iop_crc_par_crc5_11                 = 0x00000004,
+  regk_iop_crc_par_dif_in                  = 0x00000002,
+  regk_iop_crc_par_hi                      = 0x00000000,
+  regk_iop_crc_par_neg                     = 0x00000002,
+  regk_iop_crc_par_no                      = 0x00000000,
+  regk_iop_crc_par_pos                     = 0x00000001,
+  regk_iop_crc_par_pos_neg                 = 0x00000003,
+  regk_iop_crc_par_rw_cfg_default          = 0x00000000,
+  regk_iop_crc_par_rw_ctrl_default         = 0x00000000,
+  regk_iop_crc_par_yes                     = 0x00000001
+};
+#endif /* __iop_crc_par_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h
new file mode 100644
index 00000000000..76aec6e37f3
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_in_defs.h
@@ -0,0 +1,325 @@
+#ifndef __iop_dmc_in_defs_h
+#define __iop_dmc_in_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_dmc_in.r
+ *     id:           iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:45 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_in_defs.h ../../inst/io_proc/rtl/iop_dmc_in.r
+ *      id: $Id: iop_dmc_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_dmc_in */
+
+/* Register rw_cfg, scope iop_dmc_in, type rw */
+typedef struct {
+  unsigned int sth_intr     : 3;
+  unsigned int last_dis_dif : 1;
+  unsigned int dummy1       : 28;
+} reg_iop_dmc_in_rw_cfg;
+#define REG_RD_ADDR_iop_dmc_in_rw_cfg 0
+#define REG_WR_ADDR_iop_dmc_in_rw_cfg 0
+
+/* Register rw_ctrl, scope iop_dmc_in, type rw */
+typedef struct {
+  unsigned int dif_en     : 1;
+  unsigned int dif_dis    : 1;
+  unsigned int stream_clr : 1;
+  unsigned int dummy1     : 29;
+} reg_iop_dmc_in_rw_ctrl;
+#define REG_RD_ADDR_iop_dmc_in_rw_ctrl 4
+#define REG_WR_ADDR_iop_dmc_in_rw_ctrl 4
+
+/* Register r_stat, scope iop_dmc_in, type r */
+typedef struct {
+  unsigned int dif_en : 1;
+  unsigned int dummy1 : 31;
+} reg_iop_dmc_in_r_stat;
+#define REG_RD_ADDR_iop_dmc_in_r_stat 8
+
+/* Register rw_stream_cmd, scope iop_dmc_in, type rw */
+typedef struct {
+  unsigned int cmd : 10;
+  unsigned int dummy1 : 6;
+  unsigned int n   : 8;
+  unsigned int dummy2 : 8;
+} reg_iop_dmc_in_rw_stream_cmd;
+#define REG_RD_ADDR_iop_dmc_in_rw_stream_cmd 12
+#define REG_WR_ADDR_iop_dmc_in_rw_stream_cmd 12
+
+/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */
+typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data;
+#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data 16
+#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data 16
+
+/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */
+typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data_last;
+#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data_last 20
+#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data_last 20
+
+/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */
+typedef struct {
+  unsigned int eop     : 1;
+  unsigned int wait    : 1;
+  unsigned int keep_md : 1;
+  unsigned int size    : 3;
+  unsigned int dummy1  : 26;
+} reg_iop_dmc_in_rw_stream_ctrl;
+#define REG_RD_ADDR_iop_dmc_in_rw_stream_ctrl 24
+#define REG_WR_ADDR_iop_dmc_in_rw_stream_ctrl 24
+
+/* Register r_stream_stat, scope iop_dmc_in, type r */
+typedef struct {
+  unsigned int sth            : 7;
+  unsigned int dummy1         : 9;
+  unsigned int full           : 1;
+  unsigned int last_pkt       : 1;
+  unsigned int data_md_valid  : 1;
+  unsigned int ctxt_md_valid  : 1;
+  unsigned int group_md_valid : 1;
+  unsigned int stream_busy    : 1;
+  unsigned int cmd_rdy        : 1;
+  unsigned int dummy2         : 9;
+} reg_iop_dmc_in_r_stream_stat;
+#define REG_RD_ADDR_iop_dmc_in_r_stream_stat 28
+
+/* Register r_data_descr, scope iop_dmc_in, type r */
+typedef struct {
+  unsigned int ctrl : 8;
+  unsigned int stat : 8;
+  unsigned int md   : 16;
+} reg_iop_dmc_in_r_data_descr;
+#define REG_RD_ADDR_iop_dmc_in_r_data_descr 32
+
+/* Register r_ctxt_descr, scope iop_dmc_in, type r */
+typedef struct {
+  unsigned int ctrl : 8;
+  unsigned int stat : 8;
+  unsigned int md0  : 16;
+} reg_iop_dmc_in_r_ctxt_descr;
+#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr 36
+
+/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */
+typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md1;
+#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md1 40
+
+/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */
+typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md2;
+#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md2 44
+
+/* Register r_group_descr, scope iop_dmc_in, type r */
+typedef struct {
+  unsigned int ctrl : 8;
+  unsigned int stat : 8;
+  unsigned int md   : 16;
+} reg_iop_dmc_in_r_group_descr;
+#define REG_RD_ADDR_iop_dmc_in_r_group_descr 56
+
+/* Register rw_data_descr, scope iop_dmc_in, type rw */
+typedef struct {
+  unsigned int dummy1 : 16;
+  unsigned int md : 16;
+} reg_iop_dmc_in_rw_data_descr;
+#define REG_RD_ADDR_iop_dmc_in_rw_data_descr 60
+#define REG_WR_ADDR_iop_dmc_in_rw_data_descr 60
+
+/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */
+typedef struct {
+  unsigned int dummy1 : 16;
+  unsigned int md0 : 16;
+} reg_iop_dmc_in_rw_ctxt_descr;
+#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr 64
+#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr 64
+
+/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */
+typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md1;
+#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68
+#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68
+
+/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */
+typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md2;
+#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72
+#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72
+
+/* Register rw_group_descr, scope iop_dmc_in, type rw */
+typedef struct {
+  unsigned int dummy1 : 16;
+  unsigned int md : 16;
+} reg_iop_dmc_in_rw_group_descr;
+#define REG_RD_ADDR_iop_dmc_in_rw_group_descr 84
+#define REG_WR_ADDR_iop_dmc_in_rw_group_descr 84
+
+/* Register rw_intr_mask, scope iop_dmc_in, type rw */
+typedef struct {
+  unsigned int data_md  : 1;
+  unsigned int ctxt_md  : 1;
+  unsigned int group_md : 1;
+  unsigned int cmd_rdy  : 1;
+  unsigned int sth      : 1;
+  unsigned int full     : 1;
+  unsigned int dummy1   : 26;
+} reg_iop_dmc_in_rw_intr_mask;
+#define REG_RD_ADDR_iop_dmc_in_rw_intr_mask 88
+#define REG_WR_ADDR_iop_dmc_in_rw_intr_mask 88
+
+/* Register rw_ack_intr, scope iop_dmc_in, type rw */
+typedef struct {
+  unsigned int data_md  : 1;
+  unsigned int ctxt_md  : 1;
+  unsigned int group_md : 1;
+  unsigned int cmd_rdy  : 1;
+  unsigned int sth      : 1;
+  unsigned int full     : 1;
+  unsigned int dummy1   : 26;
+} reg_iop_dmc_in_rw_ack_intr;
+#define REG_RD_ADDR_iop_dmc_in_rw_ack_intr 92
+#define REG_WR_ADDR_iop_dmc_in_rw_ack_intr 92
+
+/* Register r_intr, scope iop_dmc_in, type r */
+typedef struct {
+  unsigned int data_md  : 1;
+  unsigned int ctxt_md  : 1;
+  unsigned int group_md : 1;
+  unsigned int cmd_rdy  : 1;
+  unsigned int sth      : 1;
+  unsigned int full     : 1;
+  unsigned int dummy1   : 26;
+} reg_iop_dmc_in_r_intr;
+#define REG_RD_ADDR_iop_dmc_in_r_intr 96
+
+/* Register r_masked_intr, scope iop_dmc_in, type r */
+typedef struct {
+  unsigned int data_md  : 1;
+  unsigned int ctxt_md  : 1;
+  unsigned int group_md : 1;
+  unsigned int cmd_rdy  : 1;
+  unsigned int sth      : 1;
+  unsigned int full     : 1;
+  unsigned int dummy1   : 26;
+} reg_iop_dmc_in_r_masked_intr;
+#define REG_RD_ADDR_iop_dmc_in_r_masked_intr 100
+
+
+/* Constants */
+enum {
+  regk_iop_dmc_in_ack_pkt                  = 0x00000100,
+  regk_iop_dmc_in_array                    = 0x00000008,
+  regk_iop_dmc_in_burst                    = 0x00000020,
+  regk_iop_dmc_in_copy_next                = 0x00000010,
+  regk_iop_dmc_in_copy_up                  = 0x00000020,
+  regk_iop_dmc_in_dis_c                    = 0x00000010,
+  regk_iop_dmc_in_dis_g                    = 0x00000020,
+  regk_iop_dmc_in_lim1                     = 0x00000000,
+  regk_iop_dmc_in_lim16                    = 0x00000004,
+  regk_iop_dmc_in_lim2                     = 0x00000001,
+  regk_iop_dmc_in_lim32                    = 0x00000005,
+  regk_iop_dmc_in_lim4                     = 0x00000002,
+  regk_iop_dmc_in_lim64                    = 0x00000006,
+  regk_iop_dmc_in_lim8                     = 0x00000003,
+  regk_iop_dmc_in_load_c                   = 0x00000200,
+  regk_iop_dmc_in_load_c_n                 = 0x00000280,
+  regk_iop_dmc_in_load_c_next              = 0x00000240,
+  regk_iop_dmc_in_load_d                   = 0x00000140,
+  regk_iop_dmc_in_load_g                   = 0x00000300,
+  regk_iop_dmc_in_load_g_down              = 0x000003c0,
+  regk_iop_dmc_in_load_g_next              = 0x00000340,
+  regk_iop_dmc_in_load_g_up                = 0x00000380,
+  regk_iop_dmc_in_next_en                  = 0x00000010,
+  regk_iop_dmc_in_next_pkt                 = 0x00000010,
+  regk_iop_dmc_in_no                       = 0x00000000,
+  regk_iop_dmc_in_restore                  = 0x00000020,
+  regk_iop_dmc_in_rw_cfg_default           = 0x00000000,
+  regk_iop_dmc_in_rw_ctxt_descr_default    = 0x00000000,
+  regk_iop_dmc_in_rw_ctxt_descr_md1_default = 0x00000000,
+  regk_iop_dmc_in_rw_ctxt_descr_md2_default = 0x00000000,
+  regk_iop_dmc_in_rw_data_descr_default    = 0x00000000,
+  regk_iop_dmc_in_rw_group_descr_default   = 0x00000000,
+  regk_iop_dmc_in_rw_intr_mask_default     = 0x00000000,
+  regk_iop_dmc_in_rw_stream_ctrl_default   = 0x00000000,
+  regk_iop_dmc_in_save_down                = 0x00000020,
+  regk_iop_dmc_in_save_up                  = 0x00000020,
+  regk_iop_dmc_in_set_reg                  = 0x00000050,
+  regk_iop_dmc_in_set_w_size1              = 0x00000190,
+  regk_iop_dmc_in_set_w_size2              = 0x000001a0,
+  regk_iop_dmc_in_set_w_size4              = 0x000001c0,
+  regk_iop_dmc_in_store_c                  = 0x00000002,
+  regk_iop_dmc_in_store_descr              = 0x00000000,
+  regk_iop_dmc_in_store_g                  = 0x00000004,
+  regk_iop_dmc_in_store_md                 = 0x00000001,
+  regk_iop_dmc_in_update_down              = 0x00000020,
+  regk_iop_dmc_in_yes                      = 0x00000001
+};
+#endif /* __iop_dmc_in_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h
new file mode 100644
index 00000000000..938a0d4c460
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_dmc_out_defs.h
@@ -0,0 +1,326 @@
+#ifndef __iop_dmc_out_defs_h
+#define __iop_dmc_out_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_dmc_out.r
+ *     id:           iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:45 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_out_defs.h ../../inst/io_proc/rtl/iop_dmc_out.r
+ *      id: $Id: iop_dmc_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_dmc_out */
+
+/* Register rw_cfg, scope iop_dmc_out, type rw */
+typedef struct {
+  unsigned int trf_lim         : 16;
+  unsigned int last_at_trf_lim : 1;
+  unsigned int dth_intr        : 3;
+  unsigned int dummy1          : 12;
+} reg_iop_dmc_out_rw_cfg;
+#define REG_RD_ADDR_iop_dmc_out_rw_cfg 0
+#define REG_WR_ADDR_iop_dmc_out_rw_cfg 0
+
+/* Register rw_ctrl, scope iop_dmc_out, type rw */
+typedef struct {
+  unsigned int dif_en  : 1;
+  unsigned int dif_dis : 1;
+  unsigned int dummy1  : 30;
+} reg_iop_dmc_out_rw_ctrl;
+#define REG_RD_ADDR_iop_dmc_out_rw_ctrl 4
+#define REG_WR_ADDR_iop_dmc_out_rw_ctrl 4
+
+/* Register r_stat, scope iop_dmc_out, type r */
+typedef struct {
+  unsigned int dif_en : 1;
+  unsigned int dummy1 : 31;
+} reg_iop_dmc_out_r_stat;
+#define REG_RD_ADDR_iop_dmc_out_r_stat 8
+
+/* Register rw_stream_cmd, scope iop_dmc_out, type rw */
+typedef struct {
+  unsigned int cmd : 10;
+  unsigned int dummy1 : 6;
+  unsigned int n   : 8;
+  unsigned int dummy2 : 8;
+} reg_iop_dmc_out_rw_stream_cmd;
+#define REG_RD_ADDR_iop_dmc_out_rw_stream_cmd 12
+#define REG_WR_ADDR_iop_dmc_out_rw_stream_cmd 12
+
+/* Register rs_stream_data, scope iop_dmc_out, type rs */
+typedef unsigned int reg_iop_dmc_out_rs_stream_data;
+#define REG_RD_ADDR_iop_dmc_out_rs_stream_data 16
+
+/* Register r_stream_data, scope iop_dmc_out, type r */
+typedef unsigned int reg_iop_dmc_out_r_stream_data;
+#define REG_RD_ADDR_iop_dmc_out_r_stream_data 20
+
+/* Register r_stream_stat, scope iop_dmc_out, type r */
+typedef struct {
+  unsigned int dth            : 7;
+  unsigned int dummy1         : 9;
+  unsigned int dv             : 1;
+  unsigned int all_avail      : 1;
+  unsigned int last           : 1;
+  unsigned int size           : 3;
+  unsigned int data_md_valid  : 1;
+  unsigned int ctxt_md_valid  : 1;
+  unsigned int group_md_valid : 1;
+  unsigned int stream_busy    : 1;
+  unsigned int cmd_rdy        : 1;
+  unsigned int cmd_rq         : 1;
+  unsigned int dummy2         : 4;
+} reg_iop_dmc_out_r_stream_stat;
+#define REG_RD_ADDR_iop_dmc_out_r_stream_stat 24
+
+/* Register r_data_descr, scope iop_dmc_out, type r */
+typedef struct {
+  unsigned int ctrl : 8;
+  unsigned int stat : 8;
+  unsigned int md   : 16;
+} reg_iop_dmc_out_r_data_descr;
+#define REG_RD_ADDR_iop_dmc_out_r_data_descr 28
+
+/* Register r_ctxt_descr, scope iop_dmc_out, type r */
+typedef struct {
+  unsigned int ctrl : 8;
+  unsigned int stat : 8;
+  unsigned int md0  : 16;
+} reg_iop_dmc_out_r_ctxt_descr;
+#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr 32
+
+/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */
+typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md1;
+#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md1 36
+
+/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */
+typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md2;
+#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md2 40
+
+/* Register r_group_descr, scope iop_dmc_out, type r */
+typedef struct {
+  unsigned int ctrl : 8;
+  unsigned int stat : 8;
+  unsigned int md   : 16;
+} reg_iop_dmc_out_r_group_descr;
+#define REG_RD_ADDR_iop_dmc_out_r_group_descr 52
+
+/* Register rw_data_descr, scope iop_dmc_out, type rw */
+typedef struct {
+  unsigned int dummy1 : 16;
+  unsigned int md : 16;
+} reg_iop_dmc_out_rw_data_descr;
+#define REG_RD_ADDR_iop_dmc_out_rw_data_descr 56
+#define REG_WR_ADDR_iop_dmc_out_rw_data_descr 56
+
+/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */
+typedef struct {
+  unsigned int dummy1 : 16;
+  unsigned int md0 : 16;
+} reg_iop_dmc_out_rw_ctxt_descr;
+#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr 60
+#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr 60
+
+/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */
+typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md1;
+#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64
+#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64
+
+/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */
+typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md2;
+#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68
+#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68
+
+/* Register rw_group_descr, scope iop_dmc_out, type rw */
+typedef struct {
+  unsigned int dummy1 : 16;
+  unsigned int md : 16;
+} reg_iop_dmc_out_rw_group_descr;
+#define REG_RD_ADDR_iop_dmc_out_rw_group_descr 80
+#define REG_WR_ADDR_iop_dmc_out_rw_group_descr 80
+
+/* Register rw_intr_mask, scope iop_dmc_out, type rw */
+typedef struct {
+  unsigned int data_md   : 1;
+  unsigned int ctxt_md   : 1;
+  unsigned int group_md  : 1;
+  unsigned int cmd_rdy   : 1;
+  unsigned int dth       : 1;
+  unsigned int dv        : 1;
+  unsigned int last_data : 1;
+  unsigned int trf_lim   : 1;
+  unsigned int cmd_rq    : 1;
+  unsigned int dummy1    : 23;
+} reg_iop_dmc_out_rw_intr_mask;
+#define REG_RD_ADDR_iop_dmc_out_rw_intr_mask 84
+#define REG_WR_ADDR_iop_dmc_out_rw_intr_mask 84
+
+/* Register rw_ack_intr, scope iop_dmc_out, type rw */
+typedef struct {
+  unsigned int data_md   : 1;
+  unsigned int ctxt_md   : 1;
+  unsigned int group_md  : 1;
+  unsigned int cmd_rdy   : 1;
+  unsigned int dth       : 1;
+  unsigned int dv        : 1;
+  unsigned int last_data : 1;
+  unsigned int trf_lim   : 1;
+  unsigned int cmd_rq    : 1;
+  unsigned int dummy1    : 23;
+} reg_iop_dmc_out_rw_ack_intr;
+#define REG_RD_ADDR_iop_dmc_out_rw_ack_intr 88
+#define REG_WR_ADDR_iop_dmc_out_rw_ack_intr 88
+
+/* Register r_intr, scope iop_dmc_out, type r */
+typedef struct {
+  unsigned int data_md   : 1;
+  unsigned int ctxt_md   : 1;
+  unsigned int group_md  : 1;
+  unsigned int cmd_rdy   : 1;
+  unsigned int dth       : 1;
+  unsigned int dv        : 1;
+  unsigned int last_data : 1;
+  unsigned int trf_lim   : 1;
+  unsigned int cmd_rq    : 1;
+  unsigned int dummy1    : 23;
+} reg_iop_dmc_out_r_intr;
+#define REG_RD_ADDR_iop_dmc_out_r_intr 92
+
+/* Register r_masked_intr, scope iop_dmc_out, type r */
+typedef struct {
+  unsigned int data_md   : 1;
+  unsigned int ctxt_md   : 1;
+  unsigned int group_md  : 1;
+  unsigned int cmd_rdy   : 1;
+  unsigned int dth       : 1;
+  unsigned int dv        : 1;
+  unsigned int last_data : 1;
+  unsigned int trf_lim   : 1;
+  unsigned int cmd_rq    : 1;
+  unsigned int dummy1    : 23;
+} reg_iop_dmc_out_r_masked_intr;
+#define REG_RD_ADDR_iop_dmc_out_r_masked_intr 96
+
+
+/* Constants */
+enum {
+  regk_iop_dmc_out_ack_pkt                 = 0x00000100,
+  regk_iop_dmc_out_array                   = 0x00000008,
+  regk_iop_dmc_out_burst                   = 0x00000020,
+  regk_iop_dmc_out_copy_next               = 0x00000010,
+  regk_iop_dmc_out_copy_up                 = 0x00000020,
+  regk_iop_dmc_out_dis_c                   = 0x00000010,
+  regk_iop_dmc_out_dis_g                   = 0x00000020,
+  regk_iop_dmc_out_lim1                    = 0x00000000,
+  regk_iop_dmc_out_lim16                   = 0x00000004,
+  regk_iop_dmc_out_lim2                    = 0x00000001,
+  regk_iop_dmc_out_lim32                   = 0x00000005,
+  regk_iop_dmc_out_lim4                    = 0x00000002,
+  regk_iop_dmc_out_lim64                   = 0x00000006,
+  regk_iop_dmc_out_lim8                    = 0x00000003,
+  regk_iop_dmc_out_load_c                  = 0x00000200,
+  regk_iop_dmc_out_load_c_n                = 0x00000280,
+  regk_iop_dmc_out_load_c_next             = 0x00000240,
+  regk_iop_dmc_out_load_d                  = 0x00000140,
+  regk_iop_dmc_out_load_g                  = 0x00000300,
+  regk_iop_dmc_out_load_g_down             = 0x000003c0,
+  regk_iop_dmc_out_load_g_next             = 0x00000340,
+  regk_iop_dmc_out_load_g_up               = 0x00000380,
+  regk_iop_dmc_out_next_en                 = 0x00000010,
+  regk_iop_dmc_out_next_pkt                = 0x00000010,
+  regk_iop_dmc_out_no                      = 0x00000000,
+  regk_iop_dmc_out_restore                 = 0x00000020,
+  regk_iop_dmc_out_rw_cfg_default          = 0x00000000,
+  regk_iop_dmc_out_rw_ctxt_descr_default   = 0x00000000,
+  regk_iop_dmc_out_rw_ctxt_descr_md1_default = 0x00000000,
+  regk_iop_dmc_out_rw_ctxt_descr_md2_default = 0x00000000,
+  regk_iop_dmc_out_rw_data_descr_default   = 0x00000000,
+  regk_iop_dmc_out_rw_group_descr_default  = 0x00000000,
+  regk_iop_dmc_out_rw_intr_mask_default    = 0x00000000,
+  regk_iop_dmc_out_save_down               = 0x00000020,
+  regk_iop_dmc_out_save_up                 = 0x00000020,
+  regk_iop_dmc_out_set_reg                 = 0x00000050,
+  regk_iop_dmc_out_set_w_size1             = 0x00000190,
+  regk_iop_dmc_out_set_w_size2             = 0x000001a0,
+  regk_iop_dmc_out_set_w_size4             = 0x000001c0,
+  regk_iop_dmc_out_store_c                 = 0x00000002,
+  regk_iop_dmc_out_store_descr             = 0x00000000,
+  regk_iop_dmc_out_store_g                 = 0x00000004,
+  regk_iop_dmc_out_store_md                = 0x00000001,
+  regk_iop_dmc_out_update_down             = 0x00000020,
+  regk_iop_dmc_out_yes                     = 0x00000001
+};
+#endif /* __iop_dmc_out_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h
new file mode 100644
index 00000000000..e0c982b263f
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_defs.h
@@ -0,0 +1,255 @@
+#ifndef __iop_fifo_in_defs_h
+#define __iop_fifo_in_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_fifo_in.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:07 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_defs.h ../../inst/io_proc/rtl/iop_fifo_in.r
+ *      id: $Id: iop_fifo_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_fifo_in */
+
+/* Register rw_cfg, scope iop_fifo_in, type rw */
+typedef struct {
+  unsigned int avail_lim       : 3;
+  unsigned int byte_order      : 2;
+  unsigned int trig            : 2;
+  unsigned int last_dis_dif_in : 1;
+  unsigned int mode            : 2;
+  unsigned int dummy1          : 22;
+} reg_iop_fifo_in_rw_cfg;
+#define REG_RD_ADDR_iop_fifo_in_rw_cfg 0
+#define REG_WR_ADDR_iop_fifo_in_rw_cfg 0
+
+/* Register rw_ctrl, scope iop_fifo_in, type rw */
+typedef struct {
+  unsigned int dif_in_en  : 1;
+  unsigned int dif_out_en : 1;
+  unsigned int dummy1     : 30;
+} reg_iop_fifo_in_rw_ctrl;
+#define REG_RD_ADDR_iop_fifo_in_rw_ctrl 4
+#define REG_WR_ADDR_iop_fifo_in_rw_ctrl 4
+
+/* Register r_stat, scope iop_fifo_in, type r */
+typedef struct {
+  unsigned int avail_bytes : 4;
+  unsigned int last        : 8;
+  unsigned int dif_in_en   : 1;
+  unsigned int dif_out_en  : 1;
+  unsigned int dummy1      : 18;
+} reg_iop_fifo_in_r_stat;
+#define REG_RD_ADDR_iop_fifo_in_r_stat 8
+
+/* Register rs_rd1byte, scope iop_fifo_in, type rs */
+typedef struct {
+  unsigned int data : 8;
+  unsigned int dummy1 : 24;
+} reg_iop_fifo_in_rs_rd1byte;
+#define REG_RD_ADDR_iop_fifo_in_rs_rd1byte 12
+
+/* Register r_rd1byte, scope iop_fifo_in, type r */
+typedef struct {
+  unsigned int data : 8;
+  unsigned int dummy1 : 24;
+} reg_iop_fifo_in_r_rd1byte;
+#define REG_RD_ADDR_iop_fifo_in_r_rd1byte 16
+
+/* Register rs_rd2byte, scope iop_fifo_in, type rs */
+typedef struct {
+  unsigned int data : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_fifo_in_rs_rd2byte;
+#define REG_RD_ADDR_iop_fifo_in_rs_rd2byte 20
+
+/* Register r_rd2byte, scope iop_fifo_in, type r */
+typedef struct {
+  unsigned int data : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_fifo_in_r_rd2byte;
+#define REG_RD_ADDR_iop_fifo_in_r_rd2byte 24
+
+/* Register rs_rd3byte, scope iop_fifo_in, type rs */
+typedef struct {
+  unsigned int data : 24;
+  unsigned int dummy1 : 8;
+} reg_iop_fifo_in_rs_rd3byte;
+#define REG_RD_ADDR_iop_fifo_in_rs_rd3byte 28
+
+/* Register r_rd3byte, scope iop_fifo_in, type r */
+typedef struct {
+  unsigned int data : 24;
+  unsigned int dummy1 : 8;
+} reg_iop_fifo_in_r_rd3byte;
+#define REG_RD_ADDR_iop_fifo_in_r_rd3byte 32
+
+/* Register rs_rd4byte, scope iop_fifo_in, type rs */
+typedef struct {
+  unsigned int data : 32;
+} reg_iop_fifo_in_rs_rd4byte;
+#define REG_RD_ADDR_iop_fifo_in_rs_rd4byte 36
+
+/* Register r_rd4byte, scope iop_fifo_in, type r */
+typedef struct {
+  unsigned int data : 32;
+} reg_iop_fifo_in_r_rd4byte;
+#define REG_RD_ADDR_iop_fifo_in_r_rd4byte 40
+
+/* Register rw_set_last, scope iop_fifo_in, type rw */
+typedef unsigned int reg_iop_fifo_in_rw_set_last;
+#define REG_RD_ADDR_iop_fifo_in_rw_set_last 44
+#define REG_WR_ADDR_iop_fifo_in_rw_set_last 44
+
+/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */
+typedef struct {
+  unsigned int last : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_fifo_in_rw_strb_dif_in;
+#define REG_RD_ADDR_iop_fifo_in_rw_strb_dif_in 48
+#define REG_WR_ADDR_iop_fifo_in_rw_strb_dif_in 48
+
+/* Register rw_intr_mask, scope iop_fifo_in, type rw */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int avail     : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_in_rw_intr_mask;
+#define REG_RD_ADDR_iop_fifo_in_rw_intr_mask 52
+#define REG_WR_ADDR_iop_fifo_in_rw_intr_mask 52
+
+/* Register rw_ack_intr, scope iop_fifo_in, type rw */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int avail     : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_in_rw_ack_intr;
+#define REG_RD_ADDR_iop_fifo_in_rw_ack_intr 56
+#define REG_WR_ADDR_iop_fifo_in_rw_ack_intr 56
+
+/* Register r_intr, scope iop_fifo_in, type r */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int avail     : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_in_r_intr;
+#define REG_RD_ADDR_iop_fifo_in_r_intr 60
+
+/* Register r_masked_intr, scope iop_fifo_in, type r */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int avail     : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_in_r_masked_intr;
+#define REG_RD_ADDR_iop_fifo_in_r_masked_intr 64
+
+
+/* Constants */
+enum {
+  regk_iop_fifo_in_dif_in                  = 0x00000002,
+  regk_iop_fifo_in_hi                      = 0x00000000,
+  regk_iop_fifo_in_neg                     = 0x00000002,
+  regk_iop_fifo_in_no                      = 0x00000000,
+  regk_iop_fifo_in_order16                 = 0x00000001,
+  regk_iop_fifo_in_order24                 = 0x00000002,
+  regk_iop_fifo_in_order32                 = 0x00000003,
+  regk_iop_fifo_in_order8                  = 0x00000000,
+  regk_iop_fifo_in_pos                     = 0x00000001,
+  regk_iop_fifo_in_pos_neg                 = 0x00000003,
+  regk_iop_fifo_in_rw_cfg_default          = 0x00000024,
+  regk_iop_fifo_in_rw_ctrl_default         = 0x00000000,
+  regk_iop_fifo_in_rw_intr_mask_default    = 0x00000000,
+  regk_iop_fifo_in_rw_set_last_default     = 0x00000000,
+  regk_iop_fifo_in_rw_strb_dif_in_default  = 0x00000000,
+  regk_iop_fifo_in_size16                  = 0x00000002,
+  regk_iop_fifo_in_size24                  = 0x00000001,
+  regk_iop_fifo_in_size32                  = 0x00000000,
+  regk_iop_fifo_in_size8                   = 0x00000003,
+  regk_iop_fifo_in_yes                     = 0x00000001
+};
+#endif /* __iop_fifo_in_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h
new file mode 100644
index 00000000000..798ac95870e
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_in_extra_defs.h
@@ -0,0 +1,164 @@
+#ifndef __iop_fifo_in_extra_defs_h
+#define __iop_fifo_in_extra_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_fifo_in_extra.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:08 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r
+ *      id: $Id: iop_fifo_in_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_fifo_in_extra */
+
+/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */
+typedef unsigned int reg_iop_fifo_in_extra_rw_wr_data;
+#define REG_RD_ADDR_iop_fifo_in_extra_rw_wr_data 0
+#define REG_WR_ADDR_iop_fifo_in_extra_rw_wr_data 0
+
+/* Register r_stat, scope iop_fifo_in_extra, type r */
+typedef struct {
+  unsigned int avail_bytes : 4;
+  unsigned int last        : 8;
+  unsigned int dif_in_en   : 1;
+  unsigned int dif_out_en  : 1;
+  unsigned int dummy1      : 18;
+} reg_iop_fifo_in_extra_r_stat;
+#define REG_RD_ADDR_iop_fifo_in_extra_r_stat 4
+
+/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */
+typedef struct {
+  unsigned int last : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_fifo_in_extra_rw_strb_dif_in;
+#define REG_RD_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8
+#define REG_WR_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8
+
+/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int avail     : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_in_extra_rw_intr_mask;
+#define REG_RD_ADDR_iop_fifo_in_extra_rw_intr_mask 12
+#define REG_WR_ADDR_iop_fifo_in_extra_rw_intr_mask 12
+
+/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int avail     : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_in_extra_rw_ack_intr;
+#define REG_RD_ADDR_iop_fifo_in_extra_rw_ack_intr 16
+#define REG_WR_ADDR_iop_fifo_in_extra_rw_ack_intr 16
+
+/* Register r_intr, scope iop_fifo_in_extra, type r */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int avail     : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_in_extra_r_intr;
+#define REG_RD_ADDR_iop_fifo_in_extra_r_intr 20
+
+/* Register r_masked_intr, scope iop_fifo_in_extra, type r */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int avail     : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_in_extra_r_masked_intr;
+#define REG_RD_ADDR_iop_fifo_in_extra_r_masked_intr 24
+
+
+/* Constants */
+enum {
+  regk_iop_fifo_in_extra_fifo_in           = 0x00000002,
+  regk_iop_fifo_in_extra_no                = 0x00000000,
+  regk_iop_fifo_in_extra_rw_intr_mask_default = 0x00000000,
+  regk_iop_fifo_in_extra_yes               = 0x00000001
+};
+#endif /* __iop_fifo_in_extra_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h
new file mode 100644
index 00000000000..833e10f0252
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_defs.h
@@ -0,0 +1,278 @@
+#ifndef __iop_fifo_out_defs_h
+#define __iop_fifo_out_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_fifo_out.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:09 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_defs.h ../../inst/io_proc/rtl/iop_fifo_out.r
+ *      id: $Id: iop_fifo_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_fifo_out */
+
+/* Register rw_cfg, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int free_lim         : 3;
+  unsigned int byte_order       : 2;
+  unsigned int trig             : 2;
+  unsigned int last_dis_dif_in  : 1;
+  unsigned int mode             : 2;
+  unsigned int delay_out_last   : 1;
+  unsigned int last_dis_dif_out : 1;
+  unsigned int dummy1           : 20;
+} reg_iop_fifo_out_rw_cfg;
+#define REG_RD_ADDR_iop_fifo_out_rw_cfg 0
+#define REG_WR_ADDR_iop_fifo_out_rw_cfg 0
+
+/* Register rw_ctrl, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int dif_in_en  : 1;
+  unsigned int dif_out_en : 1;
+  unsigned int dummy1     : 30;
+} reg_iop_fifo_out_rw_ctrl;
+#define REG_RD_ADDR_iop_fifo_out_rw_ctrl 4
+#define REG_WR_ADDR_iop_fifo_out_rw_ctrl 4
+
+/* Register r_stat, scope iop_fifo_out, type r */
+typedef struct {
+  unsigned int avail_bytes    : 4;
+  unsigned int last           : 8;
+  unsigned int dif_in_en      : 1;
+  unsigned int dif_out_en     : 1;
+  unsigned int zero_data_last : 1;
+  unsigned int dummy1         : 17;
+} reg_iop_fifo_out_r_stat;
+#define REG_RD_ADDR_iop_fifo_out_r_stat 8
+
+/* Register rw_wr1byte, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int data : 8;
+  unsigned int dummy1 : 24;
+} reg_iop_fifo_out_rw_wr1byte;
+#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte 12
+#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte 12
+
+/* Register rw_wr2byte, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int data : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_fifo_out_rw_wr2byte;
+#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte 16
+#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte 16
+
+/* Register rw_wr3byte, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int data : 24;
+  unsigned int dummy1 : 8;
+} reg_iop_fifo_out_rw_wr3byte;
+#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte 20
+#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte 20
+
+/* Register rw_wr4byte, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int data : 32;
+} reg_iop_fifo_out_rw_wr4byte;
+#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte 24
+#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte 24
+
+/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int data : 8;
+  unsigned int dummy1 : 24;
+} reg_iop_fifo_out_rw_wr1byte_last;
+#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte_last 28
+#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte_last 28
+
+/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int data : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_fifo_out_rw_wr2byte_last;
+#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte_last 32
+#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte_last 32
+
+/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int data : 24;
+  unsigned int dummy1 : 8;
+} reg_iop_fifo_out_rw_wr3byte_last;
+#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte_last 36
+#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte_last 36
+
+/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int data : 32;
+} reg_iop_fifo_out_rw_wr4byte_last;
+#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte_last 40
+#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte_last 40
+
+/* Register rw_set_last, scope iop_fifo_out, type rw */
+typedef unsigned int reg_iop_fifo_out_rw_set_last;
+#define REG_RD_ADDR_iop_fifo_out_rw_set_last 44
+#define REG_WR_ADDR_iop_fifo_out_rw_set_last 44
+
+/* Register rs_rd_data, scope iop_fifo_out, type rs */
+typedef unsigned int reg_iop_fifo_out_rs_rd_data;
+#define REG_RD_ADDR_iop_fifo_out_rs_rd_data 48
+
+/* Register r_rd_data, scope iop_fifo_out, type r */
+typedef unsigned int reg_iop_fifo_out_r_rd_data;
+#define REG_RD_ADDR_iop_fifo_out_r_rd_data 52
+
+/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */
+typedef unsigned int reg_iop_fifo_out_rw_strb_dif_out;
+#define REG_RD_ADDR_iop_fifo_out_rw_strb_dif_out 56
+#define REG_WR_ADDR_iop_fifo_out_rw_strb_dif_out 56
+
+/* Register rw_intr_mask, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int free      : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_out_rw_intr_mask;
+#define REG_RD_ADDR_iop_fifo_out_rw_intr_mask 60
+#define REG_WR_ADDR_iop_fifo_out_rw_intr_mask 60
+
+/* Register rw_ack_intr, scope iop_fifo_out, type rw */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int free      : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_out_rw_ack_intr;
+#define REG_RD_ADDR_iop_fifo_out_rw_ack_intr 64
+#define REG_WR_ADDR_iop_fifo_out_rw_ack_intr 64
+
+/* Register r_intr, scope iop_fifo_out, type r */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int free      : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_out_r_intr;
+#define REG_RD_ADDR_iop_fifo_out_r_intr 68
+
+/* Register r_masked_intr, scope iop_fifo_out, type r */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int free      : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_out_r_masked_intr;
+#define REG_RD_ADDR_iop_fifo_out_r_masked_intr 72
+
+
+/* Constants */
+enum {
+  regk_iop_fifo_out_hi                     = 0x00000000,
+  regk_iop_fifo_out_neg                    = 0x00000002,
+  regk_iop_fifo_out_no                     = 0x00000000,
+  regk_iop_fifo_out_order16                = 0x00000001,
+  regk_iop_fifo_out_order24                = 0x00000002,
+  regk_iop_fifo_out_order32                = 0x00000003,
+  regk_iop_fifo_out_order8                 = 0x00000000,
+  regk_iop_fifo_out_pos                    = 0x00000001,
+  regk_iop_fifo_out_pos_neg                = 0x00000003,
+  regk_iop_fifo_out_rw_cfg_default         = 0x00000024,
+  regk_iop_fifo_out_rw_ctrl_default        = 0x00000000,
+  regk_iop_fifo_out_rw_intr_mask_default   = 0x00000000,
+  regk_iop_fifo_out_rw_set_last_default    = 0x00000000,
+  regk_iop_fifo_out_rw_strb_dif_out_default = 0x00000000,
+  regk_iop_fifo_out_rw_wr1byte_default     = 0x00000000,
+  regk_iop_fifo_out_rw_wr1byte_last_default = 0x00000000,
+  regk_iop_fifo_out_rw_wr2byte_default     = 0x00000000,
+  regk_iop_fifo_out_rw_wr2byte_last_default = 0x00000000,
+  regk_iop_fifo_out_rw_wr3byte_default     = 0x00000000,
+  regk_iop_fifo_out_rw_wr3byte_last_default = 0x00000000,
+  regk_iop_fifo_out_rw_wr4byte_default     = 0x00000000,
+  regk_iop_fifo_out_rw_wr4byte_last_default = 0x00000000,
+  regk_iop_fifo_out_size16                 = 0x00000002,
+  regk_iop_fifo_out_size24                 = 0x00000001,
+  regk_iop_fifo_out_size32                 = 0x00000000,
+  regk_iop_fifo_out_size8                  = 0x00000003,
+  regk_iop_fifo_out_yes                    = 0x00000001
+};
+#endif /* __iop_fifo_out_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h
new file mode 100644
index 00000000000..4a840aae84e
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_fifo_out_extra_defs.h
@@ -0,0 +1,164 @@
+#ifndef __iop_fifo_out_extra_defs_h
+#define __iop_fifo_out_extra_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_fifo_out_extra.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:10 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r
+ *      id: $Id: iop_fifo_out_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_fifo_out_extra */
+
+/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */
+typedef unsigned int reg_iop_fifo_out_extra_rs_rd_data;
+#define REG_RD_ADDR_iop_fifo_out_extra_rs_rd_data 0
+
+/* Register r_rd_data, scope iop_fifo_out_extra, type r */
+typedef unsigned int reg_iop_fifo_out_extra_r_rd_data;
+#define REG_RD_ADDR_iop_fifo_out_extra_r_rd_data 4
+
+/* Register r_stat, scope iop_fifo_out_extra, type r */
+typedef struct {
+  unsigned int avail_bytes    : 4;
+  unsigned int last           : 8;
+  unsigned int dif_in_en      : 1;
+  unsigned int dif_out_en     : 1;
+  unsigned int zero_data_last : 1;
+  unsigned int dummy1         : 17;
+} reg_iop_fifo_out_extra_r_stat;
+#define REG_RD_ADDR_iop_fifo_out_extra_r_stat 8
+
+/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */
+typedef unsigned int reg_iop_fifo_out_extra_rw_strb_dif_out;
+#define REG_RD_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12
+#define REG_WR_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12
+
+/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int free      : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_out_extra_rw_intr_mask;
+#define REG_RD_ADDR_iop_fifo_out_extra_rw_intr_mask 16
+#define REG_WR_ADDR_iop_fifo_out_extra_rw_intr_mask 16
+
+/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int free      : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_out_extra_rw_ack_intr;
+#define REG_RD_ADDR_iop_fifo_out_extra_rw_ack_intr 20
+#define REG_WR_ADDR_iop_fifo_out_extra_rw_ack_intr 20
+
+/* Register r_intr, scope iop_fifo_out_extra, type r */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int free      : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_out_extra_r_intr;
+#define REG_RD_ADDR_iop_fifo_out_extra_r_intr 24
+
+/* Register r_masked_intr, scope iop_fifo_out_extra, type r */
+typedef struct {
+  unsigned int urun      : 1;
+  unsigned int last_data : 1;
+  unsigned int dav       : 1;
+  unsigned int free      : 1;
+  unsigned int orun      : 1;
+  unsigned int dummy1    : 27;
+} reg_iop_fifo_out_extra_r_masked_intr;
+#define REG_RD_ADDR_iop_fifo_out_extra_r_masked_intr 28
+
+
+/* Constants */
+enum {
+  regk_iop_fifo_out_extra_no               = 0x00000000,
+  regk_iop_fifo_out_extra_rw_intr_mask_default = 0x00000000,
+  regk_iop_fifo_out_extra_yes              = 0x00000001
+};
+#endif /* __iop_fifo_out_extra_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h
new file mode 100644
index 00000000000..c2b0ba1be60
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_defs.h
@@ -0,0 +1,190 @@
+#ifndef __iop_mpu_defs_h
+#define __iop_mpu_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_mpu.r
+ *     id:           iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:45 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_mpu_defs.h ../../inst/io_proc/rtl/iop_mpu.r
+ *      id: $Id: iop_mpu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_mpu */
+
+#define STRIDE_iop_mpu_rw_r 4
+/* Register rw_r, scope iop_mpu, type rw */
+typedef unsigned int reg_iop_mpu_rw_r;
+#define REG_RD_ADDR_iop_mpu_rw_r 0
+#define REG_WR_ADDR_iop_mpu_rw_r 0
+
+/* Register rw_ctrl, scope iop_mpu, type rw */
+typedef struct {
+  unsigned int en : 1;
+  unsigned int dummy1 : 31;
+} reg_iop_mpu_rw_ctrl;
+#define REG_RD_ADDR_iop_mpu_rw_ctrl 128
+#define REG_WR_ADDR_iop_mpu_rw_ctrl 128
+
+/* Register r_pc, scope iop_mpu, type r */
+typedef struct {
+  unsigned int addr : 12;
+  unsigned int dummy1 : 20;
+} reg_iop_mpu_r_pc;
+#define REG_RD_ADDR_iop_mpu_r_pc 132
+
+/* Register r_stat, scope iop_mpu, type r */
+typedef struct {
+  unsigned int instr_reg_busy : 1;
+  unsigned int intr_busy      : 1;
+  unsigned int intr_vect      : 16;
+  unsigned int dummy1         : 14;
+} reg_iop_mpu_r_stat;
+#define REG_RD_ADDR_iop_mpu_r_stat 136
+
+/* Register rw_instr, scope iop_mpu, type rw */
+typedef unsigned int reg_iop_mpu_rw_instr;
+#define REG_RD_ADDR_iop_mpu_rw_instr 140
+#define REG_WR_ADDR_iop_mpu_rw_instr 140
+
+/* Register rw_immediate, scope iop_mpu, type rw */
+typedef unsigned int reg_iop_mpu_rw_immediate;
+#define REG_RD_ADDR_iop_mpu_rw_immediate 144
+#define REG_WR_ADDR_iop_mpu_rw_immediate 144
+
+/* Register r_trace, scope iop_mpu, type r */
+typedef struct {
+  unsigned int intr_vect      : 16;
+  unsigned int pc             : 12;
+  unsigned int en             : 1;
+  unsigned int instr_reg_busy : 1;
+  unsigned int intr_busy      : 1;
+  unsigned int dummy1         : 1;
+} reg_iop_mpu_r_trace;
+#define REG_RD_ADDR_iop_mpu_r_trace 148
+
+/* Register r_wr_stat, scope iop_mpu, type r */
+typedef struct {
+  unsigned int r0  : 1;
+  unsigned int r1  : 1;
+  unsigned int r2  : 1;
+  unsigned int r3  : 1;
+  unsigned int r4  : 1;
+  unsigned int r5  : 1;
+  unsigned int r6  : 1;
+  unsigned int r7  : 1;
+  unsigned int r8  : 1;
+  unsigned int r9  : 1;
+  unsigned int r10 : 1;
+  unsigned int r11 : 1;
+  unsigned int r12 : 1;
+  unsigned int r13 : 1;
+  unsigned int r14 : 1;
+  unsigned int r15 : 1;
+  unsigned int dummy1 : 16;
+} reg_iop_mpu_r_wr_stat;
+#define REG_RD_ADDR_iop_mpu_r_wr_stat 152
+
+#define STRIDE_iop_mpu_rw_thread 4
+/* Register rw_thread, scope iop_mpu, type rw */
+typedef struct {
+  unsigned int addr : 12;
+  unsigned int dummy1 : 20;
+} reg_iop_mpu_rw_thread;
+#define REG_RD_ADDR_iop_mpu_rw_thread 156
+#define REG_WR_ADDR_iop_mpu_rw_thread 156
+
+#define STRIDE_iop_mpu_rw_intr 4
+/* Register rw_intr, scope iop_mpu, type rw */
+typedef struct {
+  unsigned int addr : 12;
+  unsigned int dummy1 : 20;
+} reg_iop_mpu_rw_intr;
+#define REG_RD_ADDR_iop_mpu_rw_intr 196
+#define REG_WR_ADDR_iop_mpu_rw_intr 196
+
+
+/* Constants */
+enum {
+  regk_iop_mpu_no                          = 0x00000000,
+  regk_iop_mpu_r_pc_default                = 0x00000000,
+  regk_iop_mpu_rw_ctrl_default             = 0x00000000,
+  regk_iop_mpu_rw_intr_size                = 0x00000010,
+  regk_iop_mpu_rw_r_size                   = 0x00000010,
+  regk_iop_mpu_rw_thread_default           = 0x00000000,
+  regk_iop_mpu_rw_thread_size              = 0x00000004,
+  regk_iop_mpu_yes                         = 0x00000001
+};
+#endif /* __iop_mpu_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h
new file mode 100644
index 00000000000..2ec897ced16
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h
@@ -0,0 +1,764 @@
+/* ************************************************************************* */
+/* This file is autogenerated by IOPASM Version 1.2                          */
+/* DO NOT EDIT THIS FILE - All changes will be lost!                         */
+/* ************************************************************************* */
+
+
+
+#ifndef __IOP_MPU_MACROS_H__
+#define __IOP_MPU_MACROS_H__
+
+
+/* ************************************************************************* */
+/*                           REGISTER DEFINITIONS                            */
+/* ************************************************************************* */
+#define MPU_R0 (0x0)
+#define MPU_R1 (0x1)
+#define MPU_R2 (0x2)
+#define MPU_R3 (0x3)
+#define MPU_R4 (0x4)
+#define MPU_R5 (0x5)
+#define MPU_R6 (0x6)
+#define MPU_R7 (0x7)
+#define MPU_R8 (0x8)
+#define MPU_R9 (0x9)
+#define MPU_R10 (0xa)
+#define MPU_R11 (0xb)
+#define MPU_R12 (0xc)
+#define MPU_R13 (0xd)
+#define MPU_R14 (0xe)
+#define MPU_R15 (0xf)
+#define MPU_PC (0x2)
+#define MPU_WSTS (0x3)
+#define MPU_JADDR (0x4)
+#define MPU_IRP (0x5)
+#define MPU_SRP (0x6)
+#define MPU_T0 (0x8)
+#define MPU_T1 (0x9)
+#define MPU_T2 (0xa)
+#define MPU_T3 (0xb)
+#define MPU_I0 (0x10)
+#define MPU_I1 (0x11)
+#define MPU_I2 (0x12)
+#define MPU_I3 (0x13)
+#define MPU_I4 (0x14)
+#define MPU_I5 (0x15)
+#define MPU_I6 (0x16)
+#define MPU_I7 (0x17)
+#define MPU_I8 (0x18)
+#define MPU_I9 (0x19)
+#define MPU_I10 (0x1a)
+#define MPU_I11 (0x1b)
+#define MPU_I12 (0x1c)
+#define MPU_I13 (0x1d)
+#define MPU_I14 (0x1e)
+#define MPU_I15 (0x1f)
+#define MPU_P2 (0x2)
+#define MPU_P3 (0x3)
+#define MPU_P5 (0x5)
+#define MPU_P6 (0x6)
+#define MPU_P8 (0x8)
+#define MPU_P9 (0x9)
+#define MPU_P10 (0xa)
+#define MPU_P11 (0xb)
+#define MPU_P16 (0x10)
+#define MPU_P17 (0x12)
+#define MPU_P18 (0x12)
+#define MPU_P19 (0x13)
+#define MPU_P20 (0x14)
+#define MPU_P21 (0x15)
+#define MPU_P22 (0x16)
+#define MPU_P23 (0x17)
+#define MPU_P24 (0x18)
+#define MPU_P25 (0x19)
+#define MPU_P26 (0x1a)
+#define MPU_P27 (0x1b)
+#define MPU_P28 (0x1c)
+#define MPU_P29 (0x1d)
+#define MPU_P30 (0x1e)
+#define MPU_P31 (0x1f)
+#define MPU_P1 (0x1)
+#define MPU_REGA (0x1)
+
+
+
+/* ************************************************************************* */
+/*                              ADDRESS MACROS                               */
+/* ************************************************************************* */
+#define MK_DWORD_ADDR(ADDR) (ADDR >> 2)
+#define MK_BYTE_ADDR(ADDR) (ADDR)
+
+
+
+/* ************************************************************************* */
+/*                            INSTRUCTION MACROS                             */
+/* ************************************************************************* */
+#define MPU_ADD_RRR(S,N,D) (0x4000008C | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADD_RRS(S,N,D) (0x4000048C | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADD_RSR(S,N,D) (0x4000018C | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADD_RSS(S,N,D) (0x4000058C | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADD_SRR(S,N,D) (0x4000028C | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADD_SRS(S,N,D) (0x4000068C | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADD_SSR(S,N,D) (0x4000038C | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADD_SSS(S,N,D) (0x4000078C | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDQ_RIR(S,N,D) (0x10000000 | ((S & ((1 << 5) - 1)) << 16)\
+                                 | ((N & ((1 << 16) - 1)) << 0)\
+                                 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDQ_IRR(S,N,D) (0x10000000 | ((S & ((1 << 16) - 1)) << 0)\
+                                 | ((N & ((1 << 5) - 1)) << 16)\
+                                 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDX_IRR_INSTR(S,N,D) (0xC000008C | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ADDX_RIR_INSTR(S,N,D) (0xC000008C | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_ADDX_ISR_INSTR(S,N,D) (0xC000028C | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ADDX_SIR_INSTR(S,N,D) (0xC000028C | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_ADDX_IRS_INSTR(S,N,D) (0xC000048C | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ADDX_RIS_INSTR(S,N,D) (0xC000048C | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_ADDX_ISS_INSTR(S,N,D) (0xC000068C | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ADDX_SIS_INSTR(S,N,D) (0xC000068C | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ADDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_AND_RRR(S,N,D) (0x4000008A | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_AND_RRS(S,N,D) (0x4000048A | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_AND_RSR(S,N,D) (0x4000018A | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_AND_RSS(S,N,D) (0x4000058A | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_AND_SRR(S,N,D) (0x4000028A | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_AND_SRS(S,N,D) (0x4000068A | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_AND_SSR(S,N,D) (0x4000038A | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_AND_SSS(S,N,D) (0x4000078A | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDQ_RIR(S,N,D) (0x08000000 | ((S & ((1 << 5) - 1)) << 16)\
+                                 | ((N & ((1 << 16) - 1)) << 0)\
+                                 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDQ_IRR(S,N,D) (0x08000000 | ((S & ((1 << 16) - 1)) << 0)\
+                                 | ((N & ((1 << 5) - 1)) << 16)\
+                                 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDX_RIR_INSTR(S,N,D) (0xC000008A | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_ANDX_IRR_INSTR(S,N,D) (0xC000008A | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ANDX_ISR_INSTR(S,N,D) (0xC000028A | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ANDX_SIR_INSTR(S,N,D) (0xC000028A | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_ANDX_IRS_INSTR(S,N,D) (0xC000048A | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ANDX_ISS_INSTR(S,N,D) (0xC000068A | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ANDX_RIS_INSTR(S,N,D) (0xC000048A | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_ANDX_SIS_INSTR(S,N,D) (0xC000068A | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ANDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_BA_I(S) (0x60000000 | ((S & ((1 << 16) - 1)) << 0))
+
+#define MPU_BAR_R(S) (0x62000000 | ((S & ((1 << 5) - 1)) << 11))
+
+#define MPU_BAR_S(S) (0x63000000 | ((S & ((1 << 5) - 1)) << 11))
+
+#define MPU_BBC_RII(S,N,D) (0x78000000 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 21)\
+                                | ((D & ((1 << 16) - 1)) << 0))
+
+#define MPU_BBS_RII(S,N,D) (0x7C000000 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 21)\
+                                | ((D & ((1 << 16) - 1)) << 0))
+
+#define MPU_BNZ_RI(S,D) (0x74400000 | ((S & ((1 << 5) - 1)) << 16)\
+                             | ((D & ((1 << 16) - 1)) << 0))
+
+#define MPU_BMI_RI(S,D) (0x7FE00000 | ((S & ((1 << 5) - 1)) << 16)\
+                             | ((D & ((1 << 16) - 1)) << 0))
+
+#define MPU_BPL_RI(S,D) (0x7BE00000 | ((S & ((1 << 5) - 1)) << 16)\
+                             | ((D & ((1 << 16) - 1)) << 0))
+
+#define MPU_BZ_RI(S,D) (0x74000000 | ((S & ((1 << 5) - 1)) << 16)\
+                            | ((D & ((1 << 16) - 1)) << 0))
+
+#define MPU_DI() (0x40000001)
+
+#define MPU_EI() (0x40000003)
+
+#define MPU_HALT() (0x40000002)
+
+#define MPU_JIR_I(S) (0x60200000 | ((S & ((1 << 16) - 1)) << 0))
+
+#define MPU_JIR_R(S) (0x62200000 | ((S & ((1 << 5) - 1)) << 11))
+
+#define MPU_JIR_S(S) (0x63200000 | ((S & ((1 << 5) - 1)) << 11))
+
+#define MPU_JNT() (0x61000000)
+
+#define MPU_JSR_I(S) (0x60400000 | ((S & ((1 << 16) - 1)) << 0))
+
+#define MPU_JSR_R(S) (0x62400000 | ((S & ((1 << 5) - 1)) << 11))
+
+#define MPU_JSR_S(S) (0x63400000 | ((S & ((1 << 5) - 1)) << 11))
+
+#define MPU_LSL_RRR(S,N,D) (0x4000008E | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSL_RRS(S,N,D) (0x4000048E | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSL_RSR(S,N,D) (0x4000018E | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSL_RSS(S,N,D) (0x4000058E | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSL_SRR(S,N,D) (0x4000028E | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSL_SRS(S,N,D) (0x4000068E | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSL_SSR(S,N,D) (0x4000038E | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSL_SSS(S,N,D) (0x4000078E | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSLQ_RIR(S,N,D) (0x18000000 | ((S & ((1 << 5) - 1)) << 16)\
+                                 | ((N & ((1 << 16) - 1)) << 0)\
+                                 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSR_RRR(S,N,D) (0x4000008F | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSR_RRS(S,N,D) (0x4000048F | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSR_RSR(S,N,D) (0x4000018F | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSR_RSS(S,N,D) (0x4000058F | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSR_SRR(S,N,D) (0x4000028F | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSR_SRS(S,N,D) (0x4000068F | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSR_SSR(S,N,D) (0x4000038F | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSR_SSS(S,N,D) (0x4000078F | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LSRQ_RIR(S,N,D) (0x1C000000 | ((S & ((1 << 5) - 1)) << 16)\
+                                 | ((N & ((1 << 16) - 1)) << 0)\
+                                 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_LW_IR(S,D) (0x64400000 | ((S & ((1 << 16) - 1)) << 0)\
+                            | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_LW_IS(S,D) (0x64600000 | ((S & ((1 << 16) - 1)) << 0)\
+                            | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_LW_RR(S,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\
+                            | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_LW_RS(S,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\
+                            | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_LW_SR(S,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\
+                            | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_LW_SS(S,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\
+                            | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_LW_RIR(S,N,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\
+                               | ((N & ((1 << 8) - 1)) << 0)\
+                               | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_LW_RIS(S,N,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\
+                               | ((N & ((1 << 8) - 1)) << 0)\
+                               | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_LW_SIR(S,N,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\
+                               | ((N & ((1 << 8) - 1)) << 0)\
+                               | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_LW_SIS(S,N,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\
+                               | ((N & ((1 << 8) - 1)) << 0)\
+                               | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_MOVE_RR(S,D) (0x40000081 | ((S & ((1 << 5) - 1)) << 11)\
+                              | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_MOVE_RS(S,D) (0x40000481 | ((S & ((1 << 5) - 1)) << 11)\
+                              | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_MOVE_SR(S,D) (0x40000181 | ((S & ((1 << 5) - 1)) << 11)\
+                              | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_MOVE_SS(S,D) (0x40000581 | ((S & ((1 << 5) - 1)) << 11)\
+                              | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_MOVEQ_IR(S,D) (0x24000000 | ((S & ((1 << 16) - 1)) << 0)\
+                               | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_MOVEQ_IS(S,D) (0x2C000000 | ((S & ((1 << 16) - 1)) << 0)\
+                               | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_MOVEX_IR_INSTR(S,D) (0xC0000081 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_MOVEX_IR_IMM(S,D) (S & 0xFFFFFFFF)
+
+#define MPU_MOVEX_IS_INSTR(S,D) (0xC0000481 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_MOVEX_IS_IMM(S,D) (S & 0xFFFFFFFF)
+
+#define MPU_NOP() (0x40000000)
+
+#define MPU_NOT_RR(S,D) (0x40100081 | ((S & ((1 << 5) - 1)) << 11)\
+                             | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_NOT_RS(S,D) (0x40100481 | ((S & ((1 << 5) - 1)) << 11)\
+                             | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_NOT_SR(S,D) (0x40100181 | ((S & ((1 << 5) - 1)) << 11)\
+                             | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_NOT_SS(S,D) (0x40100581 | ((S & ((1 << 5) - 1)) << 11)\
+                             | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_OR_RRR(S,N,D) (0x4000008B | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 5) - 1)) << 11)\
+                               | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_OR_RRS(S,N,D) (0x4000048B | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 5) - 1)) << 11)\
+                               | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_OR_RSR(S,N,D) (0x4000018B | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 5) - 1)) << 11)\
+                               | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_OR_RSS(S,N,D) (0x4000058B | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 5) - 1)) << 11)\
+                               | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_OR_SRR(S,N,D) (0x4000028B | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 5) - 1)) << 11)\
+                               | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_OR_SRS(S,N,D) (0x4000068B | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 5) - 1)) << 11)\
+                               | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_OR_SSR(S,N,D) (0x4000038B | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 5) - 1)) << 11)\
+                               | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_OR_SSS(S,N,D) (0x4000078B | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 5) - 1)) << 11)\
+                               | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORQ_RIR(S,N,D) (0x0C000000 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 16) - 1)) << 0)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORQ_IRR(S,N,D) (0x0C000000 | ((S & ((1 << 16) - 1)) << 0)\
+                                | ((N & ((1 << 5) - 1)) << 16)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORX_RIR_INSTR(S,N,D) (0xC000008B | ((S & ((1 << 5) - 1)) << 16)\
+                                      | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_ORX_IRR_INSTR(S,N,D) (0xC000008B | ((N & ((1 << 5) - 1)) << 16)\
+                                      | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ORX_SIR_INSTR(S,N,D) (0xC000028B | ((S & ((1 << 5) - 1)) << 16)\
+                                      | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_ORX_ISR_INSTR(S,N,D) (0xC000028B | ((N & ((1 << 5) - 1)) << 16)\
+                                      | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ORX_RIS_INSTR(S,N,D) (0xC000048B | ((S & ((1 << 5) - 1)) << 16)\
+                                      | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_ORX_IRS_INSTR(S,N,D) (0xC000048B | ((N & ((1 << 5) - 1)) << 16)\
+                                      | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_ORX_SIS_INSTR(S,N,D) (0xC000068B | ((S & ((1 << 5) - 1)) << 16)\
+                                      | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_ORX_ISS_INSTR(S,N,D) (0xC000068B | ((N & ((1 << 5) - 1)) << 16)\
+                                      | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_ORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_RET() (0x63003000)
+
+#define MPU_RETI() (0x63602800)
+
+#define MPU_RR_IR(S,D) (0x50000000 | ((S & ((1 << 11) - 1)) << 0)\
+                            | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_RR_SR(S,D) (0x50008000 | ((S & ((1 << 5) - 1)) << 16)\
+                            | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_RW_RI(S,D) (0x56000000 | ((S & ((1 << 5) - 1)) << 11)\
+                            | ((D & ((1 << 11) - 1)) << 0))
+
+#define MPU_RW_RS(S,D) (0x57000000 | ((S & ((1 << 5) - 1)) << 11)\
+                            | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_RWQ_II(S,D) (0x58000000 | ((S & ((1 << 16) - 1)) << 11)\
+                             | ((D & ((1 << 11) - 1)) << 0))
+
+#define MPU_RWQ_IS(S,D) (0x55000000 | ((S & ((1 << 16) - 1)) << 0)\
+                             | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_RWX_II_INSTR(S,D) (0xD4000000 | ((D & ((1 << 11) - 1)) << 0))
+
+#define MPU_RWX_II_IMM(S,D) (S & 0xFFFFFFFF)
+
+#define MPU_RWX_IS_INSTR(S,D) (0xD5000000 | ((D & ((1 << 5) - 1)) << 16))
+
+#define MPU_RWX_IS_IMM(S,D) (S & 0xFFFFFFFF)
+
+#define MPU_SUB_RRR(S,N,D) (0x4000008D | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUB_RRS(S,N,D) (0x4000048D | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUB_RSR(S,N,D) (0x4000018D | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUB_RSS(S,N,D) (0x4000058D | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUB_SRR(S,N,D) (0x4000028D | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUB_SRS(S,N,D) (0x4000068D | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUB_SSR(S,N,D) (0x4000038D | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUB_SSS(S,N,D) (0x4000078D | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUBQ_RIR(S,N,D) (0x14000000 | ((S & ((1 << 5) - 1)) << 16)\
+                                 | ((N & ((1 << 16) - 1)) << 0)\
+                                 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUBX_RIR_INSTR(S,N,D) (0xC000008D | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUBX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_SUBX_SIR_INSTR(S,N,D) (0xC000028D | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUBX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_SUBX_RIS_INSTR(S,N,D) (0xC000048D | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUBX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_SUBX_SIS_INSTR(S,N,D) (0xC000068D | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_SUBX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_SW_RI(S,D) (0x64000000 | ((S & ((1 << 5) - 1)) << 16)\
+                            | ((D & ((1 << 16) - 1)) << 0))
+
+#define MPU_SW_SI(S,D) (0x64200000 | ((S & ((1 << 5) - 1)) << 16)\
+                            | ((D & ((1 << 16) - 1)) << 0))
+
+#define MPU_SW_RR(S,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\
+                            | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SW_SR(S,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\
+                            | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SW_RS(S,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\
+                            | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SW_SS(S,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\
+                            | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SW_RIR(S,N,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 8) - 1)) << 0)\
+                               | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SW_SIR(S,N,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 8) - 1)) << 0)\
+                               | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SW_RIS(S,N,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 8) - 1)) << 0)\
+                               | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SW_SIS(S,N,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\
+                               | ((N & ((1 << 8) - 1)) << 0)\
+                               | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SWX_II_INSTR(S,D) (0xE4000000 | ((D & ((1 << 16) - 1)) << 0))
+
+#define MPU_SWX_II_IMM(S,D) (S & 0xFFFFFFFF)
+
+#define MPU_SWX_IR_INSTR(S,D) (0xE6000000 | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SWX_IR_IMM(S,D) (S & 0xFFFFFFFF)
+
+#define MPU_SWX_IS_INSTR(S,D) (0xE7000000 | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SWX_IS_IMM(S,D) (S & 0xFFFFFFFF)
+
+#define MPU_SWX_IIR_INSTR(S,N,D) (0xE6000000 | ((N & ((1 << 8) - 1)) << 0)\
+                                      | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SWX_IIR_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_SWX_IIS_INSTR(S,N,D) (0xE7000000 | ((N & ((1 << 8) - 1)) << 0)\
+                                      | ((D & ((1 << 5) - 1)) << 11))
+
+#define MPU_SWX_IIS_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_XOR_RRR(S,N,D) (0x40000089 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_RRS(S,N,D) (0x40000489 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_RSR(S,N,D) (0x40000189 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_RSS(S,N,D) (0x40000589 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_SRR(S,N,D) (0x40000289 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_SRS(S,N,D) (0x40000689 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_SSR(S,N,D) (0x40000389 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_SSS(S,N,D) (0x40000789 | ((S & ((1 << 5) - 1)) << 16)\
+                                | ((N & ((1 << 5) - 1)) << 11)\
+                                | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_RR(S,D) (0x40000088 | ((S & ((1 << 5) - 1)) << 11)\
+                             | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_RS(S,D) (0x40000488 | ((S & ((1 << 5) - 1)) << 11)\
+                             | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_SR(S,D) (0x40000188 | ((S & ((1 << 5) - 1)) << 11)\
+                             | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XOR_SS(S,D) (0x40000588 | ((S & ((1 << 5) - 1)) << 11)\
+                             | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORQ_RIR(S,N,D) (0x04000000 | ((S & ((1 << 5) - 1)) << 16)\
+                                 | ((N & ((1 << 16) - 1)) << 0)\
+                                 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORQ_IRR(S,N,D) (0x04000000 | ((S & ((1 << 16) - 1)) << 0)\
+                                 | ((N & ((1 << 5) - 1)) << 16)\
+                                 | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORX_RIR_INSTR(S,N,D) (0xC0000089 | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_XORX_IRR_INSTR(S,N,D) (0xC0000089 | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_XORX_SIR_INSTR(S,N,D) (0xC0000289 | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_XORX_ISR_INSTR(S,N,D) (0xC0000289 | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_XORX_RIS_INSTR(S,N,D) (0xC0000489 | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_XORX_IRS_INSTR(S,N,D) (0xC0000489 | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+#define MPU_XORX_SIS_INSTR(S,N,D) (0xC0000689 | ((S & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
+
+#define MPU_XORX_ISS_INSTR(S,N,D) (0xC0000689 | ((N & ((1 << 5) - 1)) << 16)\
+                                       | ((D & ((1 << 5) - 1)) << 21))
+
+#define MPU_XORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
+
+
+#endif /* end of __IOP_MPU_MACROS_H__ */
+/* End of iop_mpu_macros.h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h b/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h
new file mode 100644
index 00000000000..756550f5d6c
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_reg_space.h
@@ -0,0 +1,44 @@
+/* Autogenerated Changes here will be lost!
+ * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg
+ */
+#define regi_iop_version (regi_iop + 0)
+#define regi_iop_fifo_in0_extra (regi_iop + 64)
+#define regi_iop_fifo_in1_extra (regi_iop + 128)
+#define regi_iop_fifo_out0_extra (regi_iop + 192)
+#define regi_iop_fifo_out1_extra (regi_iop + 256)
+#define regi_iop_trigger_grp0 (regi_iop + 320)
+#define regi_iop_trigger_grp1 (regi_iop + 384)
+#define regi_iop_trigger_grp2 (regi_iop + 448)
+#define regi_iop_trigger_grp3 (regi_iop + 512)
+#define regi_iop_trigger_grp4 (regi_iop + 576)
+#define regi_iop_trigger_grp5 (regi_iop + 640)
+#define regi_iop_trigger_grp6 (regi_iop + 704)
+#define regi_iop_trigger_grp7 (regi_iop + 768)
+#define regi_iop_crc_par0 (regi_iop + 896)
+#define regi_iop_crc_par1 (regi_iop + 1024)
+#define regi_iop_dmc_in0 (regi_iop + 1152)
+#define regi_iop_dmc_in1 (regi_iop + 1280)
+#define regi_iop_dmc_out0 (regi_iop + 1408)
+#define regi_iop_dmc_out1 (regi_iop + 1536)
+#define regi_iop_fifo_in0 (regi_iop + 1664)
+#define regi_iop_fifo_in1 (regi_iop + 1792)
+#define regi_iop_fifo_out0 (regi_iop + 1920)
+#define regi_iop_fifo_out1 (regi_iop + 2048)
+#define regi_iop_scrc_in0 (regi_iop + 2176)
+#define regi_iop_scrc_in1 (regi_iop + 2304)
+#define regi_iop_scrc_out0 (regi_iop + 2432)
+#define regi_iop_scrc_out1 (regi_iop + 2560)
+#define regi_iop_timer_grp0 (regi_iop + 2688)
+#define regi_iop_timer_grp1 (regi_iop + 2816)
+#define regi_iop_timer_grp2 (regi_iop + 2944)
+#define regi_iop_timer_grp3 (regi_iop + 3072)
+#define regi_iop_sap_in (regi_iop + 3328)
+#define regi_iop_sap_out (regi_iop + 3584)
+#define regi_iop_spu0 (regi_iop + 3840)
+#define regi_iop_spu1 (regi_iop + 4096)
+#define regi_iop_sw_cfg (regi_iop + 4352)
+#define regi_iop_sw_cpu (regi_iop + 4608)
+#define regi_iop_sw_mpu (regi_iop + 4864)
+#define regi_iop_sw_spu0 (regi_iop + 5120)
+#define regi_iop_sw_spu1 (regi_iop + 5376)
+#define regi_iop_mpu (regi_iop + 5632)
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h
new file mode 100644
index 00000000000..5548ac10074
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_in_defs.h
@@ -0,0 +1,179 @@
+#ifndef __iop_sap_in_defs_h
+#define __iop_sap_in_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_sap_in.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:08:45 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_in_defs.h ../../inst/io_proc/rtl/iop_sap_in.r
+ *      id: $Id: iop_sap_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_sap_in */
+
+/* Register rw_bus0_sync, scope iop_sap_in, type rw */
+typedef struct {
+  unsigned int byte0_sel     : 2;
+  unsigned int byte0_ext_src : 3;
+  unsigned int byte0_edge    : 2;
+  unsigned int byte0_delay   : 1;
+  unsigned int byte1_sel     : 2;
+  unsigned int byte1_ext_src : 3;
+  unsigned int byte1_edge    : 2;
+  unsigned int byte1_delay   : 1;
+  unsigned int byte2_sel     : 2;
+  unsigned int byte2_ext_src : 3;
+  unsigned int byte2_edge    : 2;
+  unsigned int byte2_delay   : 1;
+  unsigned int byte3_sel     : 2;
+  unsigned int byte3_ext_src : 3;
+  unsigned int byte3_edge    : 2;
+  unsigned int byte3_delay   : 1;
+} reg_iop_sap_in_rw_bus0_sync;
+#define REG_RD_ADDR_iop_sap_in_rw_bus0_sync 0
+#define REG_WR_ADDR_iop_sap_in_rw_bus0_sync 0
+
+/* Register rw_bus1_sync, scope iop_sap_in, type rw */
+typedef struct {
+  unsigned int byte0_sel     : 2;
+  unsigned int byte0_ext_src : 3;
+  unsigned int byte0_edge    : 2;
+  unsigned int byte0_delay   : 1;
+  unsigned int byte1_sel     : 2;
+  unsigned int byte1_ext_src : 3;
+  unsigned int byte1_edge    : 2;
+  unsigned int byte1_delay   : 1;
+  unsigned int byte2_sel     : 2;
+  unsigned int byte2_ext_src : 3;
+  unsigned int byte2_edge    : 2;
+  unsigned int byte2_delay   : 1;
+  unsigned int byte3_sel     : 2;
+  unsigned int byte3_ext_src : 3;
+  unsigned int byte3_edge    : 2;
+  unsigned int byte3_delay   : 1;
+} reg_iop_sap_in_rw_bus1_sync;
+#define REG_RD_ADDR_iop_sap_in_rw_bus1_sync 4
+#define REG_WR_ADDR_iop_sap_in_rw_bus1_sync 4
+
+#define STRIDE_iop_sap_in_rw_gio 4
+/* Register rw_gio, scope iop_sap_in, type rw */
+typedef struct {
+  unsigned int sync_sel     : 2;
+  unsigned int sync_ext_src : 3;
+  unsigned int sync_edge    : 2;
+  unsigned int delay        : 1;
+  unsigned int logic        : 2;
+  unsigned int dummy1       : 22;
+} reg_iop_sap_in_rw_gio;
+#define REG_RD_ADDR_iop_sap_in_rw_gio 8
+#define REG_WR_ADDR_iop_sap_in_rw_gio 8
+
+
+/* Constants */
+enum {
+  regk_iop_sap_in_and                      = 0x00000002,
+  regk_iop_sap_in_ext_clk200               = 0x00000003,
+  regk_iop_sap_in_gio1                     = 0x00000000,
+  regk_iop_sap_in_gio13                    = 0x00000005,
+  regk_iop_sap_in_gio18                    = 0x00000003,
+  regk_iop_sap_in_gio19                    = 0x00000004,
+  regk_iop_sap_in_gio21                    = 0x00000006,
+  regk_iop_sap_in_gio23                    = 0x00000005,
+  regk_iop_sap_in_gio29                    = 0x00000007,
+  regk_iop_sap_in_gio5                     = 0x00000004,
+  regk_iop_sap_in_gio6                     = 0x00000001,
+  regk_iop_sap_in_gio7                     = 0x00000002,
+  regk_iop_sap_in_inv                      = 0x00000001,
+  regk_iop_sap_in_neg                      = 0x00000002,
+  regk_iop_sap_in_no                       = 0x00000000,
+  regk_iop_sap_in_no_del_ext_clk200        = 0x00000001,
+  regk_iop_sap_in_none                     = 0x00000000,
+  regk_iop_sap_in_or                       = 0x00000003,
+  regk_iop_sap_in_pos                      = 0x00000001,
+  regk_iop_sap_in_pos_neg                  = 0x00000003,
+  regk_iop_sap_in_rw_bus0_sync_default     = 0x02020202,
+  regk_iop_sap_in_rw_bus1_sync_default     = 0x02020202,
+  regk_iop_sap_in_rw_gio_default           = 0x00000002,
+  regk_iop_sap_in_rw_gio_size              = 0x00000020,
+  regk_iop_sap_in_timer_grp0_tmr3          = 0x00000006,
+  regk_iop_sap_in_timer_grp1_tmr3          = 0x00000004,
+  regk_iop_sap_in_timer_grp2_tmr3          = 0x00000005,
+  regk_iop_sap_in_timer_grp3_tmr3          = 0x00000007,
+  regk_iop_sap_in_tmr_clk200               = 0x00000000,
+  regk_iop_sap_in_two_clk200               = 0x00000002,
+  regk_iop_sap_in_yes                      = 0x00000001
+};
+#endif /* __iop_sap_in_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h
new file mode 100644
index 00000000000..27393699618
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sap_out_defs.h
@@ -0,0 +1,306 @@
+#ifndef __iop_sap_out_defs_h
+#define __iop_sap_out_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_sap_out.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_out_defs.h ../../inst/io_proc/rtl/iop_sap_out.r
+ *      id: $Id: iop_sap_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_sap_out */
+
+/* Register rw_gen_gated, scope iop_sap_out, type rw */
+typedef struct {
+  unsigned int clk0_src       : 2;
+  unsigned int clk0_gate_src  : 2;
+  unsigned int clk0_force_src : 3;
+  unsigned int clk1_src       : 2;
+  unsigned int clk1_gate_src  : 2;
+  unsigned int clk1_force_src : 3;
+  unsigned int clk2_src       : 2;
+  unsigned int clk2_gate_src  : 2;
+  unsigned int clk2_force_src : 3;
+  unsigned int clk3_src       : 2;
+  unsigned int clk3_gate_src  : 2;
+  unsigned int clk3_force_src : 3;
+  unsigned int dummy1         : 4;
+} reg_iop_sap_out_rw_gen_gated;
+#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0
+#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0
+
+/* Register rw_bus0, scope iop_sap_out, type rw */
+typedef struct {
+  unsigned int byte0_clk_sel   : 3;
+  unsigned int byte0_gated_clk : 2;
+  unsigned int byte0_clk_inv   : 1;
+  unsigned int byte1_clk_sel   : 3;
+  unsigned int byte1_gated_clk : 2;
+  unsigned int byte1_clk_inv   : 1;
+  unsigned int byte2_clk_sel   : 3;
+  unsigned int byte2_gated_clk : 2;
+  unsigned int byte2_clk_inv   : 1;
+  unsigned int byte3_clk_sel   : 3;
+  unsigned int byte3_gated_clk : 2;
+  unsigned int byte3_clk_inv   : 1;
+  unsigned int dummy1          : 8;
+} reg_iop_sap_out_rw_bus0;
+#define REG_RD_ADDR_iop_sap_out_rw_bus0 4
+#define REG_WR_ADDR_iop_sap_out_rw_bus0 4
+
+/* Register rw_bus1, scope iop_sap_out, type rw */
+typedef struct {
+  unsigned int byte0_clk_sel   : 3;
+  unsigned int byte0_gated_clk : 2;
+  unsigned int byte0_clk_inv   : 1;
+  unsigned int byte1_clk_sel   : 3;
+  unsigned int byte1_gated_clk : 2;
+  unsigned int byte1_clk_inv   : 1;
+  unsigned int byte2_clk_sel   : 3;
+  unsigned int byte2_gated_clk : 2;
+  unsigned int byte2_clk_inv   : 1;
+  unsigned int byte3_clk_sel   : 3;
+  unsigned int byte3_gated_clk : 2;
+  unsigned int byte3_clk_inv   : 1;
+  unsigned int dummy1          : 8;
+} reg_iop_sap_out_rw_bus1;
+#define REG_RD_ADDR_iop_sap_out_rw_bus1 8
+#define REG_WR_ADDR_iop_sap_out_rw_bus1 8
+
+/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */
+typedef struct {
+  unsigned int byte0_clk_sel   : 3;
+  unsigned int byte0_clk_ext   : 3;
+  unsigned int byte0_gated_clk : 2;
+  unsigned int byte0_clk_inv   : 1;
+  unsigned int byte0_logic     : 2;
+  unsigned int byte1_clk_sel   : 3;
+  unsigned int byte1_clk_ext   : 3;
+  unsigned int byte1_gated_clk : 2;
+  unsigned int byte1_clk_inv   : 1;
+  unsigned int byte1_logic     : 2;
+  unsigned int dummy1          : 10;
+} reg_iop_sap_out_rw_bus0_lo_oe;
+#define REG_RD_ADDR_iop_sap_out_rw_bus0_lo_oe 12
+#define REG_WR_ADDR_iop_sap_out_rw_bus0_lo_oe 12
+
+/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */
+typedef struct {
+  unsigned int byte2_clk_sel   : 3;
+  unsigned int byte2_clk_ext   : 3;
+  unsigned int byte2_gated_clk : 2;
+  unsigned int byte2_clk_inv   : 1;
+  unsigned int byte2_logic     : 2;
+  unsigned int byte3_clk_sel   : 3;
+  unsigned int byte3_clk_ext   : 3;
+  unsigned int byte3_gated_clk : 2;
+  unsigned int byte3_clk_inv   : 1;
+  unsigned int byte3_logic     : 2;
+  unsigned int dummy1          : 10;
+} reg_iop_sap_out_rw_bus0_hi_oe;
+#define REG_RD_ADDR_iop_sap_out_rw_bus0_hi_oe 16
+#define REG_WR_ADDR_iop_sap_out_rw_bus0_hi_oe 16
+
+/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */
+typedef struct {
+  unsigned int byte0_clk_sel   : 3;
+  unsigned int byte0_clk_ext   : 3;
+  unsigned int byte0_gated_clk : 2;
+  unsigned int byte0_clk_inv   : 1;
+  unsigned int byte0_logic     : 2;
+  unsigned int byte1_clk_sel   : 3;
+  unsigned int byte1_clk_ext   : 3;
+  unsigned int byte1_gated_clk : 2;
+  unsigned int byte1_clk_inv   : 1;
+  unsigned int byte1_logic     : 2;
+  unsigned int dummy1          : 10;
+} reg_iop_sap_out_rw_bus1_lo_oe;
+#define REG_RD_ADDR_iop_sap_out_rw_bus1_lo_oe 20
+#define REG_WR_ADDR_iop_sap_out_rw_bus1_lo_oe 20
+
+/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */
+typedef struct {
+  unsigned int byte2_clk_sel   : 3;
+  unsigned int byte2_clk_ext   : 3;
+  unsigned int byte2_gated_clk : 2;
+  unsigned int byte2_clk_inv   : 1;
+  unsigned int byte2_logic     : 2;
+  unsigned int byte3_clk_sel   : 3;
+  unsigned int byte3_clk_ext   : 3;
+  unsigned int byte3_gated_clk : 2;
+  unsigned int byte3_clk_inv   : 1;
+  unsigned int byte3_logic     : 2;
+  unsigned int dummy1          : 10;
+} reg_iop_sap_out_rw_bus1_hi_oe;
+#define REG_RD_ADDR_iop_sap_out_rw_bus1_hi_oe 24
+#define REG_WR_ADDR_iop_sap_out_rw_bus1_hi_oe 24
+
+#define STRIDE_iop_sap_out_rw_gio 4
+/* Register rw_gio, scope iop_sap_out, type rw */
+typedef struct {
+  unsigned int out_clk_sel   : 3;
+  unsigned int out_clk_ext   : 4;
+  unsigned int out_gated_clk : 2;
+  unsigned int out_clk_inv   : 1;
+  unsigned int out_logic     : 1;
+  unsigned int oe_clk_sel    : 3;
+  unsigned int oe_clk_ext    : 3;
+  unsigned int oe_gated_clk  : 2;
+  unsigned int oe_clk_inv    : 1;
+  unsigned int oe_logic      : 2;
+  unsigned int dummy1        : 10;
+} reg_iop_sap_out_rw_gio;
+#define REG_RD_ADDR_iop_sap_out_rw_gio 28
+#define REG_WR_ADDR_iop_sap_out_rw_gio 28
+
+
+/* Constants */
+enum {
+  regk_iop_sap_out_and                     = 0x00000002,
+  regk_iop_sap_out_clk0                    = 0x00000000,
+  regk_iop_sap_out_clk1                    = 0x00000001,
+  regk_iop_sap_out_clk12                   = 0x00000002,
+  regk_iop_sap_out_clk2                    = 0x00000002,
+  regk_iop_sap_out_clk200                  = 0x00000001,
+  regk_iop_sap_out_clk3                    = 0x00000003,
+  regk_iop_sap_out_ext                     = 0x00000003,
+  regk_iop_sap_out_gated                   = 0x00000004,
+  regk_iop_sap_out_gio1                    = 0x00000000,
+  regk_iop_sap_out_gio13                   = 0x00000002,
+  regk_iop_sap_out_gio13_clk               = 0x0000000c,
+  regk_iop_sap_out_gio15                   = 0x00000001,
+  regk_iop_sap_out_gio18                   = 0x00000003,
+  regk_iop_sap_out_gio18_clk               = 0x0000000d,
+  regk_iop_sap_out_gio1_clk                = 0x00000008,
+  regk_iop_sap_out_gio21_clk               = 0x0000000e,
+  regk_iop_sap_out_gio23                   = 0x00000002,
+  regk_iop_sap_out_gio29_clk               = 0x0000000f,
+  regk_iop_sap_out_gio31                   = 0x00000003,
+  regk_iop_sap_out_gio5                    = 0x00000001,
+  regk_iop_sap_out_gio5_clk                = 0x00000009,
+  regk_iop_sap_out_gio6_clk                = 0x0000000a,
+  regk_iop_sap_out_gio7                    = 0x00000000,
+  regk_iop_sap_out_gio7_clk                = 0x0000000b,
+  regk_iop_sap_out_gio_in13                = 0x00000001,
+  regk_iop_sap_out_gio_in21                = 0x00000002,
+  regk_iop_sap_out_gio_in29                = 0x00000003,
+  regk_iop_sap_out_gio_in5                 = 0x00000000,
+  regk_iop_sap_out_inv                     = 0x00000001,
+  regk_iop_sap_out_nand                    = 0x00000003,
+  regk_iop_sap_out_no                      = 0x00000000,
+  regk_iop_sap_out_none                    = 0x00000000,
+  regk_iop_sap_out_rw_bus0_default         = 0x00000000,
+  regk_iop_sap_out_rw_bus0_hi_oe_default   = 0x00000000,
+  regk_iop_sap_out_rw_bus0_lo_oe_default   = 0x00000000,
+  regk_iop_sap_out_rw_bus1_default         = 0x00000000,
+  regk_iop_sap_out_rw_bus1_hi_oe_default   = 0x00000000,
+  regk_iop_sap_out_rw_bus1_lo_oe_default   = 0x00000000,
+  regk_iop_sap_out_rw_gen_gated_default    = 0x00000000,
+  regk_iop_sap_out_rw_gio_default          = 0x00000000,
+  regk_iop_sap_out_rw_gio_size             = 0x00000020,
+  regk_iop_sap_out_spu0_gio0               = 0x00000002,
+  regk_iop_sap_out_spu0_gio1               = 0x00000003,
+  regk_iop_sap_out_spu0_gio12              = 0x00000004,
+  regk_iop_sap_out_spu0_gio13              = 0x00000004,
+  regk_iop_sap_out_spu0_gio14              = 0x00000004,
+  regk_iop_sap_out_spu0_gio15              = 0x00000004,
+  regk_iop_sap_out_spu0_gio2               = 0x00000002,
+  regk_iop_sap_out_spu0_gio3               = 0x00000003,
+  regk_iop_sap_out_spu0_gio4               = 0x00000002,
+  regk_iop_sap_out_spu0_gio5               = 0x00000003,
+  regk_iop_sap_out_spu0_gio6               = 0x00000002,
+  regk_iop_sap_out_spu0_gio7               = 0x00000003,
+  regk_iop_sap_out_spu1_gio0               = 0x00000005,
+  regk_iop_sap_out_spu1_gio1               = 0x00000006,
+  regk_iop_sap_out_spu1_gio12              = 0x00000007,
+  regk_iop_sap_out_spu1_gio13              = 0x00000007,
+  regk_iop_sap_out_spu1_gio14              = 0x00000007,
+  regk_iop_sap_out_spu1_gio15              = 0x00000007,
+  regk_iop_sap_out_spu1_gio2               = 0x00000005,
+  regk_iop_sap_out_spu1_gio3               = 0x00000006,
+  regk_iop_sap_out_spu1_gio4               = 0x00000005,
+  regk_iop_sap_out_spu1_gio5               = 0x00000006,
+  regk_iop_sap_out_spu1_gio6               = 0x00000005,
+  regk_iop_sap_out_spu1_gio7               = 0x00000006,
+  regk_iop_sap_out_timer_grp0_tmr2         = 0x00000004,
+  regk_iop_sap_out_timer_grp1_tmr2         = 0x00000005,
+  regk_iop_sap_out_timer_grp2_tmr2         = 0x00000006,
+  regk_iop_sap_out_timer_grp3_tmr2         = 0x00000007,
+  regk_iop_sap_out_tmr                     = 0x00000005,
+  regk_iop_sap_out_yes                     = 0x00000001
+};
+#endif /* __iop_sap_out_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h
new file mode 100644
index 00000000000..4f0a9a81e73
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_in_defs.h
@@ -0,0 +1,160 @@
+#ifndef __iop_scrc_in_defs_h
+#define __iop_scrc_in_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_scrc_in.r
+ *     id:           iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_in_defs.h ../../inst/io_proc/rtl/iop_scrc_in.r
+ *      id: $Id: iop_scrc_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_scrc_in */
+
+/* Register rw_cfg, scope iop_scrc_in, type rw */
+typedef struct {
+  unsigned int trig : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_scrc_in_rw_cfg;
+#define REG_RD_ADDR_iop_scrc_in_rw_cfg 0
+#define REG_WR_ADDR_iop_scrc_in_rw_cfg 0
+
+/* Register rw_ctrl, scope iop_scrc_in, type rw */
+typedef struct {
+  unsigned int dif_in_en : 1;
+  unsigned int dummy1    : 31;
+} reg_iop_scrc_in_rw_ctrl;
+#define REG_RD_ADDR_iop_scrc_in_rw_ctrl 4
+#define REG_WR_ADDR_iop_scrc_in_rw_ctrl 4
+
+/* Register r_stat, scope iop_scrc_in, type r */
+typedef struct {
+  unsigned int err : 1;
+  unsigned int dummy1 : 31;
+} reg_iop_scrc_in_r_stat;
+#define REG_RD_ADDR_iop_scrc_in_r_stat 8
+
+/* Register rw_init_crc, scope iop_scrc_in, type rw */
+typedef unsigned int reg_iop_scrc_in_rw_init_crc;
+#define REG_RD_ADDR_iop_scrc_in_rw_init_crc 12
+#define REG_WR_ADDR_iop_scrc_in_rw_init_crc 12
+
+/* Register rs_computed_crc, scope iop_scrc_in, type rs */
+typedef unsigned int reg_iop_scrc_in_rs_computed_crc;
+#define REG_RD_ADDR_iop_scrc_in_rs_computed_crc 16
+
+/* Register r_computed_crc, scope iop_scrc_in, type r */
+typedef unsigned int reg_iop_scrc_in_r_computed_crc;
+#define REG_RD_ADDR_iop_scrc_in_r_computed_crc 20
+
+/* Register rw_crc, scope iop_scrc_in, type rw */
+typedef unsigned int reg_iop_scrc_in_rw_crc;
+#define REG_RD_ADDR_iop_scrc_in_rw_crc 24
+#define REG_WR_ADDR_iop_scrc_in_rw_crc 24
+
+/* Register rw_correct_crc, scope iop_scrc_in, type rw */
+typedef unsigned int reg_iop_scrc_in_rw_correct_crc;
+#define REG_RD_ADDR_iop_scrc_in_rw_correct_crc 28
+#define REG_WR_ADDR_iop_scrc_in_rw_correct_crc 28
+
+/* Register rw_wr1bit, scope iop_scrc_in, type rw */
+typedef struct {
+  unsigned int data : 2;
+  unsigned int last : 2;
+  unsigned int dummy1 : 28;
+} reg_iop_scrc_in_rw_wr1bit;
+#define REG_RD_ADDR_iop_scrc_in_rw_wr1bit 32
+#define REG_WR_ADDR_iop_scrc_in_rw_wr1bit 32
+
+
+/* Constants */
+enum {
+  regk_iop_scrc_in_dif_in                  = 0x00000002,
+  regk_iop_scrc_in_hi                      = 0x00000000,
+  regk_iop_scrc_in_neg                     = 0x00000002,
+  regk_iop_scrc_in_no                      = 0x00000000,
+  regk_iop_scrc_in_pos                     = 0x00000001,
+  regk_iop_scrc_in_pos_neg                 = 0x00000003,
+  regk_iop_scrc_in_r_computed_crc_default  = 0x00000000,
+  regk_iop_scrc_in_rs_computed_crc_default = 0x00000000,
+  regk_iop_scrc_in_rw_cfg_default          = 0x00000000,
+  regk_iop_scrc_in_rw_ctrl_default         = 0x00000000,
+  regk_iop_scrc_in_rw_init_crc_default     = 0x00000000,
+  regk_iop_scrc_in_set0                    = 0x00000000,
+  regk_iop_scrc_in_set1                    = 0x00000001,
+  regk_iop_scrc_in_yes                     = 0x00000001
+};
+#endif /* __iop_scrc_in_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h
new file mode 100644
index 00000000000..fd1d6ea1d48
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_scrc_out_defs.h
@@ -0,0 +1,146 @@
+#ifndef __iop_scrc_out_defs_h
+#define __iop_scrc_out_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_scrc_out.r
+ *     id:           iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_out_defs.h ../../inst/io_proc/rtl/iop_scrc_out.r
+ *      id: $Id: iop_scrc_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_scrc_out */
+
+/* Register rw_cfg, scope iop_scrc_out, type rw */
+typedef struct {
+  unsigned int trig    : 2;
+  unsigned int inv_crc : 1;
+  unsigned int dummy1  : 29;
+} reg_iop_scrc_out_rw_cfg;
+#define REG_RD_ADDR_iop_scrc_out_rw_cfg 0
+#define REG_WR_ADDR_iop_scrc_out_rw_cfg 0
+
+/* Register rw_ctrl, scope iop_scrc_out, type rw */
+typedef struct {
+  unsigned int strb_src : 1;
+  unsigned int out_src  : 1;
+  unsigned int dummy1   : 30;
+} reg_iop_scrc_out_rw_ctrl;
+#define REG_RD_ADDR_iop_scrc_out_rw_ctrl 4
+#define REG_WR_ADDR_iop_scrc_out_rw_ctrl 4
+
+/* Register rw_init_crc, scope iop_scrc_out, type rw */
+typedef unsigned int reg_iop_scrc_out_rw_init_crc;
+#define REG_RD_ADDR_iop_scrc_out_rw_init_crc 8
+#define REG_WR_ADDR_iop_scrc_out_rw_init_crc 8
+
+/* Register rw_crc, scope iop_scrc_out, type rw */
+typedef unsigned int reg_iop_scrc_out_rw_crc;
+#define REG_RD_ADDR_iop_scrc_out_rw_crc 12
+#define REG_WR_ADDR_iop_scrc_out_rw_crc 12
+
+/* Register rw_data, scope iop_scrc_out, type rw */
+typedef struct {
+  unsigned int val : 1;
+  unsigned int dummy1 : 31;
+} reg_iop_scrc_out_rw_data;
+#define REG_RD_ADDR_iop_scrc_out_rw_data 16
+#define REG_WR_ADDR_iop_scrc_out_rw_data 16
+
+/* Register r_computed_crc, scope iop_scrc_out, type r */
+typedef unsigned int reg_iop_scrc_out_r_computed_crc;
+#define REG_RD_ADDR_iop_scrc_out_r_computed_crc 20
+
+
+/* Constants */
+enum {
+  regk_iop_scrc_out_crc                    = 0x00000001,
+  regk_iop_scrc_out_data                   = 0x00000000,
+  regk_iop_scrc_out_dif                    = 0x00000001,
+  regk_iop_scrc_out_hi                     = 0x00000000,
+  regk_iop_scrc_out_neg                    = 0x00000002,
+  regk_iop_scrc_out_no                     = 0x00000000,
+  regk_iop_scrc_out_pos                    = 0x00000001,
+  regk_iop_scrc_out_pos_neg                = 0x00000003,
+  regk_iop_scrc_out_reg                    = 0x00000000,
+  regk_iop_scrc_out_rw_cfg_default         = 0x00000000,
+  regk_iop_scrc_out_rw_crc_default         = 0x00000000,
+  regk_iop_scrc_out_rw_ctrl_default        = 0x00000000,
+  regk_iop_scrc_out_rw_data_default        = 0x00000000,
+  regk_iop_scrc_out_rw_init_crc_default    = 0x00000000,
+  regk_iop_scrc_out_yes                    = 0x00000001
+};
+#endif /* __iop_scrc_out_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h
new file mode 100644
index 00000000000..0fda26e2f06
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_spu_defs.h
@@ -0,0 +1,453 @@
+#ifndef __iop_spu_defs_h
+#define __iop_spu_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_spu.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_spu_defs.h ../../inst/io_proc/rtl/iop_spu.r
+ *      id: $Id: iop_spu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_spu */
+
+#define STRIDE_iop_spu_rw_r 4
+/* Register rw_r, scope iop_spu, type rw */
+typedef unsigned int reg_iop_spu_rw_r;
+#define REG_RD_ADDR_iop_spu_rw_r 0
+#define REG_WR_ADDR_iop_spu_rw_r 0
+
+/* Register rw_seq_pc, scope iop_spu, type rw */
+typedef struct {
+  unsigned int addr : 12;
+  unsigned int dummy1 : 20;
+} reg_iop_spu_rw_seq_pc;
+#define REG_RD_ADDR_iop_spu_rw_seq_pc 64
+#define REG_WR_ADDR_iop_spu_rw_seq_pc 64
+
+/* Register rw_fsm_pc, scope iop_spu, type rw */
+typedef struct {
+  unsigned int addr : 12;
+  unsigned int dummy1 : 20;
+} reg_iop_spu_rw_fsm_pc;
+#define REG_RD_ADDR_iop_spu_rw_fsm_pc 68
+#define REG_WR_ADDR_iop_spu_rw_fsm_pc 68
+
+/* Register rw_ctrl, scope iop_spu, type rw */
+typedef struct {
+  unsigned int fsm : 1;
+  unsigned int en  : 1;
+  unsigned int dummy1 : 30;
+} reg_iop_spu_rw_ctrl;
+#define REG_RD_ADDR_iop_spu_rw_ctrl 72
+#define REG_WR_ADDR_iop_spu_rw_ctrl 72
+
+/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */
+typedef struct {
+  unsigned int val0 : 5;
+  unsigned int src0 : 3;
+  unsigned int val1 : 5;
+  unsigned int src1 : 3;
+  unsigned int val2 : 5;
+  unsigned int src2 : 3;
+  unsigned int val3 : 5;
+  unsigned int src3 : 3;
+} reg_iop_spu_rw_fsm_inputs3_0;
+#define REG_RD_ADDR_iop_spu_rw_fsm_inputs3_0 76
+#define REG_WR_ADDR_iop_spu_rw_fsm_inputs3_0 76
+
+/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */
+typedef struct {
+  unsigned int val4 : 5;
+  unsigned int src4 : 3;
+  unsigned int val5 : 5;
+  unsigned int src5 : 3;
+  unsigned int val6 : 5;
+  unsigned int src6 : 3;
+  unsigned int val7 : 5;
+  unsigned int src7 : 3;
+} reg_iop_spu_rw_fsm_inputs7_4;
+#define REG_RD_ADDR_iop_spu_rw_fsm_inputs7_4 80
+#define REG_WR_ADDR_iop_spu_rw_fsm_inputs7_4 80
+
+/* Register rw_gio_out, scope iop_spu, type rw */
+typedef unsigned int reg_iop_spu_rw_gio_out;
+#define REG_RD_ADDR_iop_spu_rw_gio_out 84
+#define REG_WR_ADDR_iop_spu_rw_gio_out 84
+
+/* Register rw_bus0_out, scope iop_spu, type rw */
+typedef unsigned int reg_iop_spu_rw_bus0_out;
+#define REG_RD_ADDR_iop_spu_rw_bus0_out 88
+#define REG_WR_ADDR_iop_spu_rw_bus0_out 88
+
+/* Register rw_bus1_out, scope iop_spu, type rw */
+typedef unsigned int reg_iop_spu_rw_bus1_out;
+#define REG_RD_ADDR_iop_spu_rw_bus1_out 92
+#define REG_WR_ADDR_iop_spu_rw_bus1_out 92
+
+/* Register r_gio_in, scope iop_spu, type r */
+typedef unsigned int reg_iop_spu_r_gio_in;
+#define REG_RD_ADDR_iop_spu_r_gio_in 96
+
+/* Register r_bus0_in, scope iop_spu, type r */
+typedef unsigned int reg_iop_spu_r_bus0_in;
+#define REG_RD_ADDR_iop_spu_r_bus0_in 100
+
+/* Register r_bus1_in, scope iop_spu, type r */
+typedef unsigned int reg_iop_spu_r_bus1_in;
+#define REG_RD_ADDR_iop_spu_r_bus1_in 104
+
+/* Register rw_gio_out_set, scope iop_spu, type rw */
+typedef unsigned int reg_iop_spu_rw_gio_out_set;
+#define REG_RD_ADDR_iop_spu_rw_gio_out_set 108
+#define REG_WR_ADDR_iop_spu_rw_gio_out_set 108
+
+/* Register rw_gio_out_clr, scope iop_spu, type rw */
+typedef unsigned int reg_iop_spu_rw_gio_out_clr;
+#define REG_RD_ADDR_iop_spu_rw_gio_out_clr 112
+#define REG_WR_ADDR_iop_spu_rw_gio_out_clr 112
+
+/* Register rs_wr_stat, scope iop_spu, type rs */
+typedef struct {
+  unsigned int r0  : 1;
+  unsigned int r1  : 1;
+  unsigned int r2  : 1;
+  unsigned int r3  : 1;
+  unsigned int r4  : 1;
+  unsigned int r5  : 1;
+  unsigned int r6  : 1;
+  unsigned int r7  : 1;
+  unsigned int r8  : 1;
+  unsigned int r9  : 1;
+  unsigned int r10 : 1;
+  unsigned int r11 : 1;
+  unsigned int r12 : 1;
+  unsigned int r13 : 1;
+  unsigned int r14 : 1;
+  unsigned int r15 : 1;
+  unsigned int dummy1 : 16;
+} reg_iop_spu_rs_wr_stat;
+#define REG_RD_ADDR_iop_spu_rs_wr_stat 116
+
+/* Register r_wr_stat, scope iop_spu, type r */
+typedef struct {
+  unsigned int r0  : 1;
+  unsigned int r1  : 1;
+  unsigned int r2  : 1;
+  unsigned int r3  : 1;
+  unsigned int r4  : 1;
+  unsigned int r5  : 1;
+  unsigned int r6  : 1;
+  unsigned int r7  : 1;
+  unsigned int r8  : 1;
+  unsigned int r9  : 1;
+  unsigned int r10 : 1;
+  unsigned int r11 : 1;
+  unsigned int r12 : 1;
+  unsigned int r13 : 1;
+  unsigned int r14 : 1;
+  unsigned int r15 : 1;
+  unsigned int dummy1 : 16;
+} reg_iop_spu_r_wr_stat;
+#define REG_RD_ADDR_iop_spu_r_wr_stat 120
+
+/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */
+typedef unsigned int reg_iop_spu_r_reg_indexed_by_bus0_in;
+#define REG_RD_ADDR_iop_spu_r_reg_indexed_by_bus0_in 124
+
+/* Register r_stat_in, scope iop_spu, type r */
+typedef struct {
+  unsigned int timer_grp_lo    : 4;
+  unsigned int fifo_out_last   : 1;
+  unsigned int fifo_out_rdy    : 1;
+  unsigned int fifo_out_all    : 1;
+  unsigned int fifo_in_rdy     : 1;
+  unsigned int dmc_out_all     : 1;
+  unsigned int dmc_out_dth     : 1;
+  unsigned int dmc_out_eop     : 1;
+  unsigned int dmc_out_dv      : 1;
+  unsigned int dmc_out_last    : 1;
+  unsigned int dmc_out_cmd_rq  : 1;
+  unsigned int dmc_out_cmd_rdy : 1;
+  unsigned int pcrc_correct    : 1;
+  unsigned int timer_grp_hi    : 4;
+  unsigned int dmc_in_sth      : 1;
+  unsigned int dmc_in_full     : 1;
+  unsigned int dmc_in_cmd_rdy  : 1;
+  unsigned int spu_gio_out     : 4;
+  unsigned int sync_clk12      : 1;
+  unsigned int scrc_out_data   : 1;
+  unsigned int scrc_in_err     : 1;
+  unsigned int mc_busy         : 1;
+  unsigned int mc_owned        : 1;
+} reg_iop_spu_r_stat_in;
+#define REG_RD_ADDR_iop_spu_r_stat_in 128
+
+/* Register r_trigger_in, scope iop_spu, type r */
+typedef unsigned int reg_iop_spu_r_trigger_in;
+#define REG_RD_ADDR_iop_spu_r_trigger_in 132
+
+/* Register r_special_stat, scope iop_spu, type r */
+typedef struct {
+  unsigned int c_flag         : 1;
+  unsigned int v_flag         : 1;
+  unsigned int z_flag         : 1;
+  unsigned int n_flag         : 1;
+  unsigned int xor_bus0_r2_0  : 1;
+  unsigned int xor_bus1_r3_0  : 1;
+  unsigned int xor_bus0m_r2_0 : 1;
+  unsigned int xor_bus1m_r3_0 : 1;
+  unsigned int fsm_in0        : 1;
+  unsigned int fsm_in1        : 1;
+  unsigned int fsm_in2        : 1;
+  unsigned int fsm_in3        : 1;
+  unsigned int fsm_in4        : 1;
+  unsigned int fsm_in5        : 1;
+  unsigned int fsm_in6        : 1;
+  unsigned int fsm_in7        : 1;
+  unsigned int event0         : 1;
+  unsigned int event1         : 1;
+  unsigned int event2         : 1;
+  unsigned int event3         : 1;
+  unsigned int dummy1         : 12;
+} reg_iop_spu_r_special_stat;
+#define REG_RD_ADDR_iop_spu_r_special_stat 136
+
+/* Register rw_reg_access, scope iop_spu, type rw */
+typedef struct {
+  unsigned int addr   : 13;
+  unsigned int dummy1 : 3;
+  unsigned int imm_hi : 16;
+} reg_iop_spu_rw_reg_access;
+#define REG_RD_ADDR_iop_spu_rw_reg_access 140
+#define REG_WR_ADDR_iop_spu_rw_reg_access 140
+
+#define STRIDE_iop_spu_rw_event_cfg 4
+/* Register rw_event_cfg, scope iop_spu, type rw */
+typedef struct {
+  unsigned int addr   : 12;
+  unsigned int src    : 2;
+  unsigned int eq_en  : 1;
+  unsigned int eq_inv : 1;
+  unsigned int gt_en  : 1;
+  unsigned int gt_inv : 1;
+  unsigned int dummy1 : 14;
+} reg_iop_spu_rw_event_cfg;
+#define REG_RD_ADDR_iop_spu_rw_event_cfg 144
+#define REG_WR_ADDR_iop_spu_rw_event_cfg 144
+
+#define STRIDE_iop_spu_rw_event_mask 4
+/* Register rw_event_mask, scope iop_spu, type rw */
+typedef unsigned int reg_iop_spu_rw_event_mask;
+#define REG_RD_ADDR_iop_spu_rw_event_mask 160
+#define REG_WR_ADDR_iop_spu_rw_event_mask 160
+
+#define STRIDE_iop_spu_rw_event_val 4
+/* Register rw_event_val, scope iop_spu, type rw */
+typedef unsigned int reg_iop_spu_rw_event_val;
+#define REG_RD_ADDR_iop_spu_rw_event_val 176
+#define REG_WR_ADDR_iop_spu_rw_event_val 176
+
+/* Register rw_event_ret, scope iop_spu, type rw */
+typedef struct {
+  unsigned int addr : 12;
+  unsigned int dummy1 : 20;
+} reg_iop_spu_rw_event_ret;
+#define REG_RD_ADDR_iop_spu_rw_event_ret 192
+#define REG_WR_ADDR_iop_spu_rw_event_ret 192
+
+/* Register r_trace, scope iop_spu, type r */
+typedef struct {
+  unsigned int fsm      : 1;
+  unsigned int en       : 1;
+  unsigned int c_flag   : 1;
+  unsigned int v_flag   : 1;
+  unsigned int z_flag   : 1;
+  unsigned int n_flag   : 1;
+  unsigned int seq_addr : 12;
+  unsigned int dummy1   : 2;
+  unsigned int fsm_addr : 12;
+} reg_iop_spu_r_trace;
+#define REG_RD_ADDR_iop_spu_r_trace 196
+
+/* Register r_fsm_trace, scope iop_spu, type r */
+typedef struct {
+  unsigned int fsm      : 1;
+  unsigned int en       : 1;
+  unsigned int tmr_done : 1;
+  unsigned int inp0     : 1;
+  unsigned int inp1     : 1;
+  unsigned int inp2     : 1;
+  unsigned int inp3     : 1;
+  unsigned int event0   : 1;
+  unsigned int event1   : 1;
+  unsigned int event2   : 1;
+  unsigned int event3   : 1;
+  unsigned int gio_out  : 8;
+  unsigned int dummy1   : 1;
+  unsigned int fsm_addr : 12;
+} reg_iop_spu_r_fsm_trace;
+#define REG_RD_ADDR_iop_spu_r_fsm_trace 200
+
+#define STRIDE_iop_spu_rw_brp 4
+/* Register rw_brp, scope iop_spu, type rw */
+typedef struct {
+  unsigned int addr : 12;
+  unsigned int fsm  : 1;
+  unsigned int en   : 1;
+  unsigned int dummy1 : 18;
+} reg_iop_spu_rw_brp;
+#define REG_RD_ADDR_iop_spu_rw_brp 204
+#define REG_WR_ADDR_iop_spu_rw_brp 204
+
+
+/* Constants */
+enum {
+  regk_iop_spu_attn_hi                     = 0x00000005,
+  regk_iop_spu_attn_lo                     = 0x00000005,
+  regk_iop_spu_attn_r0                     = 0x00000000,
+  regk_iop_spu_attn_r1                     = 0x00000001,
+  regk_iop_spu_attn_r10                    = 0x00000002,
+  regk_iop_spu_attn_r11                    = 0x00000003,
+  regk_iop_spu_attn_r12                    = 0x00000004,
+  regk_iop_spu_attn_r13                    = 0x00000005,
+  regk_iop_spu_attn_r14                    = 0x00000006,
+  regk_iop_spu_attn_r15                    = 0x00000007,
+  regk_iop_spu_attn_r2                     = 0x00000002,
+  regk_iop_spu_attn_r3                     = 0x00000003,
+  regk_iop_spu_attn_r4                     = 0x00000004,
+  regk_iop_spu_attn_r5                     = 0x00000005,
+  regk_iop_spu_attn_r6                     = 0x00000006,
+  regk_iop_spu_attn_r7                     = 0x00000007,
+  regk_iop_spu_attn_r8                     = 0x00000000,
+  regk_iop_spu_attn_r9                     = 0x00000001,
+  regk_iop_spu_c                           = 0x00000000,
+  regk_iop_spu_flag                        = 0x00000002,
+  regk_iop_spu_gio_in                      = 0x00000000,
+  regk_iop_spu_gio_out                     = 0x00000005,
+  regk_iop_spu_gio_out0                    = 0x00000008,
+  regk_iop_spu_gio_out1                    = 0x00000009,
+  regk_iop_spu_gio_out2                    = 0x0000000a,
+  regk_iop_spu_gio_out3                    = 0x0000000b,
+  regk_iop_spu_gio_out4                    = 0x0000000c,
+  regk_iop_spu_gio_out5                    = 0x0000000d,
+  regk_iop_spu_gio_out6                    = 0x0000000e,
+  regk_iop_spu_gio_out7                    = 0x0000000f,
+  regk_iop_spu_n                           = 0x00000003,
+  regk_iop_spu_no                          = 0x00000000,
+  regk_iop_spu_r0                          = 0x00000008,
+  regk_iop_spu_r1                          = 0x00000009,
+  regk_iop_spu_r10                         = 0x0000000a,
+  regk_iop_spu_r11                         = 0x0000000b,
+  regk_iop_spu_r12                         = 0x0000000c,
+  regk_iop_spu_r13                         = 0x0000000d,
+  regk_iop_spu_r14                         = 0x0000000e,
+  regk_iop_spu_r15                         = 0x0000000f,
+  regk_iop_spu_r2                          = 0x0000000a,
+  regk_iop_spu_r3                          = 0x0000000b,
+  regk_iop_spu_r4                          = 0x0000000c,
+  regk_iop_spu_r5                          = 0x0000000d,
+  regk_iop_spu_r6                          = 0x0000000e,
+  regk_iop_spu_r7                          = 0x0000000f,
+  regk_iop_spu_r8                          = 0x00000008,
+  regk_iop_spu_r9                          = 0x00000009,
+  regk_iop_spu_reg_hi                      = 0x00000002,
+  regk_iop_spu_reg_lo                      = 0x00000002,
+  regk_iop_spu_rw_brp_default              = 0x00000000,
+  regk_iop_spu_rw_brp_size                 = 0x00000004,
+  regk_iop_spu_rw_ctrl_default             = 0x00000000,
+  regk_iop_spu_rw_event_cfg_size           = 0x00000004,
+  regk_iop_spu_rw_event_mask_size          = 0x00000004,
+  regk_iop_spu_rw_event_val_size           = 0x00000004,
+  regk_iop_spu_rw_gio_out_default          = 0x00000000,
+  regk_iop_spu_rw_r_size                   = 0x00000010,
+  regk_iop_spu_rw_reg_access_default       = 0x00000000,
+  regk_iop_spu_stat_in                     = 0x00000002,
+  regk_iop_spu_statin_hi                   = 0x00000004,
+  regk_iop_spu_statin_lo                   = 0x00000004,
+  regk_iop_spu_trig                        = 0x00000003,
+  regk_iop_spu_trigger                     = 0x00000006,
+  regk_iop_spu_v                           = 0x00000001,
+  regk_iop_spu_wsts_gioout_spec            = 0x00000001,
+  regk_iop_spu_xor                         = 0x00000003,
+  regk_iop_spu_xor_bus0_r2_0               = 0x00000000,
+  regk_iop_spu_xor_bus0m_r2_0              = 0x00000002,
+  regk_iop_spu_xor_bus1_r3_0               = 0x00000001,
+  regk_iop_spu_xor_bus1m_r3_0              = 0x00000003,
+  regk_iop_spu_yes                         = 0x00000001,
+  regk_iop_spu_z                           = 0x00000002
+};
+#endif /* __iop_spu_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h
new file mode 100644
index 00000000000..d7b6d75884d
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cfg_defs.h
@@ -0,0 +1,1042 @@
+#ifndef __iop_sw_cfg_defs_h
+#define __iop_sw_cfg_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:19 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cfg_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
+ *      id: $Id: iop_sw_cfg_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_sw_cfg */
+
+/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_crc_par0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par0_owner 0
+#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par0_owner 0
+
+/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_crc_par1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par1_owner 4
+#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par1_owner 4
+
+/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_dmc_in0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8
+#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8
+
+/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_dmc_in1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12
+#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12
+
+/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_dmc_out0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16
+#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16
+
+/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_dmc_out1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20
+#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20
+
+/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_fifo_in0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24
+#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24
+
+/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_fifo_in0_extra_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28
+#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28
+
+/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_fifo_in1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32
+#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32
+
+/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_fifo_in1_extra_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36
+#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36
+
+/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_fifo_out0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40
+#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40
+
+/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_fifo_out0_extra_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44
+#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44
+
+/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_fifo_out1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48
+#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48
+
+/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_fifo_out1_extra_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52
+#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52
+
+/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_sap_in_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 56
+#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 56
+
+/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_sap_out_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 60
+#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 60
+
+/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_scrc_in0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64
+#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64
+
+/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_scrc_in1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68
+#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68
+
+/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_scrc_out0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72
+#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72
+
+/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_scrc_out1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76
+#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76
+
+/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_spu0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_owner 80
+#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_owner 80
+
+/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_spu1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_owner 84
+#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_owner 84
+
+/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_timer_grp0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88
+#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88
+
+/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_timer_grp1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92
+#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92
+
+/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_timer_grp2_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96
+#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96
+
+/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_timer_grp3_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100
+#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100
+
+/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104
+
+/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108
+
+/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp2_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112
+
+/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp3_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116
+
+/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp4_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120
+
+/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp5_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124
+
+/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp6_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128
+
+/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp7_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132
+
+/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_cfg_rw_bus0_mask;
+#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_mask 136
+#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_mask 136
+
+/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_cfg_rw_bus0_oe_mask;
+#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140
+#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140
+
+/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_cfg_rw_bus1_mask;
+#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_mask 144
+#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_mask 144
+
+/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_cfg_rw_bus1_oe_mask;
+#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148
+#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148
+
+/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_cfg_rw_gio_mask;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 152
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 152
+
+/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_cfg_rw_gio_oe_mask;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 156
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 156
+
+/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int bus0_byte0 : 2;
+  unsigned int bus0_byte1 : 2;
+  unsigned int bus0_byte2 : 2;
+  unsigned int bus0_byte3 : 2;
+  unsigned int bus1_byte0 : 2;
+  unsigned int bus1_byte1 : 2;
+  unsigned int bus1_byte2 : 2;
+  unsigned int bus1_byte3 : 2;
+  unsigned int gio3_0     : 2;
+  unsigned int gio7_4     : 2;
+  unsigned int gio11_8    : 2;
+  unsigned int gio15_12   : 2;
+  unsigned int gio19_16   : 2;
+  unsigned int gio23_20   : 2;
+  unsigned int gio27_24   : 2;
+  unsigned int gio31_28   : 2;
+} reg_iop_sw_cfg_rw_pinmapping;
+#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 160
+#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 160
+
+/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int bus0_lo    : 3;
+  unsigned int bus0_hi    : 3;
+  unsigned int bus0_lo_oe : 3;
+  unsigned int bus0_hi_oe : 3;
+  unsigned int bus1_lo    : 3;
+  unsigned int bus1_hi    : 3;
+  unsigned int bus1_lo_oe : 3;
+  unsigned int bus1_hi_oe : 3;
+  unsigned int dummy1     : 8;
+} reg_iop_sw_cfg_rw_bus_out_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 164
+#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 164
+
+/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int gio0    : 4;
+  unsigned int gio0_oe : 2;
+  unsigned int gio1    : 4;
+  unsigned int gio1_oe : 2;
+  unsigned int gio2    : 4;
+  unsigned int gio2_oe : 2;
+  unsigned int gio3    : 4;
+  unsigned int gio3_oe : 2;
+  unsigned int dummy1  : 8;
+} reg_iop_sw_cfg_rw_gio_out_grp0_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168
+
+/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int gio4    : 4;
+  unsigned int gio4_oe : 2;
+  unsigned int gio5    : 4;
+  unsigned int gio5_oe : 2;
+  unsigned int gio6    : 4;
+  unsigned int gio6_oe : 2;
+  unsigned int gio7    : 4;
+  unsigned int gio7_oe : 2;
+  unsigned int dummy1  : 8;
+} reg_iop_sw_cfg_rw_gio_out_grp1_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172
+
+/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int gio8     : 4;
+  unsigned int gio8_oe  : 2;
+  unsigned int gio9     : 4;
+  unsigned int gio9_oe  : 2;
+  unsigned int gio10    : 4;
+  unsigned int gio10_oe : 2;
+  unsigned int gio11    : 4;
+  unsigned int gio11_oe : 2;
+  unsigned int dummy1   : 8;
+} reg_iop_sw_cfg_rw_gio_out_grp2_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176
+
+/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int gio12    : 4;
+  unsigned int gio12_oe : 2;
+  unsigned int gio13    : 4;
+  unsigned int gio13_oe : 2;
+  unsigned int gio14    : 4;
+  unsigned int gio14_oe : 2;
+  unsigned int gio15    : 4;
+  unsigned int gio15_oe : 2;
+  unsigned int dummy1   : 8;
+} reg_iop_sw_cfg_rw_gio_out_grp3_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180
+
+/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int gio16    : 4;
+  unsigned int gio16_oe : 2;
+  unsigned int gio17    : 4;
+  unsigned int gio17_oe : 2;
+  unsigned int gio18    : 4;
+  unsigned int gio18_oe : 2;
+  unsigned int gio19    : 4;
+  unsigned int gio19_oe : 2;
+  unsigned int dummy1   : 8;
+} reg_iop_sw_cfg_rw_gio_out_grp4_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184
+
+/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int gio20    : 4;
+  unsigned int gio20_oe : 2;
+  unsigned int gio21    : 4;
+  unsigned int gio21_oe : 2;
+  unsigned int gio22    : 4;
+  unsigned int gio22_oe : 2;
+  unsigned int gio23    : 4;
+  unsigned int gio23_oe : 2;
+  unsigned int dummy1   : 8;
+} reg_iop_sw_cfg_rw_gio_out_grp5_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188
+
+/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int gio24    : 4;
+  unsigned int gio24_oe : 2;
+  unsigned int gio25    : 4;
+  unsigned int gio25_oe : 2;
+  unsigned int gio26    : 4;
+  unsigned int gio26_oe : 2;
+  unsigned int gio27    : 4;
+  unsigned int gio27_oe : 2;
+  unsigned int dummy1   : 8;
+} reg_iop_sw_cfg_rw_gio_out_grp6_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192
+
+/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int gio28    : 4;
+  unsigned int gio28_oe : 2;
+  unsigned int gio29    : 4;
+  unsigned int gio29_oe : 2;
+  unsigned int gio30    : 4;
+  unsigned int gio30_oe : 2;
+  unsigned int gio31    : 4;
+  unsigned int gio31_oe : 2;
+  unsigned int dummy1   : 8;
+} reg_iop_sw_cfg_rw_gio_out_grp7_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196
+
+/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int bus0_in : 2;
+  unsigned int bus1_in : 2;
+  unsigned int dummy1  : 28;
+} reg_iop_sw_cfg_rw_spu0_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_cfg 200
+#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_cfg 200
+
+/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int bus0_in : 2;
+  unsigned int bus1_in : 2;
+  unsigned int dummy1  : 28;
+} reg_iop_sw_cfg_rw_spu1_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_cfg 204
+#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_cfg 204
+
+/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int ext_clk  : 3;
+  unsigned int tmr0_en  : 1;
+  unsigned int tmr1_en  : 1;
+  unsigned int tmr2_en  : 1;
+  unsigned int tmr3_en  : 1;
+  unsigned int tmr0_dis : 1;
+  unsigned int tmr1_dis : 1;
+  unsigned int tmr2_dis : 1;
+  unsigned int tmr3_dis : 1;
+  unsigned int dummy1   : 21;
+} reg_iop_sw_cfg_rw_timer_grp0_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208
+#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208
+
+/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int ext_clk  : 3;
+  unsigned int tmr0_en  : 1;
+  unsigned int tmr1_en  : 1;
+  unsigned int tmr2_en  : 1;
+  unsigned int tmr3_en  : 1;
+  unsigned int tmr0_dis : 1;
+  unsigned int tmr1_dis : 1;
+  unsigned int tmr2_dis : 1;
+  unsigned int tmr3_dis : 1;
+  unsigned int dummy1   : 21;
+} reg_iop_sw_cfg_rw_timer_grp1_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212
+#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212
+
+/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int ext_clk  : 3;
+  unsigned int tmr0_en  : 1;
+  unsigned int tmr1_en  : 1;
+  unsigned int tmr2_en  : 1;
+  unsigned int tmr3_en  : 1;
+  unsigned int tmr0_dis : 1;
+  unsigned int tmr1_dis : 1;
+  unsigned int tmr2_dis : 1;
+  unsigned int tmr3_dis : 1;
+  unsigned int dummy1   : 21;
+} reg_iop_sw_cfg_rw_timer_grp2_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216
+#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216
+
+/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int ext_clk  : 3;
+  unsigned int tmr0_en  : 1;
+  unsigned int tmr1_en  : 1;
+  unsigned int tmr2_en  : 1;
+  unsigned int tmr3_en  : 1;
+  unsigned int tmr0_dis : 1;
+  unsigned int tmr1_dis : 1;
+  unsigned int tmr2_dis : 1;
+  unsigned int tmr3_dis : 1;
+  unsigned int dummy1   : 21;
+} reg_iop_sw_cfg_rw_timer_grp3_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220
+#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220
+
+/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int grp0_dis : 1;
+  unsigned int grp0_en  : 1;
+  unsigned int grp1_dis : 1;
+  unsigned int grp1_en  : 1;
+  unsigned int grp2_dis : 1;
+  unsigned int grp2_en  : 1;
+  unsigned int grp3_dis : 1;
+  unsigned int grp3_en  : 1;
+  unsigned int grp4_dis : 1;
+  unsigned int grp4_en  : 1;
+  unsigned int grp5_dis : 1;
+  unsigned int grp5_en  : 1;
+  unsigned int grp6_dis : 1;
+  unsigned int grp6_en  : 1;
+  unsigned int grp7_dis : 1;
+  unsigned int grp7_en  : 1;
+  unsigned int dummy1   : 16;
+} reg_iop_sw_cfg_rw_trigger_grps_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224
+
+/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int dmc0_usr : 1;
+  unsigned int out_strb : 5;
+  unsigned int in_src   : 3;
+  unsigned int in_size  : 3;
+  unsigned int in_last  : 2;
+  unsigned int in_strb  : 4;
+  unsigned int out_src  : 1;
+  unsigned int dummy1   : 13;
+} reg_iop_sw_cfg_rw_pdp0_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_pdp0_cfg 228
+#define REG_WR_ADDR_iop_sw_cfg_rw_pdp0_cfg 228
+
+/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int dmc1_usr : 1;
+  unsigned int out_strb : 5;
+  unsigned int in_src   : 3;
+  unsigned int in_size  : 3;
+  unsigned int in_last  : 2;
+  unsigned int in_strb  : 4;
+  unsigned int out_src  : 1;
+  unsigned int dummy1   : 13;
+} reg_iop_sw_cfg_rw_pdp1_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_pdp1_cfg 232
+#define REG_WR_ADDR_iop_sw_cfg_rw_pdp1_cfg 232
+
+/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+  unsigned int sdp_out0_strb : 3;
+  unsigned int sdp_out1_strb : 3;
+  unsigned int sdp_in0_data  : 3;
+  unsigned int sdp_in0_last  : 2;
+  unsigned int sdp_in0_strb  : 3;
+  unsigned int sdp_in1_data  : 3;
+  unsigned int sdp_in1_last  : 2;
+  unsigned int sdp_in1_strb  : 3;
+  unsigned int dummy1        : 10;
+} reg_iop_sw_cfg_rw_sdp_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 236
+#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 236
+
+
+/* Constants */
+enum {
+  regk_iop_sw_cfg_a                        = 0x00000001,
+  regk_iop_sw_cfg_b                        = 0x00000002,
+  regk_iop_sw_cfg_bus0                     = 0x00000000,
+  regk_iop_sw_cfg_bus0_rot16               = 0x00000004,
+  regk_iop_sw_cfg_bus0_rot24               = 0x00000006,
+  regk_iop_sw_cfg_bus0_rot8                = 0x00000002,
+  regk_iop_sw_cfg_bus1                     = 0x00000001,
+  regk_iop_sw_cfg_bus1_rot16               = 0x00000005,
+  regk_iop_sw_cfg_bus1_rot24               = 0x00000007,
+  regk_iop_sw_cfg_bus1_rot8                = 0x00000003,
+  regk_iop_sw_cfg_clk12                    = 0x00000000,
+  regk_iop_sw_cfg_cpu                      = 0x00000000,
+  regk_iop_sw_cfg_dmc0                     = 0x00000000,
+  regk_iop_sw_cfg_dmc1                     = 0x00000001,
+  regk_iop_sw_cfg_gated_clk0               = 0x00000010,
+  regk_iop_sw_cfg_gated_clk1               = 0x00000011,
+  regk_iop_sw_cfg_gated_clk2               = 0x00000012,
+  regk_iop_sw_cfg_gated_clk3               = 0x00000013,
+  regk_iop_sw_cfg_gio0                     = 0x00000004,
+  regk_iop_sw_cfg_gio1                     = 0x00000001,
+  regk_iop_sw_cfg_gio2                     = 0x00000005,
+  regk_iop_sw_cfg_gio3                     = 0x00000002,
+  regk_iop_sw_cfg_gio4                     = 0x00000006,
+  regk_iop_sw_cfg_gio5                     = 0x00000003,
+  regk_iop_sw_cfg_gio6                     = 0x00000007,
+  regk_iop_sw_cfg_gio7                     = 0x00000004,
+  regk_iop_sw_cfg_gio_in0                  = 0x00000000,
+  regk_iop_sw_cfg_gio_in1                  = 0x00000001,
+  regk_iop_sw_cfg_gio_in10                 = 0x00000002,
+  regk_iop_sw_cfg_gio_in11                 = 0x00000003,
+  regk_iop_sw_cfg_gio_in14                 = 0x00000004,
+  regk_iop_sw_cfg_gio_in15                 = 0x00000005,
+  regk_iop_sw_cfg_gio_in18                 = 0x00000002,
+  regk_iop_sw_cfg_gio_in19                 = 0x00000003,
+  regk_iop_sw_cfg_gio_in20                 = 0x00000004,
+  regk_iop_sw_cfg_gio_in21                 = 0x00000005,
+  regk_iop_sw_cfg_gio_in26                 = 0x00000006,
+  regk_iop_sw_cfg_gio_in27                 = 0x00000007,
+  regk_iop_sw_cfg_gio_in28                 = 0x00000006,
+  regk_iop_sw_cfg_gio_in29                 = 0x00000007,
+  regk_iop_sw_cfg_gio_in4                  = 0x00000000,
+  regk_iop_sw_cfg_gio_in5                  = 0x00000001,
+  regk_iop_sw_cfg_last_timer_grp0_tmr2     = 0x00000001,
+  regk_iop_sw_cfg_last_timer_grp1_tmr2     = 0x00000001,
+  regk_iop_sw_cfg_last_timer_grp2_tmr2     = 0x00000002,
+  regk_iop_sw_cfg_last_timer_grp2_tmr3     = 0x00000003,
+  regk_iop_sw_cfg_last_timer_grp3_tmr2     = 0x00000002,
+  regk_iop_sw_cfg_last_timer_grp3_tmr3     = 0x00000003,
+  regk_iop_sw_cfg_mpu                      = 0x00000001,
+  regk_iop_sw_cfg_none                     = 0x00000000,
+  regk_iop_sw_cfg_par0                     = 0x00000000,
+  regk_iop_sw_cfg_par1                     = 0x00000001,
+  regk_iop_sw_cfg_pdp_out0                 = 0x00000002,
+  regk_iop_sw_cfg_pdp_out0_hi              = 0x00000001,
+  regk_iop_sw_cfg_pdp_out0_hi_rot8         = 0x00000005,
+  regk_iop_sw_cfg_pdp_out0_lo              = 0x00000000,
+  regk_iop_sw_cfg_pdp_out0_lo_rot8         = 0x00000004,
+  regk_iop_sw_cfg_pdp_out1                 = 0x00000003,
+  regk_iop_sw_cfg_pdp_out1_hi              = 0x00000003,
+  regk_iop_sw_cfg_pdp_out1_hi_rot8         = 0x00000005,
+  regk_iop_sw_cfg_pdp_out1_lo              = 0x00000002,
+  regk_iop_sw_cfg_pdp_out1_lo_rot8         = 0x00000004,
+  regk_iop_sw_cfg_rw_bus0_mask_default     = 0x00000000,
+  regk_iop_sw_cfg_rw_bus0_oe_mask_default  = 0x00000000,
+  regk_iop_sw_cfg_rw_bus1_mask_default     = 0x00000000,
+  regk_iop_sw_cfg_rw_bus1_oe_mask_default  = 0x00000000,
+  regk_iop_sw_cfg_rw_bus_out_cfg_default   = 0x00000000,
+  regk_iop_sw_cfg_rw_crc_par0_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_crc_par1_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_dmc_in0_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_dmc_in1_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_dmc_out0_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_dmc_out1_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_fifo_in0_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_fifo_in1_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_fifo_out0_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_fifo_out1_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_gio_mask_default      = 0x00000000,
+  regk_iop_sw_cfg_rw_gio_oe_mask_default   = 0x00000000,
+  regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_pdp0_cfg_default      = 0x00000000,
+  regk_iop_sw_cfg_rw_pdp1_cfg_default      = 0x00000000,
+  regk_iop_sw_cfg_rw_pinmapping_default    = 0x55555555,
+  regk_iop_sw_cfg_rw_sap_in_owner_default  = 0x00000000,
+  regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_scrc_in0_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_scrc_in1_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_scrc_out0_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_scrc_out1_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_sdp_cfg_default       = 0x00000000,
+  regk_iop_sw_cfg_rw_spu0_cfg_default      = 0x00000000,
+  regk_iop_sw_cfg_rw_spu0_owner_default    = 0x00000000,
+  regk_iop_sw_cfg_rw_spu1_cfg_default      = 0x00000000,
+  regk_iop_sw_cfg_rw_spu1_owner_default    = 0x00000000,
+  regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_timer_grp2_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_timer_grp2_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_timer_grp3_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_rw_timer_grp3_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000,
+  regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000,
+  regk_iop_sw_cfg_sdp_out0                 = 0x00000008,
+  regk_iop_sw_cfg_sdp_out1                 = 0x00000009,
+  regk_iop_sw_cfg_size16                   = 0x00000002,
+  regk_iop_sw_cfg_size24                   = 0x00000003,
+  regk_iop_sw_cfg_size32                   = 0x00000004,
+  regk_iop_sw_cfg_size8                    = 0x00000001,
+  regk_iop_sw_cfg_spu0                     = 0x00000002,
+  regk_iop_sw_cfg_spu0_bus_out0_hi         = 0x00000006,
+  regk_iop_sw_cfg_spu0_bus_out0_lo         = 0x00000006,
+  regk_iop_sw_cfg_spu0_bus_out1_hi         = 0x00000007,
+  regk_iop_sw_cfg_spu0_bus_out1_lo         = 0x00000007,
+  regk_iop_sw_cfg_spu0_g0                  = 0x0000000e,
+  regk_iop_sw_cfg_spu0_g1                  = 0x0000000e,
+  regk_iop_sw_cfg_spu0_g2                  = 0x0000000e,
+  regk_iop_sw_cfg_spu0_g3                  = 0x0000000e,
+  regk_iop_sw_cfg_spu0_g4                  = 0x0000000e,
+  regk_iop_sw_cfg_spu0_g5                  = 0x0000000e,
+  regk_iop_sw_cfg_spu0_g6                  = 0x0000000e,
+  regk_iop_sw_cfg_spu0_g7                  = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gio0                = 0x00000000,
+  regk_iop_sw_cfg_spu0_gio1                = 0x00000001,
+  regk_iop_sw_cfg_spu0_gio2                = 0x00000000,
+  regk_iop_sw_cfg_spu0_gio5                = 0x00000005,
+  regk_iop_sw_cfg_spu0_gio6                = 0x00000006,
+  regk_iop_sw_cfg_spu0_gio7                = 0x00000007,
+  regk_iop_sw_cfg_spu0_gio_out0            = 0x00000008,
+  regk_iop_sw_cfg_spu0_gio_out1            = 0x00000009,
+  regk_iop_sw_cfg_spu0_gio_out2            = 0x0000000a,
+  regk_iop_sw_cfg_spu0_gio_out3            = 0x0000000b,
+  regk_iop_sw_cfg_spu0_gio_out4            = 0x0000000c,
+  regk_iop_sw_cfg_spu0_gio_out5            = 0x0000000d,
+  regk_iop_sw_cfg_spu0_gio_out6            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gio_out7            = 0x0000000f,
+  regk_iop_sw_cfg_spu0_gioout0             = 0x00000000,
+  regk_iop_sw_cfg_spu0_gioout1             = 0x00000000,
+  regk_iop_sw_cfg_spu0_gioout10            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout11            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout12            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout13            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout14            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout15            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout16            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout17            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout18            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout19            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout2             = 0x00000002,
+  regk_iop_sw_cfg_spu0_gioout20            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout21            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout22            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout23            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout24            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout25            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout26            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout27            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout28            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout29            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout3             = 0x00000002,
+  regk_iop_sw_cfg_spu0_gioout30            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout31            = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout4             = 0x00000004,
+  regk_iop_sw_cfg_spu0_gioout5             = 0x00000004,
+  regk_iop_sw_cfg_spu0_gioout6             = 0x00000006,
+  regk_iop_sw_cfg_spu0_gioout7             = 0x00000006,
+  regk_iop_sw_cfg_spu0_gioout8             = 0x0000000e,
+  regk_iop_sw_cfg_spu0_gioout9             = 0x0000000e,
+  regk_iop_sw_cfg_spu1                     = 0x00000003,
+  regk_iop_sw_cfg_spu1_bus_out0_hi         = 0x00000006,
+  regk_iop_sw_cfg_spu1_bus_out0_lo         = 0x00000006,
+  regk_iop_sw_cfg_spu1_bus_out1_hi         = 0x00000007,
+  regk_iop_sw_cfg_spu1_bus_out1_lo         = 0x00000007,
+  regk_iop_sw_cfg_spu1_g0                  = 0x0000000f,
+  regk_iop_sw_cfg_spu1_g1                  = 0x0000000f,
+  regk_iop_sw_cfg_spu1_g2                  = 0x0000000f,
+  regk_iop_sw_cfg_spu1_g3                  = 0x0000000f,
+  regk_iop_sw_cfg_spu1_g4                  = 0x0000000f,
+  regk_iop_sw_cfg_spu1_g5                  = 0x0000000f,
+  regk_iop_sw_cfg_spu1_g6                  = 0x0000000f,
+  regk_iop_sw_cfg_spu1_g7                  = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gio0                = 0x00000002,
+  regk_iop_sw_cfg_spu1_gio1                = 0x00000003,
+  regk_iop_sw_cfg_spu1_gio2                = 0x00000002,
+  regk_iop_sw_cfg_spu1_gio5                = 0x00000005,
+  regk_iop_sw_cfg_spu1_gio6                = 0x00000006,
+  regk_iop_sw_cfg_spu1_gio7                = 0x00000007,
+  regk_iop_sw_cfg_spu1_gio_out0            = 0x00000008,
+  regk_iop_sw_cfg_spu1_gio_out1            = 0x00000009,
+  regk_iop_sw_cfg_spu1_gio_out2            = 0x0000000a,
+  regk_iop_sw_cfg_spu1_gio_out3            = 0x0000000b,
+  regk_iop_sw_cfg_spu1_gio_out4            = 0x0000000c,
+  regk_iop_sw_cfg_spu1_gio_out5            = 0x0000000d,
+  regk_iop_sw_cfg_spu1_gio_out6            = 0x0000000e,
+  regk_iop_sw_cfg_spu1_gio_out7            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout0             = 0x00000001,
+  regk_iop_sw_cfg_spu1_gioout1             = 0x00000001,
+  regk_iop_sw_cfg_spu1_gioout10            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout11            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout12            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout13            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout14            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout15            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout16            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout17            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout18            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout19            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout2             = 0x00000003,
+  regk_iop_sw_cfg_spu1_gioout20            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout21            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout22            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout23            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout24            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout25            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout26            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout27            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout28            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout29            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout3             = 0x00000003,
+  regk_iop_sw_cfg_spu1_gioout30            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout31            = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout4             = 0x00000005,
+  regk_iop_sw_cfg_spu1_gioout5             = 0x00000005,
+  regk_iop_sw_cfg_spu1_gioout6             = 0x00000007,
+  regk_iop_sw_cfg_spu1_gioout7             = 0x00000007,
+  regk_iop_sw_cfg_spu1_gioout8             = 0x0000000f,
+  regk_iop_sw_cfg_spu1_gioout9             = 0x0000000f,
+  regk_iop_sw_cfg_strb_timer_grp0_tmr0     = 0x00000001,
+  regk_iop_sw_cfg_strb_timer_grp0_tmr1     = 0x00000002,
+  regk_iop_sw_cfg_strb_timer_grp1_tmr0     = 0x00000001,
+  regk_iop_sw_cfg_strb_timer_grp1_tmr1     = 0x00000002,
+  regk_iop_sw_cfg_strb_timer_grp2_tmr0     = 0x00000003,
+  regk_iop_sw_cfg_strb_timer_grp2_tmr1     = 0x00000002,
+  regk_iop_sw_cfg_strb_timer_grp3_tmr0     = 0x00000003,
+  regk_iop_sw_cfg_strb_timer_grp3_tmr1     = 0x00000002,
+  regk_iop_sw_cfg_timer_grp0               = 0x00000000,
+  regk_iop_sw_cfg_timer_grp0_rot           = 0x00000001,
+  regk_iop_sw_cfg_timer_grp0_strb0         = 0x0000000a,
+  regk_iop_sw_cfg_timer_grp0_strb1         = 0x0000000a,
+  regk_iop_sw_cfg_timer_grp0_strb2         = 0x0000000a,
+  regk_iop_sw_cfg_timer_grp0_strb3         = 0x0000000a,
+  regk_iop_sw_cfg_timer_grp0_tmr0          = 0x00000004,
+  regk_iop_sw_cfg_timer_grp0_tmr1          = 0x00000004,
+  regk_iop_sw_cfg_timer_grp1               = 0x00000000,
+  regk_iop_sw_cfg_timer_grp1_rot           = 0x00000001,
+  regk_iop_sw_cfg_timer_grp1_strb0         = 0x0000000b,
+  regk_iop_sw_cfg_timer_grp1_strb1         = 0x0000000b,
+  regk_iop_sw_cfg_timer_grp1_strb2         = 0x0000000b,
+  regk_iop_sw_cfg_timer_grp1_strb3         = 0x0000000b,
+  regk_iop_sw_cfg_timer_grp1_tmr0          = 0x00000005,
+  regk_iop_sw_cfg_timer_grp1_tmr1          = 0x00000005,
+  regk_iop_sw_cfg_timer_grp2               = 0x00000000,
+  regk_iop_sw_cfg_timer_grp2_rot           = 0x00000001,
+  regk_iop_sw_cfg_timer_grp2_strb0         = 0x0000000c,
+  regk_iop_sw_cfg_timer_grp2_strb1         = 0x0000000c,
+  regk_iop_sw_cfg_timer_grp2_strb2         = 0x0000000c,
+  regk_iop_sw_cfg_timer_grp2_strb3         = 0x0000000c,
+  regk_iop_sw_cfg_timer_grp2_tmr0          = 0x00000006,
+  regk_iop_sw_cfg_timer_grp2_tmr1          = 0x00000006,
+  regk_iop_sw_cfg_timer_grp3               = 0x00000000,
+  regk_iop_sw_cfg_timer_grp3_rot           = 0x00000001,
+  regk_iop_sw_cfg_timer_grp3_strb0         = 0x0000000d,
+  regk_iop_sw_cfg_timer_grp3_strb1         = 0x0000000d,
+  regk_iop_sw_cfg_timer_grp3_strb2         = 0x0000000d,
+  regk_iop_sw_cfg_timer_grp3_strb3         = 0x0000000d,
+  regk_iop_sw_cfg_timer_grp3_tmr0          = 0x00000007,
+  regk_iop_sw_cfg_timer_grp3_tmr1          = 0x00000007,
+  regk_iop_sw_cfg_trig0_0                  = 0x00000000,
+  regk_iop_sw_cfg_trig0_1                  = 0x00000000,
+  regk_iop_sw_cfg_trig0_2                  = 0x00000000,
+  regk_iop_sw_cfg_trig0_3                  = 0x00000000,
+  regk_iop_sw_cfg_trig1_0                  = 0x00000000,
+  regk_iop_sw_cfg_trig1_1                  = 0x00000000,
+  regk_iop_sw_cfg_trig1_2                  = 0x00000000,
+  regk_iop_sw_cfg_trig1_3                  = 0x00000000,
+  regk_iop_sw_cfg_trig2_0                  = 0x00000000,
+  regk_iop_sw_cfg_trig2_1                  = 0x00000000,
+  regk_iop_sw_cfg_trig2_2                  = 0x00000000,
+  regk_iop_sw_cfg_trig2_3                  = 0x00000000,
+  regk_iop_sw_cfg_trig3_0                  = 0x00000000,
+  regk_iop_sw_cfg_trig3_1                  = 0x00000000,
+  regk_iop_sw_cfg_trig3_2                  = 0x00000000,
+  regk_iop_sw_cfg_trig3_3                  = 0x00000000,
+  regk_iop_sw_cfg_trig4_0                  = 0x00000001,
+  regk_iop_sw_cfg_trig4_1                  = 0x00000001,
+  regk_iop_sw_cfg_trig4_2                  = 0x00000001,
+  regk_iop_sw_cfg_trig4_3                  = 0x00000001,
+  regk_iop_sw_cfg_trig5_0                  = 0x00000001,
+  regk_iop_sw_cfg_trig5_1                  = 0x00000001,
+  regk_iop_sw_cfg_trig5_2                  = 0x00000001,
+  regk_iop_sw_cfg_trig5_3                  = 0x00000001,
+  regk_iop_sw_cfg_trig6_0                  = 0x00000001,
+  regk_iop_sw_cfg_trig6_1                  = 0x00000001,
+  regk_iop_sw_cfg_trig6_2                  = 0x00000001,
+  regk_iop_sw_cfg_trig6_3                  = 0x00000001,
+  regk_iop_sw_cfg_trig7_0                  = 0x00000001,
+  regk_iop_sw_cfg_trig7_1                  = 0x00000001,
+  regk_iop_sw_cfg_trig7_2                  = 0x00000001,
+  regk_iop_sw_cfg_trig7_3                  = 0x00000001
+};
+#endif /* __iop_sw_cfg_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h
new file mode 100644
index 00000000000..5fed844b19e
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_cpu_defs.h
@@ -0,0 +1,853 @@
+#ifndef __iop_sw_cpu_defs_h
+#define __iop_sw_cpu_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:19 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
+ *      id: $Id: iop_sw_cpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_sw_cpu */
+
+/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int keep_owner  : 1;
+  unsigned int cmd         : 2;
+  unsigned int size        : 3;
+  unsigned int wr_spu0_mem : 1;
+  unsigned int wr_spu1_mem : 1;
+  unsigned int dummy1      : 24;
+} reg_iop_sw_cpu_rw_mc_ctrl;
+#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 0
+#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 0
+
+/* Register rw_mc_data, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_cpu_rw_mc_data;
+#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 4
+#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 4
+
+/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
+typedef unsigned int reg_iop_sw_cpu_rw_mc_addr;
+#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 8
+#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 8
+
+/* Register rs_mc_data, scope iop_sw_cpu, type rs */
+typedef unsigned int reg_iop_sw_cpu_rs_mc_data;
+#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 12
+
+/* Register r_mc_data, scope iop_sw_cpu, type r */
+typedef unsigned int reg_iop_sw_cpu_r_mc_data;
+#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 16
+
+/* Register r_mc_stat, scope iop_sw_cpu, type r */
+typedef struct {
+  unsigned int busy_cpu      : 1;
+  unsigned int busy_mpu      : 1;
+  unsigned int busy_spu0     : 1;
+  unsigned int busy_spu1     : 1;
+  unsigned int owned_by_cpu  : 1;
+  unsigned int owned_by_mpu  : 1;
+  unsigned int owned_by_spu0 : 1;
+  unsigned int owned_by_spu1 : 1;
+  unsigned int dummy1        : 24;
+} reg_iop_sw_cpu_r_mc_stat;
+#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 20
+
+/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_cpu_rw_bus0_clr_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24
+#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24
+
+/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_cpu_rw_bus0_set_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_set_mask 28
+#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_set_mask 28
+
+/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_cpu_rw_bus0_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32
+#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32
+
+/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_cpu_rw_bus0_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36
+#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36
+
+/* Register r_bus0_in, scope iop_sw_cpu, type r */
+typedef unsigned int reg_iop_sw_cpu_r_bus0_in;
+#define REG_RD_ADDR_iop_sw_cpu_r_bus0_in 40
+
+/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_cpu_rw_bus1_clr_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44
+#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44
+
+/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_cpu_rw_bus1_set_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_set_mask 48
+#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_set_mask 48
+
+/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_cpu_rw_bus1_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52
+#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52
+
+/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_cpu_rw_bus1_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56
+#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56
+
+/* Register r_bus1_in, scope iop_sw_cpu, type r */
+typedef unsigned int reg_iop_sw_cpu_r_bus1_in;
+#define REG_RD_ADDR_iop_sw_cpu_r_bus1_in 60
+
+/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_cpu_rw_gio_clr_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 64
+#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 64
+
+/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_cpu_rw_gio_set_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 68
+#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 68
+
+/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_cpu_rw_gio_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72
+#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72
+
+/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_cpu_rw_gio_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76
+#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76
+
+/* Register r_gio_in, scope iop_sw_cpu, type r */
+typedef unsigned int reg_iop_sw_cpu_r_gio_in;
+#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 80
+
+/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int mpu_0   : 1;
+  unsigned int mpu_1   : 1;
+  unsigned int mpu_2   : 1;
+  unsigned int mpu_3   : 1;
+  unsigned int mpu_4   : 1;
+  unsigned int mpu_5   : 1;
+  unsigned int mpu_6   : 1;
+  unsigned int mpu_7   : 1;
+  unsigned int mpu_8   : 1;
+  unsigned int mpu_9   : 1;
+  unsigned int mpu_10  : 1;
+  unsigned int mpu_11  : 1;
+  unsigned int mpu_12  : 1;
+  unsigned int mpu_13  : 1;
+  unsigned int mpu_14  : 1;
+  unsigned int mpu_15  : 1;
+  unsigned int spu0_0  : 1;
+  unsigned int spu0_1  : 1;
+  unsigned int spu0_2  : 1;
+  unsigned int spu0_3  : 1;
+  unsigned int spu0_4  : 1;
+  unsigned int spu0_5  : 1;
+  unsigned int spu0_6  : 1;
+  unsigned int spu0_7  : 1;
+  unsigned int spu1_8  : 1;
+  unsigned int spu1_9  : 1;
+  unsigned int spu1_10 : 1;
+  unsigned int spu1_11 : 1;
+  unsigned int spu1_12 : 1;
+  unsigned int spu1_13 : 1;
+  unsigned int spu1_14 : 1;
+  unsigned int spu1_15 : 1;
+} reg_iop_sw_cpu_rw_intr0_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 84
+#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 84
+
+/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int mpu_0   : 1;
+  unsigned int mpu_1   : 1;
+  unsigned int mpu_2   : 1;
+  unsigned int mpu_3   : 1;
+  unsigned int mpu_4   : 1;
+  unsigned int mpu_5   : 1;
+  unsigned int mpu_6   : 1;
+  unsigned int mpu_7   : 1;
+  unsigned int mpu_8   : 1;
+  unsigned int mpu_9   : 1;
+  unsigned int mpu_10  : 1;
+  unsigned int mpu_11  : 1;
+  unsigned int mpu_12  : 1;
+  unsigned int mpu_13  : 1;
+  unsigned int mpu_14  : 1;
+  unsigned int mpu_15  : 1;
+  unsigned int spu0_0  : 1;
+  unsigned int spu0_1  : 1;
+  unsigned int spu0_2  : 1;
+  unsigned int spu0_3  : 1;
+  unsigned int spu0_4  : 1;
+  unsigned int spu0_5  : 1;
+  unsigned int spu0_6  : 1;
+  unsigned int spu0_7  : 1;
+  unsigned int spu1_8  : 1;
+  unsigned int spu1_9  : 1;
+  unsigned int spu1_10 : 1;
+  unsigned int spu1_11 : 1;
+  unsigned int spu1_12 : 1;
+  unsigned int spu1_13 : 1;
+  unsigned int spu1_14 : 1;
+  unsigned int spu1_15 : 1;
+} reg_iop_sw_cpu_rw_ack_intr0;
+#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 88
+#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 88
+
+/* Register r_intr0, scope iop_sw_cpu, type r */
+typedef struct {
+  unsigned int mpu_0   : 1;
+  unsigned int mpu_1   : 1;
+  unsigned int mpu_2   : 1;
+  unsigned int mpu_3   : 1;
+  unsigned int mpu_4   : 1;
+  unsigned int mpu_5   : 1;
+  unsigned int mpu_6   : 1;
+  unsigned int mpu_7   : 1;
+  unsigned int mpu_8   : 1;
+  unsigned int mpu_9   : 1;
+  unsigned int mpu_10  : 1;
+  unsigned int mpu_11  : 1;
+  unsigned int mpu_12  : 1;
+  unsigned int mpu_13  : 1;
+  unsigned int mpu_14  : 1;
+  unsigned int mpu_15  : 1;
+  unsigned int spu0_0  : 1;
+  unsigned int spu0_1  : 1;
+  unsigned int spu0_2  : 1;
+  unsigned int spu0_3  : 1;
+  unsigned int spu0_4  : 1;
+  unsigned int spu0_5  : 1;
+  unsigned int spu0_6  : 1;
+  unsigned int spu0_7  : 1;
+  unsigned int spu1_8  : 1;
+  unsigned int spu1_9  : 1;
+  unsigned int spu1_10 : 1;
+  unsigned int spu1_11 : 1;
+  unsigned int spu1_12 : 1;
+  unsigned int spu1_13 : 1;
+  unsigned int spu1_14 : 1;
+  unsigned int spu1_15 : 1;
+} reg_iop_sw_cpu_r_intr0;
+#define REG_RD_ADDR_iop_sw_cpu_r_intr0 92
+
+/* Register r_masked_intr0, scope iop_sw_cpu, type r */
+typedef struct {
+  unsigned int mpu_0   : 1;
+  unsigned int mpu_1   : 1;
+  unsigned int mpu_2   : 1;
+  unsigned int mpu_3   : 1;
+  unsigned int mpu_4   : 1;
+  unsigned int mpu_5   : 1;
+  unsigned int mpu_6   : 1;
+  unsigned int mpu_7   : 1;
+  unsigned int mpu_8   : 1;
+  unsigned int mpu_9   : 1;
+  unsigned int mpu_10  : 1;
+  unsigned int mpu_11  : 1;
+  unsigned int mpu_12  : 1;
+  unsigned int mpu_13  : 1;
+  unsigned int mpu_14  : 1;
+  unsigned int mpu_15  : 1;
+  unsigned int spu0_0  : 1;
+  unsigned int spu0_1  : 1;
+  unsigned int spu0_2  : 1;
+  unsigned int spu0_3  : 1;
+  unsigned int spu0_4  : 1;
+  unsigned int spu0_5  : 1;
+  unsigned int spu0_6  : 1;
+  unsigned int spu0_7  : 1;
+  unsigned int spu1_8  : 1;
+  unsigned int spu1_9  : 1;
+  unsigned int spu1_10 : 1;
+  unsigned int spu1_11 : 1;
+  unsigned int spu1_12 : 1;
+  unsigned int spu1_13 : 1;
+  unsigned int spu1_14 : 1;
+  unsigned int spu1_15 : 1;
+} reg_iop_sw_cpu_r_masked_intr0;
+#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 96
+
+/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int mpu_16  : 1;
+  unsigned int mpu_17  : 1;
+  unsigned int mpu_18  : 1;
+  unsigned int mpu_19  : 1;
+  unsigned int mpu_20  : 1;
+  unsigned int mpu_21  : 1;
+  unsigned int mpu_22  : 1;
+  unsigned int mpu_23  : 1;
+  unsigned int mpu_24  : 1;
+  unsigned int mpu_25  : 1;
+  unsigned int mpu_26  : 1;
+  unsigned int mpu_27  : 1;
+  unsigned int mpu_28  : 1;
+  unsigned int mpu_29  : 1;
+  unsigned int mpu_30  : 1;
+  unsigned int mpu_31  : 1;
+  unsigned int spu0_8  : 1;
+  unsigned int spu0_9  : 1;
+  unsigned int spu0_10 : 1;
+  unsigned int spu0_11 : 1;
+  unsigned int spu0_12 : 1;
+  unsigned int spu0_13 : 1;
+  unsigned int spu0_14 : 1;
+  unsigned int spu0_15 : 1;
+  unsigned int spu1_0  : 1;
+  unsigned int spu1_1  : 1;
+  unsigned int spu1_2  : 1;
+  unsigned int spu1_3  : 1;
+  unsigned int spu1_4  : 1;
+  unsigned int spu1_5  : 1;
+  unsigned int spu1_6  : 1;
+  unsigned int spu1_7  : 1;
+} reg_iop_sw_cpu_rw_intr1_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 100
+#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 100
+
+/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int mpu_16  : 1;
+  unsigned int mpu_17  : 1;
+  unsigned int mpu_18  : 1;
+  unsigned int mpu_19  : 1;
+  unsigned int mpu_20  : 1;
+  unsigned int mpu_21  : 1;
+  unsigned int mpu_22  : 1;
+  unsigned int mpu_23  : 1;
+  unsigned int mpu_24  : 1;
+  unsigned int mpu_25  : 1;
+  unsigned int mpu_26  : 1;
+  unsigned int mpu_27  : 1;
+  unsigned int mpu_28  : 1;
+  unsigned int mpu_29  : 1;
+  unsigned int mpu_30  : 1;
+  unsigned int mpu_31  : 1;
+  unsigned int spu0_8  : 1;
+  unsigned int spu0_9  : 1;
+  unsigned int spu0_10 : 1;
+  unsigned int spu0_11 : 1;
+  unsigned int spu0_12 : 1;
+  unsigned int spu0_13 : 1;
+  unsigned int spu0_14 : 1;
+  unsigned int spu0_15 : 1;
+  unsigned int spu1_0  : 1;
+  unsigned int spu1_1  : 1;
+  unsigned int spu1_2  : 1;
+  unsigned int spu1_3  : 1;
+  unsigned int spu1_4  : 1;
+  unsigned int spu1_5  : 1;
+  unsigned int spu1_6  : 1;
+  unsigned int spu1_7  : 1;
+} reg_iop_sw_cpu_rw_ack_intr1;
+#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 104
+#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 104
+
+/* Register r_intr1, scope iop_sw_cpu, type r */
+typedef struct {
+  unsigned int mpu_16  : 1;
+  unsigned int mpu_17  : 1;
+  unsigned int mpu_18  : 1;
+  unsigned int mpu_19  : 1;
+  unsigned int mpu_20  : 1;
+  unsigned int mpu_21  : 1;
+  unsigned int mpu_22  : 1;
+  unsigned int mpu_23  : 1;
+  unsigned int mpu_24  : 1;
+  unsigned int mpu_25  : 1;
+  unsigned int mpu_26  : 1;
+  unsigned int mpu_27  : 1;
+  unsigned int mpu_28  : 1;
+  unsigned int mpu_29  : 1;
+  unsigned int mpu_30  : 1;
+  unsigned int mpu_31  : 1;
+  unsigned int spu0_8  : 1;
+  unsigned int spu0_9  : 1;
+  unsigned int spu0_10 : 1;
+  unsigned int spu0_11 : 1;
+  unsigned int spu0_12 : 1;
+  unsigned int spu0_13 : 1;
+  unsigned int spu0_14 : 1;
+  unsigned int spu0_15 : 1;
+  unsigned int spu1_0  : 1;
+  unsigned int spu1_1  : 1;
+  unsigned int spu1_2  : 1;
+  unsigned int spu1_3  : 1;
+  unsigned int spu1_4  : 1;
+  unsigned int spu1_5  : 1;
+  unsigned int spu1_6  : 1;
+  unsigned int spu1_7  : 1;
+} reg_iop_sw_cpu_r_intr1;
+#define REG_RD_ADDR_iop_sw_cpu_r_intr1 108
+
+/* Register r_masked_intr1, scope iop_sw_cpu, type r */
+typedef struct {
+  unsigned int mpu_16  : 1;
+  unsigned int mpu_17  : 1;
+  unsigned int mpu_18  : 1;
+  unsigned int mpu_19  : 1;
+  unsigned int mpu_20  : 1;
+  unsigned int mpu_21  : 1;
+  unsigned int mpu_22  : 1;
+  unsigned int mpu_23  : 1;
+  unsigned int mpu_24  : 1;
+  unsigned int mpu_25  : 1;
+  unsigned int mpu_26  : 1;
+  unsigned int mpu_27  : 1;
+  unsigned int mpu_28  : 1;
+  unsigned int mpu_29  : 1;
+  unsigned int mpu_30  : 1;
+  unsigned int mpu_31  : 1;
+  unsigned int spu0_8  : 1;
+  unsigned int spu0_9  : 1;
+  unsigned int spu0_10 : 1;
+  unsigned int spu0_11 : 1;
+  unsigned int spu0_12 : 1;
+  unsigned int spu0_13 : 1;
+  unsigned int spu0_14 : 1;
+  unsigned int spu0_15 : 1;
+  unsigned int spu1_0  : 1;
+  unsigned int spu1_1  : 1;
+  unsigned int spu1_2  : 1;
+  unsigned int spu1_3  : 1;
+  unsigned int spu1_4  : 1;
+  unsigned int spu1_5  : 1;
+  unsigned int spu1_6  : 1;
+  unsigned int spu1_7  : 1;
+} reg_iop_sw_cpu_r_masked_intr1;
+#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 112
+
+/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int mpu_0           : 1;
+  unsigned int mpu_1           : 1;
+  unsigned int mpu_2           : 1;
+  unsigned int mpu_3           : 1;
+  unsigned int mpu_4           : 1;
+  unsigned int mpu_5           : 1;
+  unsigned int mpu_6           : 1;
+  unsigned int mpu_7           : 1;
+  unsigned int spu0_0          : 1;
+  unsigned int spu0_1          : 1;
+  unsigned int spu0_2          : 1;
+  unsigned int spu0_3          : 1;
+  unsigned int spu0_4          : 1;
+  unsigned int spu0_5          : 1;
+  unsigned int spu0_6          : 1;
+  unsigned int spu0_7          : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int timer_grp1      : 1;
+} reg_iop_sw_cpu_rw_intr2_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_intr2_mask 116
+#define REG_WR_ADDR_iop_sw_cpu_rw_intr2_mask 116
+
+/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int mpu_0  : 1;
+  unsigned int mpu_1  : 1;
+  unsigned int mpu_2  : 1;
+  unsigned int mpu_3  : 1;
+  unsigned int mpu_4  : 1;
+  unsigned int mpu_5  : 1;
+  unsigned int mpu_6  : 1;
+  unsigned int mpu_7  : 1;
+  unsigned int spu0_0 : 1;
+  unsigned int spu0_1 : 1;
+  unsigned int spu0_2 : 1;
+  unsigned int spu0_3 : 1;
+  unsigned int spu0_4 : 1;
+  unsigned int spu0_5 : 1;
+  unsigned int spu0_6 : 1;
+  unsigned int spu0_7 : 1;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_cpu_rw_ack_intr2;
+#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr2 120
+#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr2 120
+
+/* Register r_intr2, scope iop_sw_cpu, type r */
+typedef struct {
+  unsigned int mpu_0           : 1;
+  unsigned int mpu_1           : 1;
+  unsigned int mpu_2           : 1;
+  unsigned int mpu_3           : 1;
+  unsigned int mpu_4           : 1;
+  unsigned int mpu_5           : 1;
+  unsigned int mpu_6           : 1;
+  unsigned int mpu_7           : 1;
+  unsigned int spu0_0          : 1;
+  unsigned int spu0_1          : 1;
+  unsigned int spu0_2          : 1;
+  unsigned int spu0_3          : 1;
+  unsigned int spu0_4          : 1;
+  unsigned int spu0_5          : 1;
+  unsigned int spu0_6          : 1;
+  unsigned int spu0_7          : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int timer_grp1      : 1;
+} reg_iop_sw_cpu_r_intr2;
+#define REG_RD_ADDR_iop_sw_cpu_r_intr2 124
+
+/* Register r_masked_intr2, scope iop_sw_cpu, type r */
+typedef struct {
+  unsigned int mpu_0           : 1;
+  unsigned int mpu_1           : 1;
+  unsigned int mpu_2           : 1;
+  unsigned int mpu_3           : 1;
+  unsigned int mpu_4           : 1;
+  unsigned int mpu_5           : 1;
+  unsigned int mpu_6           : 1;
+  unsigned int mpu_7           : 1;
+  unsigned int spu0_0          : 1;
+  unsigned int spu0_1          : 1;
+  unsigned int spu0_2          : 1;
+  unsigned int spu0_3          : 1;
+  unsigned int spu0_4          : 1;
+  unsigned int spu0_5          : 1;
+  unsigned int spu0_6          : 1;
+  unsigned int spu0_7          : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int timer_grp1      : 1;
+} reg_iop_sw_cpu_r_masked_intr2;
+#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr2 128
+
+/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int mpu_16          : 1;
+  unsigned int mpu_17          : 1;
+  unsigned int mpu_18          : 1;
+  unsigned int mpu_19          : 1;
+  unsigned int mpu_20          : 1;
+  unsigned int mpu_21          : 1;
+  unsigned int mpu_22          : 1;
+  unsigned int mpu_23          : 1;
+  unsigned int spu1_0          : 1;
+  unsigned int spu1_1          : 1;
+  unsigned int spu1_2          : 1;
+  unsigned int spu1_3          : 1;
+  unsigned int spu1_4          : 1;
+  unsigned int spu1_5          : 1;
+  unsigned int spu1_6          : 1;
+  unsigned int spu1_7          : 1;
+  unsigned int dmc_in1         : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int timer_grp3      : 1;
+} reg_iop_sw_cpu_rw_intr3_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_intr3_mask 132
+#define REG_WR_ADDR_iop_sw_cpu_rw_intr3_mask 132
+
+/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */
+typedef struct {
+  unsigned int mpu_16 : 1;
+  unsigned int mpu_17 : 1;
+  unsigned int mpu_18 : 1;
+  unsigned int mpu_19 : 1;
+  unsigned int mpu_20 : 1;
+  unsigned int mpu_21 : 1;
+  unsigned int mpu_22 : 1;
+  unsigned int mpu_23 : 1;
+  unsigned int spu1_0 : 1;
+  unsigned int spu1_1 : 1;
+  unsigned int spu1_2 : 1;
+  unsigned int spu1_3 : 1;
+  unsigned int spu1_4 : 1;
+  unsigned int spu1_5 : 1;
+  unsigned int spu1_6 : 1;
+  unsigned int spu1_7 : 1;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_cpu_rw_ack_intr3;
+#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr3 136
+#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr3 136
+
+/* Register r_intr3, scope iop_sw_cpu, type r */
+typedef struct {
+  unsigned int mpu_16          : 1;
+  unsigned int mpu_17          : 1;
+  unsigned int mpu_18          : 1;
+  unsigned int mpu_19          : 1;
+  unsigned int mpu_20          : 1;
+  unsigned int mpu_21          : 1;
+  unsigned int mpu_22          : 1;
+  unsigned int mpu_23          : 1;
+  unsigned int spu1_0          : 1;
+  unsigned int spu1_1          : 1;
+  unsigned int spu1_2          : 1;
+  unsigned int spu1_3          : 1;
+  unsigned int spu1_4          : 1;
+  unsigned int spu1_5          : 1;
+  unsigned int spu1_6          : 1;
+  unsigned int spu1_7          : 1;
+  unsigned int dmc_in1         : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int timer_grp3      : 1;
+} reg_iop_sw_cpu_r_intr3;
+#define REG_RD_ADDR_iop_sw_cpu_r_intr3 140
+
+/* Register r_masked_intr3, scope iop_sw_cpu, type r */
+typedef struct {
+  unsigned int mpu_16          : 1;
+  unsigned int mpu_17          : 1;
+  unsigned int mpu_18          : 1;
+  unsigned int mpu_19          : 1;
+  unsigned int mpu_20          : 1;
+  unsigned int mpu_21          : 1;
+  unsigned int mpu_22          : 1;
+  unsigned int mpu_23          : 1;
+  unsigned int spu1_0          : 1;
+  unsigned int spu1_1          : 1;
+  unsigned int spu1_2          : 1;
+  unsigned int spu1_3          : 1;
+  unsigned int spu1_4          : 1;
+  unsigned int spu1_5          : 1;
+  unsigned int spu1_6          : 1;
+  unsigned int spu1_7          : 1;
+  unsigned int dmc_in1         : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int timer_grp3      : 1;
+} reg_iop_sw_cpu_r_masked_intr3;
+#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr3 144
+
+
+/* Constants */
+enum {
+  regk_iop_sw_cpu_copy                     = 0x00000000,
+  regk_iop_sw_cpu_no                       = 0x00000000,
+  regk_iop_sw_cpu_rd                       = 0x00000002,
+  regk_iop_sw_cpu_reg_copy                 = 0x00000001,
+  regk_iop_sw_cpu_rw_bus0_clr_mask_default = 0x00000000,
+  regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default = 0x00000000,
+  regk_iop_sw_cpu_rw_bus0_oe_set_mask_default = 0x00000000,
+  regk_iop_sw_cpu_rw_bus0_set_mask_default = 0x00000000,
+  regk_iop_sw_cpu_rw_bus1_clr_mask_default = 0x00000000,
+  regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default = 0x00000000,
+  regk_iop_sw_cpu_rw_bus1_oe_set_mask_default = 0x00000000,
+  regk_iop_sw_cpu_rw_bus1_set_mask_default = 0x00000000,
+  regk_iop_sw_cpu_rw_gio_clr_mask_default  = 0x00000000,
+  regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000,
+  regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000,
+  regk_iop_sw_cpu_rw_gio_set_mask_default  = 0x00000000,
+  regk_iop_sw_cpu_rw_intr0_mask_default    = 0x00000000,
+  regk_iop_sw_cpu_rw_intr1_mask_default    = 0x00000000,
+  regk_iop_sw_cpu_rw_intr2_mask_default    = 0x00000000,
+  regk_iop_sw_cpu_rw_intr3_mask_default    = 0x00000000,
+  regk_iop_sw_cpu_wr                       = 0x00000003,
+  regk_iop_sw_cpu_yes                      = 0x00000001
+};
+#endif /* __iop_sw_cpu_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h
new file mode 100644
index 00000000000..da718f2a8ca
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_mpu_defs.h
@@ -0,0 +1,893 @@
+#ifndef __iop_sw_mpu_defs_h
+#define __iop_sw_mpu_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:19 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_mpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
+ *      id: $Id: iop_sw_mpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_sw_mpu */
+
+/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int cfg : 2;
+  unsigned int dummy1 : 30;
+} reg_iop_sw_mpu_rw_sw_cfg_owner;
+#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
+#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
+
+/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int keep_owner  : 1;
+  unsigned int cmd         : 2;
+  unsigned int size        : 3;
+  unsigned int wr_spu0_mem : 1;
+  unsigned int wr_spu1_mem : 1;
+  unsigned int dummy1      : 24;
+} reg_iop_sw_mpu_rw_mc_ctrl;
+#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 4
+#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 4
+
+/* Register rw_mc_data, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_mpu_rw_mc_data;
+#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 8
+#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 8
+
+/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
+typedef unsigned int reg_iop_sw_mpu_rw_mc_addr;
+#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 12
+#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 12
+
+/* Register rs_mc_data, scope iop_sw_mpu, type rs */
+typedef unsigned int reg_iop_sw_mpu_rs_mc_data;
+#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 16
+
+/* Register r_mc_data, scope iop_sw_mpu, type r */
+typedef unsigned int reg_iop_sw_mpu_r_mc_data;
+#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 20
+
+/* Register r_mc_stat, scope iop_sw_mpu, type r */
+typedef struct {
+  unsigned int busy_cpu      : 1;
+  unsigned int busy_mpu      : 1;
+  unsigned int busy_spu0     : 1;
+  unsigned int busy_spu1     : 1;
+  unsigned int owned_by_cpu  : 1;
+  unsigned int owned_by_mpu  : 1;
+  unsigned int owned_by_spu0 : 1;
+  unsigned int owned_by_spu1 : 1;
+  unsigned int dummy1        : 24;
+} reg_iop_sw_mpu_r_mc_stat;
+#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 24
+
+/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_mpu_rw_bus0_clr_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28
+#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28
+
+/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_mpu_rw_bus0_set_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_set_mask 32
+#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_set_mask 32
+
+/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_mpu_rw_bus0_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36
+#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36
+
+/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_mpu_rw_bus0_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40
+#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40
+
+/* Register r_bus0_in, scope iop_sw_mpu, type r */
+typedef unsigned int reg_iop_sw_mpu_r_bus0_in;
+#define REG_RD_ADDR_iop_sw_mpu_r_bus0_in 44
+
+/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_mpu_rw_bus1_clr_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48
+#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48
+
+/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_mpu_rw_bus1_set_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_set_mask 52
+#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_set_mask 52
+
+/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_mpu_rw_bus1_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56
+#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56
+
+/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_mpu_rw_bus1_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60
+#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60
+
+/* Register r_bus1_in, scope iop_sw_mpu, type r */
+typedef unsigned int reg_iop_sw_mpu_r_bus1_in;
+#define REG_RD_ADDR_iop_sw_mpu_r_bus1_in 64
+
+/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_mpu_rw_gio_clr_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 68
+#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 68
+
+/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_mpu_rw_gio_set_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 72
+#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 72
+
+/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_mpu_rw_gio_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76
+#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76
+
+/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_mpu_rw_gio_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80
+#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80
+
+/* Register r_gio_in, scope iop_sw_mpu, type r */
+typedef unsigned int reg_iop_sw_mpu_r_gio_in;
+#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 84
+
+/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int intr0  : 1;
+  unsigned int intr1  : 1;
+  unsigned int intr2  : 1;
+  unsigned int intr3  : 1;
+  unsigned int intr4  : 1;
+  unsigned int intr5  : 1;
+  unsigned int intr6  : 1;
+  unsigned int intr7  : 1;
+  unsigned int intr8  : 1;
+  unsigned int intr9  : 1;
+  unsigned int intr10 : 1;
+  unsigned int intr11 : 1;
+  unsigned int intr12 : 1;
+  unsigned int intr13 : 1;
+  unsigned int intr14 : 1;
+  unsigned int intr15 : 1;
+  unsigned int intr16 : 1;
+  unsigned int intr17 : 1;
+  unsigned int intr18 : 1;
+  unsigned int intr19 : 1;
+  unsigned int intr20 : 1;
+  unsigned int intr21 : 1;
+  unsigned int intr22 : 1;
+  unsigned int intr23 : 1;
+  unsigned int intr24 : 1;
+  unsigned int intr25 : 1;
+  unsigned int intr26 : 1;
+  unsigned int intr27 : 1;
+  unsigned int intr28 : 1;
+  unsigned int intr29 : 1;
+  unsigned int intr30 : 1;
+  unsigned int intr31 : 1;
+} reg_iop_sw_mpu_rw_cpu_intr;
+#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 88
+#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 88
+
+/* Register r_cpu_intr, scope iop_sw_mpu, type r */
+typedef struct {
+  unsigned int intr0  : 1;
+  unsigned int intr1  : 1;
+  unsigned int intr2  : 1;
+  unsigned int intr3  : 1;
+  unsigned int intr4  : 1;
+  unsigned int intr5  : 1;
+  unsigned int intr6  : 1;
+  unsigned int intr7  : 1;
+  unsigned int intr8  : 1;
+  unsigned int intr9  : 1;
+  unsigned int intr10 : 1;
+  unsigned int intr11 : 1;
+  unsigned int intr12 : 1;
+  unsigned int intr13 : 1;
+  unsigned int intr14 : 1;
+  unsigned int intr15 : 1;
+  unsigned int intr16 : 1;
+  unsigned int intr17 : 1;
+  unsigned int intr18 : 1;
+  unsigned int intr19 : 1;
+  unsigned int intr20 : 1;
+  unsigned int intr21 : 1;
+  unsigned int intr22 : 1;
+  unsigned int intr23 : 1;
+  unsigned int intr24 : 1;
+  unsigned int intr25 : 1;
+  unsigned int intr26 : 1;
+  unsigned int intr27 : 1;
+  unsigned int intr28 : 1;
+  unsigned int intr29 : 1;
+  unsigned int intr30 : 1;
+  unsigned int intr31 : 1;
+} reg_iop_sw_mpu_r_cpu_intr;
+#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 92
+
+/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int spu0_intr0      : 1;
+  unsigned int spu1_intr0      : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr1      : 1;
+  unsigned int spu1_intr1      : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr2      : 1;
+  unsigned int spu1_intr2      : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr3      : 1;
+  unsigned int spu1_intr3      : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_rw_intr_grp0_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96
+#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96
+
+/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int spu0_intr0 : 1;
+  unsigned int spu1_intr0 : 1;
+  unsigned int dummy1     : 6;
+  unsigned int spu0_intr1 : 1;
+  unsigned int spu1_intr1 : 1;
+  unsigned int dummy2     : 6;
+  unsigned int spu0_intr2 : 1;
+  unsigned int spu1_intr2 : 1;
+  unsigned int dummy3     : 6;
+  unsigned int spu0_intr3 : 1;
+  unsigned int spu1_intr3 : 1;
+  unsigned int dummy4     : 6;
+} reg_iop_sw_mpu_rw_ack_intr_grp0;
+#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100
+#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100
+
+/* Register r_intr_grp0, scope iop_sw_mpu, type r */
+typedef struct {
+  unsigned int spu0_intr0      : 1;
+  unsigned int spu1_intr0      : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr1      : 1;
+  unsigned int spu1_intr1      : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr2      : 1;
+  unsigned int spu1_intr2      : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr3      : 1;
+  unsigned int spu1_intr3      : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_r_intr_grp0;
+#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 104
+
+/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
+typedef struct {
+  unsigned int spu0_intr0      : 1;
+  unsigned int spu1_intr0      : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr1      : 1;
+  unsigned int spu1_intr1      : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr2      : 1;
+  unsigned int spu1_intr2      : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr3      : 1;
+  unsigned int spu1_intr3      : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_r_masked_intr_grp0;
+#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 108
+
+/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int spu0_intr4      : 1;
+  unsigned int spu1_intr4      : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr5      : 1;
+  unsigned int spu1_intr5      : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr6      : 1;
+  unsigned int spu1_intr6      : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr7      : 1;
+  unsigned int spu1_intr7      : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_rw_intr_grp1_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112
+#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112
+
+/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int spu0_intr4 : 1;
+  unsigned int spu1_intr4 : 1;
+  unsigned int dummy1     : 6;
+  unsigned int spu0_intr5 : 1;
+  unsigned int spu1_intr5 : 1;
+  unsigned int dummy2     : 6;
+  unsigned int spu0_intr6 : 1;
+  unsigned int spu1_intr6 : 1;
+  unsigned int dummy3     : 6;
+  unsigned int spu0_intr7 : 1;
+  unsigned int spu1_intr7 : 1;
+  unsigned int dummy4     : 6;
+} reg_iop_sw_mpu_rw_ack_intr_grp1;
+#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116
+#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116
+
+/* Register r_intr_grp1, scope iop_sw_mpu, type r */
+typedef struct {
+  unsigned int spu0_intr4      : 1;
+  unsigned int spu1_intr4      : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr5      : 1;
+  unsigned int spu1_intr5      : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr6      : 1;
+  unsigned int spu1_intr6      : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr7      : 1;
+  unsigned int spu1_intr7      : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_r_intr_grp1;
+#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 120
+
+/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
+typedef struct {
+  unsigned int spu0_intr4      : 1;
+  unsigned int spu1_intr4      : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr5      : 1;
+  unsigned int spu1_intr5      : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr6      : 1;
+  unsigned int spu1_intr6      : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr7      : 1;
+  unsigned int spu1_intr7      : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_r_masked_intr_grp1;
+#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 124
+
+/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int spu0_intr8      : 1;
+  unsigned int spu1_intr8      : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr9      : 1;
+  unsigned int spu1_intr9      : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr10     : 1;
+  unsigned int spu1_intr10     : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr11     : 1;
+  unsigned int spu1_intr11     : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_rw_intr_grp2_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128
+#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128
+
+/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int spu0_intr8  : 1;
+  unsigned int spu1_intr8  : 1;
+  unsigned int dummy1      : 6;
+  unsigned int spu0_intr9  : 1;
+  unsigned int spu1_intr9  : 1;
+  unsigned int dummy2      : 6;
+  unsigned int spu0_intr10 : 1;
+  unsigned int spu1_intr10 : 1;
+  unsigned int dummy3      : 6;
+  unsigned int spu0_intr11 : 1;
+  unsigned int spu1_intr11 : 1;
+  unsigned int dummy4      : 6;
+} reg_iop_sw_mpu_rw_ack_intr_grp2;
+#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132
+#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132
+
+/* Register r_intr_grp2, scope iop_sw_mpu, type r */
+typedef struct {
+  unsigned int spu0_intr8      : 1;
+  unsigned int spu1_intr8      : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr9      : 1;
+  unsigned int spu1_intr9      : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr10     : 1;
+  unsigned int spu1_intr10     : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr11     : 1;
+  unsigned int spu1_intr11     : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_r_intr_grp2;
+#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 136
+
+/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
+typedef struct {
+  unsigned int spu0_intr8      : 1;
+  unsigned int spu1_intr8      : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr9      : 1;
+  unsigned int spu1_intr9      : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr10     : 1;
+  unsigned int spu1_intr10     : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr11     : 1;
+  unsigned int spu1_intr11     : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_r_masked_intr_grp2;
+#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 140
+
+/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int spu0_intr12     : 1;
+  unsigned int spu1_intr12     : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr13     : 1;
+  unsigned int spu1_intr13     : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr14     : 1;
+  unsigned int spu1_intr14     : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr15     : 1;
+  unsigned int spu1_intr15     : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_rw_intr_grp3_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144
+#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144
+
+/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
+typedef struct {
+  unsigned int spu0_intr12 : 1;
+  unsigned int spu1_intr12 : 1;
+  unsigned int dummy1      : 6;
+  unsigned int spu0_intr13 : 1;
+  unsigned int spu1_intr13 : 1;
+  unsigned int dummy2      : 6;
+  unsigned int spu0_intr14 : 1;
+  unsigned int spu1_intr14 : 1;
+  unsigned int dummy3      : 6;
+  unsigned int spu0_intr15 : 1;
+  unsigned int spu1_intr15 : 1;
+  unsigned int dummy4      : 6;
+} reg_iop_sw_mpu_rw_ack_intr_grp3;
+#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148
+#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148
+
+/* Register r_intr_grp3, scope iop_sw_mpu, type r */
+typedef struct {
+  unsigned int spu0_intr12     : 1;
+  unsigned int spu1_intr12     : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr13     : 1;
+  unsigned int spu1_intr13     : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr14     : 1;
+  unsigned int spu1_intr14     : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr15     : 1;
+  unsigned int spu1_intr15     : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_r_intr_grp3;
+#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 152
+
+/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
+typedef struct {
+  unsigned int spu0_intr12     : 1;
+  unsigned int spu1_intr12     : 1;
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int spu0_intr13     : 1;
+  unsigned int spu1_intr13     : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int spu0_intr14     : 1;
+  unsigned int spu1_intr14     : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int spu0_intr15     : 1;
+  unsigned int spu1_intr15     : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int dmc_in1         : 1;
+} reg_iop_sw_mpu_r_masked_intr_grp3;
+#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 156
+
+
+/* Constants */
+enum {
+  regk_iop_sw_mpu_copy                     = 0x00000000,
+  regk_iop_sw_mpu_cpu                      = 0x00000000,
+  regk_iop_sw_mpu_mpu                      = 0x00000001,
+  regk_iop_sw_mpu_no                       = 0x00000000,
+  regk_iop_sw_mpu_nop                      = 0x00000000,
+  regk_iop_sw_mpu_rd                       = 0x00000002,
+  regk_iop_sw_mpu_reg_copy                 = 0x00000001,
+  regk_iop_sw_mpu_rw_bus0_clr_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_bus0_oe_set_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_bus0_set_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_bus1_clr_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_bus1_oe_set_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_bus1_set_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_gio_clr_mask_default  = 0x00000000,
+  regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_gio_set_mask_default  = 0x00000000,
+  regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000,
+  regk_iop_sw_mpu_rw_sw_cfg_owner_default  = 0x00000000,
+  regk_iop_sw_mpu_set                      = 0x00000001,
+  regk_iop_sw_mpu_spu0                     = 0x00000002,
+  regk_iop_sw_mpu_spu1                     = 0x00000003,
+  regk_iop_sw_mpu_wr                       = 0x00000003,
+  regk_iop_sw_mpu_yes                      = 0x00000001
+};
+#endif /* __iop_sw_mpu_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h
new file mode 100644
index 00000000000..b59dde4bd0d
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_sw_spu_defs.h
@@ -0,0 +1,552 @@
+#ifndef __iop_sw_spu_defs_h
+#define __iop_sw_spu_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:10:19 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_spu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
+ *      id: $Id: iop_sw_spu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_sw_spu */
+
+/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int keep_owner  : 1;
+  unsigned int cmd         : 2;
+  unsigned int size        : 3;
+  unsigned int wr_spu0_mem : 1;
+  unsigned int wr_spu1_mem : 1;
+  unsigned int dummy1      : 24;
+} reg_iop_sw_spu_rw_mc_ctrl;
+#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 0
+#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 0
+
+/* Register rw_mc_data, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_spu_rw_mc_data;
+#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 4
+#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 4
+
+/* Register rw_mc_addr, scope iop_sw_spu, type rw */
+typedef unsigned int reg_iop_sw_spu_rw_mc_addr;
+#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 8
+#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 8
+
+/* Register rs_mc_data, scope iop_sw_spu, type rs */
+typedef unsigned int reg_iop_sw_spu_rs_mc_data;
+#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 12
+
+/* Register r_mc_data, scope iop_sw_spu, type r */
+typedef unsigned int reg_iop_sw_spu_r_mc_data;
+#define REG_RD_ADDR_iop_sw_spu_r_mc_data 16
+
+/* Register r_mc_stat, scope iop_sw_spu, type r */
+typedef struct {
+  unsigned int busy_cpu      : 1;
+  unsigned int busy_mpu      : 1;
+  unsigned int busy_spu0     : 1;
+  unsigned int busy_spu1     : 1;
+  unsigned int owned_by_cpu  : 1;
+  unsigned int owned_by_mpu  : 1;
+  unsigned int owned_by_spu0 : 1;
+  unsigned int owned_by_spu1 : 1;
+  unsigned int dummy1        : 24;
+} reg_iop_sw_spu_r_mc_stat;
+#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 20
+
+/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_spu_rw_bus0_clr_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask 24
+#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask 24
+
+/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_spu_rw_bus0_set_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask 28
+#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask 28
+
+/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_spu_rw_bus0_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32
+#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32
+
+/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_spu_rw_bus0_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36
+#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36
+
+/* Register r_bus0_in, scope iop_sw_spu, type r */
+typedef unsigned int reg_iop_sw_spu_r_bus0_in;
+#define REG_RD_ADDR_iop_sw_spu_r_bus0_in 40
+
+/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_spu_rw_bus1_clr_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask 44
+#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask 44
+
+/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+} reg_iop_sw_spu_rw_bus1_set_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask 48
+#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask 48
+
+/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_spu_rw_bus1_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52
+#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52
+
+/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 1;
+  unsigned int byte1 : 1;
+  unsigned int byte2 : 1;
+  unsigned int byte3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_sw_spu_rw_bus1_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56
+#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56
+
+/* Register r_bus1_in, scope iop_sw_spu, type r */
+typedef unsigned int reg_iop_sw_spu_r_bus1_in;
+#define REG_RD_ADDR_iop_sw_spu_r_bus1_in 60
+
+/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_spu_rw_gio_clr_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 64
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 64
+
+/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_spu_rw_gio_set_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 68
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 68
+
+/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_spu_rw_gio_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72
+
+/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 32;
+} reg_iop_sw_spu_rw_gio_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76
+
+/* Register r_gio_in, scope iop_sw_spu, type r */
+typedef unsigned int reg_iop_sw_spu_r_gio_in;
+#define REG_RD_ADDR_iop_sw_spu_r_gio_in 80
+
+/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_bus0_clr_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84
+#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84
+
+/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_bus0_clr_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88
+#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88
+
+/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_bus0_set_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92
+#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92
+
+/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_bus0_set_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96
+#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96
+
+/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_bus1_clr_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100
+#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100
+
+/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_bus1_clr_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104
+#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104
+
+/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte0 : 8;
+  unsigned int byte1 : 8;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_bus1_set_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108
+#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108
+
+/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int byte2 : 8;
+  unsigned int byte3 : 8;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_bus1_set_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112
+#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112
+
+/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_clr_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116
+
+/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_clr_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120
+
+/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_set_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124
+
+/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_set_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128
+
+/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132
+
+/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136
+
+/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_oe_set_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140
+
+/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_oe_set_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144
+
+/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int intr0  : 1;
+  unsigned int intr1  : 1;
+  unsigned int intr2  : 1;
+  unsigned int intr3  : 1;
+  unsigned int intr4  : 1;
+  unsigned int intr5  : 1;
+  unsigned int intr6  : 1;
+  unsigned int intr7  : 1;
+  unsigned int intr8  : 1;
+  unsigned int intr9  : 1;
+  unsigned int intr10 : 1;
+  unsigned int intr11 : 1;
+  unsigned int intr12 : 1;
+  unsigned int intr13 : 1;
+  unsigned int intr14 : 1;
+  unsigned int intr15 : 1;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_cpu_intr;
+#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 148
+#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 148
+
+/* Register r_cpu_intr, scope iop_sw_spu, type r */
+typedef struct {
+  unsigned int intr0  : 1;
+  unsigned int intr1  : 1;
+  unsigned int intr2  : 1;
+  unsigned int intr3  : 1;
+  unsigned int intr4  : 1;
+  unsigned int intr5  : 1;
+  unsigned int intr6  : 1;
+  unsigned int intr7  : 1;
+  unsigned int intr8  : 1;
+  unsigned int intr9  : 1;
+  unsigned int intr10 : 1;
+  unsigned int intr11 : 1;
+  unsigned int intr12 : 1;
+  unsigned int intr13 : 1;
+  unsigned int intr14 : 1;
+  unsigned int intr15 : 1;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_r_cpu_intr;
+#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 152
+
+/* Register r_hw_intr, scope iop_sw_spu, type r */
+typedef struct {
+  unsigned int trigger_grp0    : 1;
+  unsigned int trigger_grp1    : 1;
+  unsigned int trigger_grp2    : 1;
+  unsigned int trigger_grp3    : 1;
+  unsigned int trigger_grp4    : 1;
+  unsigned int trigger_grp5    : 1;
+  unsigned int trigger_grp6    : 1;
+  unsigned int trigger_grp7    : 1;
+  unsigned int timer_grp0      : 1;
+  unsigned int timer_grp1      : 1;
+  unsigned int timer_grp2      : 1;
+  unsigned int timer_grp3      : 1;
+  unsigned int fifo_out0       : 1;
+  unsigned int fifo_out0_extra : 1;
+  unsigned int fifo_in0        : 1;
+  unsigned int fifo_in0_extra  : 1;
+  unsigned int fifo_out1       : 1;
+  unsigned int fifo_out1_extra : 1;
+  unsigned int fifo_in1        : 1;
+  unsigned int fifo_in1_extra  : 1;
+  unsigned int dmc_out0        : 1;
+  unsigned int dmc_in0         : 1;
+  unsigned int dmc_out1        : 1;
+  unsigned int dmc_in1         : 1;
+  unsigned int dummy1          : 8;
+} reg_iop_sw_spu_r_hw_intr;
+#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 156
+
+/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
+typedef struct {
+  unsigned int intr0  : 1;
+  unsigned int intr1  : 1;
+  unsigned int intr2  : 1;
+  unsigned int intr3  : 1;
+  unsigned int intr4  : 1;
+  unsigned int intr5  : 1;
+  unsigned int intr6  : 1;
+  unsigned int intr7  : 1;
+  unsigned int intr8  : 1;
+  unsigned int intr9  : 1;
+  unsigned int intr10 : 1;
+  unsigned int intr11 : 1;
+  unsigned int intr12 : 1;
+  unsigned int intr13 : 1;
+  unsigned int intr14 : 1;
+  unsigned int intr15 : 1;
+  unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_mpu_intr;
+#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 160
+#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 160
+
+/* Register r_mpu_intr, scope iop_sw_spu, type r */
+typedef struct {
+  unsigned int intr0            : 1;
+  unsigned int intr1            : 1;
+  unsigned int intr2            : 1;
+  unsigned int intr3            : 1;
+  unsigned int intr4            : 1;
+  unsigned int intr5            : 1;
+  unsigned int intr6            : 1;
+  unsigned int intr7            : 1;
+  unsigned int intr8            : 1;
+  unsigned int intr9            : 1;
+  unsigned int intr10           : 1;
+  unsigned int intr11           : 1;
+  unsigned int intr12           : 1;
+  unsigned int intr13           : 1;
+  unsigned int intr14           : 1;
+  unsigned int intr15           : 1;
+  unsigned int other_spu_intr0  : 1;
+  unsigned int other_spu_intr1  : 1;
+  unsigned int other_spu_intr2  : 1;
+  unsigned int other_spu_intr3  : 1;
+  unsigned int other_spu_intr4  : 1;
+  unsigned int other_spu_intr5  : 1;
+  unsigned int other_spu_intr6  : 1;
+  unsigned int other_spu_intr7  : 1;
+  unsigned int other_spu_intr8  : 1;
+  unsigned int other_spu_intr9  : 1;
+  unsigned int other_spu_intr10 : 1;
+  unsigned int other_spu_intr11 : 1;
+  unsigned int other_spu_intr12 : 1;
+  unsigned int other_spu_intr13 : 1;
+  unsigned int other_spu_intr14 : 1;
+  unsigned int other_spu_intr15 : 1;
+} reg_iop_sw_spu_r_mpu_intr;
+#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 164
+
+
+/* Constants */
+enum {
+  regk_iop_sw_spu_copy                     = 0x00000000,
+  regk_iop_sw_spu_no                       = 0x00000000,
+  regk_iop_sw_spu_nop                      = 0x00000000,
+  regk_iop_sw_spu_rd                       = 0x00000002,
+  regk_iop_sw_spu_reg_copy                 = 0x00000001,
+  regk_iop_sw_spu_rw_bus0_clr_mask_default = 0x00000000,
+  regk_iop_sw_spu_rw_bus0_oe_clr_mask_default = 0x00000000,
+  regk_iop_sw_spu_rw_bus0_oe_set_mask_default = 0x00000000,
+  regk_iop_sw_spu_rw_bus0_set_mask_default = 0x00000000,
+  regk_iop_sw_spu_rw_bus1_clr_mask_default = 0x00000000,
+  regk_iop_sw_spu_rw_bus1_oe_clr_mask_default = 0x00000000,
+  regk_iop_sw_spu_rw_bus1_oe_set_mask_default = 0x00000000,
+  regk_iop_sw_spu_rw_bus1_set_mask_default = 0x00000000,
+  regk_iop_sw_spu_rw_gio_clr_mask_default  = 0x00000000,
+  regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000,
+  regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000,
+  regk_iop_sw_spu_rw_gio_set_mask_default  = 0x00000000,
+  regk_iop_sw_spu_set                      = 0x00000001,
+  regk_iop_sw_spu_wr                       = 0x00000003,
+  regk_iop_sw_spu_yes                      = 0x00000001
+};
+#endif /* __iop_sw_spu_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h
new file mode 100644
index 00000000000..c994114f3b5
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_timer_grp_defs.h
@@ -0,0 +1,249 @@
+#ifndef __iop_timer_grp_defs_h
+#define __iop_timer_grp_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_timer_grp.r
+ *     id:           iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_timer_grp_defs.h ../../inst/io_proc/rtl/iop_timer_grp.r
+ *      id: $Id: iop_timer_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_timer_grp */
+
+/* Register rw_cfg, scope iop_timer_grp, type rw */
+typedef struct {
+  unsigned int clk_src     : 1;
+  unsigned int trig        : 2;
+  unsigned int clk_gen_div : 8;
+  unsigned int clk_div     : 8;
+  unsigned int dummy1      : 13;
+} reg_iop_timer_grp_rw_cfg;
+#define REG_RD_ADDR_iop_timer_grp_rw_cfg 0
+#define REG_WR_ADDR_iop_timer_grp_rw_cfg 0
+
+/* Register rw_half_period, scope iop_timer_grp, type rw */
+typedef struct {
+  unsigned int quota_lo     : 15;
+  unsigned int quota_hi     : 15;
+  unsigned int quota_hi_sel : 1;
+  unsigned int dummy1       : 1;
+} reg_iop_timer_grp_rw_half_period;
+#define REG_RD_ADDR_iop_timer_grp_rw_half_period 4
+#define REG_WR_ADDR_iop_timer_grp_rw_half_period 4
+
+/* Register rw_half_period_len, scope iop_timer_grp, type rw */
+typedef unsigned int reg_iop_timer_grp_rw_half_period_len;
+#define REG_RD_ADDR_iop_timer_grp_rw_half_period_len 8
+#define REG_WR_ADDR_iop_timer_grp_rw_half_period_len 8
+
+#define STRIDE_iop_timer_grp_rw_tmr_cfg 4
+/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */
+typedef struct {
+  unsigned int clk_src         : 3;
+  unsigned int strb            : 2;
+  unsigned int run_mode        : 2;
+  unsigned int out_mode        : 1;
+  unsigned int active_on_tmr   : 2;
+  unsigned int inv             : 1;
+  unsigned int en_by_tmr       : 2;
+  unsigned int dis_by_tmr      : 2;
+  unsigned int en_only_by_reg  : 1;
+  unsigned int dis_only_by_reg : 1;
+  unsigned int rst_at_en_strb  : 1;
+  unsigned int dummy1          : 14;
+} reg_iop_timer_grp_rw_tmr_cfg;
+#define REG_RD_ADDR_iop_timer_grp_rw_tmr_cfg 12
+#define REG_WR_ADDR_iop_timer_grp_rw_tmr_cfg 12
+
+#define STRIDE_iop_timer_grp_rw_tmr_len 4
+/* Register rw_tmr_len, scope iop_timer_grp, type rw */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_timer_grp_rw_tmr_len;
+#define REG_RD_ADDR_iop_timer_grp_rw_tmr_len 44
+#define REG_WR_ADDR_iop_timer_grp_rw_tmr_len 44
+
+/* Register rw_cmd, scope iop_timer_grp, type rw */
+typedef struct {
+  unsigned int rst  : 4;
+  unsigned int en   : 4;
+  unsigned int dis  : 4;
+  unsigned int strb : 4;
+  unsigned int dummy1 : 16;
+} reg_iop_timer_grp_rw_cmd;
+#define REG_RD_ADDR_iop_timer_grp_rw_cmd 60
+#define REG_WR_ADDR_iop_timer_grp_rw_cmd 60
+
+/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */
+typedef unsigned int reg_iop_timer_grp_r_clk_gen_cnt;
+#define REG_RD_ADDR_iop_timer_grp_r_clk_gen_cnt 64
+
+#define STRIDE_iop_timer_grp_rs_tmr_cnt 8
+/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_timer_grp_rs_tmr_cnt;
+#define REG_RD_ADDR_iop_timer_grp_rs_tmr_cnt 68
+
+#define STRIDE_iop_timer_grp_r_tmr_cnt 8
+/* Register r_tmr_cnt, scope iop_timer_grp, type r */
+typedef struct {
+  unsigned int val : 16;
+  unsigned int dummy1 : 16;
+} reg_iop_timer_grp_r_tmr_cnt;
+#define REG_RD_ADDR_iop_timer_grp_r_tmr_cnt 72
+
+/* Register rw_intr_mask, scope iop_timer_grp, type rw */
+typedef struct {
+  unsigned int tmr0 : 1;
+  unsigned int tmr1 : 1;
+  unsigned int tmr2 : 1;
+  unsigned int tmr3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_timer_grp_rw_intr_mask;
+#define REG_RD_ADDR_iop_timer_grp_rw_intr_mask 100
+#define REG_WR_ADDR_iop_timer_grp_rw_intr_mask 100
+
+/* Register rw_ack_intr, scope iop_timer_grp, type rw */
+typedef struct {
+  unsigned int tmr0 : 1;
+  unsigned int tmr1 : 1;
+  unsigned int tmr2 : 1;
+  unsigned int tmr3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_timer_grp_rw_ack_intr;
+#define REG_RD_ADDR_iop_timer_grp_rw_ack_intr 104
+#define REG_WR_ADDR_iop_timer_grp_rw_ack_intr 104
+
+/* Register r_intr, scope iop_timer_grp, type r */
+typedef struct {
+  unsigned int tmr0 : 1;
+  unsigned int tmr1 : 1;
+  unsigned int tmr2 : 1;
+  unsigned int tmr3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_timer_grp_r_intr;
+#define REG_RD_ADDR_iop_timer_grp_r_intr 108
+
+/* Register r_masked_intr, scope iop_timer_grp, type r */
+typedef struct {
+  unsigned int tmr0 : 1;
+  unsigned int tmr1 : 1;
+  unsigned int tmr2 : 1;
+  unsigned int tmr3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_timer_grp_r_masked_intr;
+#define REG_RD_ADDR_iop_timer_grp_r_masked_intr 112
+
+
+/* Constants */
+enum {
+  regk_iop_timer_grp_clk200                = 0x00000000,
+  regk_iop_timer_grp_clk_gen               = 0x00000002,
+  regk_iop_timer_grp_complete              = 0x00000002,
+  regk_iop_timer_grp_div_clk200            = 0x00000001,
+  regk_iop_timer_grp_div_clk_gen           = 0x00000003,
+  regk_iop_timer_grp_ext                   = 0x00000001,
+  regk_iop_timer_grp_hi                    = 0x00000000,
+  regk_iop_timer_grp_long_period           = 0x00000001,
+  regk_iop_timer_grp_neg                   = 0x00000002,
+  regk_iop_timer_grp_no                    = 0x00000000,
+  regk_iop_timer_grp_once                  = 0x00000003,
+  regk_iop_timer_grp_pause                 = 0x00000001,
+  regk_iop_timer_grp_pos                   = 0x00000001,
+  regk_iop_timer_grp_pos_neg               = 0x00000003,
+  regk_iop_timer_grp_pulse                 = 0x00000000,
+  regk_iop_timer_grp_r_tmr_cnt_size        = 0x00000004,
+  regk_iop_timer_grp_rs_tmr_cnt_size       = 0x00000004,
+  regk_iop_timer_grp_rw_cfg_default        = 0x00000002,
+  regk_iop_timer_grp_rw_intr_mask_default  = 0x00000000,
+  regk_iop_timer_grp_rw_tmr_cfg_default0   = 0x00018000,
+  regk_iop_timer_grp_rw_tmr_cfg_default1   = 0x0001a900,
+  regk_iop_timer_grp_rw_tmr_cfg_default2   = 0x0001d200,
+  regk_iop_timer_grp_rw_tmr_cfg_default3   = 0x0001fb00,
+  regk_iop_timer_grp_rw_tmr_cfg_size       = 0x00000004,
+  regk_iop_timer_grp_rw_tmr_len_default    = 0x00000000,
+  regk_iop_timer_grp_rw_tmr_len_size       = 0x00000004,
+  regk_iop_timer_grp_short_period          = 0x00000000,
+  regk_iop_timer_grp_stop                  = 0x00000000,
+  regk_iop_timer_grp_tmr                   = 0x00000004,
+  regk_iop_timer_grp_toggle                = 0x00000001,
+  regk_iop_timer_grp_yes                   = 0x00000001
+};
+#endif /* __iop_timer_grp_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h
new file mode 100644
index 00000000000..36e44282399
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_trigger_grp_defs.h
@@ -0,0 +1,170 @@
+#ifndef __iop_trigger_grp_defs_h
+#define __iop_trigger_grp_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/iop_trigger_grp.r
+ *     id:           iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp
+ *     last modfied: Mon Apr 11 16:08:46 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_trigger_grp_defs.h ../../inst/io_proc/rtl/iop_trigger_grp.r
+ *      id: $Id: iop_trigger_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_trigger_grp */
+
+#define STRIDE_iop_trigger_grp_rw_cfg 4
+/* Register rw_cfg, scope iop_trigger_grp, type rw */
+typedef struct {
+  unsigned int action          : 2;
+  unsigned int once            : 1;
+  unsigned int trig            : 3;
+  unsigned int en_only_by_reg  : 1;
+  unsigned int dis_only_by_reg : 1;
+  unsigned int dummy1          : 24;
+} reg_iop_trigger_grp_rw_cfg;
+#define REG_RD_ADDR_iop_trigger_grp_rw_cfg 0
+#define REG_WR_ADDR_iop_trigger_grp_rw_cfg 0
+
+/* Register rw_cmd, scope iop_trigger_grp, type rw */
+typedef struct {
+  unsigned int dis : 4;
+  unsigned int en  : 4;
+  unsigned int dummy1 : 24;
+} reg_iop_trigger_grp_rw_cmd;
+#define REG_RD_ADDR_iop_trigger_grp_rw_cmd 16
+#define REG_WR_ADDR_iop_trigger_grp_rw_cmd 16
+
+/* Register rw_intr_mask, scope iop_trigger_grp, type rw */
+typedef struct {
+  unsigned int trig0 : 1;
+  unsigned int trig1 : 1;
+  unsigned int trig2 : 1;
+  unsigned int trig3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_trigger_grp_rw_intr_mask;
+#define REG_RD_ADDR_iop_trigger_grp_rw_intr_mask 20
+#define REG_WR_ADDR_iop_trigger_grp_rw_intr_mask 20
+
+/* Register rw_ack_intr, scope iop_trigger_grp, type rw */
+typedef struct {
+  unsigned int trig0 : 1;
+  unsigned int trig1 : 1;
+  unsigned int trig2 : 1;
+  unsigned int trig3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_trigger_grp_rw_ack_intr;
+#define REG_RD_ADDR_iop_trigger_grp_rw_ack_intr 24
+#define REG_WR_ADDR_iop_trigger_grp_rw_ack_intr 24
+
+/* Register r_intr, scope iop_trigger_grp, type r */
+typedef struct {
+  unsigned int trig0 : 1;
+  unsigned int trig1 : 1;
+  unsigned int trig2 : 1;
+  unsigned int trig3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_trigger_grp_r_intr;
+#define REG_RD_ADDR_iop_trigger_grp_r_intr 28
+
+/* Register r_masked_intr, scope iop_trigger_grp, type r */
+typedef struct {
+  unsigned int trig0 : 1;
+  unsigned int trig1 : 1;
+  unsigned int trig2 : 1;
+  unsigned int trig3 : 1;
+  unsigned int dummy1 : 28;
+} reg_iop_trigger_grp_r_masked_intr;
+#define REG_RD_ADDR_iop_trigger_grp_r_masked_intr 32
+
+
+/* Constants */
+enum {
+  regk_iop_trigger_grp_fall                = 0x00000002,
+  regk_iop_trigger_grp_fall_lo             = 0x00000006,
+  regk_iop_trigger_grp_no                  = 0x00000000,
+  regk_iop_trigger_grp_off                 = 0x00000000,
+  regk_iop_trigger_grp_pulse               = 0x00000000,
+  regk_iop_trigger_grp_rise                = 0x00000001,
+  regk_iop_trigger_grp_rise_fall           = 0x00000003,
+  regk_iop_trigger_grp_rise_fall_hi        = 0x00000007,
+  regk_iop_trigger_grp_rise_fall_lo        = 0x00000004,
+  regk_iop_trigger_grp_rise_hi             = 0x00000005,
+  regk_iop_trigger_grp_rw_cfg_default      = 0x000000c0,
+  regk_iop_trigger_grp_rw_cfg_size         = 0x00000004,
+  regk_iop_trigger_grp_rw_intr_mask_default = 0x00000000,
+  regk_iop_trigger_grp_toggle              = 0x00000003,
+  regk_iop_trigger_grp_yes                 = 0x00000001
+};
+#endif /* __iop_trigger_grp_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h b/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h
new file mode 100644
index 00000000000..b8d6a910c71
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/iop/iop_version_defs.h
@@ -0,0 +1,99 @@
+#ifndef __iop_version_defs_h
+#define __iop_version_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/io_proc/rtl/guinness/iop_version.r
+ *     id:           iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp
+ *     last modfied: Mon Apr 11 16:08:44 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_version_defs.h ../../inst/io_proc/rtl/guinness/iop_version.r
+ *      id: $Id: iop_version_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_version */
+
+/* Register r_version, scope iop_version, type r */
+typedef struct {
+  unsigned int nr : 8;
+  unsigned int dummy1 : 24;
+} reg_iop_version_r_version;
+#define REG_RD_ADDR_iop_version_r_version 0
+
+
+/* Constants */
+enum {
+  regk_iop_version_v1_0                    = 0x00000001
+};
+#endif /* __iop_version_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h b/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h
new file mode 100644
index 00000000000..7b167e3c057
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/irq_nmi_defs.h
@@ -0,0 +1,104 @@
+#ifndef __irq_nmi_defs_h
+#define __irq_nmi_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../mod/irq_nmi.r
+ *     id:           <not found>
+ *     last modfied: Thu Jan 22 09:22:43 2004
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile irq_nmi_defs.h ../../mod/irq_nmi.r
+ *      id: $Id: irq_nmi_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope irq_nmi */
+
+/* Register rw_cmd, scope irq_nmi, type rw */
+typedef struct {
+  unsigned int delay : 16;
+  unsigned int op    : 2;
+  unsigned int dummy1 : 14;
+} reg_irq_nmi_rw_cmd;
+#define REG_RD_ADDR_irq_nmi_rw_cmd 0
+#define REG_WR_ADDR_irq_nmi_rw_cmd 0
+
+
+/* Constants */
+enum {
+  regk_irq_nmi_ack_irq                     = 0x00000002,
+  regk_irq_nmi_ack_nmi                     = 0x00000003,
+  regk_irq_nmi_irq                         = 0x00000000,
+  regk_irq_nmi_nmi                         = 0x00000001
+};
+#endif /* __irq_nmi_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h b/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h
new file mode 100644
index 00000000000..a11fdd3cd90
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/marb_bp_defs.h
@@ -0,0 +1,205 @@
+#ifndef __marb_bp_defs_h
+#define __marb_bp_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/memarb/rtl/guinness/marb_top.r
+ *     id:           <not found>
+ *     last modfied: Fri Nov  7 15:36:04 2003
+ *
+ *   by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r
+ *      id: $Id: marb_bp_defs.h,v 1.2 2004/06/04 07:15:33 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+/* C-code for register scope marb_bp */
+
+/* Register rw_first_addr, scope marb_bp, type rw */
+typedef unsigned int reg_marb_bp_rw_first_addr;
+#define REG_RD_ADDR_marb_bp_rw_first_addr 0
+#define REG_WR_ADDR_marb_bp_rw_first_addr 0
+
+/* Register rw_last_addr, scope marb_bp, type rw */
+typedef unsigned int reg_marb_bp_rw_last_addr;
+#define REG_RD_ADDR_marb_bp_rw_last_addr 4
+#define REG_WR_ADDR_marb_bp_rw_last_addr 4
+
+/* Register rw_op, scope marb_bp, type rw */
+typedef struct {
+  unsigned int read         : 1;
+  unsigned int write        : 1;
+  unsigned int read_excl    : 1;
+  unsigned int pri_write    : 1;
+  unsigned int us_read      : 1;
+  unsigned int us_write     : 1;
+  unsigned int us_read_excl : 1;
+  unsigned int us_pri_write : 1;
+  unsigned int dummy1       : 24;
+} reg_marb_bp_rw_op;
+#define REG_RD_ADDR_marb_bp_rw_op 8
+#define REG_WR_ADDR_marb_bp_rw_op 8
+
+/* Register rw_clients, scope marb_bp, type rw */
+typedef struct {
+  unsigned int dma0  : 1;
+  unsigned int dma1  : 1;
+  unsigned int dma2  : 1;
+  unsigned int dma3  : 1;
+  unsigned int dma4  : 1;
+  unsigned int dma5  : 1;
+  unsigned int dma6  : 1;
+  unsigned int dma7  : 1;
+  unsigned int dma8  : 1;
+  unsigned int dma9  : 1;
+  unsigned int cpui  : 1;
+  unsigned int cpud  : 1;
+  unsigned int iop   : 1;
+  unsigned int slave : 1;
+  unsigned int dummy1 : 18;
+} reg_marb_bp_rw_clients;
+#define REG_RD_ADDR_marb_bp_rw_clients 12
+#define REG_WR_ADDR_marb_bp_rw_clients 12
+
+/* Register rw_options, scope marb_bp, type rw */
+typedef struct {
+  unsigned int wrap : 1;
+  unsigned int dummy1 : 31;
+} reg_marb_bp_rw_options;
+#define REG_RD_ADDR_marb_bp_rw_options 16
+#define REG_WR_ADDR_marb_bp_rw_options 16
+
+/* Register r_break_addr, scope marb_bp, type r */
+typedef unsigned int reg_marb_bp_r_break_addr;
+#define REG_RD_ADDR_marb_bp_r_break_addr 20
+
+/* Register r_break_op, scope marb_bp, type r */
+typedef struct {
+  unsigned int read         : 1;
+  unsigned int write        : 1;
+  unsigned int read_excl    : 1;
+  unsigned int pri_write    : 1;
+  unsigned int us_read      : 1;
+  unsigned int us_write     : 1;
+  unsigned int us_read_excl : 1;
+  unsigned int us_pri_write : 1;
+  unsigned int dummy1       : 24;
+} reg_marb_bp_r_break_op;
+#define REG_RD_ADDR_marb_bp_r_break_op 24
+
+/* Register r_break_clients, scope marb_bp, type r */
+typedef struct {
+  unsigned int dma0  : 1;
+  unsigned int dma1  : 1;
+  unsigned int dma2  : 1;
+  unsigned int dma3  : 1;
+  unsigned int dma4  : 1;
+  unsigned int dma5  : 1;
+  unsigned int dma6  : 1;
+  unsigned int dma7  : 1;
+  unsigned int dma8  : 1;
+  unsigned int dma9  : 1;
+  unsigned int cpui  : 1;
+  unsigned int cpud  : 1;
+  unsigned int iop   : 1;
+  unsigned int slave : 1;
+  unsigned int dummy1 : 18;
+} reg_marb_bp_r_break_clients;
+#define REG_RD_ADDR_marb_bp_r_break_clients 28
+
+/* Register r_break_first_client, scope marb_bp, type r */
+typedef struct {
+  unsigned int dma0  : 1;
+  unsigned int dma1  : 1;
+  unsigned int dma2  : 1;
+  unsigned int dma3  : 1;
+  unsigned int dma4  : 1;
+  unsigned int dma5  : 1;
+  unsigned int dma6  : 1;
+  unsigned int dma7  : 1;
+  unsigned int dma8  : 1;
+  unsigned int dma9  : 1;
+  unsigned int cpui  : 1;
+  unsigned int cpud  : 1;
+  unsigned int iop   : 1;
+  unsigned int slave : 1;
+  unsigned int dummy1 : 18;
+} reg_marb_bp_r_break_first_client;
+#define REG_RD_ADDR_marb_bp_r_break_first_client 32
+
+/* Register r_break_size, scope marb_bp, type r */
+typedef unsigned int reg_marb_bp_r_break_size;
+#define REG_RD_ADDR_marb_bp_r_break_size 36
+
+/* Register rw_ack, scope marb_bp, type rw */
+typedef unsigned int reg_marb_bp_rw_ack;
+#define REG_RD_ADDR_marb_bp_rw_ack 40
+#define REG_WR_ADDR_marb_bp_rw_ack 40
+
+
+/* Constants */
+enum {
+  regk_marb_bp_no                          = 0x00000000,
+  regk_marb_bp_rw_op_default               = 0x00000000,
+  regk_marb_bp_rw_options_default          = 0x00000000,
+  regk_marb_bp_yes                         = 0x00000001
+};
+#endif /* __marb_bp_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/marb_defs.h b/include/asm-cris/arch-v32/hwregs/marb_defs.h
new file mode 100644
index 00000000000..71e8af0bb3a
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/marb_defs.h
@@ -0,0 +1,475 @@
+#ifndef __marb_defs_h
+#define __marb_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/memarb/rtl/guinness/marb_top.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:12:16 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
+ *      id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope marb */
+
+#define STRIDE_marb_rw_int_slots 4
+/* Register rw_int_slots, scope marb, type rw */
+typedef struct {
+  unsigned int owner : 4;
+  unsigned int dummy1 : 28;
+} reg_marb_rw_int_slots;
+#define REG_RD_ADDR_marb_rw_int_slots 0
+#define REG_WR_ADDR_marb_rw_int_slots 0
+
+#define STRIDE_marb_rw_ext_slots 4
+/* Register rw_ext_slots, scope marb, type rw */
+typedef struct {
+  unsigned int owner : 4;
+  unsigned int dummy1 : 28;
+} reg_marb_rw_ext_slots;
+#define REG_RD_ADDR_marb_rw_ext_slots 256
+#define REG_WR_ADDR_marb_rw_ext_slots 256
+
+#define STRIDE_marb_rw_regs_slots 4
+/* Register rw_regs_slots, scope marb, type rw */
+typedef struct {
+  unsigned int owner : 4;
+  unsigned int dummy1 : 28;
+} reg_marb_rw_regs_slots;
+#define REG_RD_ADDR_marb_rw_regs_slots 512
+#define REG_WR_ADDR_marb_rw_regs_slots 512
+
+/* Register rw_intr_mask, scope marb, type rw */
+typedef struct {
+  unsigned int bp0 : 1;
+  unsigned int bp1 : 1;
+  unsigned int bp2 : 1;
+  unsigned int bp3 : 1;
+  unsigned int dummy1 : 28;
+} reg_marb_rw_intr_mask;
+#define REG_RD_ADDR_marb_rw_intr_mask 528
+#define REG_WR_ADDR_marb_rw_intr_mask 528
+
+/* Register rw_ack_intr, scope marb, type rw */
+typedef struct {
+  unsigned int bp0 : 1;
+  unsigned int bp1 : 1;
+  unsigned int bp2 : 1;
+  unsigned int bp3 : 1;
+  unsigned int dummy1 : 28;
+} reg_marb_rw_ack_intr;
+#define REG_RD_ADDR_marb_rw_ack_intr 532
+#define REG_WR_ADDR_marb_rw_ack_intr 532
+
+/* Register r_intr, scope marb, type r */
+typedef struct {
+  unsigned int bp0 : 1;
+  unsigned int bp1 : 1;
+  unsigned int bp2 : 1;
+  unsigned int bp3 : 1;
+  unsigned int dummy1 : 28;
+} reg_marb_r_intr;
+#define REG_RD_ADDR_marb_r_intr 536
+
+/* Register r_masked_intr, scope marb, type r */
+typedef struct {
+  unsigned int bp0 : 1;
+  unsigned int bp1 : 1;
+  unsigned int bp2 : 1;
+  unsigned int bp3 : 1;
+  unsigned int dummy1 : 28;
+} reg_marb_r_masked_intr;
+#define REG_RD_ADDR_marb_r_masked_intr 540
+
+/* Register rw_stop_mask, scope marb, type rw */
+typedef struct {
+  unsigned int dma0  : 1;
+  unsigned int dma1  : 1;
+  unsigned int dma2  : 1;
+  unsigned int dma3  : 1;
+  unsigned int dma4  : 1;
+  unsigned int dma5  : 1;
+  unsigned int dma6  : 1;
+  unsigned int dma7  : 1;
+  unsigned int dma8  : 1;
+  unsigned int dma9  : 1;
+  unsigned int cpui  : 1;
+  unsigned int cpud  : 1;
+  unsigned int iop   : 1;
+  unsigned int slave : 1;
+  unsigned int dummy1 : 18;
+} reg_marb_rw_stop_mask;
+#define REG_RD_ADDR_marb_rw_stop_mask 544
+#define REG_WR_ADDR_marb_rw_stop_mask 544
+
+/* Register r_stopped, scope marb, type r */
+typedef struct {
+  unsigned int dma0  : 1;
+  unsigned int dma1  : 1;
+  unsigned int dma2  : 1;
+  unsigned int dma3  : 1;
+  unsigned int dma4  : 1;
+  unsigned int dma5  : 1;
+  unsigned int dma6  : 1;
+  unsigned int dma7  : 1;
+  unsigned int dma8  : 1;
+  unsigned int dma9  : 1;
+  unsigned int cpui  : 1;
+  unsigned int cpud  : 1;
+  unsigned int iop   : 1;
+  unsigned int slave : 1;
+  unsigned int dummy1 : 18;
+} reg_marb_r_stopped;
+#define REG_RD_ADDR_marb_r_stopped 548
+
+/* Register rw_no_snoop, scope marb, type rw */
+typedef struct {
+  unsigned int dma0  : 1;
+  unsigned int dma1  : 1;
+  unsigned int dma2  : 1;
+  unsigned int dma3  : 1;
+  unsigned int dma4  : 1;
+  unsigned int dma5  : 1;
+  unsigned int dma6  : 1;
+  unsigned int dma7  : 1;
+  unsigned int dma8  : 1;
+  unsigned int dma9  : 1;
+  unsigned int cpui  : 1;
+  unsigned int cpud  : 1;
+  unsigned int iop   : 1;
+  unsigned int slave : 1;
+  unsigned int dummy1 : 18;
+} reg_marb_rw_no_snoop;
+#define REG_RD_ADDR_marb_rw_no_snoop 832
+#define REG_WR_ADDR_marb_rw_no_snoop 832
+
+/* Register rw_no_snoop_rq, scope marb, type rw */
+typedef struct {
+  unsigned int dummy1 : 10;
+  unsigned int cpui : 1;
+  unsigned int cpud : 1;
+  unsigned int dummy2 : 20;
+} reg_marb_rw_no_snoop_rq;
+#define REG_RD_ADDR_marb_rw_no_snoop_rq 836
+#define REG_WR_ADDR_marb_rw_no_snoop_rq 836
+
+
+/* Constants */
+enum {
+  regk_marb_cpud                           = 0x0000000b,
+  regk_marb_cpui                           = 0x0000000a,
+  regk_marb_dma0                           = 0x00000000,
+  regk_marb_dma1                           = 0x00000001,
+  regk_marb_dma2                           = 0x00000002,
+  regk_marb_dma3                           = 0x00000003,
+  regk_marb_dma4                           = 0x00000004,
+  regk_marb_dma5                           = 0x00000005,
+  regk_marb_dma6                           = 0x00000006,
+  regk_marb_dma7                           = 0x00000007,
+  regk_marb_dma8                           = 0x00000008,
+  regk_marb_dma9                           = 0x00000009,
+  regk_marb_iop                            = 0x0000000c,
+  regk_marb_no                             = 0x00000000,
+  regk_marb_r_stopped_default              = 0x00000000,
+  regk_marb_rw_ext_slots_default           = 0x00000000,
+  regk_marb_rw_ext_slots_size              = 0x00000040,
+  regk_marb_rw_int_slots_default           = 0x00000000,
+  regk_marb_rw_int_slots_size              = 0x00000040,
+  regk_marb_rw_intr_mask_default           = 0x00000000,
+  regk_marb_rw_no_snoop_default            = 0x00000000,
+  regk_marb_rw_no_snoop_rq_default         = 0x00000000,
+  regk_marb_rw_regs_slots_default          = 0x00000000,
+  regk_marb_rw_regs_slots_size             = 0x00000004,
+  regk_marb_rw_stop_mask_default           = 0x00000000,
+  regk_marb_slave                          = 0x0000000d,
+  regk_marb_yes                            = 0x00000001
+};
+#endif /* __marb_defs_h */
+#ifndef __marb_bp_defs_h
+#define __marb_bp_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/memarb/rtl/guinness/marb_top.r
+ *     id:           <not found>
+ *     last modfied: Mon Apr 11 16:12:16 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
+ *      id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope marb_bp */
+
+/* Register rw_first_addr, scope marb_bp, type rw */
+typedef unsigned int reg_marb_bp_rw_first_addr;
+#define REG_RD_ADDR_marb_bp_rw_first_addr 0
+#define REG_WR_ADDR_marb_bp_rw_first_addr 0
+
+/* Register rw_last_addr, scope marb_bp, type rw */
+typedef unsigned int reg_marb_bp_rw_last_addr;
+#define REG_RD_ADDR_marb_bp_rw_last_addr 4
+#define REG_WR_ADDR_marb_bp_rw_last_addr 4
+
+/* Register rw_op, scope marb_bp, type rw */
+typedef struct {
+  unsigned int rd         : 1;
+  unsigned int wr         : 1;
+  unsigned int rd_excl    : 1;
+  unsigned int pri_wr     : 1;
+  unsigned int us_rd      : 1;
+  unsigned int us_wr      : 1;
+  unsigned int us_rd_excl : 1;
+  unsigned int us_pri_wr  : 1;
+  unsigned int dummy1     : 24;
+} reg_marb_bp_rw_op;
+#define REG_RD_ADDR_marb_bp_rw_op 8
+#define REG_WR_ADDR_marb_bp_rw_op 8
+
+/* Register rw_clients, scope marb_bp, type rw */
+typedef struct {
+  unsigned int dma0  : 1;
+  unsigned int dma1  : 1;
+  unsigned int dma2  : 1;
+  unsigned int dma3  : 1;
+  unsigned int dma4  : 1;
+  unsigned int dma5  : 1;
+  unsigned int dma6  : 1;
+  unsigned int dma7  : 1;
+  unsigned int dma8  : 1;
+  unsigned int dma9  : 1;
+  unsigned int cpui  : 1;
+  unsigned int cpud  : 1;
+  unsigned int iop   : 1;
+  unsigned int slave : 1;
+  unsigned int dummy1 : 18;
+} reg_marb_bp_rw_clients;
+#define REG_RD_ADDR_marb_bp_rw_clients 12
+#define REG_WR_ADDR_marb_bp_rw_clients 12
+
+/* Register rw_options, scope marb_bp, type rw */
+typedef struct {
+  unsigned int wrap : 1;
+  unsigned int dummy1 : 31;
+} reg_marb_bp_rw_options;
+#define REG_RD_ADDR_marb_bp_rw_options 16
+#define REG_WR_ADDR_marb_bp_rw_options 16
+
+/* Register r_brk_addr, scope marb_bp, type r */
+typedef unsigned int reg_marb_bp_r_brk_addr;
+#define REG_RD_ADDR_marb_bp_r_brk_addr 20
+
+/* Register r_brk_op, scope marb_bp, type r */
+typedef struct {
+  unsigned int rd         : 1;
+  unsigned int wr         : 1;
+  unsigned int rd_excl    : 1;
+  unsigned int pri_wr     : 1;
+  unsigned int us_rd      : 1;
+  unsigned int us_wr      : 1;
+  unsigned int us_rd_excl : 1;
+  unsigned int us_pri_wr  : 1;
+  unsigned int dummy1     : 24;
+} reg_marb_bp_r_brk_op;
+#define REG_RD_ADDR_marb_bp_r_brk_op 24
+
+/* Register r_brk_clients, scope marb_bp, type r */
+typedef struct {
+  unsigned int dma0  : 1;
+  unsigned int dma1  : 1;
+  unsigned int dma2  : 1;
+  unsigned int dma3  : 1;
+  unsigned int dma4  : 1;
+  unsigned int dma5  : 1;
+  unsigned int dma6  : 1;
+  unsigned int dma7  : 1;
+  unsigned int dma8  : 1;
+  unsigned int dma9  : 1;
+  unsigned int cpui  : 1;
+  unsigned int cpud  : 1;
+  unsigned int iop   : 1;
+  unsigned int slave : 1;
+  unsigned int dummy1 : 18;
+} reg_marb_bp_r_brk_clients;
+#define REG_RD_ADDR_marb_bp_r_brk_clients 28
+
+/* Register r_brk_first_client, scope marb_bp, type r */
+typedef struct {
+  unsigned int dma0  : 1;
+  unsigned int dma1  : 1;
+  unsigned int dma2  : 1;
+  unsigned int dma3  : 1;
+  unsigned int dma4  : 1;
+  unsigned int dma5  : 1;
+  unsigned int dma6  : 1;
+  unsigned int dma7  : 1;
+  unsigned int dma8  : 1;
+  unsigned int dma9  : 1;
+  unsigned int cpui  : 1;
+  unsigned int cpud  : 1;
+  unsigned int iop   : 1;
+  unsigned int slave : 1;
+  unsigned int dummy1 : 18;
+} reg_marb_bp_r_brk_first_client;
+#define REG_RD_ADDR_marb_bp_r_brk_first_client 32
+
+/* Register r_brk_size, scope marb_bp, type r */
+typedef unsigned int reg_marb_bp_r_brk_size;
+#define REG_RD_ADDR_marb_bp_r_brk_size 36
+
+/* Register rw_ack, scope marb_bp, type rw */
+typedef unsigned int reg_marb_bp_rw_ack;
+#define REG_RD_ADDR_marb_bp_rw_ack 40
+#define REG_WR_ADDR_marb_bp_rw_ack 40
+
+
+/* Constants */
+enum {
+  regk_marb_bp_no                          = 0x00000000,
+  regk_marb_bp_rw_op_default               = 0x00000000,
+  regk_marb_bp_rw_options_default          = 0x00000000,
+  regk_marb_bp_yes                         = 0x00000001
+};
+#endif /* __marb_bp_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/pinmux_defs.h b/include/asm-cris/arch-v32/hwregs/pinmux_defs.h
new file mode 100644
index 00000000000..9d91c2de1b0
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/pinmux_defs.h
@@ -0,0 +1,357 @@
+#ifndef __pinmux_defs_h
+#define __pinmux_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/pinmux/rtl/guinness/pinmux_regs.r
+ *     id:           pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp
+ *     last modfied: Mon Apr 11 16:09:11 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
+ *      id: $Id: pinmux_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope pinmux */
+
+/* Register rw_pa, scope pinmux, type rw */
+typedef struct {
+  unsigned int pa0    : 1;
+  unsigned int pa1    : 1;
+  unsigned int pa2    : 1;
+  unsigned int pa3    : 1;
+  unsigned int pa4    : 1;
+  unsigned int pa5    : 1;
+  unsigned int pa6    : 1;
+  unsigned int pa7    : 1;
+  unsigned int csp2_n : 1;
+  unsigned int csp3_n : 1;
+  unsigned int csp5_n : 1;
+  unsigned int csp6_n : 1;
+  unsigned int hsh4   : 1;
+  unsigned int hsh5   : 1;
+  unsigned int hsh6   : 1;
+  unsigned int hsh7   : 1;
+  unsigned int dummy1 : 16;
+} reg_pinmux_rw_pa;
+#define REG_RD_ADDR_pinmux_rw_pa 0
+#define REG_WR_ADDR_pinmux_rw_pa 0
+
+/* Register rw_hwprot, scope pinmux, type rw */
+typedef struct {
+  unsigned int ser1     : 1;
+  unsigned int ser2     : 1;
+  unsigned int ser3     : 1;
+  unsigned int sser0    : 1;
+  unsigned int sser1    : 1;
+  unsigned int ata0     : 1;
+  unsigned int ata1     : 1;
+  unsigned int ata2     : 1;
+  unsigned int ata3     : 1;
+  unsigned int ata      : 1;
+  unsigned int eth1     : 1;
+  unsigned int eth1_mgm : 1;
+  unsigned int timer    : 1;
+  unsigned int p21      : 1;
+  unsigned int dummy1   : 18;
+} reg_pinmux_rw_hwprot;
+#define REG_RD_ADDR_pinmux_rw_hwprot 4
+#define REG_WR_ADDR_pinmux_rw_hwprot 4
+
+/* Register rw_pb_gio, scope pinmux, type rw */
+typedef struct {
+  unsigned int pb0  : 1;
+  unsigned int pb1  : 1;
+  unsigned int pb2  : 1;
+  unsigned int pb3  : 1;
+  unsigned int pb4  : 1;
+  unsigned int pb5  : 1;
+  unsigned int pb6  : 1;
+  unsigned int pb7  : 1;
+  unsigned int pb8  : 1;
+  unsigned int pb9  : 1;
+  unsigned int pb10 : 1;
+  unsigned int pb11 : 1;
+  unsigned int pb12 : 1;
+  unsigned int pb13 : 1;
+  unsigned int pb14 : 1;
+  unsigned int pb15 : 1;
+  unsigned int pb16 : 1;
+  unsigned int pb17 : 1;
+  unsigned int dummy1 : 14;
+} reg_pinmux_rw_pb_gio;
+#define REG_RD_ADDR_pinmux_rw_pb_gio 8
+#define REG_WR_ADDR_pinmux_rw_pb_gio 8
+
+/* Register rw_pb_iop, scope pinmux, type rw */
+typedef struct {
+  unsigned int pb0  : 1;
+  unsigned int pb1  : 1;
+  unsigned int pb2  : 1;
+  unsigned int pb3  : 1;
+  unsigned int pb4  : 1;
+  unsigned int pb5  : 1;
+  unsigned int pb6  : 1;
+  unsigned int pb7  : 1;
+  unsigned int pb8  : 1;
+  unsigned int pb9  : 1;
+  unsigned int pb10 : 1;
+  unsigned int pb11 : 1;
+  unsigned int pb12 : 1;
+  unsigned int pb13 : 1;
+  unsigned int pb14 : 1;
+  unsigned int pb15 : 1;
+  unsigned int pb16 : 1;
+  unsigned int pb17 : 1;
+  unsigned int dummy1 : 14;
+} reg_pinmux_rw_pb_iop;
+#define REG_RD_ADDR_pinmux_rw_pb_iop 12
+#define REG_WR_ADDR_pinmux_rw_pb_iop 12
+
+/* Register rw_pc_gio, scope pinmux, type rw */
+typedef struct {
+  unsigned int pc0  : 1;
+  unsigned int pc1  : 1;
+  unsigned int pc2  : 1;
+  unsigned int pc3  : 1;
+  unsigned int pc4  : 1;
+  unsigned int pc5  : 1;
+  unsigned int pc6  : 1;
+  unsigned int pc7  : 1;
+  unsigned int pc8  : 1;
+  unsigned int pc9  : 1;
+  unsigned int pc10 : 1;
+  unsigned int pc11 : 1;
+  unsigned int pc12 : 1;
+  unsigned int pc13 : 1;
+  unsigned int pc14 : 1;
+  unsigned int pc15 : 1;
+  unsigned int pc16 : 1;
+  unsigned int pc17 : 1;
+  unsigned int dummy1 : 14;
+} reg_pinmux_rw_pc_gio;
+#define REG_RD_ADDR_pinmux_rw_pc_gio 16
+#define REG_WR_ADDR_pinmux_rw_pc_gio 16
+
+/* Register rw_pc_iop, scope pinmux, type rw */
+typedef struct {
+  unsigned int pc0  : 1;
+  unsigned int pc1  : 1;
+  unsigned int pc2  : 1;
+  unsigned int pc3  : 1;
+  unsigned int pc4  : 1;
+  unsigned int pc5  : 1;
+  unsigned int pc6  : 1;
+  unsigned int pc7  : 1;
+  unsigned int pc8  : 1;
+  unsigned int pc9  : 1;
+  unsigned int pc10 : 1;
+  unsigned int pc11 : 1;
+  unsigned int pc12 : 1;
+  unsigned int pc13 : 1;
+  unsigned int pc14 : 1;
+  unsigned int pc15 : 1;
+  unsigned int pc16 : 1;
+  unsigned int pc17 : 1;
+  unsigned int dummy1 : 14;
+} reg_pinmux_rw_pc_iop;
+#define REG_RD_ADDR_pinmux_rw_pc_iop 20
+#define REG_WR_ADDR_pinmux_rw_pc_iop 20
+
+/* Register rw_pd_gio, scope pinmux, type rw */
+typedef struct {
+  unsigned int pd0  : 1;
+  unsigned int pd1  : 1;
+  unsigned int pd2  : 1;
+  unsigned int pd3  : 1;
+  unsigned int pd4  : 1;
+  unsigned int pd5  : 1;
+  unsigned int pd6  : 1;
+  unsigned int pd7  : 1;
+  unsigned int pd8  : 1;
+  unsigned int pd9  : 1;
+  unsigned int pd10 : 1;
+  unsigned int pd11 : 1;
+  unsigned int pd12 : 1;
+  unsigned int pd13 : 1;
+  unsigned int pd14 : 1;
+  unsigned int pd15 : 1;
+  unsigned int pd16 : 1;
+  unsigned int pd17 : 1;
+  unsigned int dummy1 : 14;
+} reg_pinmux_rw_pd_gio;
+#define REG_RD_ADDR_pinmux_rw_pd_gio 24
+#define REG_WR_ADDR_pinmux_rw_pd_gio 24
+
+/* Register rw_pd_iop, scope pinmux, type rw */
+typedef struct {
+  unsigned int pd0  : 1;
+  unsigned int pd1  : 1;
+  unsigned int pd2  : 1;
+  unsigned int pd3  : 1;
+  unsigned int pd4  : 1;
+  unsigned int pd5  : 1;
+  unsigned int pd6  : 1;
+  unsigned int pd7  : 1;
+  unsigned int pd8  : 1;
+  unsigned int pd9  : 1;
+  unsigned int pd10 : 1;
+  unsigned int pd11 : 1;
+  unsigned int pd12 : 1;
+  unsigned int pd13 : 1;
+  unsigned int pd14 : 1;
+  unsigned int pd15 : 1;
+  unsigned int pd16 : 1;
+  unsigned int pd17 : 1;
+  unsigned int dummy1 : 14;
+} reg_pinmux_rw_pd_iop;
+#define REG_RD_ADDR_pinmux_rw_pd_iop 28
+#define REG_WR_ADDR_pinmux_rw_pd_iop 28
+
+/* Register rw_pe_gio, scope pinmux, type rw */
+typedef struct {
+  unsigned int pe0  : 1;
+  unsigned int pe1  : 1;
+  unsigned int pe2  : 1;
+  unsigned int pe3  : 1;
+  unsigned int pe4  : 1;
+  unsigned int pe5  : 1;
+  unsigned int pe6  : 1;
+  unsigned int pe7  : 1;
+  unsigned int pe8  : 1;
+  unsigned int pe9  : 1;
+  unsigned int pe10 : 1;
+  unsigned int pe11 : 1;
+  unsigned int pe12 : 1;
+  unsigned int pe13 : 1;
+  unsigned int pe14 : 1;
+  unsigned int pe15 : 1;
+  unsigned int pe16 : 1;
+  unsigned int pe17 : 1;
+  unsigned int dummy1 : 14;
+} reg_pinmux_rw_pe_gio;
+#define REG_RD_ADDR_pinmux_rw_pe_gio 32
+#define REG_WR_ADDR_pinmux_rw_pe_gio 32
+
+/* Register rw_pe_iop, scope pinmux, type rw */
+typedef struct {
+  unsigned int pe0  : 1;
+  unsigned int pe1  : 1;
+  unsigned int pe2  : 1;
+  unsigned int pe3  : 1;
+  unsigned int pe4  : 1;
+  unsigned int pe5  : 1;
+  unsigned int pe6  : 1;
+  unsigned int pe7  : 1;
+  unsigned int pe8  : 1;
+  unsigned int pe9  : 1;
+  unsigned int pe10 : 1;
+  unsigned int pe11 : 1;
+  unsigned int pe12 : 1;
+  unsigned int pe13 : 1;
+  unsigned int pe14 : 1;
+  unsigned int pe15 : 1;
+  unsigned int pe16 : 1;
+  unsigned int pe17 : 1;
+  unsigned int dummy1 : 14;
+} reg_pinmux_rw_pe_iop;
+#define REG_RD_ADDR_pinmux_rw_pe_iop 36
+#define REG_WR_ADDR_pinmux_rw_pe_iop 36
+
+/* Register rw_usb_phy, scope pinmux, type rw */
+typedef struct {
+  unsigned int en_usb0 : 1;
+  unsigned int en_usb1 : 1;
+  unsigned int dummy1  : 30;
+} reg_pinmux_rw_usb_phy;
+#define REG_RD_ADDR_pinmux_rw_usb_phy 40
+#define REG_WR_ADDR_pinmux_rw_usb_phy 40
+
+
+/* Constants */
+enum {
+  regk_pinmux_no                           = 0x00000000,
+  regk_pinmux_rw_hwprot_default            = 0x00000000,
+  regk_pinmux_rw_pa_default                = 0x00000000,
+  regk_pinmux_rw_pb_gio_default            = 0x00000000,
+  regk_pinmux_rw_pb_iop_default            = 0x00000000,
+  regk_pinmux_rw_pc_gio_default            = 0x00000000,
+  regk_pinmux_rw_pc_iop_default            = 0x00000000,
+  regk_pinmux_rw_pd_gio_default            = 0x00000000,
+  regk_pinmux_rw_pd_iop_default            = 0x00000000,
+  regk_pinmux_rw_pe_gio_default            = 0x00000000,
+  regk_pinmux_rw_pe_iop_default            = 0x00000000,
+  regk_pinmux_rw_usb_phy_default           = 0x00000000,
+  regk_pinmux_yes                          = 0x00000001
+};
+#endif /* __pinmux_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/reg_map.h b/include/asm-cris/arch-v32/hwregs/reg_map.h
new file mode 100644
index 00000000000..e31502838ec
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/reg_map.h
@@ -0,0 +1,103 @@
+#ifndef __reg_map_h
+#define __reg_map_h
+
+/*
+ * This file is autogenerated from
+ *   file:            ../../mod/fakereg.rmap
+ *     id:            fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp
+ *     last modified: Wed Feb 11 20:53:25 2004
+ *   file:            ../../rtl/global.rmap
+ *     id:            global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp
+ *     last modified: Mon Aug 18 17:08:23 2003
+ *   file:            ../../mod/modreg.rmap
+ *     id:            modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp
+ *     last modified: Fri Feb 20 16:40:04 2004
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
+ *      id: $Id: reg_map.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+typedef enum {
+  regi_ata                                 = 0xb0032000,
+  regi_bif_core                            = 0xb0014000,
+  regi_bif_dma                             = 0xb0016000,
+  regi_bif_slave                           = 0xb0018000,
+  regi_config                              = 0xb003c000,
+  regi_dma0                                = 0xb0000000,
+  regi_dma1                                = 0xb0002000,
+  regi_dma2                                = 0xb0004000,
+  regi_dma3                                = 0xb0006000,
+  regi_dma4                                = 0xb0008000,
+  regi_dma5                                = 0xb000a000,
+  regi_dma6                                = 0xb000c000,
+  regi_dma7                                = 0xb000e000,
+  regi_dma8                                = 0xb0010000,
+  regi_dma9                                = 0xb0012000,
+  regi_eth0                                = 0xb0034000,
+  regi_eth1                                = 0xb0036000,
+  regi_gio                                 = 0xb001a000,
+  regi_iop                                 = 0xb0020000,
+  regi_iop_version                         = 0xb0020000,
+  regi_iop_fifo_in0_extra                  = 0xb0020040,
+  regi_iop_fifo_in1_extra                  = 0xb0020080,
+  regi_iop_fifo_out0_extra                 = 0xb00200c0,
+  regi_iop_fifo_out1_extra                 = 0xb0020100,
+  regi_iop_trigger_grp0                    = 0xb0020140,
+  regi_iop_trigger_grp1                    = 0xb0020180,
+  regi_iop_trigger_grp2                    = 0xb00201c0,
+  regi_iop_trigger_grp3                    = 0xb0020200,
+  regi_iop_trigger_grp4                    = 0xb0020240,
+  regi_iop_trigger_grp5                    = 0xb0020280,
+  regi_iop_trigger_grp6                    = 0xb00202c0,
+  regi_iop_trigger_grp7                    = 0xb0020300,
+  regi_iop_crc_par0                        = 0xb0020380,
+  regi_iop_crc_par1                        = 0xb0020400,
+  regi_iop_dmc_in0                         = 0xb0020480,
+  regi_iop_dmc_in1                         = 0xb0020500,
+  regi_iop_dmc_out0                        = 0xb0020580,
+  regi_iop_dmc_out1                        = 0xb0020600,
+  regi_iop_fifo_in0                        = 0xb0020680,
+  regi_iop_fifo_in1                        = 0xb0020700,
+  regi_iop_fifo_out0                       = 0xb0020780,
+  regi_iop_fifo_out1                       = 0xb0020800,
+  regi_iop_scrc_in0                        = 0xb0020880,
+  regi_iop_scrc_in1                        = 0xb0020900,
+  regi_iop_scrc_out0                       = 0xb0020980,
+  regi_iop_scrc_out1                       = 0xb0020a00,
+  regi_iop_timer_grp0                      = 0xb0020a80,
+  regi_iop_timer_grp1                      = 0xb0020b00,
+  regi_iop_timer_grp2                      = 0xb0020b80,
+  regi_iop_timer_grp3                      = 0xb0020c00,
+  regi_iop_sap_in                          = 0xb0020d00,
+  regi_iop_sap_out                         = 0xb0020e00,
+  regi_iop_spu0                            = 0xb0020f00,
+  regi_iop_spu1                            = 0xb0021000,
+  regi_iop_sw_cfg                          = 0xb0021100,
+  regi_iop_sw_cpu                          = 0xb0021200,
+  regi_iop_sw_mpu                          = 0xb0021300,
+  regi_iop_sw_spu0                         = 0xb0021400,
+  regi_iop_sw_spu1                         = 0xb0021500,
+  regi_iop_mpu                             = 0xb0021600,
+  regi_irq                                 = 0xb001c000,
+  regi_irq2                                = 0xb005c000,
+  regi_marb                                = 0xb003e000,
+  regi_marb_bp0                            = 0xb003e240,
+  regi_marb_bp1                            = 0xb003e280,
+  regi_marb_bp2                            = 0xb003e2c0,
+  regi_marb_bp3                            = 0xb003e300,
+  regi_pinmux                              = 0xb0038000,
+  regi_ser0                                = 0xb0026000,
+  regi_ser1                                = 0xb0028000,
+  regi_ser2                                = 0xb002a000,
+  regi_ser3                                = 0xb002c000,
+  regi_sser0                               = 0xb0022000,
+  regi_sser1                               = 0xb0024000,
+  regi_strcop                              = 0xb0030000,
+  regi_strmux                              = 0xb003a000,
+  regi_timer                               = 0xb001e000,
+  regi_timer2                              = 0xb005e000,
+  regi_trace                               = 0xb0040000,
+} reg_scope_instances;
+#endif /* __reg_map_h */
diff --git a/include/asm-cris/arch-v32/hwregs/reg_rdwr.h b/include/asm-cris/arch-v32/hwregs/reg_rdwr.h
new file mode 100644
index 00000000000..44e60233c68
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/reg_rdwr.h
@@ -0,0 +1,15 @@
+/* $Id: reg_rdwr.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
+ *
+ * Read/write register macros used by *_defs.h
+ */
+
+#ifndef reg_rdwr_h
+#define reg_rdwr_h
+
+
+#define REG_READ(type, addr) *((volatile type *) (addr))
+
+#define REG_WRITE(type, addr, val) \
+   do { *((volatile type *) (addr)) = (val); } while(0)
+
+#endif
diff --git a/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h b/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h
new file mode 100644
index 00000000000..d9f0e924fb2
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/rt_trace_defs.h
@@ -0,0 +1,173 @@
+#ifndef __rt_trace_defs_h
+#define __rt_trace_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/rt_trace/rtl/rt_regs.r
+ *     id:           rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp
+ *     last modfied: Mon Apr 11 16:09:14 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile rt_trace_defs.h ../../inst/rt_trace/rtl/rt_regs.r
+ *      id: $Id: rt_trace_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope rt_trace */
+
+/* Register rw_cfg, scope rt_trace, type rw */
+typedef struct {
+  unsigned int en       : 1;
+  unsigned int mode     : 1;
+  unsigned int owner    : 1;
+  unsigned int wp       : 1;
+  unsigned int stall    : 1;
+  unsigned int dummy1   : 3;
+  unsigned int wp_start : 7;
+  unsigned int dummy2   : 1;
+  unsigned int wp_stop  : 7;
+  unsigned int dummy3   : 9;
+} reg_rt_trace_rw_cfg;
+#define REG_RD_ADDR_rt_trace_rw_cfg 0
+#define REG_WR_ADDR_rt_trace_rw_cfg 0
+
+/* Register rw_tap_ctrl, scope rt_trace, type rw */
+typedef struct {
+  unsigned int ack_data : 1;
+  unsigned int ack_guru : 1;
+  unsigned int dummy1   : 30;
+} reg_rt_trace_rw_tap_ctrl;
+#define REG_RD_ADDR_rt_trace_rw_tap_ctrl 4
+#define REG_WR_ADDR_rt_trace_rw_tap_ctrl 4
+
+/* Register r_tap_stat, scope rt_trace, type r */
+typedef struct {
+  unsigned int dav   : 1;
+  unsigned int empty : 1;
+  unsigned int dummy1 : 30;
+} reg_rt_trace_r_tap_stat;
+#define REG_RD_ADDR_rt_trace_r_tap_stat 8
+
+/* Register rw_tap_data, scope rt_trace, type rw */
+typedef unsigned int reg_rt_trace_rw_tap_data;
+#define REG_RD_ADDR_rt_trace_rw_tap_data 12
+#define REG_WR_ADDR_rt_trace_rw_tap_data 12
+
+/* Register rw_tap_hdata, scope rt_trace, type rw */
+typedef struct {
+  unsigned int op     : 4;
+  unsigned int sub_op : 4;
+  unsigned int dummy1 : 24;
+} reg_rt_trace_rw_tap_hdata;
+#define REG_RD_ADDR_rt_trace_rw_tap_hdata 16
+#define REG_WR_ADDR_rt_trace_rw_tap_hdata 16
+
+/* Register r_redir, scope rt_trace, type r */
+typedef unsigned int reg_rt_trace_r_redir;
+#define REG_RD_ADDR_rt_trace_r_redir 20
+
+
+/* Constants */
+enum {
+  regk_rt_trace_brk                        = 0x0000000c,
+  regk_rt_trace_dbg                        = 0x00000003,
+  regk_rt_trace_dbgdi                      = 0x00000004,
+  regk_rt_trace_dbgdo                      = 0x00000005,
+  regk_rt_trace_gmode                      = 0x00000000,
+  regk_rt_trace_no                         = 0x00000000,
+  regk_rt_trace_nop                        = 0x00000000,
+  regk_rt_trace_normal                     = 0x00000000,
+  regk_rt_trace_rdmem                      = 0x00000007,
+  regk_rt_trace_rdmemb                     = 0x00000009,
+  regk_rt_trace_rdpreg                     = 0x00000002,
+  regk_rt_trace_rdreg                      = 0x00000001,
+  regk_rt_trace_rdsreg                     = 0x00000003,
+  regk_rt_trace_redir                      = 0x00000006,
+  regk_rt_trace_ret                        = 0x0000000b,
+  regk_rt_trace_rw_cfg_default             = 0x00000000,
+  regk_rt_trace_trcfg                      = 0x00000001,
+  regk_rt_trace_wp                         = 0x00000001,
+  regk_rt_trace_wp0                        = 0x00000001,
+  regk_rt_trace_wp1                        = 0x00000002,
+  regk_rt_trace_wp2                        = 0x00000004,
+  regk_rt_trace_wp3                        = 0x00000008,
+  regk_rt_trace_wp4                        = 0x00000010,
+  regk_rt_trace_wp5                        = 0x00000020,
+  regk_rt_trace_wp6                        = 0x00000040,
+  regk_rt_trace_wrmem                      = 0x00000008,
+  regk_rt_trace_wrmemb                     = 0x0000000a,
+  regk_rt_trace_wrpreg                     = 0x00000005,
+  regk_rt_trace_wrreg                      = 0x00000004,
+  regk_rt_trace_wrsreg                     = 0x00000006,
+  regk_rt_trace_yes                        = 0x00000001
+};
+#endif /* __rt_trace_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/ser_defs.h b/include/asm-cris/arch-v32/hwregs/ser_defs.h
new file mode 100644
index 00000000000..01c2fab97d4
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/ser_defs.h
@@ -0,0 +1,308 @@
+#ifndef __ser_defs_h
+#define __ser_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/ser/rtl/ser_regs.r
+ *     id:           ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp
+ *     last modfied: Mon Apr 11 16:09:21 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile ser_defs.h ../../inst/ser/rtl/ser_regs.r
+ *      id: $Id: ser_defs.h,v 1.10 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope ser */
+
+/* Register rw_tr_ctrl, scope ser, type rw */
+typedef struct {
+  unsigned int base_freq : 3;
+  unsigned int en        : 1;
+  unsigned int par       : 2;
+  unsigned int par_en    : 1;
+  unsigned int data_bits : 1;
+  unsigned int stop_bits : 1;
+  unsigned int stop      : 1;
+  unsigned int rts_delay : 3;
+  unsigned int rts_setup : 1;
+  unsigned int auto_rts  : 1;
+  unsigned int txd       : 1;
+  unsigned int auto_cts  : 1;
+  unsigned int dummy1    : 15;
+} reg_ser_rw_tr_ctrl;
+#define REG_RD_ADDR_ser_rw_tr_ctrl 0
+#define REG_WR_ADDR_ser_rw_tr_ctrl 0
+
+/* Register rw_tr_dma_en, scope ser, type rw */
+typedef struct {
+  unsigned int en : 1;
+  unsigned int dummy1 : 31;
+} reg_ser_rw_tr_dma_en;
+#define REG_RD_ADDR_ser_rw_tr_dma_en 4
+#define REG_WR_ADDR_ser_rw_tr_dma_en 4
+
+/* Register rw_rec_ctrl, scope ser, type rw */
+typedef struct {
+  unsigned int base_freq   : 3;
+  unsigned int en          : 1;
+  unsigned int par         : 2;
+  unsigned int par_en      : 1;
+  unsigned int data_bits   : 1;
+  unsigned int dma_mode    : 1;
+  unsigned int dma_err     : 1;
+  unsigned int sampling    : 1;
+  unsigned int timeout     : 3;
+  unsigned int auto_eop    : 1;
+  unsigned int half_duplex : 1;
+  unsigned int rts_n       : 1;
+  unsigned int loopback    : 1;
+  unsigned int dummy1      : 14;
+} reg_ser_rw_rec_ctrl;
+#define REG_RD_ADDR_ser_rw_rec_ctrl 8
+#define REG_WR_ADDR_ser_rw_rec_ctrl 8
+
+/* Register rw_tr_baud_div, scope ser, type rw */
+typedef struct {
+  unsigned int div : 16;
+  unsigned int dummy1 : 16;
+} reg_ser_rw_tr_baud_div;
+#define REG_RD_ADDR_ser_rw_tr_baud_div 12
+#define REG_WR_ADDR_ser_rw_tr_baud_div 12
+
+/* Register rw_rec_baud_div, scope ser, type rw */
+typedef struct {
+  unsigned int div : 16;
+  unsigned int dummy1 : 16;
+} reg_ser_rw_rec_baud_div;
+#define REG_RD_ADDR_ser_rw_rec_baud_div 16
+#define REG_WR_ADDR_ser_rw_rec_baud_div 16
+
+/* Register rw_xoff, scope ser, type rw */
+typedef struct {
+  unsigned int chr       : 8;
+  unsigned int automatic : 1;
+  unsigned int dummy1    : 23;
+} reg_ser_rw_xoff;
+#define REG_RD_ADDR_ser_rw_xoff 20
+#define REG_WR_ADDR_ser_rw_xoff 20
+
+/* Register rw_xoff_clr, scope ser, type rw */
+typedef struct {
+  unsigned int clr : 1;
+  unsigned int dummy1 : 31;
+} reg_ser_rw_xoff_clr;
+#define REG_RD_ADDR_ser_rw_xoff_clr 24
+#define REG_WR_ADDR_ser_rw_xoff_clr 24
+
+/* Register rw_dout, scope ser, type rw */
+typedef struct {
+  unsigned int data : 8;
+  unsigned int dummy1 : 24;
+} reg_ser_rw_dout;
+#define REG_RD_ADDR_ser_rw_dout 28
+#define REG_WR_ADDR_ser_rw_dout 28
+
+/* Register rs_stat_din, scope ser, type rs */
+typedef struct {
+  unsigned int data        : 8;
+  unsigned int dummy1      : 8;
+  unsigned int dav         : 1;
+  unsigned int framing_err : 1;
+  unsigned int par_err     : 1;
+  unsigned int orun        : 1;
+  unsigned int rec_err     : 1;
+  unsigned int rxd         : 1;
+  unsigned int tr_idle     : 1;
+  unsigned int tr_empty    : 1;
+  unsigned int tr_rdy      : 1;
+  unsigned int cts_n       : 1;
+  unsigned int xoff_detect : 1;
+  unsigned int rts_n       : 1;
+  unsigned int txd         : 1;
+  unsigned int dummy2      : 3;
+} reg_ser_rs_stat_din;
+#define REG_RD_ADDR_ser_rs_stat_din 32
+
+/* Register r_stat_din, scope ser, type r */
+typedef struct {
+  unsigned int data        : 8;
+  unsigned int dummy1      : 8;
+  unsigned int dav         : 1;
+  unsigned int framing_err : 1;
+  unsigned int par_err     : 1;
+  unsigned int orun        : 1;
+  unsigned int rec_err     : 1;
+  unsigned int rxd         : 1;
+  unsigned int tr_idle     : 1;
+  unsigned int tr_empty    : 1;
+  unsigned int tr_rdy      : 1;
+  unsigned int cts_n       : 1;
+  unsigned int xoff_detect : 1;
+  unsigned int rts_n       : 1;
+  unsigned int txd         : 1;
+  unsigned int dummy2      : 3;
+} reg_ser_r_stat_din;
+#define REG_RD_ADDR_ser_r_stat_din 36
+
+/* Register rw_rec_eop, scope ser, type rw */
+typedef struct {
+  unsigned int set : 1;
+  unsigned int dummy1 : 31;
+} reg_ser_rw_rec_eop;
+#define REG_RD_ADDR_ser_rw_rec_eop 40
+#define REG_WR_ADDR_ser_rw_rec_eop 40
+
+/* Register rw_intr_mask, scope ser, type rw */
+typedef struct {
+  unsigned int tr_rdy   : 1;
+  unsigned int tr_empty : 1;
+  unsigned int tr_idle  : 1;
+  unsigned int dav      : 1;
+  unsigned int dummy1   : 28;
+} reg_ser_rw_intr_mask;
+#define REG_RD_ADDR_ser_rw_intr_mask 44
+#define REG_WR_ADDR_ser_rw_intr_mask 44
+
+/* Register rw_ack_intr, scope ser, type rw */
+typedef struct {
+  unsigned int tr_rdy   : 1;
+  unsigned int tr_empty : 1;
+  unsigned int tr_idle  : 1;
+  unsigned int dav      : 1;
+  unsigned int dummy1   : 28;
+} reg_ser_rw_ack_intr;
+#define REG_RD_ADDR_ser_rw_ack_intr 48
+#define REG_WR_ADDR_ser_rw_ack_intr 48
+
+/* Register r_intr, scope ser, type r */
+typedef struct {
+  unsigned int tr_rdy   : 1;
+  unsigned int tr_empty : 1;
+  unsigned int tr_idle  : 1;
+  unsigned int dav      : 1;
+  unsigned int dummy1   : 28;
+} reg_ser_r_intr;
+#define REG_RD_ADDR_ser_r_intr 52
+
+/* Register r_masked_intr, scope ser, type r */
+typedef struct {
+  unsigned int tr_rdy   : 1;
+  unsigned int tr_empty : 1;
+  unsigned int tr_idle  : 1;
+  unsigned int dav      : 1;
+  unsigned int dummy1   : 28;
+} reg_ser_r_masked_intr;
+#define REG_RD_ADDR_ser_r_masked_intr 56
+
+
+/* Constants */
+enum {
+  regk_ser_active                          = 0x00000000,
+  regk_ser_bits1                           = 0x00000000,
+  regk_ser_bits2                           = 0x00000001,
+  regk_ser_bits7                           = 0x00000001,
+  regk_ser_bits8                           = 0x00000000,
+  regk_ser_del0_5                          = 0x00000000,
+  regk_ser_del1                            = 0x00000001,
+  regk_ser_del1_5                          = 0x00000002,
+  regk_ser_del2                            = 0x00000003,
+  regk_ser_del2_5                          = 0x00000004,
+  regk_ser_del3                            = 0x00000005,
+  regk_ser_del3_5                          = 0x00000006,
+  regk_ser_del4                            = 0x00000007,
+  regk_ser_even                            = 0x00000000,
+  regk_ser_ext                             = 0x00000001,
+  regk_ser_f100                            = 0x00000007,
+  regk_ser_f29_493                         = 0x00000004,
+  regk_ser_f32                             = 0x00000005,
+  regk_ser_f32_768                         = 0x00000006,
+  regk_ser_ignore                          = 0x00000001,
+  regk_ser_inactive                        = 0x00000001,
+  regk_ser_majority                        = 0x00000001,
+  regk_ser_mark                            = 0x00000002,
+  regk_ser_middle                          = 0x00000000,
+  regk_ser_no                              = 0x00000000,
+  regk_ser_odd                             = 0x00000001,
+  regk_ser_off                             = 0x00000000,
+  regk_ser_rw_intr_mask_default            = 0x00000000,
+  regk_ser_rw_rec_baud_div_default         = 0x00000000,
+  regk_ser_rw_rec_ctrl_default             = 0x00010000,
+  regk_ser_rw_tr_baud_div_default          = 0x00000000,
+  regk_ser_rw_tr_ctrl_default              = 0x00008000,
+  regk_ser_rw_tr_dma_en_default            = 0x00000000,
+  regk_ser_rw_xoff_default                 = 0x00000000,
+  regk_ser_space                           = 0x00000003,
+  regk_ser_stop                            = 0x00000000,
+  regk_ser_yes                             = 0x00000001
+};
+#endif /* __ser_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/sser_defs.h b/include/asm-cris/arch-v32/hwregs/sser_defs.h
new file mode 100644
index 00000000000..8d1dab218b9
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/sser_defs.h
@@ -0,0 +1,331 @@
+#ifndef __sser_defs_h
+#define __sser_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/syncser/rtl/sser_regs.r
+ *     id:           sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp
+ *     last modfied: Mon Apr 11 16:09:48 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile sser_defs.h ../../inst/syncser/rtl/sser_regs.r
+ *      id: $Id: sser_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope sser */
+
+/* Register rw_cfg, scope sser, type rw */
+typedef struct {
+  unsigned int clk_div      : 16;
+  unsigned int base_freq    : 3;
+  unsigned int gate_clk     : 1;
+  unsigned int clkgate_ctrl : 1;
+  unsigned int clkgate_in   : 1;
+  unsigned int clk_dir      : 1;
+  unsigned int clk_od_mode  : 1;
+  unsigned int out_clk_pol  : 1;
+  unsigned int out_clk_src  : 2;
+  unsigned int clk_in_sel   : 1;
+  unsigned int hold_pol     : 1;
+  unsigned int prepare      : 1;
+  unsigned int en           : 1;
+  unsigned int dummy1       : 1;
+} reg_sser_rw_cfg;
+#define REG_RD_ADDR_sser_rw_cfg 0
+#define REG_WR_ADDR_sser_rw_cfg 0
+
+/* Register rw_frm_cfg, scope sser, type rw */
+typedef struct {
+  unsigned int wordrate       : 10;
+  unsigned int rec_delay      : 3;
+  unsigned int tr_delay       : 3;
+  unsigned int early_wend     : 1;
+  unsigned int level          : 2;
+  unsigned int type           : 1;
+  unsigned int clk_pol        : 1;
+  unsigned int fr_in_rxclk    : 1;
+  unsigned int clk_src        : 1;
+  unsigned int out_off        : 1;
+  unsigned int out_on         : 1;
+  unsigned int frame_pin_dir  : 1;
+  unsigned int frame_pin_use  : 2;
+  unsigned int status_pin_dir : 1;
+  unsigned int status_pin_use : 2;
+  unsigned int dummy1         : 1;
+} reg_sser_rw_frm_cfg;
+#define REG_RD_ADDR_sser_rw_frm_cfg 4
+#define REG_WR_ADDR_sser_rw_frm_cfg 4
+
+/* Register rw_tr_cfg, scope sser, type rw */
+typedef struct {
+  unsigned int tr_en          : 1;
+  unsigned int stop           : 1;
+  unsigned int urun_stop      : 1;
+  unsigned int eop_stop       : 1;
+  unsigned int sample_size    : 6;
+  unsigned int sh_dir         : 1;
+  unsigned int clk_pol        : 1;
+  unsigned int clk_src        : 1;
+  unsigned int use_dma        : 1;
+  unsigned int mode           : 2;
+  unsigned int frm_src        : 1;
+  unsigned int use60958       : 1;
+  unsigned int iec60958_ckdiv : 2;
+  unsigned int rate_ctrl      : 1;
+  unsigned int use_md         : 1;
+  unsigned int dual_i2s       : 1;
+  unsigned int data_pin_use   : 2;
+  unsigned int od_mode        : 1;
+  unsigned int bulk_wspace    : 2;
+  unsigned int dummy1         : 4;
+} reg_sser_rw_tr_cfg;
+#define REG_RD_ADDR_sser_rw_tr_cfg 8
+#define REG_WR_ADDR_sser_rw_tr_cfg 8
+
+/* Register rw_rec_cfg, scope sser, type rw */
+typedef struct {
+  unsigned int rec_en          : 1;
+  unsigned int force_eop       : 1;
+  unsigned int stop            : 1;
+  unsigned int orun_stop       : 1;
+  unsigned int eop_stop        : 1;
+  unsigned int sample_size     : 6;
+  unsigned int sh_dir          : 1;
+  unsigned int clk_pol         : 1;
+  unsigned int clk_src         : 1;
+  unsigned int use_dma         : 1;
+  unsigned int mode            : 2;
+  unsigned int frm_src         : 2;
+  unsigned int use60958        : 1;
+  unsigned int iec60958_ui_len : 5;
+  unsigned int slave2_en       : 1;
+  unsigned int slave3_en       : 1;
+  unsigned int fifo_thr        : 2;
+  unsigned int dummy1          : 3;
+} reg_sser_rw_rec_cfg;
+#define REG_RD_ADDR_sser_rw_rec_cfg 12
+#define REG_WR_ADDR_sser_rw_rec_cfg 12
+
+/* Register rw_tr_data, scope sser, type rw */
+typedef struct {
+  unsigned int data : 16;
+  unsigned int md   : 1;
+  unsigned int dummy1 : 15;
+} reg_sser_rw_tr_data;
+#define REG_RD_ADDR_sser_rw_tr_data 16
+#define REG_WR_ADDR_sser_rw_tr_data 16
+
+/* Register r_rec_data, scope sser, type r */
+typedef struct {
+  unsigned int data      : 16;
+  unsigned int md        : 1;
+  unsigned int ext_clk   : 1;
+  unsigned int status_in : 1;
+  unsigned int frame_in  : 1;
+  unsigned int din       : 1;
+  unsigned int data_in   : 1;
+  unsigned int clk_in    : 1;
+  unsigned int dummy1    : 9;
+} reg_sser_r_rec_data;
+#define REG_RD_ADDR_sser_r_rec_data 20
+
+/* Register rw_extra, scope sser, type rw */
+typedef struct {
+  unsigned int clkoff_cycles : 20;
+  unsigned int clkoff_en     : 1;
+  unsigned int clkon_en      : 1;
+  unsigned int dout_delay    : 5;
+  unsigned int dummy1        : 5;
+} reg_sser_rw_extra;
+#define REG_RD_ADDR_sser_rw_extra 24
+#define REG_WR_ADDR_sser_rw_extra 24
+
+/* Register rw_intr_mask, scope sser, type rw */
+typedef struct {
+  unsigned int trdy    : 1;
+  unsigned int rdav    : 1;
+  unsigned int tidle   : 1;
+  unsigned int rstop   : 1;
+  unsigned int urun    : 1;
+  unsigned int orun    : 1;
+  unsigned int md_rec  : 1;
+  unsigned int md_sent : 1;
+  unsigned int r958err : 1;
+  unsigned int dummy1  : 23;
+} reg_sser_rw_intr_mask;
+#define REG_RD_ADDR_sser_rw_intr_mask 28
+#define REG_WR_ADDR_sser_rw_intr_mask 28
+
+/* Register rw_ack_intr, scope sser, type rw */
+typedef struct {
+  unsigned int trdy    : 1;
+  unsigned int rdav    : 1;
+  unsigned int tidle   : 1;
+  unsigned int rstop   : 1;
+  unsigned int urun    : 1;
+  unsigned int orun    : 1;
+  unsigned int md_rec  : 1;
+  unsigned int md_sent : 1;
+  unsigned int r958err : 1;
+  unsigned int dummy1  : 23;
+} reg_sser_rw_ack_intr;
+#define REG_RD_ADDR_sser_rw_ack_intr 32
+#define REG_WR_ADDR_sser_rw_ack_intr 32
+
+/* Register r_intr, scope sser, type r */
+typedef struct {
+  unsigned int trdy    : 1;
+  unsigned int rdav    : 1;
+  unsigned int tidle   : 1;
+  unsigned int rstop   : 1;
+  unsigned int urun    : 1;
+  unsigned int orun    : 1;
+  unsigned int md_rec  : 1;
+  unsigned int md_sent : 1;
+  unsigned int r958err : 1;
+  unsigned int dummy1  : 23;
+} reg_sser_r_intr;
+#define REG_RD_ADDR_sser_r_intr 36
+
+/* Register r_masked_intr, scope sser, type r */
+typedef struct {
+  unsigned int trdy    : 1;
+  unsigned int rdav    : 1;
+  unsigned int tidle   : 1;
+  unsigned int rstop   : 1;
+  unsigned int urun    : 1;
+  unsigned int orun    : 1;
+  unsigned int md_rec  : 1;
+  unsigned int md_sent : 1;
+  unsigned int r958err : 1;
+  unsigned int dummy1  : 23;
+} reg_sser_r_masked_intr;
+#define REG_RD_ADDR_sser_r_masked_intr 40
+
+
+/* Constants */
+enum {
+  regk_sser_both                           = 0x00000002,
+  regk_sser_bulk                           = 0x00000001,
+  regk_sser_clk100                         = 0x00000000,
+  regk_sser_clk_in                         = 0x00000000,
+  regk_sser_const0                         = 0x00000003,
+  regk_sser_dout                           = 0x00000002,
+  regk_sser_edge                           = 0x00000000,
+  regk_sser_ext                            = 0x00000001,
+  regk_sser_ext_clk                        = 0x00000001,
+  regk_sser_f100                           = 0x00000000,
+  regk_sser_f29_493                        = 0x00000004,
+  regk_sser_f32                            = 0x00000005,
+  regk_sser_f32_768                        = 0x00000006,
+  regk_sser_frm                            = 0x00000003,
+  regk_sser_gio0                           = 0x00000000,
+  regk_sser_gio1                           = 0x00000001,
+  regk_sser_hispeed                        = 0x00000001,
+  regk_sser_hold                           = 0x00000002,
+  regk_sser_in                             = 0x00000000,
+  regk_sser_inf                            = 0x00000003,
+  regk_sser_intern                         = 0x00000000,
+  regk_sser_intern_clk                     = 0x00000001,
+  regk_sser_intern_tb                      = 0x00000000,
+  regk_sser_iso                            = 0x00000000,
+  regk_sser_level                          = 0x00000001,
+  regk_sser_lospeed                        = 0x00000000,
+  regk_sser_lsbfirst                       = 0x00000000,
+  regk_sser_msbfirst                       = 0x00000001,
+  regk_sser_neg                            = 0x00000001,
+  regk_sser_neg_lo                         = 0x00000000,
+  regk_sser_no                             = 0x00000000,
+  regk_sser_no_clk                         = 0x00000007,
+  regk_sser_nojitter                       = 0x00000002,
+  regk_sser_out                            = 0x00000001,
+  regk_sser_pos                            = 0x00000000,
+  regk_sser_pos_hi                         = 0x00000001,
+  regk_sser_rec                            = 0x00000000,
+  regk_sser_rw_cfg_default                 = 0x00000000,
+  regk_sser_rw_extra_default               = 0x00000000,
+  regk_sser_rw_frm_cfg_default             = 0x00000000,
+  regk_sser_rw_intr_mask_default           = 0x00000000,
+  regk_sser_rw_rec_cfg_default             = 0x00000000,
+  regk_sser_rw_tr_cfg_default              = 0x01800000,
+  regk_sser_rw_tr_data_default             = 0x00000000,
+  regk_sser_thr16                          = 0x00000001,
+  regk_sser_thr32                          = 0x00000002,
+  regk_sser_thr8                           = 0x00000000,
+  regk_sser_tr                             = 0x00000001,
+  regk_sser_ts_out                         = 0x00000003,
+  regk_sser_tx_bulk                        = 0x00000002,
+  regk_sser_wiresave                       = 0x00000002,
+  regk_sser_yes                            = 0x00000001
+};
+#endif /* __sser_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/strcop.h b/include/asm-cris/arch-v32/hwregs/strcop.h
new file mode 100644
index 00000000000..35131ba466f
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/strcop.h
@@ -0,0 +1,57 @@
+// $Id: strcop.h,v 1.3 2003/10/22 13:27:12 henriken Exp $
+
+// Streamcop meta-data configuration structs
+
+struct strcop_meta_out {
+	unsigned char  csumsel  : 3;
+	unsigned char  ciphsel  : 3;
+	unsigned char  ciphconf : 2;
+	unsigned char  hashsel  : 3;
+	unsigned char  hashconf : 1;
+	unsigned char  hashmode : 1;
+	unsigned char  decrypt  : 1;
+	unsigned char  dlkey    : 1;
+	unsigned char  cbcmode  : 1;
+};
+
+struct strcop_meta_in {
+	unsigned char  dmasel     : 3;
+	unsigned char  sync       : 1;
+	unsigned char  res1       : 5;
+	unsigned char  res2;
+};
+
+// Source definitions
+
+enum {
+	src_none = 0,
+	src_dma  = 1,
+	src_des  = 2,
+	src_sha1 = 3,
+	src_csum = 4,
+	src_aes  = 5,
+	src_md5  = 6,
+	src_res  = 7
+};
+
+// Cipher definitions
+
+enum {
+	ciph_des = 0,
+	ciph_3des = 1,
+	ciph_aes = 2
+};
+
+// Hash definitions
+
+enum {
+	hash_sha1 = 0,
+	hash_md5 = 1
+};
+
+enum {
+	hash_noiv = 0,
+	hash_iv = 1
+};
+
+
diff --git a/include/asm-cris/arch-v32/hwregs/strcop_defs.h b/include/asm-cris/arch-v32/hwregs/strcop_defs.h
new file mode 100644
index 00000000000..bd145a49b2c
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/strcop_defs.h
@@ -0,0 +1,109 @@
+#ifndef __strcop_defs_h
+#define __strcop_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/strcop/rtl/strcop_regs.r
+ *     id:           strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp
+ *     last modfied: Mon Apr 11 16:09:38 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile strcop_defs.h ../../inst/strcop/rtl/strcop_regs.r
+ *      id: $Id: strcop_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope strcop */
+
+/* Register rw_cfg, scope strcop, type rw */
+typedef struct {
+  unsigned int td3         : 1;
+  unsigned int td2         : 1;
+  unsigned int td1         : 1;
+  unsigned int ipend       : 1;
+  unsigned int ignore_sync : 1;
+  unsigned int en          : 1;
+  unsigned int dummy1      : 26;
+} reg_strcop_rw_cfg;
+#define REG_RD_ADDR_strcop_rw_cfg 0
+#define REG_WR_ADDR_strcop_rw_cfg 0
+
+
+/* Constants */
+enum {
+  regk_strcop_big                          = 0x00000001,
+  regk_strcop_d                            = 0x00000001,
+  regk_strcop_e                            = 0x00000000,
+  regk_strcop_little                       = 0x00000000,
+  regk_strcop_rw_cfg_default               = 0x00000002
+};
+#endif /* __strcop_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/strmux_defs.h b/include/asm-cris/arch-v32/hwregs/strmux_defs.h
new file mode 100644
index 00000000000..67474855c49
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/strmux_defs.h
@@ -0,0 +1,127 @@
+#ifndef __strmux_defs_h
+#define __strmux_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/strmux/rtl/guinness/strmux_regs.r
+ *     id:           strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp
+ *     last modfied: Mon Apr 11 16:09:43 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r
+ *      id: $Id: strmux_defs.h,v 1.5 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope strmux */
+
+/* Register rw_cfg, scope strmux, type rw */
+typedef struct {
+  unsigned int dma0 : 3;
+  unsigned int dma1 : 3;
+  unsigned int dma2 : 3;
+  unsigned int dma3 : 3;
+  unsigned int dma4 : 3;
+  unsigned int dma5 : 3;
+  unsigned int dma6 : 3;
+  unsigned int dma7 : 3;
+  unsigned int dma8 : 3;
+  unsigned int dma9 : 3;
+  unsigned int dummy1 : 2;
+} reg_strmux_rw_cfg;
+#define REG_RD_ADDR_strmux_rw_cfg 0
+#define REG_WR_ADDR_strmux_rw_cfg 0
+
+
+/* Constants */
+enum {
+  regk_strmux_ata                          = 0x00000003,
+  regk_strmux_eth0                         = 0x00000001,
+  regk_strmux_eth1                         = 0x00000004,
+  regk_strmux_ext0                         = 0x00000001,
+  regk_strmux_ext1                         = 0x00000001,
+  regk_strmux_ext2                         = 0x00000001,
+  regk_strmux_ext3                         = 0x00000001,
+  regk_strmux_iop0                         = 0x00000002,
+  regk_strmux_iop1                         = 0x00000001,
+  regk_strmux_off                          = 0x00000000,
+  regk_strmux_p21                          = 0x00000004,
+  regk_strmux_rw_cfg_default               = 0x00000000,
+  regk_strmux_ser0                         = 0x00000002,
+  regk_strmux_ser1                         = 0x00000002,
+  regk_strmux_ser2                         = 0x00000004,
+  regk_strmux_ser3                         = 0x00000003,
+  regk_strmux_sser0                        = 0x00000003,
+  regk_strmux_sser1                        = 0x00000003,
+  regk_strmux_strcop                       = 0x00000002
+};
+#endif /* __strmux_defs_h */
diff --git a/include/asm-cris/arch-v32/hwregs/supp_reg.h b/include/asm-cris/arch-v32/hwregs/supp_reg.h
new file mode 100644
index 00000000000..ffe49625ae3
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/supp_reg.h
@@ -0,0 +1,78 @@
+#ifndef __SUPP_REG_H__
+#define __SUPP_REG_H__
+
+/* Macros for reading and writing support/special registers. */
+
+#ifndef STRINGIFYFY
+#define STRINGIFYFY(i) #i
+#endif
+
+#ifndef STRINGIFY
+#define STRINGIFY(i) STRINGIFYFY(i)
+#endif
+
+#define SPEC_REG_BZ     "BZ"
+#define SPEC_REG_VR     "VR"
+#define SPEC_REG_PID    "PID"
+#define SPEC_REG_SRS    "SRS"
+#define SPEC_REG_WZ     "WZ"
+#define SPEC_REG_EXS    "EXS"
+#define SPEC_REG_EDA    "EDA"
+#define SPEC_REG_MOF    "MOF"
+#define SPEC_REG_DZ     "DZ"
+#define SPEC_REG_EBP    "EBP"
+#define SPEC_REG_ERP    "ERP"
+#define SPEC_REG_SRP    "SRP"
+#define SPEC_REG_NRP    "NRP"
+#define SPEC_REG_CCS    "CCS"
+#define SPEC_REG_USP    "USP"
+#define SPEC_REG_SPC    "SPC"
+
+#define RW_MM_CFG       0
+#define RW_MM_KBASE_LO  1
+#define RW_MM_KBASE_HI  2
+#define RW_MM_CAUSE     3
+#define RW_MM_TLB_SEL   4
+#define RW_MM_TLB_LO    5
+#define RW_MM_TLB_HI    6
+#define RW_MM_TLB_PGD   7
+
+#define BANK_GC		0
+#define BANK_IM		1
+#define BANK_DM		2
+#define BANK_BP		3
+
+#define RW_GC_CFG       0
+#define RW_GC_CCS       1
+#define RW_GC_SRS       2
+#define RW_GC_NRP       3
+#define RW_GC_EXS       4
+#define RW_GC_R0        8
+#define RW_GC_R1        9
+
+#define SPEC_REG_WR(r,v) \
+__asm__ __volatile__ ("move %0, $" r : : "r" (v));
+
+#define SPEC_REG_RD(r,v) \
+__asm__ __volatile__ ("move $" r ",%0" : "=r" (v));
+
+#define NOP() \
+	__asm__ __volatile__ ("nop");
+
+#define SUPP_BANK_SEL(b) 		\
+	SPEC_REG_WR(SPEC_REG_SRS,b);	\
+	NOP();				\
+	NOP();				\
+	NOP();
+
+#define SUPP_REG_WR(r,v) \
+__asm__ __volatile__ ("move %0, $S" STRINGIFYFY(r) "\n\t"	\
+		      "nop\n\t"					\
+		      "nop\n\t"					\
+		      "nop\n\t"					\
+		      : : "r" (v));
+
+#define SUPP_REG_RD(r,v) \
+__asm__ __volatile__ ("move $S" STRINGIFYFY(r) ",%0" : "=r" (v));
+
+#endif /* __SUPP_REG_H__ */
diff --git a/include/asm-cris/arch-v32/hwregs/timer_defs.h b/include/asm-cris/arch-v32/hwregs/timer_defs.h
new file mode 100644
index 00000000000..20c8c89ec07
--- /dev/null
+++ b/include/asm-cris/arch-v32/hwregs/timer_defs.h
@@ -0,0 +1,266 @@
+#ifndef __timer_defs_h
+#define __timer_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ../../inst/timer/rtl/timer_regs.r
+ *     id:           timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
+ *     last modfied: Mon Apr 11 16:09:53 2005
+ *
+ *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r
+ *      id: $Id: timer_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope timer */
+
+/* Register rw_tmr0_div, scope timer, type rw */
+typedef unsigned int reg_timer_rw_tmr0_div;
+#define REG_RD_ADDR_timer_rw_tmr0_div 0
+#define REG_WR_ADDR_timer_rw_tmr0_div 0
+
+/* Register r_tmr0_data, scope timer, type r */
+typedef unsigned int reg_timer_r_tmr0_data;
+#define REG_RD_ADDR_timer_r_tmr0_data 4
+
+/* Register rw_tmr0_ctrl, scope timer, type rw */
+typedef struct {
+  unsigned int op   : 2;
+  unsigned int freq : 3;
+  unsigned int dummy1 : 27;
+} reg_timer_rw_tmr0_ctrl;
+#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8
+#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8
+
+/* Register rw_tmr1_div, scope timer, type rw */
+typedef unsigned int reg_timer_rw_tmr1_div;
+#define REG_RD_ADDR_timer_rw_tmr1_div 16
+#define REG_WR_ADDR_timer_rw_tmr1_div 16
+
+/* Register r_tmr1_data, scope timer, type r */
+typedef unsigned int reg_timer_r_tmr1_data;
+#define REG_RD_ADDR_timer_r_tmr1_data 20
+
+/* Register rw_tmr1_ctrl, scope timer, type rw */
+typedef struct {
+  unsigned int op   : 2;
+  unsigned int freq : 3;
+  unsigned int dummy1 : 27;
+} reg_timer_rw_tmr1_ctrl;
+#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24
+#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24
+
+/* Register rs_cnt_data, scope timer, type rs */
+typedef struct {
+  unsigned int tmr : 24;
+  unsigned int cnt : 8;
+} reg_timer_rs_cnt_data;
+#define REG_RD_ADDR_timer_rs_cnt_data 32
+
+/* Register r_cnt_data, scope timer, type r */
+typedef struct {
+  unsigned int tmr : 24;
+  unsigned int cnt : 8;
+} reg_timer_r_cnt_data;
+#define REG_RD_ADDR_timer_r_cnt_data 36
+
+/* Register rw_cnt_cfg, scope timer, type rw */
+typedef struct {
+  unsigned int clk : 2;
+  unsigned int dummy1 : 30;
+} reg_timer_rw_cnt_cfg;
+#define REG_RD_ADDR_timer_rw_cnt_cfg 40
+#define REG_WR_ADDR_timer_rw_cnt_cfg 40
+
+/* Register rw_trig, scope timer, type rw */
+typedef unsigned int reg_timer_rw_trig;
+#define REG_RD_ADDR_timer_rw_trig 48
+#define REG_WR_ADDR_timer_rw_trig 48
+
+/* Register rw_trig_cfg, scope timer, type rw */
+typedef struct {
+  unsigned int tmr : 2;
+  unsigned int dummy1 : 30;
+} reg_timer_rw_trig_cfg;
+#define REG_RD_ADDR_timer_rw_trig_cfg 52
+#define REG_WR_ADDR_timer_rw_trig_cfg 52
+
+/* Register r_time, scope timer, type r */
+typedef unsigned int reg_timer_r_time;
+#define REG_RD_ADDR_timer_r_time 56
+
+/* Register rw_out, scope timer, type rw */
+typedef struct {
+  unsigned int tmr : 2;
+  unsigned int dummy1 : 30;
+} reg_timer_rw_out;
+#define REG_RD_ADDR_timer_rw_out 60
+#define REG_WR_ADDR_timer_rw_out 60
+
+/* Register rw_wd_ctrl, scope timer, type rw */
+typedef struct {
+  unsigned int cnt : 8;
+  unsigned int cmd : 1;
+  unsigned int key : 7;
+  unsigned int dummy1 : 16;
+} reg_timer_rw_wd_ctrl;
+#define REG_RD_ADDR_timer_rw_wd_ctrl 64
+#define REG_WR_ADDR_timer_rw_wd_ctrl 64
+
+/* Register r_wd_stat, scope timer, type r */
+typedef struct {
+  unsigned int cnt : 8;
+  unsigned int cmd : 1;
+  unsigned int dummy1 : 23;
+} reg_timer_r_wd_stat;
+#define REG_RD_ADDR_timer_r_wd_stat 68
+
+/* Register rw_intr_mask, scope timer, type rw */
+typedef struct {
+  unsigned int tmr0 : 1;
+  unsigned int tmr1 : 1;
+  unsigned int cnt  : 1;
+  unsigned int trig : 1;
+  unsigned int dummy1 : 28;
+} reg_timer_rw_intr_mask;
+#define REG_RD_ADDR_timer_rw_intr_mask 72
+#define REG_WR_ADDR_timer_rw_intr_mask 72
+
+/* Register rw_ack_intr, scope timer, type rw */
+typedef struct {
+  unsigned int tmr0 : 1;
+  unsigned int tmr1 : 1;
+  unsigned int cnt  : 1;
+  unsigned int trig : 1;
+  unsigned int dummy1 : 28;
+} reg_timer_rw_ack_intr;
+#define REG_RD_ADDR_timer_rw_ack_intr 76
+#define REG_WR_ADDR_timer_rw_ack_intr 76
+
+/* Register r_intr, scope timer, type r */
+typedef struct {
+  unsigned int tmr0 : 1;
+  unsigned int tmr1 : 1;
+  unsigned int cnt  : 1;
+  unsigned int trig : 1;
+  unsigned int dummy1 : 28;
+} reg_timer_r_intr;
+#define REG_RD_ADDR_timer_r_intr 80
+
+/* Register r_masked_intr, scope timer, type r */
+typedef struct {
+  unsigned int tmr0 : 1;
+  unsigned int tmr1 : 1;
+  unsigned int cnt  : 1;
+  unsigned int trig : 1;
+  unsigned int dummy1 : 28;
+} reg_timer_r_masked_intr;
+#define REG_RD_ADDR_timer_r_masked_intr 84
+
+/* Register rw_test, scope timer, type rw */
+typedef struct {
+  unsigned int dis : 1;
+  unsigned int en  : 1;
+  unsigned int dummy1 : 30;
+} reg_timer_rw_test;
+#define REG_RD_ADDR_timer_rw_test 88
+#define REG_WR_ADDR_timer_rw_test 88
+
+
+/* Constants */
+enum {
+  regk_timer_ext                           = 0x00000001,
+  regk_timer_f100                          = 0x00000007,
+  regk_timer_f29_493                       = 0x00000004,
+  regk_timer_f32                           = 0x00000005,
+  regk_timer_f32_768                       = 0x00000006,
+  regk_timer_hold                          = 0x00000001,
+  regk_timer_ld                            = 0x00000000,
+  regk_timer_no                            = 0x00000000,
+  regk_timer_off                           = 0x00000000,
+  regk_timer_run                           = 0x00000002,
+  regk_timer_rw_cnt_cfg_default            = 0x00000000,
+  regk_timer_rw_intr_mask_default          = 0x00000000,
+  regk_timer_rw_out_default                = 0x00000000,
+  regk_timer_rw_test_default               = 0x00000000,
+  regk_timer_rw_tmr0_ctrl_default          = 0x00000000,
+  regk_timer_rw_tmr1_ctrl_default          = 0x00000000,
+  regk_timer_rw_trig_cfg_default           = 0x00000000,
+  regk_timer_start                         = 0x00000001,
+  regk_timer_stop                          = 0x00000000,
+  regk_timer_time                          = 0x00000001,
+  regk_timer_tmr0                          = 0x00000002,
+  regk_timer_tmr1                          = 0x00000003,
+  regk_timer_yes                           = 0x00000001
+};
+#endif /* __timer_defs_h */
diff --git a/include/asm-cris/arch-v32/ide.h b/include/asm-cris/arch-v32/ide.h
new file mode 100644
index 00000000000..24f5604f566
--- /dev/null
+++ b/include/asm-cris/arch-v32/ide.h
@@ -0,0 +1,61 @@
+/*
+ *  linux/include/asm-cris/ide.h
+ *
+ *  Copyright (C) 2000-2004  Axis Communications AB
+ *
+ *  Authors:    Bjorn Wesen, Mikael Starvik
+ *
+ */
+
+/*
+ *  This file contains the ETRAX FS specific IDE code.
+ */
+
+#ifndef __ASMCRIS_IDE_H
+#define __ASMCRIS_IDE_H
+
+#ifdef __KERNEL__
+
+#include <asm/arch/hwregs/intr_vect.h>
+#include <asm/arch/hwregs/ata_defs.h>
+#include <asm/io.h>
+#include <asm-generic/ide_iops.h>
+
+
+/* ETRAX FS can support 4 IDE busses on the same pins (serialized) */
+
+#define MAX_HWIFS	4
+
+extern __inline__ int ide_default_irq(unsigned long base)
+{
+	/* all IDE busses share the same IRQ,
+	 * this has the side-effect that ide-probe.c will cluster our 4 interfaces
+	 * together in a hwgroup, and will serialize accesses. this is good, because
+	 * we can't access more than one interface at the same time on ETRAX100.
+	 */
+	return ATA_INTR_VECT;
+}
+
+extern __inline__ unsigned long ide_default_io_base(int index)
+{
+	reg_ata_rw_ctrl2 ctrl2 = {.sel = index};
+	/* we have no real I/O base address per interface, since all go through the
+	 * same register. but in a bitfield in that register, we have the i/f number.
+	 * so we can use the io_base to remember that bitfield.
+	 */
+        ctrl2.sel = index;
+
+	return REG_TYPE_CONV(unsigned long, reg_ata_rw_ctrl2, ctrl2);
+}
+
+/* some configuration options we don't need */
+
+#undef SUPPORT_VLB_SYNC
+#define SUPPORT_VLB_SYNC 0
+
+#define IDE_ARCH_ACK_INTR
+#define ide_ack_intr(hwif)	(hwif)->hw.ack_intr(hwif)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASMCRIS_IDE_H */
diff --git a/include/asm-cris/arch-v32/intmem.h b/include/asm-cris/arch-v32/intmem.h
new file mode 100644
index 00000000000..c0ada33bf90
--- /dev/null
+++ b/include/asm-cris/arch-v32/intmem.h
@@ -0,0 +1,9 @@
+#ifndef _ASM_CRIS_INTMEM_H
+#define _ASM_CRIS_INTMEM_H
+
+void* crisv32_intmem_alloc(unsigned size, unsigned align);
+void crisv32_intmem_free(void* addr);
+void* crisv32_intmem_phys_to_virt(unsigned long addr);
+unsigned long crisv32_intmem_virt_to_phys(void *addr);
+
+#endif /* _ASM_CRIS_ARCH_INTMEM_H */
diff --git a/include/asm-cris/arch-v32/io.h b/include/asm-cris/arch-v32/io.h
new file mode 100644
index 00000000000..4c80263ec63
--- /dev/null
+++ b/include/asm-cris/arch-v32/io.h
@@ -0,0 +1,98 @@
+#ifndef _ASM_ARCH_CRIS_IO_H
+#define _ASM_ARCH_CRIS_IO_H
+
+#include <asm/arch/hwregs/reg_map.h>
+#include <asm/arch/hwregs/reg_rdwr.h>
+#include <asm/arch/hwregs/gio_defs.h>
+#include <linux/config.h>
+
+enum crisv32_io_dir
+{
+  crisv32_io_dir_in = 0,
+  crisv32_io_dir_out = 1
+};
+
+struct crisv32_ioport
+{
+  unsigned long* oe;
+  unsigned long* data;
+  unsigned long* data_in;
+  unsigned int pin_count;
+};
+
+struct crisv32_iopin
+{
+  struct crisv32_ioport* port;
+  int bit;
+};
+
+extern struct crisv32_ioport crisv32_ioports[];
+
+extern struct crisv32_iopin crisv32_led1_green;
+extern struct crisv32_iopin crisv32_led1_red;
+extern struct crisv32_iopin crisv32_led2_green;
+extern struct crisv32_iopin crisv32_led2_red;
+extern struct crisv32_iopin crisv32_led3_green;
+extern struct crisv32_iopin crisv32_led3_red;
+
+extern inline void crisv32_io_set(struct crisv32_iopin* iopin,
+			   int val)
+{
+	if (val)
+		*iopin->port->data |= iopin->bit;
+	else
+		*iopin->port->data &= ~iopin->bit;
+}
+
+extern inline void crisv32_io_set_dir(struct crisv32_iopin* iopin,
+			       enum crisv32_io_dir dir)
+{
+	if (dir == crisv32_io_dir_in)
+		*iopin->port->oe &= ~iopin->bit;
+	else
+		*iopin->port->oe |= iopin->bit;
+}
+
+extern inline int crisv32_io_rd(struct crisv32_iopin* iopin)
+{
+	return ((*iopin->port->data_in & iopin->bit) ? 1 : 0);
+}
+
+int crisv32_io_get(struct crisv32_iopin* iopin,
+                   unsigned int port, unsigned int pin);
+int crisv32_io_get_name(struct crisv32_iopin* iopin,
+                         char* name);
+
+#define LED_OFF    0x00
+#define LED_GREEN  0x01
+#define LED_RED    0x02
+#define LED_ORANGE (LED_GREEN | LED_RED)
+
+#define LED_NETWORK_SET(x)                          \
+	do {                                        \
+		LED_NETWORK_SET_G((x) & LED_GREEN); \
+		LED_NETWORK_SET_R((x) & LED_RED);   \
+	} while (0)
+#define LED_ACTIVE_SET(x)                           \
+	do {                                        \
+		LED_ACTIVE_SET_G((x) & LED_GREEN);  \
+		LED_ACTIVE_SET_R((x) & LED_RED);    \
+	} while (0)
+
+#define LED_NETWORK_SET_G(x) \
+	crisv32_io_set(&crisv32_led1_green, !(x));
+#define LED_NETWORK_SET_R(x) \
+	crisv32_io_set(&crisv32_led1_red, !(x));
+#define LED_ACTIVE_SET_G(x) \
+	crisv32_io_set(&crisv32_led2_green, !(x));
+#define LED_ACTIVE_SET_R(x) \
+	crisv32_io_set(&crisv32_led2_red, !(x));
+#define LED_DISK_WRITE(x) \
+         do{\
+		crisv32_io_set(&crisv32_led3_green, !(x)); \
+		crisv32_io_set(&crisv32_led3_red, !(x));   \
+        }while(0)
+#define LED_DISK_READ(x) \
+	crisv32_io_set(&crisv32_led3_green, !(x));
+
+#endif
diff --git a/include/asm-cris/arch-v32/irq.h b/include/asm-cris/arch-v32/irq.h
new file mode 100644
index 00000000000..d35aa8174c2
--- /dev/null
+++ b/include/asm-cris/arch-v32/irq.h
@@ -0,0 +1,120 @@
+#ifndef _ASM_ARCH_IRQ_H
+#define _ASM_ARCH_IRQ_H
+
+#include <linux/config.h>
+#include "hwregs/intr_vect.h"
+
+/* Number of non-cpu interrupts. */
+#define NR_IRQS 0x50 /* Exceptions + IRQs */
+#define NR_REAL_IRQS 0x20 /* IRQs */
+#define FIRST_IRQ 0x31 /* Exception number for first IRQ */
+
+#ifndef __ASSEMBLY__
+/* Global IRQ vector. */
+typedef void (*irqvectptr)(void);
+
+struct etrax_interrupt_vector {
+	irqvectptr v[256];
+};
+
+extern struct etrax_interrupt_vector *etrax_irv;	/* head.S */
+
+void mask_irq(int irq);
+void unmask_irq(int irq);
+
+void set_exception_vector(int n, irqvectptr addr);
+
+/* Save registers so that they match pt_regs. */
+#define SAVE_ALL \
+	"subq 12,$sp\n\t"	\
+	"move $erp,[$sp]\n\t"	\
+	"subq 4,$sp\n\t"	\
+	"move $srp,[$sp]\n\t"	\
+	"subq 4,$sp\n\t"	\
+	"move $ccs,[$sp]\n\t"	\
+	"subq 4,$sp\n\t"	\
+	"move $spc,[$sp]\n\t"	\
+	"subq 4,$sp\n\t"	\
+	"move $mof,[$sp]\n\t"	\
+	"subq 4,$sp\n\t"	\
+	"move $srs,[$sp]\n\t"	\
+	"subq 4,$sp\n\t"	\
+	"move.d $acr,[$sp]\n\t"	\
+	"subq 14*4,$sp\n\t"	\
+	"movem $r13,[$sp]\n\t"	\
+	"subq 4,$sp\n\t"	\
+	"move.d $r10,[$sp]\n"
+
+#define STR2(x) #x
+#define STR(x) STR2(x)
+
+#define IRQ_NAME2(nr) nr##_interrupt(void)
+#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
+
+/*
+ * The reason for setting the S-bit when debugging the kernel is that we want
+ * hardware breakpoints to remain active while we are in an exception handler.
+ * Note that we cannot simply copy S1, since we may come here from user-space,
+ * or any context where the S-bit wasn't set.
+ */
+#ifdef CONFIG_ETRAX_KGDB
+#define KGDB_FIXUP \
+	"move $ccs, $r10\n\t"		\
+	"or.d (1<<9), $r10\n\t"		\
+	"move $r10, $ccs\n\t"
+#else
+#define KGDB_FIXUP ""
+#endif
+
+/*
+ * Make sure the causing IRQ is blocked, then call do_IRQ. After that, unblock
+ * and jump to ret_from_intr which is found in entry.S.
+ *
+ * The reason for blocking the IRQ is to allow an sti() before the handler,
+ * which will acknowledge the interrupt, is run. The actual blocking is made
+ * by crisv32_do_IRQ.
+ */
+#define BUILD_IRQ(nr, mask)		\
+void IRQ_NAME(nr);			\
+__asm__ (				\
+	".text\n\t"			\
+	"IRQ" #nr "_interrupt:\n\t" 	\
+	SAVE_ALL			\
+	KGDB_FIXUP                      \
+	"move.d "#nr",$r10\n\t"		\
+	"move.d $sp,$r12\n\t"		\
+	"jsr crisv32_do_IRQ\n\t"       	\
+	"moveq 1, $r11\n\t"		\
+	"jump ret_from_intr\n\t"	\
+	"nop\n\t");
+/*
+ * This is subtle. The timer interrupt is crucial and it should not be disabled
+ * for too long. However, if it had been a normal interrupt as per BUILD_IRQ, it
+ * would have been BLOCK'ed, and then softirq's are run before we return here to
+ * UNBLOCK. If the softirq's take too much time to run, the timer irq won't run
+ * and the watchdog will kill us.
+ *
+ * Furthermore, if a lot of other irq's occur before we return here, the
+ * multiple_irq handler is run and it prioritizes the timer interrupt. However
+ * if we had BLOCK'edit here, we would not get the multiple_irq at all.
+ *
+ * The non-blocking here is based on the knowledge that the timer interrupt is
+ * registred as a fast interrupt (SA_INTERRUPT) so that we _know_ there will not
+ * be an sti() before the timer irq handler is run to acknowledge the interrupt.
+ */
+#define BUILD_TIMER_IRQ(nr, mask) 	\
+void IRQ_NAME(nr);			\
+__asm__ (				\
+	".text\n\t"			\
+	"IRQ" #nr "_interrupt:\n\t"	\
+	SAVE_ALL			\
+        KGDB_FIXUP                      \
+	"move.d "#nr",$r10\n\t"		\
+	"move.d $sp,$r12\n\t"		\
+	"jsr crisv32_do_IRQ\n\t"	\
+	"moveq 0,$r11\n\t"		\
+	"jump ret_from_intr\n\t"	\
+	"nop\n\t");
+
+#endif /* __ASSEMBLY__ */
+#endif /* _ASM_ARCH_IRQ_H */
diff --git a/include/asm-cris/arch-v32/juliette.h b/include/asm-cris/arch-v32/juliette.h
new file mode 100644
index 00000000000..f1f81725e57
--- /dev/null
+++ b/include/asm-cris/arch-v32/juliette.h
@@ -0,0 +1,326 @@
+#ifndef _ASM_JULIETTE_H
+#define _ASM_JULIETTE_H
+
+/* juliette _IOC_TYPE, bits 8 to 15 in ioctl cmd */
+
+#define JULIOCTYPE 42
+
+/* supported ioctl _IOC_NR's */
+
+#define JULSTARTDMA      0x1        /* start a picture asynchronously */
+
+/* set parameters */
+
+#define SETDEFAULT        0x2 /* CCD/VIDEO/SS1M */
+#define SETPARAMETERS     0x3 /* CCD/VIDEO      */
+#define SETSIZE           0x4 /* CCD/VIDEO/SS1M */
+#define SETCOMPRESSION    0x5 /* CCD/VIDEO/SS1M */
+#define SETCOLORLEVEL     0x6 /* CCD/VIDEO      */
+#define SETBRIGHTNESS     0x7 /* CCD            */
+#define SETROTATION       0x8 /* CCD            */
+#define SETTEXT           0x9 /* CCD/VIDEO/SS1M */
+#define SETCLOCK          0xa /* CCD/VIDEO/SS1M */
+#define SETDATE           0xb /* CCD/VIDEO/SS1M */
+#define SETTIMEFORMAT     0xc /* CCD/VIDEO/SS1M */
+#define SETDATEFORMAT     0xd /*     VIDEO      */
+#define SETTEXTALIGNMENT  0xe /*     VIDEO      */
+#define SETFPS            0xf /* CCD/VIDEO/SS1M */
+#define SETVGA           0xff /*     VIDEO      */
+#define SETCOMMENT       0xfe /* CCD/VIDEO      */
+
+/* get parameters */
+
+#define GETDRIVERTYPE    0x10 /* CCD/VIDEO/SS1M */
+#define GETNBROFCAMERAS  0x11 /* CCD/VIDEO/SS1M */
+#define GETPARAMETERS    0x12 /* CCD/VIDEO/SS1M */
+#define GETBUFFERSIZE    0x13 /* CCD/VIDEO/SS1M */
+#define GETVIDEOTYPE     0x14 /*     VIDEO/SS1M */
+#define GETVIDEOSIGNAL   0x15 /*     VIDEO      */
+#define GETMODULATION    0x16 /*     VIDEO      */
+#define GETDCYVALUES     0xa0 /* CCD      /SS1M */
+#define GETDCYWIDTH      0xa1 /* CCD      /SS1M */
+#define GETDCYHEIGHT     0xa2 /* CCD      /SS1M */
+#define GETSIZE          0xa3 /* CCD/VIDEO      */
+#define GETCOMPRESSION   0xa4 /* CCD/VIDEO      */
+
+/* detect and get parameters */
+
+#define DETECTMODULATION  0x17 /*     VIDEO      */
+#define DETECTVIDEOTYPE   0x18 /*     VIDEO      */
+#define DETECTVIDEOSIGNAL 0x19 /*     VIDEO      */
+
+/* configure default parameters */
+
+#define CONFIGUREDEFAULT  0x20 /* CCD/VIDEO/SS1M */
+#define DEFSIZE           0x21 /* CCD/VIDEO/SS1M */
+#define DEFCOMPRESSION    0x22 /* CCD/VIDEO/SS1M */
+#define DEFCOLORLEVEL     0x23 /* CCD/VIDEO      */
+#define DEFBRIGHTNESS     0x24 /* CCD            */
+#define DEFROTATION       0x25 /* CCD            */
+#define DEFWHITEBALANCE   0x26 /* CCD            */
+#define DEFEXPOSURE       0x27 /* CCD            */
+#define DEFAUTOEXPWINDOW  0x28 /* CCD            */
+#define DEFTEXT           0x29 /* CCD/VIDEO/SS1M */
+#define DEFCLOCK          0x2a /* CCD/VIDEO/SS1M */
+#define DEFDATE           0x2b /* CCD/VIDEO/SS1M */
+#define DEFTIMEFORMAT     0x2c /* CCD/VIDEO/SS1M */
+#define DEFDATEFORMAT     0x2d /*     VIDEO      */
+#define DEFTEXTALIGNMENT  0x2e /*     VIDEO      */
+#define DEFFPS            0x2f /* CCD/VIDEO/SS1M */
+#define DEFTEXTSTRING     0x30 /* CCD/VIDEO/SS1M */
+#define DEFHEADERINFO     0x31 /* CCD/VIDEO/SS1M */
+#define DEFWEXAR          0x32 /* CCD            */
+#define DEFLINEDELAY      0x33 /* CCD            */
+#define DEFDISABLEDVIDEO  0x34 /*     VIDEO      */
+#define DEFVIDEOTYPE      0x35 /*     VIDEO      */
+#define DEFMODULATION     0x36 /*     VIDEO      */
+#define DEFXOFFSET        0x37 /*     VIDEO      */
+#define DEFYOFFSET        0x38 /*     VIDEO      */
+#define DEFYCMODE         0x39 /*     VIDEO      */
+#define DEFVCRMODE        0x3a /*     VIDEO      */
+#define DEFSTOREDCYVALUES 0x3b /* CCD/VIDEO/SS1M */
+#define DEFWCDS           0x3c /* CCD            */
+#define DEFVGA            0x3d /*     VIDEO      */
+#define DEFCOMMENT        0x3e /* CCD/VIDEO      */
+#define DEFCOMMENTSIZE    0x3f /* CCD/VIDEO      */
+#define DEFCOMMENTTEXT    0x50 /* CCD/VIDEO      */
+#define DEFSTOREDCYTEXT   0x51 /*     VIDEO      */
+
+
+#define JULABORTDMA       0x70 /* Abort current DMA transfer */
+
+/* juliette general i/o port */
+
+#define JIO_READBITS      0x40 /* read and return current port bits */
+#define JIO_SETBITS       0x41 /* set bits marked by 1 in the argument */
+#define JIO_CLRBITS       0x42 /* clr bits marked by 1 in the argument */
+#define JIO_READDIR       0x43 /* read direction, 0=input 1=output */
+#define JIO_SETINPUT      0x44 /* set direction, 0=unchanged 1=input
+                                  returns current dir */
+#define JIO_SETOUTPUT     0x45 /* set direction, 0=unchanged 1=output
+                                  returns current dir */
+
+/**** YumYum internal adresses ****/
+
+/* Juliette buffer addresses */
+
+#define BUFFER1_VIDEO   0x1100
+#define BUFFER2_VIDEO   0x2800
+#define ACDC_BUFF_VIDEO 0x0aaa
+#define BUFFER1         0x1700
+#define BUFFER2         0x2b01
+#define ACDC_BUFFER     0x1200
+#define BUFFER1_SS1M    0x1100
+#define BUFFER2_SS1M    0x2800
+#define ACDC_BUFF_SS1M  0x0900
+
+/* Juliette parameter memory addresses */
+
+#define PA_BUFFER_CNT     0x3f09 /* CCD/VIDEO */
+#define PA_CCD_BUFFER     0x3f10 /* CCD       */
+#define PA_VIDEO_BUFFER   0x3f10 /*     VIDEO */
+#define PA_DCT_BUFFER     0x3f11 /* CCD/VIDEO */
+#define PA_TEMP           0x3f12 /* CCD/VIDEO */
+#define PA_VIDEOLINE_RD   0x3f13 /*     VIDEO */
+#define PA_VIDEOLINE_WR   0x3f14 /*     VIDEO */
+#define PA_VI_HDELAY0     0x3f15 /*     VIDEO */
+#define PA_VI_VDELAY0     0x3f16 /*     VIDEO */
+#define PA_VI_HDELAY1     0x3f17 /*     VIDEO */
+#define PA_VI_VDELAY1     0x3f18 /*     VIDEO */
+#define PA_VI_HDELAY2     0x3f19 /*     VIDEO */
+#define PA_VI_VDELAY2     0x3f1a /*     VIDEO */
+#define PA_VI_HDELAY3     0x3f1b /*     VIDEO */
+#define PA_VI_VDELAY3     0x3f1c /*     VIDEO */
+#define PA_VI_CTRL        0x3f20 /*     VIDEO */
+#define PA_JPEG_CTRL      0x3f22 /* CCD/VIDEO */
+#define PA_BUFFER_SIZE    0x3f24 /* CCD/VIDEO */
+#define PA_PAL_NTSC       0x3f25 /*     VIDEO */
+#define PA_MACROBLOCKS    0x3f26 /* CCD/VIDEO */
+#define PA_COLOR          0x3f27 /*     VIDEO */
+#define PA_MEMCH1CNT2     0x3f28 /* CCD/VIDEO */
+#define PA_MEMCH1CNT3     0x3f29 /*     VIDEO */
+#define PA_MEMCH1STR2     0x3f2a /* CCD/VIDEO */
+#define PA_MEMCH1STR3     0x3f2b /*     VIDEO */
+#define PA_BUFFERS        0x3f2c /* CCD/VIDEO */
+#define PA_PROGRAM        0x3f2d /* CCD/VIDEO */
+#define PA_ROTATION       0x3f2e /* CCD       */
+#define PA_PC             0x3f30 /* CCD/VIDEO */
+#define PA_PC2            0x3f31 /*     VIDEO */
+#define PA_ODD_LINE       0x3f32 /*     VIDEO */
+#define PA_EXP_DELAY      0x3f34 /* CCD       */
+#define PA_MACROBLOCK_CNT 0x3f35 /* CCD/VIDEO */
+#define PA_DRAM_PTR1_L    0x3f36 /* CCD/VIDEO */
+#define PA_CLPOB_CNT      0x3f37 /* CCD       */
+#define PA_DRAM_PTR1_H    0x3f38 /* CCD/VIDEO */
+#define PA_DRAM_PTR2_L    0x3f3a /*     VIDEO */
+#define PA_DRAM_PTR2_H    0x3f3c /*     VIDEO */
+#define PA_CCD_LINE_CNT   0x3f3f /* CCD       */
+#define PA_VIDEO_LINE_CNT 0x3f3f /*     VIDEO */
+#define PA_TEXT           0x3f41 /* CCD/VIDEO */
+#define PA_CAMERA_CHANGED 0x3f42 /*     VIDEO */
+#define PA_TEXTALIGNMENT  0x3f43 /*     VIDEO */
+#define PA_DISABLED       0x3f44 /*     VIDEO */
+#define PA_MACROBLOCKTEXT 0x3f45 /*     VIDEO */
+#define PA_VGA            0x3f46 /*     VIDEO */
+#define PA_ZERO           0x3ffe /*     VIDEO */
+#define PA_NULL           0x3fff /* CCD/VIDEO */
+
+typedef enum {
+	jpeg  = 0,
+	dummy = 1
+} request_type;
+
+typedef enum {
+	hugesize  = 0,
+	fullsize  = 1,
+	halfsize  = 2,
+	fieldsize = 3
+} size_type;
+
+typedef enum {
+	min       = 0,
+	low       = 1,
+	medium    = 2,
+	high      = 3,
+	very_high = 4,
+	very_low  = 5,
+	q1        = 6,
+	q2        = 7,
+	q3        = 8,
+	q4        = 9,
+	q5        = 10,
+	q6        = 11
+} compr_type;
+
+typedef enum {
+	deg_0   = 0,
+	deg_180 = 1,
+	deg_90  = 2,
+	deg_270 = 3
+} rotation_type;
+
+typedef enum {
+	auto_white    = 0,
+	hold          = 1,
+	fixed_outdoor = 2,
+	fixed_indoor  = 3,
+	fixed_fluor   = 4
+} white_balance_type;
+
+typedef enum {
+	auto_exp  = 0,
+	fixed_exp = 1
+} exposure_type;
+
+typedef enum {
+	no_window = 0,
+	center    = 1,
+	top       = 2,
+	lower     = 3,
+	left      = 4,
+	right     = 5,
+	spot      = 6,
+	cw        = 7
+} exp_window_type;
+
+typedef enum {
+	h_24 = 0,
+	h_12 = 1,
+	h_24P = 2
+} hour_type;
+
+typedef enum {
+	standard = 0,
+	YYYY_MM_DD = 1,
+	Www_Mmm_DD_YYYY = 2,
+	Www_DD_MM_YYYY = 3
+} date_type;
+
+typedef enum {
+	left_align = 0,
+	center_align = 1,
+	right_align = 2
+} alignment_type;
+
+typedef enum {
+	off = 0,
+	on  = 1,
+	no  = 0,
+	yes = 1
+} enable_type;
+
+typedef enum {
+         disabled = 0,
+         enabled  = 1,
+         extended = 2
+} comment_type;
+
+typedef enum {
+	pal  = 0,
+	ntsc = 1
+} video_type;
+
+typedef enum {
+	pal_bghi_ntsc_m              = 0,
+	ntsc_4_43_50hz_pal_4_43_60hz = 1,
+	pal_n_ntsc_4_43_60hz         = 2,
+	ntsc_n_pal_m                 = 3,
+	secam_pal_4_43_60hz          = 4
+} modulation_type;
+
+typedef enum {
+	cam0 = 0,
+	cam1 = 1,
+	cam2 = 2,
+	cam3 = 3,
+	quad = 32
+} camera_type;
+
+typedef enum {
+	video_driver = 0,
+	ccd_driver   = 1
+} driver_type;
+
+struct jul_param {
+	request_type req_type;
+	size_type size;
+	compr_type compression;
+	rotation_type rotation;
+	int color_level;
+	int brightness;
+	white_balance_type white_balance;
+	exposure_type exposure;
+        exp_window_type auto_exp_window;
+	hour_type time_format;
+	date_type date_format;
+	alignment_type text_alignment;
+	enable_type text;
+	enable_type clock;
+	enable_type date;
+	enable_type fps;
+        enable_type vga;
+        enable_type comment;
+};
+
+struct video_param {
+	enable_type disabled;
+	modulation_type modulation;
+	video_type video;
+	enable_type signal;
+	enable_type vcr;
+	int xoffset;
+	int yoffset;
+};
+
+/* The juliette_request structure is used during the JULSTARTDMA asynchronous
+ * picture-taking ioctl call as an argument to specify a buffer which will get
+ * the final picture.
+ */
+
+struct juliette_request {
+	char *buf;              /* Pointer to the buffer to hold picture data */
+	unsigned int buflen;    /* Length of the above buffer */
+	unsigned int size;      /* Resulting length, 0 if the picture is not ready */
+};
+
+#endif
diff --git a/include/asm-cris/arch-v32/memmap.h b/include/asm-cris/arch-v32/memmap.h
new file mode 100644
index 00000000000..d29df5644d3
--- /dev/null
+++ b/include/asm-cris/arch-v32/memmap.h
@@ -0,0 +1,24 @@
+#ifndef _ASM_ARCH_MEMMAP_H
+#define _ASM_ARCH_MEMMAP_H
+
+#define MEM_CSE0_START (0x00000000)
+#define MEM_CSE0_SIZE (0x04000000)
+#define MEM_CSE1_START (0x04000000)
+#define MEM_CSE1_SIZE (0x04000000)
+#define MEM_CSR0_START (0x08000000)
+#define MEM_CSR1_START (0x0c000000)
+#define MEM_CSP0_START (0x10000000)
+#define MEM_CSP1_START (0x14000000)
+#define MEM_CSP2_START (0x18000000)
+#define MEM_CSP3_START (0x1c000000)
+#define MEM_CSP4_START (0x20000000)
+#define MEM_CSP5_START (0x24000000)
+#define MEM_CSP6_START (0x28000000)
+#define MEM_CSP7_START (0x2c000000)
+#define MEM_INTMEM_START (0x38000000)
+#define MEM_INTMEM_SIZE (0x00020000)
+#define MEM_DRAM_START (0x40000000)
+
+#define MEM_NON_CACHEABLE (0x80000000)
+
+#endif
diff --git a/include/asm-cris/arch-v32/mmu.h b/include/asm-cris/arch-v32/mmu.h
new file mode 100644
index 00000000000..6bcdc3fdf7d
--- /dev/null
+++ b/include/asm-cris/arch-v32/mmu.h
@@ -0,0 +1,111 @@
+#ifndef _ASM_CRIS_ARCH_MMU_H
+#define _ASM_CRIS_ARCH_MMU_H
+
+/* MMU context type. */
+typedef struct
+{
+  unsigned int page_id;
+} mm_context_t;
+
+/* Kernel memory segments. */
+#define KSEG_F 0xf0000000UL
+#define KSEG_E 0xe0000000UL
+#define KSEG_D 0xd0000000UL
+#define KSEG_C 0xc0000000UL
+#define KSEG_B 0xb0000000UL
+#define KSEG_A 0xa0000000UL
+#define KSEG_9 0x90000000UL
+#define KSEG_8 0x80000000UL
+#define KSEG_7 0x70000000UL
+#define KSEG_6 0x60000000UL
+#define KSEG_5 0x50000000UL
+#define KSEG_4 0x40000000UL
+#define KSEG_3 0x30000000UL
+#define KSEG_2 0x20000000UL
+#define KSEG_1 0x10000000UL
+#define KSEG_0 0x00000000UL
+
+/*
+ * CRISv32 PTE bits:
+ *
+ *  Bit:  31-13  12-5     4        3       2        1        0
+ *       +-----+------+--------+-------+--------+-------+---------+
+ *       | pfn | zero | global | valid | kernel | write | execute |
+ *       +-----+------+--------+-------+--------+-------+---------+
+ */
+
+/*
+ * Defines for accessing the bits. Also define some synonyms for use with
+ * the software-based defined bits below.
+ */
+#define _PAGE_EXECUTE       (1 << 0)	/* Execution bit. */
+#define _PAGE_WE            (1 << 1)	/* Write bit. */
+#define _PAGE_SILENT_WRITE  (1 << 1)	/* Same as above. */
+#define _PAGE_KERNEL        (1 << 2)	/* Kernel mode page. */
+#define _PAGE_VALID         (1 << 3)	/* Page is valid. */
+#define _PAGE_SILENT_READ   (1 << 3)	/* Same as above. */
+#define _PAGE_GLOBAL        (1 << 4)	/* Global page. */
+
+/*
+ * The hardware doesn't care about these bits, but the kernel uses them in
+ * software.
+ */
+#define _PAGE_PRESENT   (1 << 5)   /* Page is present in memory. */
+#define _PAGE_FILE      (1 << 6)   /* 1=pagecache, 0=swap (when !present) */
+#define _PAGE_ACCESSED  (1 << 6)   /* Simulated in software using valid bit. */
+#define _PAGE_MODIFIED  (1 << 7)   /* Simulated in software using we bit. */
+#define _PAGE_READ      (1 << 8)   /* Read enabled. */
+#define _PAGE_WRITE     (1 << 9)   /* Write enabled. */
+
+/* Define some higher level generic page attributes. */
+#define __READABLE      (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
+#define __WRITEABLE     (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
+
+#define _PAGE_TABLE	(_PAGE_PRESENT | __READABLE | __WRITEABLE)
+#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED)
+
+#define PAGE_NONE       __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
+#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \
+                                 _PAGE_ACCESSED)
+#define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \
+                                  _PAGE_ACCESSED | _PAGE_EXECUTE)
+
+#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | __READABLE)
+#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE | _PAGE_ACCESSED)
+
+#define PAGE_COPY       __pgprot(_PAGE_PRESENT | __READABLE)
+#define PAGE_COPY_EXEC	__pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE)
+#define PAGE_KERNEL     __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \
+                                 _PAGE_PRESENT | __READABLE | __WRITEABLE)
+#define PAGE_KERNEL_EXEC __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | _PAGE_EXECUTE | \
+                                 _PAGE_PRESENT | __READABLE | __WRITEABLE)
+#define PAGE_SIGNAL_TRAMPOLINE __pgprot(_PAGE_GLOBAL | _PAGE_EXECUTE | \
+                                       _PAGE_PRESENT | __READABLE)
+
+#define _KERNPG_TABLE   (_PAGE_TABLE | _PAGE_KERNEL)
+
+/* CRISv32 can do page protection for execute.
+ * Write permissions imply read permissions.
+ * Note that the numbers are in Execute-Write-Read order!
+ */
+#define __P000  PAGE_NONE
+#define __P001  PAGE_READONLY
+#define __P010  PAGE_COPY
+#define __P011  PAGE_COPY
+#define __P100  PAGE_READONLY_EXEC
+#define __P101  PAGE_READONLY_EXEC
+#define __P110  PAGE_COPY_EXEC
+#define __P111  PAGE_COPY_EXEC
+
+#define __S000  PAGE_NONE
+#define __S001  PAGE_READONLY
+#define __S010  PAGE_SHARED
+#define __S011  PAGE_SHARED
+#define __S100  PAGE_READONLY_EXEC
+#define __S101  PAGE_READONLY_EXEC
+#define __S110  PAGE_SHARED_EXEC
+#define __S111  PAGE_SHARED_EXEC
+
+#define PTE_FILE_MAX_BITS	25
+
+#endif /* _ASM_CRIS_ARCH_MMU_H */
diff --git a/include/asm-cris/arch-v32/offset.h b/include/asm-cris/arch-v32/offset.h
new file mode 100644
index 00000000000..597419b033f
--- /dev/null
+++ b/include/asm-cris/arch-v32/offset.h
@@ -0,0 +1,35 @@
+#ifndef __ASM_OFFSETS_H__
+#define __ASM_OFFSETS_H__
+/*
+ * DO NOT MODIFY.
+ *
+ * This file was generated by arch/cris/Makefile
+ *
+ */
+
+#define PT_orig_r10 0 /* offsetof(struct pt_regs, orig_r10) */
+#define PT_r13 56 /* offsetof(struct pt_regs, r13) */
+#define PT_r12 52 /* offsetof(struct pt_regs, r12) */
+#define PT_r11 48 /* offsetof(struct pt_regs, r11) */
+#define PT_r10 44 /* offsetof(struct pt_regs, r10) */
+#define PT_r9 40 /* offsetof(struct pt_regs, r9) */
+#define PT_acr 60 /* offsetof(struct pt_regs, acr) */
+#define PT_srs 64 /* offsetof(struct pt_regs, srs) */
+#define PT_mof 68 /* offsetof(struct pt_regs, mof) */
+#define PT_ccs 76 /* offsetof(struct pt_regs, ccs) */
+#define PT_srp 80 /* offsetof(struct pt_regs, srp) */
+
+#define TI_task 0 /* offsetof(struct thread_info, task) */
+#define TI_flags 8 /* offsetof(struct thread_info, flags) */
+#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */
+
+#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */
+#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */
+#define THREAD_ccs 8 /* offsetof(struct thread_struct, ccs) */
+
+#define TASK_pid 149 /* offsetof(struct task_struct, pid) */
+
+#define LCLONE_VM 256 /* CLONE_VM */
+#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */
+
+#endif
diff --git a/include/asm-cris/arch-v32/page.h b/include/asm-cris/arch-v32/page.h
new file mode 100644
index 00000000000..77827bc17cc
--- /dev/null
+++ b/include/asm-cris/arch-v32/page.h
@@ -0,0 +1,28 @@
+#ifndef _ASM_CRIS_ARCH_PAGE_H
+#define _ASM_CRIS_ARCH_PAGE_H
+
+#include <linux/config.h>
+
+#ifdef __KERNEL__
+
+#define PAGE_OFFSET KSEG_C	/* kseg_c is mapped to physical ram. */
+
+/*
+ * Macros to convert between physical and virtual addresses. By stripiing a
+ * selected bit it's possible to convert between KSEG_x and 0x40000000 where the
+ * DRAM really resides. DRAM is virtually at 0xc.
+ */
+#ifndef CONFIG_ETRAXFS_SIM
+#define __pa(x) ((unsigned long)(x) & 0x7fffffff)
+#define __va(x) ((void *)((unsigned long)(x) | 0x80000000))
+#else
+#define __pa(x) ((unsigned long)(x) & 0x3fffffff)
+#define __va(x) ((void *)((unsigned long)(x) | 0xc0000000))
+#endif
+
+#define VM_STACK_DEFAULT_FLAGS	(VM_READ | VM_WRITE | \
+				 VM_MAYREAD | VM_MAYWRITE)
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_CRIS_ARCH_PAGE_H */
diff --git a/include/asm-cris/arch-v32/pgtable.h b/include/asm-cris/arch-v32/pgtable.h
new file mode 100644
index 00000000000..08cb7ff7e4e
--- /dev/null
+++ b/include/asm-cris/arch-v32/pgtable.h
@@ -0,0 +1,9 @@
+#ifndef _ASM_CRIS_ARCH_PGTABLE_H
+#define _ASM_CRIS_ARCH_PGTABLE_H
+
+/* Define the kernels virtual memory area. */
+#define VMALLOC_START		KSEG_D
+#define VMALLOC_END		KSEG_E
+#define VMALLOC_VMADDR(x)	((unsigned long)(x))
+
+#endif /* _ASM_CRIS_ARCH_PGTABLE_H */
diff --git a/include/asm-cris/arch-v32/pinmux.h b/include/asm-cris/arch-v32/pinmux.h
new file mode 100644
index 00000000000..a66dc997091
--- /dev/null
+++ b/include/asm-cris/arch-v32/pinmux.h
@@ -0,0 +1,39 @@
+#ifndef _ASM_CRIS_ARCH_PINMUX_H
+#define _ASM_CRIS_ARCH_PINMUX_H
+
+#define PORT_B 0
+#define PORT_C 1
+#define PORT_D 2
+#define PORT_E 3
+
+enum pin_mode
+{
+  pinmux_none = 0,
+  pinmux_fixed,
+  pinmux_gpio,
+  pinmux_iop
+};
+
+enum fixed_function
+{
+  pinmux_ser1,
+  pinmux_ser2,
+  pinmux_ser3,
+  pinmux_sser0,
+  pinmux_sser1,
+  pinmux_ata0,
+  pinmux_ata1,
+  pinmux_ata2,
+  pinmux_ata3,
+  pinmux_ata,
+  pinmux_eth1,
+  pinmux_timer
+};
+
+int crisv32_pinmux_init(void);
+int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode);
+int crisv32_pinmux_alloc_fixed(enum fixed_function function);
+int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin);
+void crisv32_pinmux_dump(void);
+
+#endif
diff --git a/include/asm-cris/arch-v32/processor.h b/include/asm-cris/arch-v32/processor.h
new file mode 100644
index 00000000000..8c939bf2798
--- /dev/null
+++ b/include/asm-cris/arch-v32/processor.h
@@ -0,0 +1,60 @@
+#ifndef _ASM_CRIS_ARCH_PROCESSOR_H
+#define _ASM_CRIS_ARCH_PROCESSOR_H
+
+#include <linux/config.h>
+
+/* Return current instruction pointer. */
+#define current_text_addr() \
+	({void *pc; __asm__ __volatile__ ("lapcq .,%0" : "=rm" (pc)); pc;})
+
+/*
+ * Since CRIS doesn't do hardware task-switching this hasn't really anything to
+ * do with the proccessor itself, it's just here for legacy reasons. This is
+ * used when task-switching using _resume defined in entry.S. The offsets here
+ * are hardcoded into _resume, so if this struct is changed, entry.S needs to be
+ * changed as well.
+ */
+struct thread_struct {
+	unsigned long ksp;	/* Kernel stack pointer. */
+	unsigned long usp;	/* User stack pointer. */
+	unsigned long ccs;	/* Saved flags register. */
+};
+
+/*
+ * User-space process size. This is hardcoded into a few places, so don't
+ * changed it unless everything's clear!
+ */
+#ifndef CONFIG_ETRAXFS_SIM
+#define TASK_SIZE	(0xB0000000UL)
+#else
+#define TASK_SIZE	(0xA0000000UL)
+#endif
+
+/* CCS I=1, enable interrupts. */
+#define INIT_THREAD { 0, 0, (1 << I_CCS_BITNR) }
+
+#define KSTK_EIP(tsk)		\
+({				\
+	unsigned long eip = 0;	\
+	unsigned long regs = (unsigned long)user_regs(tsk); \
+	if (regs > PAGE_SIZE && virt_addr_valid(regs))	    \
+		eip = ((struct pt_regs *)regs)->erp;	    \
+	eip; \
+})
+
+/*
+ * Give the thread a program location, set user-mode and switch user
+ * stackpointer.
+ */
+#define start_thread(regs, ip, usp) \
+do { \
+	set_fs(USER_DS); \
+	regs->erp = ip; \
+	regs->ccs |= 1 << (U_CCS_BITNR + CCS_SHIFT); \
+	wrusp(usp); \
+} while(0)
+
+/* Nothing special to do for v32 when handling a kernel bus fault fixup. */
+#define arch_fixup(regs) {};
+
+#endif /* _ASM_CRIS_ARCH_PROCESSOR_H */
diff --git a/include/asm-cris/arch-v32/ptrace.h b/include/asm-cris/arch-v32/ptrace.h
new file mode 100644
index 00000000000..516cc7062d9
--- /dev/null
+++ b/include/asm-cris/arch-v32/ptrace.h
@@ -0,0 +1,114 @@
+#ifndef _CRIS_ARCH_PTRACE_H
+#define _CRIS_ARCH_PTRACE_H
+
+/* Register numbers in the ptrace system call interface */
+
+#define PT_ORIG_R10  0
+#define PT_R0        1
+#define PT_R1        2
+#define PT_R2        3
+#define PT_R3        4
+#define PT_R4        5
+#define PT_R5        6
+#define PT_R6        7
+#define PT_R7        8
+#define PT_R8        9
+#define PT_R9        10
+#define PT_R10       11
+#define PT_R11       12
+#define PT_R12       13
+#define PT_R13       14
+#define PT_ACR       15
+#define PT_SRS       16
+#define PT_MOF       17
+#define PT_SPC       18
+#define PT_CCS       19
+#define PT_SRP       20
+#define PT_ERP       21    /* This is actually the debugged process' PC */
+#define PT_EXS       22
+#define PT_EDA       23
+#define PT_USP       24    /* special case - USP is not in the pt_regs */
+#define PT_PPC       25    /* special case - pseudo PC */
+#define PT_BP        26    /* Base number for BP registers. */
+#define PT_BP_CTRL   26    /* BP control register. */
+#define PT_MAX       40
+
+/* Condition code bit numbers. */
+#define C_CCS_BITNR 0
+#define V_CCS_BITNR 1
+#define Z_CCS_BITNR 2
+#define N_CCS_BITNR 3
+#define X_CCS_BITNR 4
+#define I_CCS_BITNR 5
+#define U_CCS_BITNR 6
+#define P_CCS_BITNR 7
+#define R_CCS_BITNR 8
+#define S_CCS_BITNR 9
+#define M_CCS_BITNR 30
+#define Q_CCS_BITNR 31
+#define CCS_SHIFT   10 /* Shift count for each level in CCS */
+
+/* pt_regs not only specifices the format in the user-struct during
+ * ptrace but is also the frame format used in the kernel prologue/epilogues
+ * themselves
+ */
+
+struct pt_regs {
+	unsigned long orig_r10;
+	/* pushed by movem r13, [sp] in SAVE_ALL. */
+	unsigned long r0;
+	unsigned long r1;
+	unsigned long r2;
+	unsigned long r3;
+	unsigned long r4;
+	unsigned long r5;
+	unsigned long r6;
+	unsigned long r7;
+	unsigned long r8;
+	unsigned long r9;
+	unsigned long r10;
+	unsigned long r11;
+	unsigned long r12;
+	unsigned long r13;
+	unsigned long acr;
+	unsigned long srs;
+	unsigned long mof;
+	unsigned long spc;
+	unsigned long ccs;
+	unsigned long srp;
+	unsigned long erp; /* This is actually the debugged process' PC */
+	/* For debugging purposes; saved only when needed. */
+	unsigned long exs;
+	unsigned long eda;
+};
+
+/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S)
+ * when doing a context-switch. it is used (apart from in resume) when a new
+ * thread is made and we need to make _resume (which is starting it for the
+ * first time) realise what is going on.
+ *
+ * Actually, the use is very close to the thread struct (TSS) in that both the
+ * switch_stack and the TSS are used to keep thread stuff when switching in
+ * _resume.
+ */
+
+struct switch_stack {
+	unsigned long r0;
+	unsigned long r1;
+	unsigned long r2;
+	unsigned long r3;
+	unsigned long r4;
+	unsigned long r5;
+	unsigned long r6;
+	unsigned long r7;
+	unsigned long r8;
+	unsigned long r9;
+	unsigned long return_ip; /* ip that _resume will return to */
+};
+
+#define user_mode(regs) (((regs)->ccs & (1 << (U_CCS_BITNR + CCS_SHIFT))) != 0)
+#define instruction_pointer(regs) ((regs)->erp)
+extern void show_regs(struct pt_regs *);
+#define profile_pc(regs) instruction_pointer(regs)
+
+#endif
diff --git a/include/asm-cris/arch-v32/spinlock.h b/include/asm-cris/arch-v32/spinlock.h
new file mode 100644
index 00000000000..52df72a6223
--- /dev/null
+++ b/include/asm-cris/arch-v32/spinlock.h
@@ -0,0 +1,163 @@
+#ifndef __ASM_ARCH_SPINLOCK_H
+#define __ASM_ARCH_SPINLOCK_H
+
+#include <asm/system.h>
+
+#define RW_LOCK_BIAS 0x01000000
+#define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 }
+#define spin_lock_init(x)	do { *(x) = SPIN_LOCK_UNLOCKED; } while(0)
+
+#define spin_is_locked(x)	(*(volatile signed char *)(&(x)->lock) <= 0)
+#define spin_unlock_wait(x)	do { barrier(); } while(spin_is_locked(x))
+
+extern void cris_spin_unlock(void *l, int val);
+extern void cris_spin_lock(void *l);
+extern int cris_spin_trylock(void* l);
+
+static inline void _raw_spin_unlock(spinlock_t *lock)
+{
+	__asm__ volatile ("move.d %1,%0" \
+	                  : "=m" (lock->lock) \
+			  : "r" (1) \
+			  : "memory");
+}
+
+static inline int _raw_spin_trylock(spinlock_t *lock)
+{
+	return cris_spin_trylock((void*)&lock->lock);
+}
+
+static inline void _raw_spin_lock(spinlock_t *lock)
+{
+	cris_spin_lock((void*)&lock->lock);
+}
+
+static inline void _raw_spin_lock_flags (spinlock_t *lock, unsigned long flags)
+{
+  _raw_spin_lock(lock);
+}
+
+/*
+ * Read-write spinlocks, allowing multiple readers
+ * but only one writer.
+ *
+ * NOTE! it is quite common to have readers in interrupts
+ * but no interrupt writers. For those circumstances we
+ * can "mix" irq-safe locks - any writer needs to get a
+ * irq-safe write-lock, but readers can get non-irqsafe
+ * read-locks.
+ */
+typedef struct {
+	spinlock_t lock;
+	volatile int counter;
+#ifdef CONFIG_PREEMPT
+	unsigned int break_lock;
+#endif
+} rwlock_t;
+
+#define RW_LOCK_UNLOCKED (rwlock_t) { {1}, 0 }
+
+#define rwlock_init(lp)	do { *(lp) = RW_LOCK_UNLOCKED; } while (0)
+
+/**
+ * read_can_lock - would read_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+#define read_can_lock(x) ((int)(x)->counter >= 0)
+
+/**
+ * write_can_lock - would write_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+#define write_can_lock(x) ((x)->counter == 0)
+
+#define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
+
+/* read_lock, read_unlock are pretty straightforward.  Of course it somehow
+ * sucks we end up saving/restoring flags twice for read_lock_irqsave aso. */
+
+static  __inline__ void _raw_read_lock(rwlock_t *rw)
+{
+	unsigned long flags;
+	local_irq_save(flags);
+	_raw_spin_lock(&rw->lock);
+
+	rw->counter++;
+
+	_raw_spin_unlock(&rw->lock);
+	local_irq_restore(flags);
+}
+
+static  __inline__ void _raw_read_unlock(rwlock_t *rw)
+{
+	unsigned long flags;
+	local_irq_save(flags);
+	_raw_spin_lock(&rw->lock);
+
+	rw->counter--;
+
+	_raw_spin_unlock(&rw->lock);
+	local_irq_restore(flags);
+}
+
+/* write_lock is less trivial.  We optimistically grab the lock and check
+ * if we surprised any readers.  If so we release the lock and wait till
+ * they're all gone before trying again
+ *
+ * Also note that we don't use the _irqsave / _irqrestore suffixes here.
+ * If we're called with interrupts enabled and we've got readers (or other
+ * writers) in interrupt handlers someone fucked up and we'd dead-lock
+ * sooner or later anyway.   prumpf */
+
+static  __inline__ void _raw_write_lock(rwlock_t *rw)
+{
+retry:
+	_raw_spin_lock(&rw->lock);
+
+	if(rw->counter != 0) {
+		/* this basically never happens */
+		_raw_spin_unlock(&rw->lock);
+
+		while(rw->counter != 0);
+
+		goto retry;
+	}
+
+	/* got it.  now leave without unlocking */
+	rw->counter = -1; /* remember we are locked */
+}
+
+/* write_unlock is absolutely trivial - we don't have to wait for anything */
+
+static  __inline__ void _raw_write_unlock(rwlock_t *rw)
+{
+	rw->counter = 0;
+	_raw_spin_unlock(&rw->lock);
+}
+
+static  __inline__ int _raw_write_trylock(rwlock_t *rw)
+{
+	_raw_spin_lock(&rw->lock);
+	if (rw->counter != 0) {
+		/* this basically never happens */
+		_raw_spin_unlock(&rw->lock);
+
+		return 0;
+	}
+
+	/* got it.  now leave without unlocking */
+	rw->counter = -1; /* remember we are locked */
+	return 1;
+}
+
+static __inline__ int is_read_locked(rwlock_t *rw)
+{
+	return rw->counter > 0;
+}
+
+static __inline__ int is_write_locked(rwlock_t *rw)
+{
+	return rw->counter < 0;
+}
+
+#endif /* __ASM_ARCH_SPINLOCK_H */
diff --git a/include/asm-cris/arch-v32/system.h b/include/asm-cris/arch-v32/system.h
new file mode 100644
index 00000000000..b9afbb95e0b
--- /dev/null
+++ b/include/asm-cris/arch-v32/system.h
@@ -0,0 +1,79 @@
+#ifndef _ASM_CRIS_ARCH_SYSTEM_H
+#define _ASM_CRIS_ARCH_SYSTEM_H
+
+#include <linux/config.h>
+
+/* Read the CPU version register. */
+extern inline unsigned long rdvr(void)
+{
+	unsigned char vr;
+
+	__asm__ __volatile__ ("move $vr, %0" : "=rm" (vr));
+	return vr;
+}
+
+#define cris_machine_name "crisv32"
+
+/* Read the user-mode stack pointer. */
+extern inline unsigned long rdusp(void)
+{
+	unsigned long usp;
+
+	__asm__ __volatile__ ("move $usp, %0" : "=rm" (usp));
+	return usp;
+}
+
+/* Read the current stack pointer. */
+extern inline unsigned long rdsp(void)
+{
+	unsigned long sp;
+
+	__asm__ __volatile__ ("move.d $sp, %0" : "=rm" (sp));
+	return sp;
+}
+
+/* Write the user-mode stack pointer. */
+#define wrusp(usp) __asm__ __volatile__ ("move %0, $usp" : : "rm" (usp))
+
+#define nop() __asm__ __volatile__ ("nop");
+
+#define xchg(ptr,x) \
+	((__typeof__(*(ptr)))__xchg((unsigned long) (x),(ptr),sizeof(*(ptr))))
+
+#define tas(ptr) (xchg((ptr),1))
+
+struct __xchg_dummy { unsigned long a[100]; };
+#define __xg(x) ((struct __xchg_dummy *)(x))
+
+/* Used for interrupt control. */
+#define local_save_flags(x) \
+	__asm__ __volatile__ ("move $ccs, %0" : "=rm" (x) : : "memory");
+
+#define local_irq_restore(x) \
+	__asm__ __volatile__ ("move %0, $ccs" : : "rm" (x) : "memory");
+
+#define local_irq_disable()  __asm__ __volatile__ ("di" : : : "memory");
+#define local_irq_enable()   __asm__ __volatile__ ("ei" : : : "memory");
+
+#define irqs_disabled()		\
+({				\
+	unsigned long flags;	\
+				\
+	local_save_flags(flags);\
+	!(flags & (1 << I_CCS_BITNR));	\
+})
+
+/* Used for spinlocks, etc. */
+#define local_irq_save(x) \
+	__asm__ __volatile__ ("move $ccs, %0\n\tdi" : "=rm" (x) : : "memory");
+
+#ifdef CONFIG_SMP
+typedef struct {
+	volatile unsigned int lock __attribute__ ((aligned(4)));
+#ifdef CONFIG_PREEMPT
+	unsigned int break_lock;
+#endif
+} spinlock_t;
+#endif
+
+#endif /* _ASM_CRIS_ARCH_SYSTEM_H */
diff --git a/include/asm-cris/arch-v32/thread_info.h b/include/asm-cris/arch-v32/thread_info.h
new file mode 100644
index 00000000000..a7a182307da
--- /dev/null
+++ b/include/asm-cris/arch-v32/thread_info.h
@@ -0,0 +1,13 @@
+#ifndef _ASM_CRIS_ARCH_THREAD_INFO_H
+#define _ASM_CRIS_ARCH_THREAD_INFO_H
+
+/* Return a thread_info struct. */
+extern inline struct thread_info *current_thread_info(void)
+{
+	struct thread_info *ti;
+
+	__asm__ __volatile__ ("and.d $sp, %0" : "=r" (ti) : "0" (~8191UL));
+	return ti;
+}
+
+#endif /* _ASM_CRIS_ARCH_THREAD_INFO_H */
diff --git a/include/asm-cris/arch-v32/timex.h b/include/asm-cris/arch-v32/timex.h
new file mode 100644
index 00000000000..4d0fd23b21e
--- /dev/null
+++ b/include/asm-cris/arch-v32/timex.h
@@ -0,0 +1,31 @@
+#ifndef _ASM_CRIS_ARCH_TIMEX_H
+#define _ASM_CRIS_ARCH_TIMEX_H
+
+#include <asm/arch/hwregs/reg_map.h>
+#include <asm/arch/hwregs/reg_rdwr.h>
+#include <asm/arch/hwregs/timer_defs.h>
+
+/*
+ * The clock runs at 100MHz, we divide it by 1000000. If you change anything
+ * here you must check time.c as well.
+ */
+
+#define CLOCK_TICK_RATE 100000000	/* Underlying frequency of the HZ timer */
+
+/* The timer0 values gives 10 ns resolution but interrupts at HZ. */
+#define TIMER0_FREQ (CLOCK_TICK_RATE)
+#define TIMER0_DIV (TIMER0_FREQ/(HZ))
+
+/* Convert the value in step of 10 ns to 1us without overflow: */
+#define GET_JIFFIES_USEC() \
+  ( (TIMER0_DIV - REG_RD(timer, regi_timer, r_tmr0_data)) /100 )
+
+extern unsigned long get_ns_in_jiffie(void);
+
+extern inline unsigned long get_us_in_jiffie_highres(void)
+{
+	return get_ns_in_jiffie() / 1000;
+}
+
+#endif
+
diff --git a/include/asm-cris/arch-v32/tlb.h b/include/asm-cris/arch-v32/tlb.h
new file mode 100644
index 00000000000..4effb125366
--- /dev/null
+++ b/include/asm-cris/arch-v32/tlb.h
@@ -0,0 +1,14 @@
+#ifndef _CRIS_ARCH_TLB_H
+#define _CRIS_ARCH_TLB_H
+
+/*
+ * The TLB is a 64-entry cache. Each entry has a 8-bit page_id that is used
+ * to store the "process" it belongs to (=> fast mm context switch). The
+ * last page_id is never used so we can make TLB entries that never matches.
+ */
+#define NUM_TLB_ENTRIES 64
+#define NUM_PAGEID 256
+#define INVALID_PAGEID 255
+#define NO_CONTEXT -1
+
+#endif /* _CRIS_ARCH_TLB_H */
diff --git a/include/asm-cris/arch-v32/uaccess.h b/include/asm-cris/arch-v32/uaccess.h
new file mode 100644
index 00000000000..055a0bdbe83
--- /dev/null
+++ b/include/asm-cris/arch-v32/uaccess.h
@@ -0,0 +1,748 @@
+/*
+ * Authors:    Hans-Peter Nilsson (hp@axis.com)
+ *
+ */
+#ifndef _CRIS_ARCH_UACCESS_H
+#define _CRIS_ARCH_UACCESS_H
+
+/*
+ * We don't tell gcc that we are accessing memory, but this is OK
+ * because we do not write to any memory gcc knows about, so there
+ * are no aliasing issues.
+ *
+ * Note that PC at a fault is the address *at* the faulting
+ * instruction for CRISv32.
+ */
+#define __put_user_asm(x, addr, err, op)			\
+	__asm__ __volatile__(					\
+		"2:	"op" %1,[%2]\n"				\
+		"4:\n"						\
+		"	.section .fixup,\"ax\"\n"		\
+		"3:	move.d %3,%0\n"				\
+		"	jump 4b\n"				\
+		"	nop\n"					\
+		"	.previous\n"				\
+		"	.section __ex_table,\"a\"\n"		\
+		"	.dword 2b,3b\n"				\
+		"	.previous\n"				\
+		: "=r" (err)					\
+		: "r" (x), "r" (addr), "g" (-EFAULT), "0" (err))
+
+#define __put_user_asm_64(x, addr, err) do {			\
+	int dummy_for_put_user_asm_64_;				\
+	__asm__ __volatile__(					\
+		"2:	move.d %M2,[%1+]\n"			\
+		"4:	move.d %H2,[%1]\n"			\
+		"5:\n"						\
+		"	.section .fixup,\"ax\"\n"		\
+		"3:	move.d %4,%0\n"				\
+		"	jump 5b\n"				\
+		"	.previous\n"				\
+		"	.section __ex_table,\"a\"\n"		\
+		"	.dword 2b,3b\n"				\
+		"	.dword 4b,3b\n"				\
+		"	.previous\n"				\
+		: "=r" (err), "=b" (dummy_for_put_user_asm_64_)	\
+		: "r" (x), "1" (addr), "g" (-EFAULT),		\
+		  "0" (err));					\
+	} while (0)
+
+/* See comment before __put_user_asm.  */
+
+#define __get_user_asm(x, addr, err, op)		\
+	__asm__ __volatile__(				\
+		"2:	"op" [%2],%1\n"			\
+		"4:\n"					\
+		"	.section .fixup,\"ax\"\n"	\
+		"3:	move.d %3,%0\n"			\
+		"	jump 4b\n"			\
+		"	moveq 0,%1\n"			\
+		"	.previous\n"			\
+		"	.section __ex_table,\"a\"\n"	\
+		"	.dword 2b,3b\n"			\
+		"	.previous\n"			\
+		: "=r" (err), "=r" (x)			\
+		: "r" (addr), "g" (-EFAULT), "0" (err))
+
+#define __get_user_asm_64(x, addr, err) do {		\
+	int dummy_for_get_user_asm_64_;			\
+	__asm__ __volatile__(				\
+		"2:	move.d [%2+],%M1\n"		\
+		"4:	move.d [%2],%H1\n"		\
+		"5:\n"					\
+		"	.section .fixup,\"ax\"\n"	\
+		"3:	move.d %4,%0\n"			\
+		"	jump 5b\n"			\
+		"	moveq 0,%1\n"			\
+		"	.previous\n"			\
+		"	.section __ex_table,\"a\"\n"	\
+		"	.dword 2b,3b\n"			\
+		"	.dword 4b,3b\n"			\
+		"	.previous\n"			\
+		: "=r" (err), "=r" (x),			\
+		  "=b" (dummy_for_get_user_asm_64_)	\
+		: "2" (addr), "g" (-EFAULT), "0" (err));\
+	} while (0)
+
+/*
+ * Copy a null terminated string from userspace.
+ *
+ * Must return:
+ * -EFAULT		for an exception
+ * count		if we hit the buffer limit
+ * bytes copied		if we hit a null byte
+ * (without the null byte)
+ */
+extern inline long
+__do_strncpy_from_user(char *dst, const char *src, long count)
+{
+	long res;
+
+	if (count == 0)
+		return 0;
+
+	/*
+	 * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop.
+	 *  So do we.
+	 *
+	 *  This code is deduced from:
+	 *
+	 *	char tmp2;
+	 *	long tmp1, tmp3;
+	 *	tmp1 = count;
+	 *	while ((*dst++ = (tmp2 = *src++)) != 0
+	 *	       && --tmp1)
+	 *	  ;
+	 *
+	 *	res = count - tmp1;
+	 *
+	 *  with tweaks.
+	 */
+
+	__asm__ __volatile__ (
+		"	move.d %3,%0\n"
+		"5:	move.b [%2+],$acr\n"
+		"1:	beq 2f\n"
+		"	move.b $acr,[%1+]\n"
+
+		"	subq 1,%0\n"
+		"2:	bne 1b\n"
+		"	move.b [%2+],$acr\n"
+
+		"	sub.d %3,%0\n"
+		"	neg.d %0,%0\n"
+		"3:\n"
+		"	.section .fixup,\"ax\"\n"
+		"4:	move.d %7,%0\n"
+		"	jump 3b\n"
+		"	nop\n"
+
+		/* The address for a fault at the first move is trivial.
+		   The address for a fault at the second move is that of
+		   the preceding branch insn, since the move insn is in
+		   its delay-slot.  That address is also a branch
+		   target.  Just so you don't get confused...  */
+		"	.previous\n"
+		"	.section __ex_table,\"a\"\n"
+		"	.dword 5b,4b\n"
+		"	.dword 2b,4b\n"
+		"	.previous"
+		: "=r" (res), "=b" (dst), "=b" (src), "=r" (count)
+		: "3" (count), "1" (dst), "2" (src), "g" (-EFAULT)
+		: "acr");
+
+	return res;
+}
+
+/* A few copy asms to build up the more complex ones from.
+
+   Note again, a post-increment is performed regardless of whether a bus
+   fault occurred in that instruction, and PC for a faulted insn is the
+   address for the insn, or for the preceding branch when in a delay-slot.  */
+
+#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+	__asm__ __volatile__ (				\
+			COPY				\
+		"1:\n"					\
+		"	.section .fixup,\"ax\"\n"	\
+			FIXUP				\
+		"	.previous\n"			\
+		"	.section __ex_table,\"a\"\n"	\
+			TENTRY				\
+		"	.previous\n"			\
+		: "=b" (to), "=b" (from), "=r" (ret)	\
+		: "0" (to), "1" (from), "2" (ret)	\
+		: "acr", "memory")
+
+#define __asm_copy_from_user_1(to, from, ret) \
+	__asm_copy_user_cont(to, from, ret,	\
+		"2:	move.b [%1+],$acr\n"	\
+		"	move.b $acr,[%0+]\n",	\
+		"3:	addq 1,%2\n"		\
+		"	jump 1b\n"		\
+		"	clear.b [%0+]\n",	\
+		"	.dword 2b,3b\n")
+
+#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+	__asm_copy_user_cont(to, from, ret,		\
+			COPY				\
+		"2:	move.w [%1+],$acr\n"		\
+		"	move.w $acr,[%0+]\n",		\
+			FIXUP				\
+		"3:	addq 2,%2\n"			\
+		"	jump 1b\n"			\
+		"	clear.w [%0+]\n",		\
+			TENTRY				\
+		"	.dword 2b,3b\n")
+
+#define __asm_copy_from_user_2(to, from, ret) \
+	__asm_copy_from_user_2x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_from_user_3(to, from, ret)		\
+	__asm_copy_from_user_2x_cont(to, from, ret,	\
+		"4:	move.b [%1+],$acr\n"		\
+		"	move.b $acr,[%0+]\n",		\
+		"5:	addq 1,%2\n"			\
+		"	clear.b [%0+]\n",		\
+		"	.dword 4b,5b\n")
+
+#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+	__asm_copy_user_cont(to, from, ret,		\
+			COPY				\
+		"2:	move.d [%1+],$acr\n"		\
+		"	move.d $acr,[%0+]\n",		\
+			FIXUP				\
+		"3:	addq 4,%2\n"			\
+		"	jump 1b\n"			\
+		"	clear.d [%0+]\n",		\
+			TENTRY				\
+		"	.dword 2b,3b\n")
+
+#define __asm_copy_from_user_4(to, from, ret) \
+	__asm_copy_from_user_4x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_from_user_5(to, from, ret) \
+	__asm_copy_from_user_4x_cont(to, from, ret,	\
+		"4:	move.b [%1+],$acr\n"		\
+		"	move.b $acr,[%0+]\n",		\
+		"5:	addq 1,%2\n"			\
+		"	clear.b [%0+]\n",		\
+		"	.dword 4b,5b\n")
+
+#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+	__asm_copy_from_user_4x_cont(to, from, ret,	\
+			COPY				\
+		"4:	move.w [%1+],$acr\n"		\
+		"	move.w $acr,[%0+]\n",		\
+			FIXUP				\
+		"5:	addq 2,%2\n"			\
+		"	clear.w [%0+]\n",		\
+			TENTRY				\
+		"	.dword 4b,5b\n")
+
+#define __asm_copy_from_user_6(to, from, ret) \
+	__asm_copy_from_user_6x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_from_user_7(to, from, ret) \
+	__asm_copy_from_user_6x_cont(to, from, ret,	\
+		"6:	move.b [%1+],$acr\n"		\
+		"	move.b $acr,[%0+]\n",		\
+		"7:	addq 1,%2\n"			\
+		"	clear.b [%0+]\n",		\
+		"	.dword 6b,7b\n")
+
+#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+	__asm_copy_from_user_4x_cont(to, from, ret,	\
+			COPY				\
+		"4:	move.d [%1+],$acr\n"		\
+		"	move.d $acr,[%0+]\n",		\
+			FIXUP				\
+		"5:	addq 4,%2\n"			\
+		"	clear.d [%0+]\n",		\
+			TENTRY				\
+		"	.dword 4b,5b\n")
+
+#define __asm_copy_from_user_8(to, from, ret) \
+	__asm_copy_from_user_8x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_from_user_9(to, from, ret) \
+	__asm_copy_from_user_8x_cont(to, from, ret,	\
+		"6:	move.b [%1+],$acr\n"		\
+		"	move.b $acr,[%0+]\n",		\
+		"7:	addq 1,%2\n"			\
+		"	clear.b [%0+]\n",		\
+		"	.dword 6b,7b\n")
+
+#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+	__asm_copy_from_user_8x_cont(to, from, ret,	\
+			COPY				\
+		"6:	move.w [%1+],$acr\n"		\
+		"	move.w $acr,[%0+]\n",		\
+			FIXUP				\
+		"7:	addq 2,%2\n"			\
+		"	clear.w [%0+]\n",		\
+			TENTRY				\
+		"	.dword 6b,7b\n")
+
+#define __asm_copy_from_user_10(to, from, ret) \
+	__asm_copy_from_user_10x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_from_user_11(to, from, ret)		\
+	__asm_copy_from_user_10x_cont(to, from, ret,	\
+		"8:	move.b [%1+],$acr\n"		\
+		"	move.b $acr,[%0+]\n",		\
+		"9:	addq 1,%2\n"			\
+		"	clear.b [%0+]\n",		\
+		"	.dword 8b,9b\n")
+
+#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+	__asm_copy_from_user_8x_cont(to, from, ret,	\
+			COPY				\
+		"6:	move.d [%1+],$acr\n"		\
+		"	move.d $acr,[%0+]\n",		\
+			FIXUP				\
+		"7:	addq 4,%2\n"			\
+		"	clear.d [%0+]\n",		\
+			TENTRY				\
+		"	.dword 6b,7b\n")
+
+#define __asm_copy_from_user_12(to, from, ret) \
+	__asm_copy_from_user_12x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_from_user_13(to, from, ret) \
+	__asm_copy_from_user_12x_cont(to, from, ret,	\
+		"8:	move.b [%1+],$acr\n"		\
+		"	move.b $acr,[%0+]\n",		\
+		"9:	addq 1,%2\n"			\
+		"	clear.b [%0+]\n",		\
+		"	.dword 8b,9b\n")
+
+#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+	__asm_copy_from_user_12x_cont(to, from, ret,	\
+			COPY				\
+		"8:	move.w [%1+],$acr\n"		\
+		"	move.w $acr,[%0+]\n",		\
+			FIXUP				\
+		"9:	addq 2,%2\n"			\
+		"	clear.w [%0+]\n",		\
+			TENTRY				\
+		"	.dword 8b,9b\n")
+
+#define __asm_copy_from_user_14(to, from, ret) \
+	__asm_copy_from_user_14x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_from_user_15(to, from, ret) \
+	__asm_copy_from_user_14x_cont(to, from, ret,	\
+		"10:	move.b [%1+],$acr\n"		\
+		"	move.b $acr,[%0+]\n",		\
+		"11:	addq 1,%2\n"			\
+		"	clear.b [%0+]\n",		\
+		"	.dword 10b,11b\n")
+
+#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+	__asm_copy_from_user_12x_cont(to, from, ret,	\
+			COPY				\
+		"8:	move.d [%1+],$acr\n"		\
+		"	move.d $acr,[%0+]\n",		\
+			FIXUP				\
+		"9:	addq 4,%2\n"			\
+		"	clear.d [%0+]\n",		\
+			TENTRY				\
+		"	.dword 8b,9b\n")
+
+#define __asm_copy_from_user_16(to, from, ret) \
+	__asm_copy_from_user_16x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+	__asm_copy_from_user_16x_cont(to, from, ret,	\
+			COPY				\
+		"10:	move.d [%1+],$acr\n"		\
+		"	move.d $acr,[%0+]\n",		\
+			FIXUP				\
+		"11:	addq 4,%2\n"			\
+		"	clear.d [%0+]\n",		\
+			TENTRY				\
+		"	.dword 10b,11b\n")
+
+#define __asm_copy_from_user_20(to, from, ret) \
+	__asm_copy_from_user_20x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+	__asm_copy_from_user_20x_cont(to, from, ret,	\
+			COPY				\
+		"12:	move.d [%1+],$acr\n"		\
+		"	move.d $acr,[%0+]\n",		\
+			FIXUP				\
+		"13:	addq 4,%2\n"			\
+		"	clear.d [%0+]\n",		\
+			TENTRY				\
+		"	.dword 12b,13b\n")
+
+#define __asm_copy_from_user_24(to, from, ret) \
+	__asm_copy_from_user_24x_cont(to, from, ret, "", "", "")
+
+/* And now, the to-user ones.  */
+
+#define __asm_copy_to_user_1(to, from, ret)	\
+	__asm_copy_user_cont(to, from, ret,	\
+		"	move.b [%1+],$acr\n"	\
+		"2:	move.b $acr,[%0+]\n",	\
+		"3:	jump 1b\n"		\
+		"	addq 1,%2\n",		\
+		"	.dword 2b,3b\n")
+
+#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+	__asm_copy_user_cont(to, from, ret,		\
+			COPY				\
+		"	move.w [%1+],$acr\n"		\
+		"2:	move.w $acr,[%0+]\n",		\
+			FIXUP				\
+		"3:	jump 1b\n"			\
+		"	addq 2,%2\n",			\
+			TENTRY				\
+		"	.dword 2b,3b\n")
+
+#define __asm_copy_to_user_2(to, from, ret) \
+	__asm_copy_to_user_2x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_to_user_3(to, from, ret) \
+	__asm_copy_to_user_2x_cont(to, from, ret,	\
+		"	move.b [%1+],$acr\n"		\
+		"4:	move.b $acr,[%0+]\n",		\
+		"5:	addq 1,%2\n",			\
+		"	.dword 4b,5b\n")
+
+#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+	__asm_copy_user_cont(to, from, ret,		\
+			COPY				\
+		"	move.d [%1+],$acr\n"		\
+		"2:	move.d $acr,[%0+]\n",		\
+			FIXUP				\
+		"3:	jump 1b\n"			\
+		"	addq 4,%2\n",			\
+			TENTRY				\
+		"	.dword 2b,3b\n")
+
+#define __asm_copy_to_user_4(to, from, ret) \
+	__asm_copy_to_user_4x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_to_user_5(to, from, ret) \
+	__asm_copy_to_user_4x_cont(to, from, ret,	\
+		"	move.b [%1+],$acr\n"		\
+		"4:	move.b $acr,[%0+]\n",		\
+		"5:	addq 1,%2\n",			\
+		"	.dword 4b,5b\n")
+
+#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+	__asm_copy_to_user_4x_cont(to, from, ret,	\
+			COPY				\
+		"	move.w [%1+],$acr\n"		\
+		"4:	move.w $acr,[%0+]\n",		\
+			FIXUP				\
+		"5:	addq 2,%2\n",			\
+			TENTRY				\
+		"	.dword 4b,5b\n")
+
+#define __asm_copy_to_user_6(to, from, ret) \
+	__asm_copy_to_user_6x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_to_user_7(to, from, ret) \
+	__asm_copy_to_user_6x_cont(to, from, ret,	\
+		"	move.b [%1+],$acr\n"		\
+		"6:	move.b $acr,[%0+]\n",		\
+		"7:	addq 1,%2\n",			\
+		"	.dword 6b,7b\n")
+
+#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+	__asm_copy_to_user_4x_cont(to, from, ret,	\
+			COPY				\
+		"	move.d [%1+],$acr\n"		\
+		"4:	move.d $acr,[%0+]\n",		\
+			FIXUP				\
+		"5:	addq 4,%2\n",			\
+			TENTRY				\
+		"	.dword 4b,5b\n")
+
+#define __asm_copy_to_user_8(to, from, ret) \
+	__asm_copy_to_user_8x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_to_user_9(to, from, ret) \
+	__asm_copy_to_user_8x_cont(to, from, ret,	\
+		"	move.b [%1+],$acr\n"		\
+		"6:	move.b $acr,[%0+]\n",		\
+		"7:	addq 1,%2\n",			\
+		"	.dword 6b,7b\n")
+
+#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+	__asm_copy_to_user_8x_cont(to, from, ret,	\
+			COPY				\
+		"	move.w [%1+],$acr\n"		\
+		"6:	move.w $acr,[%0+]\n",		\
+			FIXUP				\
+		"7:	addq 2,%2\n",			\
+			TENTRY				\
+		"	.dword 6b,7b\n")
+
+#define __asm_copy_to_user_10(to, from, ret) \
+	__asm_copy_to_user_10x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_to_user_11(to, from, ret) \
+	__asm_copy_to_user_10x_cont(to, from, ret,	\
+		"	move.b [%1+],$acr\n"		\
+		"8:	move.b $acr,[%0+]\n",		\
+		"9:	addq 1,%2\n",			\
+		"	.dword 8b,9b\n")
+
+#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+	__asm_copy_to_user_8x_cont(to, from, ret,	\
+			COPY				\
+		"	move.d [%1+],$acr\n"		\
+		"6:	move.d $acr,[%0+]\n",		\
+			FIXUP				\
+		"7:	addq 4,%2\n",			\
+			TENTRY				\
+		"	.dword 6b,7b\n")
+
+#define __asm_copy_to_user_12(to, from, ret) \
+	__asm_copy_to_user_12x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_to_user_13(to, from, ret) \
+	__asm_copy_to_user_12x_cont(to, from, ret,	\
+		"	move.b [%1+],$acr\n"		\
+		"8:	move.b $acr,[%0+]\n",		\
+		"9:	addq 1,%2\n",			\
+		"	.dword 8b,9b\n")
+
+#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+	__asm_copy_to_user_12x_cont(to, from, ret,	\
+			COPY				\
+		"	move.w [%1+],$acr\n"		\
+		"8:	move.w $acr,[%0+]\n",		\
+			FIXUP				\
+		"9:	addq 2,%2\n",			\
+			TENTRY				\
+		"	.dword 8b,9b\n")
+
+#define __asm_copy_to_user_14(to, from, ret)	\
+	__asm_copy_to_user_14x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_to_user_15(to, from, ret) \
+	__asm_copy_to_user_14x_cont(to, from, ret,	\
+		"	move.b [%1+],$acr\n"		\
+		"10:	move.b $acr,[%0+]\n",		\
+		"11:	addq 1,%2\n",			\
+		"	.dword 10b,11b\n")
+
+#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+	__asm_copy_to_user_12x_cont(to, from, ret,	\
+			COPY				\
+		"	move.d [%1+],$acr\n"		\
+		"8:	move.d $acr,[%0+]\n",		\
+			FIXUP				\
+		"9:	addq 4,%2\n",			\
+			TENTRY				\
+		"	.dword 8b,9b\n")
+
+#define __asm_copy_to_user_16(to, from, ret) \
+	__asm_copy_to_user_16x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
+	__asm_copy_to_user_16x_cont(to, from, ret,	\
+			COPY				\
+		"	move.d [%1+],$acr\n"		\
+		"10:	move.d $acr,[%0+]\n",		\
+			FIXUP				\
+		"11:	addq 4,%2\n",			\
+			TENTRY				\
+		"	.dword 10b,11b\n")
+
+#define __asm_copy_to_user_20(to, from, ret) \
+	__asm_copy_to_user_20x_cont(to, from, ret, "", "", "")
+
+#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY)	\
+	__asm_copy_to_user_20x_cont(to, from, ret,	\
+			COPY				\
+		"	move.d [%1+],$acr\n"		\
+		"12:	move.d $acr,[%0+]\n",		\
+			FIXUP				\
+		"13:	addq 4,%2\n",			\
+			TENTRY				\
+		"	.dword 12b,13b\n")
+
+#define __asm_copy_to_user_24(to, from, ret)	\
+	__asm_copy_to_user_24x_cont(to, from, ret, "", "", "")
+
+/* Define a few clearing asms with exception handlers.  */
+
+/* This frame-asm is like the __asm_copy_user_cont one, but has one less
+   input.  */
+
+#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \
+	__asm__ __volatile__ (				\
+			CLEAR				\
+		"1:\n"					\
+		"	.section .fixup,\"ax\"\n"	\
+			FIXUP				\
+		"	.previous\n"			\
+		"	.section __ex_table,\"a\"\n"	\
+			TENTRY				\
+		"	.previous"			\
+		: "=b" (to), "=r" (ret)			\
+		: "0" (to), "1" (ret)			\
+		: "memory")
+
+#define __asm_clear_1(to, ret) \
+	__asm_clear(to, ret,			\
+		"2:	clear.b [%0+]\n",	\
+		"3:	jump 1b\n"		\
+		"	addq 1,%1\n",		\
+		"	.dword 2b,3b\n")
+
+#define __asm_clear_2(to, ret) \
+	__asm_clear(to, ret,			\
+		"2:	clear.w [%0+]\n",	\
+		"3:	jump 1b\n"		\
+		"	addq 2,%1\n",		\
+		"	.dword 2b,3b\n")
+
+#define __asm_clear_3(to, ret) \
+     __asm_clear(to, ret,			\
+		 "2:	clear.w [%0+]\n"	\
+		 "3:	clear.b [%0+]\n",	\
+		 "4:	addq 2,%1\n"		\
+		 "5:	jump 1b\n"		\
+		 "	addq 1,%1\n",		\
+		 "	.dword 2b,4b\n"		\
+		 "	.dword 3b,5b\n")
+
+#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
+	__asm_clear(to, ret,				\
+			CLEAR				\
+		"2:	clear.d [%0+]\n",		\
+			FIXUP				\
+		"3:	jump 1b\n"			\
+		"	addq 4,%1\n",			\
+			TENTRY				\
+		"	.dword 2b,3b\n")
+
+#define __asm_clear_4(to, ret) \
+	__asm_clear_4x_cont(to, ret, "", "", "")
+
+#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
+	__asm_clear_4x_cont(to, ret,			\
+			CLEAR				\
+		"4:	clear.d [%0+]\n",		\
+			FIXUP				\
+		"5:	addq 4,%1\n",			\
+			TENTRY				\
+		"	.dword 4b,5b\n")
+
+#define __asm_clear_8(to, ret) \
+	__asm_clear_8x_cont(to, ret, "", "", "")
+
+#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
+	__asm_clear_8x_cont(to, ret,			\
+			CLEAR				\
+		"6:	clear.d [%0+]\n",		\
+			FIXUP				\
+		"7:	addq 4,%1\n",			\
+			TENTRY				\
+		"	.dword 6b,7b\n")
+
+#define __asm_clear_12(to, ret) \
+	__asm_clear_12x_cont(to, ret, "", "", "")
+
+#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
+	__asm_clear_12x_cont(to, ret,			\
+			CLEAR				\
+		"8:	clear.d [%0+]\n",		\
+			FIXUP				\
+		"9:	addq 4,%1\n",			\
+			TENTRY				\
+		"	.dword 8b,9b\n")
+
+#define __asm_clear_16(to, ret) \
+	__asm_clear_16x_cont(to, ret, "", "", "")
+
+#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
+	__asm_clear_16x_cont(to, ret,			\
+			CLEAR				\
+		"10:	clear.d [%0+]\n",		\
+			FIXUP				\
+		"11:	addq 4,%1\n",			\
+			TENTRY				\
+		"	.dword 10b,11b\n")
+
+#define __asm_clear_20(to, ret) \
+	__asm_clear_20x_cont(to, ret, "", "", "")
+
+#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
+	__asm_clear_20x_cont(to, ret,			\
+			CLEAR				\
+		"12:	clear.d [%0+]\n",		\
+			FIXUP				\
+		"13:	addq 4,%1\n",			\
+			TENTRY				\
+		"	.dword 12b,13b\n")
+
+#define __asm_clear_24(to, ret) \
+	__asm_clear_24x_cont(to, ret, "", "", "")
+
+/*
+ * Return the size of a string (including the ending 0)
+ *
+ * Return length of string in userspace including terminating 0
+ * or 0 for error.  Return a value greater than N if too long.
+ */
+
+extern inline long
+strnlen_user(const char *s, long n)
+{
+	long res, tmp1;
+
+	if (!access_ok(VERIFY_READ, s, 0))
+		return 0;
+
+	/*
+	 * This code is deduced from:
+	 *
+	 *	tmp1 = n;
+	 *	while (tmp1-- > 0 && *s++)
+	 *	  ;
+	 *
+	 *	res = n - tmp1;
+	 *
+	 *  (with tweaks).
+	 */
+
+	__asm__ __volatile__ (
+		"	move.d %1,$acr\n"
+		"	cmpq 0,$acr\n"
+		"0:\n"
+		"	ble 1f\n"
+		"	subq 1,$acr\n"
+
+		"4:	test.b [%0+]\n"
+		"	bne 0b\n"
+		"	cmpq 0,$acr\n"
+		"1:\n"
+		"	move.d %1,%0\n"
+		"	sub.d $acr,%0\n"
+		"2:\n"
+		"	.section .fixup,\"ax\"\n"
+
+		"3:	jump 2b\n"
+		"	clear.d %0\n"
+
+		"	.previous\n"
+		"	.section __ex_table,\"a\"\n"
+		"	.dword 4b,3b\n"
+		"	.previous\n"
+		: "=r" (res), "=r" (tmp1)
+		: "0" (s), "1" (n)
+		: "acr");
+
+	return res;
+}
+
+#endif
diff --git a/include/asm-cris/arch-v32/unistd.h b/include/asm-cris/arch-v32/unistd.h
new file mode 100644
index 00000000000..5d369d4439d
--- /dev/null
+++ b/include/asm-cris/arch-v32/unistd.h
@@ -0,0 +1,148 @@
+#ifndef _ASM_CRIS_ARCH_UNISTD_H_
+#define _ASM_CRIS_ARCH_UNISTD_H_
+
+/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
+/*
+ * Don't remove the .ifnc tests; they are an insurance against
+ * any hard-to-spot gcc register allocation bugs.
+ */
+#define _syscall0(type,name) \
+type name(void) \
+{ \
+  register long __a __asm__ ("r10"); \
+  register long __n_ __asm__ ("r9") = (__NR_##name); \
+  __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
+			".err\n\t" \
+			".endif\n\t" \
+			"break 13" \
+			: "=r" (__a) \
+			: "r" (__n_)); \
+  if (__a >= 0) \
+     return (type) __a; \
+  errno = -__a; \
+  return (type) -1; \
+}
+
+#define _syscall1(type,name,type1,arg1) \
+type name(type1 arg1) \
+{ \
+  register long __a __asm__ ("r10") = (long) arg1; \
+  register long __n_ __asm__ ("r9") = (__NR_##name); \
+  __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
+			".err\n\t" \
+			".endif\n\t" \
+			"break 13" \
+			: "=r" (__a) \
+			: "r" (__n_), "0" (__a)); \
+  if (__a >= 0) \
+     return (type) __a; \
+  errno = -__a; \
+  return (type) -1; \
+}
+
+#define _syscall2(type,name,type1,arg1,type2,arg2) \
+type name(type1 arg1,type2 arg2) \
+{ \
+  register long __a __asm__ ("r10") = (long) arg1; \
+  register long __b __asm__ ("r11") = (long) arg2; \
+  register long __n_ __asm__ ("r9") = (__NR_##name); \
+  __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \
+			".err\n\t" \
+			".endif\n\t" \
+			"break 13" \
+			: "=r" (__a) \
+			: "r" (__n_), "0" (__a), "r" (__b)); \
+  if (__a >= 0) \
+     return (type) __a; \
+  errno = -__a; \
+  return (type) -1; \
+}
+
+#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \
+type name(type1 arg1,type2 arg2,type3 arg3) \
+{ \
+  register long __a __asm__ ("r10") = (long) arg1; \
+  register long __b __asm__ ("r11") = (long) arg2; \
+  register long __c __asm__ ("r12") = (long) arg3; \
+  register long __n_ __asm__ ("r9") = (__NR_##name); \
+  __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \
+			".err\n\t" \
+			".endif\n\t" \
+			"break 13" \
+			: "=r" (__a) \
+			: "r" (__n_), "0" (__a), "r" (__b), "r" (__c)); \
+  if (__a >= 0) \
+     return (type) __a; \
+  errno = -__a; \
+  return (type) -1; \
+}
+
+#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
+type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \
+{ \
+  register long __a __asm__ ("r10") = (long) arg1; \
+  register long __b __asm__ ("r11") = (long) arg2; \
+  register long __c __asm__ ("r12") = (long) arg3; \
+  register long __d __asm__ ("r13") = (long) arg4; \
+  register long __n_ __asm__ ("r9") = (__NR_##name); \
+  __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
+			".err\n\t" \
+			".endif\n\t" \
+			"break 13" \
+			: "=r" (__a) \
+			: "r" (__n_), "0" (__a), "r" (__b), \
+			  "r" (__c), "r" (__d)); \
+  if (__a >= 0) \
+     return (type) __a; \
+  errno = -__a; \
+  return (type) -1; \
+}
+
+#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
+	  type5,arg5) \
+type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \
+{ \
+  register long __a __asm__ ("r10") = (long) arg1; \
+  register long __b __asm__ ("r11") = (long) arg2; \
+  register long __c __asm__ ("r12") = (long) arg3; \
+  register long __d __asm__ ("r13") = (long) arg4; \
+  register long __e __asm__ ("mof") = (long) arg5; \
+  register long __n_ __asm__ ("r9") = (__NR_##name); \
+  __asm__ __volatile__ (".ifnc %0%1%3%4%5%6,$r10$r9$r11$r12$r13$mof\n\t" \
+			".err\n\t" \
+			".endif\n\t" \
+			"break 13" \
+			: "=r" (__a) \
+			: "r" (__n_), "0" (__a), "r" (__b), \
+			  "r" (__c), "r" (__d), "h" (__e)); \
+  if (__a >= 0) \
+     return (type) __a; \
+  errno = -__a; \
+  return (type) -1; \
+}
+
+#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
+	  type5,arg5,type6,arg6) \
+type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \
+{ \
+  register long __a __asm__ ("r10") = (long) arg1; \
+  register long __b __asm__ ("r11") = (long) arg2; \
+  register long __c __asm__ ("r12") = (long) arg3; \
+  register long __d __asm__ ("r13") = (long) arg4; \
+  register long __e __asm__ ("mof") = (long) arg5; \
+  register long __f __asm__ ("srp") = (long) arg6; \
+  register long __n_ __asm__ ("r9") = (__NR_##name); \
+  __asm__ __volatile__ (".ifnc %0%1%3%4%5%6%7,$r10$r9$r11$r12$r13$mof$srp\n\t" \
+			".err\n\t" \
+			".endif\n\t" \
+			"break 13" \
+			: "=r" (__a) \
+			: "r" (__n_), "0" (__a), "r" (__b), \
+			  "r" (__c), "r" (__d), "h" (__e), "x" (__f)); \
+  if (__a >= 0) \
+     return (type) __a; \
+  errno = -__a; \
+  return (type) -1; \
+}
+
+#endif
diff --git a/include/asm-cris/arch-v32/user.h b/include/asm-cris/arch-v32/user.h
new file mode 100644
index 00000000000..03fa1f3c3c0
--- /dev/null
+++ b/include/asm-cris/arch-v32/user.h
@@ -0,0 +1,41 @@
+#ifndef _ASM_CRIS_ARCH_USER_H
+#define _ASM_CRIS_ARCH_USER_H
+
+/* User-mode register used for core dumps. */
+
+struct user_regs_struct {
+	unsigned long r0;	/* General registers. */
+	unsigned long r1;
+	unsigned long r2;
+	unsigned long r3;
+	unsigned long r4;
+	unsigned long r5;
+	unsigned long r6;
+	unsigned long r7;
+	unsigned long r8;
+	unsigned long r9;
+	unsigned long r10;
+	unsigned long r11;
+	unsigned long r12;
+	unsigned long r13;
+	unsigned long sp;	/* R14, Stack pointer. */
+	unsigned long acr;	/* R15, Address calculation register. */
+	unsigned long bz;	/* P0, Constant zero (8-bits). */
+	unsigned long vr;	/* P1, Version register (8-bits). */
+	unsigned long pid;	/* P2, Process ID (8-bits). */
+	unsigned long srs;	/* P3, Support register select (8-bits). */
+	unsigned long wz;	/* P4, Constant zero (16-bits). */
+	unsigned long exs;	/* P5, Exception status. */
+	unsigned long eda;	/* P6, Exception data address. */
+	unsigned long mof;	/* P7, Multiply overflow regiter. */
+	unsigned long dz;	/* P8, Constant zero (32-bits). */
+	unsigned long ebp;	/* P9, Exception base pointer. */
+	unsigned long erp;	/* P10, Exception return pointer. */
+	unsigned long srp;	/* P11, Subroutine return pointer. */
+	unsigned long nrp;	/* P12, NMI return pointer. */
+	unsigned long ccs;	/* P13, Condition code stack. */
+	unsigned long usp;	/* P14, User mode stack pointer. */
+	unsigned long spc;	/* P15, Single step PC. */
+};
+
+#endif /* _ASM_CRIS_ARCH_USER_H */
diff --git a/include/asm-cris/atomic.h b/include/asm-cris/atomic.h
index b3dfea5a71e..70605b09e8b 100644
--- a/include/asm-cris/atomic.h
+++ b/include/asm-cris/atomic.h
@@ -4,21 +4,14 @@
 #define __ASM_CRIS_ATOMIC__
 
 #include <asm/system.h>
+#include <asm/arch/atomic.h>
 
 /*
  * Atomic operations that C can't guarantee us.  Useful for
  * resource counting etc..
  */
 
-/*
- * Make sure gcc doesn't try to be clever and move things around
- * on us. We need to use _exactly_ the address the user gave us,
- * not some alias that contains the same information.
- */
-
-#define __atomic_fool_gcc(x) (*(struct { int a[100]; } *)x)
-
-typedef struct { int counter; } atomic_t;
+typedef struct { volatile int counter; } atomic_t;
 
 #define ATOMIC_INIT(i)  { (i) }
 
@@ -30,29 +23,26 @@ typedef struct { int counter; } atomic_t;
 extern __inline__ void atomic_add(int i, volatile atomic_t *v)
 {
 	unsigned long flags;
-	local_save_flags(flags);
-	local_irq_disable();
+	cris_atomic_save(v, flags);
 	v->counter += i;
-	local_irq_restore(flags);
+	cris_atomic_restore(v, flags);
 }
 
 extern __inline__ void atomic_sub(int i, volatile atomic_t *v)
 {
 	unsigned long flags;
-	local_save_flags(flags);
-	local_irq_disable();
+	cris_atomic_save(v, flags);
 	v->counter -= i;
-	local_irq_restore(flags);
+	cris_atomic_restore(v, flags);
 }
 
 extern __inline__ int atomic_add_return(int i, volatile atomic_t *v)
 {
 	unsigned long flags;
 	int retval;
-	local_save_flags(flags);
-	local_irq_disable();
+	cris_atomic_save(v, flags);
 	retval = (v->counter += i);
-	local_irq_restore(flags);
+	cris_atomic_restore(v, flags);
 	return retval;
 }
 
@@ -62,10 +52,9 @@ extern __inline__ int atomic_sub_return(int i, volatile atomic_t *v)
 {
 	unsigned long flags;
 	int retval;
-	local_save_flags(flags);
-	local_irq_disable();
+	cris_atomic_save(v, flags);
 	retval = (v->counter -= i);
-	local_irq_restore(flags);
+	cris_atomic_restore(v, flags);
 	return retval;
 }
 
@@ -73,39 +62,35 @@ extern __inline__ int atomic_sub_and_test(int i, volatile atomic_t *v)
 {
 	int retval;
 	unsigned long flags;
-	local_save_flags(flags);
-	local_irq_disable();
+	cris_atomic_save(v, flags);
 	retval = (v->counter -= i) == 0;
-	local_irq_restore(flags);
+	cris_atomic_restore(v, flags);
 	return retval;
 }
 
 extern __inline__ void atomic_inc(volatile atomic_t *v)
 {
 	unsigned long flags;
-	local_save_flags(flags);
-	local_irq_disable();
+	cris_atomic_save(v, flags);
 	(v->counter)++;
-	local_irq_restore(flags);
+	cris_atomic_restore(v, flags);
 }
 
 extern __inline__ void atomic_dec(volatile atomic_t *v)
 {
 	unsigned long flags;
-	local_save_flags(flags);
-	local_irq_disable();
+	cris_atomic_save(v, flags);
 	(v->counter)--;
-	local_irq_restore(flags);
+	cris_atomic_restore(v, flags);
 }
 
 extern __inline__ int atomic_inc_return(volatile atomic_t *v)
 {
 	unsigned long flags;
 	int retval;
-	local_save_flags(flags);
-	local_irq_disable();
+	cris_atomic_save(v, flags);
 	retval = (v->counter)++;
-	local_irq_restore(flags);
+	cris_atomic_restore(v, flags);
 	return retval;
 }
 
@@ -113,20 +98,18 @@ extern __inline__ int atomic_dec_return(volatile atomic_t *v)
 {
 	unsigned long flags;
 	int retval;
-	local_save_flags(flags);
-	local_irq_disable();
+	cris_atomic_save(v, flags);
 	retval = (v->counter)--;
-	local_irq_restore(flags);
+	cris_atomic_restore(v, flags);
 	return retval;
 }
 extern __inline__ int atomic_dec_and_test(volatile atomic_t *v)
 {
 	int retval;
 	unsigned long flags;
-	local_save_flags(flags);
-	local_irq_disable();
+	cris_atomic_save(v, flags);
 	retval = --(v->counter) == 0;
-	local_irq_restore(flags);
+	cris_atomic_restore(v, flags);
 	return retval;
 }
 
@@ -134,10 +117,9 @@ extern __inline__ int atomic_inc_and_test(volatile atomic_t *v)
 {
 	int retval;
 	unsigned long flags;
-	local_save_flags(flags);
-	local_irq_disable();
+	cris_atomic_save(v, flags);
 	retval = ++(v->counter) == 0;
-	local_irq_restore(flags);
+	cris_atomic_restore(v, flags);
 	return retval;
 }
 
diff --git a/include/asm-cris/axisflashmap.h b/include/asm-cris/axisflashmap.h
index 600bb8715d8..7a8d3114e68 100644
--- a/include/asm-cris/axisflashmap.h
+++ b/include/asm-cris/axisflashmap.h
@@ -40,4 +40,7 @@ struct partitiontable_entry {
 #define PARTITION_TYPE_KERNEL 0x0002
 #define PARTITION_TYPE_JFFS   0x0003
 
+/* The master mtd for the entire flash. */
+extern struct mtd_info* axisflash_mtd;
+
 #endif
diff --git a/include/asm-cris/bitops.h b/include/asm-cris/bitops.h
index d7861115d73..e3da57f9796 100644
--- a/include/asm-cris/bitops.h
+++ b/include/asm-cris/bitops.h
@@ -16,6 +16,7 @@
 
 #include <asm/arch/bitops.h>
 #include <asm/system.h>
+#include <asm/atomic.h>
 #include <linux/compiler.h>
 
 /*
@@ -88,7 +89,7 @@ struct __dummy { unsigned long a[100]; };
  * It also implies a memory barrier.
  */
 
-extern inline int test_and_set_bit(int nr, void *addr)
+extern inline int test_and_set_bit(int nr, volatile unsigned long *addr)
 {
 	unsigned int mask, retval;
 	unsigned long flags;
@@ -96,15 +97,15 @@ extern inline int test_and_set_bit(int nr, void *addr)
 	
 	adr += nr >> 5;
 	mask = 1 << (nr & 0x1f);
-	local_save_flags(flags);
-	local_irq_disable();
+	cris_atomic_save(addr, flags);
 	retval = (mask & *adr) != 0;
 	*adr |= mask;
+	cris_atomic_restore(addr, flags);
 	local_irq_restore(flags);
 	return retval;
 }
 
-extern inline int __test_and_set_bit(int nr, void *addr)
+extern inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
 {
 	unsigned int mask, retval;
 	unsigned int *adr = (unsigned int *)addr;
@@ -131,7 +132,7 @@ extern inline int __test_and_set_bit(int nr, void *addr)
  * It also implies a memory barrier.
  */
 
-extern inline int test_and_clear_bit(int nr, void *addr)
+extern inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
 {
 	unsigned int mask, retval;
 	unsigned long flags;
@@ -139,11 +140,10 @@ extern inline int test_and_clear_bit(int nr, void *addr)
 	
 	adr += nr >> 5;
 	mask = 1 << (nr & 0x1f);
-	local_save_flags(flags);
-	local_irq_disable();
+	cris_atomic_save(addr, flags);
 	retval = (mask & *adr) != 0;
 	*adr &= ~mask;
-	local_irq_restore(flags);
+	cris_atomic_restore(addr, flags);
 	return retval;
 }
 
@@ -157,7 +157,7 @@ extern inline int test_and_clear_bit(int nr, void *addr)
  * but actually fail.  You must protect multiple accesses with a lock.
  */
 
-extern inline int __test_and_clear_bit(int nr, void *addr)
+extern inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
 {
 	unsigned int mask, retval;
 	unsigned int *adr = (unsigned int *)addr;
@@ -177,24 +177,23 @@ extern inline int __test_and_clear_bit(int nr, void *addr)
  * It also implies a memory barrier.
  */
 
-extern inline int test_and_change_bit(int nr, void *addr)
+extern inline int test_and_change_bit(int nr, volatile unsigned long *addr)
 {
 	unsigned int mask, retval;
 	unsigned long flags;
 	unsigned int *adr = (unsigned int *)addr;
 	adr += nr >> 5;
 	mask = 1 << (nr & 0x1f);
-	local_save_flags(flags);
-	local_irq_disable();
+	cris_atomic_save(addr, flags);
 	retval = (mask & *adr) != 0;
 	*adr ^= mask;
-	local_irq_restore(flags);
+	cris_atomic_restore(addr, flags);
 	return retval;
 }
 
 /* WARNING: non atomic and it can be reordered! */
 
-extern inline int __test_and_change_bit(int nr, void *addr)
+extern inline int __test_and_change_bit(int nr, volatile unsigned long *addr)
 {
 	unsigned int mask, retval;
 	unsigned int *adr = (unsigned int *)addr;
@@ -215,7 +214,7 @@ extern inline int __test_and_change_bit(int nr, void *addr)
  * This routine doesn't need to be atomic.
  */
 
-extern inline int test_bit(int nr, const void *addr)
+extern inline int test_bit(int nr, const volatile unsigned long *addr)
 {
 	unsigned int mask;
 	unsigned int *adr = (unsigned int *)addr;
@@ -259,7 +258,7 @@ extern inline int test_bit(int nr, const void *addr)
  * @offset: The bitnumber to start searching at
  * @size: The maximum size to search
  */
-extern inline int find_next_zero_bit (void * addr, int size, int offset)
+extern inline int find_next_zero_bit (const unsigned long * addr, int size, int offset)
 {
 	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
 	unsigned long result = offset & ~31UL;
@@ -301,7 +300,7 @@ extern inline int find_next_zero_bit (void * addr, int size, int offset)
  * @offset: The bitnumber to start searching at
  * @size: The maximum size to search
  */
-static __inline__ int find_next_bit(void *addr, int size, int offset)
+static __inline__ int find_next_bit(const unsigned long *addr, int size, int offset)
 {
 	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
         unsigned long result = offset & ~31UL;
@@ -367,7 +366,7 @@ found_middle:
 #define minix_test_bit(nr,addr) test_bit(nr,addr)
 #define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
 
-extern inline int sched_find_first_bit(unsigned long *b)
+extern inline int sched_find_first_bit(const unsigned long *b)
 {
 	if (unlikely(b[0]))
 		return __ffs(b[0]);
diff --git a/include/asm-cris/dma-mapping.h b/include/asm-cris/dma-mapping.h
index 0d770f60127..0b5c3fdaefe 100644
--- a/include/asm-cris/dma-mapping.h
+++ b/include/asm-cris/dma-mapping.h
@@ -1,125 +1,179 @@
+/* DMA mapping. Nothing tricky here, just virt_to_phys */
+
 #ifndef _ASM_CRIS_DMA_MAPPING_H
 #define _ASM_CRIS_DMA_MAPPING_H
 
-#include "scatterlist.h"
+#include <linux/mm.h>
+#include <linux/kernel.h>
 
-static inline int
-dma_supported(struct device *dev, u64 mask)
-{
-	BUG();
-	return 0;
-}
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <asm/scatterlist.h>
 
-static inline int
-dma_set_mask(struct device *dev, u64 dma_mask)
-{
-	BUG();
-	return 1;
-}
+#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
+#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
+
+#ifdef CONFIG_PCI
+void *dma_alloc_coherent(struct device *dev, size_t size,
+			   dma_addr_t *dma_handle, int flag);
 
+void dma_free_coherent(struct device *dev, size_t size,
+			 void *vaddr, dma_addr_t dma_handle);
+#else
 static inline void *
 dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
-		   int flag)
+                   int flag)
 {
-	BUG();
-	return NULL;
+        BUG();
+        return NULL;
 }
 
 static inline void
 dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
-		    dma_addr_t dma_handle)
+                    dma_addr_t dma_handle)
 {
-	BUG();
+        BUG();
 }
-
+#endif
 static inline dma_addr_t
-dma_map_single(struct device *dev, void *cpu_addr, size_t size,
+dma_map_single(struct device *dev, void *ptr, size_t size,
 	       enum dma_data_direction direction)
 {
-	BUG();
-	return 0;
+	BUG_ON(direction == DMA_NONE);
+	return virt_to_phys(ptr);
 }
 
 static inline void
 dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
 		 enum dma_data_direction direction)
 {
-	BUG();
+	BUG_ON(direction == DMA_NONE);
+}
+
+static inline int
+dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+	   enum dma_data_direction direction)
+{
+	printk("Map sg\n");
+	return nents;
 }
 
 static inline dma_addr_t
-dma_map_page(struct device *dev, struct page *page,
-	     unsigned long offset, size_t size,
-	     enum dma_data_direction direction)
+dma_map_page(struct device *dev, struct page *page, unsigned long offset,
+	     size_t size, enum dma_data_direction direction)
 {
-	BUG();
-	return 0;
+	BUG_ON(direction == DMA_NONE);
+	return page_to_phys(page) + offset;
 }
 
 static inline void
 dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
 	       enum dma_data_direction direction)
 {
-	BUG();
+	BUG_ON(direction == DMA_NONE);
 }
 
-static inline int
-dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-	   enum dma_data_direction direction)
-{
-	BUG();
-	return 1;
-}
 
 static inline void
 dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
 	     enum dma_data_direction direction)
 {
-	BUG();
+	BUG_ON(direction == DMA_NONE);
 }
 
 static inline void
-dma_sync_single(struct device *dev, dma_addr_t dma_handle, size_t size,
-		enum dma_data_direction direction)
+dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size,
+			enum dma_data_direction direction)
 {
-	BUG();
 }
 
 static inline void
-dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems,
-	    enum dma_data_direction direction)
+dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size,
+			enum dma_data_direction direction)
 {
-	BUG();
 }
 
-/* Now for the API extensions over the pci_ one */
+static inline void
+dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
+			      unsigned long offset, size_t size,
+			      enum dma_data_direction direction)
+{
+}
 
-#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
-#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-#define dma_is_consistent(d)	(1)
+static inline void
+dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
+				 unsigned long offset, size_t size,
+				 enum dma_data_direction direction)
+{
+}
 
-static inline int
-dma_get_cache_alignment(void)
+static inline void
+dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
+		    enum dma_data_direction direction)
 {
-	/* no easy way to get cache size on all processors, so return
-	 * the maximum possible, to be safe */
-	return (1 << L1_CACHE_SHIFT_MAX);
 }
 
 static inline void
-dma_sync_single_range(struct device *dev, dma_addr_t dma_handle,
-		      unsigned long offset, size_t size,
-		      enum dma_data_direction direction)
+dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems,
+		    enum dma_data_direction direction)
 {
-	BUG();
 }
 
+static inline int
+dma_mapping_error(dma_addr_t dma_addr)
+{
+	return 0;
+}
+
+static inline int
+dma_supported(struct device *dev, u64 mask)
+{
+        /*
+         * we fall back to GFP_DMA when the mask isn't all 1s,
+         * so we can't guarantee allocations that must be
+         * within a tighter range than GFP_DMA..
+         */
+        if(mask < 0x00ffffff)
+                return 0;
+
+	return 1;
+}
+
+static inline int
+dma_set_mask(struct device *dev, u64 mask)
+{
+	if(!dev->dma_mask || !dma_supported(dev, mask))
+		return -EIO;
+
+	*dev->dma_mask = mask;
+
+	return 0;
+}
+
+static inline int
+dma_get_cache_alignment(void)
+{
+	return (1 << L1_CACHE_SHIFT_MAX);
+}
+
+#define dma_is_consistent(d)	(1)
+
 static inline void
 dma_cache_sync(void *vaddr, size_t size,
 	       enum dma_data_direction direction)
 {
-	BUG();
 }
 
-#endif
+#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
+extern int
+dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
+			    dma_addr_t device_addr, size_t size, int flags);
+
+extern void
+dma_release_declared_memory(struct device *dev);
 
+extern void *
+dma_mark_declared_memory_occupied(struct device *dev,
+				  dma_addr_t device_addr, size_t size);
+
+#endif
diff --git a/include/asm-cris/dma.h b/include/asm-cris/dma.h
index c229fac35cd..6f188dc5613 100644
--- a/include/asm-cris/dma.h
+++ b/include/asm-cris/dma.h
@@ -10,4 +10,12 @@
 
 #define MAX_DMA_ADDRESS PAGE_OFFSET
 
+/* From PCI */
+
+#ifdef CONFIG_PCI
+extern int isa_dma_bridge_buggy;
+#else
+#define isa_dma_bridge_buggy 	(0)
+#endif
+
 #endif /* _ASM_DMA_H */
diff --git a/include/asm-cris/elf.h b/include/asm-cris/elf.h
index d37fd5c4a56..87a60bd8e66 100644
--- a/include/asm-cris/elf.h
+++ b/include/asm-cris/elf.h
@@ -8,6 +8,27 @@
 #include <asm/arch/elf.h>
 #include <asm/user.h>
 
+#define R_CRIS_NONE             0
+#define R_CRIS_8                1
+#define R_CRIS_16               2
+#define R_CRIS_32               3
+#define R_CRIS_8_PCREL          4
+#define R_CRIS_16_PCREL         5
+#define R_CRIS_32_PCREL         6
+#define R_CRIS_GNU_VTINHERIT    7
+#define R_CRIS_GNU_VTENTRY      8
+#define R_CRIS_COPY             9
+#define R_CRIS_GLOB_DAT         10
+#define R_CRIS_JUMP_SLOT        11
+#define R_CRIS_RELATIVE         12
+#define R_CRIS_16_GOT           13
+#define R_CRIS_32_GOT           14
+#define R_CRIS_16_GOTPLT        15
+#define R_CRIS_32_GOTPLT        16
+#define R_CRIS_32_GOTREL        17
+#define R_CRIS_32_PLT_GOTREL    18
+#define R_CRIS_32_PLT_PCREL     19
+
 typedef unsigned long elf_greg_t;
 
 /* Note that NGREG is defined to ELF_NGREG in include/linux/elfcore.h, and is
@@ -19,17 +40,29 @@ typedef elf_greg_t elf_gregset_t[ELF_NGREG];
 typedef unsigned long elf_fpregset_t;
 
 /*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) ( (x)->e_machine == EM_CRIS )
-
-/*
  * These are used to set parameters in the core dumps.
  */
 #define ELF_CLASS	ELFCLASS32
-#define ELF_DATA	ELFDATA2LSB;
+#define ELF_DATA	ELFDATA2LSB
 #define ELF_ARCH	EM_CRIS
 
+/* The master for these definitions is {binutils}/include/elf/cris.h:  */
+/* User symbols in this file have a leading underscore.  */
+#define EF_CRIS_UNDERSCORE		0x00000001
+
+/* This is a mask for different incompatible machine variants.  */
+#define EF_CRIS_VARIANT_MASK		0x0000000e
+
+/* Variant 0; may contain v0..10 object.  */
+#define EF_CRIS_VARIANT_ANY_V0_V10	0x00000000
+
+/* Variant 1; contains v32 object.  */
+#define EF_CRIS_VARIANT_V32		0x00000002
+
+/* Variant 2; contains object compatible with v32 and v10.  */
+#define EF_CRIS_VARIANT_COMMON_V10_V32	0x00000004
+/* End of excerpt from {binutils}/include/elf/cris.h.  */
+
 #define USE_ELF_CORE_DUMP
 
 #define ELF_EXEC_PAGESIZE	8192
diff --git a/include/asm-cris/etraxgpio.h b/include/asm-cris/etraxgpio.h
index cf04af9635c..80ee10f70d4 100644
--- a/include/asm-cris/etraxgpio.h
+++ b/include/asm-cris/etraxgpio.h
@@ -13,7 +13,7 @@
          are enabled.
  *
  *
- * For ETRAX 200 (ARCH_V32):
+ * For ETRAX FS (ARCH_V32):
  * /dev/gpioa  minor 0,  8 bit GPIO, each bit can change direction
  * /dev/gpiob  minor 1, 18 bit GPIO, each bit can change direction
  * /dev/gpioc  minor 2, 18 bit GPIO, each bit can change direction
@@ -39,10 +39,10 @@
 #define ETRAXGPIO_IOCTYPE 43
 #define GPIO_MINOR_A 0
 #define GPIO_MINOR_B 1
-#define GPIO_MINOR_C 2
-#define GPIO_MINOR_D 3
-#define GPIO_MINOR_E 4
-#define GPIO_MINOR_LEDS 5
+#define GPIO_MINOR_LEDS 2
+#define GPIO_MINOR_C 3
+#define GPIO_MINOR_D 4
+#define GPIO_MINOR_E 5
 #define GPIO_MINOR_LAST 5
 #endif
 
diff --git a/include/asm-cris/hardirq.h b/include/asm-cris/hardirq.h
index f4d136228ee..1c13dd3faac 100644
--- a/include/asm-cris/hardirq.h
+++ b/include/asm-cris/hardirq.h
@@ -1,18 +1,17 @@
 #ifndef __ASM_HARDIRQ_H
 #define __ASM_HARDIRQ_H
 
-/* only non-SMP supported */
-
 #include <linux/threads.h>
 #include <linux/cache.h>
 
-/* entry.S is sensitive to the offsets of these fields */
 typedef struct {
 	unsigned int __softirq_pending;
 } ____cacheline_aligned irq_cpustat_t;
 
 #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
 
+void ack_bad_irq(unsigned int irq);
+
 #define HARDIRQ_BITS	8
 
 /*
diff --git a/include/asm-cris/hw_irq.h b/include/asm-cris/hw_irq.h
new file mode 100644
index 00000000000..341536a234e
--- /dev/null
+++ b/include/asm-cris/hw_irq.h
@@ -0,0 +1,7 @@
+#ifndef _ASM_HW_IRQ_H
+#define _ASM_HW_IRQ_H
+
+static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) {}
+
+#endif
+
diff --git a/include/asm-cris/ide.h b/include/asm-cris/ide.h
new file mode 100644
index 00000000000..a894f66665f
--- /dev/null
+++ b/include/asm-cris/ide.h
@@ -0,0 +1 @@
+#include <asm/arch/ide.h>
diff --git a/include/asm-cris/io.h b/include/asm-cris/io.h
index 1d2b51701e8..16e791b3c72 100644
--- a/include/asm-cris/io.h
+++ b/include/asm-cris/io.h
@@ -3,6 +3,21 @@
 
 #include <asm/page.h>   /* for __va, __pa */
 #include <asm/arch/io.h>
+#include <linux/kernel.h>
+
+struct cris_io_operations
+{
+	u32 (*read_mem)(void *addr, int size);
+	void (*write_mem)(u32 val, int size, void *addr);
+	u32 (*read_io)(u32 port, void *addr, int size, int count);
+	void (*write_io)(u32 port, void *addr, int size, int count);
+};
+
+#ifdef CONFIG_PCI
+extern struct cris_io_operations *cris_iops;
+#else
+#define cris_iops ((struct cris_io_operations*)NULL)
+#endif
 
 /*
  * Change virtual addresses to physical addresses and vv.
@@ -18,14 +33,17 @@ extern inline void * phys_to_virt(unsigned long address)
 	return __va(address);
 }
 
-extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
+extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
+extern void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot);
 
-extern inline void * ioremap (unsigned long offset, unsigned long size)
+extern inline void __iomem * ioremap (unsigned long offset, unsigned long size)
 {
 	return __ioremap(offset, size, 0);
 }
 
-extern void iounmap(void *addr);
+extern void iounmap(volatile void * __iomem addr);
+
+extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size);
 
 /*
  * IO bus memory addresses are also 1:1 with the physical address
@@ -39,9 +57,32 @@ extern void iounmap(void *addr);
  * differently. On the CRIS architecture, we just read/write the
  * memory location directly.
  */
-#define readb(addr) (*(volatile unsigned char *) (addr))
-#define readw(addr) (*(volatile unsigned short *) (addr))
-#define readl(addr) (*(volatile unsigned int *) (addr))
+#ifdef CONFIG_PCI
+#define PCI_SPACE(x) ((((unsigned)(x)) & 0x10000000) == 0x10000000)
+#else
+#define PCI_SPACE(x) 0
+#endif
+static inline unsigned char readb(const volatile void __iomem *addr)
+{
+	if (PCI_SPACE(addr) && cris_iops)
+		return cris_iops->read_mem((void*)addr, 1);
+	else
+		return *(volatile unsigned char __force *) addr;
+}
+static inline unsigned short readw(const volatile void __iomem *addr)
+{
+	if (PCI_SPACE(addr) && cris_iops)
+		return cris_iops->read_mem((void*)addr, 2);
+	else
+		return *(volatile unsigned short __force *) addr;
+}
+static inline unsigned int readl(const volatile void __iomem *addr)
+{
+	if (PCI_SPACE(addr) && cris_iops)
+		return cris_iops->read_mem((void*)addr, 4);
+	else
+		return *(volatile unsigned int __force *) addr;
+}
 #define readb_relaxed(addr) readb(addr)
 #define readw_relaxed(addr) readw(addr)
 #define readl_relaxed(addr) readl(addr)
@@ -49,9 +90,27 @@ extern void iounmap(void *addr);
 #define __raw_readw readw
 #define __raw_readl readl
 
-#define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
+static inline void writeb(unsigned char b, volatile void __iomem *addr)
+{
+	if (PCI_SPACE(addr) && cris_iops)
+		cris_iops->write_mem(b, 1, (void*)addr);
+	else
+		*(volatile unsigned char __force *) addr = b;
+}
+static inline void writew(unsigned short b, volatile void __iomem *addr)
+{
+	if (PCI_SPACE(addr) && cris_iops)
+		cris_iops->write_mem(b, 2, (void*)addr);
+	else
+		*(volatile unsigned short __force *) addr = b;
+}
+static inline void writel(unsigned int b, volatile void __iomem *addr)
+{
+	if (PCI_SPACE(addr) && cris_iops)
+		cris_iops->write_mem(b, 4, (void*)addr);
+	else
+		*(volatile unsigned int __force *) addr = b;
+}
 #define __raw_writeb writeb
 #define __raw_writew writew
 #define __raw_writel writel
@@ -66,25 +125,25 @@ extern void iounmap(void *addr);
  * Again, CRIS does not require mem IO specific function.
  */
 
-#define eth_io_copy_and_sum(a,b,c,d)	eth_copy_and_sum((a),(void *)(b),(c),(d))
+#define eth_io_copy_and_sum(a,b,c,d)	eth_copy_and_sum((a),(void __force *)(b),(c),(d))
 
 /* The following is junk needed for the arch-independent code but which
  * we never use in the CRIS port
  */
 
 #define IO_SPACE_LIMIT 0xffff
-#define inb(x) (0)
-#define inw(x) (0)
-#define inl(x) (0)
-#define outb(x,y)
-#define outw(x,y)
-#define outl(x,y)
-#define insb(x,y,z)
-#define insw(x,y,z)
-#define insl(x,y,z)
-#define outsb(x,y,z)
-#define outsw(x,y,z)
-#define outsl(x,y,z)
+#define inb(port) (cris_iops ? cris_iops->read_io(port,NULL,1,1) : 0)
+#define inw(port) (cris_iops ? cris_iops->read_io(port,NULL,2,1) : 0)
+#define inl(port) (cris_iops ? cris_iops->read_io(port,NULL,4,1) : 0)
+#define insb(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,1,count) : 0)
+#define insw(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,2,count) : 0)
+#define insl(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,4,count) : 0)
+#define outb(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,1,1)
+#define outw(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,2,1)
+#define outl(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,4,1)
+#define outsb(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,1,count)
+#define outsw(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,2,count)
+#define outsl(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,3,count)
 
 /*
  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
diff --git a/include/asm-cris/irq.h b/include/asm-cris/irq.h
index 87f342517bb..8e787fdaedd 100644
--- a/include/asm-cris/irq.h
+++ b/include/asm-cris/irq.h
@@ -8,16 +8,6 @@ extern __inline__ int irq_canonicalize(int irq)
   return irq; 
 }
 
-extern void disable_irq(unsigned int);
-extern void enable_irq(unsigned int);
-
-#define disable_irq_nosync      disable_irq
-#define enable_irq_nosync       enable_irq
-
-struct irqaction;
-struct pt_regs;
-int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
-
 #endif  /* _ASM_IRQ_H */
 
 
diff --git a/include/asm-cris/kmap_types.h b/include/asm-cris/kmap_types.h
index eec0974c241..492988cb907 100644
--- a/include/asm-cris/kmap_types.h
+++ b/include/asm-cris/kmap_types.h
@@ -17,8 +17,8 @@ enum km_type {
 	KM_PTE1,
 	KM_IRQ0,
 	KM_IRQ1,
-	KM_CRYPTO_USER,
-	KM_CRYPTO_SOFTIRQ,
+	KM_SOFTIRQ0,
+	KM_SOFTIRQ1,
 	KM_TYPE_NR
 };
 
diff --git a/include/asm-cris/mmu_context.h b/include/asm-cris/mmu_context.h
index f9308c5bbd9..e6e659dc757 100644
--- a/include/asm-cris/mmu_context.h
+++ b/include/asm-cris/mmu_context.h
@@ -15,7 +15,7 @@ extern void switch_mm(struct mm_struct *prev, struct mm_struct *next,
  * registers like cr3 on the i386
  */
 
-extern volatile pgd_t *current_pgd;   /* defined in arch/cris/mm/fault.c */
+extern volatile DEFINE_PER_CPU(pgd_t *,current_pgd); /* defined in arch/cris/mm/fault.c */
 
 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 {
diff --git a/include/asm-cris/page.h b/include/asm-cris/page.h
index c767da1ef8f..bbf17bd3938 100644
--- a/include/asm-cris/page.h
+++ b/include/asm-cris/page.h
@@ -29,18 +29,15 @@
  */
 #ifndef __ASSEMBLY__
 typedef struct { unsigned long pte; } pte_t;
-typedef struct { unsigned long pmd; } pmd_t;
 typedef struct { unsigned long pgd; } pgd_t;
 typedef struct { unsigned long pgprot; } pgprot_t;
 #endif
 
 #define pte_val(x)	((x).pte)
-#define pmd_val(x)	((x).pmd)
 #define pgd_val(x)	((x).pgd)
 #define pgprot_val(x)	((x).pgprot)
 
 #define __pte(x)	((pte_t) { (x) } )
-#define __pmd(x)	((pmd_t) { (x) } )
 #define __pgd(x)	((pgd_t) { (x) } )
 #define __pgprot(x)	((pgprot_t) { (x) } )
 
@@ -73,10 +70,6 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 
 #ifndef __ASSEMBLY__
 
-#define BUG() do { \
-  printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
-} while (0)
-
 /* Pure 2^n version of get_order */
 static inline int get_order(unsigned long size)
 {
diff --git a/include/asm-cris/pci.h b/include/asm-cris/pci.h
index c6104153188..2064bc1de07 100644
--- a/include/asm-cris/pci.h
+++ b/include/asm-cris/pci.h
@@ -1,13 +1,105 @@
 #ifndef __ASM_CRIS_PCI_H
 #define __ASM_CRIS_PCI_H
 
+#include <linux/config.h>
+
+#ifdef __KERNEL__
+#include <linux/mm.h>		/* for struct page */
+
+/* Can be used to override the logic in pci_scan_bus for skipping
+   already-configured bus numbers - to be used for buggy BIOSes
+   or architectures with incomplete PCI setup by the loader */
+
+#define pcibios_assign_all_busses(void) 1
+
+extern unsigned long pci_mem_start;
+#define PCIBIOS_MIN_IO		0x1000
+#define PCIBIOS_MIN_MEM		0x10000000
+
+#define PCIBIOS_MIN_CARDBUS_IO	0x4000
+
+void pcibios_config_init(void);
+struct pci_bus * pcibios_scan_root(int bus);
+int pcibios_assign_resources(void);
+
+void pcibios_set_master(struct pci_dev *dev);
+void pcibios_penalize_isa_irq(int irq);
+struct irq_routing_table *pcibios_get_irq_routing_table(void);
+int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
+
+/* Dynamic DMA mapping stuff.
+ * i386 has everything mapped statically.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
 #include <asm/scatterlist.h>
-#include <asm-generic/pci-dma-compat.h>
+#include <linux/string.h>
+#include <asm/io.h>
 
-/* ETRAX chips don't have a PCI bus. This file is just here because some stupid .c code
- * includes it even if CONFIG_PCI is not set.
+struct pci_dev;
+
+/* The PCI address space does equal the physical memory
+ * address space.  The networking and block device layers use
+ * this boolean for bounce buffer decisions.
  */
-#define PCI_DMA_BUS_IS_PHYS       (1)
+#define PCI_DMA_BUS_IS_PHYS	(1)
 
-#endif /* __ASM_CRIS_PCI_H */
+/* pci_unmap_{page,single} is a nop so... */
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
+#define pci_unmap_addr(PTR, ADDR_NAME)		(0)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)	do { } while (0)
+#define pci_unmap_len(PTR, LEN_NAME)		(0)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)	do { } while (0)
+
+/* This is always fine. */
+#define pci_dac_dma_supported(pci_dev, mask)	(1)
 
+static inline dma64_addr_t
+pci_dac_page_to_dma(struct pci_dev *pdev, struct page *page, unsigned long offset, int direction)
+{
+	return ((dma64_addr_t) page_to_phys(page) +
+		(dma64_addr_t) offset);
+}
+
+static inline struct page *
+pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr)
+{
+	return pfn_to_page(dma_addr >> PAGE_SHIFT);
+}
+
+static inline unsigned long
+pci_dac_dma_to_offset(struct pci_dev *pdev, dma64_addr_t dma_addr)
+{
+	return (dma_addr & ~PAGE_MASK);
+}
+
+static inline void
+pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction)
+{
+}
+
+static inline void
+pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction)
+{
+}
+
+#define HAVE_PCI_MMAP
+extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
+			       enum pci_mmap_state mmap_state, int write_combine);
+
+
+static inline void pcibios_add_platform_entries(struct pci_dev *dev)
+{
+}
+
+#endif /* __KERNEL__ */
+
+/* implement the pci_ DMA API in terms of the generic device dma_ one */
+#include <asm-generic/pci-dma-compat.h>
+
+/* generic pci stuff */
+#include <asm-generic/pci.h>
+
+#endif /* __ASM_CRIS_PCI_H */
diff --git a/include/asm-cris/pgalloc.h b/include/asm-cris/pgalloc.h
index b202e62ed6e..a131776edf4 100644
--- a/include/asm-cris/pgalloc.h
+++ b/include/asm-cris/pgalloc.h
@@ -47,16 +47,6 @@ extern inline void pte_free(struct page *pte)
 
 #define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte))
 
-/*
- * We don't have any real pmd's, and this code never triggers because
- * the pgd will always be present..
- */
-
-#define pmd_alloc_one(mm, addr)    ({ BUG(); ((pmd_t *)2); })
-#define pmd_free(x)                do { } while (0)
-#define __pmd_free_tlb(tlb,x)      do { } while (0)
-#define pgd_populate(mm, pmd, pte) BUG()
-
 #define check_pgt_cache()          do { } while (0)
 
 #endif
diff --git a/include/asm-cris/pgtable.h b/include/asm-cris/pgtable.h
index f7042944b07..a9143bed99d 100644
--- a/include/asm-cris/pgtable.h
+++ b/include/asm-cris/pgtable.h
@@ -5,7 +5,8 @@
 #ifndef _CRIS_PGTABLE_H
 #define _CRIS_PGTABLE_H
 
-#include <asm-generic/4level-fixup.h>
+#include <asm/page.h>
+#include <asm-generic/pgtable-nopmd.h>
 
 #ifndef __ASSEMBLY__
 #include <linux/config.h>
@@ -41,22 +42,14 @@ extern void paging_init(void);
  * but the define is needed for a generic inline function.)
  */
 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
-#define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval)
+#define set_pgu(pudptr, pudval) (*(pudptr) = pudval)
 
-/* PMD_SHIFT determines the size of the area a second-level page table can
+/* PGDIR_SHIFT determines the size of the area a second-level page table can
  * map. It is equal to the page size times the number of PTE's that fit in
  * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number.
  */
 
-#define PMD_SHIFT	(PAGE_SHIFT + (PAGE_SHIFT-2))
-#define PMD_SIZE	(1UL << PMD_SHIFT)
-#define PMD_MASK	(~(PMD_SIZE-1))
-
-/* PGDIR_SHIFT determines what a third-level page table entry can map.
- * Since we fold into a two-level structure, this is the same as PMD_SHIFT.
- */
-
-#define PGDIR_SHIFT	PMD_SHIFT
+#define PGDIR_SHIFT	(PAGE_SHIFT + (PAGE_SHIFT-2))
 #define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
 #define PGDIR_MASK	(~(PGDIR_SIZE-1))
 
@@ -67,7 +60,6 @@ extern void paging_init(void);
  * divide it by 4 (shift by 2).
  */
 #define PTRS_PER_PTE	(1UL << (PAGE_SHIFT-2))
-#define PTRS_PER_PMD	1
 #define PTRS_PER_PGD	(1UL << (PAGE_SHIFT-2))
 
 /* calculate how many PGD entries a user-level program can use
@@ -105,7 +97,7 @@ extern unsigned long empty_zero_page;
 #define pte_present(x)	(pte_val(x) & _PAGE_PRESENT)
 #define pte_clear(mm,addr,xp)	do { pte_val(*(xp)) = 0; } while (0)
 
-#define pmd_none(x)	(!pmd_val(x))
+#define pmd_none(x)     (!pmd_val(x))
 /* by removing the _PAGE_KERNEL bit from the comparision, the same pmd_bad
  * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries.
  */
@@ -116,16 +108,6 @@ extern unsigned long empty_zero_page;
 #ifndef __ASSEMBLY__
 
 /*
- * The "pgd_xxx()" functions here are trivial for a folded two-level
- * setup: the pgd is never bad, and a pmd always exists (as it's folded
- * into the pgd entry)
- */
-extern inline int pgd_none(pgd_t pgd)		{ return 0; }
-extern inline int pgd_bad(pgd_t pgd)		{ return 0; }
-extern inline int pgd_present(pgd_t pgd)	{ return 1; }
-extern inline void pgd_clear(pgd_t * pgdp)	{ }
-
-/*
  * The following only work if pte_present() is true.
  * Undefined behaviour if not..
  */
@@ -275,7 +257,7 @@ extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
 #define pmd_page_kernel(pmd)	((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
 
 /* to find an entry in a page-table-directory. */
-#define pgd_index(address) ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
+#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
 
 /* to find an entry in a page-table-directory */
 extern inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address)
@@ -286,12 +268,6 @@ extern inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address)
 /* to find an entry in a kernel page-table-directory */
 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 
-/* Find an entry in the second-level page table.. */
-extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
-{
-	return (pmd_t *) dir;
-}
-
 /* Find an entry in the third-level page table.. */
 #define __pte_offset(address) \
 	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
@@ -308,8 +284,6 @@ extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
 
 #define pte_ERROR(e) \
         printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e))
-#define pmd_ERROR(e) \
-        printk("%s:%d: bad pmd %p(%08lx).\n", __FILE__, __LINE__, &(e), pmd_val(e))
 #define pgd_ERROR(e) \
         printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
 
@@ -348,5 +322,7 @@ extern inline void update_mmu_cache(struct vm_area_struct * vma,
 #define pte_to_pgoff(x)	(pte_val(x) >> 6)
 #define pgoff_to_pte(x)	__pte(((x) << 6) | _PAGE_FILE)
 
+typedef pte_t *pte_addr_t;
+
 #endif /* __ASSEMBLY__ */
 #endif /* _CRIS_PGTABLE_H */
diff --git a/include/asm-cris/processor.h b/include/asm-cris/processor.h
index 623bdf06d91..0dc218117bd 100644
--- a/include/asm-cris/processor.h
+++ b/include/asm-cris/processor.h
@@ -55,15 +55,6 @@ unsigned long get_wchan(struct task_struct *p);
 
 #define KSTK_ESP(tsk)   ((tsk) == current ? rdusp() : (tsk)->thread.usp)
 
-/*
- * Free current thread data structures etc..
- */
-
-extern inline void exit_thread(void)
-{
-        /* Nothing needs to be done.  */
-}
-
 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 
 /* Free all resources held by a thread. */
diff --git a/include/asm-cris/ptrace.h b/include/asm-cris/ptrace.h
index 7a8c2880e48..1ec69a7ea83 100644
--- a/include/asm-cris/ptrace.h
+++ b/include/asm-cris/ptrace.h
@@ -9,4 +9,6 @@
 #define PTRACE_SETREGS            13
 #endif
 
+#define profile_pc(regs) instruction_pointer(regs)
+
 #endif /* _CRIS_PTRACE_H */
diff --git a/include/asm-cris/semaphore.h b/include/asm-cris/semaphore.h
index 605aa7eaaaf..8ed7636ab31 100644
--- a/include/asm-cris/semaphore.h
+++ b/include/asm-cris/semaphore.h
@@ -72,10 +72,9 @@ extern inline void down(struct semaphore * sem)
 	might_sleep();
 
 	/* atomically decrement the semaphores count, and if its negative, we wait */
-	local_save_flags(flags);
-	local_irq_disable();
+	cris_atomic_save(sem, flags);
 	failed = --(sem->count.counter) < 0;
-	local_irq_restore(flags);
+	cris_atomic_restore(sem, flags);
 	if(failed) {
 		__down(sem);
 	}
@@ -95,10 +94,9 @@ extern inline int down_interruptible(struct semaphore * sem)
 	might_sleep();
 
 	/* atomically decrement the semaphores count, and if its negative, we wait */
-	local_save_flags(flags);
-	local_irq_disable();
+	cris_atomic_save(sem, flags);
 	failed = --(sem->count.counter) < 0;
-	local_irq_restore(flags);
+	cris_atomic_restore(sem, flags);
 	if(failed)
 		failed = __down_interruptible(sem);
 	return(failed);
@@ -109,13 +107,13 @@ extern inline int down_trylock(struct semaphore * sem)
 	unsigned long flags;
 	int failed;
 
-	local_save_flags(flags);
-	local_irq_disable();
+	cris_atomic_save(sem, flags);
 	failed = --(sem->count.counter) < 0;
-	local_irq_restore(flags);
+	cris_atomic_restore(sem, flags);
 	if(failed)
 		failed = __down_trylock(sem);
 	return(failed);
+
 }
 
 /*
@@ -130,10 +128,9 @@ extern inline void up(struct semaphore * sem)
 	int wakeup;
 
 	/* atomically increment the semaphores count, and if it was negative, we wake people */
-	local_save_flags(flags);
-	local_irq_disable();
+	cris_atomic_save(sem, flags);
 	wakeup = ++(sem->count.counter) <= 0;
-	local_irq_restore(flags);
+	cris_atomic_restore(sem, flags);
 	if(wakeup) {
 		__up(sem);
 	}
diff --git a/include/asm-cris/smp.h b/include/asm-cris/smp.h
index c2f4feaa041..dca5ef1d8c9 100644
--- a/include/asm-cris/smp.h
+++ b/include/asm-cris/smp.h
@@ -1,4 +1,11 @@
 #ifndef __ASM_SMP_H
 #define __ASM_SMP_H
 
+#include <linux/cpumask.h>
+
+extern cpumask_t phys_cpu_present_map;
+#define cpu_possible_map phys_cpu_present_map
+
+#define __smp_processor_id() (current_thread_info()->cpu)
+
 #endif
diff --git a/include/asm-cris/spinlock.h b/include/asm-cris/spinlock.h
new file mode 100644
index 00000000000..2e8ba8afc7a
--- /dev/null
+++ b/include/asm-cris/spinlock.h
@@ -0,0 +1 @@
+#include <asm/arch/spinlock.h>
diff --git a/include/asm-cris/sync_serial.h b/include/asm-cris/sync_serial.h
new file mode 100644
index 00000000000..f930b6e0066
--- /dev/null
+++ b/include/asm-cris/sync_serial.h
@@ -0,0 +1,106 @@
+/*
+ * ioctl defines for synchronous serial port driver
+ *
+ * Copyright (c) 2001-2003 Axis Communications AB
+ *
+ * Author: Mikael Starvik
+ *
+ */
+
+#ifndef SYNC_SERIAL_H
+#define SYNC_SERIAL_H
+
+#include <linux/ioctl.h>
+
+#define SSP_SPEED      _IOR('S', 0, unsigned int)
+#define SSP_MODE       _IOR('S', 1, unsigned int)
+#define SSP_FRAME_SYNC _IOR('S', 2, unsigned int)
+#define SSP_IPOLARITY  _IOR('S', 3, unsigned int)
+#define SSP_OPOLARITY  _IOR('S', 4, unsigned int)
+#define SSP_SPI        _IOR('S', 5, unsigned int)
+#define SSP_INBUFCHUNK _IOR('S', 6, unsigned int)
+
+/* Values for SSP_SPEED */
+#define SSP150        0
+#define SSP300        1
+#define SSP600        2
+#define SSP1200       3
+#define SSP2400       4
+#define SSP4800       5
+#define SSP9600       6
+#define SSP19200      7
+#define SSP28800      8
+#define SSP57600      9
+#define SSP115200    10
+#define SSP230400    11
+#define SSP460800    12
+#define SSP921600    13
+#define SSP3125000   14
+#define CODEC        15
+
+#define FREQ_4MHz   0
+#define FREQ_2MHz   1
+#define FREQ_1MHz   2
+#define FREQ_512kHz 3
+#define FREQ_256kHz 4
+#define FREQ_128kHz 5
+#define FREQ_64kHz  6
+#define FREQ_32kHz  7
+
+/* Used by application to set CODEC divider, word rate and frame rate */
+#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) (CODEC | (freq << 8) | (clk_per_sync << 16) | (sync_per_frame << 28))
+
+/* Used by driver to extract speed */
+#define GET_SPEED(x) (x & 0xff)
+#define GET_FREQ(x) ((x & 0xff00) >> 8)
+#define GET_WORD_RATE(x) (((x & 0x0fff0000) >> 16) - 1)
+#define GET_FRAME_RATE(x) (((x & 0xf0000000) >> 28) - 1)
+
+/* Values for SSP_MODE */
+#define MASTER_OUTPUT 0
+#define SLAVE_OUTPUT  1
+#define MASTER_INPUT  2
+#define SLAVE_INPUT   3
+#define MASTER_BIDIR  4
+#define SLAVE_BIDIR   5
+
+/* Values for SSP_FRAME_SYNC */
+#define NORMAL_SYNC                1
+#define EARLY_SYNC                 2
+
+#define BIT_SYNC                   4
+#define WORD_SYNC                  8
+#define EXTENDED_SYNC           0x10
+
+#define SYNC_OFF                0x20
+#define SYNC_ON                 0x40
+#define WORD_SIZE_8             0x80
+#define WORD_SIZE_12           0x100
+#define WORD_SIZE_16           0x200
+#define WORD_SIZE_24           0x400
+#define WORD_SIZE_32           0x800
+#define BIT_ORDER_LSB         0x1000
+#define BIT_ORDER_MSB         0x2000
+#define FLOW_CONTROL_ENABLE   0x4000
+#define FLOW_CONTROL_DISABLE  0x8000
+#define CLOCK_GATED          0x10000
+#define CLOCK_NOT_GATED      0x20000
+
+/* Values for SSP_IPOLARITY and SSP_OPOLARITY */
+#define CLOCK_NORMAL         1
+#define CLOCK_INVERT         2
+#define CLOCK_INEGEDGE       CLOCK_NORMAL
+#define CLOCK_IPOSEDGE       CLOCK_INVERT
+#define FRAME_NORMAL         4
+#define FRAME_INVERT         8
+#define STATUS_NORMAL      0x10
+#define STATUS_INVERT      0x20
+
+/* Values for SSP_SPI */
+#define SPI_MASTER           0
+#define SPI_SLAVE            1
+
+/* Values for SSP_INBUFCHUNK */
+/* plain integer with the size of DMA chunks */
+
+#endif
diff --git a/include/asm-cris/termbits.h b/include/asm-cris/termbits.h
index 16d9a491fdb..be0836d2f28 100644
--- a/include/asm-cris/termbits.h
+++ b/include/asm-cris/termbits.h
@@ -152,7 +152,7 @@ struct termios {
 #define  B921600   0010005
 #define  B1843200  0010006
 #define  B6250000  0010007
-/* etrax 200 supports this as well */
+/* ETRAX FS supports this as well */
 #define  B12500000 0010010
 #define CIBAUD	  002003600000	/* input baud rate (used in v32) */
 /* The values for CIBAUD bits are the same as the values for CBAUD and CBAUDEX
diff --git a/include/asm-cris/thread_info.h b/include/asm-cris/thread_info.h
index 5ba4b7865cc..cef0140fc10 100644
--- a/include/asm-cris/thread_info.h
+++ b/include/asm-cris/thread_info.h
@@ -43,7 +43,7 @@ struct thread_info {
 
 #endif
 
-#define PREEMPT_ACTIVE		0x4000000
+#define PREEMPT_ACTIVE		0x10000000
 
 /*
  * macros/functions for gaining access to the thread information structure
diff --git a/include/asm-cris/timex.h b/include/asm-cris/timex.h
index 375c41af47d..3fb069a3771 100644
--- a/include/asm-cris/timex.h
+++ b/include/asm-cris/timex.h
@@ -14,7 +14,7 @@
  * used so it does not matter.
  */
 
-typedef unsigned int cycles_t;
+typedef unsigned long long cycles_t;
 
 extern inline cycles_t get_cycles(void)
 {
diff --git a/include/asm-cris/tlbflush.h b/include/asm-cris/tlbflush.h
index 1781fe1a32f..6ed7d9ae90d 100644
--- a/include/asm-cris/tlbflush.h
+++ b/include/asm-cris/tlbflush.h
@@ -18,13 +18,26 @@
  *
  */
 
+extern void __flush_tlb_all(void);
+extern void __flush_tlb_mm(struct mm_struct *mm);
+extern void __flush_tlb_page(struct vm_area_struct *vma,
+			   unsigned long addr);
+
+#ifdef CONFIG_SMP
 extern void flush_tlb_all(void);
 extern void flush_tlb_mm(struct mm_struct *mm);
 extern void flush_tlb_page(struct vm_area_struct *vma, 
 			   unsigned long addr);
-extern void flush_tlb_range(struct vm_area_struct *vma,
-			    unsigned long start,
-			    unsigned long end);
+#else
+#define flush_tlb_all __flush_tlb_all
+#define flush_tlb_mm __flush_tlb_mm
+#define flush_tlb_page __flush_tlb_page
+#endif
+
+static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end)
+{
+	flush_tlb_mm(vma->vm_mm);
+}
 
 extern inline void flush_tlb_pgtables(struct mm_struct *mm,
                                       unsigned long start, unsigned long end)
diff --git a/include/asm-cris/types.h b/include/asm-cris/types.h
index 41a0d450ba1..8fa6d6c7afc 100644
--- a/include/asm-cris/types.h
+++ b/include/asm-cris/types.h
@@ -52,7 +52,7 @@ typedef unsigned long long u64;
 typedef u32 dma_addr_t;
 typedef u32 dma64_addr_t;
 
-typedef unsigned int kmem_bufctl_t;
+typedef unsigned short kmem_bufctl_t;
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/include/asm-cris/unistd.h b/include/asm-cris/unistd.h
index e80bf276b10..28232ad2ff3 100644
--- a/include/asm-cris/unistd.h
+++ b/include/asm-cris/unistd.h
@@ -288,8 +288,15 @@
 #define __NR_mq_timedreceive	(__NR_mq_open+3)
 #define __NR_mq_notify		(__NR_mq_open+4)
 #define __NR_mq_getsetattr	(__NR_mq_open+5)
- 
-#define NR_syscalls 283
+#define __NR_sys_kexec_load	283
+#define __NR_waitid		284
+/* #define __NR_sys_setaltroot	285 */
+#define __NR_add_key		286
+#define __NR_request_key	287
+#define __NR_keyctl		288
+
+#define NR_syscalls 289
+
 
 
 #ifdef __KERNEL__
diff --git a/include/asm-generic/pci.h b/include/asm-generic/pci.h
index 9d4cc47bde3..ee1d8b5d816 100644
--- a/include/asm-generic/pci.h
+++ b/include/asm-generic/pci.h
@@ -22,6 +22,14 @@ pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 	region->end = res->end;
 }
 
+static inline void
+pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+			struct pci_bus_region *region)
+{
+	res->start = region->start;
+	res->end = region->end;
+}
+
 #define pcibios_scan_all_fns(a, b)	0
 
 #ifndef HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 195ccdc069e..450eae22c39 100644
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -11,5 +11,6 @@ extern char _sinittext[], _einittext[];
 extern char _sextratext[] __attribute__((weak));
 extern char _eextratext[] __attribute__((weak));
 extern char _end[];
+extern char __per_cpu_start[], __per_cpu_end[];
 
 #endif /* _ASM_GENERIC_SECTIONS_H_ */
diff --git a/include/asm-i386/bitops.h b/include/asm-i386/bitops.h
index 9db0b712d57..ddf1739dc7f 100644
--- a/include/asm-i386/bitops.h
+++ b/include/asm-i386/bitops.h
@@ -311,6 +311,20 @@ static inline int find_first_zero_bit(const unsigned long *addr, unsigned size)
 int find_next_zero_bit(const unsigned long *addr, int size, int offset);
 
 /**
+ * __ffs - find first bit in word.
+ * @word: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static inline unsigned long __ffs(unsigned long word)
+{
+	__asm__("bsfl %1,%0"
+		:"=r" (word)
+		:"rm" (word));
+	return word;
+}
+
+/**
  * find_first_bit - find the first set bit in a memory region
  * @addr: The address to start the search at
  * @size: The maximum size to search
@@ -320,22 +334,15 @@ int find_next_zero_bit(const unsigned long *addr, int size, int offset);
  */
 static inline int find_first_bit(const unsigned long *addr, unsigned size)
 {
-	int d0, d1;
-	int res;
-
-	/* This looks at memory. Mark it volatile to tell gcc not to move it around */
-	__asm__ __volatile__(
-		"xorl %%eax,%%eax\n\t"
-		"repe; scasl\n\t"
-		"jz 1f\n\t"
-		"leal -4(%%edi),%%edi\n\t"
-		"bsfl (%%edi),%%eax\n"
-		"1:\tsubl %%ebx,%%edi\n\t"
-		"shll $3,%%edi\n\t"
-		"addl %%edi,%%eax"
-		:"=a" (res), "=&c" (d0), "=&D" (d1)
-		:"1" ((size + 31) >> 5), "2" (addr), "b" (addr) : "memory");
-	return res;
+	int x = 0;
+
+	while (x < size) {
+		unsigned long val = *addr++;
+		if (val)
+			return __ffs(val) + x;
+		x += (sizeof(*addr)<<3);
+	}
+	return x;
 }
 
 /**
@@ -360,20 +367,6 @@ static inline unsigned long ffz(unsigned long word)
 	return word;
 }
 
-/**
- * __ffs - find first bit in word.
- * @word: The word to search
- *
- * Undefined if no bit exists, so code should check against 0 first.
- */
-static inline unsigned long __ffs(unsigned long word)
-{
-	__asm__("bsfl %1,%0"
-		:"=r" (word)
-		:"rm" (word));
-	return word;
-}
-
 /*
  * fls: find last bit set.
  */
diff --git a/include/asm-i386/mach-visws/do_timer.h b/include/asm-i386/mach-visws/do_timer.h
index 33acd50fd9a..92d638fc8b1 100644
--- a/include/asm-i386/mach-visws/do_timer.h
+++ b/include/asm-i386/mach-visws/do_timer.h
@@ -1,6 +1,7 @@
 /* defines for inline arch setup functions */
 
 #include <asm/fixmap.h>
+#include <asm/i8259.h>
 #include "cobalt.h"
 
 static inline void do_timer_interrupt_hook(struct pt_regs *regs)
diff --git a/include/asm-i386/pci.h b/include/asm-i386/pci.h
index 78c85985aee..2cbab30734d 100644
--- a/include/asm-i386/pci.h
+++ b/include/asm-i386/pci.h
@@ -18,11 +18,9 @@ extern unsigned int pcibios_assign_all_busses(void);
 #define pcibios_scan_all_fns(a, b)	0
 
 extern unsigned long pci_mem_start;
-#define PCIBIOS_MIN_IO		0x1000
+#define PCIBIOS_MIN_IO		0x4000
 #define PCIBIOS_MIN_MEM		(pci_mem_start)
 
-#define PCIBIOS_MIN_CARDBUS_IO	0x4000
-
 void pcibios_config_init(void);
 struct pci_bus * pcibios_scan_root(int bus);
 
diff --git a/include/asm-i386/ptrace.h b/include/asm-i386/ptrace.h
index b926cb4f4cf..05532875e39 100644
--- a/include/asm-i386/ptrace.h
+++ b/include/asm-i386/ptrace.h
@@ -55,6 +55,9 @@ struct pt_regs {
 #define PTRACE_SET_THREAD_AREA    26
 
 #ifdef __KERNEL__
+
+#include <asm/vm86.h>
+
 struct task_struct;
 extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs, int error_code);
 
diff --git a/include/asm-i386/smp.h b/include/asm-i386/smp.h
index edad9b4712f..a283738b80b 100644
--- a/include/asm-i386/smp.h
+++ b/include/asm-i386/smp.h
@@ -37,9 +37,6 @@ extern int smp_num_siblings;
 extern cpumask_t cpu_sibling_map[];
 extern cpumask_t cpu_core_map[];
 
-extern void smp_flush_tlb(void);
-extern void smp_message_irq(int cpl, void *dev_id, struct pt_regs *regs);
-extern void smp_invalidate_rcv(void);		/* Process an NMI */
 extern void (*mtrr_hook) (void);
 extern void zap_low_mappings (void);
 extern void lock_ipi_call_lock(void);
diff --git a/include/asm-ia64/unistd.h b/include/asm-ia64/unistd.h
index 517f1649ee6..3a0c6952465 100644
--- a/include/asm-ia64/unistd.h
+++ b/include/asm-ia64/unistd.h
@@ -266,6 +266,9 @@
 #define __NR_ioprio_set			1274
 #define __NR_ioprio_get			1275
 #define __NR_set_zone_reclaim		1276
+#define __NR_inotify_init		1277
+#define __NR_inotify_add_watch		1278
+#define __NR_inotify_rm_watch		1279
 
 #ifdef __KERNEL__
 
diff --git a/include/asm-parisc/pci.h b/include/asm-parisc/pci.h
index ee741c15017..98d79a3d54f 100644
--- a/include/asm-parisc/pci.h
+++ b/include/asm-parisc/pci.h
@@ -253,6 +253,10 @@ extern void
 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 			 struct resource *res);
 
+extern void
+pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+			struct pci_bus_region *region);
+
 static inline void pcibios_add_platform_entries(struct pci_dev *dev)
 {
 }
diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h
index c5883dbed63..9483d4bfacf 100644
--- a/include/asm-ppc/cpm2.h
+++ b/include/asm-ppc/cpm2.h
@@ -109,6 +109,7 @@ static inline long IS_DPERR(const uint offset)
  * and dual port ram.
  */
 extern		cpm_cpm2_t	*cpmp;	 /* Pointer to comm processor */
+
 extern uint cpm_dpalloc(uint size, uint align);
 extern int cpm_dpfree(uint offset);
 extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align);
@@ -116,6 +117,8 @@ extern void cpm_dpdump(void);
 extern void *cpm_dpram_addr(uint offset);
 extern void cpm_setbrg(uint brg, uint rate);
 extern void cpm2_fastbrg(uint brg, uint rate, int div16);
+extern void cpm2_reset(void);
+
 
 /* Buffer descriptors used by many of the CPM protocols.
 */
@@ -1087,5 +1090,3 @@ typedef struct im_idma {
 
 #endif /* __CPM2__ */
 #endif /* __KERNEL__ */
-
-
diff --git a/include/asm-ppc/dma-mapping.h b/include/asm-ppc/dma-mapping.h
index 7f0487afebb..6f74f59938d 100644
--- a/include/asm-ppc/dma-mapping.h
+++ b/include/asm-ppc/dma-mapping.h
@@ -117,7 +117,7 @@ dma_map_page(struct device *dev, struct page *page,
 
 	__dma_sync_page(page, offset, size, direction);
 
-	return (page - mem_map) * PAGE_SIZE + PCI_DRAM_OFFSET + offset;
+	return page_to_bus(page) + offset;
 }
 
 /* We do nothing. */
diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h
index 87f051138b9..21e41c9b726 100644
--- a/include/asm-ppc/ibm44x.h
+++ b/include/asm-ppc/ibm44x.h
@@ -35,8 +35,10 @@
 #define PPC44x_LOW_SLOT		63
 
 /* LS 32-bits of UART0 physical address location for early serial text debug */
-#ifdef CONFIG_440SP
+#if defined(CONFIG_440SP)
 #define UART0_PHYS_IO_BASE	0xf0000200
+#elif defined(CONFIG_440EP)
+#define UART0_PHYS_IO_BASE	0xe0000000
 #else
 #define UART0_PHYS_IO_BASE	0x40000200
 #endif
@@ -49,11 +51,16 @@
 /*
  * Standard 4GB "page" definitions
  */
-#ifdef CONFIG_440SP
+#if defined(CONFIG_440SP)
 #define	PPC44x_IO_PAGE		0x0000000100000000ULL
 #define	PPC44x_PCICFG_PAGE	0x0000000900000000ULL
 #define	PPC44x_PCIIO_PAGE	PPC44x_PCICFG_PAGE
 #define	PPC44x_PCIMEM_PAGE	0x0000000a00000000ULL
+#elif defined(CONFIG_440EP)
+#define PPC44x_IO_PAGE		0x0000000000000000ULL
+#define PPC44x_PCICFG_PAGE	0x0000000000000000ULL
+#define PPC44x_PCIIO_PAGE	PPC44x_PCICFG_PAGE
+#define PPC44x_PCIMEM_PAGE	0x0000000000000000ULL
 #else
 #define	PPC44x_IO_PAGE		0x0000000100000000ULL
 #define	PPC44x_PCICFG_PAGE	0x0000000200000000ULL
@@ -64,7 +71,7 @@
 /*
  * 36-bit trap ranges
  */
-#ifdef CONFIG_440SP
+#if defined(CONFIG_440SP)
 #define PPC44x_IO_LO		0xf0000000UL
 #define PPC44x_IO_HI		0xf0000fffUL
 #define PPC44x_PCI0CFG_LO	0x0ec00000UL
@@ -75,6 +82,13 @@
 #define PPC44x_PCI2CFG_HI	0x2ec00007UL
 #define PPC44x_PCIMEM_LO	0x80000000UL
 #define PPC44x_PCIMEM_HI	0xdfffffffUL
+#elif defined(CONFIG_440EP)
+#define PPC44x_IO_LO		0xef500000UL
+#define PPC44x_IO_HI		0xefffffffUL
+#define PPC44x_PCI0CFG_LO	0xeec00000UL
+#define PPC44x_PCI0CFG_HI	0xeecfffffUL
+#define PPC44x_PCIMEM_LO	0xa0000000UL
+#define PPC44x_PCIMEM_HI	0xdfffffffUL
 #else
 #define PPC44x_IO_LO		0x40000000UL
 #define PPC44x_IO_HI		0x40000fffUL
@@ -152,6 +166,12 @@
 #define DCRN_SDR_UART0		0x0120
 #define DCRN_SDR_UART1		0x0121
 
+#ifdef CONFIG_440EP
+#define DCRN_SDR_UART2		0x0122
+#define DCRN_SDR_UART3		0x0123
+#define DCRN_SDR_CUST0		0x4000
+#endif
+
 /* SDR read/write helper macros */
 #define SDR_READ(offset) ({\
 	mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
@@ -169,6 +189,14 @@
 #define DCRNCAP_DMA_SG		1	/* have DMA scatter/gather capability */
 #define DCRN_MAL_BASE		0x180
 
+#ifdef CONFIG_440EP
+#define DCRN_DMA2P40_BASE	0x300
+#define DCRN_DMA2P41_BASE	0x308
+#define DCRN_DMA2P42_BASE	0x310
+#define DCRN_DMA2P43_BASE	0x318
+#define DCRN_DMA2P4SR_BASE	0x320
+#endif
+
 /* UIC */
 #define DCRN_UIC0_BASE	0xc0
 #define DCRN_UIC1_BASE	0xd0
diff --git a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h
index 35260afa33a..e807be96e98 100644
--- a/include/asm-ppc/ibm4xx.h
+++ b/include/asm-ppc/ibm4xx.h
@@ -97,6 +97,10 @@ void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
 
 #elif CONFIG_44x
 
+#if defined(CONFIG_BAMBOO)
+#include <platforms/4xx/bamboo.h>
+#endif
+
 #if defined(CONFIG_EBONY)
 #include <platforms/4xx/ebony.h>
 #endif
diff --git a/include/asm-ppc/ibm_ocp.h b/include/asm-ppc/ibm_ocp.h
index 8c61d93043a..3f7b5669e6d 100644
--- a/include/asm-ppc/ibm_ocp.h
+++ b/include/asm-ppc/ibm_ocp.h
@@ -71,6 +71,8 @@ struct ocp_func_emac_data {
 
 /* Sysfs support */
 #define OCP_SYSFS_EMAC_DATA()						\
+OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_idx)	\
+OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_mux)	\
 OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_idx)	\
 OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_mux)	\
 OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_idx)	\
@@ -78,9 +80,14 @@ OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_rx_chan)	\
 OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_tx_chan)	\
 OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, wol_irq)	\
 OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mdio_idx)	\
+OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, tah_idx)	\
+OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, phy_mode)	\
+OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_map)	\
 									\
 void ocp_show_emac_data(struct device *dev)				\
 {									\
+	device_create_file(dev, &dev_attr_emac_rgmii_idx);		\
+	device_create_file(dev, &dev_attr_emac_rgmii_mux);		\
 	device_create_file(dev, &dev_attr_emac_zmii_idx);		\
 	device_create_file(dev, &dev_attr_emac_zmii_mux);		\
 	device_create_file(dev, &dev_attr_emac_mal_idx);		\
@@ -88,6 +95,9 @@ void ocp_show_emac_data(struct device *dev)				\
 	device_create_file(dev, &dev_attr_emac_mal_tx_chan);		\
 	device_create_file(dev, &dev_attr_emac_wol_irq);		\
 	device_create_file(dev, &dev_attr_emac_mdio_idx);		\
+	device_create_file(dev, &dev_attr_emac_tah_idx);		\
+	device_create_file(dev, &dev_attr_emac_phy_mode);		\
+	device_create_file(dev, &dev_attr_emac_phy_map);		\
 }
 
 #ifdef CONFIG_40x
@@ -157,7 +167,7 @@ OCP_SYSFS_ADDTL(struct ocp_func_iic_data, "%d\n", iic, fast_mode)	\
 									\
 void ocp_show_iic_data(struct device *dev)				\
 {									\
-	device_create_file(dev, &dev_attr_iic_fast_mode);			\
+	device_create_file(dev, &dev_attr_iic_fast_mode);		\
 }
 #endif /* __IBM_OCP_H__ */
 #endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mpc10x.h b/include/asm-ppc/mpc10x.h
index f5196a4efbe..77b1e092c20 100644
--- a/include/asm-ppc/mpc10x.h
+++ b/include/asm-ppc/mpc10x.h
@@ -163,7 +163,8 @@ enum ppc_sys_devices {
 	MPC10X_IIC1,
 	MPC10X_DMA0,
 	MPC10X_DMA1,
-	MPC10X_DUART,
+	MPC10X_UART0,
+	MPC10X_UART1,
 };
 
 int mpc10x_bridge_init(struct pci_controller *hose,
diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h
index a13d55870e6..a811e440c97 100644
--- a/include/asm-ppc/pci.h
+++ b/include/asm-ppc/pci.h
@@ -105,6 +105,10 @@ extern void
 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 			struct resource *res);
 
+extern void
+pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+			struct pci_bus_region *region);
+
 extern void pcibios_add_platform_entries(struct pci_dev *dev);
 
 struct file;
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
index 4d4b20c9de7..92f30b28b25 100644
--- a/include/asm-ppc/pgtable.h
+++ b/include/asm-ppc/pgtable.h
@@ -202,18 +202,64 @@ extern unsigned long ioremap_bot, ioremap_base;
  *
  * Note that these bits preclude future use of a page size
  * less than 4KB.
+ *
+ *
+ * PPC 440 core has following TLB attribute fields;
+ *
+ *   TLB1:
+ *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+ *   RPN.................................  -  -  -  -  -  - ERPN.......
+ *
+ *   TLB2:
+ *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+ *   -  -  -  -  -    - U0 U1 U2 U3 W  I  M  G  E   - UX UW UR SX SW SR
+ *
+ * There are some constrains and options, to decide mapping software bits
+ * into TLB entry.
+ *
+ *   - PRESENT *must* be in the bottom three bits because swap cache
+ *     entries use the top 29 bits for TLB2.
+ *
+ *   - FILE *must* be in the bottom three bits because swap cache
+ *     entries use the top 29 bits for TLB2.
+ *
+ *   - CACHE COHERENT bit (M) has no effect on PPC440 core, because it
+ *     doesn't support SMP. So we can use this as software bit, like
+ *     DIRTY.
+ *
+ * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
+ * for memory protection related functions (see PTE structure in
+ * include/asm-ppc/mmu.h).  The _PAGE_XXX definitions in this file map to the
+ * above bits.  Note that the bit values are CPU specific, not architecture
+ * specific.
+ *
+ * The kernel PTE entry holds an arch-dependent swp_entry structure under
+ * certain situations. In other words, in such situations some portion of
+ * the PTE bits are used as a swp_entry. In the PPC implementation, the
+ * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
+ * hold protection values. That means the three protection bits are
+ * reserved for both PTE and SWAP entry at the most significant three
+ * LSBs.
+ *
+ * There are three protection bits available for SWAP entry:
+ *	_PAGE_PRESENT
+ *	_PAGE_FILE
+ *	_PAGE_HASHPTE (if HW has)
+ *
+ * So those three bits have to be inside of 0-2nd LSB of PTE.
+ *
  */
+
 #define _PAGE_PRESENT	0x00000001		/* S: PTE valid */
 #define	_PAGE_RW	0x00000002		/* S: Write permission */
-#define	_PAGE_DIRTY	0x00000004		/* S: Page dirty */
+#define _PAGE_FILE	0x00000004		/* S: nonlinear file mapping */
 #define _PAGE_ACCESSED	0x00000008		/* S: Page referenced */
 #define _PAGE_HWWRITE	0x00000010		/* H: Dirty & RW */
 #define _PAGE_HWEXEC	0x00000020		/* H: Execute permission */
 #define	_PAGE_USER	0x00000040		/* S: User page */
 #define	_PAGE_ENDIAN	0x00000080		/* H: E bit */
 #define	_PAGE_GUARDED	0x00000100		/* H: G bit */
-#define	_PAGE_COHERENT	0x00000200		/* H: M bit */
-#define _PAGE_FILE	0x00000400		/* S: nonlinear file mapping */
+#define	_PAGE_DIRTY	0x00000200		/* S: Page dirty */
 #define	_PAGE_NO_CACHE	0x00000400		/* H: I bit */
 #define	_PAGE_WRITETHRU	0x00000800		/* H: W bit */
 
diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-ppc/ppc_asm.h
index f76221def48..bb53e2def36 100644
--- a/include/asm-ppc/ppc_asm.h
+++ b/include/asm-ppc/ppc_asm.h
@@ -186,6 +186,12 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #define PPC405_ERR77_SYNC
 #endif
 
+#ifdef CONFIG_IBM440EP_ERR42
+#define PPC440EP_ERR42 isync
+#else
+#define PPC440EP_ERR42
+#endif
+
 /* The boring bits... */
 
 /* Condition Register Bit Fields */
diff --git a/include/asm-ppc/unistd.h b/include/asm-ppc/unistd.h
index a7894e0fbbb..3173ab3d2eb 100644
--- a/include/asm-ppc/unistd.h
+++ b/include/asm-ppc/unistd.h
@@ -279,8 +279,11 @@
 #define __NR_waitid		272
 #define __NR_ioprio_set		273
 #define __NR_ioprio_get		274
+#define __NR_inotify_init	275
+#define __NR_inotify_add_watch	276
+#define __NR_inotify_rm_watch	277
 
-#define __NR_syscalls		275
+#define __NR_syscalls		278
 
 #define __NR(n)	#n
 
diff --git a/include/asm-ppc64/iSeries/HvReleaseData.h b/include/asm-ppc64/iSeries/HvReleaseData.h
index 01a1f13ea4a..c8162e5ccb2 100644
--- a/include/asm-ppc64/iSeries/HvReleaseData.h
+++ b/include/asm-ppc64/iSeries/HvReleaseData.h
@@ -39,6 +39,11 @@
  * know that this PLIC does not support running an OS "that old".
  */
 
+#define	HVREL_TAGSINACTIVE	0x8000
+#define HVREL_32BIT		0x4000
+#define HVREL_NOSHAREDPROCS	0x2000
+#define HVREL_NOHMT		0x1000
+
 struct HvReleaseData {
 	u32	xDesc;		/* Descriptor "HvRD" ebcdic	x00-x03 */
 	u16	xSize;		/* Size of this control block	x04-x05 */
@@ -46,11 +51,7 @@ struct HvReleaseData {
 	struct  naca_struct	*xSlicNacaAddr; /* Virt addr of SLIC NACA x08-x0F */
 	u32	xMsNucDataOffset; /* Offset of Linux Mapping Data x10-x13 */
 	u32	xRsvd1;		/* Reserved			x14-x17 */
-	u16	xTagsMode:1;	/* 0 == tags active, 1 == tags inactive */
-	u16	xAddressSize:1;	/* 0 == 64-bit, 1 == 32-bit */
-	u16	xNoSharedProcs:1; /* 0 == shared procs, 1 == no shared */
-	u16	xNoHMT:1;	/* 0 == allow HMT, 1 == no HMT */
-	u16	xRsvd2:12;	/* Reserved			x18-x19 */
+	u16	xFlags;
 	u16	xVrmIndex;	/* VRM Index of OS image	x1A-x1B */
 	u16	xMinSupportedPlicVrmIndex; /* Min PLIC level  (soft) x1C-x1D */
 	u16	xMinCompatablePlicVrmIndex; /* Min PLIC levelP (hard) x1E-x1F */
diff --git a/include/asm-ppc64/iSeries/LparMap.h b/include/asm-ppc64/iSeries/LparMap.h
index 038e5df7e9f..5c32e38c1c0 100644
--- a/include/asm-ppc64/iSeries/LparMap.h
+++ b/include/asm-ppc64/iSeries/LparMap.h
@@ -49,19 +49,26 @@
  * entry to map the Esid to the Vsid.
 */
 
+#define HvEsidsToMap	2
+#define HvRangesToMap	1
+
 /* Hypervisor initially maps 32MB of the load area */
 #define HvPagesToMap	8192
 
 struct LparMap {
-	u64	xNumberEsids;	// Number of ESID/VSID pairs (1)
-	u64	xNumberRanges;	// Number of VA ranges to map (1)
-	u64	xSegmentTableOffs; // Page number within load area of seg table (0)
+	u64	xNumberEsids;	// Number of ESID/VSID pairs
+	u64	xNumberRanges;	// Number of VA ranges to map
+	u64	xSegmentTableOffs; // Page number within load area of seg table
 	u64	xRsvd[5];
-	u64	xKernelEsid;	// Esid used to map kernel load (0x0C00000000)
-	u64	xKernelVsid;	// Vsid used to map kernel load (0x0C00000000)
-	u64	xPages;		// Number of pages to be mapped	(8192)
-	u64	xOffset;	// Offset from start of load area (0)
-	u64	xVPN;		// Virtual Page Number (0x000C000000000000)
+	struct {
+		u64	xKernelEsid;	// Esid used to map kernel load
+		u64	xKernelVsid;	// Vsid used to map kernel load
+	} xEsids[HvEsidsToMap];
+	struct {
+		u64	xPages;		// Number of pages to be mapped
+		u64	xOffset;	// Offset from start of load area
+		u64	xVPN;		// Virtual Page Number
+	} xRanges[HvRangesToMap];
 };
 
 extern struct LparMap		xLparMap;
diff --git a/include/asm-ppc64/machdep.h b/include/asm-ppc64/machdep.h
index f0c1d2d9267..f0ef0637594 100644
--- a/include/asm-ppc64/machdep.h
+++ b/include/asm-ppc64/machdep.h
@@ -84,7 +84,7 @@ struct machdep_calls {
 
 	void		(*init_IRQ)(void);
 	int		(*get_irq)(struct pt_regs *);
-	void		(*cpu_irq_down)(void);
+	void		(*cpu_irq_down)(int secondary);
 
 	/* PCI stuff */
 	void		(*pcibios_fixup)(void);
diff --git a/include/asm-ppc64/mmu.h b/include/asm-ppc64/mmu.h
index 3d07ddd11e3..70348a85131 100644
--- a/include/asm-ppc64/mmu.h
+++ b/include/asm-ppc64/mmu.h
@@ -200,6 +200,8 @@ extern long native_hpte_insert(unsigned long hpte_group, unsigned long va,
 			       unsigned long prpn,
 			       unsigned long vflags, unsigned long rflags);
 
+extern void stabs_alloc(void);
+
 #endif /* __ASSEMBLY__ */
 
 /*
@@ -336,6 +338,9 @@ static inline unsigned long get_vsid(unsigned long context, unsigned long ea)
 			     | (ea >> SID_SHIFT));
 }
 
+#define VSID_SCRAMBLE(pvsid)	(((pvsid) * VSID_MULTIPLIER) % VSID_MODULUS)
+#define KERNEL_VSID(ea)		VSID_SCRAMBLE(GET_ESID(ea))
+
 #endif /* __ASSEMBLY */
 
 #endif /* _PPC64_MMU_H_ */
diff --git a/include/asm-ppc64/pci.h b/include/asm-ppc64/pci.h
index faa77222307..4d057452f59 100644
--- a/include/asm-ppc64/pci.h
+++ b/include/asm-ppc64/pci.h
@@ -134,6 +134,10 @@ extern void
 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 			struct resource *res);
 
+extern void
+pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+			struct pci_bus_region *region);
+
 extern int
 unmap_bus_range(struct pci_bus *bus);
 
diff --git a/include/asm-ppc64/topology.h b/include/asm-ppc64/topology.h
index fcdcfd26a26..1e9b1907323 100644
--- a/include/asm-ppc64/topology.h
+++ b/include/asm-ppc64/topology.h
@@ -33,6 +33,7 @@ static inline int node_to_first_cpu(int node)
 	return first_cpu(tmp);
 }
 
+#define pcibus_to_node(node)    (-1)
 #define pcibus_to_cpumask(bus)	(cpu_online_map)
 
 #define nr_cpus_node(node)	(nr_cpus_in_node[node])
@@ -59,8 +60,10 @@ static inline int node_to_first_cpu(int node)
 	.nr_balance_failed	= 0,			\
 }
 
-#endif /* CONFIG_NUMA */
+#else
 
 #include <asm-generic/topology.h>
 
+#endif /* CONFIG_NUMA */
+
 #endif /* _ASM_PPC64_TOPOLOGY_H */
diff --git a/include/asm-ppc64/unistd.h b/include/asm-ppc64/unistd.h
index 4a94acf6bfe..977bc980c1a 100644
--- a/include/asm-ppc64/unistd.h
+++ b/include/asm-ppc64/unistd.h
@@ -285,8 +285,11 @@
 #define __NR_waitid		272
 #define __NR_ioprio_set		273
 #define __NR_ioprio_get		274
+#define __NR_inotify_init	275
+#define __NR_inotify_add_watch	276
+#define __NR_inotify_rm_watch	277
 
-#define __NR_syscalls		275
+#define __NR_syscalls		278
 #ifdef __KERNEL__
 #define NR_syscalls	__NR_syscalls
 #endif
diff --git a/include/asm-ppc64/xics.h b/include/asm-ppc64/xics.h
index 0c45e14e26c..1092af55d70 100644
--- a/include/asm-ppc64/xics.h
+++ b/include/asm-ppc64/xics.h
@@ -17,7 +17,7 @@
 void xics_init_IRQ(void);
 int xics_get_irq(struct pt_regs *);
 void xics_setup_cpu(void);
-void xics_teardown_cpu(void);
+void xics_teardown_cpu(int secondary);
 void xics_cause_IPI(int cpu);
 void xics_request_IPIs(void);
 void xics_migrate_irqs_away(void);
diff --git a/include/asm-s390/atomic.h b/include/asm-s390/atomic.h
index d5a05cf4716..9d86ba6f12d 100644
--- a/include/asm-s390/atomic.h
+++ b/include/asm-s390/atomic.h
@@ -123,19 +123,19 @@ typedef struct {
 #define atomic64_read(v)          ((v)->counter)
 #define atomic64_set(v,i)         (((v)->counter) = (i))
 
-static __inline__ void atomic64_add(int i, atomic64_t * v)
+static __inline__ void atomic64_add(long long i, atomic64_t * v)
 {
 	       __CSG_LOOP(v, i, "agr");
 }
-static __inline__ long long atomic64_add_return(int i, atomic64_t * v)
+static __inline__ long long atomic64_add_return(long long i, atomic64_t * v)
 {
 	return __CSG_LOOP(v, i, "agr");
 }
-static __inline__ long long atomic64_add_negative(int i, atomic64_t * v)
+static __inline__ long long atomic64_add_negative(long long i, atomic64_t * v)
 {
 	return __CSG_LOOP(v, i, "agr") < 0;
 }
-static __inline__ void atomic64_sub(int i, atomic64_t * v)
+static __inline__ void atomic64_sub(long long i, atomic64_t * v)
 {
 	       __CSG_LOOP(v, i, "sgr");
 }
diff --git a/include/asm-s390/bitops.h b/include/asm-s390/bitops.h
index 16bb08499c7..8651524217f 100644
--- a/include/asm-s390/bitops.h
+++ b/include/asm-s390/bitops.h
@@ -527,13 +527,64 @@ __constant_test_bit(unsigned long nr, const volatile unsigned long *addr) {
  __constant_test_bit((nr),(addr)) : \
  __test_bit((nr),(addr)) )
 
-#ifndef __s390x__
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+        unsigned long bit = 0;
+
+#ifdef __s390x__
+	if (likely((word & 0xffffffff) == 0xffffffff)) {
+		word >>= 32;
+		bit += 32;
+	}
+#endif
+	if (likely((word & 0xffff) == 0xffff)) {
+		word >>= 16;
+		bit += 16;
+	}
+	if (likely((word & 0xff) == 0xff)) {
+		word >>= 8;
+		bit += 8;
+	}
+	return bit + _zb_findmap[word & 0xff];
+}
+
+/*
+ * __ffs = find first bit in word. Undefined if no bit exists,
+ * so code should check against 0UL first..
+ */
+static inline unsigned long __ffs (unsigned long word)
+{
+	unsigned long bit = 0;
+
+#ifdef __s390x__
+	if (likely((word & 0xffffffff) == 0)) {
+		word >>= 32;
+		bit += 32;
+	}
+#endif
+	if (likely((word & 0xffff) == 0)) {
+		word >>= 16;
+		bit += 16;
+	}
+	if (likely((word & 0xff) == 0)) {
+		word >>= 8;
+		bit += 8;
+	}
+	return bit + _sb_findmap[word & 0xff];
+}
 
 /*
  * Find-bit routines..
  */
+
+#ifndef __s390x__
+
 static inline int
-find_first_zero_bit(const unsigned long * addr, unsigned int size)
+find_first_zero_bit(const unsigned long * addr, unsigned long size)
 {
 	typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype;
 	unsigned long cmp, count;
@@ -548,7 +599,7 @@ find_first_zero_bit(const unsigned long * addr, unsigned int size)
                 "   srl  %2,5\n"
                 "0: c    %1,0(%0,%4)\n"
                 "   jne  1f\n"
-                "   ahi  %0,4\n"
+                "   la   %0,4(%0)\n"
                 "   brct %2,0b\n"
                 "   lr   %0,%3\n"
                 "   j    4f\n"
@@ -574,7 +625,7 @@ find_first_zero_bit(const unsigned long * addr, unsigned int size)
 }
 
 static inline int
-find_first_bit(const unsigned long * addr, unsigned int size)
+find_first_bit(const unsigned long * addr, unsigned long size)
 {
 	typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype;
 	unsigned long cmp, count;
@@ -589,7 +640,7 @@ find_first_bit(const unsigned long * addr, unsigned int size)
                 "   srl  %2,5\n"
                 "0: c    %1,0(%0,%4)\n"
                 "   jne  1f\n"
-                "   ahi  %0,4\n"
+                "   la   %0,4(%0)\n"
                 "   brct %2,0b\n"
                 "   lr   %0,%3\n"
                 "   j    4f\n"
@@ -614,89 +665,8 @@ find_first_bit(const unsigned long * addr, unsigned int size)
         return (res < size) ? res : size;
 }
 
-static inline int
-find_next_zero_bit (const unsigned long * addr, int size, int offset)
-{
-        unsigned long * p = ((unsigned long *) addr) + (offset >> 5);
-        unsigned long bitvec, reg;
-        int set, bit = offset & 31, res;
-
-        if (bit) {
-                /*
-                 * Look for zero in first word
-                 */
-                bitvec = (*p) >> bit;
-                __asm__("   slr  %0,%0\n"
-                        "   lhi  %2,0xff\n"
-                        "   tml  %1,0xffff\n"
-                        "   jno  0f\n"
-                        "   ahi  %0,16\n"
-                        "   srl  %1,16\n"
-                        "0: tml  %1,0x00ff\n"
-                        "   jno  1f\n"
-                        "   ahi  %0,8\n"
-                        "   srl  %1,8\n"
-                        "1: nr   %1,%2\n"
-                        "   ic   %1,0(%1,%3)\n"
-                        "   alr  %0,%1"
-                        : "=&d" (set), "+a" (bitvec), "=&d" (reg)
-                        : "a" (&_zb_findmap) : "cc" );
-                if (set < (32 - bit))
-                        return set + offset;
-                offset += 32 - bit;
-                p++;
-        }
-        /*
-         * No zero yet, search remaining full words for a zero
-         */
-        res = find_first_zero_bit (p, size - 32 * (p - (unsigned long *) addr));
-        return (offset + res);
-}
-
-static inline int
-find_next_bit (const unsigned long * addr, int size, int offset)
-{
-        unsigned long * p = ((unsigned long *) addr) + (offset >> 5);
-        unsigned long bitvec, reg;
-        int set, bit = offset & 31, res;
-
-        if (bit) {
-                /*
-                 * Look for set bit in first word
-                 */
-                bitvec = (*p) >> bit;
-                __asm__("   slr  %0,%0\n"
-                        "   lhi  %2,0xff\n"
-                        "   tml  %1,0xffff\n"
-                        "   jnz  0f\n"
-                        "   ahi  %0,16\n"
-                        "   srl  %1,16\n"
-                        "0: tml  %1,0x00ff\n"
-                        "   jnz  1f\n"
-                        "   ahi  %0,8\n"
-                        "   srl  %1,8\n"
-                        "1: nr   %1,%2\n"
-                        "   ic   %1,0(%1,%3)\n"
-                        "   alr  %0,%1"
-                        : "=&d" (set), "+a" (bitvec), "=&d" (reg)
-                        : "a" (&_sb_findmap) : "cc" );
-                if (set < (32 - bit))
-                        return set + offset;
-                offset += 32 - bit;
-                p++;
-        }
-        /*
-         * No set bit yet, search remaining full words for a bit
-         */
-        res = find_first_bit (p, size - 32 * (p - (unsigned long *) addr));
-        return (offset + res);
-}
-
 #else /* __s390x__ */
 
-/*
- * Find-bit routines..
- */
 static inline unsigned long
 find_first_zero_bit(const unsigned long * addr, unsigned long size)
 {
@@ -712,7 +682,7 @@ find_first_zero_bit(const unsigned long * addr, unsigned long size)
                 "   srlg  %2,%2,6\n"
                 "0: cg    %1,0(%0,%4)\n"
                 "   jne   1f\n"
-                "   aghi  %0,8\n"
+                "   la    %0,8(%0)\n"
                 "   brct  %2,0b\n"
                 "   lgr   %0,%3\n"
                 "   j     5f\n"
@@ -785,143 +755,66 @@ find_first_bit(const unsigned long * addr, unsigned long size)
         return (res < size) ? res : size;
 }
 
-static inline unsigned long
-find_next_zero_bit (const unsigned long * addr, unsigned long size, unsigned long offset)
-{
-        unsigned long * p = ((unsigned long *) addr) + (offset >> 6);
-        unsigned long bitvec, reg;
-        unsigned long set, bit = offset & 63, res;
-
-        if (bit) {
-                /*
-                 * Look for zero in first word
-                 */
-                bitvec = (*p) >> bit;
-                __asm__("   lhi  %2,-1\n"
-                        "   slgr %0,%0\n"
-                        "   clr  %1,%2\n"
-                        "   jne  0f\n"
-                        "   aghi %0,32\n"
-                        "   srlg %1,%1,32\n"
-			"0: lghi %2,0xff\n"
-                        "   tmll %1,0xffff\n"
-                        "   jno  1f\n"
-                        "   aghi %0,16\n"
-                        "   srlg %1,%1,16\n"
-                        "1: tmll %1,0x00ff\n"
-                        "   jno  2f\n"
-                        "   aghi %0,8\n"
-                        "   srlg %1,%1,8\n"
-                        "2: ngr  %1,%2\n"
-                        "   ic   %1,0(%1,%3)\n"
-                        "   algr %0,%1"
-                        : "=&d" (set), "+a" (bitvec), "=&d" (reg)
-                        : "a" (&_zb_findmap) : "cc" );
-                if (set < (64 - bit))
-                        return set + offset;
-                offset += 64 - bit;
-                p++;
-        }
-        /*
-         * No zero yet, search remaining full words for a zero
-         */
-        res = find_first_zero_bit (p, size - 64 * (p - (unsigned long *) addr));
-        return (offset + res);
-}
-
-static inline unsigned long
-find_next_bit (const unsigned long * addr, unsigned long size, unsigned long offset)
-{
-        unsigned long * p = ((unsigned long *) addr) + (offset >> 6);
-        unsigned long bitvec, reg;
-        unsigned long set, bit = offset & 63, res;
-
-        if (bit) {
-                /*
-                 * Look for zero in first word
-                 */
-                bitvec = (*p) >> bit;
-                __asm__("   slgr %0,%0\n"
-                        "   ltr  %1,%1\n"
-                        "   jnz  0f\n"
-                        "   aghi %0,32\n"
-                        "   srlg %1,%1,32\n"
-			"0: lghi %2,0xff\n"
-                        "   tmll %1,0xffff\n"
-                        "   jnz  1f\n"
-                        "   aghi %0,16\n"
-                        "   srlg %1,%1,16\n"
-                        "1: tmll %1,0x00ff\n"
-                        "   jnz  2f\n"
-                        "   aghi %0,8\n"
-                        "   srlg %1,%1,8\n"
-                        "2: ngr  %1,%2\n"
-                        "   ic   %1,0(%1,%3)\n"
-                        "   algr %0,%1"
-                        : "=&d" (set), "+a" (bitvec), "=&d" (reg)
-                        : "a" (&_sb_findmap) : "cc" );
-                if (set < (64 - bit))
-                        return set + offset;
-                offset += 64 - bit;
-                p++;
-        }
-        /*
-         * No set bit yet, search remaining full words for a bit
-         */
-        res = find_first_bit (p, size - 64 * (p - (unsigned long *) addr));
-        return (offset + res);
-}
-
 #endif /* __s390x__ */
 
-/*
- * ffz = Find First Zero in word. Undefined if no zero exists,
- * so code should check against ~0UL first..
- */
-static inline unsigned long ffz(unsigned long word)
+static inline int
+find_next_zero_bit (const unsigned long * addr, unsigned long size,
+		    unsigned long offset)
 {
-        unsigned long bit = 0;
-
-#ifdef __s390x__
-	if (likely((word & 0xffffffff) == 0xffffffff)) {
-		word >>= 32;
-		bit += 32;
-	}
-#endif
-	if (likely((word & 0xffff) == 0xffff)) {
-		word >>= 16;
-		bit += 16;
+        const unsigned long *p;
+	unsigned long bit, set;
+
+	if (offset >= size)
+		return size;
+	bit = offset & (__BITOPS_WORDSIZE - 1);
+	offset -= bit;
+	size -= offset;
+	p = addr + offset / __BITOPS_WORDSIZE;
+	if (bit) {
+		/*
+		 * s390 version of ffz returns __BITOPS_WORDSIZE
+		 * if no zero bit is present in the word.
+		 */
+		set = ffz(*p >> bit) + bit;
+		if (set >= size)
+			return size + offset;
+		if (set < __BITOPS_WORDSIZE)
+			return set + offset;
+		offset += __BITOPS_WORDSIZE;
+		size -= __BITOPS_WORDSIZE;
+		p++;
 	}
-	if (likely((word & 0xff) == 0xff)) {
-		word >>= 8;
-		bit += 8;
-	}
-	return bit + _zb_findmap[word & 0xff];
+	return offset + find_first_zero_bit(p, size);
 }
 
-/*
- * __ffs = find first bit in word. Undefined if no bit exists,
- * so code should check against 0UL first..
- */
-static inline unsigned long __ffs (unsigned long word)
+static inline int
+find_next_bit (const unsigned long * addr, unsigned long size,
+	       unsigned long offset)
 {
-	unsigned long bit = 0;
-
-#ifdef __s390x__
-	if (likely((word & 0xffffffff) == 0)) {
-		word >>= 32;
-		bit += 32;
+        const unsigned long *p;
+	unsigned long bit, set;
+
+	if (offset >= size)
+		return size;
+	bit = offset & (__BITOPS_WORDSIZE - 1);
+	offset -= bit;
+	size -= offset;
+	p = addr + offset / __BITOPS_WORDSIZE;
+	if (bit) {
+		/*
+		 * s390 version of __ffs returns __BITOPS_WORDSIZE
+		 * if no one bit is present in the word.
+		 */
+		set = __ffs(*p & (~0UL << bit));
+		if (set >= size)
+			return size + offset;
+		if (set < __BITOPS_WORDSIZE)
+			return set + offset;
+		offset += __BITOPS_WORDSIZE;
+		size -= __BITOPS_WORDSIZE;
+		p++;
 	}
-#endif
-	if (likely((word & 0xffff) == 0)) {
-		word >>= 16;
-		bit += 16;
-	}
-	if (likely((word & 0xff) == 0)) {
-		word >>= 8;
-		bit += 8;
-	}
-	return bit + _sb_findmap[word & 0xff];
+	return offset + find_first_bit(p, size);
 }
 
 /*
@@ -1031,49 +924,6 @@ ext2_find_first_zero_bit(void *vaddr, unsigned int size)
         return (res < size) ? res : size;
 }
 
-static inline int 
-ext2_find_next_zero_bit(void *vaddr, unsigned int size, unsigned offset)
-{
-        unsigned long *addr = vaddr;
-        unsigned long *p = addr + (offset >> 5);
-        unsigned long word, reg;
-        unsigned int bit = offset & 31UL, res;
-
-        if (offset >= size)
-                return size;
-
-        if (bit) {
-                __asm__("   ic   %0,0(%1)\n"
-                        "   icm  %0,2,1(%1)\n"
-                        "   icm  %0,4,2(%1)\n"
-                        "   icm  %0,8,3(%1)"
-                        : "=&a" (word) : "a" (p) : "cc" );
-		word >>= bit;
-                res = bit;
-                /* Look for zero in first longword */
-                __asm__("   lhi  %2,0xff\n"
-                        "   tml  %1,0xffff\n"
-                	"   jno  0f\n"
-                	"   ahi  %0,16\n"
-                	"   srl  %1,16\n"
-                	"0: tml  %1,0x00ff\n"
-                	"   jno  1f\n"
-                	"   ahi  %0,8\n"
-                	"   srl  %1,8\n"
-                	"1: nr   %1,%2\n"
-                	"   ic   %1,0(%1,%3)\n"
-                	"   alr  %0,%1"
-                	: "+&d" (res), "+&a" (word), "=&d" (reg)
-                  	: "a" (&_zb_findmap) : "cc" );
-                if (res < 32)
-			return (p - addr)*32 + res;
-                p++;
-        }
-        /* No zero yet, search remaining full bytes for a zero */
-        res = ext2_find_first_zero_bit (p, size - 32 * (p - addr));
-        return (p - addr) * 32 + res;
-}
-
 #else /* __s390x__ */
 
 static inline unsigned long
@@ -1120,56 +970,46 @@ ext2_find_first_zero_bit(void *vaddr, unsigned long size)
         return (res < size) ? res : size;
 }
 
-static inline unsigned long
+#endif /* __s390x__ */
+
+static inline int
 ext2_find_next_zero_bit(void *vaddr, unsigned long size, unsigned long offset)
 {
-        unsigned long *addr = vaddr;
-        unsigned long *p = addr + (offset >> 6);
-        unsigned long word, reg;
-        unsigned long bit = offset & 63UL, res;
+        unsigned long *addr = vaddr, *p;
+	unsigned long word, bit, set;
 
         if (offset >= size)
                 return size;
-
+	bit = offset & (__BITOPS_WORDSIZE - 1);
+	offset -= bit;
+	size -= offset;
+	p = addr + offset / __BITOPS_WORDSIZE;
         if (bit) {
-                __asm__("   lrvg %0,%1" /* load reversed, neat instruction */
-                        : "=a" (word) : "m" (*p) );
-                word >>= bit;
-                res = bit;
-                /* Look for zero in first 8 byte word */
-                __asm__("   lghi %2,0xff\n"
-			"   tmll %1,0xffff\n"
-			"   jno  2f\n"
-			"   ahi  %0,16\n"
-			"   srlg %1,%1,16\n"
-                	"0: tmll %1,0xffff\n"
-                        "   jno  2f\n"
-                        "   ahi  %0,16\n"
-                        "   srlg %1,%1,16\n"
-                        "1: tmll %1,0xffff\n"
-                        "   jno  2f\n"
-                        "   ahi  %0,16\n"
-                        "   srl  %1,16\n"
-                        "2: tmll %1,0x00ff\n"
-                	"   jno  3f\n"
-                	"   ahi  %0,8\n"
-                	"   srl  %1,8\n"
-                	"3: ngr  %1,%2\n"
-                	"   ic   %1,0(%1,%3)\n"
-                	"   alr  %0,%1"
-                	: "+&d" (res), "+a" (word), "=&d" (reg)
-                  	: "a" (&_zb_findmap) : "cc" );
-                if (res < 64)
-			return (p - addr)*64 + res;
-                p++;
+#ifndef __s390x__
+                asm("   ic   %0,0(%1)\n"
+		    "   icm  %0,2,1(%1)\n"
+		    "   icm  %0,4,2(%1)\n"
+		    "   icm  %0,8,3(%1)"
+		    : "=&a" (word) : "a" (p), "m" (*p) : "cc" );
+#else
+                asm("   lrvg %0,%1" : "=a" (word) : "m" (*p) );
+#endif
+		/*
+		 * s390 version of ffz returns __BITOPS_WORDSIZE
+		 * if no zero bit is present in the word.
+		 */
+		set = ffz(word >> bit) + bit;
+		if (set >= size)
+			return size + offset;
+		if (set < __BITOPS_WORDSIZE)
+			return set + offset;
+		offset += __BITOPS_WORDSIZE;
+		size -= __BITOPS_WORDSIZE;
+		p++;
         }
-        /* No zero yet, search remaining full bytes for a zero */
-        res = ext2_find_first_zero_bit (p, size - 64 * (p - addr));
-        return (p - addr) * 64 + res;
+	return offset + ext2_find_first_zero_bit(p, size);
 }
 
-#endif /* __s390x__ */
-
 /* Bitmap functions for the minix filesystem.  */
 /* FIXME !!! */
 #define minix_test_and_set_bit(nr,addr) \
diff --git a/include/asm-s390/lowcore.h b/include/asm-s390/lowcore.h
index 76b5b19c0ae..afe6a9f9b0a 100644
--- a/include/asm-s390/lowcore.h
+++ b/include/asm-s390/lowcore.h
@@ -90,7 +90,6 @@
 #define __LC_SYSTEM_TIMER		0x278
 #define __LC_LAST_UPDATE_CLOCK		0x280
 #define __LC_STEAL_CLOCK		0x288
-#define __LC_DIAG44_OPCODE		0x290
 #define __LC_KERNEL_STACK               0xD40
 #define __LC_THREAD_INFO		0xD48
 #define __LC_ASYNC_STACK                0xD50
@@ -286,8 +285,7 @@ struct _lowcore
 	__u64        system_timer;             /* 0x278 */
 	__u64        last_update_clock;        /* 0x280 */
 	__u64        steal_clock;              /* 0x288 */
-	__u32        diag44_opcode;            /* 0x290 */
-        __u8         pad8[0xc00-0x294];        /* 0x294 */
+        __u8         pad8[0xc00-0x290];        /* 0x290 */
         /* System info area */
 	__u64        save_area[16];            /* 0xc00 */
         __u8         pad9[0xd40-0xc80];        /* 0xc80 */
diff --git a/include/asm-s390/processor.h b/include/asm-s390/processor.h
index 8bd14de69e3..4ec652ebb3b 100644
--- a/include/asm-s390/processor.h
+++ b/include/asm-s390/processor.h
@@ -203,7 +203,10 @@ unsigned long get_wchan(struct task_struct *p);
 # define cpu_relax()	asm volatile ("diag 0,0,68" : : : "memory")
 #else /* __s390x__ */
 # define cpu_relax() \
-	asm volatile ("ex 0,%0" : : "i" (__LC_DIAG44_OPCODE) : "memory")
+	do { \
+		if (MACHINE_HAS_DIAG44) \
+			asm volatile ("diag 0,0,68" : : : "memory"); \
+	} while (0)
 #endif /* __s390x__ */
 
 /*
diff --git a/include/asm-s390/spinlock.h b/include/asm-s390/spinlock.h
index 53cc736b982..8ff10300f7e 100644
--- a/include/asm-s390/spinlock.h
+++ b/include/asm-s390/spinlock.h
@@ -11,21 +11,16 @@
 #ifndef __ASM_SPINLOCK_H
 #define __ASM_SPINLOCK_H
 
-#ifdef __s390x__
-/*
- * Grmph, take care of %&#! user space programs that include
- * asm/spinlock.h. The diagnose is only available in kernel
- * context.
- */
-#ifdef __KERNEL__
-#include <asm/lowcore.h>
-#define __DIAG44_INSN "ex"
-#define __DIAG44_OPERAND __LC_DIAG44_OPCODE
-#else
-#define __DIAG44_INSN "#"
-#define __DIAG44_OPERAND 0
-#endif
-#endif /* __s390x__ */
+static inline int
+_raw_compare_and_swap(volatile unsigned int *lock,
+		      unsigned int old, unsigned int new)
+{
+	asm volatile ("cs %0,%3,0(%4)"
+		      : "=d" (old), "=m" (*lock)
+		      : "0" (old), "d" (new), "a" (lock), "m" (*lock)
+		      : "cc", "memory" );
+	return old;
+}
 
 /*
  * Simple spin lock operations.  There are two variants, one clears IRQ's
@@ -41,58 +36,35 @@ typedef struct {
 #endif
 } __attribute__ ((aligned (4))) spinlock_t;
 
-#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 }
-#define spin_lock_init(lp) do { (lp)->lock = 0; } while(0)
+#define SPIN_LOCK_UNLOCKED	(spinlock_t) { 0 }
+#define spin_lock_init(lp)	do { (lp)->lock = 0; } while(0)
 #define spin_unlock_wait(lp)	do { barrier(); } while(((volatile spinlock_t *)(lp))->lock)
-#define spin_is_locked(x) ((x)->lock != 0)
+#define spin_is_locked(x)	((x)->lock != 0)
 #define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
 
-extern inline void _raw_spin_lock(spinlock_t *lp)
+extern void _raw_spin_lock_wait(spinlock_t *lp, unsigned int pc);
+extern int _raw_spin_trylock_retry(spinlock_t *lp, unsigned int pc);
+
+static inline void _raw_spin_lock(spinlock_t *lp)
 {
-#ifndef __s390x__
-	unsigned int reg1, reg2;
-        __asm__ __volatile__("    bras  %0,1f\n"
-                           "0:  diag  0,0,68\n"
-                           "1:  slr   %1,%1\n"
-                           "    cs    %1,%0,0(%3)\n"
-                           "    jl    0b\n"
-                           : "=&d" (reg1), "=&d" (reg2), "=m" (lp->lock)
-			   : "a" (&lp->lock), "m" (lp->lock)
-			   : "cc", "memory" );
-#else /* __s390x__ */
-	unsigned long reg1, reg2;
-        __asm__ __volatile__("    bras  %1,1f\n"
-                           "0:  " __DIAG44_INSN " 0,%4\n"
-                           "1:  slr   %0,%0\n"
-                           "    cs    %0,%1,0(%3)\n"
-                           "    jl    0b\n"
-                           : "=&d" (reg1), "=&d" (reg2), "=m" (lp->lock)
-			   : "a" (&lp->lock), "i" (__DIAG44_OPERAND),
-			     "m" (lp->lock) : "cc", "memory" );
-#endif /* __s390x__ */
+	unsigned long pc = (unsigned long) __builtin_return_address(0);
+
+	if (unlikely(_raw_compare_and_swap(&lp->lock, 0, pc) != 0))
+		_raw_spin_lock_wait(lp, pc);
 }
 
-extern inline int _raw_spin_trylock(spinlock_t *lp)
+static inline int _raw_spin_trylock(spinlock_t *lp)
 {
-	unsigned long reg;
-	unsigned int result;
-
-	__asm__ __volatile__("    basr  %1,0\n"
-			   "0:  cs    %0,%1,0(%3)"
-			   : "=d" (result), "=&d" (reg), "=m" (lp->lock)
-			   : "a" (&lp->lock), "m" (lp->lock), "0" (0)
-			   : "cc", "memory" );
-	return !result;
+	unsigned long pc = (unsigned long) __builtin_return_address(0);
+
+	if (likely(_raw_compare_and_swap(&lp->lock, 0, pc) == 0))
+		return 1;
+	return _raw_spin_trylock_retry(lp, pc);
 }
 
-extern inline void _raw_spin_unlock(spinlock_t *lp)
+static inline void _raw_spin_unlock(spinlock_t *lp)
 {
-	unsigned int old;
-
-	__asm__ __volatile__("cs %0,%3,0(%4)"
-			   : "=d" (old), "=m" (lp->lock)
-			   : "0" (lp->lock), "d" (0), "a" (lp)
-			   : "cc", "memory" );
+	_raw_compare_and_swap(&lp->lock, lp->lock, 0);
 }
 		
 /*
@@ -106,7 +78,7 @@ extern inline void _raw_spin_unlock(spinlock_t *lp)
  * read-locks.
  */
 typedef struct {
-	volatile unsigned long lock;
+	volatile unsigned int lock;
 	volatile unsigned long owner_pc;
 #ifdef CONFIG_PREEMPT
 	unsigned int break_lock;
@@ -129,123 +101,55 @@ typedef struct {
  */
 #define write_can_lock(x) ((x)->lock == 0)
 
-#ifndef __s390x__
-#define _raw_read_lock(rw)   \
-        asm volatile("   l     2,0(%1)\n"   \
-                     "   j     1f\n"     \
-                     "0: diag  0,0,68\n" \
-                     "1: la    2,0(2)\n"     /* clear high (=write) bit */ \
-                     "   la    3,1(2)\n"     /* one more reader */ \
-                     "   cs    2,3,0(%1)\n"  /* try to write new value */ \
-                     "   jl    0b"       \
-                     : "=m" ((rw)->lock) : "a" (&(rw)->lock), \
-		       "m" ((rw)->lock) : "2", "3", "cc", "memory" )
-#else /* __s390x__ */
-#define _raw_read_lock(rw)   \
-        asm volatile("   lg    2,0(%1)\n"   \
-                     "   j     1f\n"     \
-                     "0: " __DIAG44_INSN " 0,%2\n" \
-                     "1: nihh  2,0x7fff\n" /* clear high (=write) bit */ \
-                     "   la    3,1(2)\n"   /* one more reader */  \
-                     "   csg   2,3,0(%1)\n" /* try to write new value */ \
-                     "   jl    0b"       \
-                     : "=m" ((rw)->lock) \
-		     : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \
-		       "m" ((rw)->lock) : "2", "3", "cc", "memory" )
-#endif /* __s390x__ */
-
-#ifndef __s390x__
-#define _raw_read_unlock(rw) \
-        asm volatile("   l     2,0(%1)\n"   \
-                     "   j     1f\n"     \
-                     "0: diag  0,0,68\n" \
-                     "1: lr    3,2\n"    \
-                     "   ahi   3,-1\n"    /* one less reader */ \
-                     "   cs    2,3,0(%1)\n" \
-                     "   jl    0b"       \
-                     : "=m" ((rw)->lock) : "a" (&(rw)->lock), \
-		       "m" ((rw)->lock) : "2", "3", "cc", "memory" )
-#else /* __s390x__ */
-#define _raw_read_unlock(rw) \
-        asm volatile("   lg    2,0(%1)\n"   \
-                     "   j     1f\n"     \
-                     "0: " __DIAG44_INSN " 0,%2\n" \
-                     "1: lgr   3,2\n"    \
-                     "   bctgr 3,0\n"    /* one less reader */ \
-                     "   csg   2,3,0(%1)\n" \
-                     "   jl    0b"       \
-                     : "=m" ((rw)->lock) \
-		     : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \
-		       "m" ((rw)->lock) : "2", "3", "cc", "memory" )
-#endif /* __s390x__ */
-
-#ifndef __s390x__
-#define _raw_write_lock(rw) \
-        asm volatile("   lhi   3,1\n"    \
-                     "   sll   3,31\n"    /* new lock value = 0x80000000 */ \
-                     "   j     1f\n"     \
-                     "0: diag  0,0,68\n" \
-                     "1: slr   2,2\n"     /* old lock value must be 0 */ \
-                     "   cs    2,3,0(%1)\n" \
-                     "   jl    0b"       \
-                     : "=m" ((rw)->lock) : "a" (&(rw)->lock), \
-		       "m" ((rw)->lock) : "2", "3", "cc", "memory" )
-#else /* __s390x__ */
-#define _raw_write_lock(rw) \
-        asm volatile("   llihh 3,0x8000\n" /* new lock value = 0x80...0 */ \
-                     "   j     1f\n"       \
-                     "0: " __DIAG44_INSN " 0,%2\n"   \
-                     "1: slgr  2,2\n"      /* old lock value must be 0 */ \
-                     "   csg   2,3,0(%1)\n" \
-                     "   jl    0b"         \
-                     : "=m" ((rw)->lock) \
-		     : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \
-		       "m" ((rw)->lock) : "2", "3", "cc", "memory" )
-#endif /* __s390x__ */
-
-#ifndef __s390x__
-#define _raw_write_unlock(rw) \
-        asm volatile("   slr   3,3\n"     /* new lock value = 0 */ \
-                     "   j     1f\n"     \
-                     "0: diag  0,0,68\n" \
-                     "1: lhi   2,1\n"    \
-                     "   sll   2,31\n"    /* old lock value must be 0x80000000 */ \
-                     "   cs    2,3,0(%1)\n" \
-                     "   jl    0b"       \
-                     : "=m" ((rw)->lock) : "a" (&(rw)->lock), \
-		       "m" ((rw)->lock) : "2", "3", "cc", "memory" )
-#else /* __s390x__ */
-#define _raw_write_unlock(rw) \
-        asm volatile("   slgr  3,3\n"      /* new lock value = 0 */ \
-                     "   j     1f\n"       \
-                     "0: " __DIAG44_INSN " 0,%2\n"   \
-                     "1: llihh 2,0x8000\n" /* old lock value must be 0x8..0 */\
-                     "   csg   2,3,0(%1)\n"   \
-                     "   jl    0b"         \
-                     : "=m" ((rw)->lock) \
-		     : "a" (&(rw)->lock), "i" (__DIAG44_OPERAND), \
-		       "m" ((rw)->lock) : "2", "3", "cc", "memory" )
-#endif /* __s390x__ */
-
-#define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
-
-extern inline int _raw_write_trylock(rwlock_t *rw)
+extern void _raw_read_lock_wait(rwlock_t *lp);
+extern int _raw_read_trylock_retry(rwlock_t *lp);
+extern void _raw_write_lock_wait(rwlock_t *lp);
+extern int _raw_write_trylock_retry(rwlock_t *lp);
+
+static inline void _raw_read_lock(rwlock_t *rw)
+{
+	unsigned int old;
+	old = rw->lock & 0x7fffffffU;
+	if (_raw_compare_and_swap(&rw->lock, old, old + 1) != old)
+		_raw_read_lock_wait(rw);
+}
+
+static inline void _raw_read_unlock(rwlock_t *rw)
+{
+	unsigned int old, cmp;
+
+	old = rw->lock;
+	do {
+		cmp = old;
+		old = _raw_compare_and_swap(&rw->lock, old, old - 1);
+	} while (cmp != old);
+}
+
+static inline void _raw_write_lock(rwlock_t *rw)
+{
+	if (unlikely(_raw_compare_and_swap(&rw->lock, 0, 0x80000000) != 0))
+		_raw_write_lock_wait(rw);
+}
+
+static inline void _raw_write_unlock(rwlock_t *rw)
+{
+	_raw_compare_and_swap(&rw->lock, 0x80000000, 0);
+}
+
+static inline int _raw_read_trylock(rwlock_t *rw)
+{
+	unsigned int old;
+	old = rw->lock & 0x7fffffffU;
+	if (likely(_raw_compare_and_swap(&rw->lock, old, old + 1) == old))
+		return 1;
+	return _raw_read_trylock_retry(rw);
+}
+
+static inline int _raw_write_trylock(rwlock_t *rw)
 {
-	unsigned long result, reg;
-	
-	__asm__ __volatile__(
-#ifndef __s390x__
-			     "   lhi  %1,1\n"
-			     "   sll  %1,31\n"
-			     "   cs   %0,%1,0(%3)"
-#else /* __s390x__ */
-			     "   llihh %1,0x8000\n"
-			     "0: csg %0,%1,0(%3)\n"
-#endif /* __s390x__ */
-			     : "=d" (result), "=&d" (reg), "=m" (rw->lock)
-			     : "a" (&rw->lock), "m" (rw->lock), "0" (0UL)
-			     : "cc", "memory" );
-	return result == 0;
+	if (likely(_raw_compare_and_swap(&rw->lock, 0, 0x80000000) == 0))
+		return 1;
+	return _raw_write_trylock_retry(rw);
 }
 
 #endif /* __ASM_SPINLOCK_H */
diff --git a/include/asm-s390/unistd.h b/include/asm-s390/unistd.h
index 363db45f8d0..221e965da92 100644
--- a/include/asm-s390/unistd.h
+++ b/include/asm-s390/unistd.h
@@ -274,8 +274,13 @@
 #define __NR_request_key	279
 #define __NR_keyctl		280
 #define __NR_waitid		281
+#define __NR_ioprio_set		282
+#define __NR_ioprio_get		283
+#define __NR_inotify_init	284
+#define __NR_inotify_add_watch	285
+#define __NR_inotify_rm_watch	286
 
-#define NR_syscalls 282
+#define NR_syscalls 287
 
 /* 
  * There are some system calls that are not present on 64 bit, some
diff --git a/include/asm-sparc/unistd.h b/include/asm-sparc/unistd.h
index aee17d7e2e4..58dba518239 100644
--- a/include/asm-sparc/unistd.h
+++ b/include/asm-sparc/unistd.h
@@ -167,12 +167,12 @@
 #define __NR_pciconfig_read	148 /* ENOSYS under SunOS                          */
 #define __NR_pciconfig_write	149 /* ENOSYS under SunOS                          */
 #define __NR_getsockname        150 /* Common                                      */
-/* #define __NR_getmsg          151    SunOS Specific                              */
-/* #define __NR_putmsg          152    SunOS Specific                              */
+#define __NR_inotify_init       151 /* Linux specific                              */
+#define __NR_inotify_add_watch  152 /* Linux specific                              */
 #define __NR_poll               153 /* Common                                      */
 #define __NR_getdents64		154 /* Linux specific				   */
 #define __NR_fcntl64		155 /* Linux sparc32 Specific                      */
-/* #define __NR_getdirentires 	156    SunOS Specific                              */
+#define __NR_inotify_rm_watch   156 /* Linux specific				   */
 #define __NR_statfs             157 /* Common                                      */
 #define __NR_fstatfs            158 /* Common                                      */
 #define __NR_umount             159 /* Common                                      */
diff --git a/include/asm-sparc64/unistd.h b/include/asm-sparc64/unistd.h
index f59144c6b76..51ec2879b88 100644
--- a/include/asm-sparc64/unistd.h
+++ b/include/asm-sparc64/unistd.h
@@ -167,12 +167,12 @@
 #define __NR_pciconfig_read	148 /* ENOSYS under SunOS                          */
 #define __NR_pciconfig_write	149 /* ENOSYS under SunOS                          */
 #define __NR_getsockname        150 /* Common                                      */
-/* #define __NR_getmsg          151    SunOS Specific                              */
-/* #define __NR_putmsg          152    SunOS Specific                              */
+#define __NR_inotify_init       151 /* Linux specific                              */
+#define __NR_inotify_add_watch  152 /* Linux specific                              */
 #define __NR_poll               153 /* Common                                      */
 #define __NR_getdents64		154 /* Linux specific				   */
 /* #define __NR_fcntl64         155    Linux sparc32 Specific                      */
-/* #define __NR_getdirentries   156    SunOS Specific                              */
+#define __NR_inotify_rm_watch   156 /* Linux specific				   */
 #define __NR_statfs             157 /* Common                                      */
 #define __NR_fstatfs            158 /* Common                                      */
 #define __NR_umount             159 /* Common                                      */
diff --git a/include/asm-um/vm86.h b/include/asm-um/vm86.h
new file mode 100644
index 00000000000..7801f82de1f
--- /dev/null
+++ b/include/asm-um/vm86.h
@@ -0,0 +1,6 @@
+#ifndef __UM_VM86_H
+#define __UM_VM86_H
+
+#include "asm/arch/vm86.h"
+
+#endif
diff --git a/include/asm-v850/bitops.h b/include/asm-v850/bitops.h
index 7c4ecaf5151..0e5c2f21087 100644
--- a/include/asm-v850/bitops.h
+++ b/include/asm-v850/bitops.h
@@ -1,8 +1,8 @@
 /*
  * include/asm-v850/bitops.h -- Bit operations
  *
- *  Copyright (C) 2001,02,03,04  NEC Electronics Corporation
- *  Copyright (C) 2001,02,03,04  Miles Bader <miles@gnu.org>
+ *  Copyright (C) 2001,02,03,04,05  NEC Electronics Corporation
+ *  Copyright (C) 2001,02,03,04,05  Miles Bader <miles@gnu.org>
  *  Copyright (C) 1992  Linus Torvalds.
  *
  * This file is subject to the terms and conditions of the GNU General
@@ -157,7 +157,7 @@ extern __inline__ int __test_bit (int nr, const void *addr)
 #define find_first_zero_bit(addr, size) \
   find_next_zero_bit ((addr), (size), 0)
 
-extern __inline__ int find_next_zero_bit (void *addr, int size, int offset)
+extern __inline__ int find_next_zero_bit(const void *addr, int size, int offset)
 {
 	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
 	unsigned long result = offset & ~31UL;
diff --git a/include/asm-v850/cache.h b/include/asm-v850/cache.h
index 027f8c9090c..cbf9096e851 100644
--- a/include/asm-v850/cache.h
+++ b/include/asm-v850/cache.h
@@ -1,8 +1,8 @@
 /*
  * include/asm-v850/cache.h -- Cache operations
  *
- *  Copyright (C) 2001  NEC Corporation
- *  Copyright (C) 2001  Miles Bader <miles@gnu.org>
+ *  Copyright (C) 2001,05  NEC Corporation
+ *  Copyright (C) 2001,05  Miles Bader <miles@gnu.org>
  *
  * This file is subject to the terms and conditions of the GNU General
  * Public License.  See the file COPYING in the main directory of this
@@ -20,6 +20,9 @@
 #ifndef L1_CACHE_BYTES
 /* This processor has no cache, so just choose an arbitrary value.  */
 #define L1_CACHE_BYTES		16
+#define L1_CACHE_SHIFT		4
 #endif
 
+#define L1_CACHE_SHIFT_MAX	L1_CACHE_SHIFT
+
 #endif /* __V850_CACHE_H__ */
diff --git a/include/asm-v850/io.h b/include/asm-v850/io.h
index bb5efd1b4b7..cc364fcbec1 100644
--- a/include/asm-v850/io.h
+++ b/include/asm-v850/io.h
@@ -1,8 +1,8 @@
 /*
  * include/asm-v850/io.h -- Misc I/O operations
  *
- *  Copyright (C) 2001,02,03,04  NEC Electronics Corporation
- *  Copyright (C) 2001,02,03,04  Miles Bader <miles@gnu.org>
+ *  Copyright (C) 2001,02,03,04,05  NEC Electronics Corporation
+ *  Copyright (C) 2001,02,03,04,05  Miles Bader <miles@gnu.org>
  *
  * This file is subject to the terms and conditions of the GNU General
  * Public License.  See the file COPYING in the main directory of this
@@ -27,12 +27,12 @@
 #define readw_relaxed(a) readw(a)
 #define readl_relaxed(a) readl(a)
 
-#define writeb(b, addr) \
-  (void)((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b, addr) \
-  (void)((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b, addr) \
-  (void)((*(volatile unsigned int *) (addr)) = (b))
+#define writeb(val, addr) \
+  (void)((*(volatile unsigned char *) (addr)) = (val))
+#define writew(val, addr) \
+  (void)((*(volatile unsigned short *) (addr)) = (val))
+#define writel(val, addr) \
+  (void)((*(volatile unsigned int *) (addr)) = (val))
 
 #define __raw_readb readb
 #define __raw_readw readw
@@ -96,11 +96,22 @@ outsl (unsigned long port, const void *src, unsigned long count)
 		outl (*p++, port);
 }
 
-#define iounmap(addr)				((void)0)
-#define ioremap(physaddr, size)			(physaddr)
-#define ioremap_nocache(physaddr, size)		(physaddr)
-#define ioremap_writethrough(physaddr, size)	(physaddr)
-#define ioremap_fullcache(physaddr, size)	(physaddr)
+
+/* Some places try to pass in an loff_t for PHYSADDR (?!), so we cast it to
+   long before casting it to a pointer to avoid compiler warnings.  */
+#define ioremap(physaddr, size)	((void __iomem *)(unsigned long)(physaddr))
+#define iounmap(addr)		((void)0)
+
+#define ioremap_nocache(physaddr, size)		ioremap (physaddr, size)
+#define ioremap_writethrough(physaddr, size)	ioremap (physaddr, size)
+#define ioremap_fullcache(physaddr, size)	ioremap (physaddr, size)
+
+#define ioread8(addr)		readb (addr)
+#define ioread16(addr)		readw (addr)
+#define ioread32(addr)		readl (addr)
+#define iowrite8(val, addr)	writeb (val, addr)
+#define iowrite16(val, addr)	writew (val, addr)
+#define iowrite32(val, addr)	writel (val, addr)
 
 #define mmiowb()
 
diff --git a/include/asm-v850/page.h b/include/asm-v850/page.h
index 06085b0c043..d6091622935 100644
--- a/include/asm-v850/page.h
+++ b/include/asm-v850/page.h
@@ -1,8 +1,8 @@
 /*
  * include/asm-v850/page.h -- VM ops
  *
- *  Copyright (C) 2001,02,03  NEC Electronics Corporation
- *  Copyright (C) 2001,02,03  Miles Bader <miles@gnu.org>
+ *  Copyright (C) 2001,02,03,05  NEC Electronics Corporation
+ *  Copyright (C) 2001,02,03,05  Miles Bader <miles@gnu.org>
  *
  * This file is subject to the terms and conditions of the GNU General
  * Public License.  See the file COPYING in the main directory of this
@@ -132,6 +132,7 @@ extern __inline__ int get_order (unsigned long size)
 
 #define pfn_to_page(pfn)	virt_to_page (pfn_to_virt (pfn))
 #define page_to_pfn(page)	virt_to_pfn (page_to_virt (page))
+#define pfn_valid(pfn)	        ((pfn) < max_mapnr)
 
 #define	virt_addr_valid(kaddr)						\
   (((void *)(kaddr) >= (void *)PAGE_OFFSET) && MAP_NR (kaddr) < max_mapnr)
diff --git a/include/asm-v850/pci.h b/include/asm-v850/pci.h
index 8e79be0fe99..4581826e1ca 100644
--- a/include/asm-v850/pci.h
+++ b/include/asm-v850/pci.h
@@ -1,8 +1,8 @@
 /*
  * include/asm-v850/pci.h -- PCI support
  *
- *  Copyright (C) 2001,02  NEC Corporation
- *  Copyright (C) 2001,02  Miles Bader <miles@gnu.org>
+ *  Copyright (C) 2001,02,05  NEC Corporation
+ *  Copyright (C) 2001,02,05  Miles Bader <miles@gnu.org>
  *
  * This file is subject to the terms and conditions of the GNU General
  * Public License.  See the file COPYING in the main directory of this
@@ -48,12 +48,12 @@ pci_unmap_single (struct pci_dev *pdev, dma_addr_t dma_addr, size_t size,
    perform a pci_dma_sync_for_device, and then the device again owns
    the buffer.  */
 extern void
-pci_dma_sync_single_for_cpu (struct pci_dev *dev, dma_addr_t dma_addr, size_t size,
-		     int dir);
+pci_dma_sync_single_for_cpu (struct pci_dev *dev, dma_addr_t dma_addr,
+			     size_t size, int dir);
 
 extern void
-pci_dma_sync_single_for_device (struct pci_dev *dev, dma_addr_t dma_addr, size_t size,
-		     int dir);
+pci_dma_sync_single_for_device (struct pci_dev *dev, dma_addr_t dma_addr,
+				size_t size, int dir);
 
 
 /* Do multiple DMA mappings at once.  */
@@ -65,6 +65,28 @@ extern void
 pci_unmap_sg (struct pci_dev *pdev, struct scatterlist *sg, int sg_len,
 	      int dir);
 
+/* SG-list versions of pci_dma_sync functions.  */
+extern void
+pci_dma_sync_sg_for_cpu (struct pci_dev *dev,
+			 struct scatterlist *sg, int sg_len,
+			 int dir);
+extern void
+pci_dma_sync_sg_for_device (struct pci_dev *dev,
+			    struct scatterlist *sg, int sg_len,
+			    int dir);
+
+#define pci_map_page(dev, page, offs, size, dir) \
+  pci_map_single(dev, (page_address(page) + (offs)), size, dir)
+#define pci_unmap_page(dev,addr,sz,dir) \
+  pci_unmap_single(dev, addr, sz, dir)
+
+/* Test for pci_map_single or pci_map_page having generated an error.  */
+static inline int
+pci_dma_mapping_error (dma_addr_t dma_addr)
+{
+	return dma_addr == 0;
+}
+
 /* Allocate and map kernel buffer using consistent mode DMA for PCI
    device.  Returns non-NULL cpu-view pointer to the buffer if
    successful and sets *DMA_ADDR to the pci side dma address as well,
@@ -91,6 +113,9 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 }
 #endif
 
+extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
+extern void pci_iounmap (struct pci_dev *dev, void __iomem *addr);
+
 static inline void pcibios_add_platform_entries(struct pci_dev *dev)
 {
 }
diff --git a/include/asm-v850/pgtable.h b/include/asm-v850/pgtable.h
index 76e380e481e..3cf8775ce85 100644
--- a/include/asm-v850/pgtable.h
+++ b/include/asm-v850/pgtable.h
@@ -23,6 +23,8 @@
 #define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val(pte) })
 #define __swp_entry_to_pte(x)	((pte_t) { (x).val })
 
+static inline int pte_file (pte_t pte) { return 0; }
+
 
 /* These mean nothing to !CONFIG_MMU.  */
 #define PAGE_NONE		__pgprot(0)
diff --git a/include/asm-v850/v850e2_cache.h b/include/asm-v850/v850e2_cache.h
index 61acda1023e..87edf0d311d 100644
--- a/include/asm-v850/v850e2_cache.h
+++ b/include/asm-v850/v850e2_cache.h
@@ -2,8 +2,8 @@
  * include/asm-v850/v850e2_cache_cache.h -- Cache control for V850E2
  * 	cache memories
  *
- *  Copyright (C) 2003  NEC Electronics Corporation
- *  Copyright (C) 2003  Miles Bader <miles@gnu.org>
+ *  Copyright (C) 2003,05  NEC Electronics Corporation
+ *  Copyright (C) 2003,05  Miles Bader <miles@gnu.org>
  *
  * This file is subject to the terms and conditions of the GNU General
  * Public License.  See the file COPYING in the main directory of this
@@ -69,6 +69,7 @@
 
 /* For <asm/cache.h> */
 #define L1_CACHE_BYTES			V850E2_CACHE_LINE_SIZE
+#define L1_CACHE_SHIFT			V850E2_CACHE_LINE_SIZE_BITS
 
 
 #endif /* __V850_V850E2_CACHE_H__ */
diff --git a/include/asm-x86_64/bitops.h b/include/asm-x86_64/bitops.h
index a31bb99be53..05a0d374404 100644
--- a/include/asm-x86_64/bitops.h
+++ b/include/asm-x86_64/bitops.h
@@ -348,8 +348,7 @@ static inline int sched_find_first_bit(const unsigned long *b)
 		return __ffs(b[0]);
 	if (b[1])
 		return __ffs(b[1]) + 64;
-	if (b[2])
-		return __ffs(b[2]) + 128;
+	return __ffs(b[2]) + 128;
 }
 
 /**
diff --git a/include/asm-x86_64/bug.h b/include/asm-x86_64/bug.h
index 3d2a666a5dd..eed78566728 100644
--- a/include/asm-x86_64/bug.h
+++ b/include/asm-x86_64/bug.h
@@ -8,17 +8,24 @@
  * this frame.
  */
 struct bug_frame {
-       unsigned char ud2[2];
+	unsigned char ud2[2];
+	unsigned char mov;
 	/* should use 32bit offset instead, but the assembler doesn't 
 	   like it */
 	char *filename;
+	unsigned char ret;
 	unsigned short line;
 } __attribute__((packed));
 
 #ifdef CONFIG_BUG
 #define HAVE_ARCH_BUG
-#define BUG() \
-	asm volatile("ud2 ; .quad %c1 ; .short %c0" :: \
+/* We turn the bug frame into valid instructions to not confuse
+   the disassembler. Thanks to Jan Beulich & Suresh Siddha
+   for nice instruction selection.
+   The magic numbers generate mov $64bitimm,%eax ; ret $offset. */
+#define BUG() 								\
+	asm volatile(							\
+	"ud2 ; .byte 0xa3 ; .quad %c1 ; .byte 0xc2 ; .short %c0" :: 	\
 		     "i"(__LINE__), "i" (__stringify(__FILE__)))
 void out_of_line_bug(void);
 #else
diff --git a/include/asm-x86_64/desc.h b/include/asm-x86_64/desc.h
index 6aefb9c0280..c89b58bebee 100644
--- a/include/asm-x86_64/desc.h
+++ b/include/asm-x86_64/desc.h
@@ -75,6 +75,7 @@ struct desc_ptr {
  */
 extern struct desc_struct default_ldt[];
 extern struct gate_struct idt_table[]; 
+extern struct desc_ptr cpu_gdt_descr[];
 
 static inline void _set_gate(void *adr, unsigned type, unsigned long func, unsigned dpl, unsigned ist)  
 {
diff --git a/include/asm-x86_64/ipi.h b/include/asm-x86_64/ipi.h
index d1841847ed8..5e166b9d3bd 100644
--- a/include/asm-x86_64/ipi.h
+++ b/include/asm-x86_64/ipi.h
@@ -82,30 +82,27 @@ static inline void send_IPI_mask_sequence(cpumask_t mask, int vector)
 	 */
 	local_irq_save(flags);
 
-	for (query_cpu = 0; query_cpu < NR_CPUS; ++query_cpu) {
-		if (cpu_isset(query_cpu, mask)) {
-
-			/*
-			 * Wait for idle.
-			 */
-			apic_wait_icr_idle();
-
-			/*
-			 * prepare target chip field
-			 */
-			cfg = __prepare_ICR2(x86_cpu_to_apicid[query_cpu]);
-			apic_write_around(APIC_ICR2, cfg);
-
-			/*
-			 * program the ICR
-			 */
-			cfg = __prepare_ICR(0, vector, APIC_DEST_PHYSICAL);
-
-			/*
-			 * Send the IPI. The write to APIC_ICR fires this off.
-			 */
-			apic_write_around(APIC_ICR, cfg);
-		}
+	for_each_cpu_mask(query_cpu, mask) {
+		/*
+		 * Wait for idle.
+		 */
+		apic_wait_icr_idle();
+
+		/*
+		 * prepare target chip field
+		 */
+		cfg = __prepare_ICR2(x86_cpu_to_apicid[query_cpu]);
+		apic_write_around(APIC_ICR2, cfg);
+
+		/*
+		 * program the ICR
+		 */
+		cfg = __prepare_ICR(0, vector, APIC_DEST_PHYSICAL);
+
+		/*
+		 * Send the IPI. The write to APIC_ICR fires this off.
+		 */
+		apic_write_around(APIC_ICR, cfg);
 	}
 	local_irq_restore(flags);
 }
diff --git a/include/asm-x86_64/irq.h b/include/asm-x86_64/irq.h
index eb3b7aa9eb9..4482657777b 100644
--- a/include/asm-x86_64/irq.h
+++ b/include/asm-x86_64/irq.h
@@ -57,4 +57,6 @@ int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
 extern void fixup_irqs(cpumask_t map);
 #endif
 
+#define __ARCH_HAS_DO_SOFTIRQ 1
+
 #endif /* _ASM_IRQ_H */
diff --git a/include/asm-x86_64/msr.h b/include/asm-x86_64/msr.h
index bc700232728..ba15279a79d 100644
--- a/include/asm-x86_64/msr.h
+++ b/include/asm-x86_64/msr.h
@@ -218,7 +218,7 @@ extern inline unsigned int cpuid_edx(unsigned int op)
 #define MSR_K7_PERFCTR3            0xC0010007
 #define MSR_K8_TOP_MEM1		   0xC001001A
 #define MSR_K8_TOP_MEM2		   0xC001001D
-#define MSR_K8_SYSCFG		   0xC0000010	
+#define MSR_K8_SYSCFG		   0xC0010010
 
 /* K6 MSRs */
 #define MSR_K6_EFER			0xC0000080
diff --git a/include/asm-x86_64/pci.h b/include/asm-x86_64/pci.h
index eeb3088a1c9..9c4527eb55e 100644
--- a/include/asm-x86_64/pci.h
+++ b/include/asm-x86_64/pci.h
@@ -22,11 +22,9 @@ extern unsigned int pcibios_assign_all_busses(void);
 extern int no_iommu, force_iommu;
 
 extern unsigned long pci_mem_start;
-#define PCIBIOS_MIN_IO		0x1000
+#define PCIBIOS_MIN_IO		0x4000
 #define PCIBIOS_MIN_MEM		(pci_mem_start)
 
-#define PCIBIOS_MIN_CARDBUS_IO	0x4000
-
 void pcibios_config_init(void);
 struct pci_bus * pcibios_scan_root(int bus);
 extern int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int len, u32 *value);
diff --git a/include/asm-x86_64/pgtable.h b/include/asm-x86_64/pgtable.h
index 4eec176c3c3..4e167b5ea8f 100644
--- a/include/asm-x86_64/pgtable.h
+++ b/include/asm-x86_64/pgtable.h
@@ -176,6 +176,8 @@ extern inline void pgd_clear (pgd_t * pgd)
 	(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_PCD)
 #define __PAGE_KERNEL_LARGE \
 	(__PAGE_KERNEL | _PAGE_PSE)
+#define __PAGE_KERNEL_LARGE_EXEC \
+	(__PAGE_KERNEL_EXEC | _PAGE_PSE)
 
 #define MAKE_GLOBAL(x) __pgprot((x) | _PAGE_GLOBAL)
 
diff --git a/include/asm-x86_64/smp.h b/include/asm-x86_64/smp.h
index aeb1b73e21e..de8b57b2b62 100644
--- a/include/asm-x86_64/smp.h
+++ b/include/asm-x86_64/smp.h
@@ -46,12 +46,12 @@ extern int pic_mode;
 extern void lock_ipi_call_lock(void);
 extern void unlock_ipi_call_lock(void);
 extern int smp_num_siblings;
-extern void smp_flush_tlb(void);
-extern void smp_message_irq(int cpl, void *dev_id, struct pt_regs *regs);
 extern void smp_send_reschedule(int cpu);
-extern void smp_invalidate_rcv(void);		/* Process an NMI */
 extern void zap_low_mappings(void);
 void smp_stop_cpu(void);
+extern int smp_call_function_single(int cpuid, void (*func) (void *info),
+				void *info, int retry, int wait);
+
 extern cpumask_t cpu_sibling_map[NR_CPUS];
 extern cpumask_t cpu_core_map[NR_CPUS];
 extern u8 phys_proc_id[NR_CPUS];
diff --git a/include/asm-x86_64/system.h b/include/asm-x86_64/system.h
index 76165736e43..8606e170a7d 100644
--- a/include/asm-x86_64/system.h
+++ b/include/asm-x86_64/system.h
@@ -116,12 +116,12 @@ struct alt_instr {
 /*
  * Alternative inline assembly with input.
  * 
- * Pecularities:
+ * Peculiarities:
  * No memory clobber here. 
  * Argument numbers start with 1.
  * Best is to use constraints that are fixed size (like (%1) ... "r")
  * If you use variable sized constraints like "m" or "g" in the 
- * replacement maake sure to pad to the worst case length.
+ * replacement make sure to pad to the worst case length.
  */
 #define alternative_input(oldinstr, newinstr, feature, input...)	\
 	asm volatile ("661:\n\t" oldinstr "\n662:\n"			\
@@ -335,9 +335,6 @@ void cpu_idle_wait(void);
 void disable_hlt(void);
 void enable_hlt(void);
 
-#define HAVE_EAT_KEY
-void eat_key(void);
-
 extern unsigned long arch_align_stack(unsigned long sp);
 
 #endif
diff --git a/include/asm-x86_64/tlbflush.h b/include/asm-x86_64/tlbflush.h
index 06174238252..505b0cf906d 100644
--- a/include/asm-x86_64/tlbflush.h
+++ b/include/asm-x86_64/tlbflush.h
@@ -56,8 +56,9 @@ extern unsigned long pgkern_mask;
  *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
  *  - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
  *
- * ..but the x86_64 has somewhat limited tlb flushing capabilities,
- * and page-granular flushes are available only on i486 and up.
+ * x86-64 can only flush individual pages or full VMs. For a range flush
+ * we always do the full VM. Might be worth trying if for a small
+ * range a few INVLPGs in a row are a win.
  */
 
 #ifndef CONFIG_SMP
@@ -115,7 +116,9 @@ static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long st
 static inline void flush_tlb_pgtables(struct mm_struct *mm,
 				      unsigned long start, unsigned long end)
 {
-	/* x86_64 does not keep any page table caches in TLB */
+	/* x86_64 does not keep any page table caches in a software TLB.
+	   The CPUs do in their hardware TLBs, but they are handled
+	   by the normal TLB flushing algorithms. */
 }
 
 #endif /* _X8664_TLBFLUSH_H */
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index f85cbe919e1..b46a5205ee7 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -453,9 +453,7 @@ int acpi_gsi_to_irq (u32 gsi, unsigned int *irq);
  * If this matches the last registration, any IRQ resources for gsi
  * are freed.
  */
-#ifdef CONFIG_ACPI_DEALLOCATE_IRQ
 void acpi_unregister_gsi (u32 gsi);
-#endif
 
 #ifdef CONFIG_ACPI_PCI
 
@@ -480,9 +478,7 @@ struct pci_dev;
 int acpi_pci_irq_enable (struct pci_dev *dev);
 void acpi_penalize_isa_irq(int irq, int active);
 
-#ifdef CONFIG_ACPI_DEALLOCATE_IRQ
 void acpi_pci_irq_disable (struct pci_dev *dev);
-#endif
 
 struct acpi_pci_driver {
 	struct acpi_pci_driver *next;
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index 0881b5cdee3..19bd8e7e11b 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -301,6 +301,7 @@ struct blk_queue_tag {
 	struct list_head busy_list;	/* fifo list of busy tags */
 	int busy;			/* current depth */
 	int max_depth;			/* what we will send to device */
+	int real_max_depth;		/* what the array can hold */
 	atomic_t refcnt;		/* map can be shared */
 };
 
diff --git a/include/linux/dcookies.h b/include/linux/dcookies.h
index c2805013616..1d68428c925 100644
--- a/include/linux/dcookies.h
+++ b/include/linux/dcookies.h
@@ -48,12 +48,12 @@ int get_dcookie(struct dentry * dentry, struct vfsmount * vfsmnt,
 
 #else
 
-struct dcookie_user * dcookie_register(void)
+static inline struct dcookie_user * dcookie_register(void)
 {
 	return NULL;
 }
 
-void dcookie_unregister(struct dcookie_user * user)
+static inline void dcookie_unregister(struct dcookie_user * user)
 {
 	return;
 }
diff --git a/include/linux/fs.h b/include/linux/fs.h
index 0f53e012494..f9adf75fd9b 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -697,11 +697,13 @@ extern struct list_head file_lock_list;
 #include <linux/fcntl.h>
 
 extern int fcntl_getlk(struct file *, struct flock __user *);
-extern int fcntl_setlk(struct file *, unsigned int, struct flock __user *);
+extern int fcntl_setlk(unsigned int, struct file *, unsigned int,
+			struct flock __user *);
 
 #if BITS_PER_LONG == 32
 extern int fcntl_getlk64(struct file *, struct flock64 __user *);
-extern int fcntl_setlk64(struct file *, unsigned int, struct flock64 __user *);
+extern int fcntl_setlk64(unsigned int, struct file *, unsigned int,
+			struct flock64 __user *);
 #endif
 
 extern void send_sigio(struct fown_struct *fown, int fd, int band);
diff --git a/include/linux/fsnotify.h b/include/linux/fsnotify.h
index d07a92c9477..602c305c858 100644
--- a/include/linux/fsnotify.h
+++ b/include/linux/fsnotify.h
@@ -21,7 +21,7 @@
  */
 static inline void fsnotify_move(struct inode *old_dir, struct inode *new_dir,
 				 const char *old_name, const char *new_name,
-				 int isdir)
+				 int isdir, struct inode *target)
 {
 	u32 cookie = inotify_get_cookie();
 
@@ -36,31 +36,30 @@ static inline void fsnotify_move(struct inode *old_dir, struct inode *new_dir,
 		isdir = IN_ISDIR;
 	inotify_inode_queue_event(old_dir, IN_MOVED_FROM|isdir,cookie,old_name);
 	inotify_inode_queue_event(new_dir, IN_MOVED_TO|isdir, cookie, new_name);
+
+	if (target) {
+		inotify_inode_queue_event(target, IN_DELETE_SELF, 0, NULL);
+		inotify_inode_is_dead(target);
+	}
 }
 
 /*
- * fsnotify_unlink - file was unlinked
+ * fsnotify_nameremove - a filename was removed from a directory
  */
-static inline void fsnotify_unlink(struct dentry *dentry, struct inode *dir)
+static inline void fsnotify_nameremove(struct dentry *dentry, int isdir)
 {
-	struct inode *inode = dentry->d_inode;
-
-	inode_dir_notify(dir, DN_DELETE);
-	inotify_inode_queue_event(dir, IN_DELETE, 0, dentry->d_name.name);
-	inotify_inode_queue_event(inode, IN_DELETE_SELF, 0, NULL);
-
-	inotify_inode_is_dead(inode);
+	if (isdir)
+		isdir = IN_ISDIR;
+	dnotify_parent(dentry, DN_DELETE);
+	inotify_dentry_parent_queue_event(dentry, IN_DELETE|isdir, 0, dentry->d_name.name);
 }
 
 /*
- * fsnotify_rmdir - directory was removed
+ * fsnotify_inoderemove - an inode is going away
  */
-static inline void fsnotify_rmdir(struct dentry *dentry, struct inode *inode,
-				  struct inode *dir)
+static inline void fsnotify_inoderemove(struct inode *inode)
 {
-	inode_dir_notify(dir, DN_DELETE);
-	inotify_inode_queue_event(dir,IN_DELETE|IN_ISDIR,0,dentry->d_name.name);
-	inotify_inode_queue_event(inode, IN_DELETE_SELF | IN_ISDIR, 0, NULL);
+	inotify_inode_queue_event(inode, IN_DELETE_SELF, 0, NULL);
 	inotify_inode_is_dead(inode);
 }
 
diff --git a/include/linux/ftape.h b/include/linux/ftape.h
index c6b38d5b918..72faeec9f6e 100644
--- a/include/linux/ftape.h
+++ b/include/linux/ftape.h
@@ -165,7 +165,7 @@ typedef union {
 #  undef  CONFIG_FT_FDC_DMA
 #  define CONFIG_FT_FDC_DMA 2
 # endif
-#elif CONFIG_FT_ALT_FDC == 1  /* CONFIG_FT_MACH2 */
+#elif defined(CONFIG_FT_ALT_FDC)  /* CONFIG_FT_MACH2 */
 # if CONFIG_FT_FDC_BASE == 0
 #  undef  CONFIG_FT_FDC_BASE
 #  define CONFIG_FT_FDC_BASE 0x370
diff --git a/include/linux/input.h b/include/linux/input.h
index b9cc0ac71f4..bdc53c6cc96 100644
--- a/include/linux/input.h
+++ b/include/linux/input.h
@@ -811,9 +811,9 @@ struct input_dev {
 
 	void *private;
 
-	char *name;
-	char *phys;
-	char *uniq;
+	const char *name;
+	const char *phys;
+	const char *uniq;
 	struct input_id id;
 
 	unsigned long evbit[NBITS(EV_MAX)];
diff --git a/include/linux/mbcache.h b/include/linux/mbcache.h
index 8e5a10410a3..9263d2db2d6 100644
--- a/include/linux/mbcache.h
+++ b/include/linux/mbcache.h
@@ -29,7 +29,7 @@ struct mb_cache_op {
 
 struct mb_cache * mb_cache_create(const char *, struct mb_cache_op *, size_t,
 				  int, int);
-void mb_cache_shrink(struct mb_cache *, struct block_device *);
+void mb_cache_shrink(struct block_device *);
 void mb_cache_destroy(struct mb_cache *);
 
 /* Functions on cache entries */
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 6eb7f48317f..82d7024f076 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -625,10 +625,16 @@ static inline int page_mapped(struct page *page)
  * Used to decide whether a process gets delivered SIGBUS or
  * just gets major/minor fault counters bumped up.
  */
-#define VM_FAULT_OOM	(-1)
-#define VM_FAULT_SIGBUS	0
-#define VM_FAULT_MINOR	1
-#define VM_FAULT_MAJOR	2
+#define VM_FAULT_OOM	0x00
+#define VM_FAULT_SIGBUS	0x01
+#define VM_FAULT_MINOR	0x02
+#define VM_FAULT_MAJOR	0x03
+
+/* 
+ * Special case for get_user_pages.
+ * Must be in a distinct bit from the above VM_FAULT_ flags.
+ */
+#define VM_FAULT_WRITE	0x10
 
 #define offset_in_page(p)	((unsigned long)(p) & ~PAGE_MASK)
 
@@ -704,7 +710,13 @@ extern pte_t *FASTCALL(pte_alloc_kernel(struct mm_struct *mm, pmd_t *pmd, unsign
 extern pte_t *FASTCALL(pte_alloc_map(struct mm_struct *mm, pmd_t *pmd, unsigned long address));
 extern int install_page(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long addr, struct page *page, pgprot_t prot);
 extern int install_file_pte(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long addr, unsigned long pgoff, pgprot_t prot);
-extern int handle_mm_fault(struct mm_struct *mm,struct vm_area_struct *vma, unsigned long address, int write_access);
+extern int __handle_mm_fault(struct mm_struct *mm,struct vm_area_struct *vma, unsigned long address, int write_access);
+
+static inline int handle_mm_fault(struct mm_struct *mm, struct vm_area_struct *vma, unsigned long address, int write_access)
+{
+	return __handle_mm_fault(mm, vma, address, write_access) & (~VM_FAULT_WRITE);
+}
+
 extern int make_pages_present(unsigned long addr, unsigned long end);
 extern int access_process_vm(struct task_struct *tsk, unsigned long addr, void *buf, int len, int write);
 void install_arg_page(struct vm_area_struct *, struct page *, unsigned long);
diff --git a/include/linux/netlink.h b/include/linux/netlink.h
index 70c2a9dc4b2..6552b71bfa7 100644
--- a/include/linux/netlink.h
+++ b/include/linux/netlink.h
@@ -12,15 +12,13 @@
 #define NETLINK_NFLOG		5	/* netfilter/iptables ULOG */
 #define NETLINK_XFRM		6	/* ipsec */
 #define NETLINK_SELINUX		7	/* SELinux event notifications */
-#define NETLINK_ARPD		8
+#define NETLINK_ISCSI		8	/* Open-iSCSI */
 #define NETLINK_AUDIT		9	/* auditing */
 #define NETLINK_FIB_LOOKUP	10	
-#define NETLINK_ROUTE6		11	/* af_inet6 route comm channel */
 #define NETLINK_NETFILTER	12	/* netfilter subsystem */
 #define NETLINK_IP6_FW		13
 #define NETLINK_DNRTMSG		14	/* DECnet routing messages */
 #define NETLINK_KOBJECT_UEVENT	15	/* Kernel messages to userspace */
-#define NETLINK_TAPBASE		16	/* 16 to 31 are ethertap */
 
 #define MAX_LINKS 32		
 
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 7ac14961ba2..8621cf42b46 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -971,6 +971,8 @@ static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int en
 
 #define	isa_bridge	((struct pci_dev *)NULL)
 
+#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
+
 #else
 
 /*
@@ -985,9 +987,6 @@ static inline int pci_proc_domain(struct pci_bus *bus)
 	return 0;
 }
 #endif
-
-#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
-
 #endif /* !CONFIG_PCI */
 
 /* these helpers provide future and backwards compatibility
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index d2ad2c4f835..bc4cc10fabe 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1020,6 +1020,7 @@
 #define PCI_DEVICE_ID_PLX_SPCOM200	0x1103
 #define PCI_DEVICE_ID_PLX_DJINN_ITOO	0x1151
 #define PCI_DEVICE_ID_PLX_R753		0x1152
+#define PCI_DEVICE_ID_PLX_OLITEC	0x1187
 #define PCI_DEVICE_ID_PLX_9030		0x9030
 #define PCI_DEVICE_ID_PLX_9050		0x9050
 #define PCI_DEVICE_ID_PLX_9060		0x9060
diff --git a/include/linux/raid/bitmap.h b/include/linux/raid/bitmap.h
index 6213e976ead..4bf1659f8aa 100644
--- a/include/linux/raid/bitmap.h
+++ b/include/linux/raid/bitmap.h
@@ -248,6 +248,7 @@ struct bitmap {
 
 /* these are used only by md/bitmap */
 int  bitmap_create(mddev_t *mddev);
+void bitmap_flush(mddev_t *mddev);
 void bitmap_destroy(mddev_t *mddev);
 int  bitmap_active(struct bitmap *bitmap);
 
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 30b64f3534f..f6fca8f2f3c 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -104,7 +104,7 @@
 #define PORT_MPSC	63
 
 /* TXX9 type number */
-#define PORT_TXX9       64
+#define PORT_TXX9	64
 
 /* NEC VR4100 series SIU/DSIU */
 #define PORT_VR41XX_SIU		65
diff --git a/include/linux/slab.h b/include/linux/slab.h
index 4c8e552471b..80b2dfde2e8 100644
--- a/include/linux/slab.h
+++ b/include/linux/slab.h
@@ -111,7 +111,7 @@ static inline void *kmem_cache_alloc_node(kmem_cache_t *cachep, int flags, int n
 {
 	return kmem_cache_alloc(cachep, flags);
 }
-static inline void *kmalloc_node(size_t size, int flags, int node)
+static inline void *kmalloc_node(size_t size, unsigned int __nocast flags, int node)
 {
 	return kmalloc(size, flags);
 }
diff --git a/include/linux/swap.h b/include/linux/swap.h
index 239f520cc49..bfe3e763ccf 100644
--- a/include/linux/swap.h
+++ b/include/linux/swap.h
@@ -7,7 +7,6 @@
 #include <linux/mmzone.h>
 #include <linux/list.h>
 #include <linux/sched.h>
-#include <linux/pagemap.h>
 
 #include <asm/atomic.h>
 #include <asm/page.h>
@@ -255,6 +254,8 @@ static inline void put_swap_token(struct mm_struct *mm)
 
 #define si_swapinfo(val) \
 	do { (val)->freeswap = (val)->totalswap = 0; } while (0)
+/* only sparc can not include linux/pagemap.h in this file
+ * so leave page_cache_release and release_pages undeclared... */
 #define free_page_and_swap_cache(page) \
 	page_cache_release(page)
 #define free_pages_and_swap_cache(pages, nr) \
diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h
index bfbbe94b297..e82be96d490 100644
--- a/include/linux/sysctl.h
+++ b/include/linux/sysctl.h
@@ -145,6 +145,7 @@ enum
 	KERN_BOOTLOADER_TYPE=67, /* int: boot loader type */
 	KERN_RANDOMIZE=68, /* int: randomize virtual address space */
 	KERN_SETUID_DUMPABLE=69, /* int: behaviour of dumps for setuid core */
+	KERN_SPIN_RETRY=70,	/* int: number of spinlock retries */
 };
 
 
diff --git a/include/linux/uinput.h b/include/linux/uinput.h
index 4c2c82336d1..84876077027 100644
--- a/include/linux/uinput.h
+++ b/include/linux/uinput.h
@@ -42,8 +42,7 @@ struct uinput_request {
 	int			code;	/* UI_FF_UPLOAD, UI_FF_ERASE */
 
 	int			retval;
-	wait_queue_head_t	waitq;
-	int			completed;
+	struct completion	done;
 
 	union {
 		int		effect_id;
@@ -62,7 +61,7 @@ struct uinput_device {
 
 	struct uinput_request	*requests[UINPUT_NUM_REQUESTS];
 	wait_queue_head_t	requests_waitq;
-	struct semaphore	requests_sem;
+	spinlock_t		requests_lock;
 };
 #endif	/* __KERNEL__ */
 
diff --git a/include/linux/usb_input.h b/include/linux/usb_input.h
new file mode 100644
index 00000000000..716e0cc1604
--- /dev/null
+++ b/include/linux/usb_input.h
@@ -0,0 +1,25 @@
+#ifndef __USB_INPUT_H
+#define __USB_INPUT_H
+
+/*
+ * Copyright (C) 2005 Dmitry Torokhov
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+#include <linux/usb.h>
+#include <linux/input.h>
+#include <asm/byteorder.h>
+
+static inline void
+usb_to_input_id(const struct usb_device *dev, struct input_id *id)
+{
+	id->bustype = BUS_USB;
+	id->vendor = le16_to_cpu(dev->descriptor.idVendor);
+	id->product = le16_to_cpu(dev->descriptor.idProduct);
+	id->version = le16_to_cpu(dev->descriptor.bcdDevice);
+}
+
+#endif
diff --git a/include/linux/watchdog.h b/include/linux/watchdog.h
index 88ba0d29f8c..1192ed8f4fe 100644
--- a/include/linux/watchdog.h
+++ b/include/linux/watchdog.h
@@ -47,4 +47,14 @@ struct watchdog_info {
 #define	WDIOS_ENABLECARD	0x0002	/* Turn on the watchdog timer */
 #define	WDIOS_TEMPPANIC		0x0004	/* Kernel panic on temperature trip */
 
+#ifdef __KERNEL__
+
+#ifdef CONFIG_WATCHDOG_NOWAYOUT
+#define WATCHDOG_NOWAYOUT	1
+#else
+#define WATCHDOG_NOWAYOUT	0
+#endif
+
+#endif	/* __KERNEL__ */
+
 #endif  /* ifndef _LINUX_WATCHDOG_H */
diff --git a/include/linux/zlib.h b/include/linux/zlib.h
index 850076ea14d..74f7b78c22d 100644
--- a/include/linux/zlib.h
+++ b/include/linux/zlib.h
@@ -506,6 +506,11 @@ extern int zlib_deflateReset (z_streamp strm);
    stream state was inconsistent (such as zalloc or state being NULL).
 */
 
+static inline unsigned long deflateBound(unsigned long s)
+{
+	return s + ((s + 7) >> 3) + ((s + 63) >> 6) + 11;
+}
+
 extern int zlib_deflateParams (z_streamp strm, int level, int strategy);
 /*
      Dynamically update the compression level and compression strategy.  The
diff --git a/include/media/tuner.h b/include/media/tuner.h
index d8c0a556328..eeaa15ddee8 100644
--- a/include/media/tuner.h
+++ b/include/media/tuner.h
@@ -1,5 +1,5 @@
 
-/* $Id: tuner.h,v 1.42 2005/07/06 09:42:19 mchehab Exp $
+/* $Id: tuner.h,v 1.45 2005/07/28 18:41:21 mchehab Exp $
  *
     tuner.h - definition for different tuners
 
@@ -108,6 +108,8 @@
 
 #define TUNER_TEA5767         62	/* Only FM Radio Tuner */
 #define TUNER_PHILIPS_FMD1216ME_MK3 63
+#define TUNER_LG_TDVS_H062F   64	/* DViCO FusionHDTV 5 */
+#define TUNER_YMEC_TVF66T5_B_DFF 65	/* Acorp Y878F */
 
 #define NOTUNER 0
 #define PAL     1	/* PAL_BG */
diff --git a/include/media/tveeprom.h b/include/media/tveeprom.h
index 5c4fe30e8d1..854a2c2f105 100644
--- a/include/media/tveeprom.h
+++ b/include/media/tveeprom.h
@@ -24,4 +24,3 @@ void tveeprom_hauppauge_analog(struct tveeprom *tvee,
 			       unsigned char *eeprom_data);
 
 int tveeprom_read(struct i2c_client *c, unsigned char *eedata, int len);
-int tveeprom_dump(unsigned char *eedata, int len);
diff --git a/include/net/bluetooth/bluetooth.h b/include/net/bluetooth/bluetooth.h
index 42a84c53678..06b24f63702 100644
--- a/include/net/bluetooth/bluetooth.h
+++ b/include/net/bluetooth/bluetooth.h
@@ -57,12 +57,6 @@
 #define BT_DBG(fmt, arg...)  printk(KERN_INFO "%s: " fmt "\n" , __FUNCTION__ , ## arg)
 #define BT_ERR(fmt, arg...)  printk(KERN_ERR  "%s: " fmt "\n" , __FUNCTION__ , ## arg)
 
-#ifdef HCI_DATA_DUMP
-#define BT_DMP(buf, len) bt_dump(__FUNCTION__, buf, len)
-#else
-#define BT_DMP(D...)
-#endif
-
 extern struct proc_dir_entry *proc_bt;
 
 /* Connection and socket states */
@@ -174,8 +168,6 @@ static inline int skb_frags_no(struct sk_buff *skb)
 	return n;
 }
 
-void bt_dump(char *pref, __u8 *buf, int count);
-
 int bt_err(__u16 code);
 
 #endif /* __BLUETOOTH_H */
diff --git a/include/net/tcp.h b/include/net/tcp.h
index f4f9aba07ac..5010f0c5a56 100644
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -1236,7 +1236,7 @@ static inline void tcp_sync_left_out(struct tcp_sock *tp)
 	tp->left_out = tp->sacked_out + tp->lost_out;
 }
 
-/* Set slow start threshould and cwnd not falling to slow start */
+/* Set slow start threshold and cwnd not falling to slow start */
 static inline void __tcp_enter_cwr(struct tcp_sock *tp)
 {
 	tp->undo_marker = 0;
diff --git a/include/sound/core.h b/include/sound/core.h
index f8c4ef0aa35..38b357fc895 100644
--- a/include/sound/core.h
+++ b/include/sound/core.h
@@ -126,25 +126,26 @@ struct snd_monitor_file {
 	struct snd_monitor_file *next;
 };
 
-struct snd_shutdown_f_ops;	/* define it later */
+struct snd_shutdown_f_ops;	/* define it later in init.c */
 
 /* main structure for soundcard */
 
 struct _snd_card {
-	int number;			/* number of soundcard (index to snd_cards) */
+	int number;			/* number of soundcard (index to
+								snd_cards) */
 
 	char id[16];			/* id string of this card */
 	char driver[16];		/* driver name */
 	char shortname[32];		/* short name of this soundcard */
 	char longname[80];		/* name of this soundcard */
 	char mixername[80];		/* mixer name */
-	char components[80];		/* card components delimited with space */
-
+	char components[80];		/* card components delimited with
+								space */
 	struct module *module;		/* top-level module */
 
 	void *private_data;		/* private data for soundcard */
-	void (*private_free) (snd_card_t *card); /* callback for freeing of private data */
-
+	void (*private_free) (snd_card_t *card); /* callback for freeing of
+								private data */
 	struct list_head devices;	/* devices */
 
 	unsigned int last_numid;	/* last used numeric ID */
@@ -160,7 +161,8 @@ struct _snd_card {
 	struct proc_dir_entry *proc_root_link;	/* number link to real id */
 
 	struct snd_monitor_file *files; /* all files associated to this card */
-	struct snd_shutdown_f_ops *s_f_ops; /* file operations in the shutdown state */
+	struct snd_shutdown_f_ops *s_f_ops; /* file operations in the shutdown
+								state */
 	spinlock_t files_lock;		/* lock the files for this card */
 	int shutdown;			/* this card is going down */
 	wait_queue_head_t shutdown_sleep;
@@ -196,8 +198,6 @@ static inline void snd_power_unlock(snd_card_t *card)
 	up(&card->power_lock);
 }
 
-int snd_power_wait(snd_card_t *card, unsigned int power_state, struct file *file);
-
 static inline unsigned int snd_power_get_state(snd_card_t *card)
 {
 	return card->power_state;
@@ -208,6 +208,10 @@ static inline void snd_power_change_state(snd_card_t *card, unsigned int state)
 	card->power_state = state;
 	wake_up(&card->power_sleep);
 }
+
+/* init.c */
+int snd_power_wait(snd_card_t *card, unsigned int power_state, struct file *file);
+
 int snd_card_set_pm_callback(snd_card_t *card,
 			     int (*suspend)(snd_card_t *, pm_message_t),
 			     int (*resume)(snd_card_t *),
@@ -238,15 +242,14 @@ static inline int snd_power_wait(snd_card_t *card, unsigned int state, struct fi
 
 #endif /* CONFIG_PM */
 
-/* device.c */
-
 struct _snd_minor {
 	struct list_head list;		/* list of all minors per card */
 	int number;			/* minor number */
 	int device;			/* device number */
 	const char *comment;		/* for /proc/asound/devices */
 	struct file_operations *f_ops;	/* file operations */
-	char name[0];			/* device name (keep at the end of structure) */
+	char name[0];			/* device name (keep at the end of
+								structure) */
 };
 
 typedef struct _snd_minor snd_minor_t;
@@ -287,12 +290,12 @@ void snd_memory_init(void);
 void snd_memory_done(void);
 int snd_memory_info_init(void);
 int snd_memory_info_done(void);
-void *snd_hidden_kmalloc(size_t size, int flags);
-void *snd_hidden_kcalloc(size_t n, size_t size, int flags);
+void *snd_hidden_kmalloc(size_t size, unsigned int __nocast flags);
+void *snd_hidden_kcalloc(size_t n, size_t size, unsigned int __nocast flags);
 void snd_hidden_kfree(const void *obj);
 void *snd_hidden_vmalloc(unsigned long size);
 void snd_hidden_vfree(void *obj);
-char *snd_hidden_kstrdup(const char *s, int flags);
+char *snd_hidden_kstrdup(const char *s, unsigned int __nocast flags);
 #define kmalloc(size, flags) snd_hidden_kmalloc(size, flags)
 #define kcalloc(n, size, flags) snd_hidden_kcalloc(n, size, flags)
 #define kfree(obj) snd_hidden_kfree(obj)
@@ -411,7 +414,7 @@ void snd_verbose_printd(const char *file, int line, const char *format, ...)
 	printk(fmt ,##args)
 #endif
 /**
- * snd_assert - run-time assersion macro
+ * snd_assert - run-time assertion macro
  * @expr: expression
  * @args...: the action
  *
@@ -427,7 +430,7 @@ void snd_verbose_printd(const char *file, int line, const char *format, ...)
 	}\
 } while (0)
 /**
- * snd_runtime_check - run-time assersion macro
+ * snd_runtime_check - run-time assertion macro
  * @expr: expression
  * @args...: the action
  *
diff --git a/include/sound/driver.h b/include/sound/driver.h
index 948e9a1aebe..0d12456ec3a 100644
--- a/include/sound/driver.h
+++ b/include/sound/driver.h
@@ -51,7 +51,7 @@
 #ifdef CONFIG_SND_DEBUG_MEMORY
 #include <linux/slab.h>
 #include <linux/vmalloc.h>
-void *snd_wrapper_kmalloc(size_t, int);
+void *snd_wrapper_kmalloc(size_t, unsigned int __nocast);
 #undef kmalloc
 void snd_wrapper_kfree(const void *);
 #undef kfree
diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h
index c50b91958ff..c2ef3f02368 100644
--- a/include/sound/emu10k1.h
+++ b/include/sound/emu10k1.h
@@ -1167,6 +1167,7 @@ int snd_emu10k1_create(snd_card_t * card,
 		       unsigned short extout_mask,
 		       long max_cache_bytes,
 		       int enable_ir,
+		       uint subsystem,
 		       emu10k1_t ** remu);
 
 int snd_emu10k1_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
diff --git a/include/sound/version.h b/include/sound/version.h
index 46acfa8c998..c085136f391 100644
--- a/include/sound/version.h
+++ b/include/sound/version.h
@@ -1,3 +1,3 @@
 /* include/version.h.  Generated by configure.  */
-#define CONFIG_SND_VERSION "1.0.9"
-#define CONFIG_SND_DATE " (Sun May 29 07:31:02 2005 UTC)"
+#define CONFIG_SND_VERSION "1.0.9b"
+#define CONFIG_SND_DATE " (Thu Jul 28 12:20:13 2005 UTC)"
diff --git a/include/sound/vx_core.h b/include/sound/vx_core.h
index a7e29933f2d..7a60a388866 100644
--- a/include/sound/vx_core.h
+++ b/include/sound/vx_core.h
@@ -233,37 +233,37 @@ irqreturn_t snd_vx_irq_handler(int irq, void *dev, struct pt_regs *regs);
 /*
  * lowlevel functions
  */
-inline static int vx_test_and_ack(vx_core_t *chip)
+static inline int vx_test_and_ack(vx_core_t *chip)
 {
 	snd_assert(chip->ops->test_and_ack, return -ENXIO);
 	return chip->ops->test_and_ack(chip);
 }
 
-inline static void vx_validate_irq(vx_core_t *chip, int enable)
+static inline void vx_validate_irq(vx_core_t *chip, int enable)
 {
 	snd_assert(chip->ops->validate_irq, return);
 	chip->ops->validate_irq(chip, enable);
 }
 
-inline static unsigned char snd_vx_inb(vx_core_t *chip, int reg)
+static inline unsigned char snd_vx_inb(vx_core_t *chip, int reg)
 {
 	snd_assert(chip->ops->in8, return 0);
 	return chip->ops->in8(chip, reg);
 }
 
-inline static unsigned int snd_vx_inl(vx_core_t *chip, int reg)
+static inline unsigned int snd_vx_inl(vx_core_t *chip, int reg)
 {
 	snd_assert(chip->ops->in32, return 0);
 	return chip->ops->in32(chip, reg);
 }
 
-inline static void snd_vx_outb(vx_core_t *chip, int reg, unsigned char val)
+static inline void snd_vx_outb(vx_core_t *chip, int reg, unsigned char val)
 {
 	snd_assert(chip->ops->out8, return);
 	chip->ops->out8(chip, reg, val);
 }
 
-inline static void snd_vx_outl(vx_core_t *chip, int reg, unsigned int val)
+static inline void snd_vx_outl(vx_core_t *chip, int reg, unsigned int val)
 {
 	snd_assert(chip->ops->out32, return);
 	chip->ops->out32(chip, reg, val);
@@ -303,14 +303,14 @@ int snd_vx_check_reg_bit(vx_core_t *chip, int reg, int mask, int bit, int time);
 /*
  * pseudo-DMA transfer
  */
-inline static void vx_pseudo_dma_write(vx_core_t *chip, snd_pcm_runtime_t *runtime,
+static inline void vx_pseudo_dma_write(vx_core_t *chip, snd_pcm_runtime_t *runtime,
 				       vx_pipe_t *pipe, int count)
 {
 	snd_assert(chip->ops->dma_write, return);
 	chip->ops->dma_write(chip, runtime, pipe, count);
 }
 
-inline static void vx_pseudo_dma_read(vx_core_t *chip, snd_pcm_runtime_t *runtime,
+static inline void vx_pseudo_dma_read(vx_core_t *chip, snd_pcm_runtime_t *runtime,
 				      vx_pipe_t *pipe, int count)
 {
 	snd_assert(chip->ops->dma_read, return);
diff --git a/init/Kconfig b/init/Kconfig
index 75755ef50c8..05a75c4f5ce 100644
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -231,7 +231,7 @@ config CPUSETS
 	bool "Cpuset support"
 	depends on SMP
 	help
-	  This options will let you create and manage CPUSET's which
+	  This option will let you create and manage CPUSETs which
 	  allow dynamically partitioning a system into sets of CPUs and
 	  Memory Nodes and assigning tasks to run only within those sets.
 	  This is primarily useful on large SMP or NUMA systems.
diff --git a/init/main.c b/init/main.c
index b5e421e39ed..c9c311cf177 100644
--- a/init/main.c
+++ b/init/main.c
@@ -51,6 +51,7 @@
 #include <asm/io.h>
 #include <asm/bugs.h>
 #include <asm/setup.h>
+#include <asm/sections.h>
 
 /*
  * This is one of the first .c files built. Error out early
@@ -323,8 +324,6 @@ static void __init setup_per_cpu_areas(void)
 {
 	unsigned long size, i;
 	char *ptr;
-	/* Created by linker magic */
-	extern char __per_cpu_start[], __per_cpu_end[];
 
 	/* Copy section for each CPU (we discard the original) */
 	size = ALIGN(__per_cpu_end - __per_cpu_start, SMP_CACHE_BYTES);
diff --git a/ipc/sem.c b/ipc/sem.c
index 7e8a25c82ef..70975ce0784 100644
--- a/ipc/sem.c
+++ b/ipc/sem.c
@@ -895,7 +895,7 @@ static inline void lock_semundo(void)
 	struct sem_undo_list *undo_list;
 
 	undo_list = current->sysvsem.undo_list;
-	if ((undo_list != NULL) && (atomic_read(&undo_list->refcnt) != 1))
+	if (undo_list)
 		spin_lock(&undo_list->lock);
 }
 
@@ -915,7 +915,7 @@ static inline void unlock_semundo(void)
 	struct sem_undo_list *undo_list;
 
 	undo_list = current->sysvsem.undo_list;
-	if ((undo_list != NULL) && (atomic_read(&undo_list->refcnt) != 1))
+	if (undo_list)
 		spin_unlock(&undo_list->lock);
 }
 
@@ -943,9 +943,7 @@ static inline int get_undo_list(struct sem_undo_list **undo_listp)
 		if (undo_list == NULL)
 			return -ENOMEM;
 		memset(undo_list, 0, size);
-		/* don't initialize unodhd->lock here.  It's done
-		 * in copy_semundo() instead.
-		 */
+		spin_lock_init(&undo_list->lock);
 		atomic_set(&undo_list->refcnt, 1);
 		current->sysvsem.undo_list = undo_list;
 	}
@@ -1231,8 +1229,6 @@ int copy_semundo(unsigned long clone_flags, struct task_struct *tsk)
 		error = get_undo_list(&undo_list);
 		if (error)
 			return error;
-		if (atomic_read(&undo_list->refcnt) == 1)
-			spin_lock_init(&undo_list->lock);
 		atomic_inc(&undo_list->refcnt);
 		tsk->sysvsem.undo_list = undo_list;
 	} else 
diff --git a/ipc/shm.c b/ipc/shm.c
index cce022435db..1d6cf08d950 100644
--- a/ipc/shm.c
+++ b/ipc/shm.c
@@ -170,7 +170,7 @@ static struct vm_operations_struct shm_vm_ops = {
 	.open	= shm_open,	/* callback for a new vm-area open */
 	.close	= shm_close,	/* callback for when the vm-area is released */
 	.nopage	= shmem_nopage,
-#ifdef CONFIG_NUMA
+#if defined(CONFIG_NUMA) && defined(CONFIG_SHMEM)
 	.set_policy = shmem_set_policy,
 	.get_policy = shmem_get_policy,
 #endif
diff --git a/kernel/capability.c b/kernel/capability.c
index 64db1ee820c..8986a37a67e 100644
--- a/kernel/capability.c
+++ b/kernel/capability.c
@@ -31,8 +31,14 @@ static DEFINE_SPINLOCK(task_capability_lock);
  * uninteresting and/or not to be changed.
  */
 
-/*
+/**
  * sys_capget - get the capabilities of a given process.
+ * @header: pointer to struct that contains capability version and
+ *	target pid data
+ * @dataptr: pointer to struct that contains the effective, permitted,
+ *	and inheritable capabilities that are returned
+ *
+ * Returns 0 on success and < 0 on error.
  */
 asmlinkage long sys_capget(cap_user_header_t header, cap_user_data_t dataptr)
 {
@@ -141,8 +147,14 @@ static inline int cap_set_all(kernel_cap_t *effective,
      return ret;
 }
 
-/*
- * sys_capset - set capabilities for a given process, all processes, or all
+/**
+ * sys_capset - set capabilities for a process or a group of processes
+ * @header: pointer to struct that contains capability version and
+ *	target pid data
+ * @data: pointer to struct that contains the effective, permitted,
+ *	and inheritable capabilities
+ *
+ * Set capabilities for a given process, all processes, or all
  * processes in a given process group.
  *
  * The restrictions on setting capabilities are specified as:
@@ -152,6 +164,8 @@ static inline int cap_set_all(kernel_cap_t *effective,
  * I: any raised capabilities must be a subset of the (old current) permitted
  * P: any raised capabilities must be a subset of the (old current) permitted
  * E: must be set to a subset of (new target) permitted
+ *
+ * Returns 0 on success and < 0 on error.
  */
 asmlinkage long sys_capset(cap_user_header_t header, const cap_user_data_t data)
 {
diff --git a/kernel/cpuset.c b/kernel/cpuset.c
index 984c0bf3807..805fb909731 100644
--- a/kernel/cpuset.c
+++ b/kernel/cpuset.c
@@ -1440,10 +1440,10 @@ void __init cpuset_init_smp(void)
 
 /**
  * cpuset_fork - attach newly forked task to its parents cpuset.
- * @p: pointer to task_struct of forking parent process.
+ * @tsk: pointer to task_struct of forking parent process.
  *
  * Description: By default, on fork, a task inherits its
- * parents cpuset.  The pointer to the shared cpuset is
+ * parent's cpuset.  The pointer to the shared cpuset is
  * automatically copied in fork.c by dup_task_struct().
  * This cpuset_fork() routine need only increment the usage
  * counter in that cpuset.
@@ -1471,7 +1471,6 @@ void cpuset_fork(struct task_struct *tsk)
  * by the cpuset_sem semaphore.  If you don't hold cpuset_sem,
  * then a zero cpuset use count is a license to any other task to
  * nuke the cpuset immediately.
- *
  **/
 
 void cpuset_exit(struct task_struct *tsk)
@@ -1521,7 +1520,9 @@ void cpuset_init_current_mems_allowed(void)
 	current->mems_allowed = NODE_MASK_ALL;
 }
 
-/*
+/**
+ * cpuset_update_current_mems_allowed - update mems parameters to new values
+ *
  * If the current tasks cpusets mems_allowed changed behind our backs,
  * update current->mems_allowed and mems_generation to the new value.
  * Do not call this routine if in_interrupt().
@@ -1540,13 +1541,20 @@ void cpuset_update_current_mems_allowed(void)
 	}
 }
 
+/**
+ * cpuset_restrict_to_mems_allowed - limit nodes to current mems_allowed
+ * @nodes: pointer to a node bitmap that is and-ed with mems_allowed
+ */
 void cpuset_restrict_to_mems_allowed(unsigned long *nodes)
 {
 	bitmap_and(nodes, nodes, nodes_addr(current->mems_allowed),
 							MAX_NUMNODES);
 }
 
-/*
+/**
+ * cpuset_zonelist_valid_mems_allowed - check zonelist vs. curremt mems_allowed
+ * @zl: the zonelist to be checked
+ *
  * Are any of the nodes on zonelist zl allowed in current->mems_allowed?
  */
 int cpuset_zonelist_valid_mems_allowed(struct zonelist *zl)
@@ -1562,8 +1570,12 @@ int cpuset_zonelist_valid_mems_allowed(struct zonelist *zl)
 	return 0;
 }
 
-/*
- * Is 'current' valid, and is zone z allowed in current->mems_allowed?
+/**
+ * cpuset_zone_allowed - is zone z allowed in current->mems_allowed
+ * @z: zone in question
+ *
+ * Is zone z allowed in current->mems_allowed, or is
+ * the CPU in interrupt context? (zone is always allowed in this case)
  */
 int cpuset_zone_allowed(struct zone *z)
 {
diff --git a/kernel/crash_dump.c b/kernel/crash_dump.c
index 459ba49e376..334c37f5218 100644
--- a/kernel/crash_dump.c
+++ b/kernel/crash_dump.c
@@ -18,7 +18,16 @@
 /* Stores the physical address of elf header of crash image. */
 unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX;
 
-/*
+/**
+ * copy_oldmem_page - copy one page from "oldmem"
+ * @pfn: page frame number to be copied
+ * @buf: target memory address for the copy; this can be in kernel address
+ *	space or user address space (see @userbuf)
+ * @csize: number of bytes to copy
+ * @offset: offset in bytes into the page (based on pfn) to begin the copy
+ * @userbuf: if set, @buf is in user address space, use copy_to_user(),
+ *	otherwise @buf is in kernel address space, use memcpy().
+ *
  * Copy a page from "oldmem". For this page, there is no pte mapped
  * in the current kernel. We stitch up a pte, similar to kmap_atomic.
  */
diff --git a/kernel/exit.c b/kernel/exit.c
index 9d1b10ed013..5b0fb9f09f2 100644
--- a/kernel/exit.c
+++ b/kernel/exit.c
@@ -829,8 +829,10 @@ fastcall NORET_TYPE void do_exit(long code)
 	acct_update_integrals(tsk);
 	update_mem_hiwater(tsk);
 	group_dead = atomic_dec_and_test(&tsk->signal->live);
-	if (group_dead)
+	if (group_dead) {
+ 		del_timer_sync(&tsk->signal->real_timer);
 		acct_process(code);
+	}
 	exit_mm(tsk);
 
 	exit_sem(tsk);
diff --git a/kernel/itimer.c b/kernel/itimer.c
index a72cb0e5aa4..7c1b25e25e4 100644
--- a/kernel/itimer.c
+++ b/kernel/itimer.c
@@ -112,28 +112,11 @@ asmlinkage long sys_getitimer(int which, struct itimerval __user *value)
 	return error;
 }
 
-/*
- * Called with P->sighand->siglock held and P->signal->real_timer inactive.
- * If interval is nonzero, arm the timer for interval ticks from now.
- */
-static inline void it_real_arm(struct task_struct *p, unsigned long interval)
-{
-	p->signal->it_real_value = interval; /* XXX unnecessary field?? */
-	if (interval == 0)
-		return;
-	if (interval > (unsigned long) LONG_MAX)
-		interval = LONG_MAX;
-	/* the "+ 1" below makes sure that the timer doesn't go off before
-	 * the interval requested. This could happen if
-	 * time requested % (usecs per jiffy) is more than the usecs left
-	 * in the current jiffy */
-	p->signal->real_timer.expires = jiffies + interval + 1;
-	add_timer(&p->signal->real_timer);
-}
 
 void it_real_fn(unsigned long __data)
 {
 	struct task_struct * p = (struct task_struct *) __data;
+	unsigned long inc = p->signal->it_real_incr;
 
 	send_group_sig_info(SIGALRM, SEND_SIG_PRIV, p);
 
@@ -141,14 +124,23 @@ void it_real_fn(unsigned long __data)
 	 * Now restart the timer if necessary.  We don't need any locking
 	 * here because do_setitimer makes sure we have finished running
 	 * before it touches anything.
+	 * Note, we KNOW we are (or should be) at a jiffie edge here so
+	 * we don't need the +1 stuff.  Also, we want to use the prior
+	 * expire value so as to not "slip" a jiffie if we are late.
+	 * Deal with requesting a time prior to "now" here rather than
+	 * in add_timer.
 	 */
-	it_real_arm(p, p->signal->it_real_incr);
+	if (!inc)
+		return;
+	while (time_before_eq(p->signal->real_timer.expires, jiffies))
+		p->signal->real_timer.expires += inc;
+	add_timer(&p->signal->real_timer);
 }
 
 int do_setitimer(int which, struct itimerval *value, struct itimerval *ovalue)
 {
 	struct task_struct *tsk = current;
- 	unsigned long val, interval;
+ 	unsigned long val, interval, expires;
 	cputime_t cval, cinterval, nval, ninterval;
 
 	switch (which) {
@@ -164,7 +156,10 @@ again:
 		}
 		tsk->signal->it_real_incr =
 			timeval_to_jiffies(&value->it_interval);
-		it_real_arm(tsk, timeval_to_jiffies(&value->it_value));
+		expires = timeval_to_jiffies(&value->it_value);
+		if (expires)
+			mod_timer(&tsk->signal->real_timer,
+				  jiffies + 1 + expires);
 		spin_unlock_irq(&tsk->sighand->siglock);
 		if (ovalue) {
 			jiffies_to_timeval(val, &ovalue->it_value);
diff --git a/kernel/module.c b/kernel/module.c
index 068e271ab3a..c32995fbd8f 100644
--- a/kernel/module.c
+++ b/kernel/module.c
@@ -250,13 +250,18 @@ static inline unsigned int block_size(int val)
 /* Created by linker magic */
 extern char __per_cpu_start[], __per_cpu_end[];
 
-static void *percpu_modalloc(unsigned long size, unsigned long align)
+static void *percpu_modalloc(unsigned long size, unsigned long align,
+			     const char *name)
 {
 	unsigned long extra;
 	unsigned int i;
 	void *ptr;
 
-	BUG_ON(align > SMP_CACHE_BYTES);
+	if (align > SMP_CACHE_BYTES) {
+		printk(KERN_WARNING "%s: per-cpu alignment %li > %i\n",
+		       name, align, SMP_CACHE_BYTES);
+		align = SMP_CACHE_BYTES;
+	}
 
 	ptr = __per_cpu_start;
 	for (i = 0; i < pcpu_num_used; ptr += block_size(pcpu_size[i]), i++) {
@@ -348,7 +353,8 @@ static int percpu_modinit(void)
 }	
 __initcall(percpu_modinit);
 #else /* ... !CONFIG_SMP */
-static inline void *percpu_modalloc(unsigned long size, unsigned long align)
+static inline void *percpu_modalloc(unsigned long size, unsigned long align,
+				    const char *name)
 {
 	return NULL;
 }
@@ -1644,7 +1650,8 @@ static struct module *load_module(void __user *umod,
 	if (pcpuindex) {
 		/* We have a special allocation for this section. */
 		percpu = percpu_modalloc(sechdrs[pcpuindex].sh_size,
-					 sechdrs[pcpuindex].sh_addralign);
+					 sechdrs[pcpuindex].sh_addralign,
+					 mod->name);
 		if (!percpu) {
 			err = -ENOMEM;
 			goto free_mod;
diff --git a/kernel/posix-timers.c b/kernel/posix-timers.c
index 5b7b4736d82..38798a2ff99 100644
--- a/kernel/posix-timers.c
+++ b/kernel/posix-timers.c
@@ -896,21 +896,10 @@ static int adjust_abs_time(struct k_clock *clock, struct timespec *tp,
 			jiffies_64_f = get_jiffies_64();
 		}
 		/*
-		 * Take away now to get delta
+		 * Take away now to get delta and normalize
 		 */
-		oc.tv_sec -= now.tv_sec;
-		oc.tv_nsec -= now.tv_nsec;
-		/*
-		 * Normalize...
-		 */
-		while ((oc.tv_nsec - NSEC_PER_SEC) >= 0) {
-			oc.tv_nsec -= NSEC_PER_SEC;
-			oc.tv_sec++;
-		}
-		while ((oc.tv_nsec) < 0) {
-			oc.tv_nsec += NSEC_PER_SEC;
-			oc.tv_sec--;
-		}
+		set_normalized_timespec(&oc, oc.tv_sec - now.tv_sec,
+					oc.tv_nsec - now.tv_nsec);
 	}else{
 		jiffies_64_f = get_jiffies_64();
 	}
@@ -1177,7 +1166,6 @@ void exit_itimers(struct signal_struct *sig)
 		tmr = list_entry(sig->posix_timers.next, struct k_itimer, list);
 		itimer_delete(tmr);
 	}
-	del_timer_sync(&sig->real_timer);
 }
 
 /*
diff --git a/kernel/power/smp.c b/kernel/power/smp.c
index bbe23079c62..911fc62b822 100644
--- a/kernel/power/smp.c
+++ b/kernel/power/smp.c
@@ -38,7 +38,7 @@ void disable_nonboot_cpus(void)
 		}
 		printk("Error taking cpu %d down: %d\n", cpu, error);
 	}
-	BUG_ON(smp_processor_id() != 0);
+	BUG_ON(raw_smp_processor_id() != 0);
 	if (error)
 		panic("cpus not sleeping");
 }
diff --git a/kernel/sys.c b/kernel/sys.c
index a74039036fb..0bcaed6560a 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -371,7 +371,6 @@ void kernel_restart(char *cmd)
 {
 	notifier_call_chain(&reboot_notifier_list, SYS_RESTART, cmd);
 	system_state = SYSTEM_RESTART;
-	device_suspend(PMSG_FREEZE);
 	device_shutdown();
 	if (!cmd) {
 		printk(KERN_EMERG "Restarting system.\n");
@@ -393,7 +392,6 @@ void kernel_kexec(void)
 	}
 	notifier_call_chain(&reboot_notifier_list, SYS_RESTART, NULL);
 	system_state = SYSTEM_RESTART;
-	device_suspend(PMSG_FREEZE);
 	device_shutdown();
 	printk(KERN_EMERG "Starting new kernel\n");
 	machine_shutdown();
@@ -406,7 +404,6 @@ void kernel_halt(void)
 {
 	notifier_call_chain(&reboot_notifier_list, SYS_HALT, NULL);
 	system_state = SYSTEM_HALT;
-	device_suspend(PMSG_SUSPEND);
 	device_shutdown();
 	printk(KERN_EMERG "System halted.\n");
 	machine_halt();
@@ -417,7 +414,6 @@ void kernel_power_off(void)
 {
 	notifier_call_chain(&reboot_notifier_list, SYS_POWER_OFF, NULL);
 	system_state = SYSTEM_POWER_OFF;
-	device_suspend(PMSG_SUSPEND);
 	device_shutdown();
 	printk(KERN_EMERG "Power down.\n");
 	machine_power_off();
diff --git a/kernel/sys_ni.c b/kernel/sys_ni.c
index 42b40ae5ead..1ab2370e2ef 100644
--- a/kernel/sys_ni.c
+++ b/kernel/sys_ni.c
@@ -79,7 +79,6 @@ cond_syscall(sys_request_key);
 cond_syscall(sys_keyctl);
 cond_syscall(compat_sys_keyctl);
 cond_syscall(compat_sys_socketcall);
-cond_syscall(sys_set_zone_reclaim);
 cond_syscall(sys_inotify_init);
 cond_syscall(sys_inotify_add_watch);
 cond_syscall(sys_inotify_rm_watch);
diff --git a/kernel/sysctl.c b/kernel/sysctl.c
index e60b9c36f1f..3e0bbee549e 100644
--- a/kernel/sysctl.c
+++ b/kernel/sysctl.c
@@ -114,6 +114,7 @@ extern int unaligned_enabled;
 extern int sysctl_ieee_emulation_warnings;
 #endif
 extern int sysctl_userprocess_debug;
+extern int spin_retry;
 #endif
 
 extern int sysctl_hz_timer;
@@ -647,7 +648,16 @@ static ctl_table kern_table[] = {
 		.mode		= 0644,
 		.proc_handler	= &proc_dointvec,
 	},
-
+#if defined(CONFIG_ARCH_S390)
+	{
+		.ctl_name	= KERN_SPIN_RETRY,
+		.procname	= "spin_retry",
+		.data		= &spin_retry,
+		.maxlen		= sizeof (int),
+		.mode		= 0644,
+		.proc_handler	= &proc_dointvec,
+	},
+#endif
 	{ .ctl_name = 0 }
 };
 
diff --git a/kernel/time.c b/kernel/time.c
index d4335c1c884..dd5ae1162a8 100644
--- a/kernel/time.c
+++ b/kernel/time.c
@@ -128,7 +128,7 @@ asmlinkage long sys_gettimeofday(struct timeval __user *tv, struct timezone __us
  * as real UNIX machines always do it. This avoids all headaches about
  * daylight saving times and warping kernel clocks.
  */
-inline static void warp_clock(void)
+static inline void warp_clock(void)
 {
 	write_seqlock_irq(&xtime_lock);
 	wall_to_monotonic.tv_sec -= sys_tz.tz_minuteswest * 60;
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index 0c421295e61..299f7f3b5b0 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -141,7 +141,7 @@ config DEBUG_IOREMAP
 
 config DEBUG_FS
 	bool "Debug Filesystem"
-	depends on DEBUG_KERNEL
+	depends on DEBUG_KERNEL && SYSFS
 	help
 	  debugfs is a virtual file system that kernel developers use to put
 	  debugging files into.  Enable this option to be able to read and
diff --git a/lib/Makefile b/lib/Makefile
index beed1585294..f28d9031303 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -5,11 +5,11 @@
 lib-y := errno.o ctype.o string.o vsprintf.o cmdline.o \
 	 bust_spinlocks.o rbtree.o radix-tree.o dump_stack.o \
 	 idr.o div64.o int_sqrt.o bitmap.o extable.o prio_tree.o \
-	 sha1.o halfmd4.o
+	 sha1.o
 
 lib-y	+= kobject.o kref.o kobject_uevent.o klist.o
 
-obj-y += sort.o parser.o
+obj-y += sort.o parser.o halfmd4.o
 
 ifeq ($(CONFIG_DEBUG_KOBJECT),y)
 CFLAGS_kobject.o += -DDEBUG
diff --git a/lib/crc32.c b/lib/crc32.c
index 58b222783f9..065198f98b3 100644
--- a/lib/crc32.c
+++ b/lib/crc32.c
@@ -473,7 +473,7 @@ static u32 test_step(u32 init, unsigned char *buf, size_t len)
 	init = bitreverse(init);
 	crc2 = bitreverse(crc1);
 	if (crc1 != bitreverse(crc2))
-		printf("\nBit reversal fail: 0x%08x -> %0x08x -> 0x%08x\n",
+		printf("\nBit reversal fail: 0x%08x -> 0x%08x -> 0x%08x\n",
 		       crc1, crc2, bitreverse(crc2));
 	crc1 = crc32_le(init, buf, len);
 	if (crc1 != crc2)
diff --git a/lib/inflate.c b/lib/inflate.c
index 75e7d303c72..6db6e98d163 100644
--- a/lib/inflate.c
+++ b/lib/inflate.c
@@ -326,7 +326,7 @@ DEBG("huft1 ");
   {
     *t = (struct huft *)NULL;
     *m = 0;
-    return 0;
+    return 2;
   }
 
 DEBG("huft2 ");
@@ -374,6 +374,7 @@ DEBG("huft5 ");
     if ((j = *p++) != 0)
       v[x[j]++] = i;
   } while (++i < n);
+  n = x[g];                   /* set n to length of v */
 
 DEBG("h6 ");
 
@@ -410,12 +411,13 @@ DEBG1("1 ");
 DEBG1("2 ");
           f -= a + 1;           /* deduct codes from patterns left */
           xp = c + k;
-          while (++j < z)       /* try smaller tables up to z bits */
-          {
-            if ((f <<= 1) <= *++xp)
-              break;            /* enough codes to use up j bits */
-            f -= *xp;           /* else deduct codes from patterns */
-          }
+          if (j < z)
+            while (++j < z)       /* try smaller tables up to z bits */
+            {
+              if ((f <<= 1) <= *++xp)
+                break;            /* enough codes to use up j bits */
+              f -= *xp;           /* else deduct codes from patterns */
+            }
         }
 DEBG1("3 ");
         z = 1 << j;             /* table entries for j-bit table */
diff --git a/lib/zlib_inflate/inftrees.c b/lib/zlib_inflate/inftrees.c
index 874950ec485..c5f66fbb0dd 100644
--- a/lib/zlib_inflate/inftrees.c
+++ b/lib/zlib_inflate/inftrees.c
@@ -141,7 +141,7 @@ static int huft_build(
   {
     *t = NULL;
     *m = 0;
-    return Z_OK;
+    return Z_DATA_ERROR;
   }
 
 
diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index fbd1111ea11..6bf720bc662 100644
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -301,6 +301,7 @@ void unmap_hugepage_range(struct vm_area_struct *vma, unsigned long start,
 {
 	struct mm_struct *mm = vma->vm_mm;
 	unsigned long address;
+	pte_t *ptep;
 	pte_t pte;
 	struct page *page;
 
@@ -309,9 +310,17 @@ void unmap_hugepage_range(struct vm_area_struct *vma, unsigned long start,
 	BUG_ON(end & ~HPAGE_MASK);
 
 	for (address = start; address < end; address += HPAGE_SIZE) {
-		pte = huge_ptep_get_and_clear(mm, address, huge_pte_offset(mm, address));
+		ptep = huge_pte_offset(mm, address);
+		if (! ptep)
+			/* This can happen on truncate, or if an
+			 * mmap() is aborted due to an error before
+			 * the prefault */
+			continue;
+
+		pte = huge_ptep_get_and_clear(mm, address, ptep);
 		if (pte_none(pte))
 			continue;
+
 		page = pte_page(pte);
 		put_page(page);
 	}
diff --git a/mm/madvise.c b/mm/madvise.c
index 73180a22877..c8c01a12fea 100644
--- a/mm/madvise.c
+++ b/mm/madvise.c
@@ -83,9 +83,6 @@ static long madvise_willneed(struct vm_area_struct * vma,
 {
 	struct file *file = vma->vm_file;
 
-	if (!file)
-		return -EBADF;
-
 	if (file->f_mapping->a_ops->get_xip_page) {
 		/* no bad return value, but ignore advice */
 		return 0;
@@ -140,11 +137,16 @@ static long madvise_dontneed(struct vm_area_struct * vma,
 	return 0;
 }
 
-static long madvise_vma(struct vm_area_struct *vma, struct vm_area_struct **prev,
-			unsigned long start, unsigned long end, int behavior)
+static long
+madvise_vma(struct vm_area_struct *vma, struct vm_area_struct **prev,
+		unsigned long start, unsigned long end, int behavior)
 {
+	struct file *filp = vma->vm_file;
 	long error = -EBADF;
 
+	if (!filp)
+		goto  out;
+
 	switch (behavior) {
 	case MADV_NORMAL:
 	case MADV_SEQUENTIAL:
@@ -165,6 +167,7 @@ static long madvise_vma(struct vm_area_struct *vma, struct vm_area_struct **prev
 		break;
 	}
 		
+out:
 	return error;
 }
 
diff --git a/mm/memory.c b/mm/memory.c
index beabdefa625..e046b7e4b53 100644
--- a/mm/memory.c
+++ b/mm/memory.c
@@ -776,8 +776,8 @@ unsigned long zap_page_range(struct vm_area_struct *vma, unsigned long address,
  * Do a quick page-table lookup for a single page.
  * mm->page_table_lock must be held.
  */
-static struct page *
-__follow_page(struct mm_struct *mm, unsigned long address, int read, int write)
+static struct page *__follow_page(struct mm_struct *mm, unsigned long address,
+			int read, int write, int accessed)
 {
 	pgd_t *pgd;
 	pud_t *pud;
@@ -818,9 +818,11 @@ __follow_page(struct mm_struct *mm, unsigned long address, int read, int write)
 		pfn = pte_pfn(pte);
 		if (pfn_valid(pfn)) {
 			page = pfn_to_page(pfn);
-			if (write && !pte_dirty(pte) && !PageDirty(page))
-				set_page_dirty(page);
-			mark_page_accessed(page);
+			if (accessed) {
+				if (write && !pte_dirty(pte) &&!PageDirty(page))
+					set_page_dirty(page);
+				mark_page_accessed(page);
+			}
 			return page;
 		}
 	}
@@ -829,16 +831,19 @@ out:
 	return NULL;
 }
 
-struct page *
+inline struct page *
 follow_page(struct mm_struct *mm, unsigned long address, int write)
 {
-	return __follow_page(mm, address, /*read*/0, write);
+	return __follow_page(mm, address, 0, write, 1);
 }
 
-int
-check_user_page_readable(struct mm_struct *mm, unsigned long address)
+/*
+ * check_user_page_readable() can be called frm niterrupt context by oprofile,
+ * so we need to avoid taking any non-irq-safe locks
+ */
+int check_user_page_readable(struct mm_struct *mm, unsigned long address)
 {
-	return __follow_page(mm, address, /*read*/1, /*write*/0) != NULL;
+	return __follow_page(mm, address, 1, 0, 0) != NULL;
 }
 EXPORT_SYMBOL(check_user_page_readable);
 
@@ -908,9 +913,13 @@ int get_user_pages(struct task_struct *tsk, struct mm_struct *mm,
 			pud = pud_offset(pgd, pg);
 			BUG_ON(pud_none(*pud));
 			pmd = pmd_offset(pud, pg);
-			BUG_ON(pmd_none(*pmd));
+			if (pmd_none(*pmd))
+				return i ? : -EFAULT;
 			pte = pte_offset_map(pmd, pg);
-			BUG_ON(pte_none(*pte));
+			if (pte_none(*pte)) {
+				pte_unmap(pte);
+				return i ? : -EFAULT;
+			}
 			if (pages) {
 				pages[i] = pte_page(*pte);
 				get_page(pages[i]);
@@ -935,11 +944,13 @@ int get_user_pages(struct task_struct *tsk, struct mm_struct *mm,
 		}
 		spin_lock(&mm->page_table_lock);
 		do {
+			int write_access = write;
 			struct page *page;
-			int lookup_write = write;
 
 			cond_resched_lock(&mm->page_table_lock);
-			while (!(page = follow_page(mm, start, lookup_write))) {
+			while (!(page = follow_page(mm, start, write_access))) {
+				int ret;
+
 				/*
 				 * Shortcut for anonymous pages. We don't want
 				 * to force the creation of pages tables for
@@ -947,13 +958,23 @@ int get_user_pages(struct task_struct *tsk, struct mm_struct *mm,
 				 * nobody touched so far. This is important
 				 * for doing a core dump for these mappings.
 				 */
-				if (!lookup_write &&
-				    untouched_anonymous_page(mm,vma,start)) {
+				if (!write && untouched_anonymous_page(mm,vma,start)) {
 					page = ZERO_PAGE(start);
 					break;
 				}
 				spin_unlock(&mm->page_table_lock);
-				switch (handle_mm_fault(mm,vma,start,write)) {
+				ret = __handle_mm_fault(mm, vma, start, write_access);
+
+				/*
+				 * The VM_FAULT_WRITE bit tells us that do_wp_page has
+				 * broken COW when necessary, even if maybe_mkwrite
+				 * decided not to set pte_write. We can thus safely do
+				 * subsequent page lookups as if they were reads.
+				 */
+				if (ret & VM_FAULT_WRITE)
+					write_access = 0;
+				
+				switch (ret & ~VM_FAULT_WRITE) {
 				case VM_FAULT_MINOR:
 					tsk->min_flt++;
 					break;
@@ -967,14 +988,6 @@ int get_user_pages(struct task_struct *tsk, struct mm_struct *mm,
 				default:
 					BUG();
 				}
-				/*
-				 * Now that we have performed a write fault
-				 * and surely no longer have a shared page we
-				 * shouldn't write, we shouldn't ignore an
-				 * unwritable page in the page table if
-				 * we are forcing write access.
-				 */
-				lookup_write = write && !force;
 				spin_lock(&mm->page_table_lock);
 			}
 			if (pages) {
@@ -1224,6 +1237,7 @@ static int do_wp_page(struct mm_struct *mm, struct vm_area_struct * vma,
 	struct page *old_page, *new_page;
 	unsigned long pfn = pte_pfn(pte);
 	pte_t entry;
+	int ret;
 
 	if (unlikely(!pfn_valid(pfn))) {
 		/*
@@ -1251,7 +1265,7 @@ static int do_wp_page(struct mm_struct *mm, struct vm_area_struct * vma,
 			lazy_mmu_prot_update(entry);
 			pte_unmap(page_table);
 			spin_unlock(&mm->page_table_lock);
-			return VM_FAULT_MINOR;
+			return VM_FAULT_MINOR|VM_FAULT_WRITE;
 		}
 	}
 	pte_unmap(page_table);
@@ -1278,6 +1292,7 @@ static int do_wp_page(struct mm_struct *mm, struct vm_area_struct * vma,
 	/*
 	 * Re-check the pte - we dropped the lock
 	 */
+	ret = VM_FAULT_MINOR;
 	spin_lock(&mm->page_table_lock);
 	page_table = pte_offset_map(pmd, address);
 	if (likely(pte_same(*page_table, pte))) {
@@ -1294,12 +1309,13 @@ static int do_wp_page(struct mm_struct *mm, struct vm_area_struct * vma,
 
 		/* Free the old page.. */
 		new_page = old_page;
+		ret |= VM_FAULT_WRITE;
 	}
 	pte_unmap(page_table);
 	page_cache_release(new_page);
 	page_cache_release(old_page);
 	spin_unlock(&mm->page_table_lock);
-	return VM_FAULT_MINOR;
+	return ret;
 
 no_new_page:
 	page_cache_release(old_page);
@@ -1991,7 +2007,6 @@ static inline int handle_pte_fault(struct mm_struct *mm,
 	if (write_access) {
 		if (!pte_write(entry))
 			return do_wp_page(mm, vma, address, pte, pmd, entry);
-
 		entry = pte_mkdirty(entry);
 	}
 	entry = pte_mkyoung(entry);
@@ -2006,7 +2021,7 @@ static inline int handle_pte_fault(struct mm_struct *mm,
 /*
  * By the time we get here, we already hold the mm semaphore
  */
-int handle_mm_fault(struct mm_struct *mm, struct vm_area_struct * vma,
+int __handle_mm_fault(struct mm_struct *mm, struct vm_area_struct * vma,
 		unsigned long address, int write_access)
 {
 	pgd_t *pgd;
diff --git a/mm/mempolicy.c b/mm/mempolicy.c
index cb41c31e7c8..b4eababc819 100644
--- a/mm/mempolicy.c
+++ b/mm/mempolicy.c
@@ -443,7 +443,7 @@ asmlinkage long sys_set_mempolicy(int mode, unsigned long __user *nmask,
 	struct mempolicy *new;
 	DECLARE_BITMAP(nodes, MAX_NUMNODES);
 
-	if (mode > MPOL_MAX)
+	if (mode < 0 || mode > MPOL_MAX)
 		return -EINVAL;
 	err = get_nodes(nodes, nmask, maxnode, mode);
 	if (err)
@@ -1138,11 +1138,11 @@ void mpol_free_shared_policy(struct shared_policy *p)
 	while (next) {
 		n = rb_entry(next, struct sp_node, nd);
 		next = rb_next(&n->nd);
+		rb_erase(&n->nd, &p->root);
 		mpol_free(n->policy);
 		kmem_cache_free(sn_cache, n);
 	}
 	spin_unlock(&p->lock);
-	p->root = RB_ROOT;
 }
 
 /* assumes fs == KERNEL_DS */
diff --git a/mm/mmap.c b/mm/mmap.c
index da3fa90a0aa..404319477e7 100644
--- a/mm/mmap.c
+++ b/mm/mmap.c
@@ -143,7 +143,11 @@ int __vm_enough_memory(long pages, int cap_sys_admin)
 	   leave 3% of the size of this process for other processes */
 	allowed -= current->mm->total_vm / 32;
 
-	if (atomic_read(&vm_committed_space) < allowed)
+	/*
+	 * cast `allowed' as a signed long because vm_committed_space
+	 * sometimes has a negative value
+	 */
+	if (atomic_read(&vm_committed_space) < (long)allowed)
 		return 0;
 
 	vm_unacct_memory(pages);
diff --git a/mm/mremap.c b/mm/mremap.c
index ec7238a78f3..fc45dc9a617 100644
--- a/mm/mremap.c
+++ b/mm/mremap.c
@@ -229,6 +229,7 @@ static unsigned long move_vma(struct vm_area_struct *vma,
 	 * since do_munmap() will decrement it by old_len == new_len
 	 */
 	mm->total_vm += new_len >> PAGE_SHIFT;
+	__vm_stat_account(mm, vma->vm_flags, vma->vm_file, new_len>>PAGE_SHIFT);
 
 	if (do_munmap(mm, old_addr, old_len) < 0) {
 		/* OOM: unable to split vma, just get accounts right */
@@ -243,7 +244,6 @@ static unsigned long move_vma(struct vm_area_struct *vma,
 			vma->vm_next->vm_flags |= VM_ACCOUNT;
 	}
 
-	__vm_stat_account(mm, vma->vm_flags, vma->vm_file, new_len>>PAGE_SHIFT);
 	if (vm_flags & VM_LOCKED) {
 		mm->locked_vm += new_len >> PAGE_SHIFT;
 		if (new_len > old_len)
diff --git a/mm/nommu.c b/mm/nommu.c
index ce74452c02d..fd4e8df0f02 100644
--- a/mm/nommu.c
+++ b/mm/nommu.c
@@ -1167,7 +1167,11 @@ int __vm_enough_memory(long pages, int cap_sys_admin)
 	   leave 3% of the size of this process for other processes */
 	allowed -= current->mm->total_vm / 32;
 
-	if (atomic_read(&vm_committed_space) < allowed)
+	/*
+	 * cast `allowed' as a signed long because vm_committed_space
+	 * sometimes has a negative value
+	 */
+	if (atomic_read(&vm_committed_space) < (long)allowed)
 		return 0;
 
 	vm_unacct_memory(pages);
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 1d6ba6a4b59..8d088371196 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -1061,20 +1061,19 @@ unsigned int nr_free_pages_pgdat(pg_data_t *pgdat)
 
 static unsigned int nr_free_zone_pages(int offset)
 {
-	pg_data_t *pgdat;
+	/* Just pick one node, since fallback list is circular */
+	pg_data_t *pgdat = NODE_DATA(numa_node_id());
 	unsigned int sum = 0;
 
-	for_each_pgdat(pgdat) {
-		struct zonelist *zonelist = pgdat->node_zonelists + offset;
-		struct zone **zonep = zonelist->zones;
-		struct zone *zone;
+	struct zonelist *zonelist = pgdat->node_zonelists + offset;
+	struct zone **zonep = zonelist->zones;
+	struct zone *zone;
 
-		for (zone = *zonep++; zone; zone = *zonep++) {
-			unsigned long size = zone->present_pages;
-			unsigned long high = zone->pages_high;
-			if (size > high)
-				sum += size - high;
-		}
+	for (zone = *zonep++; zone; zone = *zonep++) {
+		unsigned long size = zone->present_pages;
+		unsigned long high = zone->pages_high;
+		if (size > high)
+			sum += size - high;
 	}
 
 	return sum;
@@ -1861,7 +1860,6 @@ static void __init free_area_init_core(struct pglist_data *pgdat,
 		unsigned long *zones_size, unsigned long *zholes_size)
 {
 	unsigned long i, j;
-	const unsigned long zone_required_alignment = 1UL << (MAX_ORDER-1);
 	int cpu, nid = pgdat->node_id;
 	unsigned long zone_start_pfn = pgdat->node_start_pfn;
 
@@ -1934,9 +1932,6 @@ static void __init free_area_init_core(struct pglist_data *pgdat,
 		zone->zone_mem_map = pfn_to_page(zone_start_pfn);
 		zone->zone_start_pfn = zone_start_pfn;
 
-		if ((zone_start_pfn) & (zone_required_alignment-1))
-			printk(KERN_CRIT "BUG: wrong zone alignment, it will crash\n");
-
 		memmap_init(size, nid, j, zone_start_pfn);
 
 		zonetable_add(zone, nid, j, zone_start_pfn, size);
diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c
index fb5524365bc..ffa26c10bfe 100644
--- a/net/bluetooth/hci_core.c
+++ b/net/bluetooth/hci_core.c
@@ -299,7 +299,6 @@ struct hci_dev *hci_dev_get(int index)
 	read_unlock(&hci_dev_list_lock);
 	return hdev;
 }
-EXPORT_SYMBOL(hci_dev_get);
 
 /* ---- Inquiry support ---- */
 static void inquiry_cache_flush(struct hci_dev *hdev)
@@ -1042,7 +1041,6 @@ int hci_send_cmd(struct hci_dev *hdev, __u16 ogf, __u16 ocf, __u32 plen, void *p
 
 	return 0;
 }
-EXPORT_SYMBOL(hci_send_cmd);
 
 /* Get data from the previously sent command */
 void *hci_sent_cmd_data(struct hci_dev *hdev, __u16 ogf, __u16 ocf)
diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c
index c4b592b4ef1..46367bd129c 100644
--- a/net/bluetooth/hci_event.c
+++ b/net/bluetooth/hci_event.c
@@ -1035,9 +1035,11 @@ void hci_si_event(struct hci_dev *hdev, int type, int dlen, void *data)
 	ev->type = type;
 	memcpy(ev->data, data, dlen);
 
+	bt_cb(skb)->incoming = 1;
+	do_gettimeofday(&skb->stamp);
+
 	skb->pkt_type = HCI_EVENT_PKT;
 	skb->dev = (void *) hdev;
 	hci_send_to_sock(hdev, skb);
 	kfree_skb(skb);
 }
-EXPORT_SYMBOL(hci_si_event);
diff --git a/net/bluetooth/lib.c b/net/bluetooth/lib.c
index 9efb0a09361..ee6a6697991 100644
--- a/net/bluetooth/lib.c
+++ b/net/bluetooth/lib.c
@@ -34,31 +34,6 @@
 
 #include <net/bluetooth/bluetooth.h>
 
-void bt_dump(char *pref, __u8 *buf, int count)
-{
-	char *ptr;
-	char line[100];
-	unsigned int i;
-
-	printk(KERN_INFO "%s: dump, len %d\n", pref, count);
-
-	ptr = line;
-	*ptr = 0;
-	for (i = 0; i < count; i++) {
-		ptr += sprintf(ptr, " %2.2X", buf[i]);
-
-		if (i && !((i + 1) % 20)) {
-			printk(KERN_INFO "%s:%s\n", pref, line);
-			ptr = line;
-			*ptr = 0;
-		}
-	}
-
-	if (line[0])
-		printk(KERN_INFO "%s:%s\n", pref, line);
-}
-EXPORT_SYMBOL(bt_dump);
-
 void baswap(bdaddr_t *dst, bdaddr_t *src)
 {
 	unsigned char *d = (unsigned char *) dst;
diff --git a/net/bluetooth/rfcomm/core.c b/net/bluetooth/rfcomm/core.c
index e9e6fda66f1..27bf5047cd3 100644
--- a/net/bluetooth/rfcomm/core.c
+++ b/net/bluetooth/rfcomm/core.c
@@ -389,8 +389,6 @@ static int __rfcomm_dlc_close(struct rfcomm_dlc *d, int err)
 		rfcomm_dlc_unlock(d);
 
 		skb_queue_purge(&d->tx_queue);
-		rfcomm_session_put(s);
-
 		rfcomm_dlc_unlink(d);
 	}
 
@@ -600,8 +598,6 @@ static struct rfcomm_session *rfcomm_session_create(bdaddr_t *src, bdaddr_t *dst
 		goto failed;
 	}
 
-	rfcomm_session_hold(s);
-
 	s->initiator = 1;
 
 	bacpy(&addr.l2_bdaddr, dst);
diff --git a/net/core/dev.c b/net/core/dev.c
index ff9dc029233..52a3bf7ae17 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -901,8 +901,7 @@ int dev_close(struct net_device *dev)
 	smp_mb__after_clear_bit(); /* Commit netif_running(). */
 	while (test_bit(__LINK_STATE_RX_SCHED, &dev->state)) {
 		/* No hurry. */
-		current->state = TASK_INTERRUPTIBLE;
-		schedule_timeout(1);
+		msleep(1);
 	}
 
 	/*
diff --git a/net/core/dst.c b/net/core/dst.c
index fc434ade527..334790da9f1 100644
--- a/net/core/dst.c
+++ b/net/core/dst.c
@@ -45,6 +45,7 @@ static struct timer_list dst_gc_timer =
 static void dst_run_gc(unsigned long dummy)
 {
 	int    delayed = 0;
+	int    work_performed;
 	struct dst_entry * dst, **dstp;
 
 	if (!spin_trylock(&dst_lock)) {
@@ -52,9 +53,9 @@ static void dst_run_gc(unsigned long dummy)
 		return;
 	}
 
-
 	del_timer(&dst_gc_timer);
 	dstp = &dst_garbage_list;
+	work_performed = 0;
 	while ((dst = *dstp) != NULL) {
 		if (atomic_read(&dst->__refcnt)) {
 			dstp = &dst->next;
@@ -62,6 +63,7 @@ static void dst_run_gc(unsigned long dummy)
 			continue;
 		}
 		*dstp = dst->next;
+		work_performed = 1;
 
 		dst = dst_destroy(dst);
 		if (dst) {
@@ -86,9 +88,14 @@ static void dst_run_gc(unsigned long dummy)
 		dst_gc_timer_inc = DST_GC_MAX;
 		goto out;
 	}
-	if ((dst_gc_timer_expires += dst_gc_timer_inc) > DST_GC_MAX)
-		dst_gc_timer_expires = DST_GC_MAX;
-	dst_gc_timer_inc += DST_GC_INC;
+	if (!work_performed) {
+		if ((dst_gc_timer_expires += dst_gc_timer_inc) > DST_GC_MAX)
+			dst_gc_timer_expires = DST_GC_MAX;
+		dst_gc_timer_inc += DST_GC_INC;
+	} else {
+		dst_gc_timer_inc = DST_GC_INC;
+		dst_gc_timer_expires = DST_GC_MIN;
+	}
 	dst_gc_timer.expires = jiffies + dst_gc_timer_expires;
 #if RT_CACHE_DEBUG >= 2
 	printk("dst_total: %d/%d %ld\n",
diff --git a/net/core/pktgen.c b/net/core/pktgen.c
index 975d651312d..8eb083b6041 100644
--- a/net/core/pktgen.c
+++ b/net/core/pktgen.c
@@ -363,7 +363,7 @@ struct pktgen_thread {
  * All Rights Reserved.
  *
  */
-inline static s64 divremdi3(s64 x, s64 y, int type) 
+static inline s64 divremdi3(s64 x, s64 y, int type)
 {
         u64 a = (x < 0) ? -x : x;
         u64 b = (y < 0) ? -y : y;
diff --git a/net/core/sock.c b/net/core/sock.c
index 8b35ccdc2b3..12f6d9a2a52 100644
--- a/net/core/sock.c
+++ b/net/core/sock.c
@@ -206,13 +206,14 @@ int sock_setsockopt(struct socket *sock, int level, int optname,
 	 */
 
 #ifdef SO_DONTLINGER		/* Compatibility item... */
-	switch (optname) {
-		case SO_DONTLINGER:
-			sock_reset_flag(sk, SOCK_LINGER);
-			return 0;
+	if (optname == SO_DONTLINGER) {
+		lock_sock(sk);
+		sock_reset_flag(sk, SOCK_LINGER);
+		release_sock(sk);
+		return 0;
 	}
-#endif	
-		
+#endif
+	
   	if(optlen<sizeof(int))
   		return(-EINVAL);
   	
diff --git a/net/core/utils.c b/net/core/utils.c
index e11a8654f36..88eb8b68e26 100644
--- a/net/core/utils.c
+++ b/net/core/utils.c
@@ -23,10 +23,10 @@
 #include <linux/percpu.h>
 #include <linux/init.h>
 
+#include <asm/byteorder.h>
 #include <asm/system.h>
 #include <asm/uaccess.h>
 
-
 /*
   This is a maximally equidistributed combined Tausworthe generator
   based on code from GNU Scientific Library 1.5 (30 Jun 2004)
@@ -153,3 +153,38 @@ int net_ratelimit(void)
 EXPORT_SYMBOL(net_random);
 EXPORT_SYMBOL(net_ratelimit);
 EXPORT_SYMBOL(net_srandom);
+
+/*
+ * Convert an ASCII string to binary IP.
+ * This is outside of net/ipv4/ because various code that uses IP addresses
+ * is otherwise not dependent on the TCP/IP stack.
+ */
+
+__u32 in_aton(const char *str)
+{
+	unsigned long l;
+	unsigned int val;
+	int i;
+
+	l = 0;
+	for (i = 0; i < 4; i++)
+	{
+		l <<= 8;
+		if (*str != '\0')
+		{
+			val = 0;
+			while (*str != '\0' && *str != '.')
+			{
+				val *= 10;
+				val += *str - '0';
+				str++;
+			}
+			l |= val;
+			if (*str != '\0')
+				str++;
+		}
+	}
+	return(htonl(l));
+}
+
+EXPORT_SYMBOL(in_aton);
diff --git a/net/ipv4/Kconfig b/net/ipv4/Kconfig
index fc561c0ae8e..0b3d9f1d806 100644
--- a/net/ipv4/Kconfig
+++ b/net/ipv4/Kconfig
@@ -124,7 +124,7 @@ config IP_ROUTE_MULTIPATH
 
 config IP_ROUTE_MULTIPATH_CACHED
 	bool "IP: equal cost multipath with caching support (EXPERIMENTAL)"
-	depends on: IP_ROUTE_MULTIPATH
+	depends on IP_ROUTE_MULTIPATH
 	help
 	  Normally, equal cost multipath routing is not supported by the
 	  routing cache. If you say Y here, alternative routes are cached
diff --git a/net/ipv4/Makefile b/net/ipv4/Makefile
index 5718cdb3a61..55dc6cca1e7 100644
--- a/net/ipv4/Makefile
+++ b/net/ipv4/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the Linux TCP/IP (INET) layer.
 #
 
-obj-y     := utils.o route.o inetpeer.o protocol.o \
+obj-y     := route.o inetpeer.o protocol.o \
 	     ip_input.o ip_fragment.o ip_forward.o ip_options.o \
 	     ip_output.o ip_sockglue.o \
 	     tcp.o tcp_input.o tcp_output.o tcp_timer.o tcp_ipv4.o \
diff --git a/net/ipv4/fib_semantics.c b/net/ipv4/fib_semantics.c
index c886b28ba9f..e278cb9d007 100644
--- a/net/ipv4/fib_semantics.c
+++ b/net/ipv4/fib_semantics.c
@@ -593,10 +593,13 @@ static void fib_hash_move(struct hlist_head *new_info_hash,
 			  struct hlist_head *new_laddrhash,
 			  unsigned int new_size)
 {
+	struct hlist_head *old_info_hash, *old_laddrhash;
 	unsigned int old_size = fib_hash_size;
-	unsigned int i;
+	unsigned int i, bytes;
 
 	write_lock(&fib_info_lock);
+	old_info_hash = fib_info_hash;
+	old_laddrhash = fib_info_laddrhash;
 	fib_hash_size = new_size;
 
 	for (i = 0; i < old_size; i++) {
@@ -636,6 +639,10 @@ static void fib_hash_move(struct hlist_head *new_info_hash,
 	fib_info_laddrhash = new_laddrhash;
 
 	write_unlock(&fib_info_lock);
+
+	bytes = old_size * sizeof(struct hlist_head *);
+	fib_hash_free(old_info_hash, bytes);
+	fib_hash_free(old_laddrhash, bytes);
 }
 
 struct fib_info *
diff --git a/net/ipv4/icmp.c b/net/ipv4/icmp.c
index 279f57abfec..3d78464f64e 100644
--- a/net/ipv4/icmp.c
+++ b/net/ipv4/icmp.c
@@ -936,8 +936,7 @@ int icmp_rcv(struct sk_buff *skb)
 	case CHECKSUM_HW:
 		if (!(u16)csum_fold(skb->csum))
 			break;
-		NETDEBUG(if (net_ratelimit())
-				printk(KERN_DEBUG "icmp v4 hw csum failure\n"));
+		LIMIT_NETDEBUG(printk(KERN_DEBUG "icmp v4 hw csum failure\n"));
 	case CHECKSUM_NONE:
 		if ((u16)csum_fold(skb_checksum(skb, 0, skb->len, 0)))
 			goto error;
diff --git a/net/ipv4/ip_fragment.c b/net/ipv4/ip_fragment.c
index 7f68e27eb4e..eb377ae1530 100644
--- a/net/ipv4/ip_fragment.c
+++ b/net/ipv4/ip_fragment.c
@@ -377,7 +377,7 @@ static struct ipq *ip_frag_create(unsigned hash, struct iphdr *iph, u32 user)
 	return ip_frag_intern(hash, qp);
 
 out_nomem:
-	NETDEBUG(if (net_ratelimit()) printk(KERN_ERR "ip_frag_create: no memory left !\n"));
+	LIMIT_NETDEBUG(printk(KERN_ERR "ip_frag_create: no memory left !\n"));
 	return NULL;
 }
 
@@ -625,10 +625,8 @@ static struct sk_buff *ip_frag_reasm(struct ipq *qp, struct net_device *dev)
 	return head;
 
 out_nomem:
- 	NETDEBUG(if (net_ratelimit())
-	         printk(KERN_ERR 
-			"IP: queue_glue: no memory for gluing queue %p\n",
-			qp));
+ 	LIMIT_NETDEBUG(printk(KERN_ERR "IP: queue_glue: no memory for gluing "
+			      "queue %p\n", qp));
 	goto out_fail;
 out_oversize:
 	if (net_ratelimit())
diff --git a/net/ipv4/ip_gre.c b/net/ipv4/ip_gre.c
index 88483552222..f0d5740d7e2 100644
--- a/net/ipv4/ip_gre.c
+++ b/net/ipv4/ip_gre.c
@@ -290,7 +290,6 @@ static struct ip_tunnel * ipgre_tunnel_locate(struct ip_tunnel_parm *parms, int
 
 	dev_hold(dev);
 	ipgre_tunnel_link(nt);
-	/* Do not decrement MOD_USE_COUNT here. */
 	return nt;
 
 failed:
@@ -1277,12 +1276,28 @@ err1:
 	goto out;
 }
 
-static void ipgre_fini(void)
+static void __exit ipgre_destroy_tunnels(void)
+{
+	int prio;
+
+	for (prio = 0; prio < 4; prio++) {
+		int h;
+		for (h = 0; h < HASH_SIZE; h++) {
+			struct ip_tunnel *t;
+			while ((t = tunnels[prio][h]) != NULL)
+				unregister_netdevice(t->dev);
+		}
+	}
+}
+
+static void __exit ipgre_fini(void)
 {
 	if (inet_del_protocol(&ipgre_protocol, IPPROTO_GRE) < 0)
 		printk(KERN_INFO "ipgre close: can't remove protocol\n");
 
-	unregister_netdev(ipgre_fb_tunnel_dev);
+	rtnl_lock();
+	ipgre_destroy_tunnels();
+	rtnl_unlock();
 }
 
 module_init(ipgre_init);
diff --git a/net/ipv4/ip_sockglue.c b/net/ipv4/ip_sockglue.c
index fc7c481d0d7..ff4bd067b39 100644
--- a/net/ipv4/ip_sockglue.c
+++ b/net/ipv4/ip_sockglue.c
@@ -848,6 +848,9 @@ mc_msf_out:
  
 		case IP_IPSEC_POLICY:
 		case IP_XFRM_POLICY:
+			err = -EPERM;
+			if (!capable(CAP_NET_ADMIN))
+				break;
 			err = xfrm_user_policy(sk, optname, optval, optlen);
 			break;
 
diff --git a/net/ipv4/ipip.c b/net/ipv4/ipip.c
index c3947cd566b..c05c1df0bb0 100644
--- a/net/ipv4/ipip.c
+++ b/net/ipv4/ipip.c
@@ -255,7 +255,6 @@ static struct ip_tunnel * ipip_tunnel_locate(struct ip_tunnel_parm *parms, int c
 
 	dev_hold(dev);
 	ipip_tunnel_link(nt);
-	/* Do not decrement MOD_USE_COUNT here. */
 	return nt;
 
 failed:
@@ -920,12 +919,29 @@ static int __init ipip_init(void)
 	goto out;
 }
 
+static void __exit ipip_destroy_tunnels(void)
+{
+	int prio;
+
+	for (prio = 1; prio < 4; prio++) {
+		int h;
+		for (h = 0; h < HASH_SIZE; h++) {
+			struct ip_tunnel *t;
+			while ((t = tunnels[prio][h]) != NULL)
+				unregister_netdevice(t->dev);
+		}
+	}
+}
+
 static void __exit ipip_fini(void)
 {
 	if (ipip_unregister() < 0)
 		printk(KERN_INFO "ipip close: can't deregister tunnel\n");
 
-	unregister_netdev(ipip_fb_tunnel_dev);
+	rtnl_lock();
+	ipip_destroy_tunnels();
+	unregister_netdevice(ipip_fb_tunnel_dev);
+	rtnl_unlock();
 }
 
 module_init(ipip_init);
diff --git a/net/ipv4/ipmr.c b/net/ipv4/ipmr.c
index 7833d920bdb..dc806b57842 100644
--- a/net/ipv4/ipmr.c
+++ b/net/ipv4/ipmr.c
@@ -362,7 +362,7 @@ out:
 
 /* Fill oifs list. It is called under write locked mrt_lock. */
 
-static void ipmr_update_threshoulds(struct mfc_cache *cache, unsigned char *ttls)
+static void ipmr_update_thresholds(struct mfc_cache *cache, unsigned char *ttls)
 {
 	int vifi;
 
@@ -727,7 +727,7 @@ static int ipmr_mfc_add(struct mfcctl *mfc, int mrtsock)
 	if (c != NULL) {
 		write_lock_bh(&mrt_lock);
 		c->mfc_parent = mfc->mfcc_parent;
-		ipmr_update_threshoulds(c, mfc->mfcc_ttls);
+		ipmr_update_thresholds(c, mfc->mfcc_ttls);
 		if (!mrtsock)
 			c->mfc_flags |= MFC_STATIC;
 		write_unlock_bh(&mrt_lock);
@@ -744,7 +744,7 @@ static int ipmr_mfc_add(struct mfcctl *mfc, int mrtsock)
 	c->mfc_origin=mfc->mfcc_origin.s_addr;
 	c->mfc_mcastgrp=mfc->mfcc_mcastgrp.s_addr;
 	c->mfc_parent=mfc->mfcc_parent;
-	ipmr_update_threshoulds(c, mfc->mfcc_ttls);
+	ipmr_update_thresholds(c, mfc->mfcc_ttls);
 	if (!mrtsock)
 		c->mfc_flags |= MFC_STATIC;
 
diff --git a/net/ipv4/netfilter/ip_conntrack_core.c b/net/ipv4/netfilter/ip_conntrack_core.c
index 63bf8826498..a7f0c821a9b 100644
--- a/net/ipv4/netfilter/ip_conntrack_core.c
+++ b/net/ipv4/netfilter/ip_conntrack_core.c
@@ -510,9 +510,14 @@ init_conntrack(const struct ip_conntrack_tuple *tuple,
 		/* Welcome, Mr. Bond.  We've been expecting you... */
 		__set_bit(IPS_EXPECTED_BIT, &conntrack->status);
 		conntrack->master = exp->master;
-#if CONFIG_IP_NF_CONNTRACK_MARK
+#ifdef CONFIG_IP_NF_CONNTRACK_MARK
 		conntrack->mark = exp->master->mark;
 #endif
+#if defined(CONFIG_IP_NF_TARGET_MASQUERADE) || \
+    defined(CONFIG_IP_NF_TARGET_MASQUERADE_MODULE)
+		/* this is ugly, but there is no other place where to put it */
+		conntrack->nat.masq_index = exp->master->nat.masq_index;
+#endif
 		nf_conntrack_get(&conntrack->master->ct_general);
 		CONNTRACK_STAT_INC(expect_new);
 	} else {
diff --git a/net/ipv4/netfilter/ip_nat_standalone.c b/net/ipv4/netfilter/ip_nat_standalone.c
index bc59d0d6e89..91d5ea1dbbc 100644
--- a/net/ipv4/netfilter/ip_nat_standalone.c
+++ b/net/ipv4/netfilter/ip_nat_standalone.c
@@ -102,6 +102,10 @@ ip_nat_fn(unsigned int hooknum,
 		return NF_ACCEPT;
 	}
 
+	/* Don't try to NAT if this packet is not conntracked */
+	if (ct == &ip_conntrack_untracked)
+		return NF_ACCEPT;
+
 	switch (ctinfo) {
 	case IP_CT_RELATED:
 	case IP_CT_RELATED+IP_CT_IS_REPLY:
diff --git a/net/ipv4/tcp_ipv4.c b/net/ipv4/tcp_ipv4.c
index 62f62bb05c2..5d91213d34c 100644
--- a/net/ipv4/tcp_ipv4.c
+++ b/net/ipv4/tcp_ipv4.c
@@ -1494,12 +1494,11 @@ int tcp_v4_conn_request(struct sock *sk, struct sk_buff *skb)
 			 * to destinations, already remembered
 			 * to the moment of synflood.
 			 */
-			NETDEBUG(if (net_ratelimit()) \
-					printk(KERN_DEBUG "TCP: drop open "
-							  "request from %u.%u."
-							  "%u.%u/%u\n", \
-					       NIPQUAD(saddr),
-					       ntohs(skb->h.th->source)));
+			LIMIT_NETDEBUG(printk(KERN_DEBUG "TCP: drop open "
+					      "request from %u.%u."
+					      "%u.%u/%u\n",
+					      NIPQUAD(saddr),
+					      ntohs(skb->h.th->source)));
 			dst_release(dst);
 			goto drop_and_free;
 		}
@@ -1627,8 +1626,7 @@ static int tcp_v4_checksum_init(struct sk_buff *skb)
 				  skb->nh.iph->daddr, skb->csum))
 			return 0;
 
-		NETDEBUG(if (net_ratelimit())
-				printk(KERN_DEBUG "hw tcp v4 csum failed\n"));
+		LIMIT_NETDEBUG(printk(KERN_DEBUG "hw tcp v4 csum failed\n"));
 		skb->ip_summed = CHECKSUM_NONE;
 	}
 	if (skb->len <= 76) {
diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c
index e3f8ea1bfa9..7d076f0db10 100644
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -403,11 +403,9 @@ static void tcp_queue_skb(struct sock *sk, struct sk_buff *skb)
 		sk->sk_send_head = skb;
 }
 
-static void tcp_set_skb_tso_segs(struct sock *sk, struct sk_buff *skb)
+static void tcp_set_skb_tso_segs(struct sock *sk, struct sk_buff *skb, unsigned int mss_now)
 {
-	struct tcp_sock *tp = tcp_sk(sk);
-
-	if (skb->len <= tp->mss_cache ||
+	if (skb->len <= mss_now ||
 	    !(sk->sk_route_caps & NETIF_F_TSO)) {
 		/* Avoid the costly divide in the normal
 		 * non-TSO case.
@@ -417,10 +415,10 @@ static void tcp_set_skb_tso_segs(struct sock *sk, struct sk_buff *skb)
 	} else {
 		unsigned int factor;
 
-		factor = skb->len + (tp->mss_cache - 1);
-		factor /= tp->mss_cache;
+		factor = skb->len + (mss_now - 1);
+		factor /= mss_now;
 		skb_shinfo(skb)->tso_segs = factor;
-		skb_shinfo(skb)->tso_size = tp->mss_cache;
+		skb_shinfo(skb)->tso_size = mss_now;
 	}
 }
 
@@ -429,7 +427,7 @@ static void tcp_set_skb_tso_segs(struct sock *sk, struct sk_buff *skb)
  * packet to the list.  This won't be called frequently, I hope. 
  * Remember, these are still headerless SKBs at this point.
  */
-static int tcp_fragment(struct sock *sk, struct sk_buff *skb, u32 len)
+static int tcp_fragment(struct sock *sk, struct sk_buff *skb, u32 len, unsigned int mss_now)
 {
 	struct tcp_sock *tp = tcp_sk(sk);
 	struct sk_buff *buff;
@@ -492,8 +490,8 @@ static int tcp_fragment(struct sock *sk, struct sk_buff *skb, u32 len)
 	}
 
 	/* Fix up tso_factor for both original and new SKB.  */
-	tcp_set_skb_tso_segs(sk, skb);
-	tcp_set_skb_tso_segs(sk, buff);
+	tcp_set_skb_tso_segs(sk, skb, mss_now);
+	tcp_set_skb_tso_segs(sk, buff, mss_now);
 
 	if (TCP_SKB_CB(skb)->sacked & TCPCB_LOST) {
 		tp->lost_out += tcp_skb_pcount(skb);
@@ -569,7 +567,7 @@ int tcp_trim_head(struct sock *sk, struct sk_buff *skb, u32 len)
 	 * factor and mss.
 	 */
 	if (tcp_skb_pcount(skb) > 1)
-		tcp_set_skb_tso_segs(sk, skb);
+		tcp_set_skb_tso_segs(sk, skb, tcp_current_mss(sk, 1));
 
 	return 0;
 }
@@ -734,12 +732,14 @@ static inline unsigned int tcp_cwnd_test(struct tcp_sock *tp, struct sk_buff *sk
 /* This must be invoked the first time we consider transmitting
  * SKB onto the wire.
  */
-static inline int tcp_init_tso_segs(struct sock *sk, struct sk_buff *skb)
+static inline int tcp_init_tso_segs(struct sock *sk, struct sk_buff *skb, unsigned int mss_now)
 {
 	int tso_segs = tcp_skb_pcount(skb);
 
-	if (!tso_segs) {
-		tcp_set_skb_tso_segs(sk, skb);
+	if (!tso_segs ||
+	    (tso_segs > 1 &&
+	     skb_shinfo(skb)->tso_size != mss_now)) {
+		tcp_set_skb_tso_segs(sk, skb, mss_now);
 		tso_segs = tcp_skb_pcount(skb);
 	}
 	return tso_segs;
@@ -817,7 +817,7 @@ static unsigned int tcp_snd_test(struct sock *sk, struct sk_buff *skb,
 	struct tcp_sock *tp = tcp_sk(sk);
 	unsigned int cwnd_quota;
 
-	tcp_init_tso_segs(sk, skb);
+	tcp_init_tso_segs(sk, skb, cur_mss);
 
 	if (!tcp_nagle_test(tp, skb, cur_mss, nonagle))
 		return 0;
@@ -854,7 +854,7 @@ int tcp_may_send_now(struct sock *sk, struct tcp_sock *tp)
  * know that all the data is in scatter-gather pages, and that the
  * packet has never been sent out before (and thus is not cloned).
  */
-static int tso_fragment(struct sock *sk, struct sk_buff *skb, unsigned int len)
+static int tso_fragment(struct sock *sk, struct sk_buff *skb, unsigned int len, unsigned int mss_now)
 {
 	struct sk_buff *buff;
 	int nlen = skb->len - len;
@@ -887,8 +887,8 @@ static int tso_fragment(struct sock *sk, struct sk_buff *skb, unsigned int len)
 	skb_split(skb, buff, len);
 
 	/* Fix up tso_factor for both original and new SKB.  */
-	tcp_set_skb_tso_segs(sk, skb);
-	tcp_set_skb_tso_segs(sk, buff);
+	tcp_set_skb_tso_segs(sk, skb, mss_now);
+	tcp_set_skb_tso_segs(sk, buff, mss_now);
 
 	/* Link BUFF into the send queue. */
 	skb_header_release(buff);
@@ -972,19 +972,18 @@ static int tcp_write_xmit(struct sock *sk, unsigned int mss_now, int nonagle)
 	if (unlikely(sk->sk_state == TCP_CLOSE))
 		return 0;
 
-	skb = sk->sk_send_head;
-	if (unlikely(!skb))
-		return 0;
-
-	tso_segs = tcp_init_tso_segs(sk, skb);
-	cwnd_quota = tcp_cwnd_test(tp, skb);
-	if (unlikely(!cwnd_quota))
-		goto out;
-
 	sent_pkts = 0;
-	while (likely(tcp_snd_wnd_test(tp, skb, mss_now))) {
+	while ((skb = sk->sk_send_head)) {
+		tso_segs = tcp_init_tso_segs(sk, skb, mss_now);
 		BUG_ON(!tso_segs);
 
+		cwnd_quota = tcp_cwnd_test(tp, skb);
+		if (!cwnd_quota)
+			break;
+
+		if (unlikely(!tcp_snd_wnd_test(tp, skb, mss_now)))
+			break;
+
 		if (tso_segs == 1) {
 			if (unlikely(!tcp_nagle_test(tp, skb, mss_now,
 						     (tcp_skb_is_last(sk, skb) ?
@@ -1006,11 +1005,11 @@ static int tcp_write_xmit(struct sock *sk, unsigned int mss_now, int nonagle)
 					limit = skb->len - trim;
 			}
 			if (skb->len > limit) {
-				if (tso_fragment(sk, skb, limit))
+				if (tso_fragment(sk, skb, limit, mss_now))
 					break;
 			}
 		} else if (unlikely(skb->len > mss_now)) {
-			if (unlikely(tcp_fragment(sk, skb,  mss_now)))
+			if (unlikely(tcp_fragment(sk, skb,  mss_now, mss_now)))
 				break;
 		}
 
@@ -1026,27 +1025,12 @@ static int tcp_write_xmit(struct sock *sk, unsigned int mss_now, int nonagle)
 
 		tcp_minshall_update(tp, mss_now, skb);
 		sent_pkts++;
-
-		/* Do not optimize this to use tso_segs. If we chopped up
-		 * the packet above, tso_segs will no longer be valid.
-		 */
-		cwnd_quota -= tcp_skb_pcount(skb);
-
-		BUG_ON(cwnd_quota < 0);
-		if (!cwnd_quota)
-			break;
-
-		skb = sk->sk_send_head;
-		if (!skb)
-			break;
-		tso_segs = tcp_init_tso_segs(sk, skb);
 	}
 
 	if (likely(sent_pkts)) {
 		tcp_cwnd_validate(sk, tp);
 		return 0;
 	}
-out:
 	return !tp->packets_out && sk->sk_send_head;
 }
 
@@ -1076,7 +1060,7 @@ void tcp_push_one(struct sock *sk, unsigned int mss_now)
 
 	BUG_ON(!skb || skb->len < mss_now);
 
-	tso_segs = tcp_init_tso_segs(sk, skb);
+	tso_segs = tcp_init_tso_segs(sk, skb, mss_now);
 	cwnd_quota = tcp_snd_test(sk, skb, mss_now, TCP_NAGLE_PUSH);
 
 	if (likely(cwnd_quota)) {
@@ -1093,11 +1077,11 @@ void tcp_push_one(struct sock *sk, unsigned int mss_now)
 					limit = skb->len - trim;
 			}
 			if (skb->len > limit) {
-				if (unlikely(tso_fragment(sk, skb, limit)))
+				if (unlikely(tso_fragment(sk, skb, limit, mss_now)))
 					return;
 			}
 		} else if (unlikely(skb->len > mss_now)) {
-			if (unlikely(tcp_fragment(sk, skb, mss_now)))
+			if (unlikely(tcp_fragment(sk, skb, mss_now, mss_now)))
 				return;
 		}
 
@@ -1388,7 +1372,7 @@ int tcp_retransmit_skb(struct sock *sk, struct sk_buff *skb)
 		int old_factor = tcp_skb_pcount(skb);
 		int new_factor;
 
-		if (tcp_fragment(sk, skb, cur_mss))
+		if (tcp_fragment(sk, skb, cur_mss, cur_mss))
 			return -ENOMEM; /* We'll try again later. */
 
 		/* New SKB created, account for it. */
@@ -1991,7 +1975,7 @@ int tcp_write_wakeup(struct sock *sk)
 			    skb->len > mss) {
 				seg_size = min(seg_size, mss);
 				TCP_SKB_CB(skb)->flags |= TCPCB_FLAG_PSH;
-				if (tcp_fragment(sk, skb, seg_size))
+				if (tcp_fragment(sk, skb, seg_size, mss))
 					return -1;
 				/* SWS override triggered forced fragmentation.
 				 * Disable TSO, the connection is too sick. */
@@ -2000,7 +1984,7 @@ int tcp_write_wakeup(struct sock *sk)
 					sk->sk_route_caps &= ~NETIF_F_TSO;
 				}
 			} else if (!tcp_skb_pcount(skb))
-				tcp_set_skb_tso_segs(sk, skb);
+				tcp_set_skb_tso_segs(sk, skb, mss);
 
 			TCP_SKB_CB(skb)->flags |= TCPCB_FLAG_PSH;
 			TCP_SKB_CB(skb)->when = tcp_time_stamp;
diff --git a/net/ipv4/udp.c b/net/ipv4/udp.c
index 7c24e64b443..dc4d07357e3 100644
--- a/net/ipv4/udp.c
+++ b/net/ipv4/udp.c
@@ -628,7 +628,7 @@ back_from_confirm:
 		/* ... which is an evident application bug. --ANK */
 		release_sock(sk);
 
-		NETDEBUG(if (net_ratelimit()) printk(KERN_DEBUG "udp cork app bug 2\n"));
+		LIMIT_NETDEBUG(printk(KERN_DEBUG "udp cork app bug 2\n"));
 		err = -EINVAL;
 		goto out;
 	}
@@ -693,7 +693,7 @@ static int udp_sendpage(struct sock *sk, struct page *page, int offset,
 	if (unlikely(!up->pending)) {
 		release_sock(sk);
 
-		NETDEBUG(if (net_ratelimit()) printk(KERN_DEBUG "udp cork app bug 3\n"));
+		LIMIT_NETDEBUG(printk(KERN_DEBUG "udp cork app bug 3\n"));
 		return -EINVAL;
 	}
 
@@ -1102,7 +1102,7 @@ static int udp_checksum_init(struct sk_buff *skb, struct udphdr *uh,
 		skb->ip_summed = CHECKSUM_UNNECESSARY;
 		if (!udp_check(uh, ulen, saddr, daddr, skb->csum))
 			return 0;
-		NETDEBUG(if (net_ratelimit()) printk(KERN_DEBUG "udp v4 hw csum failure.\n"));
+		LIMIT_NETDEBUG(printk(KERN_DEBUG "udp v4 hw csum failure.\n"));
 		skb->ip_summed = CHECKSUM_NONE;
 	}
 	if (skb->ip_summed != CHECKSUM_UNNECESSARY)
@@ -1181,14 +1181,13 @@ int udp_rcv(struct sk_buff *skb)
 	return(0);
 
 short_packet:
-	NETDEBUG(if (net_ratelimit())
-		printk(KERN_DEBUG "UDP: short packet: From %u.%u.%u.%u:%u %d/%d to %u.%u.%u.%u:%u\n",
-			NIPQUAD(saddr),
-			ntohs(uh->source),
-			ulen,
-			len,
-			NIPQUAD(daddr),
-			ntohs(uh->dest)));
+	LIMIT_NETDEBUG(printk(KERN_DEBUG "UDP: short packet: From %u.%u.%u.%u:%u %d/%d to %u.%u.%u.%u:%u\n",
+			      NIPQUAD(saddr),
+			      ntohs(uh->source),
+			      ulen,
+			      len,
+			      NIPQUAD(daddr),
+			      ntohs(uh->dest)));
 no_header:
 	UDP_INC_STATS_BH(UDP_MIB_INERRORS);
 	kfree_skb(skb);
@@ -1199,13 +1198,12 @@ csum_error:
 	 * RFC1122: OK.  Discards the bad packet silently (as far as 
 	 * the network is concerned, anyway) as per 4.1.3.4 (MUST). 
 	 */
-	NETDEBUG(if (net_ratelimit())
-		 printk(KERN_DEBUG "UDP: bad checksum. From %d.%d.%d.%d:%d to %d.%d.%d.%d:%d ulen %d\n",
-			NIPQUAD(saddr),
-			ntohs(uh->source),
-			NIPQUAD(daddr),
-			ntohs(uh->dest),
-			ulen));
+	LIMIT_NETDEBUG(printk(KERN_DEBUG "UDP: bad checksum. From %d.%d.%d.%d:%d to %d.%d.%d.%d:%d ulen %d\n",
+			      NIPQUAD(saddr),
+			      ntohs(uh->source),
+			      NIPQUAD(daddr),
+			      ntohs(uh->dest),
+			      ulen));
 drop:
 	UDP_INC_STATS_BH(UDP_MIB_INERRORS);
 	kfree_skb(skb);
diff --git a/net/ipv4/utils.c b/net/ipv4/utils.c
deleted file mode 100644
index 6aecd7a4353..00000000000
--- a/net/ipv4/utils.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * INET		An implementation of the TCP/IP protocol suite for the LINUX
- *		operating system.  INET is implemented using the  BSD Socket
- *		interface as the means of communication with the user level.
- *
- *		Various kernel-resident INET utility functions; mainly
- *		for format conversion and debugging output.
- *
- * Version:	$Id: utils.c,v 1.8 2000/10/03 07:29:01 anton Exp $
- *
- * Author:	Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
- *
- * Fixes:
- *		Alan Cox	:	verify_area check.
- *		Alan Cox	:	removed old debugging.
- *		Andi Kleen	:	add net_ratelimit()  
- *
- *		This program is free software; you can redistribute it and/or
- *		modify it under the terms of the GNU General Public License
- *		as published by the Free Software Foundation; either version
- *		2 of the License, or (at your option) any later version.
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <asm/byteorder.h>
-
-/*
- *	Convert an ASCII string to binary IP. 
- */
- 
-__u32 in_aton(const char *str)
-{
-	unsigned long l;
-	unsigned int val;
-	int i;
-
-	l = 0;
-	for (i = 0; i < 4; i++) 
-	{
-		l <<= 8;
-		if (*str != '\0') 
-		{
-			val = 0;
-			while (*str != '\0' && *str != '.') 
-			{
-				val *= 10;
-				val += *str - '0';
-				str++;
-			}
-			l |= val;
-			if (*str != '\0') 
-				str++;
-		}
-	}
-	return(htonl(l));
-}
-
-EXPORT_SYMBOL(in_aton);
diff --git a/net/ipv6/ip6_output.c b/net/ipv6/ip6_output.c
index 1f2c2f9e353..ae652ca14bc 100644
--- a/net/ipv6/ip6_output.c
+++ b/net/ipv6/ip6_output.c
@@ -792,13 +792,8 @@ int ip6_dst_lookup(struct sock *sk, struct dst_entry **dst, struct flowi *fl)
 	if (ipv6_addr_any(&fl->fl6_src)) {
 		err = ipv6_get_saddr(*dst, &fl->fl6_dst, &fl->fl6_src);
 
-		if (err) {
-#if IP6_DEBUG >= 2
-			printk(KERN_DEBUG "ip6_dst_lookup: "
-			       "no available source address\n");
-#endif
+		if (err)
 			goto out_err_release;
-		}
 	}
 
 	return 0;
diff --git a/net/ipv6/ipv6_sockglue.c b/net/ipv6/ipv6_sockglue.c
index f3ef4c38d31..3bc144a79fa 100644
--- a/net/ipv6/ipv6_sockglue.c
+++ b/net/ipv6/ipv6_sockglue.c
@@ -504,6 +504,9 @@ done:
 		break;
 	case IPV6_IPSEC_POLICY:
 	case IPV6_XFRM_POLICY:
+		retv = -EPERM;
+		if (!capable(CAP_NET_ADMIN))
+			break;
 		retv = xfrm_user_policy(sk, optname, optval, optlen);
 		break;
 
diff --git a/net/ipv6/sit.c b/net/ipv6/sit.c
index b788f55e139..e553e5b80d6 100644
--- a/net/ipv6/sit.c
+++ b/net/ipv6/sit.c
@@ -195,7 +195,6 @@ static struct ip_tunnel * ipip6_tunnel_locate(struct ip_tunnel_parm *parms, int
 	dev_hold(dev);
 
 	ipip6_tunnel_link(nt);
-	/* Do not decrement MOD_USE_COUNT here. */
 	return nt;
 
 failed:
@@ -794,10 +793,28 @@ static struct net_protocol sit_protocol = {
 	.err_handler	=	ipip6_err,
 };
 
+static void __exit sit_destroy_tunnels(void)
+{
+	int prio;
+
+	for (prio = 1; prio < 4; prio++) {
+		int h;
+		for (h = 0; h < HASH_SIZE; h++) {
+			struct ip_tunnel *t;
+			while ((t = tunnels[prio][h]) != NULL)
+				unregister_netdevice(t->dev);
+		}
+	}
+}
+
 void __exit sit_cleanup(void)
 {
 	inet_del_protocol(&sit_protocol, IPPROTO_IPV6);
-	unregister_netdev(ipip6_fb_tunnel_dev);
+
+	rtnl_lock();
+	sit_destroy_tunnels();
+	unregister_netdevice(ipip6_fb_tunnel_dev);
+	rtnl_unlock();
 }
 
 int __init sit_init(void)
diff --git a/scripts/kconfig/gconf.c b/scripts/kconfig/gconf.c
index ad6b1204387..9f5aabd58fa 100644
--- a/scripts/kconfig/gconf.c
+++ b/scripts/kconfig/gconf.c
@@ -178,17 +178,31 @@ const char *dbg_print_ptype(int val)
 }
 
 
-/* Main Window Initialization */
+void replace_button_icon(GladeXML * xml, GdkDrawable * window,
+			 GtkStyle * style, gchar * btn_name, gchar ** xpm)
+{
+	GdkPixmap *pixmap;
+	GdkBitmap *mask;
+	GtkToolButton *button;
+	GtkWidget *image;
 
+	pixmap = gdk_pixmap_create_from_xpm_d(window, &mask,
+					      &style->bg[GTK_STATE_NORMAL],
+					      xpm);
+
+	button = GTK_TOOL_BUTTON(glade_xml_get_widget(xml, btn_name));
+	image = gtk_image_new_from_pixmap(pixmap, mask);
+	gtk_widget_show(image);
+	gtk_tool_button_set_icon_widget(button, image);
+}
 
+/* Main Window Initialization */
 void init_main_window(const gchar * glade_file)
 {
 	GladeXML *xml;
 	GtkWidget *widget;
 	GtkTextBuffer *txtbuf;
 	char title[256];
-	GdkPixmap *pixmap;
-	GdkBitmap *mask;
 	GtkStyle *style;
 
 	xml = glade_xml_new(glade_file, "window1", NULL);
@@ -221,36 +235,22 @@ void init_main_window(const gchar * glade_file)
 	style = gtk_widget_get_style(main_wnd);
 	widget = glade_xml_get_widget(xml, "toolbar1");
 
-	pixmap = gdk_pixmap_create_from_xpm_d(main_wnd->window, &mask,
-					      &style->bg[GTK_STATE_NORMAL],
-					      (gchar **) xpm_single_view);
-	gtk_image_set_from_pixmap(GTK_IMAGE
-				  (((GtkToolbarChild
-				     *) (g_list_nth(GTK_TOOLBAR(widget)->
-						    children,
-						    5)->data))->icon),
-				  pixmap, mask);
-	pixmap =
-	    gdk_pixmap_create_from_xpm_d(main_wnd->window, &mask,
-					 &style->bg[GTK_STATE_NORMAL],
-					 (gchar **) xpm_split_view);
-	gtk_image_set_from_pixmap(GTK_IMAGE
-				  (((GtkToolbarChild
-				     *) (g_list_nth(GTK_TOOLBAR(widget)->
-						    children,
-						    6)->data))->icon),
-				  pixmap, mask);
-	pixmap =
-	    gdk_pixmap_create_from_xpm_d(main_wnd->window, &mask,
-					 &style->bg[GTK_STATE_NORMAL],
-					 (gchar **) xpm_tree_view);
-	gtk_image_set_from_pixmap(GTK_IMAGE
-				  (((GtkToolbarChild
-				     *) (g_list_nth(GTK_TOOLBAR(widget)->
-						    children,
-						    7)->data))->icon),
-				  pixmap, mask);
-
+#if 0	/* Use stock Gtk icons instead */
+	replace_button_icon(xml, main_wnd->window, style,
+			    "button1", (gchar **) xpm_back);
+	replace_button_icon(xml, main_wnd->window, style,
+			    "button2", (gchar **) xpm_load);
+	replace_button_icon(xml, main_wnd->window, style,
+			    "button3", (gchar **) xpm_save);
+#endif
+	replace_button_icon(xml, main_wnd->window, style,
+			    "button4", (gchar **) xpm_single_view);
+	replace_button_icon(xml, main_wnd->window, style,
+			    "button5", (gchar **) xpm_split_view);
+	replace_button_icon(xml, main_wnd->window, style,
+			    "button6", (gchar **) xpm_tree_view);
+
+#if 0
 	switch (view_mode) {
 	case SINGLE_VIEW:
 		widget = glade_xml_get_widget(xml, "button4");
@@ -265,7 +265,7 @@ void init_main_window(const gchar * glade_file)
 		g_signal_emit_by_name(widget, "clicked");
 		break;
 	}
-
+#endif
 	txtbuf = gtk_text_view_get_buffer(GTK_TEXT_VIEW(text_w));
 	tag1 = gtk_text_buffer_create_tag(txtbuf, "mytag1",
 					  "foreground", "red",
@@ -322,7 +322,7 @@ void init_left_tree(void)
 	gtk_tree_view_set_model(view, model1);
 	gtk_tree_view_set_headers_visible(view, TRUE);
 	gtk_tree_view_set_rules_hint(view, FALSE);
-	
+
 	column = gtk_tree_view_column_new();
 	gtk_tree_view_append_column(view, column);
 	gtk_tree_view_column_set_title(column, _("Options"));
@@ -334,11 +334,11 @@ void init_left_tree(void)
 					    renderer,
 					    "active", COL_BTNACT,
 					    "inconsistent", COL_BTNINC,
-					    "visible", COL_BTNVIS, 
+					    "visible", COL_BTNVIS,
 					    "radio", COL_BTNRAD, NULL);
 	renderer = gtk_cell_renderer_text_new();
 	gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column),
-					renderer, FALSE);	
+					renderer, FALSE);
 	gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column),
 					    renderer,
 					    "text", COL_OPTION,
@@ -386,7 +386,7 @@ void init_right_tree(void)
 					    renderer,
 					    "active", COL_BTNACT,
 					    "inconsistent", COL_BTNINC,
-					    "visible", COL_BTNVIS, 
+					    "visible", COL_BTNVIS,
 					    "radio", COL_BTNRAD, NULL);
 	/*g_signal_connect(G_OBJECT(renderer), "toggled",
 	   G_CALLBACK(renderer_toggled), NULL); */
@@ -806,7 +806,7 @@ void on_license1_activate(GtkMenuItem * menuitem, gpointer user_data)
 }
 
 
-void on_back_pressed(GtkButton * button, gpointer user_data)
+void on_back_clicked(GtkButton * button, gpointer user_data)
 {
 	enum prop_type ptype;
 
@@ -821,13 +821,13 @@ void on_back_pressed(GtkButton * button, gpointer user_data)
 }
 
 
-void on_load_pressed(GtkButton * button, gpointer user_data)
+void on_load_clicked(GtkButton * button, gpointer user_data)
 {
 	on_load1_activate(NULL, user_data);
 }
 
 
-void on_save_pressed(GtkButton * button, gpointer user_data)
+void on_save_clicked(GtkButton * button, gpointer user_data)
 {
 	on_save1_activate(NULL, user_data);
 }
@@ -850,9 +850,12 @@ void on_split_clicked(GtkButton * button, gpointer user_data)
 	gtk_widget_show(tree1_w);
 	gtk_window_get_default_size(GTK_WINDOW(main_wnd), &w, &h);
 	gtk_paned_set_position(GTK_PANED(hpaned), w / 2);
-	if (tree2)	
+	if (tree2)
 		gtk_tree_store_clear(tree2);
 	display_list();
+
+	/* Disable back btn, like in full mode. */
+	gtk_widget_set_sensitive(back_btn, FALSE);
 }
 
 
@@ -868,13 +871,13 @@ void on_full_clicked(GtkButton * button, gpointer user_data)
 }
 
 
-void on_collapse_pressed(GtkButton * button, gpointer user_data)
+void on_collapse_clicked(GtkButton * button, gpointer user_data)
 {
 	gtk_tree_view_collapse_all(GTK_TREE_VIEW(tree2_w));
 }
 
 
-void on_expand_pressed(GtkButton * button, gpointer user_data)
+void on_expand_clicked(GtkButton * button, gpointer user_data)
 {
 	gtk_tree_view_expand_all(GTK_TREE_VIEW(tree2_w));
 }
@@ -1242,13 +1245,13 @@ static gchar **fill_row(struct menu *menu)
 			row[COL_VALUE] =
 			    g_strdup(menu_get_prompt(def_menu));
 	}
-	if(sym->flags & SYMBOL_CHOICEVAL)
+	if (sym->flags & SYMBOL_CHOICEVAL)
 		row[COL_BTNRAD] = GINT_TO_POINTER(TRUE);
 
 	stype = sym_get_type(sym);
 	switch (stype) {
 	case S_BOOLEAN:
-		if(GPOINTER_TO_INT(row[COL_PIXVIS]) == FALSE)
+		if (GPOINTER_TO_INT(row[COL_PIXVIS]) == FALSE)
 			row[COL_BTNVIS] = GINT_TO_POINTER(TRUE);
 		if (sym_is_choice(sym))
 			break;
@@ -1423,7 +1426,7 @@ static void update_tree(struct menu *src, GtkTreeIter * dst)
 								 child2);
 				gtk_tree_store_remove(tree2, &tmp);
 				if (!valid)
-					return;	// next parent 
+					return;	// next parent
 				else
 					goto reparse;	// next child
 			} else
@@ -1448,7 +1451,7 @@ static void update_tree(struct menu *src, GtkTreeIter * dst)
 								 child2);
 				gtk_tree_store_remove(tree2, &tmp);
 				if (!valid)
-					return;	// next parent 
+					return;	// next parent
 				else
 					goto reparse;	// next child
 			}
@@ -1486,12 +1489,12 @@ static void display_tree(struct menu *menu)
 		if (sym)
 			sym->flags &= ~SYMBOL_CHANGED;
 
-		if ((view_mode == SPLIT_VIEW) && !(child->flags & MENU_ROOT) &&
-		    (tree == tree1))
+		if ((view_mode == SPLIT_VIEW)
+		    && !(child->flags & MENU_ROOT) && (tree == tree1))
 			continue;
 
-		if ((view_mode == SPLIT_VIEW) && (child->flags & MENU_ROOT) &&
-		    (tree == tree2))
+		if ((view_mode == SPLIT_VIEW) && (child->flags & MENU_ROOT)
+		    && (tree == tree2))
 			continue;
 
 		if (menu_is_visible(child) || show_all)
@@ -1513,11 +1516,12 @@ static void display_tree(struct menu *menu)
 		    && (tree == tree2))
 			continue;
 /*
-		if (((menu != &rootmenu) && !(menu->flags & MENU_ROOT)) ||
-		    (view_mode == FULL_VIEW)
+                if (((menu != &rootmenu) && !(menu->flags & MENU_ROOT))
+		    || (view_mode == FULL_VIEW)
 		    || (view_mode == SPLIT_VIEW))*/
 		if (((view_mode == SINGLE_VIEW) && (menu->flags & MENU_ROOT))
-		    || (view_mode == FULL_VIEW) || (view_mode == SPLIT_VIEW)) {
+		    || (view_mode == FULL_VIEW)
+		    || (view_mode == SPLIT_VIEW)) {
 			indent++;
 			display_tree(child);
 			indent--;
@@ -1530,9 +1534,9 @@ static void display_tree_part(void)
 {
 	if (tree2)
 		gtk_tree_store_clear(tree2);
-	if(view_mode == SINGLE_VIEW)
+	if (view_mode == SINGLE_VIEW)
 		display_tree(current);
- 	else if(view_mode == SPLIT_VIEW)
+	else if (view_mode == SPLIT_VIEW)
 		display_tree(browsed);
 	gtk_tree_view_expand_all(GTK_TREE_VIEW(tree2_w));
 }
@@ -1551,24 +1555,22 @@ static void display_list(void)
 
 void fixup_rootmenu(struct menu *menu)
 {
-        struct menu *child;
-        static int menu_cnt = 0;
-
-        menu->flags |= MENU_ROOT;
-        for (child = menu->list; child; child = child->next) {
-                if (child->prompt && child->prompt->type == P_MENU) {
-                        menu_cnt++;
-                        fixup_rootmenu(child);
-                        menu_cnt--;
-                } else if (!menu_cnt)
-                        fixup_rootmenu(child);
-        }
+	struct menu *child;
+	static int menu_cnt = 0;
+
+	menu->flags |= MENU_ROOT;
+	for (child = menu->list; child; child = child->next) {
+		if (child->prompt && child->prompt->type == P_MENU) {
+			menu_cnt++;
+			fixup_rootmenu(child);
+			menu_cnt--;
+		} else if (!menu_cnt)
+			fixup_rootmenu(child);
+	}
 }
 
 
 /* Main */
-
-
 int main(int ac, char *av[])
 {
 	const char *name;
diff --git a/scripts/kconfig/gconf.glade b/scripts/kconfig/gconf.glade
index ace4706ab25..f8744ed6496 100644
--- a/scripts/kconfig/gconf.glade
+++ b/scripts/kconfig/gconf.glade
@@ -13,6 +13,11 @@
   <property name="default_height">480</property>
   <property name="resizable">True</property>
   <property name="destroy_with_parent">False</property>
+  <property name="decorated">True</property>
+  <property name="skip_taskbar_hint">False</property>
+  <property name="skip_pager_hint">False</property>
+  <property name="type_hint">GDK_WINDOW_TYPE_HINT_NORMAL</property>
+  <property name="gravity">GDK_GRAVITY_NORTH_WEST</property>
   <signal name="destroy" handler="on_window1_destroy" object="window1"/>
   <signal name="size_request" handler="on_window1_size_request" object="vpaned1" last_modification_time="Fri, 11 Jan 2002 16:17:11 GMT"/>
   <signal name="delete_event" handler="on_window1_delete_event" object="window1" last_modification_time="Sun, 09 Mar 2003 19:42:46 GMT"/>
@@ -46,7 +51,7 @@
 		      <accelerator key="L" modifiers="GDK_CONTROL_MASK" signal="activate"/>
 
 		      <child internal-child="image">
-			<widget class="GtkImage" id="image27">
+			<widget class="GtkImage" id="image39">
 			  <property name="visible">True</property>
 			  <property name="stock">gtk-open</property>
 			  <property name="icon_size">1</property>
@@ -69,7 +74,7 @@
 		      <accelerator key="S" modifiers="GDK_CONTROL_MASK" signal="activate"/>
 
 		      <child internal-child="image">
-			<widget class="GtkImage" id="image28">
+			<widget class="GtkImage" id="image40">
 			  <property name="visible">True</property>
 			  <property name="stock">gtk-save</property>
 			  <property name="icon_size">1</property>
@@ -91,7 +96,7 @@
 		      <signal name="activate" handler="on_save_as1_activate"/>
 
 		      <child internal-child="image">
-			<widget class="GtkImage" id="image29">
+			<widget class="GtkImage" id="image41">
 			  <property name="visible">True</property>
 			  <property name="stock">gtk-save-as</property>
 			  <property name="icon_size">1</property>
@@ -105,7 +110,7 @@
 		  </child>
 
 		  <child>
-		    <widget class="GtkMenuItem" id="separator1">
+		    <widget class="GtkSeparatorMenuItem" id="separator1">
 		      <property name="visible">True</property>
 		    </widget>
 		  </child>
@@ -119,7 +124,7 @@
 		      <accelerator key="Q" modifiers="GDK_CONTROL_MASK" signal="activate"/>
 
 		      <child internal-child="image">
-			<widget class="GtkImage" id="image30">
+			<widget class="GtkImage" id="image42">
 			  <property name="visible">True</property>
 			  <property name="stock">gtk-quit</property>
 			  <property name="icon_size">1</property>
@@ -179,7 +184,7 @@
 		  </child>
 
 		  <child>
-		    <widget class="GtkMenuItem" id="separator2">
+		    <widget class="GtkSeparatorMenuItem" id="separator2">
 		      <property name="visible">True</property>
 		    </widget>
 		  </child>
@@ -228,7 +233,7 @@
 		      <accelerator key="I" modifiers="GDK_CONTROL_MASK" signal="activate"/>
 
 		      <child internal-child="image">
-			<widget class="GtkImage" id="image31">
+			<widget class="GtkImage" id="image43">
 			  <property name="visible">True</property>
 			  <property name="stock">gtk-dialog-question</property>
 			  <property name="icon_size">1</property>
@@ -250,7 +255,7 @@
 		      <accelerator key="A" modifiers="GDK_CONTROL_MASK" signal="activate"/>
 
 		      <child internal-child="image">
-			<widget class="GtkImage" id="image32">
+			<widget class="GtkImage" id="image44">
 			  <property name="visible">True</property>
 			  <property name="stock">gtk-properties</property>
 			  <property name="icon_size">1</property>
@@ -271,7 +276,7 @@
 		      <signal name="activate" handler="on_license1_activate" last_modification_time="Fri, 15 Nov 2002 20:26:30 GMT"/>
 
 		      <child internal-child="image">
-			<widget class="GtkImage" id="image33">
+			<widget class="GtkImage" id="image45">
 			  <property name="visible">True</property>
 			  <property name="stock">gtk-justify-fill</property>
 			  <property name="icon_size">1</property>
@@ -308,109 +313,207 @@
 	      <property name="orientation">GTK_ORIENTATION_HORIZONTAL</property>
 	      <property name="toolbar_style">GTK_TOOLBAR_BOTH</property>
 	      <property name="tooltips">True</property>
+	      <property name="show_arrow">True</property>
 
 	      <child>
-		<widget class="button" id="button1">
+		<widget class="GtkToolButton" id="button1">
 		  <property name="visible">True</property>
 		  <property name="tooltip" translatable="yes">Goes up of one level (single view)</property>
 		  <property name="label" translatable="yes">Back</property>
 		  <property name="use_underline">True</property>
-		  <property name="stock_pixmap">gtk-undo</property>
-		  <signal name="pressed" handler="on_back_pressed"/>
+		  <property name="stock_id">gtk-undo</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
+		  <signal name="clicked" handler="on_back_clicked"/>
 		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">True</property>
+		</packing>
 	      </child>
 
 	      <child>
-		<widget class="GtkVSeparator" id="vseparator1">
+		<widget class="GtkToolItem" id="toolitem1">
 		  <property name="visible">True</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
+
+		  <child>
+		    <widget class="GtkVSeparator" id="vseparator1">
+		      <property name="visible">True</property>
+		    </widget>
+		  </child>
 		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">False</property>
+		</packing>
 	      </child>
 
 	      <child>
-		<widget class="button" id="button2">
+		<widget class="GtkToolButton" id="button2">
 		  <property name="visible">True</property>
 		  <property name="tooltip" translatable="yes">Load a config file</property>
 		  <property name="label" translatable="yes">Load</property>
 		  <property name="use_underline">True</property>
-		  <property name="stock_pixmap">gtk-open</property>
-		  <signal name="pressed" handler="on_load_pressed"/>
+		  <property name="stock_id">gtk-open</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
+		  <signal name="clicked" handler="on_load_clicked"/>
 		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">True</property>
+		</packing>
 	      </child>
 
 	      <child>
-		<widget class="button" id="button3">
+		<widget class="GtkToolButton" id="button3">
 		  <property name="visible">True</property>
 		  <property name="tooltip" translatable="yes">Save a config file</property>
 		  <property name="label" translatable="yes">Save</property>
 		  <property name="use_underline">True</property>
-		  <property name="stock_pixmap">gtk-save</property>
-		  <signal name="pressed" handler="on_save_pressed"/>
+		  <property name="stock_id">gtk-save</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
+		  <signal name="clicked" handler="on_save_clicked"/>
 		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">True</property>
+		</packing>
 	      </child>
 
 	      <child>
-		<widget class="GtkVSeparator" id="vseparator2">
+		<widget class="GtkToolItem" id="toolitem2">
 		  <property name="visible">True</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
+
+		  <child>
+		    <widget class="GtkVSeparator" id="vseparator2">
+		      <property name="visible">True</property>
+		    </widget>
+		  </child>
 		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">False</property>
+		</packing>
 	      </child>
 
 	      <child>
-		<widget class="button" id="button4">
+		<widget class="GtkToolButton" id="button4">
 		  <property name="visible">True</property>
 		  <property name="tooltip" translatable="yes">Single view</property>
 		  <property name="label" translatable="yes">Single</property>
 		  <property name="use_underline">True</property>
-		  <property name="stock_pixmap">gtk-missing-image</property>
+		  <property name="stock_id">gtk-missing-image</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
 		  <signal name="clicked" handler="on_single_clicked" last_modification_time="Sun, 12 Jan 2003 14:28:39 GMT"/>
 		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">True</property>
+		</packing>
 	      </child>
 
 	      <child>
-		<widget class="button" id="button5">
+		<widget class="GtkToolButton" id="button5">
 		  <property name="visible">True</property>
 		  <property name="tooltip" translatable="yes">Split view</property>
 		  <property name="label" translatable="yes">Split</property>
 		  <property name="use_underline">True</property>
-		  <property name="stock_pixmap">gtk-missing-image</property>
+		  <property name="stock_id">gtk-missing-image</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
 		  <signal name="clicked" handler="on_split_clicked" last_modification_time="Sun, 12 Jan 2003 14:28:45 GMT"/>
 		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">True</property>
+		</packing>
 	      </child>
 
 	      <child>
-		<widget class="button" id="button6">
+		<widget class="GtkToolButton" id="button6">
 		  <property name="visible">True</property>
 		  <property name="tooltip" translatable="yes">Full view</property>
 		  <property name="label" translatable="yes">Full</property>
 		  <property name="use_underline">True</property>
-		  <property name="stock_pixmap">gtk-missing-image</property>
+		  <property name="stock_id">gtk-missing-image</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
 		  <signal name="clicked" handler="on_full_clicked" last_modification_time="Sun, 12 Jan 2003 14:28:50 GMT"/>
 		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">True</property>
+		</packing>
 	      </child>
 
 	      <child>
-		<widget class="GtkVSeparator" id="vseparator3">
+		<widget class="GtkToolItem" id="toolitem3">
 		  <property name="visible">True</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
+
+		  <child>
+		    <widget class="GtkVSeparator" id="vseparator3">
+		      <property name="visible">True</property>
+		    </widget>
+		  </child>
 		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">False</property>
+		</packing>
 	      </child>
 
 	      <child>
-		<widget class="button" id="button7">
+		<widget class="GtkToolButton" id="button7">
 		  <property name="visible">True</property>
 		  <property name="tooltip" translatable="yes">Collapse the whole tree in the right frame</property>
 		  <property name="label" translatable="yes">Collapse</property>
 		  <property name="use_underline">True</property>
-		  <signal name="pressed" handler="on_collapse_pressed"/>
+		  <property name="stock_id">gtk-remove</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
+		  <signal name="clicked" handler="on_collapse_clicked"/>
 		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">True</property>
+		</packing>
 	      </child>
 
 	      <child>
-		<widget class="button" id="button8">
+		<widget class="GtkToolButton" id="button8">
 		  <property name="visible">True</property>
 		  <property name="tooltip" translatable="yes">Expand the whole tree in the right frame</property>
 		  <property name="label" translatable="yes">Expand</property>
 		  <property name="use_underline">True</property>
-		  <signal name="pressed" handler="on_expand_pressed"/>
+		  <property name="stock_id">gtk-add</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
+		  <signal name="clicked" handler="on_expand_clicked"/>
 		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">True</property>
+		</packing>
 	      </child>
 	    </widget>
 	  </child>
@@ -505,6 +608,8 @@
 		      <property name="visible">True</property>
 		      <property name="can_focus">True</property>
 		      <property name="editable">False</property>
+		      <property name="overwrite">False</property>
+		      <property name="accepts_tab">True</property>
 		      <property name="justification">GTK_JUSTIFY_LEFT</property>
 		      <property name="wrap_mode">GTK_WRAP_WORD</property>
 		      <property name="cursor_visible">True</property>
diff --git a/security/keys/keyctl.c b/security/keys/keyctl.c
index fea262860ea..a6516a64b29 100644
--- a/security/keys/keyctl.c
+++ b/security/keys/keyctl.c
@@ -49,9 +49,6 @@ asmlinkage long sys_add_key(const char __user *_type,
 		goto error;
 	type[31] = '\0';
 
-	if (!type[0])
-		goto error;
-
 	ret = -EPERM;
 	if (type[0] == '.')
 		goto error;
@@ -144,6 +141,10 @@ asmlinkage long sys_request_key(const char __user *_type,
 		goto error;
 	type[31] = '\0';
 
+	ret = -EPERM;
+	if (type[0] == '.')
+		goto error;
+
 	/* pull the description into kernel space */
 	ret = -EFAULT;
 	dlen = strnlen_user(_description, PAGE_SIZE - 1);
@@ -362,7 +363,7 @@ long keyctl_revoke_key(key_serial_t id)
 
 	key_put(key);
  error:
-	return 0;
+	return ret;
 
 } /* end keyctl_revoke_key() */
 
@@ -685,6 +686,8 @@ long keyctl_read_key(key_serial_t keyid, char __user *buffer, size_t buflen)
 			goto can_read_key2;
 
 		ret = PTR_ERR(skey);
+		if (ret == -EAGAIN)
+			ret = -EACCES;
 		goto error2;
 	}
 
diff --git a/security/keys/keyring.c b/security/keys/keyring.c
index a1f6bac647a..9c208c756df 100644
--- a/security/keys/keyring.c
+++ b/security/keys/keyring.c
@@ -201,7 +201,11 @@ static void keyring_destroy(struct key *keyring)
 
 	if (keyring->description) {
 		write_lock(&keyring_name_lock);
-		list_del(&keyring->type_data.link);
+
+		if (keyring->type_data.link.next != NULL &&
+		    !list_empty(&keyring->type_data.link))
+			list_del(&keyring->type_data.link);
+
 		write_unlock(&keyring_name_lock);
 	}
 
diff --git a/security/keys/process_keys.c b/security/keys/process_keys.c
index 9b0369c5a22..c089f78fb94 100644
--- a/security/keys/process_keys.c
+++ b/security/keys/process_keys.c
@@ -678,7 +678,7 @@ long join_session_keyring(const char *name)
 		keyring = keyring_alloc(name, tsk->uid, tsk->gid, 0, NULL);
 		if (IS_ERR(keyring)) {
 			ret = PTR_ERR(keyring);
-			goto error;
+			goto error2;
 		}
 	}
 	else if (IS_ERR(keyring)) {
diff --git a/security/keys/request_key.c b/security/keys/request_key.c
index dfcd983af1f..90c1506d007 100644
--- a/security/keys/request_key.c
+++ b/security/keys/request_key.c
@@ -405,7 +405,7 @@ struct key *request_key_and_link(struct key_type *type,
 		key_user_put(user);
 
 		/* link the new key into the appropriate keyring */
-		if (!PTR_ERR(key))
+		if (!IS_ERR(key))
 			request_key_link(key, dest_keyring);
 	}
 
diff --git a/security/selinux/hooks.c b/security/selinux/hooks.c
index 5e755a3f4ca..9f946300068 100644
--- a/security/selinux/hooks.c
+++ b/security/selinux/hooks.c
@@ -826,7 +826,8 @@ static int inode_doinit_with_dentry(struct inode *inode, struct dentry *opt_dent
 			sid = sbsec->def_sid;
 			rc = 0;
 		} else {
-			rc = security_context_to_sid(context, rc, &sid);
+			rc = security_context_to_sid_default(context, rc, &sid,
+			                                     sbsec->def_sid);
 			if (rc) {
 				printk(KERN_WARNING "%s:  context_to_sid(%s) "
 				       "returned %d for dev=%s ino=%ld\n",
@@ -3125,12 +3126,12 @@ static int selinux_socket_connect(struct socket *sock, struct sockaddr *address,
 
 		if (sk->sk_family == PF_INET) {
 			addr4 = (struct sockaddr_in *)address;
-			if (addrlen != sizeof(struct sockaddr_in))
+			if (addrlen < sizeof(struct sockaddr_in))
 				return -EINVAL;
 			snum = ntohs(addr4->sin_port);
 		} else {
 			addr6 = (struct sockaddr_in6 *)address;
-			if (addrlen != sizeof(struct sockaddr_in6))
+			if (addrlen < SIN6_LEN_RFC2133)
 				return -EINVAL;
 			snum = ntohs(addr6->sin6_port);
 		}
diff --git a/security/selinux/include/security.h b/security/selinux/include/security.h
index fa187c9a351..71c0a19c975 100644
--- a/security/selinux/include/security.h
+++ b/security/selinux/include/security.h
@@ -65,6 +65,8 @@ int security_sid_to_context(u32 sid, char **scontext,
 int security_context_to_sid(char *scontext, u32 scontext_len,
 	u32 *out_sid);
 
+int security_context_to_sid_default(char *scontext, u32 scontext_len, u32 *out_sid, u32 def_sid);
+
 int security_get_user_sids(u32 callsid, char *username,
 			   u32 **sids, u32 *nel);
 
diff --git a/security/selinux/ss/mls.c b/security/selinux/ss/mls.c
index 756036bcc24..d4c32c39ccc 100644
--- a/security/selinux/ss/mls.c
+++ b/security/selinux/ss/mls.c
@@ -15,6 +15,7 @@
 #include <linux/slab.h>
 #include <linux/string.h>
 #include <linux/errno.h>
+#include "sidtab.h"
 #include "mls.h"
 #include "policydb.h"
 #include "services.h"
@@ -208,6 +209,26 @@ int mls_context_isvalid(struct policydb *p, struct context *c)
 }
 
 /*
+ * Copies the MLS range from `src' into `dst'.
+ */
+static inline int mls_copy_context(struct context *dst,
+				   struct context *src)
+{
+	int l, rc = 0;
+
+	/* Copy the MLS range from the source context */
+	for (l = 0; l < 2; l++) {
+		dst->range.level[l].sens = src->range.level[l].sens;
+		rc = ebitmap_cpy(&dst->range.level[l].cat,
+				 &src->range.level[l].cat);
+		if (rc)
+			break;
+	}
+
+	return rc;
+}
+
+/*
  * Set the MLS fields in the security context structure
  * `context' based on the string representation in
  * the string `*scontext'.  Update `*scontext' to
@@ -216,10 +237,20 @@ int mls_context_isvalid(struct policydb *p, struct context *c)
  *
  * This function modifies the string in place, inserting
  * NULL characters to terminate the MLS fields.
+ *
+ * If a def_sid is provided and no MLS field is present,
+ * copy the MLS field of the associated default context.
+ * Used for upgraded to MLS systems where objects may lack
+ * MLS fields.
+ *
+ * Policy read-lock must be held for sidtab lookup.
+ *
  */
 int mls_context_to_sid(char oldc,
 		       char **scontext,
-		       struct context *context)
+		       struct context *context,
+		       struct sidtab *s,
+		       u32 def_sid)
 {
 
 	char delim;
@@ -231,9 +262,23 @@ int mls_context_to_sid(char oldc,
 	if (!selinux_mls_enabled)
 		return 0;
 
-	/* No MLS component to the security context. */
-	if (!oldc)
+	/*
+	 * No MLS component to the security context, try and map to
+	 * default if provided.
+	 */
+	if (!oldc) {
+		struct context *defcon;
+
+		if (def_sid == SECSID_NULL)
+			goto out;
+
+		defcon = sidtab_search(s, def_sid);
+		if (!defcon)
+			goto out;
+
+		rc = mls_copy_context(context, defcon);
 		goto out;
+	}
 
 	/* Extract low sensitivity. */
 	scontextp = p = *scontext;
@@ -334,26 +379,6 @@ out:
 }
 
 /*
- * Copies the MLS range from `src' into `dst'.
- */
-static inline int mls_copy_context(struct context *dst,
-				   struct context *src)
-{
-	int l, rc = 0;
-
-	/* Copy the MLS range from the source context */
-	for (l = 0; l < 2; l++) {
-		dst->range.level[l].sens = src->range.level[l].sens;
-		rc = ebitmap_cpy(&dst->range.level[l].cat,
-				 &src->range.level[l].cat);
-		if (rc)
-			break;
-	}
-
-	return rc;
-}
-
-/*
  * Copies the effective MLS range from `src' into `dst'.
  */
 static inline int mls_scopy_context(struct context *dst,
diff --git a/security/selinux/ss/mls.h b/security/selinux/ss/mls.h
index 0d37beaa85e..03de697c805 100644
--- a/security/selinux/ss/mls.h
+++ b/security/selinux/ss/mls.h
@@ -23,7 +23,9 @@ int mls_context_isvalid(struct policydb *p, struct context *c);
 
 int mls_context_to_sid(char oldc,
 	               char **scontext,
-		       struct context *context);
+		       struct context *context,
+		       struct sidtab *s,
+		       u32 def_sid);
 
 int mls_convert_context(struct policydb *oldp,
 			struct policydb *newp,
diff --git a/security/selinux/ss/services.c b/security/selinux/ss/services.c
index bfa5a7dd6cf..45d317044cb 100644
--- a/security/selinux/ss/services.c
+++ b/security/selinux/ss/services.c
@@ -601,18 +601,7 @@ out:
 
 }
 
-/**
- * security_context_to_sid - Obtain a SID for a given security context.
- * @scontext: security context
- * @scontext_len: length in bytes
- * @sid: security identifier, SID
- *
- * Obtains a SID associated with the security context that
- * has the string representation specified by @scontext.
- * Returns -%EINVAL if the context is invalid, -%ENOMEM if insufficient
- * memory is available, or 0 on success.
- */
-int security_context_to_sid(char *scontext, u32 scontext_len, u32 *sid)
+static int security_context_to_sid_core(char *scontext, u32 scontext_len, u32 *sid, u32 def_sid)
 {
 	char *scontext2;
 	struct context context;
@@ -703,7 +692,7 @@ int security_context_to_sid(char *scontext, u32 scontext_len, u32 *sid)
 
 	context.type = typdatum->value;
 
-	rc = mls_context_to_sid(oldc, &p, &context);
+	rc = mls_context_to_sid(oldc, &p, &context, &sidtab, def_sid);
 	if (rc)
 		goto out_unlock;
 
@@ -727,6 +716,46 @@ out:
 	return rc;
 }
 
+/**
+ * security_context_to_sid - Obtain a SID for a given security context.
+ * @scontext: security context
+ * @scontext_len: length in bytes
+ * @sid: security identifier, SID
+ *
+ * Obtains a SID associated with the security context that
+ * has the string representation specified by @scontext.
+ * Returns -%EINVAL if the context is invalid, -%ENOMEM if insufficient
+ * memory is available, or 0 on success.
+ */
+int security_context_to_sid(char *scontext, u32 scontext_len, u32 *sid)
+{
+	return security_context_to_sid_core(scontext, scontext_len,
+	                                    sid, SECSID_NULL);
+}
+
+/**
+ * security_context_to_sid_default - Obtain a SID for a given security context,
+ * falling back to specified default if needed.
+ *
+ * @scontext: security context
+ * @scontext_len: length in bytes
+ * @sid: security identifier, SID
+ * @def_sid: default SID to assign on errror
+ *
+ * Obtains a SID associated with the security context that
+ * has the string representation specified by @scontext.
+ * The default SID is passed to the MLS layer to be used to allow
+ * kernel labeling of the MLS field if the MLS field is not present
+ * (for upgrading to MLS without full relabel).
+ * Returns -%EINVAL if the context is invalid, -%ENOMEM if insufficient
+ * memory is available, or 0 on success.
+ */
+int security_context_to_sid_default(char *scontext, u32 scontext_len, u32 *sid, u32 def_sid)
+{
+	return security_context_to_sid_core(scontext, scontext_len,
+	                                    sid, def_sid);
+}
+
 static int compute_sid_handle_invalid_context(
 	struct context *scontext,
 	struct context *tcontext,
diff --git a/sound/arm/Kconfig b/sound/arm/Kconfig
index 34c1740aa6e..2e4a5e0d16d 100644
--- a/sound/arm/Kconfig
+++ b/sound/arm/Kconfig
@@ -20,5 +20,17 @@ config SND_ARMAACI
 	select SND_PCM
 	select SND_AC97_CODEC
 
-endmenu
+config SND_PXA2XX_PCM
+	tristate
+	select SND_PCM
+
+config SND_PXA2XX_AC97
+	tristate "AC97 driver for the Intel PXA2xx chip"
+	depends on ARCH_PXA && SND
+	select SND_PXA2XX_PCM
+	select SND_AC97_CODEC
+	help
+	  Say Y or M if you want to support any AC97 codec attached to
+	  the PXA2xx AC97 interface.
 
+endmenu
diff --git a/sound/arm/Makefile b/sound/arm/Makefile
index f74ec28e106..103f136926d 100644
--- a/sound/arm/Makefile
+++ b/sound/arm/Makefile
@@ -3,9 +3,11 @@
 #
 
 snd-sa11xx-uda1341-objs := sa11xx-uda1341.o
+snd-aaci-objs			:= aaci.o devdma.o
+snd-pxa2xx-pcm-objs := pxa2xx-pcm.o
+snd-pxa2xx-ac97-objs := pxa2xx-ac97.o
 
-# Toplevel Module Dependency
 obj-$(CONFIG_SND_SA11XX_UDA1341) += snd-sa11xx-uda1341.o 
-
 obj-$(CONFIG_SND_ARMAACI)	+= snd-aaci.o
-snd-aaci-objs			:= aaci.o devdma.o
+obj-$(CONFIG_SND_PXA2XX_PCM) += snd-pxa2xx-pcm.o
+obj-$(CONFIG_SND_PXA2XX_AC97) += snd-pxa2xx-ac97.o
diff --git a/sound/arm/pxa2xx-ac97.c b/sound/arm/pxa2xx-ac97.c
new file mode 100644
index 00000000000..46052304e23
--- /dev/null
+++ b/sound/arm/pxa2xx-ac97.c
@@ -0,0 +1,410 @@
+/*
+ * linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip.
+ *
+ * Author:	Nicolas Pitre
+ * Created:	Dec 02, 2004
+ * Copyright:	MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/wait.h>
+#include <linux/delay.h>
+
+#include <sound/driver.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/ac97_codec.h>
+#include <sound/initval.h>
+
+#include <asm/irq.h>
+#include <asm/semaphore.h>
+#include <asm/hardware.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/audio.h>
+
+#include "pxa2xx-pcm.h"
+
+
+static DECLARE_MUTEX(car_mutex);
+static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
+static volatile long gsr_bits;
+
+static unsigned short pxa2xx_ac97_read(ac97_t *ac97, unsigned short reg)
+{
+	unsigned short val = -1;
+	volatile u32 *reg_addr;
+
+	down(&car_mutex);
+	if (CAR & CAR_CAIP) {
+		printk(KERN_CRIT"%s: CAR_CAIP already set\n", __FUNCTION__);
+		goto out;
+	}
+
+	/* set up primary or secondary codec space */
+	reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE;
+	reg_addr += (reg >> 1);
+
+	/* start read access across the ac97 link */
+	gsr_bits = 0;
+	val = *reg_addr;
+	if (reg == AC97_GPIO_STATUS)
+		goto out;
+	wait_event_timeout(gsr_wq, gsr_bits & GSR_SDONE, 1);
+	if (!gsr_bits & GSR_SDONE) {
+		printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
+				__FUNCTION__, reg, gsr_bits);
+		val = -1;
+		goto out;
+	}
+
+	/* valid data now */
+	gsr_bits = 0;
+	val = *reg_addr;			
+	/* but we've just started another cycle... */
+	wait_event_timeout(gsr_wq, gsr_bits & GSR_SDONE, 1);
+
+out:	up(&car_mutex);
+	return val;
+}
+
+static void pxa2xx_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val)
+{
+	volatile u32 *reg_addr;
+
+	down(&car_mutex);
+
+	if (CAR & CAR_CAIP) {
+		printk(KERN_CRIT "%s: CAR_CAIP already set\n", __FUNCTION__);
+		goto out;
+	}
+
+	/* set up primary or secondary codec space */
+	reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE;
+	reg_addr += (reg >> 1);
+	gsr_bits = 0;
+	*reg_addr = val;
+	wait_event_timeout(gsr_wq, gsr_bits & GSR_CDONE, 1);
+	if (!gsr_bits & GSR_SDONE)
+		printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
+				__FUNCTION__, reg, gsr_bits);
+
+out:	up(&car_mutex);
+}
+
+static void pxa2xx_ac97_reset(ac97_t *ac97)
+{
+	/* First, try cold reset */
+	GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
+	GCR &= ~GCR_COLD_RST;  /* then assert nCRST */
+
+	gsr_bits = 0;
+#ifdef CONFIG_PXA27x
+	/* PXA27x Developers Manual section 13.5.2.2.1 */
+	pxa_set_cken(1 << 31, 1);
+	udelay(5);
+	pxa_set_cken(1 << 31, 0);
+	GCR = GCR_COLD_RST;
+	udelay(50);
+#else
+	GCR = GCR_COLD_RST;
+	GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
+	wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
+#endif
+
+	if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) {
+		printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
+				 __FUNCTION__, gsr_bits);
+
+		/* let's try warm reset */
+		gsr_bits = 0;
+#ifdef CONFIG_PXA27x
+		/* warm reset broken on Bulverde,
+		   so manually keep AC97 reset high */
+		pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH); 
+		udelay(10);
+		GCR |= GCR_WARM_RST;
+		pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
+		udelay(50);
+#else
+		GCR |= GCR_WARM_RST|GCR_PRIRDY_IEN|GCR_SECRDY_IEN;;
+		wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
+#endif			
+
+		if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)))
+			printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
+					 __FUNCTION__, gsr_bits);
+	}
+
+	GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
+	GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
+}
+
+static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id, struct pt_regs *regs)
+{
+	long status;
+
+	status = GSR;
+	if (status) {
+		GSR = status;
+		gsr_bits |= status;
+		wake_up(&gsr_wq);
+
+#ifdef CONFIG_PXA27x
+		/* Although we don't use those we still need to clear them
+		   since they tend to spuriously trigger when MMC is used
+		   (hardware bug? go figure)... */
+		MISR = MISR_EOC;
+		PISR = PISR_EOC;
+		MCSR = MCSR_EOC;
+#endif
+
+		return IRQ_HANDLED;
+	}
+
+	return IRQ_NONE;
+}
+
+static ac97_bus_ops_t pxa2xx_ac97_ops = {
+	.read	= pxa2xx_ac97_read,
+	.write	= pxa2xx_ac97_write,
+	.reset	= pxa2xx_ac97_reset,
+};
+
+static pxa2xx_pcm_dma_params_t pxa2xx_ac97_pcm_out = {
+	.name			= "AC97 PCM out",
+	.dev_addr		= __PREG(PCDR),
+	.drcmr			= &DRCMRTXPCDR,
+	.dcmd			= DCMD_INCSRCADDR | DCMD_FLOWTRG |
+				  DCMD_BURST32 | DCMD_WIDTH4,
+};
+
+static pxa2xx_pcm_dma_params_t pxa2xx_ac97_pcm_in = {
+	.name			= "AC97 PCM in",
+	.dev_addr		= __PREG(PCDR),
+	.drcmr			= &DRCMRRXPCDR,
+	.dcmd			= DCMD_INCTRGADDR | DCMD_FLOWSRC |
+				  DCMD_BURST32 | DCMD_WIDTH4,
+};
+
+static snd_pcm_t *pxa2xx_ac97_pcm;
+static ac97_t *pxa2xx_ac97_ac97;
+
+static int pxa2xx_ac97_pcm_startup(snd_pcm_substream_t *substream)
+{
+	snd_pcm_runtime_t *runtime = substream->runtime;
+	pxa2xx_audio_ops_t *platform_ops;
+	int r;
+
+	runtime->hw.channels_min = 2;
+	runtime->hw.channels_max = 2;
+
+	r = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
+	    AC97_RATES_FRONT_DAC : AC97_RATES_ADC;
+	runtime->hw.rates = pxa2xx_ac97_ac97->rates[r];
+	snd_pcm_limit_hw_rates(runtime);
+
+       	platform_ops = substream->pcm->card->dev->platform_data;
+	if (platform_ops && platform_ops->startup)
+		return platform_ops->startup(substream, platform_ops->priv);
+	else
+		return 0;
+}
+
+static void pxa2xx_ac97_pcm_shutdown(snd_pcm_substream_t *substream)
+{
+	pxa2xx_audio_ops_t *platform_ops;
+
+       	platform_ops = substream->pcm->card->dev->platform_data;
+	if (platform_ops && platform_ops->shutdown)
+		platform_ops->shutdown(substream, platform_ops->priv);
+}
+
+static int pxa2xx_ac97_pcm_prepare(snd_pcm_substream_t *substream)
+{
+	snd_pcm_runtime_t *runtime = substream->runtime;
+	int reg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
+		  AC97_PCM_FRONT_DAC_RATE : AC97_PCM_LR_ADC_RATE;
+	return snd_ac97_set_rate(pxa2xx_ac97_ac97, reg, runtime->rate);
+}
+
+static pxa2xx_pcm_client_t pxa2xx_ac97_pcm_client = {
+	.playback_params	= &pxa2xx_ac97_pcm_out,
+	.capture_params		= &pxa2xx_ac97_pcm_in,
+	.startup		= pxa2xx_ac97_pcm_startup,
+	.shutdown		= pxa2xx_ac97_pcm_shutdown,
+	.prepare		= pxa2xx_ac97_pcm_prepare,
+};
+
+#ifdef CONFIG_PM
+
+static int pxa2xx_ac97_do_suspend(snd_card_t *card, unsigned int state)
+{
+	if (card->power_state != SNDRV_CTL_POWER_D3cold) {
+		pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data;
+		snd_pcm_suspend_all(pxa2xx_ac97_pcm);
+		snd_ac97_suspend(pxa2xx_ac97_ac97);
+		snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
+		if (platform_ops && platform_ops->suspend)
+			platform_ops->suspend(platform_ops->priv);
+		GCR |= GCR_ACLINK_OFF;
+		pxa_set_cken(CKEN2_AC97, 0);
+	}
+
+	return 0;
+}
+
+static int pxa2xx_ac97_do_resume(snd_card_t *card, unsigned int state)
+{
+	if (card->power_state != SNDRV_CTL_POWER_D0) {
+		pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data;
+		pxa_set_cken(CKEN2_AC97, 1);
+		if (platform_ops && platform_ops->resume)
+			platform_ops->resume(platform_ops->priv);
+		snd_ac97_resume(pxa2xx_ac97_ac97);
+		snd_power_change_state(card, SNDRV_CTL_POWER_D0);
+	}
+
+	return 0;
+}
+
+static int pxa2xx_ac97_suspend(struct device *_dev, u32 state, u32 level)
+{
+	snd_card_t *card = dev_get_drvdata(_dev);
+	int ret = 0;
+
+	if (card && level == SUSPEND_DISABLE)
+		ret = pxa2xx_ac97_do_suspend(card, SNDRV_CTL_POWER_D3cold);
+
+	return ret;
+}
+
+static int pxa2xx_ac97_resume(struct device *_dev, u32 level)
+{
+	snd_card_t *card = dev_get_drvdata(_dev);
+	int ret = 0;
+
+	if (card && level == RESUME_ENABLE)
+		ret = pxa2xx_ac97_do_resume(card, SNDRV_CTL_POWER_D0);
+
+	return ret;
+}
+
+#else
+#define pxa2xx_ac97_suspend	NULL
+#define pxa2xx_ac97_resume	NULL
+#endif
+
+static int pxa2xx_ac97_probe(struct device *dev)
+{
+	snd_card_t *card;
+	ac97_bus_t *ac97_bus;
+	ac97_template_t ac97_template;
+	int ret;
+
+	ret = -ENOMEM;
+	card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
+			    THIS_MODULE, 0);
+	if (!card)
+		goto err;
+
+	card->dev = dev;
+	strncpy(card->driver, dev->driver->name, sizeof(card->driver));
+
+	ret = pxa2xx_pcm_new(card, &pxa2xx_ac97_pcm_client, &pxa2xx_ac97_pcm);
+	if (ret)
+		goto err;
+
+	ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
+	if (ret < 0)
+		goto err;
+
+	pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
+	pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
+	pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
+	pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
+#ifdef CONFIG_PXA27x
+	/* Use GPIO 113 as AC97 Reset on Bulverde */
+	pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
+#endif
+	pxa_set_cken(CKEN2_AC97, 1);
+
+	ret = snd_ac97_bus(card, 0, &pxa2xx_ac97_ops, NULL, &ac97_bus);
+	if (ret)
+		goto err;
+	memset(&ac97_template, 0, sizeof(ac97_template));
+	ret = snd_ac97_mixer(ac97_bus, &ac97_template, &pxa2xx_ac97_ac97);
+	if (ret)
+		goto err;
+
+	snprintf(card->shortname, sizeof(card->shortname),
+		 "%s", snd_ac97_get_short_name(pxa2xx_ac97_ac97));
+	snprintf(card->longname, sizeof(card->longname),
+		 "%s (%s)", dev->driver->name, card->mixername);
+
+	snd_card_set_pm_callback(card, pxa2xx_ac97_do_suspend,
+				 pxa2xx_ac97_do_resume, NULL);
+	ret = snd_card_register(card);
+	if (ret == 0) {
+		dev_set_drvdata(dev, card);
+		return 0;
+	}
+
+ err:
+	if (card)
+		snd_card_free(card);
+	if (CKEN & CKEN2_AC97) {
+		GCR |= GCR_ACLINK_OFF;
+		free_irq(IRQ_AC97, NULL);
+		pxa_set_cken(CKEN2_AC97, 0);
+	}
+	return ret;
+}
+
+static int pxa2xx_ac97_remove(struct device *dev)
+{
+	snd_card_t *card = dev_get_drvdata(dev);
+
+	if (card) {
+		snd_card_free(card);
+		dev_set_drvdata(dev, NULL);
+		GCR |= GCR_ACLINK_OFF;
+		free_irq(IRQ_AC97, NULL);
+		pxa_set_cken(CKEN2_AC97, 0);
+	}
+
+	return 0;
+}
+
+static struct device_driver pxa2xx_ac97_driver = {
+	.name		= "pxa2xx-ac97",
+	.bus		= &platform_bus_type,
+	.probe		= pxa2xx_ac97_probe,
+	.remove		= pxa2xx_ac97_remove,
+	.suspend	= pxa2xx_ac97_suspend,
+	.resume		= pxa2xx_ac97_resume,
+};
+
+static int __init pxa2xx_ac97_init(void)
+{
+	return driver_register(&pxa2xx_ac97_driver);
+}
+
+static void __exit pxa2xx_ac97_exit(void)
+{
+	driver_unregister(&pxa2xx_ac97_driver);
+}
+
+module_init(pxa2xx_ac97_init);
+module_exit(pxa2xx_ac97_exit);
+
+MODULE_AUTHOR("Nicolas Pitre");
+MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip");
+MODULE_LICENSE("GPL");
diff --git a/sound/arm/pxa2xx-pcm.c b/sound/arm/pxa2xx-pcm.c
new file mode 100644
index 00000000000..b1eb53b02ea
--- /dev/null
+++ b/sound/arm/pxa2xx-pcm.c
@@ -0,0 +1,367 @@
+/*
+ * linux/sound/arm/pxa2xx-pcm.c -- ALSA PCM interface for the Intel PXA2xx chip
+ *
+ * Author:	Nicolas Pitre
+ * Created:	Nov 30, 2004
+ * Copyright:	(C) 2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+
+#include <sound/driver.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+
+#include <asm/dma.h>
+#include <asm/hardware.h>
+#include <asm/arch/pxa-regs.h>
+
+#include "pxa2xx-pcm.h"
+
+
+static const snd_pcm_hardware_t pxa2xx_pcm_hardware = {
+	.info			= SNDRV_PCM_INFO_MMAP |
+				  SNDRV_PCM_INFO_MMAP_VALID |
+				  SNDRV_PCM_INFO_INTERLEAVED |
+				  SNDRV_PCM_INFO_PAUSE,
+	.formats		= SNDRV_PCM_FMTBIT_S16_LE,
+	.period_bytes_min	= 32,
+	.period_bytes_max	= 8192 - 32,
+	.periods_min		= 1,
+	.periods_max		= PAGE_SIZE/sizeof(pxa_dma_desc),
+	.buffer_bytes_max	= 128 * 1024,
+	.fifo_size		= 32,
+};
+
+struct pxa2xx_runtime_data {
+	int dma_ch;
+	pxa2xx_pcm_dma_params_t *params;
+	pxa_dma_desc *dma_desc_array;
+	dma_addr_t dma_desc_array_phys;
+};
+
+static int pxa2xx_pcm_hw_params(snd_pcm_substream_t *substream,
+				snd_pcm_hw_params_t *params)
+{
+	snd_pcm_runtime_t *runtime = substream->runtime;
+	struct pxa2xx_runtime_data *rtd = runtime->private_data;
+	size_t totsize = params_buffer_bytes(params);
+	size_t period = params_period_bytes(params);
+	pxa_dma_desc *dma_desc;
+	dma_addr_t dma_buff_phys, next_desc_phys;
+
+	snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
+	runtime->dma_bytes = totsize;
+
+	dma_desc = rtd->dma_desc_array;
+	next_desc_phys = rtd->dma_desc_array_phys;
+	dma_buff_phys = runtime->dma_addr;
+	do {
+		next_desc_phys += sizeof(pxa_dma_desc);
+		dma_desc->ddadr = next_desc_phys;
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+			dma_desc->dsadr = dma_buff_phys;
+			dma_desc->dtadr = rtd->params->dev_addr;
+		} else {
+			dma_desc->dsadr = rtd->params->dev_addr;
+			dma_desc->dtadr = dma_buff_phys;
+		}
+		if (period > totsize)
+			period = totsize;
+		dma_desc->dcmd = rtd->params->dcmd | period | DCMD_ENDIRQEN;
+		dma_desc++;
+		dma_buff_phys += period;
+	} while (totsize -= period);
+	dma_desc[-1].ddadr = rtd->dma_desc_array_phys;
+
+	return 0;
+}
+
+static int pxa2xx_pcm_hw_free(snd_pcm_substream_t *substream)
+{
+	struct pxa2xx_runtime_data *rtd = substream->runtime->private_data;
+
+	*rtd->params->drcmr = 0;
+	snd_pcm_set_runtime_buffer(substream, NULL);
+	return 0;
+}
+
+static int pxa2xx_pcm_prepare(snd_pcm_substream_t *substream)
+{
+	pxa2xx_pcm_client_t *client = substream->private_data;
+	snd_pcm_runtime_t *runtime = substream->runtime;
+	struct pxa2xx_runtime_data *rtd = runtime->private_data;
+
+	DCSR(rtd->dma_ch) &= ~DCSR_RUN;
+	DCSR(rtd->dma_ch) = 0;
+	DCMD(rtd->dma_ch) = 0;
+	*rtd->params->drcmr = rtd->dma_ch | DRCMR_MAPVLD;
+
+	return client->prepare(substream);
+}
+
+static int pxa2xx_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
+{
+	struct pxa2xx_runtime_data *rtd = substream->runtime->private_data;
+	int ret = 0;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+		DDADR(rtd->dma_ch) = rtd->dma_desc_array_phys;
+		DCSR(rtd->dma_ch) = DCSR_RUN;
+		break;
+
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		DCSR(rtd->dma_ch) &= ~DCSR_RUN;
+		break;
+
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		DCSR(rtd->dma_ch) |= DCSR_RUN;
+		break;
+
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static void pxa2xx_pcm_dma_irq(int dma_ch, void *dev_id, struct pt_regs *regs)
+{
+	snd_pcm_substream_t *substream = dev_id;
+	struct pxa2xx_runtime_data *rtd = substream->runtime->private_data;
+	int dcsr;
+
+	dcsr = DCSR(dma_ch);
+	DCSR(dma_ch) = dcsr & ~DCSR_STOPIRQEN;
+
+	if (dcsr & DCSR_ENDINTR) {
+		snd_pcm_period_elapsed(substream);
+	} else {
+		printk( KERN_ERR "%s: DMA error on channel %d (DCSR=%#x)\n",
+			rtd->params->name, dma_ch, dcsr );
+		snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
+	}
+}
+
+static snd_pcm_uframes_t pxa2xx_pcm_pointer(snd_pcm_substream_t *substream)
+{
+	snd_pcm_runtime_t *runtime = substream->runtime;
+	struct pxa2xx_runtime_data *rtd = runtime->private_data;
+	dma_addr_t ptr = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
+			 DSADR(rtd->dma_ch) : DTADR(rtd->dma_ch);
+	snd_pcm_uframes_t x = bytes_to_frames(runtime, ptr - runtime->dma_addr);
+	if (x == runtime->buffer_size)
+		x = 0;
+	return x;
+}
+
+static int
+pxa2xx_pcm_hw_rule_mult32(snd_pcm_hw_params_t *params, snd_pcm_hw_rule_t *rule)
+{
+	snd_interval_t *i = hw_param_interval(params, rule->var);
+	int changed = 0;
+
+	if (i->min & 31) {
+		i->min = (i->min & ~31) + 32;
+		i->openmin = 0;
+		changed = 1;
+	}
+
+	if (i->max & 31) {
+		i->max &= ~31;
+		i->openmax = 0;
+		changed = 1;
+	}
+
+	return changed;
+}
+
+static int pxa2xx_pcm_open(snd_pcm_substream_t *substream)
+{
+	pxa2xx_pcm_client_t *client = substream->private_data;
+	snd_pcm_runtime_t *runtime = substream->runtime;
+	struct pxa2xx_runtime_data *rtd;
+	int ret;
+
+	runtime->hw = pxa2xx_pcm_hardware;
+
+	/*
+	 * For mysterious reasons (and despite what the manual says)
+	 * playback samples are lost if the DMA count is not a multiple
+	 * of the DMA burst size.  Let's add a rule to enforce that.
+	 */
+	ret = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
+				  pxa2xx_pcm_hw_rule_mult32, NULL,
+				  SNDRV_PCM_HW_PARAM_PERIOD_BYTES, -1);
+	if (ret)
+		goto out;
+	ret = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
+				  pxa2xx_pcm_hw_rule_mult32, NULL,
+				  SNDRV_PCM_HW_PARAM_BUFFER_BYTES, -1);
+	if (ret)
+		goto out;
+
+	ret = -ENOMEM;
+	rtd = kmalloc(sizeof(*rtd), GFP_KERNEL);
+	if (!rtd)
+		goto out;
+	rtd->dma_desc_array =
+		dma_alloc_writecombine(substream->pcm->card->dev, PAGE_SIZE,
+				       &rtd->dma_desc_array_phys, GFP_KERNEL);
+	if (!rtd->dma_desc_array)
+		goto err1;
+
+	rtd->params = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
+		      client->playback_params : client->capture_params;
+	ret = pxa_request_dma(rtd->params->name, DMA_PRIO_LOW,
+			      pxa2xx_pcm_dma_irq, substream);
+	if (ret < 0)
+		goto err2;
+	rtd->dma_ch = ret;
+
+	runtime->private_data = rtd;
+	ret = client->startup(substream);
+	if (!ret)
+		goto out;
+
+	pxa_free_dma(rtd->dma_ch);
+ err2:
+	dma_free_writecombine(substream->pcm->card->dev, PAGE_SIZE,
+			      rtd->dma_desc_array, rtd->dma_desc_array_phys);
+ err1:
+	kfree(rtd);
+ out:
+	return ret;
+}
+
+static int pxa2xx_pcm_close(snd_pcm_substream_t *substream)
+{
+	pxa2xx_pcm_client_t *client = substream->private_data;
+	struct pxa2xx_runtime_data *rtd = substream->runtime->private_data;
+
+	pxa_free_dma(rtd->dma_ch);
+	client->shutdown(substream);
+	dma_free_writecombine(substream->pcm->card->dev, PAGE_SIZE,
+			      rtd->dma_desc_array, rtd->dma_desc_array_phys);
+	kfree(rtd);
+	return 0;
+}
+
+static int
+pxa2xx_pcm_mmap(snd_pcm_substream_t *substream, struct vm_area_struct *vma)
+{
+	snd_pcm_runtime_t *runtime = substream->runtime;
+	return dma_mmap_writecombine(substream->pcm->card->dev, vma,
+				     runtime->dma_area,
+				     runtime->dma_addr,
+				     runtime->dma_bytes);
+}
+
+static snd_pcm_ops_t pxa2xx_pcm_ops = {
+	.open		= pxa2xx_pcm_open,
+	.close		= pxa2xx_pcm_close,
+	.ioctl		= snd_pcm_lib_ioctl,
+	.hw_params	= pxa2xx_pcm_hw_params,
+	.hw_free	= pxa2xx_pcm_hw_free,
+	.prepare	= pxa2xx_pcm_prepare,
+	.trigger	= pxa2xx_pcm_trigger,
+	.pointer	= pxa2xx_pcm_pointer,
+	.mmap		= pxa2xx_pcm_mmap,
+};
+
+static int pxa2xx_pcm_preallocate_dma_buffer(snd_pcm_t *pcm, int stream)
+{
+	snd_pcm_substream_t *substream = pcm->streams[stream].substream;
+	struct snd_dma_buffer *buf = &substream->dma_buffer;
+	size_t size = pxa2xx_pcm_hardware.buffer_bytes_max;
+	buf->dev.type = SNDRV_DMA_TYPE_DEV;
+	buf->dev.dev = pcm->card->dev;
+	buf->private_data = NULL;
+	buf->area = dma_alloc_writecombine(pcm->card->dev, size,
+					   &buf->addr, GFP_KERNEL);
+	if (!buf->area)
+		return -ENOMEM;
+	buf->bytes = size;
+	return 0;
+}
+
+static void pxa2xx_pcm_free_dma_buffers(snd_pcm_t *pcm)
+{
+	snd_pcm_substream_t *substream;
+	struct snd_dma_buffer *buf;
+	int stream;
+
+	for (stream = 0; stream < 2; stream++) {
+		substream = pcm->streams[stream].substream;
+		if (!substream)
+			continue;
+		buf = &substream->dma_buffer;
+		if (!buf->area)
+			continue;
+		dma_free_writecombine(pcm->card->dev, buf->bytes,
+				      buf->area, buf->addr);
+		buf->area = NULL;
+	}
+}
+
+static u64 pxa2xx_pcm_dmamask = 0xffffffff;
+
+int pxa2xx_pcm_new(snd_card_t *card, pxa2xx_pcm_client_t *client, snd_pcm_t **rpcm)
+{
+	snd_pcm_t *pcm;
+	int play = client->playback_params ? 1 : 0;
+	int capt = client->capture_params ? 1 : 0;
+	int ret;
+
+	ret = snd_pcm_new(card, "PXA2xx-PCM", 0, play, capt, &pcm);
+	if (ret)
+		goto out;
+
+	pcm->private_data = client;
+	pcm->private_free = pxa2xx_pcm_free_dma_buffers;
+
+	if (!card->dev->dma_mask)
+		card->dev->dma_mask = &pxa2xx_pcm_dmamask;
+	if (!card->dev->coherent_dma_mask)
+		card->dev->coherent_dma_mask = 0xffffffff;
+
+	if (play) {
+		int stream = SNDRV_PCM_STREAM_PLAYBACK;
+		snd_pcm_set_ops(pcm, stream, &pxa2xx_pcm_ops);
+		ret = pxa2xx_pcm_preallocate_dma_buffer(pcm, stream);
+		if (ret)
+			goto out;
+	}
+	if (capt) {
+		int stream = SNDRV_PCM_STREAM_CAPTURE;
+		snd_pcm_set_ops(pcm, stream, &pxa2xx_pcm_ops);
+		ret = pxa2xx_pcm_preallocate_dma_buffer(pcm, stream);
+		if (ret)
+			goto out;
+	}
+
+	if (rpcm)
+		*rpcm = pcm;
+	ret = 0;
+
+ out:
+	return ret;
+}
+
+EXPORT_SYMBOL(pxa2xx_pcm_new);
+
+MODULE_AUTHOR("Nicolas Pitre");
+MODULE_DESCRIPTION("Intel PXA2xx PCM DMA module");
+MODULE_LICENSE("GPL");
diff --git a/sound/arm/pxa2xx-pcm.h b/sound/arm/pxa2xx-pcm.h
new file mode 100644
index 00000000000..43517597cab
--- /dev/null
+++ b/sound/arm/pxa2xx-pcm.h
@@ -0,0 +1,29 @@
+/*
+ * linux/sound/arm/pxa2xx-pcm.h -- ALSA PCM interface for the Intel PXA2xx chip
+ *
+ * Author:	Nicolas Pitre
+ * Created:	Nov 30, 2004
+ * Copyright:	MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+typedef struct {
+	char *name;			/* stream identifier */
+	u32 dcmd;			/* DMA descriptor dcmd field */
+	volatile u32 *drcmr;		/* the DMA request channel to use */
+	u32 dev_addr;			/* device physical address for DMA */
+} pxa2xx_pcm_dma_params_t;
+	
+typedef struct {
+	pxa2xx_pcm_dma_params_t *playback_params;
+	pxa2xx_pcm_dma_params_t *capture_params;
+	int (*startup)(snd_pcm_substream_t *);
+	void (*shutdown)(snd_pcm_substream_t *);
+	int (*prepare)(snd_pcm_substream_t *);
+} pxa2xx_pcm_client_t;
+
+extern int pxa2xx_pcm_new(snd_card_t *, pxa2xx_pcm_client_t *, snd_pcm_t **);
+
diff --git a/sound/core/device.c b/sound/core/device.c
index 18c71f913d2..ca00ad7740c 100644
--- a/sound/core/device.c
+++ b/sound/core/device.c
@@ -28,7 +28,7 @@
 /**
  * snd_device_new - create an ALSA device component
  * @card: the card instance
- * @type: the device type, SNDRV_DEV_TYPE_XXX
+ * @type: the device type, SNDRV_DEV_XXX
  * @device_data: the data pointer of this device
  * @ops: the operator table
  *
@@ -46,7 +46,9 @@ int snd_device_new(snd_card_t *card, snd_device_type_t type,
 {
 	snd_device_t *dev;
 
-	snd_assert(card != NULL && device_data != NULL && ops != NULL, return -ENXIO);
+	snd_assert(card != NULL, return -ENXIO);
+	snd_assert(device_data != NULL, return -ENXIO);
+	snd_assert(ops != NULL, return -ENXIO);
 	dev = kcalloc(1, sizeof(*dev), GFP_KERNEL);
 	if (dev == NULL)
 		return -ENOMEM;
@@ -102,7 +104,7 @@ int snd_device_free(snd_card_t *card, void *device_data)
 }
 
 /**
- * snd_device_free - disconnect the device
+ * snd_device_disconnect - disconnect the device
  * @card: the card instance
  * @device_data: the data pointer to disconnect
  *
@@ -118,7 +120,7 @@ int snd_device_disconnect(snd_card_t *card, void *device_data)
 {
 	struct list_head *list;
 	snd_device_t *dev;
-	
+
 	snd_assert(card != NULL, return -ENXIO);
 	snd_assert(device_data != NULL, return -ENXIO);
 	list_for_each(list, &card->devices) {
@@ -154,8 +156,9 @@ int snd_device_register(snd_card_t *card, void *device_data)
 	struct list_head *list;
 	snd_device_t *dev;
 	int err;
-	
-	snd_assert(card != NULL && device_data != NULL, return -ENXIO);
+
+	snd_assert(card != NULL, return -ENXIO);
+	snd_assert(device_data != NULL, return -ENXIO);
 	list_for_each(list, &card->devices) {
 		dev = snd_device(list);
 		if (dev->device_data != device_data)
diff --git a/sound/core/info.c b/sound/core/info.c
index 5e122bbe7c9..7f8bdf7b005 100644
--- a/sound/core/info.c
+++ b/sound/core/info.c
@@ -702,7 +702,7 @@ int snd_info_get_line(snd_info_buffer_t * buffer, char *line, int len)
 }
 
 /**
- * snd_info_get_line - parse a string token
+ * snd_info_get_str - parse a string token
  * @dest: the buffer to store the string token
  * @src: the original string
  * @len: the max. length of token - 1
@@ -939,7 +939,8 @@ int snd_info_unregister(snd_info_entry_t * entry)
 {
 	struct proc_dir_entry *root;
 
-	snd_assert(entry != NULL && entry->p != NULL, return -ENXIO);
+	snd_assert(entry != NULL, return -ENXIO);
+	snd_assert(entry->p != NULL, return -ENXIO);
 	root = entry->parent == NULL ? snd_proc_root : entry->parent->p;
 	snd_assert(root, return -ENXIO);
 	down(&info_mutex);
diff --git a/sound/core/memalloc.c b/sound/core/memalloc.c
index dbc23e35fa0..02132561c3f 100644
--- a/sound/core/memalloc.c
+++ b/sound/core/memalloc.c
@@ -105,7 +105,8 @@ struct snd_mem_list {
  */
 
 static void *snd_dma_hack_alloc_coherent(struct device *dev, size_t size,
-					 dma_addr_t *dma_handle, int flags)
+					 dma_addr_t *dma_handle,
+					 unsigned int __nocast flags)
 {
 	void *ret;
 	u64 dma_mask, coherent_dma_mask;
diff --git a/sound/core/memory.c b/sound/core/memory.c
index c1fb28e8433..f6895577bf8 100644
--- a/sound/core/memory.c
+++ b/sound/core/memory.c
@@ -89,7 +89,7 @@ void snd_memory_done(void)
 	}
 }
 
-static void *__snd_kmalloc(size_t size, int flags, void *caller)
+static void *__snd_kmalloc(size_t size, unsigned int __nocast flags, void *caller)
 {
 	unsigned long cpu_flags;
 	struct snd_alloc_track *t;
@@ -111,12 +111,12 @@ static void *__snd_kmalloc(size_t size, int flags, void *caller)
 }
 
 #define _snd_kmalloc(size, flags) __snd_kmalloc((size), (flags), __builtin_return_address(0));
-void *snd_hidden_kmalloc(size_t size, int flags)
+void *snd_hidden_kmalloc(size_t size, unsigned int __nocast flags)
 {
 	return _snd_kmalloc(size, flags);
 }
 
-void *snd_hidden_kcalloc(size_t n, size_t size, int flags)
+void *snd_hidden_kcalloc(size_t n, size_t size, unsigned int __nocast flags)
 {
 	void *ret = NULL;
 	if (n != 0 && size > INT_MAX / n)
@@ -184,7 +184,7 @@ void snd_hidden_vfree(void *obj)
 	snd_wrapper_vfree(obj);
 }
 
-char *snd_hidden_kstrdup(const char *s, int flags)
+char *snd_hidden_kstrdup(const char *s, unsigned int __nocast flags)
 {
 	int len;
 	char *buf;
diff --git a/sound/core/seq/Makefile b/sound/core/seq/Makefile
index 64cb50d7b58..402e2b4a34c 100644
--- a/sound/core/seq/Makefile
+++ b/sound/core/seq/Makefile
@@ -38,7 +38,7 @@ obj-$(CONFIG_SND_VIRMIDI) += snd-seq-virmidi.o snd-seq-midi-event.o
 obj-$(call sequencer,$(CONFIG_SND_RAWMIDI)) += snd-seq-midi.o snd-seq-midi-event.o
 obj-$(call sequencer,$(CONFIG_SND_OPL3_LIB)) += snd-seq-midi-event.o snd-seq-midi-emul.o snd-seq-instr.o
 obj-$(call sequencer,$(CONFIG_SND_OPL4_LIB)) += snd-seq-midi-event.o snd-seq-midi-emul.o snd-seq-instr.o
-obj-$(call sequencer,$(CONFIG_SND_GUS_SYNTH)) += snd-seq-instr.o
+obj-$(call sequencer,$(CONFIG_SND_GUS_SYNTH)) += snd-seq-midi-emul.o snd-seq-instr.o
 obj-$(call sequencer,$(CONFIG_SND_SBAWE)) += snd-seq-midi-emul.o snd-seq-virmidi.o
 obj-$(call sequencer,$(CONFIG_SND_EMU10K1)) += snd-seq-midi-emul.o snd-seq-virmidi.o
 obj-$(call sequencer,$(CONFIG_SND_TRIDENT)) += snd-seq-midi-emul.o snd-seq-instr.o
diff --git a/sound/core/seq/instr/ainstr_gf1.c b/sound/core/seq/instr/ainstr_gf1.c
index 0779c41ca03..32e91c6b25f 100644
--- a/sound/core/seq/instr/ainstr_gf1.c
+++ b/sound/core/seq/instr/ainstr_gf1.c
@@ -50,7 +50,8 @@ static int snd_seq_gf1_copy_wave_from_stream(snd_gf1_ops_t *ops,
 {
 	gf1_wave_t *wp, *prev;
 	gf1_xwave_t xp;
-	int err, gfp_mask;
+	int err;
+	unsigned int gfp_mask;
 	unsigned int real_size;
 	
 	gfp_mask = atomic ? GFP_ATOMIC : GFP_KERNEL;
diff --git a/sound/core/seq/instr/ainstr_iw.c b/sound/core/seq/instr/ainstr_iw.c
index 39ff72b2aab..2622b8679ca 100644
--- a/sound/core/seq/instr/ainstr_iw.c
+++ b/sound/core/seq/instr/ainstr_iw.c
@@ -58,7 +58,7 @@ static int snd_seq_iwffff_copy_env_from_stream(__u32 req_stype,
 					       iwffff_xenv_t *ex,
 					       char __user **data,
 					       long *len,
-					       int gfp_mask)
+					       unsigned int __nocast gfp_mask)
 {
 	__u32 stype;
 	iwffff_env_record_t *rp, *rp_last;
@@ -128,7 +128,8 @@ static int snd_seq_iwffff_copy_wave_from_stream(snd_iwffff_ops_t *ops,
 {
 	iwffff_wave_t *wp, *prev;
 	iwffff_xwave_t xp;
-	int err, gfp_mask;
+	int err;
+	unsigned int gfp_mask;
 	unsigned int real_size;
 	
 	gfp_mask = atomic ? GFP_ATOMIC : GFP_KERNEL;
@@ -234,7 +235,8 @@ static int snd_seq_iwffff_put(void *private_data, snd_seq_kinstr_t *instr,
 	iwffff_xinstrument_t ix;
 	iwffff_layer_t *lp, *prev_lp;
 	iwffff_xlayer_t lx;
-	int err, gfp_mask;
+	int err;
+	unsigned int gfp_mask;
 
 	if (cmd != SNDRV_SEQ_INSTR_PUT_CMD_CREATE)
 		return -EINVAL;
diff --git a/sound/core/seq/oss/seq_oss_device.h b/sound/core/seq/oss/seq_oss_device.h
index da23c4db8dd..973786758c5 100644
--- a/sound/core/seq/oss/seq_oss_device.h
+++ b/sound/core/seq/oss/seq_oss_device.h
@@ -158,21 +158,21 @@ void snd_seq_oss_readq_info_read(seq_oss_readq_t *q, snd_info_buffer_t *buf);
 #define is_nonblock_mode(mode)	((mode) & SNDRV_SEQ_OSS_FILE_NONBLOCK)
 
 /* dispatch event */
-inline static int
+static inline int
 snd_seq_oss_dispatch(seq_oss_devinfo_t *dp, snd_seq_event_t *ev, int atomic, int hop)
 {
 	return snd_seq_kernel_client_dispatch(dp->cseq, ev, atomic, hop);
 }
 
 /* ioctl */
-inline static int
+static inline int
 snd_seq_oss_control(seq_oss_devinfo_t *dp, unsigned int type, void *arg)
 {
 	return snd_seq_kernel_client_ctl(dp->cseq, type, arg);
 }
 
 /* fill the addresses in header */
-inline static void
+static inline void
 snd_seq_oss_fill_addr(seq_oss_devinfo_t *dp, snd_seq_event_t *ev,
 		     int dest_client, int dest_port)
 {
diff --git a/sound/core/seq/seq_memory.c b/sound/core/seq/seq_memory.c
index 00d841e82fb..03acb2d519b 100644
--- a/sound/core/seq/seq_memory.c
+++ b/sound/core/seq/seq_memory.c
@@ -36,12 +36,12 @@
 #define semaphore_of(fp)	((fp)->f_dentry->d_inode->i_sem)
 
 
-inline static int snd_seq_pool_available(pool_t *pool)
+static inline int snd_seq_pool_available(pool_t *pool)
 {
 	return pool->total_elements - atomic_read(&pool->counter);
 }
 
-inline static int snd_seq_output_ok(pool_t *pool)
+static inline int snd_seq_output_ok(pool_t *pool)
 {
 	return snd_seq_pool_available(pool) >= pool->room;
 }
diff --git a/sound/core/seq/seq_midi.c b/sound/core/seq/seq_midi.c
index 57be9155eb6..4374829ea77 100644
--- a/sound/core/seq/seq_midi.c
+++ b/sound/core/seq/seq_midi.c
@@ -134,7 +134,7 @@ static int event_process_midi(snd_seq_event_t * ev, int direct,
 	seq_midisynth_t *msynth = (seq_midisynth_t *) private_data;
 	unsigned char msg[10];	/* buffer for constructing midi messages */
 	snd_rawmidi_substream_t *substream;
-	int res;
+	int len;
 
 	snd_assert(msynth != NULL, return -EINVAL);
 	substream = msynth->output_rfile.output;
@@ -146,20 +146,16 @@ static int event_process_midi(snd_seq_event_t * ev, int direct,
 			snd_printd("seq_midi: invalid sysex event flags = 0x%x\n", ev->flags);
 			return 0;
 		}
-		res = snd_seq_dump_var_event(ev, (snd_seq_dump_func_t)dump_midi, substream);
+		snd_seq_dump_var_event(ev, (snd_seq_dump_func_t)dump_midi, substream);
 		snd_midi_event_reset_decode(msynth->parser);
-		if (res < 0)
-			return res;
 	} else {
 		if (msynth->parser == NULL)
 			return -EIO;
-		res = snd_midi_event_decode(msynth->parser, msg, sizeof(msg), ev);
-		if (res < 0)
-			return res;
-		if ((res = dump_midi(substream, msg, res)) < 0) {
+		len = snd_midi_event_decode(msynth->parser, msg, sizeof(msg), ev);
+		if (len < 0)
+			return 0;
+		if (dump_midi(substream, msg, len) < 0)
 			snd_midi_event_reset_decode(msynth->parser);
-			return res;
-		}
 	}
 	return 0;
 }
diff --git a/sound/core/seq/seq_midi_event.c b/sound/core/seq/seq_midi_event.c
index df1e2bb3974..603b63716db 100644
--- a/sound/core/seq/seq_midi_event.c
+++ b/sound/core/seq/seq_midi_event.c
@@ -146,7 +146,7 @@ void snd_midi_event_free(snd_midi_event_t *dev)
 /*
  * initialize record
  */
-inline static void reset_encode(snd_midi_event_t *dev)
+static inline void reset_encode(snd_midi_event_t *dev)
 {
 	dev->read = 0;
 	dev->qlen = 0;
diff --git a/sound/core/wrappers.c b/sound/core/wrappers.c
index 9f393023c32..508e6d67ee1 100644
--- a/sound/core/wrappers.c
+++ b/sound/core/wrappers.c
@@ -27,7 +27,7 @@
 #include <linux/fs.h>
 
 #ifdef CONFIG_SND_DEBUG_MEMORY
-void *snd_wrapper_kmalloc(size_t size, int flags)
+void *snd_wrapper_kmalloc(size_t size, unsigned int __nocast flags)
 {
 	return kmalloc(size, flags);
 }
diff --git a/sound/drivers/serial-u16550.c b/sound/drivers/serial-u16550.c
index 964b97e70c8..986df35fb82 100644
--- a/sound/drivers/serial-u16550.c
+++ b/sound/drivers/serial-u16550.c
@@ -168,7 +168,7 @@ typedef struct _snd_uart16550 {
 
 static snd_card_t *snd_serial_cards[SNDRV_CARDS] = SNDRV_DEFAULT_PTR;
 
-inline static void snd_uart16550_add_timer(snd_uart16550_t *uart)
+static inline void snd_uart16550_add_timer(snd_uart16550_t *uart)
 {
 	if (! uart->timer_running) {
 		/* timer 38600bps * 10bit * 16byte */
@@ -178,7 +178,7 @@ inline static void snd_uart16550_add_timer(snd_uart16550_t *uart)
 	}
 }
 
-inline static void snd_uart16550_del_timer(snd_uart16550_t *uart)
+static inline void snd_uart16550_del_timer(snd_uart16550_t *uart)
 {
 	if (uart->timer_running) {
 		del_timer(&uart->buffer_timer);
@@ -187,7 +187,7 @@ inline static void snd_uart16550_del_timer(snd_uart16550_t *uart)
 }
 
 /* This macro is only used in snd_uart16550_io_loop */
-inline static void snd_uart16550_buffer_output(snd_uart16550_t *uart)
+static inline void snd_uart16550_buffer_output(snd_uart16550_t *uart)
 {
 	unsigned short buff_out = uart->buff_out;
 	if( uart->buff_in_count > 0 ) {
@@ -579,7 +579,7 @@ static int snd_uart16550_output_close(snd_rawmidi_substream_t * substream)
 	return 0;
 };
 
-inline static int snd_uart16550_buffer_can_write( snd_uart16550_t *uart, int Num )
+static inline int snd_uart16550_buffer_can_write( snd_uart16550_t *uart, int Num )
 {
 	if( uart->buff_in_count + Num < TX_BUFF_SIZE )
 		return 1;
@@ -587,7 +587,7 @@ inline static int snd_uart16550_buffer_can_write( snd_uart16550_t *uart, int Num
 		return 0;
 }
 
-inline static int snd_uart16550_write_buffer(snd_uart16550_t *uart, unsigned char byte)
+static inline int snd_uart16550_write_buffer(snd_uart16550_t *uart, unsigned char byte)
 {
 	unsigned short buff_in = uart->buff_in;
 	if( uart->buff_in_count < TX_BUFF_SIZE ) {
diff --git a/sound/drivers/vx/vx_uer.c b/sound/drivers/vx/vx_uer.c
index 18114713c3b..4fc38bde34f 100644
--- a/sound/drivers/vx/vx_uer.c
+++ b/sound/drivers/vx/vx_uer.c
@@ -162,34 +162,24 @@ static int vx_read_uer_status(vx_core_t *chip, int *mode)
 
 static int vx_calc_clock_from_freq(vx_core_t *chip, int freq)
 {
-#define XX_FECH48000                    0x0000004B
-#define XX_FECH32000                    0x00000171
-#define XX_FECH24000                    0x0000024B
-#define XX_FECH16000                    0x00000371
-#define XX_FECH12000                    0x0000044B
-#define XX_FECH8000                     0x00000571
-#define XX_FECH44100                    0x0000007F
-#define XX_FECH29400                    0x0000016F
-#define XX_FECH22050                    0x0000027F
-#define XX_FECH14000                    0x000003EF
-#define XX_FECH11025                    0x0000047F
-#define XX_FECH7350                     0x000005BF
-
-	switch (freq) {
-	case 48000:     return XX_FECH48000;
-	case 44100:     return XX_FECH44100;
-	case 32000:     return XX_FECH32000;
-	case 29400:     return XX_FECH29400;
-	case 24000:     return XX_FECH24000;
-	case 22050:     return XX_FECH22050;
-	case 16000:     return XX_FECH16000;
-	case 14000:     return XX_FECH14000;
-	case 12000:     return XX_FECH12000;
-	case 11025:     return XX_FECH11025;
-	case 8000:      return XX_FECH8000;
-	case 7350:      return XX_FECH7350;
-	default:        return freq;   /* The value is already correct */
-	}
+	int hexfreq;
+
+	snd_assert(freq > 0, return 0);
+
+	hexfreq = (28224000 * 10) / freq;
+	hexfreq = (hexfreq + 5) / 10;
+
+	/* max freq = 55125 Hz */
+	snd_assert(hexfreq > 0x00000200, return 0);
+
+	if (hexfreq <= 0x03ff)
+		return hexfreq - 0x00000201;
+	if (hexfreq <= 0x07ff) 
+		return (hexfreq / 2) - 1;
+	if (hexfreq <= 0x0fff)
+		return (hexfreq / 4) + 0x000001ff;
+
+	return 0x5fe; 	/* min freq = 6893 Hz */
 }
 
 
diff --git a/sound/i2c/other/ak4114.c b/sound/i2c/other/ak4114.c
index f5e6018ea3f..5adde308a00 100644
--- a/sound/i2c/other/ak4114.c
+++ b/sound/i2c/other/ak4114.c
@@ -554,7 +554,6 @@ int snd_ak4114_check_rate_and_errors(ak4114_t *ak4114, unsigned int flags)
 		if (snd_pcm_running(ak4114->capture_substream)) {
 			// printk("rate changed (%i <- %i)\n", runtime->rate, res);
 			snd_pcm_stop(ak4114->capture_substream, SNDRV_PCM_STATE_DRAINING);
-			wake_up(&runtime->sleep);
 			res = 1;
 		}
 		snd_pcm_stream_unlock_irqrestore(ak4114->capture_substream, _flags);
diff --git a/sound/isa/gus/gus_main.c b/sound/isa/gus/gus_main.c
index 94bbd344be5..a636d9ce350 100644
--- a/sound/isa/gus/gus_main.c
+++ b/sound/isa/gus/gus_main.c
@@ -417,11 +417,13 @@ static int snd_gus_check_version(snd_gus_card_t * gus)
 	return 0;
 }
 
+#if defined(CONFIG_SND_SEQUENCER) || (defined(MODULE) && defined(CONFIG_SND_SEQUENCER_MODULE))
 static void snd_gus_seq_dev_free(snd_seq_device_t *seq_dev)
 {
 	snd_gus_card_t *gus = seq_dev->private_data;
 	gus->seq_dev = NULL;
 }
+#endif
 
 int snd_gus_initialize(snd_gus_card_t *gus)
 {
diff --git a/sound/isa/sb/emu8000_patch.c b/sound/isa/sb/emu8000_patch.c
index 4afc4a1bc14..26e693078cb 100644
--- a/sound/isa/sb/emu8000_patch.c
+++ b/sound/isa/sb/emu8000_patch.c
@@ -128,7 +128,7 @@ snd_emu8000_write_wait(emu8000_t *emu)
  * This is therefore much slower than need be, but is at least
  * working.
  */
-inline static void
+static inline void
 write_word(emu8000_t *emu, int *offset, unsigned short data)
 {
 	if (emu8000_reset_addr) {
diff --git a/sound/isa/sb/sb_mixer.c b/sound/isa/sb/sb_mixer.c
index cc5a2c6dec1..ff4b5996802 100644
--- a/sound/isa/sb/sb_mixer.c
+++ b/sound/isa/sb/sb_mixer.c
@@ -688,7 +688,7 @@ static struct sbmix_elem snd_als4000_ctl_3d_poweroff_switch =
 	SB_SINGLE("3D PowerOff Switch", SB_ALS4000_3D_TIME_DELAY, 4, 0x01);
 static struct sbmix_elem snd_als4000_ctl_3d_delay =
 	SB_SINGLE("3D Delay", SB_ALS4000_3D_TIME_DELAY, 0, 0x0f);
-#if NOT_AVAILABLE
+#ifdef NOT_AVAILABLE
 static struct sbmix_elem snd_als4000_ctl_fmdac =
 	SB_SINGLE("FMDAC Switch (Option ?)", SB_ALS4000_FMDAC, 0, 0x01);
 static struct sbmix_elem snd_als4000_ctl_qsound =
@@ -723,7 +723,7 @@ static struct sbmix_elem *snd_als4000_controls[] = {
 	&snd_als4000_ctl_3d_output_ratio,
 	&snd_als4000_ctl_3d_delay,
 	&snd_als4000_ctl_3d_poweroff_switch,
-#if NOT_AVAILABLE
+#ifdef NOT_AVAILABLE
 	&snd_als4000_ctl_fmdac,
 	&snd_als4000_ctl_qsound,
 #endif
diff --git a/sound/isa/wavefront/wavefront_fx.c b/sound/isa/wavefront/wavefront_fx.c
index 0e13623f69f..32379688eed 100644
--- a/sound/isa/wavefront/wavefront_fx.c
+++ b/sound/isa/wavefront/wavefront_fx.c
@@ -34,7 +34,7 @@
 
 /* weird stuff, derived from port I/O tracing with dosemu */
 
-unsigned char page_zero[] __initdata = {
+static unsigned char page_zero[] __initdata = {
 0x01, 0x7c, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf5, 0x00,
 0x11, 0x00, 0x20, 0x00, 0x32, 0x00, 0x40, 0x00, 0x13, 0x00, 0x00,
 0x00, 0x14, 0x02, 0x76, 0x00, 0x60, 0x00, 0x80, 0x02, 0x00, 0x00,
@@ -61,7 +61,7 @@ unsigned char page_zero[] __initdata = {
 0x1d, 0x02, 0xdf
 };
 
-unsigned char page_one[] __initdata = {
+static unsigned char page_one[] __initdata = {
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x19, 0x00,
 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xd8, 0x00, 0x00,
 0x02, 0x20, 0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x01,
@@ -88,7 +88,7 @@ unsigned char page_one[] __initdata = {
 0x60, 0x00, 0x1b
 };
 
-unsigned char page_two[] __initdata = {
+static unsigned char page_two[] __initdata = {
 0xc4, 0x00, 0x44, 0x07, 0x44, 0x00, 0x40, 0x25, 0x01, 0x06, 0xc4,
 0x07, 0x40, 0x25, 0x01, 0x00, 0x46, 0x46, 0x00, 0x00, 0x00, 0x00,
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -103,7 +103,7 @@ unsigned char page_two[] __initdata = {
 0x46, 0x05, 0x46, 0x07, 0x46, 0x07, 0x44
 };
 
-unsigned char page_three[] __initdata = {
+static unsigned char page_three[] __initdata = {
 0x07, 0x40, 0x00, 0x00, 0x00, 0x47, 0x00, 0x40, 0x00, 0x40, 0x06,
 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -118,7 +118,7 @@ unsigned char page_three[] __initdata = {
 0x02, 0x00, 0x42, 0x00, 0xc0, 0x00, 0x40
 };
 
-unsigned char page_four[] __initdata = {
+static unsigned char page_four[] __initdata = {
 0x63, 0x03, 0x26, 0x02, 0x2c, 0x00, 0x24, 0x00, 0x2e, 0x02, 0x02,
 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -133,7 +133,7 @@ unsigned char page_four[] __initdata = {
 0x02, 0x62, 0x02, 0x20, 0x01, 0x21, 0x01
 };
 
-unsigned char page_six[] __initdata = {
+static unsigned char page_six[] __initdata = {
 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x04, 0x00, 0x00, 0x06, 0x00,
 0x00, 0x08, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x0e,
 0x00, 0x00, 0x10, 0x00, 0x00, 0x12, 0x00, 0x00, 0x14, 0x00, 0x00,
@@ -154,7 +154,7 @@ unsigned char page_six[] __initdata = {
 0x80, 0x00, 0x7e, 0x80, 0x80
 };
 
-unsigned char page_seven[] __initdata = {
+static unsigned char page_seven[] __initdata = {
 0x0f, 0xff, 0x00, 0x00, 0x08, 0x00, 0x08, 0x00, 0x02, 0x00, 0x00,
 0x00, 0x00, 0x00, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00,
 0x08, 0x00, 0x00, 0x00, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x0f,
@@ -181,7 +181,7 @@ unsigned char page_seven[] __initdata = {
 0x00, 0x02, 0x00
 };
 
-unsigned char page_zero_v2[] __initdata = {
+static unsigned char page_zero_v2[] __initdata = {
 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -193,7 +193,7 @@ unsigned char page_zero_v2[] __initdata = {
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 };
 
-unsigned char page_one_v2[] __initdata = {
+static unsigned char page_one_v2[] __initdata = {
 0x01, 0xc0, 0x01, 0xfa, 0x00, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x00,
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -205,21 +205,21 @@ unsigned char page_one_v2[] __initdata = {
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 };
 
-unsigned char page_two_v2[] __initdata = {
+static unsigned char page_two_v2[] __initdata = {
 0x46, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 0x00, 0x00, 0x00, 0x00
 };
-unsigned char page_three_v2[] __initdata = {
+static unsigned char page_three_v2[] __initdata = {
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 0x00, 0x00, 0x00, 0x00
 };
-unsigned char page_four_v2[] __initdata = {
+static unsigned char page_four_v2[] __initdata = {
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -227,7 +227,7 @@ unsigned char page_four_v2[] __initdata = {
 0x00, 0x00, 0x00, 0x00
 };
 
-unsigned char page_seven_v2[] __initdata = {
+static unsigned char page_seven_v2[] __initdata = {
 0x0f, 0xff, 0x0f, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -239,7 +239,7 @@ unsigned char page_seven_v2[] __initdata = {
 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 };
 
-unsigned char mod_v2[] __initdata = {
+static unsigned char mod_v2[] __initdata = {
 0x01, 0x00, 0x02, 0x00, 0x01, 0x01, 0x02, 0x00, 0x01, 0x02, 0x02,
 0x00, 0x01, 0x03, 0x02, 0x00, 0x01, 0x04, 0x02, 0x00, 0x01, 0x05,
 0x02, 0x00, 0x01, 0x06, 0x02, 0x00, 0x01, 0x07, 0x02, 0x00, 0xb0,
@@ -269,7 +269,7 @@ unsigned char mod_v2[] __initdata = {
 0x02, 0x01, 0x01, 0x04, 0x02, 0x01, 0x01, 0x05, 0x02, 0x01, 0x01,
 0x06, 0x02, 0x01, 0x01, 0x07, 0x02, 0x01
 };
-unsigned char coefficients[] __initdata = {
+static unsigned char coefficients[] __initdata = {
 0x07, 0x46, 0x00, 0x00, 0x07, 0x49, 0x00, 0x00, 0x00, 0x4b, 0x03,
 0x11, 0x00, 0x4d, 0x01, 0x32, 0x07, 0x46, 0x00, 0x00, 0x07, 0x49,
 0x00, 0x00, 0x07, 0x40, 0x00, 0x00, 0x07, 0x41, 0x00, 0x00, 0x01,
@@ -305,14 +305,14 @@ unsigned char coefficients[] __initdata = {
 0x06, 0x6c, 0x4c, 0x6c, 0x06, 0x50, 0x52, 0xe2, 0x06, 0x42, 0x02,
 0xba
 };
-unsigned char coefficients2[] __initdata = {
+static unsigned char coefficients2[] __initdata = {
 0x07, 0x46, 0x00, 0x00, 0x07, 0x49, 0x00, 0x00, 0x07, 0x45, 0x0f,
 0xff, 0x07, 0x48, 0x0f, 0xff, 0x07, 0x7b, 0x04, 0xcc, 0x07, 0x7d,
 0x04, 0xcc, 0x07, 0x7c, 0x00, 0x00, 0x07, 0x7e, 0x00, 0x00, 0x07,
 0x46, 0x00, 0x00, 0x07, 0x49, 0x00, 0x00, 0x07, 0x47, 0x00, 0x00,
 0x07, 0x4a, 0x00, 0x00, 0x07, 0x4c, 0x00, 0x00, 0x07, 0x4e, 0x00, 0x00
 };
-unsigned char coefficients3[] __initdata = {
+static unsigned char coefficients3[] __initdata = {
 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x00, 0x28, 0x00, 0x51, 0x00,
 0x51, 0x00, 0x7a, 0x00, 0x7a, 0x00, 0xa3, 0x00, 0xa3, 0x00, 0xcc,
 0x00, 0xcc, 0x00, 0xf5, 0x00, 0xf5, 0x01, 0x1e, 0x01, 0x1e, 0x01,
diff --git a/sound/oss/dmasound/dmasound_awacs.c b/sound/oss/dmasound/dmasound_awacs.c
index 2704e1598ad..2ceb46f1d40 100644
--- a/sound/oss/dmasound/dmasound_awacs.c
+++ b/sound/oss/dmasound/dmasound_awacs.c
@@ -1557,7 +1557,7 @@ static int awacs_sleep_notify(struct pmu_sleep_notifier *self, int when)
 /* All the burgundy functions: */
 
 /* Waits for busy flag to clear */
-inline static void
+static inline void
 awacs_burgundy_busy_wait(void)
 {
 	int count = 50; /* > 2 samples at 44k1 */
@@ -1565,7 +1565,7 @@ awacs_burgundy_busy_wait(void)
 		udelay(1) ;
 }
 
-inline static void
+static inline void
 awacs_burgundy_extend_wait(void)
 {
 	int count = 50 ; /* > 2 samples at 44k1 */
diff --git a/sound/oss/pss.c b/sound/oss/pss.c
index 3ed38765dcc..a617ccb40e0 100644
--- a/sound/oss/pss.c
+++ b/sound/oss/pss.c
@@ -714,7 +714,7 @@ static int __init attach_pss(struct address_info *hw_config)
 	 
 	disable_all_emulations();
 
-#if YOU_REALLY_WANT_TO_ALLOCATE_THESE_RESOURCES
+#ifdef YOU_REALLY_WANT_TO_ALLOCATE_THESE_RESOURCES
 	if (sound_alloc_dma(hw_config->dma, "PSS"))
 	{
 		printk("pss.c: Can't allocate DMA channel.\n");
diff --git a/sound/pci/ac97/ac97_codec.c b/sound/pci/ac97/ac97_codec.c
index a4b72cd2eea..6983eea226d 100644
--- a/sound/pci/ac97/ac97_codec.c
+++ b/sound/pci/ac97/ac97_codec.c
@@ -367,6 +367,7 @@ int snd_ac97_update(ac97_t *ac97, unsigned short reg, unsigned short value)
 		ac97->regs[reg] = value;
 		ac97->bus->ops->write(ac97, reg, value);
 	}
+	set_bit(reg, ac97->reg_accessed);
 	up(&ac97->reg_mutex);
 	return change;
 }
@@ -410,6 +411,7 @@ int snd_ac97_update_bits_nolock(ac97_t *ac97, unsigned short reg,
 		ac97->regs[reg] = new;
 		ac97->bus->ops->write(ac97, reg, new);
 	}
+	set_bit(reg, ac97->reg_accessed);
 	return change;
 }
 
@@ -1076,6 +1078,11 @@ static void check_volume_resolution(ac97_t *ac97, int reg, unsigned char *lo_max
 	for (i = 0 ; i < ARRAY_SIZE(cbit); i++) {
 		unsigned short val;
 		snd_ac97_write(ac97, reg, 0x8080 | cbit[i] | (cbit[i] << 8));
+		/* Do the read twice due to buffers on some ac97 codecs.
+		 * e.g. The STAC9704 returns exactly what you wrote the the register
+		 * if you read it immediately. This causes the detect routine to fail.
+		 */
+		val = snd_ac97_read(ac97, reg);
 		val = snd_ac97_read(ac97, reg);
 		if (! *lo_max && (val & 0x7f) == cbit[i])
 			*lo_max = max[i];
@@ -2224,7 +2231,7 @@ void snd_ac97_restore_iec958(ac97_t *ac97)
  */
 void snd_ac97_resume(ac97_t *ac97)
 {
-	int i;
+	unsigned long end_time;
 
 	if (ac97->bus->ops->reset) {
 		ac97->bus->ops->reset(ac97);
@@ -2242,26 +2249,26 @@ void snd_ac97_resume(ac97_t *ac97)
 	snd_ac97_write(ac97, AC97_POWERDOWN, ac97->regs[AC97_POWERDOWN]);
 	if (ac97_is_audio(ac97)) {
 		ac97->bus->ops->write(ac97, AC97_MASTER, 0x8101);
-		for (i = HZ/10; i >= 0; i--) {
+		end_time = jiffies + msecs_to_jiffies(100);
+		do {
 			if (snd_ac97_read(ac97, AC97_MASTER) == 0x8101)
 				break;
 			set_current_state(TASK_UNINTERRUPTIBLE);
 			schedule_timeout(1);
-		}
+		} while (time_after_eq(end_time, jiffies));
 		/* FIXME: extra delay */
 		ac97->bus->ops->write(ac97, AC97_MASTER, 0x8000);
-		if (snd_ac97_read(ac97, AC97_MASTER) != 0x8000) {
-			set_current_state(TASK_UNINTERRUPTIBLE);
-			schedule_timeout(HZ/4);
-		}
+		if (snd_ac97_read(ac97, AC97_MASTER) != 0x8000)
+			msleep(250);
 	} else {
-		for (i = HZ/10; i >= 0; i--) {
+		end_time = jiffies + msecs_to_jiffies(100);
+		do {
 			unsigned short val = snd_ac97_read(ac97, AC97_EXTENDED_MID);
 			if (val != 0xffff && (val & 1) != 0)
 				break;
 			set_current_state(TASK_UNINTERRUPTIBLE);
 			schedule_timeout(1);
-		}
+		} while (time_after_eq(end_time, jiffies));
 	}
 __reset_ready:
 
diff --git a/sound/pci/ac97/ac97_patch.c b/sound/pci/ac97/ac97_patch.c
index a15eb8522b7..66edc857d3e 100644
--- a/sound/pci/ac97/ac97_patch.c
+++ b/sound/pci/ac97/ac97_patch.c
@@ -1528,6 +1528,9 @@ static const snd_kcontrol_new_t snd_ac97_ad1888_controls[] = {
 	},
 	AC97_SURROUND_JACK_MODE_CTL,
 	AC97_CHANNEL_MODE_CTL,
+
+	AC97_SINGLE("Headphone Jack Sense", AC97_AD_JACK_SPDIF, 10, 1, 0),
+	AC97_SINGLE("Line Jack Sense", AC97_AD_JACK_SPDIF, 12, 1, 0),
 };
 
 static int patch_ad1888_specific(ac97_t *ac97)
diff --git a/sound/pci/ali5451/ali5451.c b/sound/pci/ali5451/ali5451.c
index eb5c36d31a5..f08ae71f902 100644
--- a/sound/pci/ali5451/ali5451.c
+++ b/sound/pci/ali5451/ali5451.c
@@ -399,7 +399,7 @@ static int snd_ali_codec_ready(	ali_t *codec,
 	unsigned long end_time;
 	unsigned int res;
 	
-	end_time = jiffies + 10 * (HZ >> 2);
+	end_time = jiffies + 10 * msecs_to_jiffies(250);
 	do {
 		res = snd_ali_5451_peek(codec,port);
 		if (! (res & 0x8000))
@@ -422,7 +422,7 @@ static int snd_ali_stimer_ready(ali_t *codec, int sched)
 	dwChk1 = snd_ali_5451_peek(codec, ALI_STIMER);
 	dwChk2 = snd_ali_5451_peek(codec, ALI_STIMER);
 
-	end_time = jiffies + 10 * (HZ >> 2);
+	end_time = jiffies + 10 * msecs_to_jiffies(250);
 	do {
 		dwChk2 = snd_ali_5451_peek(codec, ALI_STIMER);
 		if (dwChk2 != dwChk1)
diff --git a/sound/pci/atiixp_modem.c b/sound/pci/atiixp_modem.c
index a6b4b8d589f..8d2002951bd 100644
--- a/sound/pci/atiixp_modem.c
+++ b/sound/pci/atiixp_modem.c
@@ -265,6 +265,7 @@ struct snd_atiixp {
  */
 static struct pci_device_id snd_atiixp_ids[] = {
 	{ 0x1002, 0x434d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB200 */
+	{ 0x1002, 0x4378, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB400 */
 	{ 0, }
 };
 
diff --git a/sound/pci/cmipci.c b/sound/pci/cmipci.c
index b4503385ea6..f5a4ac1ceef 100644
--- a/sound/pci/cmipci.c
+++ b/sound/pci/cmipci.c
@@ -306,7 +306,7 @@ MODULE_PARM_DESC(joystick_port, "Joystick port address.");
 #define CM_REG_FM_PCI		0x50
 
 /*
- * for CMI-8338 .. this is not valid for CMI-8738.
+ * access from SB-mixer port
  */
 #define CM_REG_EXTENT_IND	0xf0
 #define CM_VPHONE_MASK		0xe0	/* Phone volume control (0-3) << 5 */
@@ -315,6 +315,7 @@ MODULE_PARM_DESC(joystick_port, "Joystick port address.");
 #define CM_VSPKM		0x08	/* Speaker mute control, default high */
 #define CM_RLOOPREN		0x04    /* Rec. R-channel enable */
 #define CM_RLOOPLEN		0x02	/* Rec. L-channel enable */
+#define CM_VADMIC3		0x01	/* Mic record boost */
 
 /*
  * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
@@ -488,32 +489,34 @@ struct snd_stru_cmipci {
 
 
 /* read/write operations for dword register */
-inline static void snd_cmipci_write(cmipci_t *cm, unsigned int cmd, unsigned int data)
+static inline void snd_cmipci_write(cmipci_t *cm, unsigned int cmd, unsigned int data)
 {
 	outl(data, cm->iobase + cmd);
 }
-inline static unsigned int snd_cmipci_read(cmipci_t *cm, unsigned int cmd)
+
+static inline unsigned int snd_cmipci_read(cmipci_t *cm, unsigned int cmd)
 {
 	return inl(cm->iobase + cmd);
 }
 
 /* read/write operations for word register */
-inline static void snd_cmipci_write_w(cmipci_t *cm, unsigned int cmd, unsigned short data)
+static inline void snd_cmipci_write_w(cmipci_t *cm, unsigned int cmd, unsigned short data)
 {
 	outw(data, cm->iobase + cmd);
 }
-inline static unsigned short snd_cmipci_read_w(cmipci_t *cm, unsigned int cmd)
+
+static inline unsigned short snd_cmipci_read_w(cmipci_t *cm, unsigned int cmd)
 {
 	return inw(cm->iobase + cmd);
 }
 
 /* read/write operations for byte register */
-inline static void snd_cmipci_write_b(cmipci_t *cm, unsigned int cmd, unsigned char data)
+static inline void snd_cmipci_write_b(cmipci_t *cm, unsigned int cmd, unsigned char data)
 {
 	outb(data, cm->iobase + cmd);
 }
 
-inline static unsigned char snd_cmipci_read_b(cmipci_t *cm, unsigned int cmd)
+static inline unsigned char snd_cmipci_read_b(cmipci_t *cm, unsigned int cmd)
 {
 	return inb(cm->iobase + cmd);
 }
@@ -2133,8 +2136,12 @@ static snd_kcontrol_new_t snd_cmipci_mixers[] __devinitdata = {
 	CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
 	CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
 	CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
-	CMIPCI_MIXER_SW_MONO("Mic Boost", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
+	CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
 	CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
+	CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
+	CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
+	CMIPCI_DOUBLE("PC Speaker Playnack Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
+	CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
 };
 
 /*
diff --git a/sound/pci/cs4281.c b/sound/pci/cs4281.c
index eb3c52b03af..c7a370d4f92 100644
--- a/sound/pci/cs4281.c
+++ b/sound/pci/cs4281.c
@@ -542,7 +542,7 @@ static void snd_cs4281_delay(unsigned int delay)
 	}
 }
 
-inline static void snd_cs4281_delay_long(void)
+static inline void snd_cs4281_delay_long(void)
 {
 	set_current_state(TASK_UNINTERRUPTIBLE);
 	schedule_timeout(1);
diff --git a/sound/pci/cs46xx/cs46xx_lib.c b/sound/pci/cs46xx/cs46xx_lib.c
index fd4c50c88bc..ff28af1f658 100644
--- a/sound/pci/cs46xx/cs46xx_lib.c
+++ b/sound/pci/cs46xx/cs46xx_lib.c
@@ -2400,8 +2400,7 @@ static void snd_cs46xx_codec_reset (ac97_t * ac97)
 		if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
 			return;
 
-		set_current_state(TASK_UNINTERRUPTIBLE);
-		schedule_timeout(HZ/100);
+		msleep(10);
 	} while (time_after_eq(end_time, jiffies));
 
 	snd_printk("CS46xx secondary codec dont respond!\n");  
@@ -2435,8 +2434,7 @@ static int __devinit cs46xx_detect_codec(cs46xx_t *chip, int codec)
 			err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
 			return err;
 		}
-		set_current_state(TASK_INTERRUPTIBLE);
-		schedule_timeout(HZ/100);
+		msleep(10);
 	}
 	snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec);
 	return -ENXIO;
@@ -3018,8 +3016,7 @@ static int snd_cs46xx_chip_init(cs46xx_t *chip)
 	/*
          *  Wait until the PLL has stabilized.
 	 */
-	set_current_state(TASK_UNINTERRUPTIBLE);
-	schedule_timeout(HZ/10); /* 100ms */
+	msleep(100);
 
 	/*
 	 *  Turn on clocking of the core so that we can setup the serial ports.
@@ -3072,8 +3069,7 @@ static int snd_cs46xx_chip_init(cs46xx_t *chip)
 		 */
 		if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
 			goto ok1;
-		set_current_state(TASK_UNINTERRUPTIBLE);
-		schedule_timeout((HZ+99)/100);
+		msleep(10);
 	}
 
 
@@ -3122,8 +3118,7 @@ static int snd_cs46xx_chip_init(cs46xx_t *chip)
 		 */
 		if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
 			goto ok2;
-		set_current_state(TASK_UNINTERRUPTIBLE);
-		schedule_timeout((HZ+99)/100);
+		msleep(10);
 	}
 
 #ifndef CONFIG_SND_CS46XX_NEW_DSP
diff --git a/sound/pci/emu10k1/emu10k1.c b/sound/pci/emu10k1/emu10k1.c
index 2085a998eae..b17142cabea 100644
--- a/sound/pci/emu10k1/emu10k1.c
+++ b/sound/pci/emu10k1/emu10k1.c
@@ -52,6 +52,7 @@ static int seq_ports[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4};
 static int max_synth_voices[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 64};
 static int max_buffer_size[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 128};
 static int enable_ir[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
+static uint subsystem[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0}; /* Force card subsystem model */
 
 module_param_array(index, int, NULL, 0444);
 MODULE_PARM_DESC(index, "Index value for the EMU10K1 soundcard.");
@@ -71,7 +72,8 @@ module_param_array(max_buffer_size, int, NULL, 0444);
 MODULE_PARM_DESC(max_buffer_size, "Maximum sample buffer size in MB.");
 module_param_array(enable_ir, bool, NULL, 0444);
 MODULE_PARM_DESC(enable_ir, "Enable IR.");
-
+module_param_array(subsystem, uint, NULL, 0444);
+MODULE_PARM_DESC(subsystem, "Force card subsystem model.");
 /*
  * Class 0401: 1102:0008 (rev 00) Subsystem: 1102:1001 -> Audigy2 Value  Model:SB0400
  */
@@ -122,7 +124,7 @@ static int __devinit snd_card_emu10k1_probe(struct pci_dev *pci,
 		max_buffer_size[dev] = 1024;
 	if ((err = snd_emu10k1_create(card, pci, extin[dev], extout[dev],
 				      (long)max_buffer_size[dev] * 1024 * 1024,
-				      enable_ir[dev],
+				      enable_ir[dev], subsystem[dev],
 				      &emu)) < 0) {
 		snd_card_free(card);
 		return err;
@@ -140,7 +142,7 @@ static int __devinit snd_card_emu10k1_probe(struct pci_dev *pci,
 		return err;
 	}
 	/* This stores the periods table. */
-	if (emu->audigy && emu->revision == 4) { /* P16V */	
+	if (emu->card_capabilities->ca0151_chip) { /* P16V */	
 		if(snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 1024, &emu->p16v_buffer) < 0) {
 			snd_p16v_free(emu);
 			return -ENOMEM;
@@ -161,7 +163,7 @@ static int __devinit snd_card_emu10k1_probe(struct pci_dev *pci,
 		snd_card_free(card);
 		return err;
 	}
-	if (emu->audigy && emu->revision == 4) { /* P16V */	
+	if (emu->card_capabilities->ca0151_chip) { /* P16V */	
 		if ((err = snd_p16v_pcm(emu, 4, NULL)) < 0) {
 			snd_card_free(card);
 			return err;
diff --git a/sound/pci/emu10k1/emu10k1_main.c b/sound/pci/emu10k1/emu10k1_main.c
index a341e758acd..746b51ef396 100644
--- a/sound/pci/emu10k1/emu10k1_main.c
+++ b/sound/pci/emu10k1/emu10k1_main.c
@@ -191,7 +191,7 @@ static int __devinit snd_emu10k1_init(emu10k1_t * emu, int enable_ir)
 		/* Set playback routing. */
 		snd_emu10k1_ptr20_write(emu, CAPTURE_P16V_SOURCE, 0, 0x78e4);
 	}
-	if (emu->audigy && (emu->serial == 0x10011102) ) { /* audigy2 Value */
+	if (emu->card_capabilities->ca0108_chip) { /* audigy2 Value */
 		/* Hacks for Alice3 to work independent of haP16V driver */
 		u32 tmp;
 
@@ -253,6 +253,8 @@ static int __devinit snd_emu10k1_init(emu10k1_t * emu, int enable_ir)
 			     HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
 		else
 			outl(HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
+	/* FIXME: Remove all these emu->model and replace it with a card recognition parameter,
+	 * e.g. card_capabilities->joystick */
 	} else if (emu->model == 0x20 ||
 	    emu->model == 0xc400 ||
 	    (emu->model == 0x21 && emu->revision < 6))
@@ -299,12 +301,12 @@ static int __devinit snd_emu10k1_init(emu10k1_t * emu, int enable_ir)
 	if (emu->audigy) {
 		outl(inl(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG);
  
-		if (emu->revision == 4) { /* audigy2 */
+		if (emu->card_capabilities->ca0151_chip) { /* audigy2 */
 			/* Unmute Analog now.  Set GPO6 to 1 for Apollo.
 			 * This has to be done after init ALice3 I2SOut beyond 48KHz.
 			 * So, sequence is important. */
 			outl(inl(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG);
-		} else if (emu->serial == 0x10011102) { /* audigy2 value */
+		} else if (emu->card_capabilities->ca0108_chip) { /* audigy2 value */
 			/* Unmute Analog now. */
 			outl(inl(emu->port + A_IOCFG) | 0x0060, emu->port + A_IOCFG);
 		} else {
@@ -614,6 +616,7 @@ static int snd_emu10k1_dev_free(snd_device_t *device)
 
 static emu_chip_details_t emu_chip_details[] = {
 	/* Audigy 2 Value AC3 out does not work yet. Need to find out how to turn off interpolators.*/
+	/* Tested by James@superbug.co.uk 3rd July 2005 */
 	{.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10011102,
 	 .driver = "Audigy2", .name = "Audigy 2 Value [SB0400]", 
 	 .id = "Audigy2",
@@ -627,6 +630,14 @@ static emu_chip_details_t emu_chip_details[] = {
 	 .emu10k2_chip = 1,
 	 .ca0108_chip = 1,
 	 .ac97_chip = 1} ,
+	/* Tested by James@superbug.co.uk 8th July 2005. No sound available yet. */
+	{.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40011102,
+	 .driver = "Audigy2", .name = "E-mu 1212m [4001]", 
+	 .id = "EMU1212m",
+	 .emu10k2_chip = 1,
+	 .ca0102_chip = 1,
+	 .ecard = 1} ,
+	/* Tested by James@superbug.co.uk 3rd July 2005 */
 	{.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20071102,
 	 .driver = "Audigy2", .name = "Audigy 4 PRO [SB0380]", 
 	 .id = "Audigy2",
@@ -687,18 +698,18 @@ static emu_chip_details_t emu_chip_details[] = {
 	 .ca0151_chip = 1,
 	 .spdif_bug = 1,
 	 .ac97_chip = 1} ,
-	{.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10020052,
-	 .driver = "Audigy", .name = "Audigy 1 ES [SB0160]", 
+	{.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00531102,
+	 .driver = "Audigy", .name = "Audigy 1 [SB0090]", 
 	 .id = "Audigy",
 	 .emu10k2_chip = 1,
 	 .ca0102_chip = 1,
-	 .spdif_bug = 1,
 	 .ac97_chip = 1} ,
-	{.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00531102,
-	 .driver = "Audigy", .name = "Audigy 1 [SB0090]", 
+	{.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00521102,
+	 .driver = "Audigy", .name = "Audigy 1 ES [SB0160]", 
 	 .id = "Audigy",
 	 .emu10k2_chip = 1,
 	 .ca0102_chip = 1,
+	 .spdif_bug = 1,
 	 .ac97_chip = 1} ,
 	{.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00511102,
 	 .driver = "Audigy", .name = "Audigy 1 [SB0090]", 
@@ -712,54 +723,49 @@ static emu_chip_details_t emu_chip_details[] = {
 	 .emu10k2_chip = 1,
 	 .ca0102_chip = 1,
 	 .ac97_chip = 1} ,
-	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x40011102,
-	 .driver = "EMU10K1", .name = "E-mu APS [4001]", 
-	 .id = "APS",
-	 .emu10k1_chip = 1,
-	 .ecard = 1} ,
-	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80611102,
-	 .driver = "EMU10K1", .name = "SBLive! Player 5.1 [SB0060]", 
+	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806B1102,
+	 .driver = "EMU10K1", .name = "SBLive! [SB0105]", 
 	 .id = "Live",
 	 .emu10k1_chip = 1,
 	 .ac97_chip = 1,
 	 .sblive51 = 1} ,
-	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80641102,
-	 .driver = "EMU10K1", .name = "SB Live 5.1", 
+	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806A1102,
+	 .driver = "EMU10K1", .name = "SBLive! Value [SB0103]", 
 	 .id = "Live",
 	 .emu10k1_chip = 1,
 	 .ac97_chip = 1,
 	 .sblive51 = 1} ,
-	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80401102,
-	 .driver = "EMU10K1", .name = "SBLive! Platinum [CT4760P]", 
-	 .id = "Live",
-	 .emu10k1_chip = 1,
-	 .ac97_chip = 1} ,
-	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00211102,
-	 .driver = "EMU10K1", .name = "SBLive! [CT4620]", 
+	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80691102,
+	 .driver = "EMU10K1", .name = "SBLive! Value [SB0101]", 
 	 .id = "Live",
 	 .emu10k1_chip = 1,
 	 .ac97_chip = 1,
 	 .sblive51 = 1} ,
-	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00201102,
-	 .driver = "EMU10K1", .name = "SBLive! Value [CT4670]", 
+	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80641102,
+	 .driver = "EMU10K1", .name = "SB Live 5.1", 
 	 .id = "Live",
 	 .emu10k1_chip = 1,
 	 .ac97_chip = 1,
 	 .sblive51 = 1} ,
-	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80221102,
-	 .driver = "EMU10K1", .name = "SBLive! Value [CT4780]", 
+	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80611102,
+	 .driver = "EMU10K1", .name = "SBLive! Player 5.1 [SB0060]", 
 	 .id = "Live",
 	 .emu10k1_chip = 1,
 	 .ac97_chip = 1,
 	 .sblive51 = 1} ,
-	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80231102,
-	 .driver = "EMU10K1", .name = "SB PCI512 [CT4790]", 
+	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80511102,
+	 .driver = "EMU10K1", .name = "SBLive! Value [CT4850]", 
 	 .id = "Live",
 	 .emu10k1_chip = 1,
 	 .ac97_chip = 1,
 	 .sblive51 = 1} ,
-	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80261102,
-	 .driver = "EMU10K1", .name = "SBLive! Value [CT4830]", 
+	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80401102,
+	 .driver = "EMU10K1", .name = "SBLive! Platinum [CT4760P]", 
+	 .id = "Live",
+	 .emu10k1_chip = 1,
+	 .ac97_chip = 1} ,
+	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80321102,
+	 .driver = "EMU10K1", .name = "SBLive! Value [CT4871]", 
 	 .id = "Live",
 	 .emu10k1_chip = 1,
 	 .ac97_chip = 1,
@@ -770,50 +776,50 @@ static emu_chip_details_t emu_chip_details[] = {
 	 .emu10k1_chip = 1,
 	 .ac97_chip = 1,
 	 .sblive51 = 1} ,
-	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80271102,
-	 .driver = "EMU10K1", .name = "SBLive! Value [CT4832]", 
+	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80281102,
+	 .driver = "EMU10K1", .name = "SBLive! Value [CT4870]", 
 	 .id = "Live",
 	 .emu10k1_chip = 1,
 	 .ac97_chip = 1,
 	 .sblive51 = 1} ,
-	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80511102,
-	 .driver = "EMU10K1", .name = "SBLive! Value [CT4850]", 
+	/* Tested by James@superbug.co.uk 3rd July 2005 */
+	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80271102,
+	 .driver = "EMU10K1", .name = "SBLive! Value [CT4832]", 
 	 .id = "Live",
 	 .emu10k1_chip = 1,
 	 .ac97_chip = 1,
 	 .sblive51 = 1} ,
-	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80281102,
-	 .driver = "EMU10K1", .name = "SBLive! Value [CT4870]", 
+	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80261102,
+	 .driver = "EMU10K1", .name = "SBLive! Value [CT4830]", 
 	 .id = "Live",
 	 .emu10k1_chip = 1,
 	 .ac97_chip = 1,
 	 .sblive51 = 1} ,
-	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80321102,
-	 .driver = "EMU10K1", .name = "SBLive! Value [CT4871]", 
+	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80231102,
+	 .driver = "EMU10K1", .name = "SB PCI512 [CT4790]", 
 	 .id = "Live",
 	 .emu10k1_chip = 1,
 	 .ac97_chip = 1,
 	 .sblive51 = 1} ,
-	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80611102,
-	 .driver = "EMU10K1", .name = "SBLive! Value [SB0060]", 
+	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80221102,
+	 .driver = "EMU10K1", .name = "SBLive! Value [CT4780]", 
 	 .id = "Live",
 	 .emu10k1_chip = 1,
 	 .ac97_chip = 1,
 	 .sblive51 = 1} ,
-	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80691102,
-	 .driver = "EMU10K1", .name = "SBLive! Value [SB0101]", 
-	 .id = "Live",
+	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x40011102,
+	 .driver = "EMU10K1", .name = "E-mu APS [4001]", 
+	 .id = "APS",
 	 .emu10k1_chip = 1,
-	 .ac97_chip = 1,
-	 .sblive51 = 1} ,
-	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806A1102,
-	 .driver = "EMU10K1", .name = "SBLive! Value [SB0103]", 
+	 .ecard = 1} ,
+	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00211102,
+	 .driver = "EMU10K1", .name = "SBLive! [CT4620]", 
 	 .id = "Live",
 	 .emu10k1_chip = 1,
 	 .ac97_chip = 1,
 	 .sblive51 = 1} ,
-	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806B1102,
-	 .driver = "EMU10K1", .name = "SBLive! [SB0105]", 
+	{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00201102,
+	 .driver = "EMU10K1", .name = "SBLive! Value [CT4670]", 
 	 .id = "Live",
 	 .emu10k1_chip = 1,
 	 .ac97_chip = 1,
@@ -833,6 +839,7 @@ int __devinit snd_emu10k1_create(snd_card_t * card,
 		       unsigned short extout_mask,
 		       long max_cache_bytes,
 		       int enable_ir,
+		       uint subsystem,
 		       emu10k1_t ** remu)
 {
 	emu10k1_t *emu;
@@ -878,10 +885,16 @@ int __devinit snd_emu10k1_create(snd_card_t * card,
 
 	for (c = emu_chip_details; c->vendor; c++) {
 		if (c->vendor == pci->vendor && c->device == pci->device) {
-			if (c->subsystem && c->subsystem != emu->serial)
-				continue;
-			if (c->revision && c->revision != emu->revision)
-				continue;
+			if (subsystem) {
+				if (c->subsystem && (c->subsystem == subsystem) ) {
+					break;
+				} else continue;
+			} else {
+				if (c->subsystem && (c->subsystem != emu->serial) )
+					continue;
+				if (c->revision && c->revision != emu->revision)
+					continue;
+			}
 			break;
 		}
 	}
@@ -892,10 +905,14 @@ int __devinit snd_emu10k1_create(snd_card_t * card,
 		return -ENOENT;
 	}
 	emu->card_capabilities = c;
-	if (c->subsystem != 0)
+	if (c->subsystem && !subsystem)
 		snd_printdd("Sound card name=%s\n", c->name);
-	else
-		snd_printdd("Sound card name=%s, vendor=0x%x, device=0x%x, subsystem=0x%x\n", c->name, pci->vendor, pci->device, emu->serial);
+	else if (subsystem) 
+		snd_printdd("Sound card name=%s, vendor=0x%x, device=0x%x, subsystem=0x%x. Forced to subsytem=0x%x\n",
+		       	c->name, pci->vendor, pci->device, emu->serial, c->subsystem);
+	else 
+		snd_printdd("Sound card name=%s, vendor=0x%x, device=0x%x, subsystem=0x%x.\n",
+		      	c->name, pci->vendor, pci->device, emu->serial);
 	
 	if (!*card->id && c->id) {
 		int i, n = 0;
diff --git a/sound/pci/emu10k1/memory.c b/sound/pci/emu10k1/memory.c
index 7a595f0dd7a..6afeaeab3e1 100644
--- a/sound/pci/emu10k1/memory.c
+++ b/sound/pci/emu10k1/memory.c
@@ -495,7 +495,7 @@ static int synth_free_pages(emu10k1_t *emu, emu10k1_memblk_t *blk)
 }
 
 /* calculate buffer pointer from offset address */
-inline static void *offset_ptr(emu10k1_t *emu, int page, int offset)
+static inline void *offset_ptr(emu10k1_t *emu, int page, int offset)
 {
 	char *ptr;
 	snd_assert(page >= 0 && page < emu->max_cache_pages, return NULL);
diff --git a/sound/pci/emu10k1/p16v.c b/sound/pci/emu10k1/p16v.c
index 98f98018989..a1691330d3b 100644
--- a/sound/pci/emu10k1/p16v.c
+++ b/sound/pci/emu10k1/p16v.c
@@ -822,7 +822,7 @@ static int snd_p16v_volume_put_analog_unknown(snd_kcontrol_t * kcontrol,
 static snd_kcontrol_new_t snd_p16v_volume_control_analog_front =
 {
         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
-        .name =         "HD Analog Front Volume",
+        .name =         "HD Analog Front Playback Volume",
         .info =         snd_p16v_volume_info,
         .get =          snd_p16v_volume_get_analog_front,
         .put =          snd_p16v_volume_put_analog_front
@@ -831,7 +831,7 @@ static snd_kcontrol_new_t snd_p16v_volume_control_analog_front =
 static snd_kcontrol_new_t snd_p16v_volume_control_analog_center_lfe =
 {
         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
-        .name =         "HD Analog Center/LFE Volume",
+        .name =         "HD Analog Center/LFE Playback Volume",
         .info =         snd_p16v_volume_info,
         .get =          snd_p16v_volume_get_analog_center_lfe,
         .put =          snd_p16v_volume_put_analog_center_lfe
@@ -840,7 +840,7 @@ static snd_kcontrol_new_t snd_p16v_volume_control_analog_center_lfe =
 static snd_kcontrol_new_t snd_p16v_volume_control_analog_unknown =
 {
         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
-        .name =         "HD Analog Unknown Volume",
+        .name =         "HD Analog Unknown Playback Volume",
         .info =         snd_p16v_volume_info,
         .get =          snd_p16v_volume_get_analog_unknown,
         .put =          snd_p16v_volume_put_analog_unknown
@@ -849,7 +849,7 @@ static snd_kcontrol_new_t snd_p16v_volume_control_analog_unknown =
 static snd_kcontrol_new_t snd_p16v_volume_control_analog_rear =
 {
         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
-        .name =         "HD Analog Rear Volume",
+        .name =         "HD Analog Rear Playback Volume",
         .info =         snd_p16v_volume_info,
         .get =          snd_p16v_volume_get_analog_rear,
         .put =          snd_p16v_volume_put_analog_rear
@@ -858,7 +858,7 @@ static snd_kcontrol_new_t snd_p16v_volume_control_analog_rear =
 static snd_kcontrol_new_t snd_p16v_volume_control_spdif_front =
 {
         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
-        .name =         "HD SPDIF Front Volume",
+        .name =         "HD SPDIF Front Playback Volume",
         .info =         snd_p16v_volume_info,
         .get =          snd_p16v_volume_get_spdif_front,
         .put =          snd_p16v_volume_put_spdif_front
@@ -867,7 +867,7 @@ static snd_kcontrol_new_t snd_p16v_volume_control_spdif_front =
 static snd_kcontrol_new_t snd_p16v_volume_control_spdif_center_lfe =
 {
         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
-        .name =         "HD SPDIF Center/LFE Volume",
+        .name =         "HD SPDIF Center/LFE Playback Volume",
         .info =         snd_p16v_volume_info,
         .get =          snd_p16v_volume_get_spdif_center_lfe,
         .put =          snd_p16v_volume_put_spdif_center_lfe
@@ -876,7 +876,7 @@ static snd_kcontrol_new_t snd_p16v_volume_control_spdif_center_lfe =
 static snd_kcontrol_new_t snd_p16v_volume_control_spdif_unknown =
 {
         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
-        .name =         "HD SPDIF Unknown Volume",
+        .name =         "HD SPDIF Unknown Playback Volume",
         .info =         snd_p16v_volume_info,
         .get =          snd_p16v_volume_get_spdif_unknown,
         .put =          snd_p16v_volume_put_spdif_unknown
@@ -885,7 +885,7 @@ static snd_kcontrol_new_t snd_p16v_volume_control_spdif_unknown =
 static snd_kcontrol_new_t snd_p16v_volume_control_spdif_rear =
 {
         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
-        .name =         "HD SPDIF Rear Volume",
+        .name =         "HD SPDIF Rear Playback Volume",
         .info =         snd_p16v_volume_info,
         .get =          snd_p16v_volume_get_spdif_rear,
         .put =          snd_p16v_volume_put_spdif_rear
@@ -936,7 +936,7 @@ static int snd_p16v_capture_source_put(snd_kcontrol_t * kcontrol,
 static snd_kcontrol_new_t snd_p16v_capture_source __devinitdata =
 {
 	.iface =	SNDRV_CTL_ELEM_IFACE_MIXER,
-	.name =		"HD Capture source",
+	.name =		"HD source Capture",
 	.info =		snd_p16v_capture_source_info,
 	.get =		snd_p16v_capture_source_get,
 	.put =		snd_p16v_capture_source_put
@@ -985,7 +985,7 @@ static int snd_p16v_capture_channel_put(snd_kcontrol_t * kcontrol,
 static snd_kcontrol_new_t snd_p16v_capture_channel __devinitdata =
 {
 	.iface =	SNDRV_CTL_ELEM_IFACE_MIXER,
-	.name =		"HD Capture channel",
+	.name =		"HD channel Capture",
 	.info =		snd_p16v_capture_channel_info,
 	.get =		snd_p16v_capture_channel_get,
 	.put =		snd_p16v_capture_channel_put
diff --git a/sound/pci/ens1370.c b/sound/pci/ens1370.c
index 4e63498a58b..78a81f3912a 100644
--- a/sound/pci/ens1370.c
+++ b/sound/pci/ens1370.c
@@ -685,6 +685,15 @@ static unsigned short snd_es1371_codec_read(ac97_t *ac97,
 	return 0;
 }
 
+static void snd_es1371_codec_wait(ac97_t *ac97)
+{
+	msleep(750);
+	snd_es1371_codec_read(ac97, AC97_RESET);
+	snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
+	snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
+	msleep(50);
+}
+
 static void snd_es1371_adc_rate(ensoniq_t * ensoniq, unsigned int rate)
 {
 	unsigned int n, truncm, freq, result;
@@ -1585,6 +1594,7 @@ static int snd_ensoniq_1371_mixer(ensoniq_t * ensoniq)
 	static ac97_bus_ops_t ops = {
 		.write = snd_es1371_codec_write,
 		.read = snd_es1371_codec_read,
+		.wait = snd_es1371_codec_wait,
 	};
 
 	if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
@@ -2008,21 +2018,11 @@ static int __devinit snd_ensoniq_create(snd_card_t * card,
 		if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
 		    pci->device == es1371_ac97_reset_hack[idx].did &&
 		    ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
-		        unsigned long tmo;
-			signed long tmo2;
-
 			ensoniq->cssr |= ES_1371_ST_AC97_RST;
 			outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
 			/* need to delay around 20ms(bleech) to give
 			some CODECs enough time to wakeup */
-			tmo = jiffies + (HZ / 50) + 1;
-			while (1) {
-				tmo2 = tmo - jiffies;
-				if (tmo2 <= 0)
-					break;
-				set_current_state(TASK_UNINTERRUPTIBLE);
-				schedule_timeout(tmo2);
-			}
+			msleep(20);
 			break;
 		}
 	/* AC'97 warm reset to start the bitclk */
diff --git a/sound/pci/es1968.c b/sound/pci/es1968.c
index ea889b31139..9d7a2878393 100644
--- a/sound/pci/es1968.c
+++ b/sound/pci/es1968.c
@@ -636,7 +636,7 @@ static void __maestro_write(es1968_t *chip, u16 reg, u16 data)
 	chip->maestro_map[reg] = data;
 }
 
-inline static void maestro_write(es1968_t *chip, u16 reg, u16 data)
+static inline void maestro_write(es1968_t *chip, u16 reg, u16 data)
 {
 	unsigned long flags;
 	spin_lock_irqsave(&chip->reg_lock, flags);
@@ -654,7 +654,7 @@ static u16 __maestro_read(es1968_t *chip, u16 reg)
 	return chip->maestro_map[reg];
 }
 
-inline static u16 maestro_read(es1968_t *chip, u16 reg)
+static inline u16 maestro_read(es1968_t *chip, u16 reg)
 {
 	unsigned long flags;
 	u16 result;
@@ -664,11 +664,6 @@ inline static u16 maestro_read(es1968_t *chip, u16 reg)
 	return result;
 }
 
-#define big_mdelay(msec) do {\
-	set_current_state(TASK_UNINTERRUPTIBLE);\
-	schedule_timeout(((msec) * HZ + 999) / 1000);\
-} while (0)
-	
 /* Wait for the codec bus to be free */
 static int snd_es1968_ac97_wait(es1968_t *chip)
 {
@@ -755,7 +750,7 @@ static void __apu_set_register(es1968_t *chip, u16 channel, u8 reg, u16 data)
 	apu_data_set(chip, data);
 }
 
-inline static void apu_set_register(es1968_t *chip, u16 channel, u8 reg, u16 data)
+static inline void apu_set_register(es1968_t *chip, u16 channel, u8 reg, u16 data)
 {
 	unsigned long flags;
 	spin_lock_irqsave(&chip->reg_lock, flags);
@@ -771,7 +766,7 @@ static u16 __apu_get_register(es1968_t *chip, u16 channel, u8 reg)
 	return __maestro_read(chip, IDR0_DATA_PORT);
 }
 
-inline static u16 apu_get_register(es1968_t *chip, u16 channel, u8 reg)
+static inline u16 apu_get_register(es1968_t *chip, u16 channel, u8 reg)
 {
 	unsigned long flags;
 	u16 v;
@@ -957,7 +952,7 @@ static u32 snd_es1968_compute_rate(es1968_t *chip, u32 freq)
 }
 
 /* get current pointer */
-inline static unsigned int
+static inline unsigned int
 snd_es1968_get_dma_ptr(es1968_t *chip, esschan_t *es)
 {
 	unsigned int offset;
@@ -978,7 +973,7 @@ static void snd_es1968_apu_set_freq(es1968_t *chip, int apu, int freq)
 }
 
 /* spin lock held */
-inline static void snd_es1968_trigger_apu(es1968_t *esm, int apu, int mode)
+static inline void snd_es1968_trigger_apu(es1968_t *esm, int apu, int mode)
 {
 	/* set the APU mode */
 	__apu_set_register(esm, apu, 0,
@@ -1809,8 +1804,7 @@ static void __devinit es1968_measure_clock(es1968_t *chip)
 	snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR);
 	do_gettimeofday(&start_time);
 	spin_unlock_irq(&chip->reg_lock);
-	set_current_state(TASK_UNINTERRUPTIBLE);
-	schedule_timeout(HZ / 20); /* 50 msec */
+	msleep(50);
 	spin_lock_irq(&chip->reg_lock);
 	offset = __apu_get_register(chip, apu, 5);
 	do_gettimeofday(&stop_time);
@@ -2093,7 +2087,7 @@ static void snd_es1968_ac97_reset(es1968_t *chip)
 	outw(0x0000, ioaddr + 0x60);	/* write 0 to gpio 0 */
 	udelay(20);
 	outw(0x0001, ioaddr + 0x60);	/* write 1 to gpio 1 */
-	big_mdelay(20);
+	msleep(20);
 
 	outw(save_68 | 0x1, ioaddr + 0x68);	/* now restore .. */
 	outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38);
@@ -2109,7 +2103,7 @@ static void snd_es1968_ac97_reset(es1968_t *chip)
 	outw(0x0001, ioaddr + 0x60);	/* write 1 to gpio */
 	udelay(20);
 	outw(0x0009, ioaddr + 0x60);	/* write 9 to gpio */
-	big_mdelay(500);
+	msleep(500);
 	//outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38);
 	outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
 	outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
@@ -2135,7 +2129,7 @@ static void snd_es1968_ac97_reset(es1968_t *chip)
 
 		if (w > 10000) {
 			outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37);	/* do a software reset */
-			big_mdelay(500);	/* oh my.. */
+			msleep(500);	/* oh my.. */
 			outb(inb(ioaddr + 0x37) & ~0x08,
 				ioaddr + 0x37);
 			udelay(1);
diff --git a/sound/pci/hda/hda_codec.h b/sound/pci/hda/hda_codec.h
index 59991560d49..dd0d99d2ad2 100644
--- a/sound/pci/hda/hda_codec.h
+++ b/sound/pci/hda/hda_codec.h
@@ -262,6 +262,9 @@ enum {
 #define AC_PINCTL_OUT_EN		(1<<6)
 #define AC_PINCTL_HP_EN			(1<<7)
 
+/* Unsolicited response - 8bit */
+#define AC_USRSP_EN			(1<<7)
+
 /* configuration default - 32bit */
 #define AC_DEFCFG_SEQUENCE		(0xf<<0)
 #define AC_DEFCFG_DEF_ASSOC		(0xf<<4)
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 5e0cca36ed5..288ab076483 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -178,6 +178,9 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 #define ICH6_INT_CTRL_EN	0x40000000	/* controller interrupt enable bit */
 #define ICH6_INT_GLOBAL_EN	0x80000000	/* global interrupt enable bit */
 
+/* GCTL unsolicited response enable bit */
+#define ICH6_GCTL_UREN		(1<<8)
+
 /* GCTL reset bit */
 #define ICH6_GCTL_RESET		(1<<0)
 
@@ -562,6 +565,9 @@ static int azx_reset(azx_t *chip)
 		return -EBUSY;
 	}
 
+	/* Accept unsolicited responses */
+	azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
+
 	/* detect codecs */
 	if (! chip->codec_mask) {
 		chip->codec_mask = azx_readw(chip, STATESTS);
diff --git a/sound/pci/hda/patch_cmedia.c b/sound/pci/hda/patch_cmedia.c
index 2d6e3e3d0a3..86f195f19ee 100644
--- a/sound/pci/hda/patch_cmedia.c
+++ b/sound/pci/hda/patch_cmedia.c
@@ -408,7 +408,7 @@ static int cmi9880_fill_multi_dac_nids(struct hda_codec *codec, const struct aut
 		/* search for an empty channel */
 		for (j = 0; j < cfg->line_outs; j++) {
 			if (! assigned[j]) {
-				spec->dac_nids[i] = i + 0x03;
+				spec->dac_nids[i] = j + 0x03;
 				assigned[j] = 1;
 				break;
 			}
@@ -444,11 +444,10 @@ static int cmi9880_fill_multi_init(struct hda_codec *codec, const struct auto_pi
 			len = snd_hda_get_connections(codec, nid, conn, 4);
 			for (k = 0; k < len; k++)
 				if (conn[k] == spec->dac_nids[i]) {
-					spec->multi_init[j].param = j;
+					spec->multi_init[j].param = k;
 					break;
 				}
 			j++;
-			break;
 		}
 	}
 	return 0;
diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index bab89843d85..9b856990078 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -40,6 +40,7 @@ enum {
 	ALC880_W810,
 	ALC880_Z71V,
 	ALC880_AUTO,
+	ALC880_6ST,
 	ALC880_6ST_DIG,
 	ALC880_F1734,
 	ALC880_ASUS,
@@ -119,6 +120,7 @@ struct alc_spec {
 	unsigned int num_kctl_alloc, num_kctl_used;
 	snd_kcontrol_new_t *kctl_alloc;
 	struct hda_input_mux private_imux;
+	hda_nid_t private_dac_nids[4];
 };
 
 
@@ -1547,9 +1549,10 @@ static struct hda_board_config alc880_cfg_tbl[] = {
 	{ .pci_subvendor = 0x8086, .pci_subdevice = 0xa100, .config = ALC880_5ST_DIG },
 	{ .pci_subvendor = 0x1565, .pci_subdevice = 0x8202, .config = ALC880_5ST_DIG },
 	{ .pci_subvendor = 0x1019, .pci_subdevice = 0xa880, .config = ALC880_5ST_DIG },
-	{ .pci_subvendor = 0x1019, .pci_subdevice = 0xa884, .config = ALC880_5ST_DIG },
+	/* { .pci_subvendor = 0x1019, .pci_subdevice = 0xa884, .config = ALC880_5ST_DIG }, */ /* conflict with 6stack */
 	{ .pci_subvendor = 0x1695, .pci_subdevice = 0x400d, .config = ALC880_5ST_DIG },
-	{ .pci_subvendor = 0x0000, .pci_subdevice = 0x8086, .config = ALC880_5ST_DIG },
+	/* note subvendor = 0 below */
+	/* { .pci_subvendor = 0x0000, .pci_subdevice = 0x8086, .config = ALC880_5ST_DIG }, */
 
 	{ .modelname = "w810", .config = ALC880_W810 },
 	{ .pci_subvendor = 0x161f, .pci_subdevice = 0x203d, .config = ALC880_W810 },
@@ -1557,7 +1560,10 @@ static struct hda_board_config alc880_cfg_tbl[] = {
 	{ .modelname = "z71v", .config = ALC880_Z71V },
 	{ .pci_subvendor = 0x1043, .pci_subdevice = 0x1964, .config = ALC880_Z71V },
 
-	{ .modelname = "6statack-digout", .config = ALC880_6ST_DIG },
+	{ .modelname = "6stack", .config = ALC880_6ST },
+	{ .pci_subvendor = 0x1019, .pci_subdevice = 0xa884, .config = ALC880_6ST }, /* Acer APFV */
+
+	{ .modelname = "6stack-digout", .config = ALC880_6ST_DIG },
 	{ .pci_subvendor = 0x2668, .pci_subdevice = 0x8086, .config = ALC880_6ST_DIG },
 	{ .pci_subvendor = 0x8086, .pci_subdevice = 0x2668, .config = ALC880_6ST_DIG },
 	{ .pci_subvendor = 0x1462, .pci_subdevice = 0x1150, .config = ALC880_6ST_DIG },
@@ -1644,6 +1650,15 @@ static struct alc_config_preset alc880_presets[] = {
 		.channel_mode = alc880_fivestack_modes,
 		.input_mux = &alc880_capture_source,
 	},
+	[ALC880_6ST] = {
+		.mixers = { alc880_six_stack_mixer },
+		.init_verbs = { alc880_volume_init_verbs, alc880_pin_6stack_init_verbs },
+		.num_dacs = ARRAY_SIZE(alc880_6st_dac_nids),
+		.dac_nids = alc880_6st_dac_nids,
+		.num_channel_mode = ARRAY_SIZE(alc880_sixstack_modes),
+		.channel_mode = alc880_sixstack_modes,
+		.input_mux = &alc880_6stack_capture_source,
+	},
 	[ALC880_6ST_DIG] = {
 		.mixers = { alc880_six_stack_mixer },
 		.init_verbs = { alc880_volume_init_verbs, alc880_pin_6stack_init_verbs },
@@ -1656,7 +1671,8 @@ static struct alc_config_preset alc880_presets[] = {
 	},
 	[ALC880_W810] = {
 		.mixers = { alc880_w810_base_mixer },
-		.init_verbs = { alc880_volume_init_verbs, alc880_pin_w810_init_verbs },
+		.init_verbs = { alc880_volume_init_verbs, alc880_pin_w810_init_verbs,
+				alc880_gpio2_init_verbs },
 		.num_dacs = ARRAY_SIZE(alc880_w810_dac_nids),
 		.dac_nids = alc880_w810_dac_nids,
 		.dig_out_nid = ALC880_DIGOUT_NID,
@@ -1666,8 +1682,7 @@ static struct alc_config_preset alc880_presets[] = {
 	},
 	[ALC880_Z71V] = {
 		.mixers = { alc880_z71v_mixer },
-		.init_verbs = { alc880_volume_init_verbs, alc880_pin_z71v_init_verbs,
-				alc880_gpio2_init_verbs },
+		.init_verbs = { alc880_volume_init_verbs, alc880_pin_z71v_init_verbs },
 		.num_dacs = ARRAY_SIZE(alc880_z71v_dac_nids),
 		.dac_nids = alc880_z71v_dac_nids,
 		.dig_out_nid = ALC880_DIGOUT_NID,
@@ -1809,6 +1824,7 @@ static int alc880_auto_fill_dac_nids(struct alc_spec *spec, const struct auto_pi
 	int i, j;
 
 	memset(assigned, 0, sizeof(assigned));
+	spec->multiout.dac_nids = spec->private_dac_nids;
 
 	/* check the pins hardwired to audio widget */
 	for (i = 0; i < cfg->line_outs; i++) {
diff --git a/sound/pci/hda/patch_sigmatel.c b/sound/pci/hda/patch_sigmatel.c
index 013be2ea513..9d503da7320 100644
--- a/sound/pci/hda/patch_sigmatel.c
+++ b/sound/pci/hda/patch_sigmatel.c
@@ -30,32 +30,37 @@
 #include <linux/slab.h>
 #include <linux/pci.h>
 #include <sound/core.h>
+#include <sound/asoundef.h>
 #include "hda_codec.h"
 #include "hda_local.h"
 
 #undef STAC_TEST
 
+#define NUM_CONTROL_ALLOC	32
+#define STAC_HP_EVENT		0x37
+#define STAC_UNSOL_ENABLE 	(AC_USRSP_EN | STAC_HP_EVENT)
+
 struct sigmatel_spec {
+	snd_kcontrol_new_t *mixers[4];
+	unsigned int num_mixers;
+
+	unsigned int surr_switch: 1;
+
 	/* playback */
 	struct hda_multi_out multiout;
-	hda_nid_t playback_nid;
+	hda_nid_t dac_nids[4];
 
 	/* capture */
 	hda_nid_t *adc_nids;
 	unsigned int num_adcs;
 	hda_nid_t *mux_nids;
 	unsigned int num_muxes;
-	hda_nid_t capture_nid;
 	hda_nid_t dig_in_nid;
 
-	/* power management*/
-	hda_nid_t *pstate_nids;
-	unsigned int num_pstates;
-
+#ifdef STAC_TEST
 	/* pin widgets */
 	hda_nid_t *pin_nids;
 	unsigned int num_pins;
-#ifdef STAC_TEST
 	unsigned int *pin_configs;
 #endif
 
@@ -64,16 +69,20 @@ struct sigmatel_spec {
 	snd_kcontrol_new_t *mixer;
 
 	/* capture source */
-	struct hda_input_mux input_mux;
-	char input_labels[HDA_MAX_NUM_INPUTS][16];
+	struct hda_input_mux *input_mux;
 	unsigned int cur_mux[2];
 
 	/* channel mode */
 	unsigned int num_ch_modes;
 	unsigned int cur_ch_mode;
-	const struct sigmatel_channel_mode *channel_modes;
 
-	struct hda_pcm pcm_rec[1];	/* PCM information */
+	struct hda_pcm pcm_rec[2];	/* PCM information */
+
+	/* dynamic controls and input_mux */
+	struct auto_pin_cfg autocfg;
+	unsigned int num_kctl_alloc, num_kctl_used;
+	snd_kcontrol_new_t *kctl_alloc;
+	struct hda_input_mux private_imux;
 };
 
 static hda_nid_t stac9200_adc_nids[1] = {
@@ -88,14 +97,6 @@ static hda_nid_t stac9200_dac_nids[1] = {
         0x02,
 };
 
-static hda_nid_t stac9200_pstate_nids[3] = {
-	0x01, 0x02, 0x03,
-};
-
-static hda_nid_t stac9200_pin_nids[8] = {
-	0x08, 0x09, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12,
-};
-
 static hda_nid_t stac922x_adc_nids[2] = {
         0x06, 0x07,
 };
@@ -104,24 +105,22 @@ static hda_nid_t stac922x_mux_nids[2] = {
         0x12, 0x13,
 };
 
-static hda_nid_t stac922x_dac_nids[4] = {
-        0x02, 0x03, 0x04, 0x05,
-};
-
-static hda_nid_t stac922x_pstate_nids[8] = {
-	0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x11,
+#ifdef STAC_TEST
+static hda_nid_t stac9200_pin_nids[8] = {
+	0x08, 0x09, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12,
 };
 
 static hda_nid_t stac922x_pin_nids[10] = {
 	0x0a, 0x0b, 0x0c, 0x0d, 0x0e,
 	0x0f, 0x10, 0x11, 0x15, 0x1b,
 };
+#endif
 
 static int stac92xx_mux_enum_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
 {
 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
 	struct sigmatel_spec *spec = codec->spec;
-	return snd_hda_input_mux_info(&spec->input_mux, uinfo);
+	return snd_hda_input_mux_info(spec->input_mux, uinfo);
 }
 
 static int stac92xx_mux_enum_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
@@ -140,26 +139,64 @@ static int stac92xx_mux_enum_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t
 	struct sigmatel_spec *spec = codec->spec;
 	unsigned int adc_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
 
-	return snd_hda_input_mux_put(codec, &spec->input_mux, ucontrol,
+	return snd_hda_input_mux_put(codec, spec->input_mux, ucontrol,
 				     spec->mux_nids[adc_idx], &spec->cur_mux[adc_idx]);
 }
 
-static struct hda_verb stac9200_ch2_init[] = {
+static struct hda_verb stac9200_core_init[] = {
 	/* set dac0mux for dac converter */
-	{ 0x07, 0x701, 0x00},
+	{ 0x07, AC_VERB_SET_CONNECT_SEL, 0x00},
 	{}
 };
 
-static struct hda_verb stac922x_ch2_init[] = {
+static struct hda_verb stac922x_core_init[] = {
 	/* set master volume and direct control */	
-	{ 0x16, 0x70f, 0xff},
+	{ 0x16, AC_VERB_SET_VOLUME_KNOB_CONTROL, 0xff},
 	{}
 };
 
-struct sigmatel_channel_mode {
-	unsigned int channels;
-	const struct hda_verb *sequence;
-};
+static int stac922x_channel_modes[3] = {2, 6, 8};
+
+static int stac922x_ch_mode_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
+{
+	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
+	struct sigmatel_spec *spec = codec->spec;
+
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
+	uinfo->count = 1;
+	uinfo->value.enumerated.items = spec->num_ch_modes;
+	if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
+		uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
+	sprintf(uinfo->value.enumerated.name, "%dch",
+		stac922x_channel_modes[uinfo->value.enumerated.item]);
+	return 0;
+}
+
+static int stac922x_ch_mode_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
+	struct sigmatel_spec *spec = codec->spec;
+
+	ucontrol->value.enumerated.item[0] = spec->cur_ch_mode;
+	return 0;
+}
+
+static int stac922x_ch_mode_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
+{
+	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
+	struct sigmatel_spec *spec = codec->spec;
+
+	if (ucontrol->value.enumerated.item[0] >= spec->num_ch_modes)
+		ucontrol->value.enumerated.item[0] = spec->num_ch_modes;
+	if (ucontrol->value.enumerated.item[0] == spec->cur_ch_mode &&
+	    ! codec->in_resume)
+		return 0;
+
+	spec->cur_ch_mode = ucontrol->value.enumerated.item[0];
+	spec->multiout.max_channels = stac922x_channel_modes[spec->cur_ch_mode];
+
+	return 1;
+}
 
 static snd_kcontrol_new_t stac9200_mixer[] = {
 	HDA_CODEC_VOLUME("Master Playback Volume", 0xb, 0, HDA_OUTPUT),
@@ -174,13 +211,12 @@ static snd_kcontrol_new_t stac9200_mixer[] = {
 	},
 	HDA_CODEC_VOLUME("Capture Volume", 0x0a, 0, HDA_OUTPUT),
 	HDA_CODEC_MUTE("Capture Switch", 0x0a, 0, HDA_OUTPUT),
-	HDA_CODEC_VOLUME("Input Mux Volume", 0x0c, 0, HDA_OUTPUT),
+	HDA_CODEC_VOLUME("Capture Mux Volume", 0x0c, 0, HDA_OUTPUT),
 	{ } /* end */
 };
 
+/* This needs to be generated dynamically based on sequence */
 static snd_kcontrol_new_t stac922x_mixer[] = {
-	HDA_CODEC_VOLUME("PCM Playback Volume", 0x2, 0x0, HDA_OUTPUT),
-	HDA_CODEC_MUTE("PCM Playback Switch", 0x2, 0x0, HDA_OUTPUT),
 	{
 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
 		.name = "Input Source",
@@ -195,14 +231,38 @@ static snd_kcontrol_new_t stac922x_mixer[] = {
 	{ } /* end */
 };
 
+static snd_kcontrol_new_t stac922x_ch_mode_mixer[] = {
+	{
+		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+		.name = "Channel Mode",
+		.info = stac922x_ch_mode_info,
+		.get = stac922x_ch_mode_get,
+		.put = stac922x_ch_mode_put,
+	},
+	{ } /* end */
+};
+
 static int stac92xx_build_controls(struct hda_codec *codec)
 {
 	struct sigmatel_spec *spec = codec->spec;
 	int err;
+	int i;
 
 	err = snd_hda_add_new_ctls(codec, spec->mixer);
 	if (err < 0)
 		return err;
+
+	for (i = 0; i < spec->num_mixers; i++) {
+		err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
+		if (err < 0)
+			return err;
+	}
+
+	if (spec->surr_switch) {
+		err = snd_hda_add_new_ctls(codec, stac922x_ch_mode_mixer);
+		if (err < 0)
+			return err;
+	}
 	if (spec->multiout.dig_out_nid) {
 		err = snd_hda_create_spdif_out_ctls(codec, spec->multiout.dig_out_nid);
 		if (err < 0)
@@ -222,9 +282,9 @@ static unsigned int stac9200_pin_configs[8] = {
 	0x02a19020, 0x01a19021, 0x90100140, 0x01813122,
 };
 
-static unsigned int stac922x_pin_configs[14] = {
-	0x40000100, 0x40000100, 0x40000100, 0x01114010,
-	0x01813122, 0x40000100, 0x01447010, 0x01c47010,
+static unsigned int stac922x_pin_configs[10] = {
+	0x01014010, 0x01014011, 0x01014012, 0x0221401f,
+	0x01813122, 0x01014014, 0x01441030, 0x01c41030,
 	0x40000100, 0x40000100,
 };
 
@@ -255,180 +315,66 @@ static void stac92xx_set_config_regs(struct hda_codec *codec)
 }
 #endif
 
-static int stac92xx_set_pinctl(struct hda_codec *codec, hda_nid_t nid, unsigned int value)
-{
-	unsigned int pin_ctl;
-
-	pin_ctl = snd_hda_codec_read(codec, nid, 0,
-				     AC_VERB_GET_PIN_WIDGET_CONTROL,
-				     0x00);
-	snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_PIN_WIDGET_CONTROL,
-			    pin_ctl | value);
-
-	return 0;
-}
-
-static int stac92xx_set_vref(struct hda_codec *codec, hda_nid_t nid)
-{
-	unsigned int vref_caps = snd_hda_param_read(codec, nid, AC_PAR_PIN_CAP) >> AC_PINCAP_VREF_SHIFT;
-	unsigned int vref_ctl = AC_PINCTL_VREF_HIZ;
-
-	if (vref_caps & AC_PINCAP_VREF_100)
-		vref_ctl = AC_PINCTL_VREF_100;
-	else if (vref_caps & AC_PINCAP_VREF_80)
-		vref_ctl = AC_PINCTL_VREF_80;
-	else if (vref_caps & AC_PINCAP_VREF_50)
-		vref_ctl = AC_PINCTL_VREF_50;
-	else if (vref_caps & AC_PINCAP_VREF_GRD)
-		vref_ctl = AC_PINCTL_VREF_GRD;
-
-	stac92xx_set_pinctl(codec, nid, vref_ctl);
-	
-	return 0;
-}
-
 /*
- * retrieve the default device type from the default config value
+ * Analog playback callbacks
  */
-#define get_defcfg_type(cfg) ((cfg & AC_DEFCFG_DEVICE) >> AC_DEFCFG_DEVICE_SHIFT)
-#define get_defcfg_location(cfg) ((cfg & AC_DEFCFG_LOCATION) >> AC_DEFCFG_LOCATION_SHIFT)
-
-static int stac92xx_config_pin(struct hda_codec *codec, hda_nid_t nid, unsigned int pin_cfg)
+static int stac92xx_playback_pcm_open(struct hda_pcm_stream *hinfo,
+				      struct hda_codec *codec,
+				      snd_pcm_substream_t *substream)
 {
 	struct sigmatel_spec *spec = codec->spec;
-	u32 location = get_defcfg_location(pin_cfg);
-	char *label;
-	const char *type = NULL;
-	int ainput = 0;
-
-	switch(get_defcfg_type(pin_cfg)) {
-		case AC_JACK_HP_OUT:
-			/* Enable HP amp */
-			stac92xx_set_pinctl(codec, nid, AC_PINCTL_HP_EN);
-			/* Fall through */
-		case AC_JACK_SPDIF_OUT:
-		case AC_JACK_LINE_OUT:
-		case AC_JACK_SPEAKER:
-			/* Enable output */
-			stac92xx_set_pinctl(codec, nid, AC_PINCTL_OUT_EN);
-			break;
-		case AC_JACK_SPDIF_IN:
-			stac92xx_set_pinctl(codec, nid, AC_PINCTL_IN_EN);
-			break;
-		case AC_JACK_MIC_IN:
-			if ((location & 0x0f) == AC_JACK_LOC_FRONT)
-				type = "Front Mic";
-			else
-				type = "Mic";
-			ainput = 1;
-			/* Set vref */
-			stac92xx_set_vref(codec, nid);
-			stac92xx_set_pinctl(codec, nid, AC_PINCTL_IN_EN);
-			break;
-		case AC_JACK_CD:
-			type = "CD";
-			ainput = 1;
-			stac92xx_set_pinctl(codec, nid, AC_PINCTL_IN_EN);
-			break;
-		case AC_JACK_LINE_IN:
-			if ((location & 0x0f) == AC_JACK_LOC_FRONT)
-				type = "Front Line";
-			else
-				type = "Line";
-			ainput = 1;
-			stac92xx_set_pinctl(codec, nid, AC_PINCTL_IN_EN);
-			break;
-		case AC_JACK_AUX:
-			if ((location & 0x0f) == AC_JACK_LOC_FRONT)
-				type = "Front Aux";
-			else
-				type = "Aux";
-			ainput = 1;
-			stac92xx_set_pinctl(codec, nid, AC_PINCTL_IN_EN);
-			break;
-	}
-
-	if (ainput) {
-		hda_nid_t con_lst[HDA_MAX_NUM_INPUTS];
-		int i, j, num_cons, index = -1;
-		if (!type)
-			type = "Input";
-		label = spec->input_labels[spec->input_mux.num_items];
-		strcpy(label, type);
-		spec->input_mux.items[spec->input_mux.num_items].label = label;
-		for (i=0; i<spec->num_muxes; i++) {
-			num_cons = snd_hda_get_connections(codec, spec->mux_nids[i], con_lst, HDA_MAX_NUM_INPUTS);
-			for (j=0; j<num_cons; j++)
-				if (con_lst[j] == nid) {
-					index = j;
-					break;
-				}
-			if (index >= 0)
-				break;
-		}
-		spec->input_mux.items[spec->input_mux.num_items].index = index;
-		spec->input_mux.num_items++;
-	}
-
-	return 0;
+	return snd_hda_multi_out_analog_open(codec, &spec->multiout, substream);
 }
 
-static int stac92xx_config_pins(struct hda_codec *codec)
+/*
+ * set up the i/o for analog out
+ * when the digital out is available, copy the front out to digital out, too.
+ */
+static int stac92xx_multi_out_analog_prepare(struct hda_codec *codec, struct hda_multi_out *mout,
+				     unsigned int stream_tag,
+				     unsigned int format,
+				     snd_pcm_substream_t *substream)
 {
-	struct sigmatel_spec *spec = codec->spec;
+	hda_nid_t *nids = mout->dac_nids;
+	int chs = substream->runtime->channels;
 	int i;
-	unsigned int pin_cfg;
 
-	for (i=0; i < spec->num_pins; i++) {
-		/* Default to disabled */
-		snd_hda_codec_write(codec, spec->pin_nids[i], 0,
-				    AC_VERB_SET_PIN_WIDGET_CONTROL,
-				    0x00);
-
-		pin_cfg = snd_hda_codec_read(codec, spec->pin_nids[i], 0,
-					     AC_VERB_GET_CONFIG_DEFAULT,
-					     0x00);
-		if (((pin_cfg & AC_DEFCFG_PORT_CONN) >> AC_DEFCFG_PORT_CONN_SHIFT) == AC_JACK_PORT_NONE)
-			continue;	/* Move on */
-
-		stac92xx_config_pin(codec, spec->pin_nids[i], pin_cfg);
+	down(&codec->spdif_mutex);
+	if (mout->dig_out_nid && mout->dig_out_used != HDA_DIG_EXCLUSIVE) {
+		if (chs == 2 &&
+		    snd_hda_is_supported_format(codec, mout->dig_out_nid, format) &&
+		    ! (codec->spdif_status & IEC958_AES0_NONAUDIO)) {
+			mout->dig_out_used = HDA_DIG_ANALOG_DUP;
+			/* setup digital receiver */
+			snd_hda_codec_setup_stream(codec, mout->dig_out_nid,
+						   stream_tag, 0, format);
+		} else {
+			mout->dig_out_used = 0;
+			snd_hda_codec_setup_stream(codec, mout->dig_out_nid, 0, 0, 0);
+		}
 	}
-
-	return 0;
-}
-
-static int stac92xx_init(struct hda_codec *codec)
-{
-	struct sigmatel_spec *spec = codec->spec;
-	int i;
-
-	for (i=0; i < spec->num_pstates; i++)
-		snd_hda_codec_write(codec, spec->pstate_nids[i], 0,
-				    AC_VERB_SET_POWER_STATE, 0x00);
-
-	mdelay(100);
-
-	snd_hda_sequence_write(codec, spec->init);
-
-#ifdef STAC_TEST
-	stac92xx_set_config_regs(codec);
-#endif
-
-	stac92xx_config_pins(codec);
-
+	up(&codec->spdif_mutex);
+
+	/* front */
+	snd_hda_codec_setup_stream(codec, nids[HDA_FRONT], stream_tag, 0, format);
+	if (mout->hp_nid)
+		/* headphone out will just decode front left/right (stereo) */
+		snd_hda_codec_setup_stream(codec, mout->hp_nid, stream_tag, 0, format);
+	/* surrounds */
+	if (mout->max_channels > 2)
+		for (i = 1; i < mout->num_dacs; i++) {
+			if ((mout->max_channels == 6) && (i == 3))
+				break;
+			if (chs >= (i + 1) * 2) /* independent out */
+				snd_hda_codec_setup_stream(codec, nids[i], stream_tag, i * 2,
+						format);
+			else /* copy front */
+				snd_hda_codec_setup_stream(codec, nids[i], stream_tag, 0,
+						format);
+		}
 	return 0;
 }
 
-/*
- * Analog playback callbacks
- */
-static int stac92xx_playback_pcm_open(struct hda_pcm_stream *hinfo,
-				      struct hda_codec *codec,
-				      snd_pcm_substream_t *substream)
-{
-	struct sigmatel_spec *spec = codec->spec;
-	return snd_hda_multi_out_analog_open(codec, &spec->multiout, substream);
-}
 
 static int stac92xx_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
 					 struct hda_codec *codec,
@@ -437,7 +383,7 @@ static int stac92xx_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
 					 snd_pcm_substream_t *substream)
 {
 	struct sigmatel_spec *spec = codec->spec;
-	return snd_hda_multi_out_analog_prepare(codec, &spec->multiout, stream_tag,
+	return stac92xx_multi_out_analog_prepare(codec, &spec->multiout, stream_tag,
 						format, substream);
 }
 
@@ -516,7 +462,7 @@ static struct hda_pcm_stream stac92xx_pcm_digital_capture = {
 static struct hda_pcm_stream stac92xx_pcm_analog_playback = {
 	.substreams = 1,
 	.channels_min = 2,
-	.channels_max = 2,
+	.channels_max = 8,
 	.nid = 0x02, /* NID to query formats and rates */
 	.ops = {
 		.open = stac92xx_playback_pcm_open,
@@ -544,11 +490,9 @@ static int stac92xx_build_pcms(struct hda_codec *codec)
 	codec->num_pcms = 1;
 	codec->pcm_info = info;
 
-	info->name = "STAC92xx";
+	info->name = "STAC92xx Analog";
 	info->stream[SNDRV_PCM_STREAM_PLAYBACK] = stac92xx_pcm_analog_playback;
-	info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->playback_nid;
 	info->stream[SNDRV_PCM_STREAM_CAPTURE] = stac92xx_pcm_analog_capture;
-	info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->capture_nid;
 
 	if (spec->multiout.dig_out_nid || spec->dig_in_nid) {
 		codec->num_pcms++;
@@ -567,21 +511,413 @@ static int stac92xx_build_pcms(struct hda_codec *codec)
 	return 0;
 }
 
+enum {
+	STAC_CTL_WIDGET_VOL,
+	STAC_CTL_WIDGET_MUTE,
+};
+
+static snd_kcontrol_new_t stac92xx_control_templates[] = {
+	HDA_CODEC_VOLUME(NULL, 0, 0, 0),
+	HDA_CODEC_MUTE(NULL, 0, 0, 0),
+};
+
+/* add dynamic controls */
+static int stac92xx_add_control(struct sigmatel_spec *spec, int type, const char *name, unsigned long val)
+{
+	snd_kcontrol_new_t *knew;
+
+	if (spec->num_kctl_used >= spec->num_kctl_alloc) {
+		int num = spec->num_kctl_alloc + NUM_CONTROL_ALLOC;
+
+		knew = kcalloc(num + 1, sizeof(*knew), GFP_KERNEL); /* array + terminator */
+		if (! knew)
+			return -ENOMEM;
+		if (spec->kctl_alloc) {
+			memcpy(knew, spec->kctl_alloc, sizeof(*knew) * spec->num_kctl_alloc);
+			kfree(spec->kctl_alloc);
+		}
+		spec->kctl_alloc = knew;
+		spec->num_kctl_alloc = num;
+	}
+
+	knew = &spec->kctl_alloc[spec->num_kctl_used];
+	*knew = stac92xx_control_templates[type];
+	knew->name = kstrdup(name, GFP_KERNEL);
+	if (! knew->name)
+		return -ENOMEM;
+	knew->private_value = val;
+	spec->num_kctl_used++;
+	return 0;
+}
+
+/* fill in the dac_nids table from the parsed pin configuration */
+static int stac92xx_auto_fill_dac_nids(struct hda_codec *codec, const struct auto_pin_cfg *cfg)
+{
+	struct sigmatel_spec *spec = codec->spec;
+	hda_nid_t nid;
+	int i;
+
+	/* check the pins hardwired to audio widget */
+	for (i = 0; i < cfg->line_outs; i++) {
+		nid = cfg->line_out_pins[i];
+		spec->multiout.dac_nids[i] = snd_hda_codec_read(codec, nid, 0,
+					AC_VERB_GET_CONNECT_LIST, 0) & 0xff;
+	}
+
+	spec->multiout.num_dacs = cfg->line_outs;
+
+	return 0;
+}
+
+/* add playback controls from the parsed DAC table */
+static int stac92xx_auto_create_multi_out_ctls(struct sigmatel_spec *spec, const struct auto_pin_cfg *cfg)
+{
+	char name[32];
+	static const char *chname[4] = { "Front", "Surround", NULL /*CLFE*/, "Side" };
+	hda_nid_t nid;
+	int i, err;
+
+	for (i = 0; i < cfg->line_outs; i++) {
+		if (! spec->multiout.dac_nids[i])
+			continue;
+
+		nid = spec->multiout.dac_nids[i];
+
+		if (i == 2) {
+			/* Center/LFE */
+			if ((err = stac92xx_add_control(spec, STAC_CTL_WIDGET_VOL, "Center Playback Volume",
+					       HDA_COMPOSE_AMP_VAL(nid, 1, 0, HDA_OUTPUT))) < 0)
+				return err;
+			if ((err = stac92xx_add_control(spec, STAC_CTL_WIDGET_VOL, "LFE Playback Volume",
+					       HDA_COMPOSE_AMP_VAL(nid, 2, 0, HDA_OUTPUT))) < 0)
+				return err;
+			if ((err = stac92xx_add_control(spec, STAC_CTL_WIDGET_MUTE, "Center Playback Switch",
+					       HDA_COMPOSE_AMP_VAL(nid, 1, 0, HDA_OUTPUT))) < 0)
+				return err;
+			if ((err = stac92xx_add_control(spec, STAC_CTL_WIDGET_MUTE, "LFE Playback Switch",
+					       HDA_COMPOSE_AMP_VAL(nid, 2, 0, HDA_OUTPUT))) < 0)
+				return err;
+		} else {
+			sprintf(name, "%s Playback Volume", chname[i]);
+			if ((err = stac92xx_add_control(spec, STAC_CTL_WIDGET_VOL, name,
+					       HDA_COMPOSE_AMP_VAL(nid, 3, 0, HDA_OUTPUT))) < 0)
+				return err;
+			sprintf(name, "%s Playback Switch", chname[i]);
+			if ((err = stac92xx_add_control(spec, STAC_CTL_WIDGET_MUTE, name,
+					       HDA_COMPOSE_AMP_VAL(nid, 3, 0, HDA_OUTPUT))) < 0)
+				return err;
+		}
+	}
+
+	return 0;
+}
+
+/* add playback controls for HP output */
+static int stac92xx_auto_create_hp_ctls(struct hda_codec *codec, struct auto_pin_cfg *cfg)
+{
+	struct sigmatel_spec *spec = codec->spec;
+	hda_nid_t pin = cfg->hp_pin;
+	hda_nid_t nid;
+	int i, err;
+	unsigned int wid_caps;
+
+	if (! pin)
+		return 0;
+
+	wid_caps = snd_hda_param_read(codec, pin, AC_PAR_AUDIO_WIDGET_CAP);
+	if (wid_caps & AC_WCAP_UNSOL_CAP)
+		/* Enable unsolicited responses on the HP widget */
+		snd_hda_codec_write(codec, pin, 0,
+				AC_VERB_SET_UNSOLICITED_ENABLE,
+				STAC_UNSOL_ENABLE);
+
+	nid = snd_hda_codec_read(codec, pin, 0, AC_VERB_GET_CONNECT_LIST, 0) & 0xff;
+	for (i = 0; i < cfg->line_outs; i++) {
+		if (! spec->multiout.dac_nids[i])
+			continue;
+		if (spec->multiout.dac_nids[i] == nid)
+			return 0;
+	}
+
+	spec->multiout.hp_nid = nid;
+
+	/* control HP volume/switch on the output mixer amp */
+	if ((err = stac92xx_add_control(spec, STAC_CTL_WIDGET_VOL, "Headphone Playback Volume",
+					HDA_COMPOSE_AMP_VAL(nid, 3, 0, HDA_OUTPUT))) < 0)
+		return err;
+	if ((err = stac92xx_add_control(spec, STAC_CTL_WIDGET_MUTE, "Headphone Playback Switch",
+					HDA_COMPOSE_AMP_VAL(nid, 3, 0, HDA_OUTPUT))) < 0)
+		return err;
+
+	return 0;
+}
+
+/* create playback/capture controls for input pins */
+static int stac92xx_auto_create_analog_input_ctls(struct hda_codec *codec, const struct auto_pin_cfg *cfg)
+{
+	struct sigmatel_spec *spec = codec->spec;
+	static char *labels[AUTO_PIN_LAST] = {
+		"Mic", "Front Mic", "Line", "Front Line", "CD", "Aux"
+	};
+	struct hda_input_mux *imux = &spec->private_imux;
+	hda_nid_t con_lst[HDA_MAX_NUM_INPUTS];
+	int i, j, k;
+
+	for (i = 0; i < AUTO_PIN_LAST; i++) {
+		int index = -1;
+		if (cfg->input_pins[i]) {
+			imux->items[imux->num_items].label = labels[i];
+
+			for (j=0; j<spec->num_muxes; j++) {
+				int num_cons = snd_hda_get_connections(codec, spec->mux_nids[j], con_lst, HDA_MAX_NUM_INPUTS);
+				for (k=0; k<num_cons; k++)
+					if (con_lst[k] == cfg->input_pins[i]) {
+						index = k;
+					 	break;
+					}
+				if (index >= 0)
+					break;
+			}
+			imux->items[imux->num_items].index = index;
+			imux->num_items++;
+		}
+	}
+
+	return 0;
+}
+
+static void stac92xx_auto_set_pinctl(struct hda_codec *codec, hda_nid_t nid, int pin_type)
+
+{
+	snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, pin_type);
+}
+
+static void stac92xx_auto_init_multi_out(struct hda_codec *codec)
+{
+	struct sigmatel_spec *spec = codec->spec;
+	int i;
+
+	for (i = 0; i < spec->autocfg.line_outs; i++) {
+		hda_nid_t nid = spec->autocfg.line_out_pins[i];
+		stac92xx_auto_set_pinctl(codec, nid, AC_PINCTL_OUT_EN);
+	}
+}
+
+static void stac92xx_auto_init_hp_out(struct hda_codec *codec)
+{
+	struct sigmatel_spec *spec = codec->spec;
+	hda_nid_t pin;
+
+	pin = spec->autocfg.hp_pin;
+	if (pin) /* connect to front */
+		stac92xx_auto_set_pinctl(codec, pin, AC_PINCTL_OUT_EN | AC_PINCTL_HP_EN);
+}
+
+static int stac922x_parse_auto_config(struct hda_codec *codec)
+{
+	struct sigmatel_spec *spec = codec->spec;
+	int err;
+
+	if ((err = snd_hda_parse_pin_def_config(codec, &spec->autocfg)) < 0)
+		return err;
+	if ((err = stac92xx_auto_fill_dac_nids(codec, &spec->autocfg)) < 0)
+		return err;
+	if (! spec->autocfg.line_outs && ! spec->autocfg.hp_pin)
+		return 0; /* can't find valid pin config */
+
+	if ((err = stac92xx_auto_create_multi_out_ctls(spec, &spec->autocfg)) < 0 ||
+	    (err = stac92xx_auto_create_hp_ctls(codec, &spec->autocfg)) < 0 ||
+	    (err = stac92xx_auto_create_analog_input_ctls(codec, &spec->autocfg)) < 0)
+		return err;
+
+	spec->multiout.max_channels = spec->multiout.num_dacs * 2;
+	if (spec->multiout.max_channels > 2) {
+		spec->surr_switch = 1;
+		spec->cur_ch_mode = 1;
+		spec->num_ch_modes = 2;
+		if (spec->multiout.max_channels == 8) {
+			spec->cur_ch_mode++;
+			spec->num_ch_modes++;
+		}
+	}
+
+	if (spec->autocfg.dig_out_pin) {
+		spec->multiout.dig_out_nid = 0x08;
+		stac92xx_auto_set_pinctl(codec, spec->autocfg.dig_out_pin, AC_PINCTL_OUT_EN);
+	}
+	if (spec->autocfg.dig_in_pin) {
+		spec->dig_in_nid = 0x09;
+		stac92xx_auto_set_pinctl(codec, spec->autocfg.dig_in_pin, AC_PINCTL_IN_EN);
+	}
+
+	if (spec->kctl_alloc)
+		spec->mixers[spec->num_mixers++] = spec->kctl_alloc;
+
+	spec->input_mux = &spec->private_imux;
+
+	return 1;
+}
+
+static int stac9200_parse_auto_config(struct hda_codec *codec)
+{
+	struct sigmatel_spec *spec = codec->spec;
+	int err;
+
+	if ((err = snd_hda_parse_pin_def_config(codec, &spec->autocfg)) < 0)
+		return err;
+
+	if ((err = stac92xx_auto_create_analog_input_ctls(codec, &spec->autocfg)) < 0)
+		return err;
+
+	if (spec->autocfg.dig_out_pin) {
+		spec->multiout.dig_out_nid = 0x05;
+		stac92xx_auto_set_pinctl(codec, spec->autocfg.dig_out_pin, AC_PINCTL_OUT_EN);
+	}
+	if (spec->autocfg.dig_in_pin) {
+		spec->dig_in_nid = 0x04;
+		stac92xx_auto_set_pinctl(codec, spec->autocfg.dig_in_pin, AC_PINCTL_IN_EN);
+	}
+
+	if (spec->kctl_alloc)
+		spec->mixers[spec->num_mixers++] = spec->kctl_alloc;
+
+	spec->input_mux = &spec->private_imux;
+
+	return 1;
+}
+
+static int stac92xx_init_pstate(struct hda_codec *codec)
+{
+       hda_nid_t nid, nid_start;
+       int nodes;
+
+	snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_POWER_STATE, 0x00);
+
+       nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid_start);
+       for (nid = nid_start; nid < nodes + nid_start; nid++) {
+               unsigned int wid_caps = snd_hda_param_read(codec, nid,
+                                                  AC_PAR_AUDIO_WIDGET_CAP);
+		if (wid_caps & AC_WCAP_POWER)
+			snd_hda_codec_write(codec, nid, 0,
+                                    AC_VERB_SET_POWER_STATE, 0x00);
+	}
+
+	mdelay(100);
+
+	return 0;
+}
+
+static int stac92xx_init(struct hda_codec *codec)
+{
+	struct sigmatel_spec *spec = codec->spec;
+
+	stac92xx_init_pstate(codec);
+
+	snd_hda_sequence_write(codec, spec->init);
+
+	stac92xx_auto_init_multi_out(codec);
+	stac92xx_auto_init_hp_out(codec);
+
+	return 0;
+}
+
 static void stac92xx_free(struct hda_codec *codec)
 {
-	kfree(codec->spec);
+	struct sigmatel_spec *spec = codec->spec;
+	int i;
+
+	if (! spec)
+		return;
+
+	if (spec->kctl_alloc) {
+		for (i = 0; i < spec->num_kctl_used; i++)
+			kfree(spec->kctl_alloc[i].name);
+		kfree(spec->kctl_alloc);
+	}
+
+	kfree(spec);
+}
+
+static void stac92xx_set_pinctl(struct hda_codec *codec, hda_nid_t nid,
+				unsigned int flag)
+{
+	unsigned int pin_ctl = snd_hda_codec_read(codec, nid,
+			0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0x00);
+	snd_hda_codec_write(codec, nid, 0,
+			AC_VERB_SET_PIN_WIDGET_CONTROL,
+			pin_ctl | flag);
+}
+
+static void stac92xx_reset_pinctl(struct hda_codec *codec, hda_nid_t nid,
+				  unsigned int flag)
+{
+	unsigned int pin_ctl = snd_hda_codec_read(codec, nid,
+			0, AC_VERB_GET_PIN_WIDGET_CONTROL, 0x00);
+	snd_hda_codec_write(codec, nid, 0,
+			AC_VERB_SET_PIN_WIDGET_CONTROL,
+			pin_ctl & ~flag);
+}
+
+static void stac92xx_unsol_event(struct hda_codec *codec, unsigned int res)
+{
+	struct sigmatel_spec *spec = codec->spec;
+	struct auto_pin_cfg *cfg = &spec->autocfg;
+	int i, presence;
+
+	if ((res >> 26) != STAC_HP_EVENT)
+		return;
+
+	presence = snd_hda_codec_read(codec, cfg->hp_pin, 0,
+			AC_VERB_GET_PIN_SENSE, 0x00) >> 31;
+
+	if (presence) {
+		/* disable lineouts, enable hp */
+		for (i = 0; i < cfg->line_outs; i++)
+			stac92xx_reset_pinctl(codec, cfg->line_out_pins[i],
+						AC_PINCTL_OUT_EN);
+		stac92xx_set_pinctl(codec, cfg->hp_pin, AC_PINCTL_OUT_EN);
+	} else {
+		/* enable lineouts, disable hp */
+		for (i = 0; i < cfg->line_outs; i++)
+			stac92xx_set_pinctl(codec, cfg->line_out_pins[i],
+						AC_PINCTL_OUT_EN);
+		stac92xx_reset_pinctl(codec, cfg->hp_pin, AC_PINCTL_OUT_EN);
+	}
+} 
+
+#ifdef CONFIG_PM
+static int stac92xx_resume(struct hda_codec *codec)
+{
+	struct sigmatel_spec *spec = codec->spec;
+	int i;
+
+	stac92xx_init(codec);
+	for (i = 0; i < spec->num_mixers; i++)
+		snd_hda_resume_ctls(codec, spec->mixers[i]);
+	if (spec->multiout.dig_out_nid)
+		snd_hda_resume_spdif_out(codec);
+	if (spec->dig_in_nid)
+		snd_hda_resume_spdif_in(codec);
+
+	return 0;
 }
+#endif
 
 static struct hda_codec_ops stac92xx_patch_ops = {
 	.build_controls = stac92xx_build_controls,
 	.build_pcms = stac92xx_build_pcms,
 	.init = stac92xx_init,
 	.free = stac92xx_free,
+	.unsol_event = stac92xx_unsol_event,
+#ifdef CONFIG_PM
+	.resume = stac92xx_resume,
+#endif
 };
 
 static int patch_stac9200(struct hda_codec *codec)
 {
 	struct sigmatel_spec *spec;
+	int err;
 
 	spec  = kcalloc(1, sizeof(*spec), GFP_KERNEL);
 	if (spec == NULL)
@@ -589,26 +925,27 @@ static int patch_stac9200(struct hda_codec *codec)
 
 	codec->spec = spec;
 
+#ifdef STAC_TEST
+	spec->pin_nids = stac9200_pin_nids;
+	spec->num_pins = 8;
+	spec->pin_configs = stac9200_pin_configs;
+	stac92xx_set_config_regs(codec);
+#endif
 	spec->multiout.max_channels = 2;
 	spec->multiout.num_dacs = 1;
 	spec->multiout.dac_nids = stac9200_dac_nids;
-	spec->multiout.dig_out_nid = 0x05;
-	spec->dig_in_nid = 0x04;
 	spec->adc_nids = stac9200_adc_nids;
 	spec->mux_nids = stac9200_mux_nids;
 	spec->num_muxes = 1;
-	spec->input_mux.num_items = 0;
-	spec->pstate_nids = stac9200_pstate_nids;
-	spec->num_pstates = 3;
-	spec->pin_nids = stac9200_pin_nids;
-#ifdef STAC_TEST
-	spec->pin_configs = stac9200_pin_configs;
-#endif
-	spec->num_pins = 8;
-	spec->init = stac9200_ch2_init;
+
+	spec->init = stac9200_core_init;
 	spec->mixer = stac9200_mixer;
-	spec->playback_nid = 0x02;
-	spec->capture_nid = 0x03;
+
+	err = stac9200_parse_auto_config(codec);
+	if (err < 0) {
+		stac92xx_free(codec);
+		return err;
+	}
 
 	codec->patch_ops = stac92xx_patch_ops;
 
@@ -618,6 +955,7 @@ static int patch_stac9200(struct hda_codec *codec)
 static int patch_stac922x(struct hda_codec *codec)
 {
 	struct sigmatel_spec *spec;
+	int err;
 
 	spec  = kcalloc(1, sizeof(*spec), GFP_KERNEL);
 	if (spec == NULL)
@@ -625,26 +963,26 @@ static int patch_stac922x(struct hda_codec *codec)
 
 	codec->spec = spec;
 
-	spec->multiout.max_channels = 2;
-	spec->multiout.num_dacs = 4;
-	spec->multiout.dac_nids = stac922x_dac_nids;
-	spec->multiout.dig_out_nid = 0x08;
-	spec->dig_in_nid = 0x09;
-	spec->adc_nids = stac922x_adc_nids;
-	spec->mux_nids = stac922x_mux_nids;
-	spec->num_muxes = 2;
-	spec->input_mux.num_items = 0;
-	spec->pstate_nids = stac922x_pstate_nids;
-	spec->num_pstates = 8;
-	spec->pin_nids = stac922x_pin_nids;
 #ifdef STAC_TEST
+	spec->num_pins = 10;
+	spec->pin_nids = stac922x_pin_nids;
 	spec->pin_configs = stac922x_pin_configs;
+	stac92xx_set_config_regs(codec);
 #endif
-	spec->num_pins = 10;
-	spec->init = stac922x_ch2_init;
+	spec->adc_nids = stac922x_adc_nids;
+	spec->mux_nids = stac922x_mux_nids;
+	spec->num_muxes = 2;
+
+	spec->init = stac922x_core_init;
 	spec->mixer = stac922x_mixer;
-	spec->playback_nid = 0x02;
-	spec->capture_nid = 0x06;
+
+	spec->multiout.dac_nids = spec->dac_nids;
+
+	err = stac922x_parse_auto_config(codec);
+	if (err < 0) {
+		stac92xx_free(codec);
+		return err;
+	}
 
 	codec->patch_ops = stac92xx_patch_ops;
 
diff --git a/sound/pci/intel8x0.c b/sound/pci/intel8x0.c
index cc16f95f9ce..d7af3e47443 100644
--- a/sound/pci/intel8x0.c
+++ b/sound/pci/intel8x0.c
@@ -424,6 +424,7 @@ struct _snd_intel8x0 {
 	unsigned xbox: 1;		/* workaround for Xbox AC'97 detection */
 
 	int spdif_idx;	/* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
+	unsigned int sdm_saved;	/* SDM reg value */
 
 	ac97_bus_t *ac97_bus;
 	ac97_t *ac97[3];
@@ -2373,6 +2374,11 @@ static int intel8x0_suspend(snd_card_t *card, pm_message_t state)
 	for (i = 0; i < 3; i++)
 		if (chip->ac97[i])
 			snd_ac97_suspend(chip->ac97[i]);
+	if (chip->device_type == DEVICE_INTEL_ICH4)
+		chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
+
+	if (chip->irq >= 0)
+		free_irq(chip->irq, (void *)chip);
 	pci_disable_device(chip->pci);
 	return 0;
 }
@@ -2384,7 +2390,19 @@ static int intel8x0_resume(snd_card_t *card)
 
 	pci_enable_device(chip->pci);
 	pci_set_master(chip->pci);
-	snd_intel8x0_chip_init(chip, 0);
+	request_irq(chip->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip);
+	synchronize_irq(chip->irq);
+	snd_intel8x0_chip_init(chip, 1);
+
+	/* re-initialize mixer stuff */
+	if (chip->device_type == DEVICE_INTEL_ICH4) {
+		/* enable separate SDINs for ICH4 */
+		iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
+		/* use slot 10/11 for SPDIF */
+		iputdword(chip, ICHREG(GLOB_CNT),
+			  (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
+			  ICH_PCM_SPDIF_1011);
+	}
 
 	/* refill nocache */
 	if (chip->fix_nocache)
@@ -2451,8 +2469,7 @@ static void __devinit intel8x0_measure_ac97_clock(intel8x0_t *chip)
 	}
 	do_gettimeofday(&start_time);
 	spin_unlock_irq(&chip->reg_lock);
-	set_current_state(TASK_UNINTERRUPTIBLE);
-	schedule_timeout(HZ / 20);
+	msleep(50);
 	spin_lock_irq(&chip->reg_lock);
 	/* check the position */
 	pos = ichdev->fragsize1;
diff --git a/sound/pci/maestro3.c b/sound/pci/maestro3.c
index 096f1513285..39b5e7db154 100644
--- a/sound/pci/maestro3.c
+++ b/sound/pci/maestro3.c
@@ -1050,27 +1050,22 @@ static struct m3_hv_quirk m3_hv_quirk_list[] = {
  * lowlevel functions
  */
 
-#define big_mdelay(msec) do {\
-	set_current_state(TASK_UNINTERRUPTIBLE);\
-	schedule_timeout(((msec) * HZ) / 1000);\
-} while (0)
-	
-inline static void snd_m3_outw(m3_t *chip, u16 value, unsigned long reg)
+static inline void snd_m3_outw(m3_t *chip, u16 value, unsigned long reg)
 {
 	outw(value, chip->iobase + reg);
 }
 
-inline static u16 snd_m3_inw(m3_t *chip, unsigned long reg)
+static inline u16 snd_m3_inw(m3_t *chip, unsigned long reg)
 {
 	return inw(chip->iobase + reg);
 }
 
-inline static void snd_m3_outb(m3_t *chip, u8 value, unsigned long reg)
+static inline void snd_m3_outb(m3_t *chip, u8 value, unsigned long reg)
 {
 	outb(value, chip->iobase + reg);
 }
 
-inline static u8 snd_m3_inb(m3_t *chip, unsigned long reg)
+static inline u8 snd_m3_inb(m3_t *chip, unsigned long reg)
 {
 	return inb(chip->iobase + reg);
 }
@@ -1096,7 +1091,7 @@ static void snd_m3_assp_write(m3_t *chip, u16 region, u16 index, u16 data)
 static void snd_m3_assp_halt(m3_t *chip)
 {
 	chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
-	big_mdelay(10);
+	msleep(10);
 	snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
 }
 
@@ -2108,9 +2103,9 @@ static void snd_m3_ac97_reset(m3_t *chip)
 	 */
 	tmp = inw(io + RING_BUS_CTRL_A);
 	outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
-	big_mdelay(20);
+	msleep(20);
 	outw(tmp, io + RING_BUS_CTRL_A);
-	big_mdelay(50);
+	msleep(50);
 #endif
 }
 
@@ -2525,9 +2520,13 @@ static void
 snd_m3_enable_ints(m3_t *chip)
 {
 	unsigned long io = chip->iobase;
+	unsigned short val;
 
 	/* TODO: MPU401 not supported yet */
-	outw(ASSP_INT_ENABLE | HV_INT_ENABLE /*| MPU401_INT_ENABLE*/, io + HOST_INT_CTRL);
+	val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
+	if (chip->hv_quirk && (chip->hv_quirk->config & HV_CTRL_ENABLE))
+		val |= HV_INT_ENABLE;
+	outw(val, io + HOST_INT_CTRL);
 	outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
 	     io + ASSP_CONTROL_C);
 }
@@ -2589,7 +2588,7 @@ static int m3_suspend(snd_card_t *card, pm_message_t state)
 	snd_pcm_suspend_all(chip->pcm);
 	snd_ac97_suspend(chip->ac97);
 
-	big_mdelay(10); /* give the assp a chance to idle.. */
+	msleep(10); /* give the assp a chance to idle.. */
 
 	snd_m3_assp_halt(chip);
 
@@ -2697,6 +2696,8 @@ snd_m3_create(snd_card_t *card, struct pci_dev *pci,
 	}
 
 	spin_lock_init(&chip->reg_lock);
+	spin_lock_init(&chip->ac97_lock);
+
 	switch (pci->device) {
 	case PCI_DEVICE_ID_ESS_ALLEGRO:
 	case PCI_DEVICE_ID_ESS_ALLEGRO_1:
@@ -2765,6 +2766,8 @@ snd_m3_create(snd_card_t *card, struct pci_dev *pci,
 	snd_m3_assp_init(chip);
 	snd_m3_amp_enable(chip, 1);
 
+	tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip);
+
 	if (request_irq(pci->irq, snd_m3_interrupt, SA_INTERRUPT|SA_SHIRQ,
 			card->driver, (void *)chip)) {
 		snd_printk("unable to grab IRQ %d\n", pci->irq);
@@ -2786,9 +2789,6 @@ snd_m3_create(snd_card_t *card, struct pci_dev *pci,
 		return err;
 	}
 
-	spin_lock_init(&chip->ac97_lock);
-	tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip);
-
 	if ((err = snd_m3_mixer(chip)) < 0)
 		return err;
 
diff --git a/sound/pci/mixart/mixart.c b/sound/pci/mixart/mixart.c
index 082c0d0f73d..6c868d91363 100644
--- a/sound/pci/mixart/mixart.c
+++ b/sound/pci/mixart/mixart.c
@@ -445,9 +445,9 @@ static int snd_mixart_trigger(snd_pcm_substream_t *subs, int cmd)
 
 static int mixart_sync_nonblock_events(mixart_mgr_t *mgr)
 {
-	int timeout = HZ;
+	unsigned long timeout = jiffies + HZ;
 	while (atomic_read(&mgr->msg_processed) > 0) {
-		if (! timeout--) {
+		if (time_after(jiffies, timeout)) {
 			snd_printk(KERN_ERR "mixart: cannot process nonblock events!\n");
 			return -EBUSY;
 		}
diff --git a/sound/pci/nm256/nm256.c b/sound/pci/nm256/nm256.c
index 8a52091f855..7eb20b8f89f 100644
--- a/sound/pci/nm256/nm256.c
+++ b/sound/pci/nm256/nm256.c
@@ -285,43 +285,43 @@ MODULE_DEVICE_TABLE(pci, snd_nm256_ids);
  * lowlvel stuffs
  */
 
-inline static u8
+static inline u8
 snd_nm256_readb(nm256_t *chip, int offset)
 {
 	return readb(chip->cport + offset);
 }
 
-inline static u16
+static inline u16
 snd_nm256_readw(nm256_t *chip, int offset)
 {
 	return readw(chip->cport + offset);
 }
 
-inline static u32
+static inline u32
 snd_nm256_readl(nm256_t *chip, int offset)
 {
 	return readl(chip->cport + offset);
 }
 
-inline static void
+static inline void
 snd_nm256_writeb(nm256_t *chip, int offset, u8 val)
 {
 	writeb(val, chip->cport + offset);
 }
 
-inline static void
+static inline void
 snd_nm256_writew(nm256_t *chip, int offset, u16 val)
 {
 	writew(val, chip->cport + offset);
 }
 
-inline static void
+static inline void
 snd_nm256_writel(nm256_t *chip, int offset, u32 val)
 {
 	writel(val, chip->cport + offset);
 }
 
-inline static void
+static inline void
 snd_nm256_write_buffer(nm256_t *chip, void *src, int offset, int size)
 {
 	offset -= chip->buffer_start;
@@ -926,7 +926,7 @@ snd_nm256_init_chip(nm256_t *chip)
 }
 
 
-inline static void
+static inline void
 snd_nm256_intr_check(nm256_t *chip)
 {
 	if (chip->badintrcount++ > 1000) {
diff --git a/sound/pci/rme9652/hdsp.c b/sound/pci/rme9652/hdsp.c
index a673cc438b9..796621de500 100644
--- a/sound/pci/rme9652/hdsp.c
+++ b/sound/pci/rme9652/hdsp.c
@@ -445,6 +445,7 @@ struct _hdsp {
 	u32                   control2_register;     /* cached value */
 	u32                   creg_spdif;
 	u32                   creg_spdif_stream;
+	int                   clock_source_locked;
 	char                 *card_name;	     /* digiface/multiface */
 	HDSP_IO_Type          io_type;               /* ditto, but for code use */
         unsigned short        firmware_rev;
@@ -678,8 +679,7 @@ static int snd_hdsp_load_firmware_from_cache(hdsp_t *hdsp) {
 		}
 
 		if ((1000 / HZ) < 3000) {
-			set_current_state(TASK_UNINTERRUPTIBLE);
-			schedule_timeout((3000 * HZ + 999) / 1000);
+			ssleep(3);
 		} else {
 			mdelay(3000);
 		}
@@ -2095,6 +2095,34 @@ static int snd_hdsp_put_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_val
 	return change;
 }
 
+static int snd_hdsp_info_clock_source_lock(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
+{
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+	uinfo->count = 1;
+	uinfo->value.integer.min = 0;
+	uinfo->value.integer.max = 1;
+	return 0;
+}
+
+static int snd_hdsp_get_clock_source_lock(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
+{
+	hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
+	
+	ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
+	return 0;
+}
+
+static int snd_hdsp_put_clock_source_lock(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
+{
+	hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
+	int change;
+
+	change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
+	if (change)
+		hdsp->clock_source_locked = ucontrol->value.integer.value[0];
+	return change;
+}
+
 #define HDSP_DA_GAIN(xname, xindex) \
 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
   .name = xname, \
@@ -3117,6 +3145,15 @@ HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0),
 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0),
 /* 'Sample Clock Source' complies with the alsa control naming scheme */ 
 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
+{
+	/* FIXME: should be PCM or MIXER? */
+	/* .iface = SNDRV_CTL_ELEM_IFACE_PCM, */
+	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+	.name = "Sample Clock Source Locking",
+	.info = snd_hdsp_info_clock_source_lock,
+	.get = snd_hdsp_get_clock_source_lock,
+	.put = snd_hdsp_put_clock_source_lock,
+},
 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
@@ -3349,6 +3386,7 @@ snd_hdsp_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
 	snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
 
 	snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
+	snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
 		
 	snd_iprintf(buffer, "\n");
 
@@ -3853,13 +3891,14 @@ static int snd_hdsp_hw_params(snd_pcm_substream_t *substream,
 	 */
 
 	spin_lock_irq(&hdsp->lock);
-	if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
-		spin_unlock_irq(&hdsp->lock);
-		_snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
-		return err;
-	} else {
-		spin_unlock_irq(&hdsp->lock);
+	if (! hdsp->clock_source_locked) {
+		if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
+			spin_unlock_irq(&hdsp->lock);
+			_snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
+			return err;
+		}
 	}
+	spin_unlock_irq(&hdsp->lock);
 
 	if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
 		_snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
@@ -4284,13 +4323,17 @@ static int snd_hdsp_playback_open(snd_pcm_substream_t *substream)
 
 	snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
 	snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
-	if (hdsp->io_type == H9632) {
-		runtime->hw.channels_min = hdsp->qs_out_channels;
-		runtime->hw.channels_max = hdsp->ss_out_channels;
+	if (hdsp->clock_source_locked) {
+		runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
+	} else if (hdsp->io_type == H9632) {
 		runtime->hw.rate_max = 192000;
 		runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
 		snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
 	}
+	if (hdsp->io_type == H9632) {
+		runtime->hw.channels_min = hdsp->qs_out_channels;
+		runtime->hw.channels_max = hdsp->ss_out_channels;
+	}	
 	
 	snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
 			     snd_hdsp_hw_rule_out_channels, hdsp,
@@ -5036,8 +5079,7 @@ static int __devinit snd_hdsp_create(snd_card_t *card,
 	if (!is_9652 && !is_9632) {
 		/* we wait 2 seconds to let freshly inserted cardbus cards do their hardware init */
  		if ((1000 / HZ) < 2000) {
-			set_current_state(TASK_UNINTERRUPTIBLE);
-			schedule_timeout((2000 * HZ + 999) / 1000);
+			ssleep(2);
 		} else {
 			mdelay(2000);
 		}
diff --git a/sound/pci/rme9652/rme9652.c b/sound/pci/rme9652/rme9652.c
index f3037402d58..1bc9d0df851 100644
--- a/sound/pci/rme9652/rme9652.c
+++ b/sound/pci/rme9652/rme9652.c
@@ -1470,7 +1470,7 @@ static int snd_rme9652_get_tc_valid(snd_kcontrol_t * kcontrol, snd_ctl_elem_valu
 	return 0;
 }
 
-#if ALSA_HAS_STANDARD_WAY_OF_RETURNING_TIMECODE
+#ifdef ALSA_HAS_STANDARD_WAY_OF_RETURNING_TIMECODE
 
 /* FIXME: this routine needs a port to the new control API --jk */
 
diff --git a/sound/pci/trident/trident_main.c b/sound/pci/trident/trident_main.c
index ccd5ca2ba16..29d89bfba0a 100644
--- a/sound/pci/trident/trident_main.c
+++ b/sound/pci/trident/trident_main.c
@@ -472,6 +472,7 @@ void snd_trident_write_voice_regs(trident_t * trident,
 		break;
 	default:
 		snd_BUG();
+		return;
 	}
 
 	outb(voice->number, TRID_REG(trident, T4D_LFO_GC_CIR));
@@ -3152,8 +3153,7 @@ static int snd_trident_gameport_open(struct gameport *gameport, int mode)
 	switch (mode) {
 		case GAMEPORT_MODE_COOKED:
 			outb(GAMEPORT_MODE_ADC, TRID_REG(chip, GAMEPORT_GCR));
-			set_current_state(TASK_UNINTERRUPTIBLE);
-			schedule_timeout(1 + 20 * HZ / 1000); /* 20msec */
+			msleep(20);
 			return 0;
 		case GAMEPORT_MODE_RAW:
 			outb(0, TRID_REG(chip, GAMEPORT_GCR));
@@ -3204,7 +3204,7 @@ static inline void snd_trident_free_gameport(trident_t *chip) { }
 /*
  * delay for 1 tick
  */
-inline static void do_delay(trident_t *chip)
+static inline void do_delay(trident_t *chip)
 {
 	set_current_state(TASK_UNINTERRUPTIBLE);
 	schedule_timeout(1);
diff --git a/sound/pci/trident/trident_memory.c b/sound/pci/trident/trident_memory.c
index 6cc282681e0..333d3790692 100644
--- a/sound/pci/trident/trident_memory.c
+++ b/sound/pci/trident/trident_memory.c
@@ -118,7 +118,7 @@ static inline void set_silent_tlb(trident_t *trident, int page)
 #endif /* PAGE_SIZE */
 
 /* calculate buffer pointer from offset address */
-inline static void *offset_ptr(trident_t *trident, int offset)
+static inline void *offset_ptr(trident_t *trident, int offset)
 {
 	char *ptr;
 	ptr = page_to_ptr(trident, get_aligned_page(offset));
diff --git a/sound/pci/via82xx.c b/sound/pci/via82xx.c
index 42c48f0ce8e..4889600387c 100644
--- a/sound/pci/via82xx.c
+++ b/sound/pci/via82xx.c
@@ -547,8 +547,7 @@ static void snd_via82xx_codec_wait(ac97_t *ac97)
 	int err;
 	err = snd_via82xx_codec_ready(chip, ac97->num);
 	/* here we need to wait fairly for long time.. */
-	set_current_state(TASK_UNINTERRUPTIBLE);
-	schedule_timeout(HZ/2);
+	msleep(500);
 }
 
 static void snd_via82xx_codec_write(ac97_t *ac97,
@@ -1847,7 +1846,7 @@ static void __devinit snd_via82xx_proc_init(via82xx_t *chip)
 static int snd_via82xx_chip_init(via82xx_t *chip)
 {
 	unsigned int val;
-	int max_count;
+	unsigned long end_time;
 	unsigned char pval;
 
 #if 0 /* broken on K7M? */
@@ -1889,14 +1888,14 @@ static int snd_via82xx_chip_init(via82xx_t *chip)
 	}
 
 	/* wait until codec ready */
-	max_count = ((3 * HZ) / 4) + 1;
+	end_time = jiffies + msecs_to_jiffies(750);
 	do {
 		pci_read_config_byte(chip->pci, VIA_ACLINK_STAT, &pval);
 		if (pval & VIA_ACLINK_C00_READY) /* primary codec ready */
 			break;
 		set_current_state(TASK_UNINTERRUPTIBLE);
 		schedule_timeout(1);
-	} while (--max_count > 0);
+	} while (time_before(jiffies, end_time));
 
 	if ((val = snd_via82xx_codec_xread(chip)) & VIA_REG_AC97_BUSY)
 		snd_printk("AC'97 codec is not ready [0x%x]\n", val);
@@ -1905,7 +1904,7 @@ static int snd_via82xx_chip_init(via82xx_t *chip)
 	snd_via82xx_codec_xwrite(chip, VIA_REG_AC97_READ |
 				 VIA_REG_AC97_SECONDARY_VALID |
 				 (VIA_REG_AC97_CODEC_ID_SECONDARY << VIA_REG_AC97_CODEC_ID_SHIFT));
-	max_count = ((3 * HZ) / 4) + 1;
+	end_time = jiffies + msecs_to_jiffies(750);
 	snd_via82xx_codec_xwrite(chip, VIA_REG_AC97_READ |
 				 VIA_REG_AC97_SECONDARY_VALID |
 				 (VIA_REG_AC97_CODEC_ID_SECONDARY << VIA_REG_AC97_CODEC_ID_SHIFT));
@@ -1916,7 +1915,7 @@ static int snd_via82xx_chip_init(via82xx_t *chip)
 		}
 		set_current_state(TASK_INTERRUPTIBLE);
 		schedule_timeout(1);
-	} while (--max_count > 0);
+	} while (time_before(jiffies, end_time));
 	/* This is ok, the most of motherboards have only one codec */
 
       __ac97_ok2:
@@ -2178,7 +2177,7 @@ static int __devinit check_dxs_list(struct pci_dev *pci)
 		{ .subvendor = 0x147b, .subdevice = 0x1413, .action = VIA_DXS_ENABLE }, /* ABIT KV8 Pro */
 		{ .subvendor = 0x147b, .subdevice = 0x1415, .action = VIA_DXS_NO_VRA }, /* Abit AV8 */
 		{ .subvendor = 0x14ff, .subdevice = 0x0403, .action = VIA_DXS_ENABLE }, /* Twinhead mobo */
-		{ .subvendor = 0x14ff, .subdevice = 0x0408, .action = VIA_DXS_NO_VRA }, /* Twinhead mobo */
+		{ .subvendor = 0x14ff, .subdevice = 0x0408, .action = VIA_DXS_SRC }, /* Twinhead laptop */
 		{ .subvendor = 0x1584, .subdevice = 0x8120, .action = VIA_DXS_ENABLE }, /* Gericom/Targa/Vobis/Uniwill laptop */
 		{ .subvendor = 0x1584, .subdevice = 0x8123, .action = VIA_DXS_NO_VRA }, /* Uniwill (Targa Visionary XP-210) */
 		{ .subvendor = 0x161f, .subdevice = 0x202b, .action = VIA_DXS_NO_VRA }, /* Amira Note book */
@@ -2187,6 +2186,7 @@ static int __devinit check_dxs_list(struct pci_dev *pci)
 		{ .subvendor = 0x1695, .subdevice = 0x3005, .action = VIA_DXS_ENABLE }, /* EPoX EP-8K9A */
 		{ .subvendor = 0x1849, .subdevice = 0x3059, .action = VIA_DXS_NO_VRA }, /* ASRock K7VM2 */
 		{ .subvendor = 0x1919, .subdevice = 0x200a, .action = VIA_DXS_NO_VRA }, /* Soltek SL-K8Tpro-939 */
+		{ .subvendor = 0x4005, .subdevice = 0x4710, .action = VIA_DXS_SRC },	/* MSI K7T266 Pro2 (MS-6380 V2.0) BIOS 3.7 */
 		{ } /* terminator */
 	};
 	struct dxs_whitelist *w;
diff --git a/sound/pci/via82xx_modem.c b/sound/pci/via82xx_modem.c
index 5896d289f9a..4a9779cc973 100644
--- a/sound/pci/via82xx_modem.c
+++ b/sound/pci/via82xx_modem.c
@@ -408,8 +408,7 @@ static void snd_via82xx_codec_wait(ac97_t *ac97)
 	int err;
 	err = snd_via82xx_codec_ready(chip, ac97->num);
 	/* here we need to wait fairly for long time.. */
-	set_current_state(TASK_UNINTERRUPTIBLE);
-	schedule_timeout(HZ/2);
+	msleep(500);
 }
 
 static void snd_via82xx_codec_write(ac97_t *ac97,
@@ -923,7 +922,7 @@ static void __devinit snd_via82xx_proc_init(via82xx_t *chip)
 static int snd_via82xx_chip_init(via82xx_t *chip)
 {
 	unsigned int val;
-	int max_count;
+	unsigned long end_time;
 	unsigned char pval;
 
 	pci_read_config_byte(chip->pci, VIA_MC97_CTRL, &pval);
@@ -962,14 +961,14 @@ static int snd_via82xx_chip_init(via82xx_t *chip)
 	}
 
 	/* wait until codec ready */
-	max_count = ((3 * HZ) / 4) + 1;
+	end_time = jiffies + msecs_to_jiffies(750);
 	do {
 		pci_read_config_byte(chip->pci, VIA_ACLINK_STAT, &pval);
 		if (pval & VIA_ACLINK_C00_READY) /* primary codec ready */
 			break;
 		set_current_state(TASK_UNINTERRUPTIBLE);
 		schedule_timeout(1);
-	} while (--max_count > 0);
+	} while (time_before(jiffies, end_time));
 
 	if ((val = snd_via82xx_codec_xread(chip)) & VIA_REG_AC97_BUSY)
 		snd_printk("AC'97 codec is not ready [0x%x]\n", val);
@@ -977,7 +976,7 @@ static int snd_via82xx_chip_init(via82xx_t *chip)
 	snd_via82xx_codec_xwrite(chip, VIA_REG_AC97_READ |
 				 VIA_REG_AC97_SECONDARY_VALID |
 				 (VIA_REG_AC97_CODEC_ID_SECONDARY << VIA_REG_AC97_CODEC_ID_SHIFT));
-	max_count = ((3 * HZ) / 4) + 1;
+	end_time = jiffies + msecs_to_jiffies(750);
 	snd_via82xx_codec_xwrite(chip, VIA_REG_AC97_READ |
 				 VIA_REG_AC97_SECONDARY_VALID |
 				 (VIA_REG_AC97_CODEC_ID_SECONDARY << VIA_REG_AC97_CODEC_ID_SHIFT));
@@ -988,7 +987,7 @@ static int snd_via82xx_chip_init(via82xx_t *chip)
 		}
 		set_current_state(TASK_INTERRUPTIBLE);
 		schedule_timeout(1);
-	} while (--max_count > 0);
+	} while (time_before(jiffies, end_time));
 	/* This is ok, the most of motherboards have only one codec */
 
       __ac97_ok2:
diff --git a/sound/pci/vx222/vx222_ops.c b/sound/pci/vx222/vx222_ops.c
index 683e9799976..967bd5e6b23 100644
--- a/sound/pci/vx222/vx222_ops.c
+++ b/sound/pci/vx222/vx222_ops.c
@@ -82,7 +82,7 @@ static int vx2_reg_index[VX_REG_MAX] = {
 	[VX_GPIOC]	= 0,	/* on the PLX */
 };
 
-inline static unsigned long vx2_reg_addr(vx_core_t *_chip, int reg)
+static inline unsigned long vx2_reg_addr(vx_core_t *_chip, int reg)
 {
 	struct snd_vx222 *chip = (struct snd_vx222 *)_chip;
 	return chip->port[vx2_reg_index[reg]] + vx2_reg_offset[reg];
@@ -235,7 +235,7 @@ static void vx2_setup_pseudo_dma(vx_core_t *chip, int do_write)
 /*
  * vx_release_pseudo_dma - disable the pseudo-DMA mode
  */
-inline static void vx2_release_pseudo_dma(vx_core_t *chip)
+static inline void vx2_release_pseudo_dma(vx_core_t *chip)
 {
 	/* HREQ pin disabled. */
 	vx_outl(chip, ICR, 0);
diff --git a/sound/pci/ymfpci/ymfpci_main.c b/sound/pci/ymfpci/ymfpci_main.c
index 2ae79610ecb..d54f88a1b52 100644
--- a/sound/pci/ymfpci/ymfpci_main.c
+++ b/sound/pci/ymfpci/ymfpci_main.c
@@ -84,16 +84,16 @@ static inline void snd_ymfpci_writel(ymfpci_t *chip, u32 offset, u32 val)
 
 static int snd_ymfpci_codec_ready(ymfpci_t *chip, int secondary)
 {
-	signed long end_time;
+	unsigned long end_time;
 	u32 reg = secondary ? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR;
 	
-	end_time = (jiffies + ((3 * HZ) / 4)) + 1;
+	end_time = jiffies + msecs_to_jiffies(750);
 	do {
 		if ((snd_ymfpci_readw(chip, reg) & 0x8000) == 0)
 			return 0;
 		set_current_state(TASK_UNINTERRUPTIBLE);
 		schedule_timeout(1);
-	} while (end_time - (signed long)jiffies >= 0);
+	} while (time_before(jiffies, end_time));
 	snd_printk("codec_ready: codec %i is not ready [0x%x]\n", secondary, snd_ymfpci_readw(chip, reg));
 	return -EBUSY;
 }
diff --git a/sound/pcmcia/Kconfig b/sound/pcmcia/Kconfig
index 3611e298834..5d1b0b762ef 100644
--- a/sound/pcmcia/Kconfig
+++ b/sound/pcmcia/Kconfig
@@ -8,23 +8,12 @@ config SND_VXPOCKET
 	depends on SND && PCMCIA && ISA
 	select SND_VX_LIB
 	help
-	  Say Y here to include support for Digigram VXpocket
-	  soundcards.
+	  Say Y here to include support for Digigram VXpocket and
+	  VXpocket 440 soundcards.
 
 	  To compile this driver as a module, choose M here: the module
 	  will be called snd-vxpocket.
 
-config SND_VXP440
-	tristate "Digigram VXpocket 440"
-	depends on SND && PCMCIA && ISA
-	select SND_VX_LIB
-	help
-	  Say Y here to include support for Digigram VXpocket 440
-	  soundcards.
-
-	  To compile this driver as a module, choose M here: the module
-	  will be called snd-vxp440.
-
 config SND_PDAUDIOCF
 	tristate "Sound Core PDAudioCF"
 	depends on SND && PCMCIA && ISA
diff --git a/sound/pcmcia/vx/Makefile b/sound/pcmcia/vx/Makefile
index f35dfa1af09..54971f01e96 100644
--- a/sound/pcmcia/vx/Makefile
+++ b/sound/pcmcia/vx/Makefile
@@ -3,9 +3,6 @@
 # Copyright (c) 2001 by Jaroslav Kysela <perex@suse.cz>
 #
 
-snd-vx-cs-objs := vx_entry.o vxp_ops.o vxp_mixer.o
-snd-vxpocket-objs := vxpocket.o
-snd-vxp440-objs := vxp440.o
+snd-vxpocket-objs := vxpocket.o vxp_ops.o vxp_mixer.o
 
-obj-$(CONFIG_SND_VXPOCKET) += snd-vxpocket.o snd-vx-cs.o
-obj-$(CONFIG_SND_VXP440) += snd-vxp440.o snd-vx-cs.o
+obj-$(CONFIG_SND_VXPOCKET) += snd-vxpocket.o
diff --git a/sound/pcmcia/vx/vx_entry.c b/sound/pcmcia/vx/vx_entry.c
deleted file mode 100644
index df7a39ba968..00000000000
--- a/sound/pcmcia/vx/vx_entry.c
+++ /dev/null
@@ -1,375 +0,0 @@
-/*
- * Driver for Digigram VXpocket soundcards
- *
- * PCMCIA entry part
- *
- * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
- *
- *   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program; if not, write to the Free Software
- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#include <sound/driver.h>
-#include <sound/core.h>
-#include "vxpocket.h"
-#include <pcmcia/ciscode.h>
-#include <pcmcia/cisreg.h>
-
-
-MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
-MODULE_DESCRIPTION("Common routines for Digigram PCMCIA VX drivers");
-MODULE_LICENSE("GPL");
-
-/*
- * prototypes
- */
-static void vxpocket_config(dev_link_t *link);
-
-
-static void vxpocket_release(dev_link_t *link)
-{
-	if (link->state & DEV_CONFIG) {
-		/* release cs resources */
-		pcmcia_release_configuration(link->handle);
-		pcmcia_release_io(link->handle, &link->io);
-		pcmcia_release_irq(link->handle, &link->irq);
-		link->state &= ~DEV_CONFIG;
-	}
-}
-
-/*
- * destructor
- */
-static int snd_vxpocket_free(vx_core_t *chip)
-{
-	struct snd_vxpocket *vxp = (struct snd_vxpocket *)chip;
-	struct snd_vxp_entry *hw;
-	dev_link_t *link = &vxp->link;
-
-	vxpocket_release(link);
-
-	/* Break the link with Card Services */
-	if (link->handle)
-		pcmcia_deregister_client(link->handle);
-
-	hw = vxp->hw_entry;
-	if (hw)
-		hw->card_list[vxp->index] = NULL;
-	chip->card = NULL;
-	kfree(chip->dev);
-
-	snd_vx_free_firmware(chip);
-	kfree(chip);
-	return 0;
-}
-
-static int snd_vxpocket_dev_free(snd_device_t *device)
-{
-	vx_core_t *chip = device->device_data;
-	return snd_vxpocket_free(chip);
-}
-
-/*
- * snd_vxpocket_attach - attach callback for cs
- * @hw: the hardware information
- */
-dev_link_t *snd_vxpocket_attach(struct snd_vxp_entry *hw)
-{
-	client_reg_t client_reg;	/* Register with cardmgr */
-	dev_link_t *link;		/* Info for cardmgr */
-	int i, ret;
-	vx_core_t *chip;
-	struct snd_vxpocket *vxp;
-	snd_card_t *card;
-	static snd_device_ops_t ops = {
-		.dev_free =	snd_vxpocket_dev_free,
-	};
-
-	snd_printdd(KERN_DEBUG "vxpocket_attach called\n");
-	/* find an empty slot from the card list */
-	for (i = 0; i < SNDRV_CARDS; i++) {
-		if (! hw->card_list[i])
-			break;
-	}
-	if (i >= SNDRV_CARDS) {
-		snd_printk(KERN_ERR "vxpocket: too many cards found\n");
-		return NULL;
-	}
-	if (! hw->enable_table[i])
-		return NULL; /* disabled explicitly */
-
-	/* ok, create a card instance */
-	card = snd_card_new(hw->index_table[i], hw->id_table[i], THIS_MODULE, 0);
-	if (card == NULL) {
-		snd_printk(KERN_ERR "vxpocket: cannot create a card instance\n");
-		return NULL;
-	}
-
-	chip = snd_vx_create(card, hw->hardware, hw->ops,
-			     sizeof(struct snd_vxpocket) - sizeof(vx_core_t));
-	if (! chip)
-		return NULL;
-
-#ifdef SND_VX_FW_LOADER
-	/* fake a device here since pcmcia doesn't give a valid device... */
-	chip->dev = kcalloc(1, sizeof(*chip->dev), GFP_KERNEL);
-	if (! chip->dev) {
-		snd_printk(KERN_ERR "vxp: can't malloc chip->dev\n");
-		kfree(chip);
-		snd_card_free(card);
-		return NULL;
-	}
-	device_initialize(chip->dev);
-	sprintf(chip->dev->bus_id, "vxpocket%d", i);
-#endif
-
-	if (snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops) < 0) {
-		kfree(chip);
-		snd_card_free(card);
-		return NULL;
-	}
-
-	vxp = (struct snd_vxpocket *)chip;
-	vxp->index = i;
-	vxp->hw_entry = hw;
-	chip->ibl.size = hw->ibl[i];
-	hw->card_list[i] = chip;
-
-	link = &vxp->link;
-	link->priv = chip;
-
-	link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
-	link->io.NumPorts1 = 16;
-
-	link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;
-	// link->irq.Attributes = IRQ_TYPE_DYNAMIC_SHARING|IRQ_FIRST_SHARED;
-
-	link->irq.IRQInfo1 = IRQ_LEVEL_ID;
-	link->irq.Handler = &snd_vx_irq_handler;
-	link->irq.Instance = chip;
-
-	link->conf.Attributes = CONF_ENABLE_IRQ;
-	link->conf.Vcc = 50;
-	link->conf.IntType = INT_MEMORY_AND_IO;
-	link->conf.ConfigIndex = 1;
-	link->conf.Present = PRESENT_OPTION;
-
-	/* Register with Card Services */
-	memset(&client_reg, 0, sizeof(client_reg));
-	client_reg.dev_info = hw->dev_info;
-	client_reg.Version = 0x0210;
-	client_reg.event_callback_args.client_data = link;
-
-	ret = pcmcia_register_client(&link->handle, &client_reg);
-	if (ret != CS_SUCCESS) {
-		cs_error(link->handle, RegisterClient, ret);
-		snd_card_free(card);
-		return NULL;
-	}
-
-	/* Chain drivers */
-	link->next = hw->dev_list;
-	hw->dev_list = link;
-
-	/* snd_card_set_pm_callback(card, snd_vxpocket_suspend, snd_vxpocket_resume, chip); */
-
-	return link;
-}
-
-
-/**
- * snd_vxpocket_assign_resources - initialize the hardware and card instance.
- * @port: i/o port for the card
- * @irq: irq number for the card
- *
- * this function assigns the specified port and irq, boot the card,
- * create pcm and control instances, and initialize the rest hardware.
- *
- * returns 0 if successful, or a negative error code.
- */
-static int snd_vxpocket_assign_resources(vx_core_t *chip, int port, int irq)
-{
-	int err;
-	snd_card_t *card = chip->card;
-	struct snd_vxpocket *vxp = (struct snd_vxpocket *)chip;
-
-	snd_printdd(KERN_DEBUG "vxpocket assign resources: port = 0x%x, irq = %d\n", port, irq);
-	vxp->port = port;
-
-	sprintf(card->shortname, "Digigram %s", card->driver);
-	sprintf(card->longname, "%s at 0x%x, irq %i",
-		card->shortname, port, irq);
-
-	chip->irq = irq;
-
-	if ((err = snd_vx_setup_firmware(chip)) < 0)
-		return err;
-
-	return 0;
-}
-
-
-/*
- * snd_vxpocket_detach - detach callback for cs
- * @hw: the hardware information
- */
-void snd_vxpocket_detach(struct snd_vxp_entry *hw, dev_link_t *link)
-{
-	vx_core_t *chip;
-
-	if (! link)
-		return;
-
-	chip = link->priv;
-
-	snd_printdd(KERN_DEBUG "vxpocket_detach called\n");
-	/* Remove the interface data from the linked list */
-	if (hw) {
-		dev_link_t **linkp;
-		/* Locate device structure */
-		for (linkp = &hw->dev_list; *linkp; linkp = &(*linkp)->next)
-			if (*linkp == link) {
-				*linkp = link->next;
-				break;
-			}
-	}
-	chip->chip_status |= VX_STAT_IS_STALE; /* to be sure */
-	snd_card_disconnect(chip->card);
-	snd_card_free_in_thread(chip->card);
-}
-
-/*
- * configuration callback
- */
-
-#define CS_CHECK(fn, ret) \
-do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
-
-static void vxpocket_config(dev_link_t *link)
-{
-	client_handle_t handle = link->handle;
-	vx_core_t *chip = link->priv;
-	struct snd_vxpocket *vxp = (struct snd_vxpocket *)chip;
-	tuple_t tuple;
-	cisparse_t *parse = NULL;
-	u_short buf[32];
-	int last_fn, last_ret;
-
-	snd_printdd(KERN_DEBUG "vxpocket_config called\n");
-	parse = kmalloc(sizeof(*parse), GFP_KERNEL);
-	if (! parse) {
-		snd_printk(KERN_ERR "vx: cannot allocate\n");
-		return;
-	}
-	tuple.Attributes = 0;
-	tuple.TupleData = (cisdata_t *)buf;
-	tuple.TupleDataMax = sizeof(buf);
-	tuple.TupleOffset = 0;
-	tuple.DesiredTuple = CISTPL_CONFIG;
-	CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
-	CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
-	CS_CHECK(ParseTuple, pcmcia_parse_tuple(handle, &tuple, parse));
-	link->conf.ConfigBase = parse->config.base;
-	link->conf.Present = parse->config.rmask[0];
-
-	/* Configure card */
-	link->state |= DEV_CONFIG;
-
-	CS_CHECK(RequestIO, pcmcia_request_io(handle, &link->io));
-	CS_CHECK(RequestIRQ, pcmcia_request_irq(link->handle, &link->irq));
-	CS_CHECK(RequestConfiguration, pcmcia_request_configuration(link->handle, &link->conf));
-
-	if (snd_vxpocket_assign_resources(chip, link->io.BasePort1, link->irq.AssignedIRQ) < 0)
-		goto failed;
-
-	link->dev = &vxp->node;
-	link->state &= ~DEV_CONFIG_PENDING;
-	kfree(parse);
-	return;
-
-cs_failed:
-	cs_error(link->handle, last_fn, last_ret);
-failed:
-	pcmcia_release_configuration(link->handle);
-	pcmcia_release_io(link->handle, &link->io);
-	pcmcia_release_irq(link->handle, &link->irq);
-	link->state &= ~DEV_CONFIG;
-	kfree(parse);
-}
-
-
-/*
- * event callback
- */
-int vxpocket_event(event_t event, int priority, event_callback_args_t *args)
-{
-	dev_link_t *link = args->client_data;
-	vx_core_t *chip = link->priv;
-
-	switch (event) {
-	case CS_EVENT_CARD_REMOVAL:
-		snd_printdd(KERN_DEBUG "CARD_REMOVAL..\n");
-		link->state &= ~DEV_PRESENT;
-		if (link->state & DEV_CONFIG) {
-			chip->chip_status |= VX_STAT_IS_STALE;
-		}
-		break;
-	case CS_EVENT_CARD_INSERTION:
-		snd_printdd(KERN_DEBUG "CARD_INSERTION..\n");
-		link->state |= DEV_PRESENT | DEV_CONFIG_PENDING;
-		vxpocket_config(link);
-		break;
-#ifdef CONFIG_PM
-	case CS_EVENT_PM_SUSPEND:
-		snd_printdd(KERN_DEBUG "SUSPEND\n");
-		link->state |= DEV_SUSPEND;
-		if (chip && chip->card->pm_suspend) {
-			snd_printdd(KERN_DEBUG "snd_vx_suspend calling\n");
-			chip->card->pm_suspend(chip->card, PMSG_SUSPEND);
-		}
-		/* Fall through... */
-	case CS_EVENT_RESET_PHYSICAL:
-		snd_printdd(KERN_DEBUG "RESET_PHYSICAL\n");
-		if (link->state & DEV_CONFIG)
-			pcmcia_release_configuration(link->handle);
-		break;
-	case CS_EVENT_PM_RESUME:
-		snd_printdd(KERN_DEBUG "RESUME\n");
-		link->state &= ~DEV_SUSPEND;
-		/* Fall through... */
-	case CS_EVENT_CARD_RESET:
-		snd_printdd(KERN_DEBUG "CARD_RESET\n");
-		if (DEV_OK(link)) {
-			//struct snd_vxpocket *vxp = (struct snd_vxpocket *)chip;
-			snd_printdd(KERN_DEBUG "requestconfig...\n");
-			pcmcia_request_configuration(link->handle, &link->conf);
-			if (chip && chip->card->pm_resume) {
-				snd_printdd(KERN_DEBUG "calling snd_vx_resume\n");
-				chip->card->pm_resume(chip->card);
-			}
-		}
-		snd_printdd(KERN_DEBUG "resume done!\n");
-		break;
-#endif
-	}
-	return 0;
-}
-
-/*
- * exported stuffs
- */
-EXPORT_SYMBOL(snd_vxpocket_ops);
-EXPORT_SYMBOL(snd_vxpocket_attach);
-EXPORT_SYMBOL(vxpocket_event);
-EXPORT_SYMBOL(snd_vxpocket_detach);
diff --git a/sound/pcmcia/vx/vxp440.c b/sound/pcmcia/vx/vxp440.c
deleted file mode 100644
index 59190a83300..00000000000
--- a/sound/pcmcia/vx/vxp440.c
+++ /dev/null
@@ -1,14 +0,0 @@
-#define COMPILE_VXP440
-
-/*
- add the following as /etc/pcmcia/vxp440.conf:
-
-  device "snd-vxp440"
-    class "audio" module "snd-vxp440"
-
-  card "Digigram VX-POCKET440"
-    manfid 0x01f1, 0x0100
-    bind "snd-vxp440"
-*/
-
-#include "vxpocket.c"
diff --git a/sound/pcmcia/vx/vxp_ops.c b/sound/pcmcia/vx/vxp_ops.c
index ef673427160..6f15c3d03ab 100644
--- a/sound/pcmcia/vx/vxp_ops.c
+++ b/sound/pcmcia/vx/vxp_ops.c
@@ -49,7 +49,7 @@ static int vxp_reg_offset[VX_REG_MAX] = {
 };
 
 
-inline static unsigned long vxp_reg_addr(vx_core_t *_chip, int reg)
+static inline unsigned long vxp_reg_addr(vx_core_t *_chip, int reg)
 {
 	struct snd_vxpocket *chip = (struct snd_vxpocket *)_chip;
 	return chip->port + vxp_reg_offset[reg];
diff --git a/sound/pcmcia/vx/vxpocket.c b/sound/pcmcia/vx/vxpocket.c
index 62d6fa12814..3a82161d3b2 100644
--- a/sound/pcmcia/vx/vxpocket.c
+++ b/sound/pcmcia/vx/vxpocket.c
@@ -24,21 +24,17 @@
 #include <linux/moduleparam.h>
 #include <sound/core.h>
 #include "vxpocket.h"
+#include <pcmcia/ciscode.h>
+#include <pcmcia/cisreg.h>
 #include <sound/initval.h>
 
 /*
  */
 
-#ifdef COMPILE_VXP440
-#define CARD_NAME	"VXPocket440"
-#else
-#define CARD_NAME	"VXPocket"
-#endif
-
 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
-MODULE_DESCRIPTION("Digigram " CARD_NAME);
+MODULE_DESCRIPTION("Digigram VXPocket");
 MODULE_LICENSE("GPL");
-MODULE_SUPPORTED_DEVICE("{{Digigram," CARD_NAME "}}");
+MODULE_SUPPORTED_DEVICE("{{Digigram,VXPocket},{Digigram,VXPocket440}}");
 
 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;	/* Index 0-MAX */
 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;	/* ID for this card */
@@ -46,82 +42,405 @@ static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;	/* Enable switches */
 static int ibl[SNDRV_CARDS];
 
 module_param_array(index, int, NULL, 0444);
-MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
+MODULE_PARM_DESC(index, "Index value for VXPocket soundcard.");
 module_param_array(id, charp, NULL, 0444);
-MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
+MODULE_PARM_DESC(id, "ID string for VXPocket soundcard.");
 module_param_array(enable, bool, NULL, 0444);
-MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard.");
+MODULE_PARM_DESC(enable, "Enable VXPocket soundcard.");
 module_param_array(ibl, int, NULL, 0444);
-MODULE_PARM_DESC(ibl, "Capture IBL size for " CARD_NAME " soundcard.");
+MODULE_PARM_DESC(ibl, "Capture IBL size for VXPocket soundcard.");
  
 
 /*
  */
 
-#ifdef COMPILE_VXP440
+static unsigned int card_alloc;
+static dev_link_t *dev_list;		/* Linked list of devices */
+static dev_info_t dev_info = "snd-vxpocket";
 
-/* 1 DSP, 1 sync UER, 1 sync World Clock (NIY) */
-/* SMPTE (NIY) */
-/* 2 stereo analog input (line/micro) */
-/* 2 stereo analog output */
-/* Only output levels can be modified */
-/* UER, but only for the first two inputs and outputs. */
 
-#define NUM_CODECS	2
-#define CARD_TYPE	VX_TYPE_VXP440
-#define DEV_INFO	"snd-vxp440"
+static int vxpocket_event(event_t event, int priority, event_callback_args_t *args);
 
-#else
 
-/* 1 DSP, 1 sync UER */
-/* 1 programmable clock (NIY) */
-/* 1 stereo analog input (line/micro) */
-/* 1 stereo analog output */
-/* Only output levels can be modified */
+/*
+ */
+static void vxpocket_release(dev_link_t *link)
+{
+	if (link->state & DEV_CONFIG) {
+		/* release cs resources */
+		pcmcia_release_configuration(link->handle);
+		pcmcia_release_io(link->handle, &link->io);
+		pcmcia_release_irq(link->handle, &link->irq);
+		link->state &= ~DEV_CONFIG;
+	}
+	if (link->handle) {
+		/* Break the link with Card Services */
+		pcmcia_deregister_client(link->handle);
+		link->handle = NULL;
+	}
+}
 
-#define NUM_CODECS	1
-#define CARD_TYPE	VX_TYPE_VXPOCKET
-#define DEV_INFO	"snd-vxpocket"
+/*
+ * destructor, called from snd_card_free_in_thread()
+ */
+static int snd_vxpocket_dev_free(snd_device_t *device)
+{
+	vx_core_t *chip = device->device_data;
 
-#endif
+	snd_vx_free_firmware(chip);
+	kfree(chip);
+	return 0;
+}
 
-static dev_info_t dev_info = DEV_INFO;
 
-static struct snd_vx_hardware vxp_hw = {
-	.name = CARD_NAME,
-	.type = CARD_TYPE,
+/*
+ * Hardware information
+ */
+
+/* VX-pocket V2
+ *
+ * 1 DSP, 1 sync UER
+ * 1 programmable clock (NIY)
+ * 1 stereo analog input (line/micro)
+ * 1 stereo analog output
+ * Only output levels can be modified
+ */
+
+static struct snd_vx_hardware vxpocket_hw = {
+	.name = "VXPocket",
+	.type = VX_TYPE_VXPOCKET,
 
 	/* hardware specs */
-	.num_codecs = NUM_CODECS,
-	.num_ins = NUM_CODECS,
-	.num_outs = NUM_CODECS,
+	.num_codecs = 1,
+	.num_ins = 1,
+	.num_outs = 1,
 	.output_level_max = VX_ANALOG_OUT_LEVEL_MAX,
 };	
 
-static struct snd_vxp_entry hw_entry = {
-	.dev_info = &dev_info,
+/* VX-pocket 440
+ *
+ * 1 DSP, 1 sync UER, 1 sync World Clock (NIY)
+ * SMPTE (NIY)
+ * 2 stereo analog input (line/micro)
+ * 2 stereo analog output
+ * Only output levels can be modified
+ * UER, but only for the first two inputs and outputs.
+ */
 
-	/* module parameters */
-	.index_table = index,
-	.id_table = id,
-	.enable_table = enable,
-	.ibl = ibl,
+static struct snd_vx_hardware vxp440_hw = {
+	.name = "VXPocket440",
+	.type = VX_TYPE_VXP440,
+
+	/* hardware specs */
+	.num_codecs = 2,
+	.num_ins = 2,
+	.num_outs = 2,
+	.output_level_max = VX_ANALOG_OUT_LEVEL_MAX,
+};	
+
+
+/*
+ * create vxpocket instance
+ */
+static struct snd_vxpocket *snd_vxpocket_new(snd_card_t *card, int ibl)
+{
+	client_reg_t client_reg;	/* Register with cardmgr */
+	dev_link_t *link;		/* Info for cardmgr */
+	vx_core_t *chip;
+	struct snd_vxpocket *vxp;
+	int ret;
+	static snd_device_ops_t ops = {
+		.dev_free =	snd_vxpocket_dev_free,
+	};
+
+	chip = snd_vx_create(card, &vxpocket_hw, &snd_vxpocket_ops,
+			     sizeof(struct snd_vxpocket) - sizeof(vx_core_t));
+	if (! chip)
+		return NULL;
+
+	if (snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops) < 0) {
+		kfree(chip);
+		return NULL;
+	}
+	chip->ibl.size = ibl;
+
+	vxp = (struct snd_vxpocket *)chip;
+
+	link = &vxp->link;
+	link->priv = chip;
+
+	link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
+	link->io.NumPorts1 = 16;
+
+	link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;
+
+	link->irq.IRQInfo1 = IRQ_LEVEL_ID;
+	link->irq.Handler = &snd_vx_irq_handler;
+	link->irq.Instance = chip;
+
+	link->conf.Attributes = CONF_ENABLE_IRQ;
+	link->conf.Vcc = 50;
+	link->conf.IntType = INT_MEMORY_AND_IO;
+	link->conf.ConfigIndex = 1;
+	link->conf.Present = PRESENT_OPTION;
+
+	/* Register with Card Services */
+	memset(&client_reg, 0, sizeof(client_reg));
+	client_reg.dev_info = &dev_info;
+	client_reg.EventMask = 
+		CS_EVENT_CARD_INSERTION | CS_EVENT_CARD_REMOVAL
+#ifdef CONFIG_PM
+		| CS_EVENT_RESET_PHYSICAL | CS_EVENT_CARD_RESET
+		| CS_EVENT_PM_SUSPEND | CS_EVENT_PM_RESUME
+#endif
+		;
+	client_reg.event_handler = &vxpocket_event;
+	client_reg.Version = 0x0210;
+	client_reg.event_callback_args.client_data = link;
+
+	ret = pcmcia_register_client(&link->handle, &client_reg);
+	if (ret != CS_SUCCESS) {
+		cs_error(link->handle, RegisterClient, ret);
+		return NULL;
+	}
+
+	return vxp;
+}
+
+
+/**
+ * snd_vxpocket_assign_resources - initialize the hardware and card instance.
+ * @port: i/o port for the card
+ * @irq: irq number for the card
+ *
+ * this function assigns the specified port and irq, boot the card,
+ * create pcm and control instances, and initialize the rest hardware.
+ *
+ * returns 0 if successful, or a negative error code.
+ */
+static int snd_vxpocket_assign_resources(vx_core_t *chip, int port, int irq)
+{
+	int err;
+	snd_card_t *card = chip->card;
+	struct snd_vxpocket *vxp = (struct snd_vxpocket *)chip;
+
+	snd_printdd(KERN_DEBUG "vxpocket assign resources: port = 0x%x, irq = %d\n", port, irq);
+	vxp->port = port;
+
+	sprintf(card->shortname, "Digigram %s", card->driver);
+	sprintf(card->longname, "%s at 0x%x, irq %i",
+		card->shortname, port, irq);
+
+	chip->irq = irq;
+
+	if ((err = snd_vx_setup_firmware(chip)) < 0)
+		return err;
+
+	return 0;
+}
+
+
+/*
+ * configuration callback
+ */
+
+#define CS_CHECK(fn, ret) \
+do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
+
+static void vxpocket_config(dev_link_t *link)
+{
+	client_handle_t handle = link->handle;
+	vx_core_t *chip = link->priv;
+	struct snd_vxpocket *vxp = (struct snd_vxpocket *)chip;
+	tuple_t tuple;
+	cisparse_t *parse;
+	u_short buf[32];
+	int last_fn, last_ret;
+
+	snd_printdd(KERN_DEBUG "vxpocket_config called\n");
+	parse = kmalloc(sizeof(*parse), GFP_KERNEL);
+	if (! parse) {
+		snd_printk(KERN_ERR "vx: cannot allocate\n");
+		return;
+	}
+	tuple.Attributes = 0;
+	tuple.TupleData = (cisdata_t *)buf;
+	tuple.TupleDataMax = sizeof(buf);
+	tuple.TupleOffset = 0;
+	tuple.DesiredTuple = CISTPL_CONFIG;
+	CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
+	CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
+	CS_CHECK(ParseTuple, pcmcia_parse_tuple(handle, &tuple, parse));
+	link->conf.ConfigBase = parse->config.base;
+	link->conf.Present = parse->config.rmask[0];
+
+	/* redefine hardware record according to the VERSION1 string */
+	tuple.DesiredTuple = CISTPL_VERS_1;
+	CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
+	CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
+	CS_CHECK(ParseTuple, pcmcia_parse_tuple(handle, &tuple, parse));
+	if (! strcmp(parse->version_1.str + parse->version_1.ofs[1], "VX-POCKET")) {
+		snd_printdd("VX-pocket is detected\n");
+	} else {
+		snd_printdd("VX-pocket 440 is detected\n");
+		/* overwrite the hardware information */
+		chip->hw = &vxp440_hw;
+		chip->type = vxp440_hw.type;
+		strcpy(chip->card->driver, vxp440_hw.name);
+	}
+
+	/* Configure card */
+	link->state |= DEV_CONFIG;
+
+	CS_CHECK(RequestIO, pcmcia_request_io(handle, &link->io));
+	CS_CHECK(RequestIRQ, pcmcia_request_irq(link->handle, &link->irq));
+	CS_CHECK(RequestConfiguration, pcmcia_request_configuration(link->handle, &link->conf));
+
+	chip->dev = &handle_to_dev(link->handle);
+
+	if (snd_vxpocket_assign_resources(chip, link->io.BasePort1, link->irq.AssignedIRQ) < 0)
+		goto failed;
+
+	link->dev = &vxp->node;
+	link->state &= ~DEV_CONFIG_PENDING;
+	kfree(parse);
+	return;
+
+cs_failed:
+	cs_error(link->handle, last_fn, last_ret);
+failed:
+	pcmcia_release_configuration(link->handle);
+	pcmcia_release_io(link->handle, &link->io);
+	pcmcia_release_irq(link->handle, &link->irq);
+	link->state &= ~DEV_CONFIG;
+	kfree(parse);
+}
+
+
+/*
+ * event callback
+ */
+static int vxpocket_event(event_t event, int priority, event_callback_args_t *args)
+{
+	dev_link_t *link = args->client_data;
+	vx_core_t *chip = link->priv;
+
+	switch (event) {
+	case CS_EVENT_CARD_REMOVAL:
+		snd_printdd(KERN_DEBUG "CARD_REMOVAL..\n");
+		link->state &= ~DEV_PRESENT;
+		if (link->state & DEV_CONFIG)
+			chip->chip_status |= VX_STAT_IS_STALE;
+		break;
+	case CS_EVENT_CARD_INSERTION:
+		snd_printdd(KERN_DEBUG "CARD_INSERTION..\n");
+		link->state |= DEV_PRESENT | DEV_CONFIG_PENDING;
+		vxpocket_config(link);
+		break;
+#ifdef CONFIG_PM
+	case CS_EVENT_PM_SUSPEND:
+		snd_printdd(KERN_DEBUG "SUSPEND\n");
+		link->state |= DEV_SUSPEND;
+		if (chip && chip->card->pm_suspend) {
+			snd_printdd(KERN_DEBUG "snd_vx_suspend calling\n");
+			chip->card->pm_suspend(chip->card, PMSG_SUSPEND);
+		}
+		/* Fall through... */
+	case CS_EVENT_RESET_PHYSICAL:
+		snd_printdd(KERN_DEBUG "RESET_PHYSICAL\n");
+		if (link->state & DEV_CONFIG)
+			pcmcia_release_configuration(link->handle);
+		break;
+	case CS_EVENT_PM_RESUME:
+		snd_printdd(KERN_DEBUG "RESUME\n");
+		link->state &= ~DEV_SUSPEND;
+		/* Fall through... */
+	case CS_EVENT_CARD_RESET:
+		snd_printdd(KERN_DEBUG "CARD_RESET\n");
+		if (DEV_OK(link)) {
+			//struct snd_vxpocket *vxp = (struct snd_vxpocket *)chip;
+			snd_printdd(KERN_DEBUG "requestconfig...\n");
+			pcmcia_request_configuration(link->handle, &link->conf);
+			if (chip && chip->card->pm_resume) {
+				snd_printdd(KERN_DEBUG "calling snd_vx_resume\n");
+				chip->card->pm_resume(chip->card);
+			}
+		}
+		snd_printdd(KERN_DEBUG "resume done!\n");
+		break;
+#endif
+	}
+	return 0;
+}
 
-	/* h/w config */
-	.hardware = &vxp_hw,
-	.ops = &snd_vxpocket_ops,
-};
 
 /*
  */
 static dev_link_t *vxp_attach(void)
 {
-	return snd_vxpocket_attach(&hw_entry);
+	snd_card_t *card;
+	struct snd_vxpocket *vxp;
+	int i;
+
+	/* find an empty slot from the card list */
+	for (i = 0; i < SNDRV_CARDS; i++) {
+		if (! card_alloc & (1 << i))
+			break;
+	}
+	if (i >= SNDRV_CARDS) {
+		snd_printk(KERN_ERR "vxpocket: too many cards found\n");
+		return NULL;
+	}
+	if (! enable[i])
+		return NULL; /* disabled explicitly */
+
+	/* ok, create a card instance */
+	card = snd_card_new(index[i], id[i], THIS_MODULE, 0);
+	if (card == NULL) {
+		snd_printk(KERN_ERR "vxpocket: cannot create a card instance\n");
+		return NULL;
+	}
+
+	vxp = snd_vxpocket_new(card, ibl[i]);
+	if (! vxp) {
+		snd_card_free(card);
+		return NULL;
+	}
+
+	vxp->index = index[i];
+	card_alloc |= 1 << i;
+
+	/* Chain drivers */
+	vxp->link.next = dev_list;
+	dev_list = &vxp->link;
+
+	return &vxp->link;
 }
 
 static void vxp_detach(dev_link_t *link)
 {
-	snd_vxpocket_detach(&hw_entry, link);
+	struct snd_vxpocket *vxp;
+	vx_core_t *chip;
+	dev_link_t **linkp;
+
+	if (! link)
+		return;
+
+	vxp = link->priv;
+	chip = (vx_core_t *)vxp;
+	card_alloc &= ~(1 << vxp->index);
+
+	/* Remove the interface data from the linked list */
+	for (linkp = &dev_list; *linkp; linkp = &(*linkp)->next)
+		if (*linkp == link) {
+			*linkp = link->next;
+			break;
+		}
+
+	chip->chip_status |= VX_STAT_IS_STALE; /* to be sure */
+	snd_card_disconnect(chip->card);
+	vxpocket_release(link);
+	snd_card_free_in_thread(chip->card);
 }
 
 /*
@@ -137,7 +456,7 @@ MODULE_DEVICE_TABLE(pcmcia, vxp_ids);
 static struct pcmcia_driver vxp_cs_driver = {
 	.owner		= THIS_MODULE,
 	.drv		= {
-		.name	= DEV_INFO,
+		.name	= "snd-vxpocket",
 	},
 	.attach		= vxp_attach,
 	.detach		= vxp_detach,
@@ -152,7 +471,7 @@ static int __init init_vxpocket(void)
 static void __exit exit_vxpocket(void)
 {
 	pcmcia_unregister_driver(&vxp_cs_driver);
-	BUG_ON(hw_entry.dev_list != NULL);
+	BUG_ON(dev_list != NULL);
 }
 
 module_init(init_vxpocket);
diff --git a/sound/pcmcia/vx/vxpocket.h b/sound/pcmcia/vx/vxpocket.h
index 4462c04a4e8..70754aa3dd1 100644
--- a/sound/pcmcia/vx/vxpocket.h
+++ b/sound/pcmcia/vx/vxpocket.h
@@ -28,24 +28,6 @@
 #include <pcmcia/cistpl.h>
 #include <pcmcia/ds.h>
 
-struct snd_vxp_entry {
-	dev_info_t *dev_info;
-
-	/* module parameters */
-	int *index_table;
-	char **id_table;
-	int *enable_table;
-	int *ibl;
-
-	/* h/w config */
-	struct snd_vx_hardware *hardware;
-	struct snd_vx_ops *ops;
-
-	/* slots */
-	vx_core_t *card_list[SNDRV_CARDS];
-	dev_link_t *dev_list;		/* Linked list of devices */
-};
-
 struct snd_vxpocket {
 
 	vx_core_t core;
@@ -57,8 +39,7 @@ struct snd_vxpocket {
 	unsigned int regCDSP;	/* current CDSP register */
 	unsigned int regDIALOG;	/* current DIALOG register */
 
-	int index;
-	struct snd_vxp_entry *hw_entry;
+	int index;	/* card index */
 
 	/* pcmcia stuff */
 	dev_link_t link;
@@ -70,12 +51,6 @@ extern struct snd_vx_ops snd_vxpocket_ops;
 void vx_set_mic_boost(vx_core_t *chip, int boost);
 void vx_set_mic_level(vx_core_t *chip, int level);
 
-/*
- * pcmcia stuff
- */
-dev_link_t *snd_vxpocket_attach(struct snd_vxp_entry *hw);
-void snd_vxpocket_detach(struct snd_vxp_entry *hw, dev_link_t *link);
-
 int vxp_add_mic_controls(vx_core_t *chip);
 
 /* Constants used to access the CDSP register (0x08). */
diff --git a/sound/ppc/awacs.c b/sound/ppc/awacs.c
index 061e52d3d77..758ca1bcbcf 100644
--- a/sound/ppc/awacs.c
+++ b/sound/ppc/awacs.c
@@ -103,7 +103,7 @@ static void screamer_recalibrate(pmac_t *chip)
 	snd_pmac_awacs_write_noreg(chip, 1, chip->awacs_reg[1]);
 	if (chip->manufacturer == 0x1)
 		/* delay for broken crystal part */
-		big_mdelay(750);
+		msleep(750);
 	snd_pmac_awacs_write_noreg(chip, 1,
 				   chip->awacs_reg[1] | MASK_RECALIBRATE | MASK_CMUTE | MASK_AMUTE);
 	snd_pmac_awacs_write_noreg(chip, 1, chip->awacs_reg[1]);
@@ -653,10 +653,10 @@ static void snd_pmac_awacs_resume(pmac_t *chip)
 {
 	if (machine_is_compatible("PowerBook3,1")
 	    || machine_is_compatible("PowerBook3,2")) {
-		big_mdelay(100);
+		msleep(100);
 		snd_pmac_awacs_write_reg(chip, 1,
 			chip->awacs_reg[1] & ~MASK_PAROUT);
-		big_mdelay(300);
+		msleep(300);
 	}
 
 	awacs_restore_all_regs(chip);
diff --git a/sound/ppc/burgundy.c b/sound/ppc/burgundy.c
index 3f837d9f3eb..edbc0484e22 100644
--- a/sound/ppc/burgundy.c
+++ b/sound/ppc/burgundy.c
@@ -30,7 +30,7 @@
 
 
 /* Waits for busy flag to clear */
-inline static void
+static inline void
 snd_pmac_burgundy_busy_wait(pmac_t *chip)
 {
 	int timeout = 50;
@@ -40,7 +40,7 @@ snd_pmac_burgundy_busy_wait(pmac_t *chip)
 		printk(KERN_DEBUG "burgundy_busy_wait: timeout\n");
 }
 
-inline static void
+static inline void
 snd_pmac_burgundy_extend_wait(pmac_t *chip)
 {
 	int timeout;
diff --git a/sound/ppc/pmac.c b/sound/ppc/pmac.c
index 75b8b742303..844d76152ea 100644
--- a/sound/ppc/pmac.c
+++ b/sound/ppc/pmac.c
@@ -153,7 +153,7 @@ static pmac_stream_t *snd_pmac_get_stream(pmac_t *chip, int stream)
 /*
  * wait while run status is on
  */
-inline static void
+static inline void
 snd_pmac_wait_ack(pmac_stream_t *rec)
 {
 	int timeout = 50000;
@@ -177,7 +177,7 @@ static void snd_pmac_pcm_set_format(pmac_t *chip)
 /*
  * stop the DMA transfer
  */
-inline static void snd_pmac_dma_stop(pmac_stream_t *rec)
+static inline void snd_pmac_dma_stop(pmac_stream_t *rec)
 {
 	out_le32(&rec->dma->control, (RUN|WAKE|FLUSH|PAUSE) << 16);
 	snd_pmac_wait_ack(rec);
@@ -186,7 +186,7 @@ inline static void snd_pmac_dma_stop(pmac_stream_t *rec)
 /*
  * set the command pointer address
  */
-inline static void snd_pmac_dma_set_command(pmac_stream_t *rec, pmac_dbdma_t *cmd)
+static inline void snd_pmac_dma_set_command(pmac_stream_t *rec, pmac_dbdma_t *cmd)
 {
 	out_le32(&rec->dma->cmdptr, cmd->addr);
 }
@@ -194,7 +194,7 @@ inline static void snd_pmac_dma_set_command(pmac_stream_t *rec, pmac_dbdma_t *cm
 /*
  * start the DMA
  */
-inline static void snd_pmac_dma_run(pmac_stream_t *rec, int status)
+static inline void snd_pmac_dma_run(pmac_stream_t *rec, int status)
 {
 	out_le32(&rec->dma->control, status | (status << 16));
 }
diff --git a/sound/ppc/pmac.h b/sound/ppc/pmac.h
index 582db522011..ae3bb6c6edf 100644
--- a/sound/ppc/pmac.h
+++ b/sound/ppc/pmac.h
@@ -212,9 +212,4 @@ int snd_pmac_boolean_mono_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *ui
 
 int snd_pmac_add_automute(pmac_t *chip);
 
-#define big_mdelay(msec) do {\
-	set_current_state(TASK_UNINTERRUPTIBLE);\
-	schedule_timeout(((msec) * HZ + 999) / 1000);\
-} while (0)
-
 #endif /* __PMAC_H */
diff --git a/sound/ppc/tumbler.c b/sound/ppc/tumbler.c
index 36c5d5d45bb..b94437c024b 100644
--- a/sound/ppc/tumbler.c
+++ b/sound/ppc/tumbler.c
@@ -945,7 +945,7 @@ static void device_change_handler(void *self)
 			check_mute(chip, &mix->line_mute, 0, mix->auto_mute_notify,
 				   chip->lineout_sw_ctl);
 		if (mix->anded_reset)
-			big_mdelay(10);
+			msleep(10);
 		check_mute(chip, &mix->amp_mute, 1, mix->auto_mute_notify,
 			   chip->speaker_sw_ctl);
 		mix->drc_enable = 0;
@@ -954,7 +954,7 @@ static void device_change_handler(void *self)
 		check_mute(chip, &mix->amp_mute, 0, mix->auto_mute_notify,
 			   chip->speaker_sw_ctl);
 		if (mix->anded_reset)
-			big_mdelay(10);
+			msleep(10);
 		check_mute(chip, &mix->hp_mute, 1, mix->auto_mute_notify,
 			   chip->master_sw_ctl);
 		if (mix->line_mute.addr != 0)
@@ -1109,22 +1109,22 @@ static void tumbler_reset_audio(pmac_t *chip)
 		DBG("(I) codec anded reset !\n");
 		write_audio_gpio(&mix->hp_mute, 0);
 		write_audio_gpio(&mix->amp_mute, 0);
-		big_mdelay(200);
+		msleep(200);
 		write_audio_gpio(&mix->hp_mute, 1);
 		write_audio_gpio(&mix->amp_mute, 1);
-		big_mdelay(100);
+		msleep(100);
 		write_audio_gpio(&mix->hp_mute, 0);
 		write_audio_gpio(&mix->amp_mute, 0);
-		big_mdelay(100);
+		msleep(100);
 	} else {
 		DBG("(I) codec normal reset !\n");
 
 		write_audio_gpio(&mix->audio_reset, 0);
-		big_mdelay(200);
+		msleep(200);
 		write_audio_gpio(&mix->audio_reset, 1);
-		big_mdelay(100);
+		msleep(100);
 		write_audio_gpio(&mix->audio_reset, 0);
-		big_mdelay(100);
+		msleep(100);
 	}
 }
 
diff --git a/sound/sparc/Kconfig b/sound/sparc/Kconfig
index 2358df1c45a..25a8a558ef9 100644
--- a/sound/sparc/Kconfig
+++ b/sound/sparc/Kconfig
@@ -7,12 +7,30 @@ config SND_SUN_AMD7930
 	tristate "Sun AMD7930"
 	depends on SBUS && SND
 	select SND_PCM
+	help
+	  Say Y here to include support for AMD7930 sound device on Sun.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called snd-sun-amd7930.
 
-#  dep_tristate 'Sun DBRI' CONFIG_SND_SUN_DBRI $CONFIG_SND
 config SND_SUN_CS4231
 	tristate "Sun CS4231"
 	depends on SND
 	select SND_PCM
+	help
+	  Say Y here to include support for CS4231 sound device on Sun.
 
-endmenu
+	  To compile this driver as a module, choose M here: the module
+	  will be called snd-sun-cs4231.
+
+config SND_SUN_DBRI
+	tristate "Sun DBRI"
+	depends on SND && SBUS
+	select SND_PCM
+	help
+	  Say Y here to include support for DBRI sound device on Sun.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called snd-sun-dbri.
 
+endmenu
diff --git a/sound/sparc/Makefile b/sound/sparc/Makefile
index 6809cc92d27..3cd89c67c2f 100644
--- a/sound/sparc/Makefile
+++ b/sound/sparc/Makefile
@@ -4,9 +4,9 @@
 #
 
 snd-sun-amd7930-objs := amd7930.o
-#snd-sun-dbri-objs := dbri.o
 snd-sun-cs4231-objs := cs4231.o
+snd-sun-dbri-objs := dbri.o
 
 obj-$(CONFIG_SND_SUN_AMD7930) += snd-sun-amd7930.o
-#obj-$(CONFIG_SND_SUN_DBRI) += snd-sun-dbri.o
 obj-$(CONFIG_SND_SUN_CS4231) += snd-sun-cs4231.o
+obj-$(CONFIG_SND_SUN_DBRI) += snd-sun-dbri.o
diff --git a/sound/sparc/dbri.c b/sound/sparc/dbri.c
new file mode 100644
index 00000000000..941c7b1e7eb
--- /dev/null
+++ b/sound/sparc/dbri.c
@@ -0,0 +1,2729 @@
+/*
+ * Driver for DBRI sound chip found on Sparcs.
+ * Copyright (C) 2004 Martin Habets (mhabets@users.sourceforge.net)
+ *
+ * Based entirely upon drivers/sbus/audio/dbri.c which is:
+ * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
+ * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
+ *
+ * This is the lowlevel driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
+ * on Sun SPARCstation 10, 20, LX and Voyager models.
+ *
+ * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
+ *   data time multiplexer with ISDN support (aka T7259)
+ *   Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
+ *   CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
+ *   Documentation:
+ *   - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Tranceiver" from
+ *     Sparc Technology Business (courtesy of Sun Support)
+ *   - Data sheet of the T7903, a newer but very similar ISA bus equivalent
+ *     available from the Lucent (formarly AT&T microelectronics) home
+ *     page.
+ *   - http://www.freesoft.org/Linux/DBRI/
+ * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
+ *   Interfaces: CHI, Audio In & Out, 2 bits parallel
+ *   Documentation: from the Crystal Semiconductor home page.
+ *
+ * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
+ * memory and a serial device (long pipes, nr 0-15) or between two serial
+ * devices (short pipes, nr 16-31), or simply send a fixed data to a serial
+ * device (short pipes).
+ * A timeslot defines the bit-offset and nr of bits read from a serial device.
+ * The timeslots are linked to 6 circular lists, one for each direction for
+ * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
+ * (the second one is a monitor/tee pipe, valid only for serial input).
+ *
+ * The mmcodec is connected via the CHI bus and needs the data & some
+ * parameters (volume, balance, output selection) timemultiplexed in 8 byte
+ * chunks. It also has a control mode, which serves for audio format setting.
+ *
+ * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
+ * the same CHI bus, so I thought perhaps it is possible to use the onboard
+ * & the speakerbox codec simultanously, giving 2 (not very independent :-)
+ * audio devices. But the SUN HW group decided against it, at least on my
+ * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
+ * connected.
+ */
+
+#include <sound/driver.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/info.h>
+#include <sound/control.h>
+#include <sound/initval.h>
+
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <asm/sbus.h>
+#include <asm/atomic.h>
+
+MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
+MODULE_DESCRIPTION("Sun DBRI");
+MODULE_LICENSE("GPL");
+MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");
+
+static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;	/* Index 0-MAX */
+static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;	/* ID for this card */
+static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;	/* Enable this card */
+
+module_param_array(index, int, NULL, 0444);
+MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
+module_param_array(id, charp, NULL, 0444);
+MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
+module_param_array(enable, bool, NULL, 0444);
+MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
+
+#define DBRI_DEBUG
+
+#define D_INT	(1<<0)
+#define D_GEN	(1<<1)
+#define D_CMD	(1<<2)
+#define D_MM	(1<<3)
+#define D_USR	(1<<4)
+#define D_DESC	(1<<5)
+
+static int dbri_debug = 0;
+module_param(dbri_debug, int, 0444);
+MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
+
+#ifdef DBRI_DEBUG
+static char *cmds[] = {
+	"WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
+	"SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
+};
+
+#define dprintk(a, x...) if(dbri_debug & a) printk(KERN_DEBUG x)
+
+#define DBRI_CMD(cmd, intr, value) ((cmd << 28) |			\
+				    (1 << 27) | \
+				    value)
+#else
+#define dprintk(a, x...)
+
+#define DBRI_CMD(cmd, intr, value) ((cmd << 28) |			\
+				    (intr << 27) | \
+				    value)
+#endif				/* DBRI_DEBUG */
+
+/***************************************************************************
+	CS4215 specific definitions and structures
+****************************************************************************/
+
+struct cs4215 {
+	__u8 data[4];		/* Data mode: Time slots 5-8 */
+	__u8 ctrl[4];		/* Ctrl mode: Time slots 1-4 */
+	__u8 onboard;
+	__u8 offset;		/* Bit offset from frame sync to time slot 1 */
+	volatile __u32 status;
+	volatile __u32 version;
+	__u8 precision;		/* In bits, either 8 or 16 */
+	__u8 channels;		/* 1 or 2 */
+};
+
+/*
+ * Control mode first 
+ */
+
+/* Time Slot 1, Status register */
+#define CS4215_CLB	(1<<2)	/* Control Latch Bit */
+#define CS4215_OLB	(1<<3)	/* 1: line: 2.0V, speaker 4V */
+				/* 0: line: 2.8V, speaker 8V */
+#define CS4215_MLB	(1<<4)	/* 1: Microphone: 20dB gain disabled */
+#define CS4215_RSRVD_1  (1<<5)
+
+/* Time Slot 2, Data Format Register */
+#define CS4215_DFR_LINEAR16	0
+#define CS4215_DFR_ULAW		1
+#define CS4215_DFR_ALAW		2
+#define CS4215_DFR_LINEAR8	3
+#define CS4215_DFR_STEREO	(1<<2)
+static struct {
+	unsigned short freq;
+	unsigned char xtal;
+	unsigned char csval;
+} CS4215_FREQ[] = {
+	{  8000, (1 << 4), (0 << 3) },
+	{ 16000, (1 << 4), (1 << 3) },
+	{ 27429, (1 << 4), (2 << 3) },	/* Actually 24428.57 */
+	{ 32000, (1 << 4), (3 << 3) },
+     /* {    NA, (1 << 4), (4 << 3) }, */
+     /* {    NA, (1 << 4), (5 << 3) }, */
+	{ 48000, (1 << 4), (6 << 3) },
+	{  9600, (1 << 4), (7 << 3) },
+	{  5513, (2 << 4), (0 << 3) },	/* Actually 5512.5 */
+	{ 11025, (2 << 4), (1 << 3) },
+	{ 18900, (2 << 4), (2 << 3) },
+	{ 22050, (2 << 4), (3 << 3) },
+	{ 37800, (2 << 4), (4 << 3) },
+	{ 44100, (2 << 4), (5 << 3) },
+	{ 33075, (2 << 4), (6 << 3) },
+	{  6615, (2 << 4), (7 << 3) },
+	{ 0, 0, 0}
+};
+
+#define CS4215_HPF	(1<<7)	/* High Pass Filter, 1: Enabled */
+
+#define CS4215_12_MASK	0xfcbf	/* Mask off reserved bits in slot 1 & 2 */
+
+/* Time Slot 3, Serial Port Control register */
+#define CS4215_XEN	(1<<0)	/* 0: Enable serial output */
+#define CS4215_XCLK	(1<<1)	/* 1: Master mode: Generate SCLK */
+#define CS4215_BSEL_64	(0<<2)	/* Bitrate: 64 bits per frame */
+#define CS4215_BSEL_128	(1<<2)
+#define CS4215_BSEL_256	(2<<2)
+#define CS4215_MCK_MAST (0<<4)	/* Master clock */
+#define CS4215_MCK_XTL1 (1<<4)	/* 24.576 MHz clock source */
+#define CS4215_MCK_XTL2 (2<<4)	/* 16.9344 MHz clock source */
+#define CS4215_MCK_CLK1 (3<<4)	/* Clockin, 256 x Fs */
+#define CS4215_MCK_CLK2 (4<<4)	/* Clockin, see DFR */
+
+/* Time Slot 4, Test Register */
+#define CS4215_DAD	(1<<0)	/* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
+#define CS4215_ENL	(1<<1)	/* Enable Loopback Testing */
+
+/* Time Slot 5, Parallel Port Register */
+/* Read only here and the same as the in data mode */
+
+/* Time Slot 6, Reserved  */
+
+/* Time Slot 7, Version Register  */
+#define CS4215_VERSION_MASK 0xf	/* Known versions 0/C, 1/D, 2/E */
+
+/* Time Slot 8, Reserved  */
+
+/*
+ * Data mode
+ */
+/* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data  */
+
+/* Time Slot 5, Output Setting  */
+#define CS4215_LO(v)	v	/* Left Output Attenuation 0x3f: -94.5 dB */
+#define CS4215_LE	(1<<6)	/* Line Out Enable */
+#define CS4215_HE	(1<<7)	/* Headphone Enable */
+
+/* Time Slot 6, Output Setting  */
+#define CS4215_RO(v)	v	/* Right Output Attenuation 0x3f: -94.5 dB */
+#define CS4215_SE	(1<<6)	/* Speaker Enable */
+#define CS4215_ADI	(1<<7)	/* A/D Data Invalid: Busy in calibration */
+
+/* Time Slot 7, Input Setting */
+#define CS4215_LG(v)	v	/* Left Gain Setting 0xf: 22.5 dB */
+#define CS4215_IS	(1<<4)	/* Input Select: 1=Microphone, 0=Line */
+#define CS4215_OVR	(1<<5)	/* 1: Overrange condition occurred */
+#define CS4215_PIO0	(1<<6)	/* Parallel I/O 0 */
+#define CS4215_PIO1	(1<<7)
+
+/* Time Slot 8, Input Setting */
+#define CS4215_RG(v)	v	/* Right Gain Setting 0xf: 22.5 dB */
+#define CS4215_MA(v)	(v<<4)	/* Monitor Path Attenuation 0xf: mute */
+
+/***************************************************************************
+		DBRI specific definitions and structures
+****************************************************************************/
+
+/* DBRI main registers */
+#define REG0	0x00UL		/* Status and Control */
+#define REG1	0x04UL		/* Mode and Interrupt */
+#define REG2	0x08UL		/* Parallel IO */
+#define REG3	0x0cUL		/* Test */
+#define REG8	0x20UL		/* Command Queue Pointer */
+#define REG9	0x24UL		/* Interrupt Queue Pointer */
+
+#define DBRI_NO_CMDS	64
+#define DBRI_NO_INTS	1	/* Note: the value of this define was
+				 * originally 2.  The ringbuffer to store
+				 * interrupts in dma is currently broken.
+				 * This is a temporary fix until the ringbuffer
+				 * is fixed.
+				 */
+#define DBRI_INT_BLK	64
+#define DBRI_NO_DESCS	64
+#define DBRI_NO_PIPES	32
+
+#define DBRI_MM_ONB	1
+#define DBRI_MM_SB	2
+
+#define DBRI_REC	0
+#define DBRI_PLAY	1
+#define DBRI_NO_STREAMS	2
+
+/* One transmit/receive descriptor */
+struct dbri_mem {
+	volatile __u32 word1;
+	volatile __u32 ba;	/* Transmit/Receive Buffer Address */
+	volatile __u32 nda;	/* Next Descriptor Address */
+	volatile __u32 word4;
+};
+
+/* This structure is in a DMA region where it can accessed by both
+ * the CPU and the DBRI
+ */
+struct dbri_dma {
+	volatile s32 cmd[DBRI_NO_CMDS];	/* Place for commands       */
+	volatile s32 intr[DBRI_NO_INTS * DBRI_INT_BLK];	/* Interrupt field  */
+	struct dbri_mem desc[DBRI_NO_DESCS];	/* Xmit/receive descriptors */
+};
+
+#define dbri_dma_off(member, elem)	\
+	((u32)(unsigned long)		\
+	 (&(((struct dbri_dma *)0)->member[elem])))
+
+enum in_or_out { PIPEinput, PIPEoutput };
+
+struct dbri_pipe {
+	u32 sdp;		/* SDP command word */
+	enum in_or_out direction;
+	int nextpipe;		/* Next pipe in linked list */
+	int prevpipe;
+	int cycle;		/* Offset of timeslot (bits) */
+	int length;		/* Length of timeslot (bits) */
+	int first_desc;		/* Index of first descriptor */
+	int desc;		/* Index of active descriptor */
+	volatile __u32 *recv_fixed_ptr;	/* Ptr to receive fixed data */
+};
+
+struct dbri_desc {
+	int inuse;		/* Boolean flag */
+	int next;		/* Index of next desc, or -1 */
+	unsigned int len;
+};
+
+/* Per stream (playback or record) information */
+typedef struct dbri_streaminfo {
+	snd_pcm_substream_t *substream;
+	u32 dvma_buffer;	/* Device view of Alsa DMA buffer */
+	int left;		/* # of bytes left in DMA buffer  */
+	int size;		/* Size of DMA buffer             */
+	size_t offset;		/* offset in user buffer          */
+	int pipe;		/* Data pipe used                 */
+	int left_gain;		/* mixer elements                 */
+	int right_gain;
+	int balance;
+} dbri_streaminfo_t;
+
+/* This structure holds the information for both chips (DBRI & CS4215) */
+typedef struct snd_dbri {
+	snd_card_t *card;	/* ALSA card */
+	snd_pcm_t *pcm;
+
+	int regs_size, irq;	/* Needed for unload */
+	struct sbus_dev *sdev;	/* SBUS device info */
+	spinlock_t lock;
+
+	volatile struct dbri_dma *dma;	/* Pointer to our DMA block */
+	u32 dma_dvma;		/* DBRI visible DMA address */
+
+	void __iomem *regs;	/* dbri HW regs */
+	int dbri_version;	/* 'e' and up is OK */
+	int dbri_irqp;		/* intr queue pointer */
+	int wait_seen;
+
+	struct dbri_pipe pipes[DBRI_NO_PIPES];	/* DBRI's 32 data pipes */
+	struct dbri_desc descs[DBRI_NO_DESCS];
+
+	int chi_in_pipe;
+	int chi_out_pipe;
+	int chi_bpf;
+
+	struct cs4215 mm;	/* mmcodec special info */
+				/* per stream (playback/record) info */
+	struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
+
+	struct snd_dbri *next;
+} snd_dbri_t;
+
+/* Needed for the ALSA macros to work */
+#define chip_t snd_dbri_t
+
+#define DBRI_MAX_VOLUME		63	/* Output volume */
+#define DBRI_MAX_GAIN		15	/* Input gain */
+#define DBRI_RIGHT_BALANCE	255
+#define DBRI_MID_BALANCE	(DBRI_RIGHT_BALANCE >> 1)
+
+/* DBRI Reg0 - Status Control Register - defines. (Page 17) */
+#define D_P		(1<<15)	/* Program command & queue pointer valid */
+#define D_G		(1<<14)	/* Allow 4-Word SBus Burst */
+#define D_S		(1<<13)	/* Allow 16-Word SBus Burst */
+#define D_E		(1<<12)	/* Allow 8-Word SBus Burst */
+#define D_X		(1<<7)	/* Sanity Timer Disable */
+#define D_T		(1<<6)	/* Permit activation of the TE interface */
+#define D_N		(1<<5)	/* Permit activation of the NT interface */
+#define D_C		(1<<4)	/* Permit activation of the CHI interface */
+#define D_F		(1<<3)	/* Force Sanity Timer Time-Out */
+#define D_D		(1<<2)	/* Disable Master Mode */
+#define D_H		(1<<1)	/* Halt for Analysis */
+#define D_R		(1<<0)	/* Soft Reset */
+
+/* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
+#define D_LITTLE_END	(1<<8)	/* Byte Order */
+#define D_BIG_END	(0<<8)	/* Byte Order */
+#define D_MRR		(1<<4)	/* Multiple Error Ack on SBus (readonly) */
+#define D_MLE		(1<<3)	/* Multiple Late Error on SBus (readonly) */
+#define D_LBG		(1<<2)	/* Lost Bus Grant on SBus (readonly) */
+#define D_MBE		(1<<1)	/* Burst Error on SBus (readonly) */
+#define D_IR		(1<<0)	/* Interrupt Indicator (readonly) */
+
+/* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
+#define D_ENPIO3	(1<<7)	/* Enable Pin 3 */
+#define D_ENPIO2	(1<<6)	/* Enable Pin 2 */
+#define D_ENPIO1	(1<<5)	/* Enable Pin 1 */
+#define D_ENPIO0	(1<<4)	/* Enable Pin 0 */
+#define D_ENPIO		(0xf0)	/* Enable all the pins */
+#define D_PIO3		(1<<3)	/* Pin 3: 1: Data mode, 0: Ctrl mode */
+#define D_PIO2		(1<<2)	/* Pin 2: 1: Onboard PDN */
+#define D_PIO1		(1<<1)	/* Pin 1: 0: Reset */
+#define D_PIO0		(1<<0)	/* Pin 0: 1: Speakerbox PDN */
+
+/* DBRI Commands (Page 20) */
+#define D_WAIT		0x0	/* Stop execution */
+#define D_PAUSE		0x1	/* Flush long pipes */
+#define D_JUMP		0x2	/* New command queue */
+#define D_IIQ		0x3	/* Initialize Interrupt Queue */
+#define D_REX		0x4	/* Report command execution via interrupt */
+#define D_SDP		0x5	/* Setup Data Pipe */
+#define D_CDP		0x6	/* Continue Data Pipe (reread NULL Pointer) */
+#define D_DTS		0x7	/* Define Time Slot */
+#define D_SSP		0x8	/* Set short Data Pipe */
+#define D_CHI		0x9	/* Set CHI Global Mode */
+#define D_NT		0xa	/* NT Command */
+#define D_TE		0xb	/* TE Command */
+#define D_CDEC		0xc	/* Codec setup */
+#define D_TEST		0xd	/* No comment */
+#define D_CDM		0xe	/* CHI Data mode command */
+
+/* Special bits for some commands */
+#define D_PIPE(v)      ((v)<<0)	/* Pipe Nr: 0-15 long, 16-21 short */
+
+/* Setup Data Pipe */
+/* IRM */
+#define D_SDP_2SAME	(1<<18)	/* Report 2nd time in a row value rcvd */
+#define D_SDP_CHANGE	(2<<18)	/* Report any changes */
+#define D_SDP_EVERY	(3<<18)	/* Report any changes */
+#define D_SDP_EOL	(1<<17)	/* EOL interrupt enable */
+#define D_SDP_IDLE	(1<<16)	/* HDLC idle interrupt enable */
+
+/* Pipe data MODE */
+#define D_SDP_MEM	(0<<13)	/* To/from memory */
+#define D_SDP_HDLC	(2<<13)
+#define D_SDP_HDLC_D	(3<<13)	/* D Channel (prio control) */
+#define D_SDP_SER	(4<<13)	/* Serial to serial */
+#define D_SDP_FIXED	(6<<13)	/* Short only */
+#define D_SDP_MODE(v)	((v)&(7<<13))
+
+#define D_SDP_TO_SER	(1<<12)	/* Direction */
+#define D_SDP_FROM_SER	(0<<12)	/* Direction */
+#define D_SDP_MSB	(1<<11)	/* Bit order within Byte */
+#define D_SDP_LSB	(0<<11)	/* Bit order within Byte */
+#define D_SDP_P		(1<<10)	/* Pointer Valid */
+#define D_SDP_A		(1<<8)	/* Abort */
+#define D_SDP_C		(1<<7)	/* Clear */
+
+/* Define Time Slot */
+#define D_DTS_VI	(1<<17)	/* Valid Input Time-Slot Descriptor */
+#define D_DTS_VO	(1<<16)	/* Valid Output Time-Slot Descriptor */
+#define D_DTS_INS	(1<<15)	/* Insert Time Slot */
+#define D_DTS_DEL	(0<<15)	/* Delete Time Slot */
+#define D_DTS_PRVIN(v) ((v)<<10)	/* Previous In Pipe */
+#define D_DTS_PRVOUT(v)        ((v)<<5)	/* Previous Out Pipe */
+
+/* Time Slot defines */
+#define D_TS_LEN(v)	((v)<<24)	/* Number of bits in this time slot */
+#define D_TS_CYCLE(v)	((v)<<14)	/* Bit Count at start of TS */
+#define D_TS_DI		(1<<13)	/* Data Invert */
+#define D_TS_1CHANNEL	(0<<10)	/* Single Channel / Normal mode */
+#define D_TS_MONITOR	(2<<10)	/* Monitor pipe */
+#define D_TS_NONCONTIG	(3<<10)	/* Non contiguous mode */
+#define D_TS_ANCHOR	(7<<10)	/* Starting short pipes */
+#define D_TS_MON(v)    ((v)<<5)	/* Monitor Pipe */
+#define D_TS_NEXT(v)   ((v)<<0)	/* Pipe Nr: 0-15 long, 16-21 short */
+
+/* Concentration Highway Interface Modes */
+#define D_CHI_CHICM(v)	((v)<<16)	/* Clock mode */
+#define D_CHI_IR	(1<<15)	/* Immediate Interrupt Report */
+#define D_CHI_EN	(1<<14)	/* CHIL Interrupt enabled */
+#define D_CHI_OD	(1<<13)	/* Open Drain Enable */
+#define D_CHI_FE	(1<<12)	/* Sample CHIFS on Rising Frame Edge */
+#define D_CHI_FD	(1<<11)	/* Frame Drive */
+#define D_CHI_BPF(v)	((v)<<0)	/* Bits per Frame */
+
+/* NT: These are here for completeness */
+#define D_NT_FBIT	(1<<17)	/* Frame Bit */
+#define D_NT_NBF	(1<<16)	/* Number of bad frames to loose framing */
+#define D_NT_IRM_IMM	(1<<15)	/* Interrupt Report & Mask: Immediate */
+#define D_NT_IRM_EN	(1<<14)	/* Interrupt Report & Mask: Enable */
+#define D_NT_ISNT	(1<<13)	/* Configfure interface as NT */
+#define D_NT_FT		(1<<12)	/* Fixed Timing */
+#define D_NT_EZ		(1<<11)	/* Echo Channel is Zeros */
+#define D_NT_IFA	(1<<10)	/* Inhibit Final Activation */
+#define D_NT_ACT	(1<<9)	/* Activate Interface */
+#define D_NT_MFE	(1<<8)	/* Multiframe Enable */
+#define D_NT_RLB(v)	((v)<<5)	/* Remote Loopback */
+#define D_NT_LLB(v)	((v)<<2)	/* Local Loopback */
+#define D_NT_FACT	(1<<1)	/* Force Activation */
+#define D_NT_ABV	(1<<0)	/* Activate Bipolar Violation */
+
+/* Codec Setup */
+#define D_CDEC_CK(v)	((v)<<24)	/* Clock Select */
+#define D_CDEC_FED(v)	((v)<<12)	/* FSCOD Falling Edge Delay */
+#define D_CDEC_RED(v)	((v)<<0)	/* FSCOD Rising Edge Delay */
+
+/* Test */
+#define D_TEST_RAM(v)	((v)<<16)	/* RAM Pointer */
+#define D_TEST_SIZE(v)	((v)<<11)	/* */
+#define D_TEST_ROMONOFF	0x5	/* Toggle ROM opcode monitor on/off */
+#define D_TEST_PROC	0x6	/* MicroProcessor test */
+#define D_TEST_SER	0x7	/* Serial-Controller test */
+#define D_TEST_RAMREAD	0x8	/* Copy from Ram to system memory */
+#define D_TEST_RAMWRITE	0x9	/* Copy into Ram from system memory */
+#define D_TEST_RAMBIST	0xa	/* RAM Built-In Self Test */
+#define D_TEST_MCBIST	0xb	/* Microcontroller Built-In Self Test */
+#define D_TEST_DUMP	0xe	/* ROM Dump */
+
+/* CHI Data Mode */
+#define D_CDM_THI	(1<<8)	/* Transmit Data on CHIDR Pin */
+#define D_CDM_RHI	(1<<7)	/* Receive Data on CHIDX Pin */
+#define D_CDM_RCE	(1<<6)	/* Receive on Rising Edge of CHICK */
+#define D_CDM_XCE	(1<<2)	/* Transmit Data on Rising Edge of CHICK */
+#define D_CDM_XEN	(1<<1)	/* Transmit Highway Enable */
+#define D_CDM_REN	(1<<0)	/* Receive Highway Enable */
+
+/* The Interrupts */
+#define D_INTR_BRDY	1	/* Buffer Ready for processing */
+#define D_INTR_MINT	2	/* Marked Interrupt in RD/TD */
+#define D_INTR_IBEG	3	/* Flag to idle transition detected (HDLC) */
+#define D_INTR_IEND	4	/* Idle to flag transition detected (HDLC) */
+#define D_INTR_EOL	5	/* End of List */
+#define D_INTR_CMDI	6	/* Command has bean read */
+#define D_INTR_XCMP	8	/* Transmission of frame complete */
+#define D_INTR_SBRI	9	/* BRI status change info */
+#define D_INTR_FXDT	10	/* Fixed data change */
+#define D_INTR_CHIL	11	/* CHI lost frame sync (channel 36 only) */
+#define D_INTR_COLL	11	/* Unrecoverable D-Channel collision */
+#define D_INTR_DBYT	12	/* Dropped by frame slip */
+#define D_INTR_RBYT	13	/* Repeated by frame slip */
+#define D_INTR_LINT	14	/* Lost Interrupt */
+#define D_INTR_UNDR	15	/* DMA underrun */
+
+#define D_INTR_TE	32
+#define D_INTR_NT	34
+#define D_INTR_CHI	36
+#define D_INTR_CMD	38
+
+#define D_INTR_GETCHAN(v)	(((v)>>24) & 0x3f)
+#define D_INTR_GETCODE(v)	(((v)>>20) & 0xf)
+#define D_INTR_GETCMD(v)	(((v)>>16) & 0xf)
+#define D_INTR_GETVAL(v)	((v) & 0xffff)
+#define D_INTR_GETRVAL(v)	((v) & 0xfffff)
+
+#define D_P_0		0	/* TE receive anchor */
+#define D_P_1		1	/* TE transmit anchor */
+#define D_P_2		2	/* NT transmit anchor */
+#define D_P_3		3	/* NT receive anchor */
+#define D_P_4		4	/* CHI send data */
+#define D_P_5		5	/* CHI receive data */
+#define D_P_6		6	/* */
+#define D_P_7		7	/* */
+#define D_P_8		8	/* */
+#define D_P_9		9	/* */
+#define D_P_10		10	/* */
+#define D_P_11		11	/* */
+#define D_P_12		12	/* */
+#define D_P_13		13	/* */
+#define D_P_14		14	/* */
+#define D_P_15		15	/* */
+#define D_P_16		16	/* CHI anchor pipe */
+#define D_P_17		17	/* CHI send */
+#define D_P_18		18	/* CHI receive */
+#define D_P_19		19	/* CHI receive */
+#define D_P_20		20	/* CHI receive */
+#define D_P_21		21	/* */
+#define D_P_22		22	/* */
+#define D_P_23		23	/* */
+#define D_P_24		24	/* */
+#define D_P_25		25	/* */
+#define D_P_26		26	/* */
+#define D_P_27		27	/* */
+#define D_P_28		28	/* */
+#define D_P_29		29	/* */
+#define D_P_30		30	/* */
+#define D_P_31		31	/* */
+
+/* Transmit descriptor defines */
+#define DBRI_TD_F	(1<<31)	/* End of Frame */
+#define DBRI_TD_D	(1<<30)	/* Do not append CRC */
+#define DBRI_TD_CNT(v)	((v)<<16)	/* Number of valid bytes in the buffer */
+#define DBRI_TD_B	(1<<15)	/* Final interrupt */
+#define DBRI_TD_M	(1<<14)	/* Marker interrupt */
+#define DBRI_TD_I	(1<<13)	/* Transmit Idle Characters */
+#define DBRI_TD_FCNT(v)	(v)	/* Flag Count */
+#define DBRI_TD_UNR	(1<<3)	/* Underrun: transmitter is out of data */
+#define DBRI_TD_ABT	(1<<2)	/* Abort: frame aborted */
+#define DBRI_TD_TBC	(1<<0)	/* Transmit buffer Complete */
+#define DBRI_TD_STATUS(v)       ((v)&0xff)	/* Transmit status */
+			/* Maximum buffer size per TD: almost 8Kb */
+#define DBRI_TD_MAXCNT	((1 << 13) - 1)
+
+/* Receive descriptor defines */
+#define DBRI_RD_F	(1<<31)	/* End of Frame */
+#define DBRI_RD_C	(1<<30)	/* Completed buffer */
+#define DBRI_RD_B	(1<<15)	/* Final interrupt */
+#define DBRI_RD_M	(1<<14)	/* Marker interrupt */
+#define DBRI_RD_BCNT(v)	(v)	/* Buffer size */
+#define DBRI_RD_CRC	(1<<7)	/* 0: CRC is correct */
+#define DBRI_RD_BBC	(1<<6)	/* 1: Bad Byte received */
+#define DBRI_RD_ABT	(1<<5)	/* Abort: frame aborted */
+#define DBRI_RD_OVRN	(1<<3)	/* Overrun: data lost */
+#define DBRI_RD_STATUS(v)      ((v)&0xff)	/* Receive status */
+#define DBRI_RD_CNT(v) (((v)>>16)&0x1fff)	/* Valid bytes in the buffer */
+
+/* stream_info[] access */
+/* Translate the ALSA direction into the array index */
+#define DBRI_STREAMNO(substream)				\
+		(substream->stream == 				\
+		 SNDRV_PCM_STREAM_PLAYBACK? DBRI_PLAY: DBRI_REC)
+
+/* Return a pointer to dbri_streaminfo */
+#define DBRI_STREAM(dbri, substream)	&dbri->stream_info[DBRI_STREAMNO(substream)]
+
+static snd_dbri_t *dbri_list = NULL;	/* All DBRI devices */
+
+/*
+ * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
+ * So we have to reverse the bits. Note: not all bit lengths are supported
+ */
+static __u32 reverse_bytes(__u32 b, int len)
+{
+	switch (len) {
+	case 32:
+		b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
+	case 16:
+		b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
+	case 8:
+		b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
+	case 4:
+		b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
+	case 2:
+		b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
+	case 1:
+	case 0:
+		break;
+	default:
+		printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
+	};
+
+	return b;
+}
+
+/*
+****************************************************************************
+************** DBRI initialization and command synchronization *************
+****************************************************************************
+
+Commands are sent to the DBRI by building a list of them in memory,
+then writing the address of the first list item to DBRI register 8.
+The list is terminated with a WAIT command, which can generate a
+CPU interrupt if required.
+
+Since the DBRI can run in parallel with the CPU, several means of
+synchronization present themselves.  The original scheme (Rudolf's)
+was to set a flag when we "cmdlock"ed the DBRI, clear the flag when
+an interrupt signaled completion, and wait on a wait_queue if a routine
+attempted to cmdlock while the flag was set.  The problems arose when
+we tried to cmdlock from inside an interrupt handler, which might
+cause scheduling in an interrupt (if we waited), etc, etc
+
+A more sophisticated scheme might involve a circular command buffer
+or an array of command buffers.  A routine could fill one with
+commands and link it onto a list.  When a interrupt signaled
+completion of the current command buffer, look on the list for
+the next one.
+
+I've decided to implement something much simpler - after each command,
+the CPU waits for the DBRI to finish the command by polling the P bit
+in DBRI register 0.  I've tried to implement this in such a way
+that might make implementing a more sophisticated scheme easier.
+
+Every time a routine wants to write commands to the DBRI, it must
+first call dbri_cmdlock() and get an initial pointer into dbri->dma->cmd
+in return.  After the commands have been writen, dbri_cmdsend() is
+called with the final pointer value.
+
+*/
+
+enum dbri_lock_t { NoGetLock, GetLock };
+
+static volatile s32 *dbri_cmdlock(snd_dbri_t * dbri, enum dbri_lock_t get)
+{
+#ifndef SMP
+	if ((get == GetLock) && spin_is_locked(&dbri->lock)) {
+		printk(KERN_ERR "DBRI: cmdlock called while in spinlock.");
+	}
+#endif
+
+	/*if (get == GetLock) spin_lock(&dbri->lock); */
+	return &dbri->dma->cmd[0];
+}
+
+static void dbri_process_interrupt_buffer(snd_dbri_t *);
+
+static void dbri_cmdsend(snd_dbri_t * dbri, volatile s32 * cmd)
+{
+	int MAXLOOPS = 1000000;
+	int maxloops = MAXLOOPS;
+	volatile s32 *ptr;
+
+	for (ptr = &dbri->dma->cmd[0]; ptr < cmd; ptr++) {
+		dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
+	}
+
+	if ((cmd - &dbri->dma->cmd[0]) >= DBRI_NO_CMDS - 1) {
+		printk("DBRI: Command buffer overflow! (bug in driver)\n");
+		/* Ignore the last part. */
+		cmd = &dbri->dma->cmd[DBRI_NO_CMDS - 3];
+	}
+
+	*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
+	*(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
+	dbri->wait_seen = 0;
+	sbus_writel(dbri->dma_dvma, dbri->regs + REG8);
+	while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P))
+		barrier();
+	if (maxloops == 0) {
+		printk(KERN_ERR "DBRI: Chip never completed command buffer\n");
+		dprintk(D_CMD, "DBRI: Chip never completed command buffer\n");
+	} else {
+		while ((--maxloops) > 0 && (!dbri->wait_seen))
+			dbri_process_interrupt_buffer(dbri);
+		if (maxloops == 0) {
+			printk(KERN_ERR "DBRI: Chip never acked WAIT\n");
+			dprintk(D_CMD, "DBRI: Chip never acked WAIT\n");
+		} else {
+			dprintk(D_CMD, "Chip completed command "
+				"buffer (%d)\n", MAXLOOPS - maxloops);
+		}
+	}
+
+	/*spin_unlock(&dbri->lock); */
+}
+
+/* Lock must be held when calling this */
+static void dbri_reset(snd_dbri_t * dbri)
+{
+	int i;
+
+	dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
+		sbus_readl(dbri->regs + REG0),
+		sbus_readl(dbri->regs + REG2),
+		sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
+
+	sbus_writel(D_R, dbri->regs + REG0);	/* Soft Reset */
+	for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
+		udelay(10);
+}
+
+/* Lock must not be held before calling this */
+static void dbri_initialize(snd_dbri_t * dbri)
+{
+	volatile s32 *cmd;
+	u32 dma_addr, tmp;
+	unsigned long flags;
+	int n;
+
+	spin_lock_irqsave(&dbri->lock, flags);
+
+	dbri_reset(dbri);
+
+	cmd = dbri_cmdlock(dbri, NoGetLock);
+	dprintk(D_GEN, "init: cmd: %p, int: %p\n",
+		&dbri->dma->cmd[0], &dbri->dma->intr[0]);
+
+	/*
+	 * Initialize the interrupt ringbuffer.
+	 */
+	for (n = 0; n < DBRI_NO_INTS - 1; n++) {
+		dma_addr = dbri->dma_dvma;
+		dma_addr += dbri_dma_off(intr, ((n + 1) & DBRI_INT_BLK));
+		dbri->dma->intr[n * DBRI_INT_BLK] = dma_addr;
+	}
+	dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
+	dbri->dma->intr[n * DBRI_INT_BLK] = dma_addr;
+	dbri->dbri_irqp = 1;
+
+	/* Initialize pipes */
+	for (n = 0; n < DBRI_NO_PIPES; n++)
+		dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
+
+	/* We should query the openprom to see what burst sizes this
+	 * SBus supports.  For now, just disable all SBus bursts */
+	tmp = sbus_readl(dbri->regs + REG0);
+	tmp &= ~(D_G | D_S | D_E);
+	sbus_writel(tmp, dbri->regs + REG0);
+
+	/*
+	 * Set up the interrupt queue
+	 */
+	dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
+	*(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
+	*(cmd++) = dma_addr;
+
+	dbri_cmdsend(dbri, cmd);
+	spin_unlock_irqrestore(&dbri->lock, flags);
+}
+
+/*
+****************************************************************************
+************************** DBRI data pipe management ***********************
+****************************************************************************
+
+While DBRI control functions use the command and interrupt buffers, the
+main data path takes the form of data pipes, which can be short (command
+and interrupt driven), or long (attached to DMA buffers).  These functions
+provide a rudimentary means of setting up and managing the DBRI's pipes,
+but the calling functions have to make sure they respect the pipes' linked
+list ordering, among other things.  The transmit and receive functions
+here interface closely with the transmit and receive interrupt code.
+
+*/
+static int pipe_active(snd_dbri_t * dbri, int pipe)
+{
+	return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
+}
+
+/* reset_pipe(dbri, pipe)
+ *
+ * Called on an in-use pipe to clear anything being transmitted or received
+ * Lock must be held before calling this.
+ */
+static void reset_pipe(snd_dbri_t * dbri, int pipe)
+{
+	int sdp;
+	int desc;
+	volatile int *cmd;
+
+	if (pipe < 0 || pipe > 31) {
+		printk("DBRI: reset_pipe called with illegal pipe number\n");
+		return;
+	}
+
+	sdp = dbri->pipes[pipe].sdp;
+	if (sdp == 0) {
+		printk("DBRI: reset_pipe called on uninitialized pipe\n");
+		return;
+	}
+
+	cmd = dbri_cmdlock(dbri, NoGetLock);
+	*(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
+	*(cmd++) = 0;
+	dbri_cmdsend(dbri, cmd);
+
+	desc = dbri->pipes[pipe].first_desc;
+	while (desc != -1) {
+		dbri->descs[desc].inuse = 0;
+		desc = dbri->descs[desc].next;
+	}
+
+	dbri->pipes[pipe].desc = -1;
+	dbri->pipes[pipe].first_desc = -1;
+}
+
+/* FIXME: direction as an argument? */
+static void setup_pipe(snd_dbri_t * dbri, int pipe, int sdp)
+{
+	if (pipe < 0 || pipe > 31) {
+		printk("DBRI: setup_pipe called with illegal pipe number\n");
+		return;
+	}
+
+	if ((sdp & 0xf800) != sdp) {
+		printk("DBRI: setup_pipe called with strange SDP value\n");
+		/* sdp &= 0xf800; */
+	}
+
+	/* If this is a fixed receive pipe, arrange for an interrupt
+	 * every time its data changes
+	 */
+	if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
+		sdp |= D_SDP_CHANGE;
+
+	sdp |= D_PIPE(pipe);
+	dbri->pipes[pipe].sdp = sdp;
+	dbri->pipes[pipe].desc = -1;
+	dbri->pipes[pipe].first_desc = -1;
+	if (sdp & D_SDP_TO_SER)
+		dbri->pipes[pipe].direction = PIPEoutput;
+	else
+		dbri->pipes[pipe].direction = PIPEinput;
+
+	reset_pipe(dbri, pipe);
+}
+
+/* FIXME: direction not needed */
+static void link_time_slot(snd_dbri_t * dbri, int pipe,
+			   enum in_or_out direction, int basepipe,
+			   int length, int cycle)
+{
+	volatile s32 *cmd;
+	int val;
+	int prevpipe;
+	int nextpipe;
+
+	if (pipe < 0 || pipe > 31 || basepipe < 0 || basepipe > 31) {
+		printk
+		    ("DBRI: link_time_slot called with illegal pipe number\n");
+		return;
+	}
+
+	if (dbri->pipes[pipe].sdp == 0 || dbri->pipes[basepipe].sdp == 0) {
+		printk("DBRI: link_time_slot called on uninitialized pipe\n");
+		return;
+	}
+
+	/* Deal with CHI special case:
+	 * "If transmission on edges 0 or 1 is desired, then cycle n
+	 *  (where n = # of bit times per frame...) must be used."
+	 *                  - DBRI data sheet, page 11
+	 */
+	if (basepipe == 16 && direction == PIPEoutput && cycle == 0)
+		cycle = dbri->chi_bpf;
+
+	if (basepipe == pipe) {
+		prevpipe = pipe;
+		nextpipe = pipe;
+	} else {
+		/* We're not initializing a new linked list (basepipe != pipe),
+		 * so run through the linked list and find where this pipe
+		 * should be sloted in, based on its cycle.  CHI confuses
+		 * things a bit, since it has a single anchor for both its
+		 * transmit and receive lists.
+		 */
+		if (basepipe == 16) {
+			if (direction == PIPEinput) {
+				prevpipe = dbri->chi_in_pipe;
+			} else {
+				prevpipe = dbri->chi_out_pipe;
+			}
+		} else {
+			prevpipe = basepipe;
+		}
+
+		nextpipe = dbri->pipes[prevpipe].nextpipe;
+
+		while (dbri->pipes[nextpipe].cycle < cycle
+		       && dbri->pipes[nextpipe].nextpipe != basepipe) {
+			prevpipe = nextpipe;
+			nextpipe = dbri->pipes[nextpipe].nextpipe;
+		}
+	}
+
+	if (prevpipe == 16) {
+		if (direction == PIPEinput) {
+			dbri->chi_in_pipe = pipe;
+		} else {
+			dbri->chi_out_pipe = pipe;
+		}
+	} else {
+		dbri->pipes[prevpipe].nextpipe = pipe;
+	}
+
+	dbri->pipes[pipe].nextpipe = nextpipe;
+	dbri->pipes[pipe].cycle = cycle;
+	dbri->pipes[pipe].length = length;
+
+	cmd = dbri_cmdlock(dbri, NoGetLock);
+
+	if (direction == PIPEinput) {
+		val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
+		*(cmd++) = DBRI_CMD(D_DTS, 0, val);
+		*(cmd++) =
+		    D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
+		*(cmd++) = 0;
+	} else {
+		val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
+		*(cmd++) = DBRI_CMD(D_DTS, 0, val);
+		*(cmd++) = 0;
+		*(cmd++) =
+		    D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
+	}
+
+	dbri_cmdsend(dbri, cmd);
+}
+
+static void unlink_time_slot(snd_dbri_t * dbri, int pipe,
+			     enum in_or_out direction, int prevpipe,
+			     int nextpipe)
+{
+	volatile s32 *cmd;
+	int val;
+
+	if (pipe < 0 || pipe > 31 || prevpipe < 0 || prevpipe > 31) {
+		printk
+		    ("DBRI: unlink_time_slot called with illegal pipe number\n");
+		return;
+	}
+
+	cmd = dbri_cmdlock(dbri, NoGetLock);
+
+	if (direction == PIPEinput) {
+		val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
+		*(cmd++) = DBRI_CMD(D_DTS, 0, val);
+		*(cmd++) = D_TS_NEXT(nextpipe);
+		*(cmd++) = 0;
+	} else {
+		val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
+		*(cmd++) = DBRI_CMD(D_DTS, 0, val);
+		*(cmd++) = 0;
+		*(cmd++) = D_TS_NEXT(nextpipe);
+	}
+
+	dbri_cmdsend(dbri, cmd);
+}
+
+/* xmit_fixed() / recv_fixed()
+ *
+ * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
+ * expected to change much, and which we don't need to buffer.
+ * The DBRI only interrupts us when the data changes (receive pipes),
+ * or only changes the data when this function is called (transmit pipes).
+ * Only short pipes (numbers 16-31) can be used in fixed data mode.
+ *
+ * These function operate on a 32-bit field, no matter how large
+ * the actual time slot is.  The interrupt handler takes care of bit
+ * ordering and alignment.  An 8-bit time slot will always end up
+ * in the low-order 8 bits, filled either MSB-first or LSB-first,
+ * depending on the settings passed to setup_pipe()
+ */
+static void xmit_fixed(snd_dbri_t * dbri, int pipe, unsigned int data)
+{
+	volatile s32 *cmd;
+
+	if (pipe < 16 || pipe > 31) {
+		printk("DBRI: xmit_fixed: Illegal pipe number\n");
+		return;
+	}
+
+	if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
+		printk("DBRI: xmit_fixed: Uninitialized pipe %d\n", pipe);
+		return;
+	}
+
+	if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
+		printk("DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
+		return;
+	}
+
+	if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
+		printk("DBRI: xmit_fixed: Called on receive pipe %d\n", pipe);
+		return;
+	}
+
+	/* DBRI short pipes always transmit LSB first */
+
+	if (dbri->pipes[pipe].sdp & D_SDP_MSB)
+		data = reverse_bytes(data, dbri->pipes[pipe].length);
+
+	cmd = dbri_cmdlock(dbri, GetLock);
+
+	*(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
+	*(cmd++) = data;
+
+	dbri_cmdsend(dbri, cmd);
+}
+
+static void recv_fixed(snd_dbri_t * dbri, int pipe, volatile __u32 * ptr)
+{
+	if (pipe < 16 || pipe > 31) {
+		printk("DBRI: recv_fixed called with illegal pipe number\n");
+		return;
+	}
+
+	if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
+		printk("DBRI: recv_fixed called on non-fixed pipe %d\n", pipe);
+		return;
+	}
+
+	if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
+		printk("DBRI: recv_fixed called on transmit pipe %d\n", pipe);
+		return;
+	}
+
+	dbri->pipes[pipe].recv_fixed_ptr = ptr;
+}
+
+/* setup_descs()
+ *
+ * Setup transmit/receive data on a "long" pipe - i.e, one associated
+ * with a DMA buffer.
+ *
+ * Only pipe numbers 0-15 can be used in this mode.
+ *
+ * This function takes a stream number pointing to a data buffer,
+ * and work by building chains of descriptors which identify the
+ * data buffers.  Buffers too large for a single descriptor will
+ * be spread across multiple descriptors.
+ */
+static int setup_descs(snd_dbri_t * dbri, int streamno, unsigned int period)
+{
+	dbri_streaminfo_t *info = &dbri->stream_info[streamno];
+	__u32 dvma_buffer;
+	int desc = 0;
+	int len;
+	int first_desc = -1;
+	int last_desc = -1;
+
+	if (info->pipe < 0 || info->pipe > 15) {
+		printk("DBRI: setup_descs: Illegal pipe number\n");
+		return -2;
+	}
+
+	if (dbri->pipes[info->pipe].sdp == 0) {
+		printk("DBRI: setup_descs: Uninitialized pipe %d\n",
+		       info->pipe);
+		return -2;
+	}
+
+	dvma_buffer = info->dvma_buffer;
+	len = info->size;
+
+	if (streamno == DBRI_PLAY) {
+		if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
+			printk("DBRI: setup_descs: Called on receive pipe %d\n",
+			       info->pipe);
+			return -2;
+		}
+	} else {
+		if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
+			printk
+			    ("DBRI: setup_descs: Called on transmit pipe %d\n",
+			     info->pipe);
+			return -2;
+		}
+		/* Should be able to queue multiple buffers to receive on a pipe */
+		if (pipe_active(dbri, info->pipe)) {
+			printk("DBRI: recv_on_pipe: Called on active pipe %d\n",
+			       info->pipe);
+			return -2;
+		}
+
+		/* Make sure buffer size is multiple of four */
+		len &= ~3;
+	}
+
+	while (len > 0) {
+		int mylen;
+
+		for (; desc < DBRI_NO_DESCS; desc++) {
+			if (!dbri->descs[desc].inuse)
+				break;
+		}
+		if (desc == DBRI_NO_DESCS) {
+			printk("DBRI: setup_descs: No descriptors\n");
+			return -1;
+		}
+
+		if (len > DBRI_TD_MAXCNT) {
+			mylen = DBRI_TD_MAXCNT;	/* 8KB - 1 */
+		} else {
+			mylen = len;
+		}
+		if (mylen > period) {
+			mylen = period;
+		}
+
+		dbri->descs[desc].inuse = 1;
+		dbri->descs[desc].next = -1;
+		dbri->dma->desc[desc].ba = dvma_buffer;
+		dbri->dma->desc[desc].nda = 0;
+
+		if (streamno == DBRI_PLAY) {
+			dbri->descs[desc].len = mylen;
+			dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
+			dbri->dma->desc[desc].word4 = 0;
+			if (first_desc != -1)
+				dbri->dma->desc[desc].word1 |= DBRI_TD_M;
+		} else {
+			dbri->descs[desc].len = 0;
+			dbri->dma->desc[desc].word1 = 0;
+			dbri->dma->desc[desc].word4 =
+			    DBRI_RD_B | DBRI_RD_BCNT(mylen);
+		}
+
+		if (first_desc == -1) {
+			first_desc = desc;
+		} else {
+			dbri->descs[last_desc].next = desc;
+			dbri->dma->desc[last_desc].nda =
+			    dbri->dma_dvma + dbri_dma_off(desc, desc);
+		}
+
+		last_desc = desc;
+		dvma_buffer += mylen;
+		len -= mylen;
+	}
+
+	if (first_desc == -1 || last_desc == -1) {
+		printk("DBRI: setup_descs: Not enough descriptors available\n");
+		return -1;
+	}
+
+	dbri->dma->desc[last_desc].word1 &= ~DBRI_TD_M;
+	if (streamno == DBRI_PLAY) {
+		dbri->dma->desc[last_desc].word1 |=
+		    DBRI_TD_I | DBRI_TD_F | DBRI_TD_B;
+	}
+	dbri->pipes[info->pipe].first_desc = first_desc;
+	dbri->pipes[info->pipe].desc = first_desc;
+
+	for (desc = first_desc; desc != -1; desc = dbri->descs[desc].next) {
+		dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
+			desc,
+			dbri->dma->desc[desc].word1,
+			dbri->dma->desc[desc].ba,
+			dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
+	}
+	return 0;
+}
+
+/*
+****************************************************************************
+************************** DBRI - CHI interface ****************************
+****************************************************************************
+
+The CHI is a four-wire (clock, frame sync, data in, data out) time-division
+multiplexed serial interface which the DBRI can operate in either master
+(give clock/frame sync) or slave (take clock/frame sync) mode.
+
+*/
+
+enum master_or_slave { CHImaster, CHIslave };
+
+static void reset_chi(snd_dbri_t * dbri, enum master_or_slave master_or_slave,
+		      int bits_per_frame)
+{
+	volatile s32 *cmd;
+	int val;
+	static int chi_initialized = 0;	/* FIXME: mutex? */
+
+	if (!chi_initialized) {
+
+		cmd = dbri_cmdlock(dbri, GetLock);
+
+		/* Set CHI Anchor: Pipe 16 */
+
+		val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(16) | D_PIPE(16);
+		*(cmd++) = DBRI_CMD(D_DTS, 0, val);
+		*(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
+		*(cmd++) = 0;
+
+		val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(16) | D_PIPE(16);
+		*(cmd++) = DBRI_CMD(D_DTS, 0, val);
+		*(cmd++) = 0;
+		*(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
+
+		dbri->pipes[16].sdp = 1;
+		dbri->pipes[16].nextpipe = 16;
+		dbri->chi_in_pipe = 16;
+		dbri->chi_out_pipe = 16;
+
+#if 0
+		chi_initialized++;
+#endif
+	} else {
+		int pipe;
+
+		for (pipe = dbri->chi_in_pipe;
+		     pipe != 16; pipe = dbri->pipes[pipe].nextpipe) {
+			unlink_time_slot(dbri, pipe, PIPEinput,
+					 16, dbri->pipes[pipe].nextpipe);
+		}
+		for (pipe = dbri->chi_out_pipe;
+		     pipe != 16; pipe = dbri->pipes[pipe].nextpipe) {
+			unlink_time_slot(dbri, pipe, PIPEoutput,
+					 16, dbri->pipes[pipe].nextpipe);
+		}
+
+		dbri->chi_in_pipe = 16;
+		dbri->chi_out_pipe = 16;
+
+		cmd = dbri_cmdlock(dbri, GetLock);
+	}
+
+	if (master_or_slave == CHIslave) {
+		/* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
+		 *
+		 * CHICM  = 0 (slave mode, 8 kHz frame rate)
+		 * IR     = give immediate CHI status interrupt
+		 * EN     = give CHI status interrupt upon change
+		 */
+		*(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
+	} else {
+		/* Setup DBRI for CHI Master - generate clock, FS
+		 *
+		 * BPF                          =  bits per 8 kHz frame
+		 * 12.288 MHz / CHICM_divisor   = clock rate
+		 * FD  =  1 - drive CHIFS on rising edge of CHICK
+		 */
+		int clockrate = bits_per_frame * 8;
+		int divisor = 12288 / clockrate;
+
+		if (divisor > 255 || divisor * clockrate != 12288)
+			printk("DBRI: illegal bits_per_frame in setup_chi\n");
+
+		*(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
+				    | D_CHI_BPF(bits_per_frame));
+	}
+
+	dbri->chi_bpf = bits_per_frame;
+
+	/* CHI Data Mode
+	 *
+	 * RCE   =  0 - receive on falling edge of CHICK
+	 * XCE   =  1 - transmit on rising edge of CHICK
+	 * XEN   =  1 - enable transmitter
+	 * REN   =  1 - enable receiver
+	 */
+
+	*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
+	*(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
+
+	dbri_cmdsend(dbri, cmd);
+}
+
+/*
+****************************************************************************
+*********************** CS4215 audio codec management **********************
+****************************************************************************
+
+In the standard SPARC audio configuration, the CS4215 codec is attached
+to the DBRI via the CHI interface and few of the DBRI's PIO pins.
+
+*/
+static void cs4215_setup_pipes(snd_dbri_t * dbri)
+{
+	/*
+	 * Data mode:
+	 * Pipe  4: Send timeslots 1-4 (audio data)
+	 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
+	 * Pipe  6: Receive timeslots 1-4 (audio data)
+	 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
+	 *          interrupt, and the rest of the data (slot 5 and 8) is
+	 *          not relevant for us (only for doublechecking).
+	 *
+	 * Control mode:
+	 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
+	 * Pipe 18: Receive timeslot 1 (clb).
+	 * Pipe 19: Receive timeslot 7 (version). 
+	 */
+
+	setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
+	setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
+	setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
+	setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
+
+	setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
+	setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
+	setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
+}
+
+static int cs4215_init_data(struct cs4215 *mm)
+{
+	/*
+	 * No action, memory resetting only.
+	 *
+	 * Data Time Slot 5-8
+	 * Speaker,Line and Headphone enable. Gain set to the half.
+	 * Input is mike.
+	 */
+	mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
+	mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
+	mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
+	mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
+
+	/*
+	 * Control Time Slot 1-4
+	 * 0: Default I/O voltage scale
+	 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
+	 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
+	 * 3: Tests disabled
+	 */
+	mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
+	mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
+	mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
+	mm->ctrl[3] = 0;
+
+	mm->status = 0;
+	mm->version = 0xff;
+	mm->precision = 8;	/* For ULAW */
+	mm->channels = 2;
+
+	return 0;
+}
+
+static void cs4215_setdata(snd_dbri_t * dbri, int muted)
+{
+	if (muted) {
+		dbri->mm.data[0] |= 63;
+		dbri->mm.data[1] |= 63;
+		dbri->mm.data[2] &= ~15;
+		dbri->mm.data[3] &= ~15;
+	} else {
+		/* Start by setting the playback attenuation. */
+		dbri_streaminfo_t *info = &dbri->stream_info[DBRI_PLAY];
+		int left_gain = info->left_gain % 64;
+		int right_gain = info->right_gain % 64;
+
+		if (info->balance < DBRI_MID_BALANCE) {
+			right_gain *= info->balance;
+			right_gain /= DBRI_MID_BALANCE;
+		} else {
+			left_gain *= DBRI_RIGHT_BALANCE - info->balance;
+			left_gain /= DBRI_MID_BALANCE;
+		}
+
+		dbri->mm.data[0] &= ~0x3f;	/* Reset the volume bits */
+		dbri->mm.data[1] &= ~0x3f;
+		dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
+		dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
+
+		/* Now set the recording gain. */
+		info = &dbri->stream_info[DBRI_REC];
+		left_gain = info->left_gain % 16;
+		right_gain = info->right_gain % 16;
+		dbri->mm.data[2] |= CS4215_LG(left_gain);
+		dbri->mm.data[3] |= CS4215_RG(right_gain);
+	}
+
+	xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
+}
+
+/*
+ * Set the CS4215 to data mode.
+ */
+static void cs4215_open(snd_dbri_t * dbri)
+{
+	int data_width;
+	u32 tmp;
+
+	dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
+		dbri->mm.channels, dbri->mm.precision);
+
+	/* Temporarily mute outputs, and wait 1/8000 sec (125 us)
+	 * to make sure this takes.  This avoids clicking noises.
+	 */
+
+	cs4215_setdata(dbri, 1);
+	udelay(125);
+
+	/*
+	 * Data mode:
+	 * Pipe  4: Send timeslots 1-4 (audio data)
+	 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
+	 * Pipe  6: Receive timeslots 1-4 (audio data)
+	 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
+	 *          interrupt, and the rest of the data (slot 5 and 8) is
+	 *          not relevant for us (only for doublechecking).
+	 *
+	 * Just like in control mode, the time slots are all offset by eight
+	 * bits.  The CS4215, it seems, observes TSIN (the delayed signal)
+	 * even if it's the CHI master.  Don't ask me...
+	 */
+	tmp = sbus_readl(dbri->regs + REG0);
+	tmp &= ~(D_C);		/* Disable CHI */
+	sbus_writel(tmp, dbri->regs + REG0);
+
+	/* Switch CS4215 to data mode - set PIO3 to 1 */
+	sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
+		    (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
+
+	reset_chi(dbri, CHIslave, 128);
+
+	/* Note: this next doesn't work for 8-bit stereo, because the two
+	 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
+	 * (See CS4215 datasheet Fig 15)
+	 *
+	 * DBRI non-contiguous mode would be required to make this work.
+	 */
+	data_width = dbri->mm.channels * dbri->mm.precision;
+
+	link_time_slot(dbri, 20, PIPEoutput, 16, 32, dbri->mm.offset + 32);
+	link_time_slot(dbri, 4, PIPEoutput, 16, data_width, dbri->mm.offset);
+	link_time_slot(dbri, 6, PIPEinput, 16, data_width, dbri->mm.offset);
+	link_time_slot(dbri, 21, PIPEinput, 16, 16, dbri->mm.offset + 40);
+
+	/* FIXME: enable CHI after _setdata? */
+	tmp = sbus_readl(dbri->regs + REG0);
+	tmp |= D_C;		/* Enable CHI */
+	sbus_writel(tmp, dbri->regs + REG0);
+
+	cs4215_setdata(dbri, 0);
+}
+
+/*
+ * Send the control information (i.e. audio format)
+ */
+static int cs4215_setctrl(snd_dbri_t * dbri)
+{
+	int i, val;
+	u32 tmp;
+
+	/* FIXME - let the CPU do something useful during these delays */
+
+	/* Temporarily mute outputs, and wait 1/8000 sec (125 us)
+	 * to make sure this takes.  This avoids clicking noises.
+	 */
+
+	cs4215_setdata(dbri, 1);
+	udelay(125);
+
+	/*
+	 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
+	 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
+	 */
+	val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
+	sbus_writel(val, dbri->regs + REG2);
+	dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
+	udelay(34);
+
+	/* In Control mode, the CS4215 is a slave device, so the DBRI must
+	 * operate as CHI master, supplying clocking and frame synchronization.
+	 *
+	 * In Data mode, however, the CS4215 must be CHI master to insure
+	 * that its data stream is synchronous with its codec.
+	 *
+	 * The upshot of all this?  We start by putting the DBRI into master
+	 * mode, program the CS4215 in Control mode, then switch the CS4215
+	 * into Data mode and put the DBRI into slave mode.  Various timing
+	 * requirements must be observed along the way.
+	 *
+	 * Oh, and one more thing, on a SPARCStation 20 (and maybe
+	 * others?), the addressing of the CS4215's time slots is
+	 * offset by eight bits, so we add eight to all the "cycle"
+	 * values in the Define Time Slot (DTS) commands.  This is
+	 * done in hardware by a TI 248 that delays the DBRI->4215
+	 * frame sync signal by eight clock cycles.  Anybody know why?
+	 */
+	tmp = sbus_readl(dbri->regs + REG0);
+	tmp &= ~D_C;		/* Disable CHI */
+	sbus_writel(tmp, dbri->regs + REG0);
+
+	reset_chi(dbri, CHImaster, 128);
+
+	/*
+	 * Control mode:
+	 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
+	 * Pipe 18: Receive timeslot 1 (clb).
+	 * Pipe 19: Receive timeslot 7 (version). 
+	 */
+
+	link_time_slot(dbri, 17, PIPEoutput, 16, 32, dbri->mm.offset);
+	link_time_slot(dbri, 18, PIPEinput, 16, 8, dbri->mm.offset);
+	link_time_slot(dbri, 19, PIPEinput, 16, 8, dbri->mm.offset + 48);
+
+	/* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
+	dbri->mm.ctrl[0] &= ~CS4215_CLB;
+	xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
+
+	tmp = sbus_readl(dbri->regs + REG0);
+	tmp |= D_C;		/* Enable CHI */
+	sbus_writel(tmp, dbri->regs + REG0);
+
+	for (i = 64; ((dbri->mm.status & 0xe4) != 0x20); --i) {
+		udelay(125);
+	}
+	if (i == 0) {
+		dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
+			dbri->mm.status);
+		return -1;
+	}
+
+	/* Disable changes to our copy of the version number, as we are about
+	 * to leave control mode.
+	 */
+	recv_fixed(dbri, 19, NULL);
+
+	/* Terminate CS4215 control mode - data sheet says
+	 * "Set CLB=1 and send two more frames of valid control info"
+	 */
+	dbri->mm.ctrl[0] |= CS4215_CLB;
+	xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
+
+	/* Two frames of control info @ 8kHz frame rate = 250 us delay */
+	udelay(250);
+
+	cs4215_setdata(dbri, 0);
+
+	return 0;
+}
+
+/*
+ * Setup the codec with the sampling rate, audio format and number of
+ * channels.
+ * As part of the process we resend the settings for the data
+ * timeslots as well.
+ */
+static int cs4215_prepare(snd_dbri_t * dbri, unsigned int rate,
+			  snd_pcm_format_t format, unsigned int channels)
+{
+	int freq_idx;
+	int ret = 0;
+
+	/* Lookup index for this rate */
+	for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
+		if (CS4215_FREQ[freq_idx].freq == rate)
+			break;
+	}
+	if (CS4215_FREQ[freq_idx].freq != rate) {
+		printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
+		return -1;
+	}
+
+	switch (format) {
+	case SNDRV_PCM_FORMAT_MU_LAW:
+		dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
+		dbri->mm.precision = 8;
+		break;
+	case SNDRV_PCM_FORMAT_A_LAW:
+		dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
+		dbri->mm.precision = 8;
+		break;
+	case SNDRV_PCM_FORMAT_U8:
+		dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
+		dbri->mm.precision = 8;
+		break;
+	case SNDRV_PCM_FORMAT_S16_BE:
+		dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
+		dbri->mm.precision = 16;
+		break;
+	default:
+		printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
+		return -1;
+	}
+
+	/* Add rate parameters */
+	dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
+	dbri->mm.ctrl[2] = CS4215_XCLK |
+	    CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
+
+	dbri->mm.channels = channels;
+	/* Stereo bit: 8 bit stereo not working yet. */
+	if ((channels > 1) && (dbri->mm.precision == 16))
+		dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
+
+	ret = cs4215_setctrl(dbri);
+	if (ret == 0)
+		cs4215_open(dbri);	/* set codec to data mode */
+
+	return ret;
+}
+
+/*
+ *
+ */
+static int cs4215_init(snd_dbri_t * dbri)
+{
+	u32 reg2 = sbus_readl(dbri->regs + REG2);
+	dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
+
+	/* Look for the cs4215 chips */
+	if (reg2 & D_PIO2) {
+		dprintk(D_MM, "Onboard CS4215 detected\n");
+		dbri->mm.onboard = 1;
+	}
+	if (reg2 & D_PIO0) {
+		dprintk(D_MM, "Speakerbox detected\n");
+		dbri->mm.onboard = 0;
+
+		if (reg2 & D_PIO2) {
+			printk(KERN_INFO "DBRI: Using speakerbox / "
+			       "ignoring onboard mmcodec.\n");
+			sbus_writel(D_ENPIO2, dbri->regs + REG2);
+		}
+	}
+
+	if (!(reg2 & (D_PIO0 | D_PIO2))) {
+		printk(KERN_ERR "DBRI: no mmcodec found.\n");
+		return -EIO;
+	}
+
+	cs4215_setup_pipes(dbri);
+
+	cs4215_init_data(&dbri->mm);
+
+	/* Enable capture of the status & version timeslots. */
+	recv_fixed(dbri, 18, &dbri->mm.status);
+	recv_fixed(dbri, 19, &dbri->mm.version);
+
+	dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
+	if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
+		dprintk(D_MM, "CS4215 failed probe at offset %d\n",
+			dbri->mm.offset);
+		return -EIO;
+	}
+	dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
+
+	return 0;
+}
+
+/*
+****************************************************************************
+*************************** DBRI interrupt handler *************************
+****************************************************************************
+
+The DBRI communicates with the CPU mainly via a circular interrupt
+buffer.  When an interrupt is signaled, the CPU walks through the
+buffer and calls dbri_process_one_interrupt() for each interrupt word.
+Complicated interrupts are handled by dedicated functions (which
+appear first in this file).  Any pending interrupts can be serviced by
+calling dbri_process_interrupt_buffer(), which works even if the CPU's
+interrupts are disabled.  This function is used by dbri_cmdsend()
+to make sure we're synced up with the chip after each command sequence,
+even if we're running cli'ed.
+
+*/
+
+/* xmit_descs()
+ *
+ * Transmit the current TD's for recording/playing, if needed.
+ * For playback, ALSA has filled the DMA memory with new data (we hope).
+ */
+static void xmit_descs(unsigned long data)
+{
+	snd_dbri_t *dbri = (snd_dbri_t *) data;
+	dbri_streaminfo_t *info;
+	volatile s32 *cmd;
+	unsigned long flags;
+	int first_td;
+
+	if (dbri == NULL)
+		return;		/* Disabled */
+
+	/* First check the recording stream for buffer overflow */
+	info = &dbri->stream_info[DBRI_REC];
+	spin_lock_irqsave(&dbri->lock, flags);
+
+	if ((info->left >= info->size) && (info->pipe >= 0)) {
+		first_td = dbri->pipes[info->pipe].first_desc;
+
+		dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
+
+		/* Stream could be closed by the time we run. */
+		if (first_td < 0) {
+			goto play;
+		}
+
+		cmd = dbri_cmdlock(dbri, NoGetLock);
+		*(cmd++) = DBRI_CMD(D_SDP, 0,
+				    dbri->pipes[info->pipe].sdp
+				    | D_SDP_P | D_SDP_EVERY | D_SDP_C);
+		*(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
+		dbri_cmdsend(dbri, cmd);
+
+		/* Reset our admin of the pipe & bytes read. */
+		dbri->pipes[info->pipe].desc = first_td;
+		info->left = 0;
+	}
+
+play:
+	spin_unlock_irqrestore(&dbri->lock, flags);
+
+	/* Now check the playback stream for buffer underflow */
+	info = &dbri->stream_info[DBRI_PLAY];
+	spin_lock_irqsave(&dbri->lock, flags);
+
+	if ((info->left <= 0) && (info->pipe >= 0)) {
+		first_td = dbri->pipes[info->pipe].first_desc;
+
+		dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
+
+		/* Stream could be closed by the time we run. */
+		if (first_td < 0) {
+			spin_unlock_irqrestore(&dbri->lock, flags);
+			return;
+		}
+
+		cmd = dbri_cmdlock(dbri, NoGetLock);
+		*(cmd++) = DBRI_CMD(D_SDP, 0,
+				    dbri->pipes[info->pipe].sdp
+				    | D_SDP_P | D_SDP_EVERY | D_SDP_C);
+		*(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
+		dbri_cmdsend(dbri, cmd);
+
+		/* Reset our admin of the pipe & bytes written. */
+		dbri->pipes[info->pipe].desc = first_td;
+		info->left = info->size;
+	}
+	spin_unlock_irqrestore(&dbri->lock, flags);
+}
+
+DECLARE_TASKLET(xmit_descs_task, xmit_descs, 0);
+
+/* transmission_complete_intr()
+ *
+ * Called by main interrupt handler when DBRI signals transmission complete
+ * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
+ *
+ * Walks through the pipe's list of transmit buffer descriptors, releasing
+ * each one's DMA buffer (if present), flagging the descriptor available,
+ * and signaling its callback routine (if present), before proceeding
+ * to the next one.  Stops when the first descriptor is found without
+ * TBC (Transmit Buffer Complete) set, or we've run through them all.
+ */
+
+static void transmission_complete_intr(snd_dbri_t * dbri, int pipe)
+{
+	dbri_streaminfo_t *info;
+	int td;
+	int status;
+
+	info = &dbri->stream_info[DBRI_PLAY];
+
+	td = dbri->pipes[pipe].desc;
+	while (td >= 0) {
+		if (td >= DBRI_NO_DESCS) {
+			printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
+			return;
+		}
+
+		status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
+		if (!(status & DBRI_TD_TBC)) {
+			break;
+		}
+
+		dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
+
+		dbri->dma->desc[td].word4 = 0;	/* Reset it for next time. */
+		info->offset += dbri->descs[td].len;
+		info->left -= dbri->descs[td].len;
+
+		/* On the last TD, transmit them all again. */
+		if (dbri->descs[td].next == -1) {
+			if (info->left > 0) {
+				printk(KERN_WARNING
+				       "%d bytes left after last transfer.\n",
+				       info->left);
+				info->left = 0;
+			}
+			tasklet_schedule(&xmit_descs_task);
+		}
+
+		td = dbri->descs[td].next;
+		dbri->pipes[pipe].desc = td;
+	}
+
+	/* Notify ALSA */
+	if (spin_is_locked(&dbri->lock)) {
+		spin_unlock(&dbri->lock);
+		snd_pcm_period_elapsed(info->substream);
+		spin_lock(&dbri->lock);
+	} else
+		snd_pcm_period_elapsed(info->substream);
+}
+
+static void reception_complete_intr(snd_dbri_t * dbri, int pipe)
+{
+	dbri_streaminfo_t *info;
+	int rd = dbri->pipes[pipe].desc;
+	s32 status;
+
+	if (rd < 0 || rd >= DBRI_NO_DESCS) {
+		printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
+		return;
+	}
+
+	dbri->descs[rd].inuse = 0;
+	dbri->pipes[pipe].desc = dbri->descs[rd].next;
+	status = dbri->dma->desc[rd].word1;
+	dbri->dma->desc[rd].word1 = 0;	/* Reset it for next time. */
+
+	info = &dbri->stream_info[DBRI_REC];
+	info->offset += DBRI_RD_CNT(status);
+	info->left += DBRI_RD_CNT(status);
+
+	/* FIXME: Check status */
+
+	dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
+		rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
+
+	/* On the last TD, transmit them all again. */
+	if (dbri->descs[rd].next == -1) {
+		if (info->left > info->size) {
+			printk(KERN_WARNING
+			       "%d bytes recorded in %d size buffer.\n",
+			       info->left, info->size);
+		}
+		tasklet_schedule(&xmit_descs_task);
+	}
+
+	/* Notify ALSA */
+	if (spin_is_locked(&dbri->lock)) {
+		spin_unlock(&dbri->lock);
+		snd_pcm_period_elapsed(info->substream);
+		spin_lock(&dbri->lock);
+	} else
+		snd_pcm_period_elapsed(info->substream);
+}
+
+static void dbri_process_one_interrupt(snd_dbri_t * dbri, int x)
+{
+	int val = D_INTR_GETVAL(x);
+	int channel = D_INTR_GETCHAN(x);
+	int command = D_INTR_GETCMD(x);
+	int code = D_INTR_GETCODE(x);
+#ifdef DBRI_DEBUG
+	int rval = D_INTR_GETRVAL(x);
+#endif
+
+	if (channel == D_INTR_CMD) {
+		dprintk(D_CMD, "INTR: Command: %-5s  Value:%d\n",
+			cmds[command], val);
+	} else {
+		dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
+			channel, code, rval);
+	}
+
+	if (channel == D_INTR_CMD && command == D_WAIT) {
+		dbri->wait_seen++;
+		return;
+	}
+
+	switch (code) {
+	case D_INTR_BRDY:
+		reception_complete_intr(dbri, channel);
+		break;
+	case D_INTR_XCMP:
+	case D_INTR_MINT:
+		transmission_complete_intr(dbri, channel);
+		break;
+	case D_INTR_UNDR:
+		/* UNDR - Transmission underrun
+		 * resend SDP command with clear pipe bit (C) set
+		 */
+		{
+			volatile s32 *cmd;
+
+			int pipe = channel;
+			int td = dbri->pipes[pipe].desc;
+
+			dbri->dma->desc[td].word4 = 0;
+			cmd = dbri_cmdlock(dbri, NoGetLock);
+			*(cmd++) = DBRI_CMD(D_SDP, 0,
+					    dbri->pipes[pipe].sdp
+					    | D_SDP_P | D_SDP_C | D_SDP_2SAME);
+			*(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
+			dbri_cmdsend(dbri, cmd);
+		}
+		break;
+	case D_INTR_FXDT:
+		/* FXDT - Fixed data change */
+		if (dbri->pipes[channel].sdp & D_SDP_MSB)
+			val = reverse_bytes(val, dbri->pipes[channel].length);
+
+		if (dbri->pipes[channel].recv_fixed_ptr)
+			*(dbri->pipes[channel].recv_fixed_ptr) = val;
+		break;
+	default:
+		if (channel != D_INTR_CMD)
+			printk(KERN_WARNING
+			       "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
+	}
+}
+
+/* dbri_process_interrupt_buffer advances through the DBRI's interrupt
+ * buffer until it finds a zero word (indicating nothing more to do
+ * right now).  Non-zero words require processing and are handed off
+ * to dbri_process_one_interrupt AFTER advancing the pointer.  This
+ * order is important since we might recurse back into this function
+ * and need to make sure the pointer has been advanced first.
+ */
+static void dbri_process_interrupt_buffer(snd_dbri_t * dbri)
+{
+	s32 x;
+
+	while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
+		dbri->dma->intr[dbri->dbri_irqp] = 0;
+		dbri->dbri_irqp++;
+		if (dbri->dbri_irqp == (DBRI_NO_INTS * DBRI_INT_BLK))
+			dbri->dbri_irqp = 1;
+		else if ((dbri->dbri_irqp & (DBRI_INT_BLK - 1)) == 0)
+			dbri->dbri_irqp++;
+
+		dbri_process_one_interrupt(dbri, x);
+	}
+}
+
+static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id,
+				      struct pt_regs *regs)
+{
+	snd_dbri_t *dbri = dev_id;
+	static int errcnt = 0;
+	int x;
+
+	if (dbri == NULL)
+		return IRQ_NONE;
+	spin_lock(&dbri->lock);
+
+	/*
+	 * Read it, so the interrupt goes away.
+	 */
+	x = sbus_readl(dbri->regs + REG1);
+
+	if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
+		u32 tmp;
+
+		if (x & D_MRR)
+			printk(KERN_ERR
+			       "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
+			       x);
+		if (x & D_MLE)
+			printk(KERN_ERR
+			       "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
+			       x);
+		if (x & D_LBG)
+			printk(KERN_ERR
+			       "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
+		if (x & D_MBE)
+			printk(KERN_ERR
+			       "DBRI: Burst Error on SBus reg1=0x%x\n", x);
+
+		/* Some of these SBus errors cause the chip's SBus circuitry
+		 * to be disabled, so just re-enable and try to keep going.
+		 *
+		 * The only one I've seen is MRR, which will be triggered
+		 * if you let a transmit pipe underrun, then try to CDP it.
+		 *
+		 * If these things persist, we should probably reset
+		 * and re-init the chip.
+		 */
+		if ((++errcnt) % 10 == 0) {
+			dprintk(D_INT, "Interrupt errors exceeded.\n");
+			dbri_reset(dbri);
+		} else {
+			tmp = sbus_readl(dbri->regs + REG0);
+			tmp &= ~(D_D);
+			sbus_writel(tmp, dbri->regs + REG0);
+		}
+	}
+
+	dbri_process_interrupt_buffer(dbri);
+
+	/* FIXME: Write 0 into regs to ACK interrupt */
+
+	spin_unlock(&dbri->lock);
+
+	return IRQ_HANDLED;
+}
+
+/****************************************************************************
+		PCM Interface
+****************************************************************************/
+static snd_pcm_hardware_t snd_dbri_pcm_hw = {
+	.info			= (SNDRV_PCM_INFO_MMAP |
+				   SNDRV_PCM_INFO_INTERLEAVED |
+				   SNDRV_PCM_INFO_BLOCK_TRANSFER |
+				   SNDRV_PCM_INFO_MMAP_VALID),
+	.formats		= SNDRV_PCM_FMTBIT_MU_LAW |
+				  SNDRV_PCM_FMTBIT_A_LAW |
+				  SNDRV_PCM_FMTBIT_U8 |
+				  SNDRV_PCM_FMTBIT_S16_BE,
+	.rates			= SNDRV_PCM_RATE_8000_48000,
+	.rate_min		= 8000,
+	.rate_max		= 48000,
+	.channels_min		= 1,
+	.channels_max		= 2,
+	.buffer_bytes_max	= (64 * 1024),
+	.period_bytes_min	= 1,
+	.period_bytes_max	= DBRI_TD_MAXCNT,
+	.periods_min		= 1,
+	.periods_max		= 1024,
+};
+
+static int snd_dbri_open(snd_pcm_substream_t * substream)
+{
+	snd_dbri_t *dbri = snd_pcm_substream_chip(substream);
+	snd_pcm_runtime_t *runtime = substream->runtime;
+	dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream);
+	unsigned long flags;
+
+	dprintk(D_USR, "open audio output.\n");
+	runtime->hw = snd_dbri_pcm_hw;
+
+	spin_lock_irqsave(&dbri->lock, flags);
+	info->substream = substream;
+	info->left = 0;
+	info->offset = 0;
+	info->dvma_buffer = 0;
+	info->pipe = -1;
+	spin_unlock_irqrestore(&dbri->lock, flags);
+
+	cs4215_open(dbri);
+
+	return 0;
+}
+
+static int snd_dbri_close(snd_pcm_substream_t * substream)
+{
+	snd_dbri_t *dbri = snd_pcm_substream_chip(substream);
+	dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream);
+
+	dprintk(D_USR, "close audio output.\n");
+	info->substream = NULL;
+	info->left = 0;
+	info->offset = 0;
+
+	return 0;
+}
+
+static int snd_dbri_hw_params(snd_pcm_substream_t * substream,
+			      snd_pcm_hw_params_t * hw_params)
+{
+	snd_pcm_runtime_t *runtime = substream->runtime;
+	snd_dbri_t *dbri = snd_pcm_substream_chip(substream);
+	dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream);
+	int direction;
+	int ret;
+
+	/* set sampling rate, audio format and number of channels */
+	ret = cs4215_prepare(dbri, params_rate(hw_params),
+			     params_format(hw_params),
+			     params_channels(hw_params));
+	if (ret != 0)
+		return ret;
+
+	if ((ret = snd_pcm_lib_malloc_pages(substream,
+				params_buffer_bytes(hw_params))) < 0) {
+		snd_printk(KERN_ERR "malloc_pages failed with %d\n", ret);
+		return ret;
+	}
+
+	/* hw_params can get called multiple times. Only map the DMA once.
+	 */
+	if (info->dvma_buffer == 0) {
+		if (DBRI_STREAMNO(substream) == DBRI_PLAY)
+			direction = SBUS_DMA_TODEVICE;
+		else
+			direction = SBUS_DMA_FROMDEVICE;
+
+		info->dvma_buffer = sbus_map_single(dbri->sdev,
+					runtime->dma_area,
+					params_buffer_bytes(hw_params),
+					direction);
+	}
+
+	direction = params_buffer_bytes(hw_params);
+	dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
+		direction, info->dvma_buffer);
+	return 0;
+}
+
+static int snd_dbri_hw_free(snd_pcm_substream_t * substream)
+{
+	snd_dbri_t *dbri = snd_pcm_substream_chip(substream);
+	dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream);
+	int direction;
+	dprintk(D_USR, "hw_free.\n");
+
+	/* hw_free can get called multiple times. Only unmap the DMA once.
+	 */
+	if (info->dvma_buffer) {
+		if (DBRI_STREAMNO(substream) == DBRI_PLAY)
+			direction = SBUS_DMA_TODEVICE;
+		else
+			direction = SBUS_DMA_FROMDEVICE;
+
+		sbus_unmap_single(dbri->sdev, info->dvma_buffer,
+				  substream->runtime->buffer_size, direction);
+		info->dvma_buffer = 0;
+	}
+	info->pipe = -1;
+
+	return snd_pcm_lib_free_pages(substream);
+}
+
+static int snd_dbri_prepare(snd_pcm_substream_t * substream)
+{
+	snd_dbri_t *dbri = snd_pcm_substream_chip(substream);
+	dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream);
+	snd_pcm_runtime_t *runtime = substream->runtime;
+	int ret;
+
+	info->size = snd_pcm_lib_buffer_bytes(substream);
+	if (DBRI_STREAMNO(substream) == DBRI_PLAY)
+		info->pipe = 4;	/* Send pipe */
+	else {
+		info->pipe = 6;	/* Receive pipe */
+		info->left = info->size;	/* To trigger submittal */
+	}
+
+	spin_lock_irq(&dbri->lock);
+
+	/* Setup the all the transmit/receive desciptors to cover the
+	 * whole DMA buffer.
+	 */
+	ret = setup_descs(dbri, DBRI_STREAMNO(substream),
+			  snd_pcm_lib_period_bytes(substream));
+
+	runtime->stop_threshold = DBRI_TD_MAXCNT / runtime->channels;
+
+	spin_unlock_irq(&dbri->lock);
+
+	dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
+	return ret;
+}
+
+static int snd_dbri_trigger(snd_pcm_substream_t * substream, int cmd)
+{
+	snd_dbri_t *dbri = snd_pcm_substream_chip(substream);
+	dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream);
+	int ret = 0;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+		dprintk(D_USR, "start audio, period is %d bytes\n",
+			(int)snd_pcm_lib_period_bytes(substream));
+		/* Enable & schedule the tasklet that re-submits the TDs. */
+		xmit_descs_task.data = (unsigned long)dbri;
+		tasklet_schedule(&xmit_descs_task);
+		break;
+	case SNDRV_PCM_TRIGGER_STOP:
+		dprintk(D_USR, "stop audio.\n");
+		/* Make the tasklet bail out immediately. */
+		xmit_descs_task.data = 0;
+		reset_pipe(dbri, info->pipe);
+		break;
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static snd_pcm_uframes_t snd_dbri_pointer(snd_pcm_substream_t * substream)
+{
+	snd_dbri_t *dbri = snd_pcm_substream_chip(substream);
+	dbri_streaminfo_t *info = DBRI_STREAM(dbri, substream);
+	snd_pcm_uframes_t ret;
+
+	ret = bytes_to_frames(substream->runtime, info->offset)
+		% substream->runtime->buffer_size;
+	dprintk(D_USR, "I/O pointer: %ld frames, %d bytes left.\n",
+		ret, info->left);
+	return ret;
+}
+
+static snd_pcm_ops_t snd_dbri_ops = {
+	.open = snd_dbri_open,
+	.close = snd_dbri_close,
+	.ioctl = snd_pcm_lib_ioctl,
+	.hw_params = snd_dbri_hw_params,
+	.hw_free = snd_dbri_hw_free,
+	.prepare = snd_dbri_prepare,
+	.trigger = snd_dbri_trigger,
+	.pointer = snd_dbri_pointer,
+};
+
+static int __devinit snd_dbri_pcm(snd_dbri_t * dbri)
+{
+	snd_pcm_t *pcm;
+	int err;
+
+	if ((err = snd_pcm_new(dbri->card,
+			       /* ID */		    "sun_dbri",
+			       /* device */	    0,
+			       /* playback count */ 1,
+			       /* capture count */  1, &pcm)) < 0)
+		return err;
+	snd_assert(pcm != NULL, return -EINVAL);
+
+	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
+	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
+
+	pcm->private_data = dbri;
+	pcm->info_flags = 0;
+	strcpy(pcm->name, dbri->card->shortname);
+	dbri->pcm = pcm;
+
+	if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm,
+			SNDRV_DMA_TYPE_CONTINUOUS,
+			snd_dma_continuous_data(GFP_KERNEL),
+			64 * 1024, 64 * 1024)) < 0) {
+		return err;
+	}
+
+	return 0;
+}
+
+/*****************************************************************************
+			Mixer interface
+*****************************************************************************/
+
+static int snd_cs4215_info_volume(snd_kcontrol_t * kcontrol,
+				  snd_ctl_elem_info_t * uinfo)
+{
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+	uinfo->count = 2;
+	uinfo->value.integer.min = 0;
+	if (kcontrol->private_value == DBRI_PLAY) {
+		uinfo->value.integer.max = DBRI_MAX_VOLUME;
+	} else {
+		uinfo->value.integer.max = DBRI_MAX_GAIN;
+	}
+	return 0;
+}
+
+static int snd_cs4215_get_volume(snd_kcontrol_t * kcontrol,
+				 snd_ctl_elem_value_t * ucontrol)
+{
+	snd_dbri_t *dbri = snd_kcontrol_chip(kcontrol);
+	dbri_streaminfo_t *info;
+	snd_assert(dbri != NULL, return -EINVAL);
+	info = &dbri->stream_info[kcontrol->private_value];
+	snd_assert(info != NULL, return -EINVAL);
+
+	ucontrol->value.integer.value[0] = info->left_gain;
+	ucontrol->value.integer.value[1] = info->right_gain;
+	return 0;
+}
+
+static int snd_cs4215_put_volume(snd_kcontrol_t * kcontrol,
+				 snd_ctl_elem_value_t * ucontrol)
+{
+	snd_dbri_t *dbri = snd_kcontrol_chip(kcontrol);
+	dbri_streaminfo_t *info = &dbri->stream_info[kcontrol->private_value];
+	unsigned long flags;
+	int changed = 0;
+
+	if (info->left_gain != ucontrol->value.integer.value[0]) {
+		info->left_gain = ucontrol->value.integer.value[0];
+		changed = 1;
+	}
+	if (info->right_gain != ucontrol->value.integer.value[1]) {
+		info->right_gain = ucontrol->value.integer.value[1];
+		changed = 1;
+	}
+	if (changed == 1) {
+		/* First mute outputs, and wait 1/8000 sec (125 us)
+		 * to make sure this takes.  This avoids clicking noises.
+		 */
+		spin_lock_irqsave(&dbri->lock, flags);
+
+		cs4215_setdata(dbri, 1);
+		udelay(125);
+		cs4215_setdata(dbri, 0);
+
+		spin_unlock_irqrestore(&dbri->lock, flags);
+	}
+	return changed;
+}
+
+static int snd_cs4215_info_single(snd_kcontrol_t * kcontrol,
+				  snd_ctl_elem_info_t * uinfo)
+{
+	int mask = (kcontrol->private_value >> 16) & 0xff;
+
+	uinfo->type = (mask == 1) ?
+	    SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
+	uinfo->count = 1;
+	uinfo->value.integer.min = 0;
+	uinfo->value.integer.max = mask;
+	return 0;
+}
+
+static int snd_cs4215_get_single(snd_kcontrol_t * kcontrol,
+				 snd_ctl_elem_value_t * ucontrol)
+{
+	snd_dbri_t *dbri = snd_kcontrol_chip(kcontrol);
+	int elem = kcontrol->private_value & 0xff;
+	int shift = (kcontrol->private_value >> 8) & 0xff;
+	int mask = (kcontrol->private_value >> 16) & 0xff;
+	int invert = (kcontrol->private_value >> 24) & 1;
+	snd_assert(dbri != NULL, return -EINVAL);
+
+	if (elem < 4) {
+		ucontrol->value.integer.value[0] =
+		    (dbri->mm.data[elem] >> shift) & mask;
+	} else {
+		ucontrol->value.integer.value[0] =
+		    (dbri->mm.ctrl[elem - 4] >> shift) & mask;
+	}
+
+	if (invert == 1) {
+		ucontrol->value.integer.value[0] =
+		    mask - ucontrol->value.integer.value[0];
+	}
+	return 0;
+}
+
+static int snd_cs4215_put_single(snd_kcontrol_t * kcontrol,
+				 snd_ctl_elem_value_t * ucontrol)
+{
+	snd_dbri_t *dbri = snd_kcontrol_chip(kcontrol);
+	unsigned long flags;
+	int elem = kcontrol->private_value & 0xff;
+	int shift = (kcontrol->private_value >> 8) & 0xff;
+	int mask = (kcontrol->private_value >> 16) & 0xff;
+	int invert = (kcontrol->private_value >> 24) & 1;
+	int changed = 0;
+	unsigned short val;
+	snd_assert(dbri != NULL, return -EINVAL);
+
+	val = (ucontrol->value.integer.value[0] & mask);
+	if (invert == 1)
+		val = mask - val;
+	val <<= shift;
+
+	if (elem < 4) {
+		dbri->mm.data[elem] = (dbri->mm.data[elem] &
+				       ~(mask << shift)) | val;
+		changed = (val != dbri->mm.data[elem]);
+	} else {
+		dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
+					   ~(mask << shift)) | val;
+		changed = (val != dbri->mm.ctrl[elem - 4]);
+	}
+
+	dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
+		"mixer-value=%ld, mm-value=0x%x\n",
+		mask, changed, ucontrol->value.integer.value[0],
+		dbri->mm.data[elem & 3]);
+
+	if (changed) {
+		/* First mute outputs, and wait 1/8000 sec (125 us)
+		 * to make sure this takes.  This avoids clicking noises.
+		 */
+		spin_lock_irqsave(&dbri->lock, flags);
+
+		cs4215_setdata(dbri, 1);
+		udelay(125);
+		cs4215_setdata(dbri, 0);
+
+		spin_unlock_irqrestore(&dbri->lock, flags);
+	}
+	return changed;
+}
+
+/* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
+   timeslots. Shift is the bit offset in the timeslot, mask defines the
+   number of bits. invert is a boolean for use with attenuation.
+ */
+#define CS4215_SINGLE(xname, entry, shift, mask, invert) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+  .info = snd_cs4215_info_single, \
+  .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \
+  .private_value = entry | (shift << 8) | (mask << 16) | (invert << 24) },
+
+static snd_kcontrol_new_t dbri_controls[] __devinitdata = {
+	{
+	 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+	 .name  = "Playback Volume",
+	 .info  = snd_cs4215_info_volume,
+	 .get   = snd_cs4215_get_volume,
+	 .put   = snd_cs4215_put_volume,
+	 .private_value = DBRI_PLAY,
+	 },
+	CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
+	CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
+	CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
+	{
+	 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+	 .name  = "Capture Volume",
+	 .info  = snd_cs4215_info_volume,
+	 .get   = snd_cs4215_get_volume,
+	 .put   = snd_cs4215_put_volume,
+	 .private_value = DBRI_REC,
+	 },
+	/* FIXME: mic/line switch */
+	CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
+	CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
+	CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
+	CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
+};
+
+#define NUM_CS4215_CONTROLS (sizeof(dbri_controls)/sizeof(snd_kcontrol_new_t))
+
+static int __init snd_dbri_mixer(snd_dbri_t * dbri)
+{
+	snd_card_t *card;
+	int idx, err;
+
+	snd_assert(dbri != NULL && dbri->card != NULL, return -EINVAL);
+
+	card = dbri->card;
+	strcpy(card->mixername, card->shortname);
+
+	for (idx = 0; idx < NUM_CS4215_CONTROLS; idx++) {
+		if ((err = snd_ctl_add(card,
+				       snd_ctl_new1(&dbri_controls[idx],
+						    dbri))) < 0)
+			return err;
+	}
+
+	for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
+		dbri->stream_info[idx].left_gain = 0;
+		dbri->stream_info[idx].right_gain = 0;
+		dbri->stream_info[idx].balance = DBRI_MID_BALANCE;
+	}
+
+	return 0;
+}
+
+/****************************************************************************
+			/proc interface
+****************************************************************************/
+static void dbri_regs_read(snd_info_entry_t * entry, snd_info_buffer_t * buffer)
+{
+	snd_dbri_t *dbri = entry->private_data;
+
+	snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
+	snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
+	snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
+	snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
+}
+
+#ifdef DBRI_DEBUG
+static void dbri_debug_read(snd_info_entry_t * entry,
+			    snd_info_buffer_t * buffer)
+{
+	snd_dbri_t *dbri = entry->private_data;
+	int pipe;
+	snd_iprintf(buffer, "debug=%d\n", dbri_debug);
+
+	snd_iprintf(buffer, "CHI pipe in=%d, out=%d\n",
+		    dbri->chi_in_pipe, dbri->chi_out_pipe);
+	for (pipe = 0; pipe < 32; pipe++) {
+		if (pipe_active(dbri, pipe)) {
+			struct dbri_pipe *pptr = &dbri->pipes[pipe];
+			snd_iprintf(buffer,
+				    "Pipe %d: %s SDP=0x%x desc=%d, "
+				    "len=%d @ %d prev: %d next %d\n",
+				    pipe,
+				    (pptr->direction ==
+				     PIPEinput ? "input" : "output"), pptr->sdp,
+				    pptr->desc, pptr->length, pptr->cycle,
+				    pptr->prevpipe, pptr->nextpipe);
+		}
+	}
+}
+
+static void dbri_debug_write(snd_info_entry_t * entry,
+			     snd_info_buffer_t * buffer)
+{
+	char line[80];
+	int i;
+
+	if (snd_info_get_line(buffer, line, 80) == 0) {
+		sscanf(line, "%d\n", &i);
+		dbri_debug = i & 0x3f;
+	}
+}
+#endif
+
+void snd_dbri_proc(snd_dbri_t * dbri)
+{
+	snd_info_entry_t *entry;
+	int err;
+
+	err = snd_card_proc_new(dbri->card, "regs", &entry);
+	snd_info_set_text_ops(entry, dbri, 1024, dbri_regs_read);
+
+#ifdef DBRI_DEBUG
+	err = snd_card_proc_new(dbri->card, "debug", &entry);
+	snd_info_set_text_ops(entry, dbri, 4096, dbri_debug_read);
+	entry->mode = S_IFREG | S_IRUGO | S_IWUSR; /* Writable for root */
+	entry->c.text.write_size = 256;
+	entry->c.text.write = dbri_debug_write;
+#endif
+}
+
+/*
+****************************************************************************
+**************************** Initialization ********************************
+****************************************************************************
+*/
+static void snd_dbri_free(snd_dbri_t * dbri);
+
+static int __init snd_dbri_create(snd_card_t * card,
+				  struct sbus_dev *sdev,
+				  struct linux_prom_irqs *irq, int dev)
+{
+	snd_dbri_t *dbri = card->private_data;
+	int err;
+
+	spin_lock_init(&dbri->lock);
+	dbri->card = card;
+	dbri->sdev = sdev;
+	dbri->irq = irq->pri;
+	dbri->dbri_version = sdev->prom_name[9];
+
+	dbri->dma = sbus_alloc_consistent(sdev, sizeof(struct dbri_dma),
+					  &dbri->dma_dvma);
+	memset((void *)dbri->dma, 0, sizeof(struct dbri_dma));
+
+	dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n",
+		dbri->dma, dbri->dma_dvma);
+
+	/* Map the registers into memory. */
+	dbri->regs_size = sdev->reg_addrs[0].reg_size;
+	dbri->regs = sbus_ioremap(&sdev->resource[0], 0,
+				  dbri->regs_size, "DBRI Registers");
+	if (!dbri->regs) {
+		printk(KERN_ERR "DBRI: could not allocate registers\n");
+		sbus_free_consistent(sdev, sizeof(struct dbri_dma),
+				     (void *)dbri->dma, dbri->dma_dvma);
+		return -EIO;
+	}
+
+	err = request_irq(dbri->irq, snd_dbri_interrupt, SA_SHIRQ,
+			  "DBRI audio", dbri);
+	if (err) {
+		printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
+		sbus_iounmap(dbri->regs, dbri->regs_size);
+		sbus_free_consistent(sdev, sizeof(struct dbri_dma),
+				     (void *)dbri->dma, dbri->dma_dvma);
+		return err;
+	}
+
+	/* Do low level initialization of the DBRI and CS4215 chips */
+	dbri_initialize(dbri);
+	err = cs4215_init(dbri);
+	if (err) {
+		snd_dbri_free(dbri);
+		return err;
+	}
+
+	dbri->next = dbri_list;
+	dbri_list = dbri;
+
+	return 0;
+}
+
+static void snd_dbri_free(snd_dbri_t * dbri)
+{
+	dprintk(D_GEN, "snd_dbri_free\n");
+	dbri_reset(dbri);
+
+	if (dbri->irq)
+		free_irq(dbri->irq, dbri);
+
+	if (dbri->regs)
+		sbus_iounmap(dbri->regs, dbri->regs_size);
+
+	if (dbri->dma)
+		sbus_free_consistent(dbri->sdev, sizeof(struct dbri_dma),
+				     (void *)dbri->dma, dbri->dma_dvma);
+}
+
+static int __init dbri_attach(int prom_node, struct sbus_dev *sdev)
+{
+	snd_dbri_t *dbri;
+	struct linux_prom_irqs irq;
+	struct resource *rp;
+	snd_card_t *card;
+	static int dev = 0;
+	int err;
+
+	if (sdev->prom_name[9] < 'e') {
+		printk(KERN_ERR "DBRI: unsupported chip version %c found.\n",
+		       sdev->prom_name[9]);
+		return -EIO;
+	}
+
+	if (dev >= SNDRV_CARDS)
+		return -ENODEV;
+	if (!enable[dev]) {
+		dev++;
+		return -ENOENT;
+	}
+
+	prom_getproperty(prom_node, "intr", (char *)&irq, sizeof(irq));
+
+	card = snd_card_new(index[dev], id[dev], THIS_MODULE,
+			    sizeof(snd_dbri_t));
+	if (card == NULL)
+		return -ENOMEM;
+
+	strcpy(card->driver, "DBRI");
+	strcpy(card->shortname, "Sun DBRI");
+	rp = &sdev->resource[0];
+	sprintf(card->longname, "%s at 0x%02lx:0x%08lx, irq %s",
+		card->shortname,
+		rp->flags & 0xffL, rp->start, __irq_itoa(irq.pri));
+
+	if ((err = snd_dbri_create(card, sdev, &irq, dev)) < 0) {
+		snd_card_free(card);
+		return err;
+	}
+
+	dbri = (snd_dbri_t *) card->private_data;
+	if ((err = snd_dbri_pcm(dbri)) < 0) {
+		snd_dbri_free(dbri);
+		snd_card_free(card);
+		return err;
+	}
+
+	if ((err = snd_dbri_mixer(dbri)) < 0) {
+		snd_dbri_free(dbri);
+		snd_card_free(card);
+		return err;
+	}
+
+	/* /proc file handling */
+	snd_dbri_proc(dbri);
+
+	if ((err = snd_card_register(card)) < 0) {
+		snd_dbri_free(dbri);
+		snd_card_free(card);
+		return err;
+	}
+
+	printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
+	       dev, dbri->regs,
+	       dbri->irq, dbri->dbri_version, dbri->mm.version);
+	dev++;
+
+	return 0;
+}
+
+/* Probe for the dbri chip and then attach the driver. */
+static int __init dbri_init(void)
+{
+	struct sbus_bus *sbus;
+	struct sbus_dev *sdev;
+	int found = 0;
+
+	/* Probe each SBUS for the DBRI chip(s). */
+	for_all_sbusdev(sdev, sbus) {
+		/*
+		 * The version is coded in the last character
+		 */
+		if (!strncmp(sdev->prom_name, "SUNW,DBRI", 9)) {
+			dprintk(D_GEN, "DBRI: Found %s in SBUS slot %d\n",
+				sdev->prom_name, sdev->slot);
+
+			if (dbri_attach(sdev->prom_node, sdev) == 0)
+				found++;
+		}
+	}
+
+	return (found > 0) ? 0 : -EIO;
+}
+
+static void __exit dbri_exit(void)
+{
+	snd_dbri_t *this = dbri_list;
+
+	while (this != NULL) {
+		snd_dbri_t *next = this->next;
+		snd_card_t *card = this->card;
+
+		snd_dbri_free(this);
+		snd_card_free(card);
+		this = next;
+	}
+	dbri_list = NULL;
+}
+
+module_init(dbri_init);
+module_exit(dbri_exit);
diff --git a/sound/usb/usbaudio.c b/sound/usb/usbaudio.c
index a75695045f2..8298c462c29 100644
--- a/sound/usb/usbaudio.c
+++ b/sound/usb/usbaudio.c
@@ -153,6 +153,7 @@ struct snd_usb_substream {
 	unsigned int format;     /* USB data format */
 	unsigned int datapipe;   /* the data i/o pipe */
 	unsigned int syncpipe;   /* 1 - async out or adaptive in */
+	unsigned int datainterval;	/* log_2 of data packet interval */
 	unsigned int syncinterval;  /* P for adaptive mode, 0 otherwise */
 	unsigned int freqn;      /* nominal sampling rate in fs/fps in Q16.16 format */
 	unsigned int freqm;      /* momentary sampling rate in fs/fps in Q16.16 format */
@@ -212,7 +213,7 @@ static snd_usb_audio_t *usb_chip[SNDRV_CARDS];
  * convert a sampling rate into our full speed format (fs/1000 in Q16.16)
  * this will overflow at approx 524 kHz
  */
-inline static unsigned get_usb_full_speed_rate(unsigned int rate)
+static inline unsigned get_usb_full_speed_rate(unsigned int rate)
 {
 	return ((rate << 13) + 62) / 125;
 }
@@ -221,19 +222,19 @@ inline static unsigned get_usb_full_speed_rate(unsigned int rate)
  * convert a sampling rate into USB high speed format (fs/8000 in Q16.16)
  * this will overflow at approx 4 MHz
  */
-inline static unsigned get_usb_high_speed_rate(unsigned int rate)
+static inline unsigned get_usb_high_speed_rate(unsigned int rate)
 {
 	return ((rate << 10) + 62) / 125;
 }
 
 /* convert our full speed USB rate into sampling rate in Hz */
-inline static unsigned get_full_speed_hz(unsigned int usb_rate)
+static inline unsigned get_full_speed_hz(unsigned int usb_rate)
 {
 	return (usb_rate * 125 + (1 << 12)) >> 13;
 }
 
 /* convert our high speed USB rate into sampling rate in Hz */
-inline static unsigned get_high_speed_hz(unsigned int usb_rate)
+static inline unsigned get_high_speed_hz(unsigned int usb_rate)
 {
 	return (usb_rate * 125 + (1 << 9)) >> 10;
 }
@@ -518,7 +519,8 @@ static int prepare_playback_urb(snd_usb_substream_t *subs,
 		if (subs->fill_max)
 			counts = subs->maxframesize; /* fixed */
 		else {
-			subs->phase = (subs->phase & 0xffff) + subs->freqm;
+			subs->phase = (subs->phase & 0xffff)
+				+ (subs->freqm << subs->datainterval);
 			counts = subs->phase >> 16;
 			if (counts > subs->maxframesize)
 				counts = subs->maxframesize;
@@ -790,7 +792,7 @@ static int start_urbs(snd_usb_substream_t *subs, snd_pcm_runtime_t *runtime)
  */
 static int wait_clear_urbs(snd_usb_substream_t *subs)
 {
-	int timeout = HZ;
+	unsigned long end_time = jiffies + msecs_to_jiffies(1000);
 	unsigned int i;
 	int alive;
 
@@ -810,7 +812,7 @@ static int wait_clear_urbs(snd_usb_substream_t *subs)
 			break;
 		set_current_state(TASK_UNINTERRUPTIBLE);
 		schedule_timeout(1);
-	} while (--timeout > 0);
+	} while (time_before(jiffies, end_time));
 	if (alive)
 		snd_printk(KERN_ERR "timeout: still %d active urbs..\n", alive);
 	return 0;
@@ -899,16 +901,19 @@ static int init_substream_urbs(snd_usb_substream_t *subs, unsigned int period_by
 	else
 		subs->freqn = get_usb_high_speed_rate(rate);
 	subs->freqm = subs->freqn;
-	subs->freqmax = subs->freqn + (subs->freqn >> 2); /* max. allowed frequency */
-	subs->phase = 0;
-
-	/* calculate the max. size of packet */
-	maxsize = ((subs->freqmax + 0xffff) * (frame_bits >> 3)) >> 16;
-	if (subs->maxpacksize && maxsize > subs->maxpacksize) {
-		//snd_printd(KERN_DEBUG "maxsize %d is greater than defined size %d\n",
-		//	   maxsize, subs->maxpacksize);
+	/* calculate max. frequency */
+	if (subs->maxpacksize) {
+		/* whatever fits into a max. size packet */
 		maxsize = subs->maxpacksize;
+		subs->freqmax = (maxsize / (frame_bits >> 3))
+				<< (16 - subs->datainterval);
+	} else {
+		/* no max. packet size: just take 25% higher than nominal */
+		subs->freqmax = subs->freqn + (subs->freqn >> 2);
+		maxsize = ((subs->freqmax + 0xffff) * (frame_bits >> 3))
+				>> (16 - subs->datainterval);
 	}
+	subs->phase = 0;
 
 	if (subs->fill_max)
 		subs->curpacksize = subs->maxpacksize;
@@ -918,7 +923,7 @@ static int init_substream_urbs(snd_usb_substream_t *subs, unsigned int period_by
 	if (snd_usb_get_speed(subs->dev) == USB_SPEED_FULL)
 		urb_packs = nrpacks;
 	else
-		urb_packs = nrpacks * 8;
+		urb_packs = (nrpacks * 8) >> subs->datainterval;
 
 	/* allocate a temporary buffer for playback */
 	if (is_playback) {
@@ -991,7 +996,7 @@ static int init_substream_urbs(snd_usb_substream_t *subs, unsigned int period_by
 		u->urb->pipe = subs->datapipe;
 		u->urb->transfer_flags = URB_ISO_ASAP;
 		u->urb->number_of_packets = u->packets;
-		u->urb->interval = 1;
+		u->urb->interval = 1 << subs->datainterval;
 		u->urb->context = u;
 		u->urb->complete = snd_usb_complete_callback(snd_complete_urb);
 	}
@@ -1195,6 +1200,12 @@ static int set_format(snd_usb_substream_t *subs, struct audioformat *fmt)
 		subs->datapipe = usb_sndisocpipe(dev, ep);
 	else
 		subs->datapipe = usb_rcvisocpipe(dev, ep);
+	if (snd_usb_get_speed(subs->dev) == USB_SPEED_HIGH &&
+	    get_endpoint(alts, 0)->bInterval >= 1 &&
+	    get_endpoint(alts, 0)->bInterval <= 4)
+		subs->datainterval = get_endpoint(alts, 0)->bInterval - 1;
+	else
+		subs->datainterval = 0;
 	subs->syncpipe = subs->syncinterval = 0;
 	subs->maxpacksize = fmt->maxpacksize;
 	subs->fill_max = 0;
@@ -2397,10 +2408,9 @@ static int parse_audio_format(snd_usb_audio_t *chip, struct audioformat *fp,
 	if (chip->usb_id == USB_ID(0x041e, 0x3000) ||
 	    chip->usb_id == USB_ID(0x041e, 0x3020)) {
 		if (fmt[3] == USB_FORMAT_TYPE_I &&
-		    stream == SNDRV_PCM_STREAM_PLAYBACK &&
 		    fp->rates != SNDRV_PCM_RATE_48000 &&
 		    fp->rates != SNDRV_PCM_RATE_96000)
-			return -1; /* use 48k only */
+			return -1;
 	}
 #endif
 	return 0;
@@ -2492,8 +2502,10 @@ static int parse_audio_endpoints(snd_usb_audio_t *chip, int iface_no)
 		fp->altset_idx = i;
 		fp->endpoint = get_endpoint(alts, 0)->bEndpointAddress;
 		fp->ep_attr = get_endpoint(alts, 0)->bmAttributes;
-		/* FIXME: decode wMaxPacketSize of high bandwith endpoints */
 		fp->maxpacksize = le16_to_cpu(get_endpoint(alts, 0)->wMaxPacketSize);
+		if (snd_usb_get_speed(dev) == USB_SPEED_HIGH)
+			fp->maxpacksize = (((fp->maxpacksize >> 11) & 3) + 1)
+					* (fp->maxpacksize & 0x7ff);
 		fp->attributes = csep[3];
 
 		/* some quirks for attributes here */
@@ -2723,7 +2735,8 @@ static int create_standard_interface_quirk(snd_usb_audio_t *chip,
  * to detect the sample rate is by looking at wMaxPacketSize.
  */
 static int create_ua700_ua25_quirk(snd_usb_audio_t *chip,
-				   struct usb_interface *iface)
+				   struct usb_interface *iface,
+				   const snd_usb_audio_quirk_t *quirk)
 {
 	static const struct audioformat ua_format = {
 		.format = SNDRV_PCM_FORMAT_S24_3LE,
@@ -2814,7 +2827,9 @@ static int create_ua700_ua25_quirk(snd_usb_audio_t *chip,
 /*
  * Create a stream for an Edirol UA-1000 interface.
  */
-static int create_ua1000_quirk(snd_usb_audio_t *chip, struct usb_interface *iface)
+static int create_ua1000_quirk(snd_usb_audio_t *chip,
+			       struct usb_interface *iface,
+			       const snd_usb_audio_quirk_t *quirk)
 {
 	static const struct audioformat ua1000_format = {
 		.format = SNDRV_PCM_FORMAT_S32_LE,
@@ -2891,6 +2906,13 @@ static int create_composite_quirk(snd_usb_audio_t *chip,
 	return 0;
 }
 
+static int ignore_interface_quirk(snd_usb_audio_t *chip,
+				  struct usb_interface *iface,
+				  const snd_usb_audio_quirk_t *quirk)
+{
+	return 0;
+}
+
 
 /*
  * boot quirks
@@ -2926,8 +2948,6 @@ static int snd_usb_extigy_boot_quirk(struct usb_device *dev, struct usb_interfac
 
 static int snd_usb_audigy2nx_boot_quirk(struct usb_device *dev)
 {
-#if 0
-	/* TODO: enable this when high speed synchronization actually works */
 	u8 buf = 1;
 
 	snd_usb_ctl_msg(dev, usb_rcvctrlpipe(dev, 0), 0x2a,
@@ -2939,7 +2959,6 @@ static int snd_usb_audigy2nx_boot_quirk(struct usb_device *dev)
 				1, 2000, NULL, 0, 1000);
 		return -ENODEV;
 	}
-#endif
 	return 0;
 }
 
@@ -2956,28 +2975,28 @@ static int snd_usb_create_quirk(snd_usb_audio_t *chip,
 				struct usb_interface *iface,
 				const snd_usb_audio_quirk_t *quirk)
 {
-	switch (quirk->type) {
-	case QUIRK_MIDI_FIXED_ENDPOINT:
-	case QUIRK_MIDI_YAMAHA:
-	case QUIRK_MIDI_MIDIMAN:
-	case QUIRK_MIDI_NOVATION:
-	case QUIRK_MIDI_MOTU:
-	case QUIRK_MIDI_EMAGIC:
-		return snd_usb_create_midi_interface(chip, iface, quirk);
-	case QUIRK_COMPOSITE:
-		return create_composite_quirk(chip, iface, quirk);
-	case QUIRK_AUDIO_FIXED_ENDPOINT:
-		return create_fixed_stream_quirk(chip, iface, quirk);
-	case QUIRK_AUDIO_STANDARD_INTERFACE:
-	case QUIRK_MIDI_STANDARD_INTERFACE:
-		return create_standard_interface_quirk(chip, iface, quirk);
-	case QUIRK_AUDIO_EDIROL_UA700_UA25:
-		return create_ua700_ua25_quirk(chip, iface);
-	case QUIRK_AUDIO_EDIROL_UA1000:
-		return create_ua1000_quirk(chip, iface);
-	case QUIRK_IGNORE_INTERFACE:
-		return 0;
-	default:
+	typedef int (*quirk_func_t)(snd_usb_audio_t *, struct usb_interface *,
+				    const snd_usb_audio_quirk_t *);
+	static const quirk_func_t quirk_funcs[] = {
+		[QUIRK_IGNORE_INTERFACE] = ignore_interface_quirk,
+		[QUIRK_COMPOSITE] = create_composite_quirk,
+		[QUIRK_MIDI_STANDARD_INTERFACE] = snd_usb_create_midi_interface,
+		[QUIRK_MIDI_FIXED_ENDPOINT] = snd_usb_create_midi_interface,
+		[QUIRK_MIDI_YAMAHA] = snd_usb_create_midi_interface,
+		[QUIRK_MIDI_MIDIMAN] = snd_usb_create_midi_interface,
+		[QUIRK_MIDI_NOVATION] = snd_usb_create_midi_interface,
+		[QUIRK_MIDI_RAW] = snd_usb_create_midi_interface,
+		[QUIRK_MIDI_EMAGIC] = snd_usb_create_midi_interface,
+		[QUIRK_MIDI_MIDITECH] = snd_usb_create_midi_interface,
+		[QUIRK_AUDIO_STANDARD_INTERFACE] = create_standard_interface_quirk,
+		[QUIRK_AUDIO_FIXED_ENDPOINT] = create_fixed_stream_quirk,
+		[QUIRK_AUDIO_EDIROL_UA700_UA25] = create_ua700_ua25_quirk,
+		[QUIRK_AUDIO_EDIROL_UA1000] = create_ua1000_quirk,
+	};
+
+	if (quirk->type < QUIRK_TYPE_COUNT) {
+		return quirk_funcs[quirk->type](chip, iface, quirk);
+	} else {
 		snd_printd(KERN_ERR "invalid quirk type %d\n", quirk->type);
 		return -ENXIO;
 	}
diff --git a/sound/usb/usbaudio.h b/sound/usb/usbaudio.h
index aedb42aaa74..ad9eab211d8 100644
--- a/sound/usb/usbaudio.h
+++ b/sound/usb/usbaudio.h
@@ -153,20 +153,24 @@ struct snd_usb_audio {
 #define QUIRK_NO_INTERFACE		-2
 #define QUIRK_ANY_INTERFACE		-1
 
-/* quirk type */
-#define QUIRK_MIDI_FIXED_ENDPOINT	0
-#define QUIRK_MIDI_YAMAHA		1
-#define QUIRK_MIDI_MIDIMAN		2
-#define QUIRK_COMPOSITE			3
-#define QUIRK_AUDIO_FIXED_ENDPOINT	4
-#define QUIRK_AUDIO_STANDARD_INTERFACE	5
-#define QUIRK_MIDI_STANDARD_INTERFACE	6
-#define QUIRK_AUDIO_EDIROL_UA700_UA25	7
-#define QUIRK_AUDIO_EDIROL_UA1000	8
-#define QUIRK_IGNORE_INTERFACE		9
-#define QUIRK_MIDI_NOVATION		10
-#define QUIRK_MIDI_MOTU			11
-#define QUIRK_MIDI_EMAGIC		12
+enum quirk_type {
+	QUIRK_IGNORE_INTERFACE,
+	QUIRK_COMPOSITE,
+	QUIRK_MIDI_STANDARD_INTERFACE,
+	QUIRK_MIDI_FIXED_ENDPOINT,
+	QUIRK_MIDI_YAMAHA,
+	QUIRK_MIDI_MIDIMAN,
+	QUIRK_MIDI_NOVATION,
+	QUIRK_MIDI_RAW,
+	QUIRK_MIDI_EMAGIC,
+	QUIRK_MIDI_MIDITECH,
+	QUIRK_AUDIO_STANDARD_INTERFACE,
+	QUIRK_AUDIO_FIXED_ENDPOINT,
+	QUIRK_AUDIO_EDIROL_UA700_UA25,
+	QUIRK_AUDIO_EDIROL_UA1000,
+
+	QUIRK_TYPE_COUNT
+};
 
 typedef struct snd_usb_audio_quirk snd_usb_audio_quirk_t;
 typedef struct snd_usb_midi_endpoint_info snd_usb_midi_endpoint_info_t;
@@ -175,7 +179,7 @@ struct snd_usb_audio_quirk {
 	const char *vendor_name;
 	const char *product_name;
 	int16_t ifnum;
-	int16_t type;
+	uint16_t type;
 	const void *data;
 };
 
@@ -205,11 +209,13 @@ struct snd_usb_midi_endpoint_info {
 
 /* for QUIRK_IGNORE_INTERFACE, data is NULL */
 
-/* for QUIRK_MIDI_NOVATION and _MOTU, data is NULL */
+/* for QUIRK_MIDI_NOVATION and _RAW, data is NULL */
 
 /* for QUIRK_MIDI_EMAGIC, data points to a snd_usb_midi_endpoint_info
  * structure (out_cables and in_cables only) */
 
+/* for QUIRK_MIDI_MIDITECH, data is NULL */
+
 /*
  */
 
diff --git a/sound/usb/usbmidi.c b/sound/usb/usbmidi.c
index bee70068dce..5778a9b725e 100644
--- a/sound/usb/usbmidi.c
+++ b/sound/usb/usbmidi.c
@@ -524,16 +524,16 @@ static struct usb_protocol_ops snd_usbmidi_novation_ops = {
 };
 
 /*
- * Mark of the Unicorn USB MIDI protocol: raw MIDI.
+ * "raw" protocol: used by the MOTU FastLane.
  */
 
-static void snd_usbmidi_motu_input(snd_usb_midi_in_endpoint_t* ep,
-				   uint8_t* buffer, int buffer_length)
+static void snd_usbmidi_raw_input(snd_usb_midi_in_endpoint_t* ep,
+				  uint8_t* buffer, int buffer_length)
 {
 	snd_usbmidi_input_data(ep, 0, buffer, buffer_length);
 }
 
-static void snd_usbmidi_motu_output(snd_usb_midi_out_endpoint_t* ep)
+static void snd_usbmidi_raw_output(snd_usb_midi_out_endpoint_t* ep)
 {
 	int count;
 
@@ -549,9 +549,9 @@ static void snd_usbmidi_motu_output(snd_usb_midi_out_endpoint_t* ep)
 	ep->urb->transfer_buffer_length = count;
 }
 
-static struct usb_protocol_ops snd_usbmidi_motu_ops = {
-	.input = snd_usbmidi_motu_input,
-	.output = snd_usbmidi_motu_output,
+static struct usb_protocol_ops snd_usbmidi_raw_ops = {
+	.input = snd_usbmidi_raw_input,
+	.output = snd_usbmidi_raw_output,
 };
 
 /*
@@ -1505,8 +1505,8 @@ int snd_usb_create_midi_interface(snd_usb_audio_t* chip,
 			umidi->usb_protocol_ops = &snd_usbmidi_novation_ops;
 			err = snd_usbmidi_detect_per_port_endpoints(umidi, endpoints);
 			break;
-		case QUIRK_MIDI_MOTU:
-			umidi->usb_protocol_ops = &snd_usbmidi_motu_ops;
+		case QUIRK_MIDI_RAW:
+			umidi->usb_protocol_ops = &snd_usbmidi_raw_ops;
 			err = snd_usbmidi_detect_per_port_endpoints(umidi, endpoints);
 			break;
 		case QUIRK_MIDI_EMAGIC:
@@ -1515,6 +1515,9 @@ int snd_usb_create_midi_interface(snd_usb_audio_t* chip,
 			       sizeof(snd_usb_midi_endpoint_info_t));
 			err = snd_usbmidi_detect_endpoints(umidi, &endpoints[0], 1);
 			break;
+		case QUIRK_MIDI_MIDITECH:
+			err = snd_usbmidi_detect_per_port_endpoints(umidi, endpoints);
+			break;
 		default:
 			snd_printd(KERN_ERR "invalid quirk type %d\n", quirk->type);
 			err = -ENXIO;
diff --git a/sound/usb/usbmixer.c b/sound/usb/usbmixer.c
index e73c1c9d3e7..fa7056f5caa 100644
--- a/sound/usb/usbmixer.c
+++ b/sound/usb/usbmixer.c
@@ -363,7 +363,7 @@ static int get_cur_ctl_value(usb_mixer_elem_info_t *cval, int validx, int *value
 }
 
 /* channel = 0: master, 1 = first channel */
-inline static int get_cur_mix_value(usb_mixer_elem_info_t *cval, int channel, int *value)
+static inline int get_cur_mix_value(usb_mixer_elem_info_t *cval, int channel, int *value)
 {
 	return get_ctl_value(cval, GET_CUR, (cval->control << 8) | channel, value);
 }
@@ -399,7 +399,7 @@ static int set_cur_ctl_value(usb_mixer_elem_info_t *cval, int validx, int value)
 	return set_ctl_value(cval, SET_CUR, validx, value);
 }
 
-inline static int set_cur_mix_value(usb_mixer_elem_info_t *cval, int channel, int value)
+static inline int set_cur_mix_value(usb_mixer_elem_info_t *cval, int channel, int value)
 {
 	return set_ctl_value(cval, SET_CUR, (cval->control << 8) | channel, value);
 }
diff --git a/sound/usb/usbquirks.h b/sound/usb/usbquirks.h
index f5135641b3e..f74e652a1e5 100644
--- a/sound/usb/usbquirks.h
+++ b/sound/usb/usbquirks.h
@@ -116,6 +116,7 @@ YAMAHA_DEVICE(0x1039, NULL),
 YAMAHA_DEVICE(0x103a, NULL),
 YAMAHA_DEVICE(0x103b, NULL),
 YAMAHA_DEVICE(0x103c, NULL),
+YAMAHA_DEVICE(0x103d, NULL),
 YAMAHA_DEVICE(0x2000, "DGP-7"),
 YAMAHA_DEVICE(0x2001, "DGP-5"),
 YAMAHA_DEVICE(0x2002, NULL),
@@ -1259,7 +1260,12 @@ YAMAHA_DEVICE(0x7010, "UB99"),
 /* Mark of the Unicorn devices */
 {
 	/* thanks to Robert A. Lerche <ral 'at' msbit.com> */
-	USB_DEVICE(0x07fd, 0x0001),
+	.match_flags = USB_DEVICE_ID_MATCH_VENDOR |
+		       USB_DEVICE_ID_MATCH_PRODUCT |
+		       USB_DEVICE_ID_MATCH_DEV_SUBCLASS,
+	.idVendor = 0x07fd,
+	.idProduct = 0x0001,
+	.bDeviceSubClass = 2,
 	.driver_info = (unsigned long) & (const snd_usb_audio_quirk_t) {
 		.vendor_name = "MOTU",
 		.product_name = "Fastlane",
@@ -1268,7 +1274,7 @@ YAMAHA_DEVICE(0x7010, "UB99"),
 		.data = & (const snd_usb_audio_quirk_t[]) {
 			{
 				.ifnum = 0,
-				.type = QUIRK_MIDI_MOTU
+				.type = QUIRK_MIDI_RAW
 			},
 			{
 				.ifnum = 1,
@@ -1373,6 +1379,25 @@ YAMAHA_DEVICE(0x7010, "UB99"),
 },
 
 {
+	USB_DEVICE(0x4752, 0x0011),
+	.driver_info = (unsigned long) & (const snd_usb_audio_quirk_t) {
+		.vendor_name = "Miditech",
+		.product_name = "Midistart-2",
+		.ifnum = 0,
+		.type = QUIRK_MIDI_MIDITECH
+	}
+},
+{
+	USB_DEVICE(0x7104, 0x2202),
+	.driver_info = (unsigned long) & (const snd_usb_audio_quirk_t) {
+		.vendor_name = "Miditech",
+		.product_name = "MidiStudio-2",
+		.ifnum = 0,
+		.type = QUIRK_MIDI_MIDITECH
+	}
+},
+
+{
 	/*
 	 * Some USB MIDI devices don't have an audio control interface,
 	 * so we have to grab MIDI streaming interfaces here.
diff --git a/sound/usb/usx2y/usX2Yhwdep.c b/sound/usb/usx2y/usX2Yhwdep.c
index bef9b0c142c..0281a362857 100644
--- a/sound/usb/usx2y/usX2Yhwdep.c
+++ b/sound/usb/usx2y/usX2Yhwdep.c
@@ -232,8 +232,7 @@ static int snd_usX2Y_hwdep_dsp_load(snd_hwdep_t *hw, snd_hwdep_dsp_image_t *dsp)
 	if (err)
 		return err;
 	if (dsp->index == 1) {
-		set_current_state(TASK_UNINTERRUPTIBLE);
-		schedule_timeout(HZ/4);			// give the device some time 
+		msleep(250);				// give the device some time
 		err = usX2Y_AsyncSeq04_init(priv);
 		if (err) {
 			snd_printk("usX2Y_AsyncSeq04_init error \n");
diff --git a/sound/usb/usx2y/usx2yhwdeppcm.c b/sound/usb/usx2y/usx2yhwdeppcm.c
index bb2c8e9000c..ef28061287f 100644
--- a/sound/usb/usx2y/usx2yhwdeppcm.c
+++ b/sound/usb/usx2y/usx2yhwdeppcm.c
@@ -50,6 +50,7 @@
    Currently rawusb dma pcm buffer transport (this file) is only available to snd-usb-usx2y. 
 */
 
+#include <linux/delay.h>
 #include "usbusx2yaudio.c"
 
 #if defined(USX2Y_NRPACKS_VARIABLE) || (!defined(USX2Y_NRPACKS_VARIABLE) &&  USX2Y_NRPACKS == 1)
@@ -520,11 +521,8 @@ static int snd_usX2Y_usbpcm_prepare(snd_pcm_substream_t *substream)
 		usX2Y->hwdep_pcm_shm->playback_iso_start = -1;
 		if (atomic_read(&subs->state) < state_PREPARED) {
 			while (usX2Y_iso_frames_per_buffer(runtime, usX2Y) > usX2Y->hwdep_pcm_shm->captured_iso_frames) {
-				signed long timeout;
 				snd_printd("Wait: iso_frames_per_buffer=%i,captured_iso_frames=%i\n", usX2Y_iso_frames_per_buffer(runtime, usX2Y), usX2Y->hwdep_pcm_shm->captured_iso_frames);
-				set_current_state(TASK_INTERRUPTIBLE);
-				timeout = schedule_timeout(HZ/100 + 1);
-				if (signal_pending(current)) {
+				if (msleep_interruptible(10)) {
 					err = -ERESTARTSYS;
 					goto up_prepare_mutex;
 				}