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authorRalf Baechle <ralf@linux-mips.org>2008-07-16 12:07:05 +0100
committerRalf Baechle <ralf@linux-mips.org>2008-07-20 14:38:18 +0100
commitd6d8a4635a8451ca3c6fa2aaf9bbf934d8e2097b (patch)
tree5c88efce6c89e6c3500a875ab285f1db5fa3cec3
parentc29d150305f7f655b7002cc31754c605e5c0d1a0 (diff)
[MIPS] Tinker with constraints in <asm/atomic.h> to fix build error.
[...] CC init/main.o include/asm/bitops.h: In function `start_kernel': include/asm/bitops.h:76: warning: asm operand 2 probably doesn't match constraints include/asm/bitops.h:76: warning: asm operand 2 probably doesn't match constraints include/asm/bitops.h:76: warning: asm operand 2 probably doesn't match constraints include/asm/bitops.h:76: error: impossible constraint in `asm' include/asm/bitops.h:76: error: impossible constraint in `asm' include/asm/bitops.h:76: error: impossible constraint in `asm' make[1]: *** [init/main.o] Error 1 [...] The build error is caused by the ages old gcc bug where gcc at the time of analyzing the constraints is unable to figure out that an "i" constraint actually can be satisfied and thus will abort unless an "r" is added to the constraint. For the actual code generation gcc will only ever use the "i" constraint. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--include/asm-mips/bitops.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 9a7274ba6a0..49df8c4c9d2 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -82,7 +82,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
"2: b 1b \n"
" .previous \n"
: "=&r" (temp), "=m" (*m)
- : "i" (bit), "m" (*m), "r" (~0));
+ : "ir" (bit), "m" (*m), "r" (~0));
#endif /* CONFIG_CPU_MIPSR2 */
} else if (cpu_has_llsc) {
__asm__ __volatile__(
@@ -147,7 +147,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
"2: b 1b \n"
" .previous \n"
: "=&r" (temp), "=m" (*m)
- : "i" (bit), "m" (*m));
+ : "ir" (bit), "m" (*m));
#endif /* CONFIG_CPU_MIPSR2 */
} else if (cpu_has_llsc) {
__asm__ __volatile__(
@@ -428,7 +428,7 @@ static inline int test_and_clear_bit(unsigned long nr,
"2: b 1b \n"
" .previous \n"
: "=&r" (temp), "=m" (*m), "=&r" (res)
- : "i" (bit), "m" (*m)
+ : "ir" (bit), "m" (*m)
: "memory");
#endif
} else if (cpu_has_llsc) {