glamo: rename glamo-fb.c/reg_* by glamofb_reg_* ; same for glamo-mci.c/glamo_reg_*

2 files changed, 67 insertions, 67 deletions

diff --git a/drivers/mmc/host/glamo-mci.c b/drivers/mmc/host/glamo-mci.c
index b2442c22b1a..4fb0c4a4189 100644
--- a/drivers/mmc/host/glamo-mci.c
+++ b/drivers/mmc/host/glamo-mci.c
@@ -110,19 +110,19 @@ static int sd_post_power_clock = 1000000;
 module_param(sd_post_power_clock, int, 0644);
 
 
-static inline void glamo_reg_write(struct glamo_mci_host *glamo,
+static inline void glamomci_reg_write(struct glamo_mci_host *glamo,
 				uint16_t reg, uint16_t val)
 {
 	writew(val, glamo->mmio_base + reg);
 }
 
-static inline uint16_t glamo_reg_read(struct glamo_mci_host *glamo,
+static inline uint16_t glamomci_reg_read(struct glamo_mci_host *glamo,
 				      uint16_t reg)
 {
 	return readw(glamo->mmio_base + reg);
 }
 
-static void glamo_reg_set_bit_mask(struct glamo_mci_host *glamo,
+static void glamomci_reg_set_bit_mask(struct glamo_mci_host *glamo,
 				   uint16_t reg, uint16_t mask,
 				   uint16_t val)
 {
@@ -130,24 +130,24 @@ static void glamo_reg_set_bit_mask(struct glamo_mci_host *glamo,
 
 	val &= mask;
 
-	tmp = glamo_reg_read(glamo, reg);
+	tmp = glamomci_reg_read(glamo, reg);
 	tmp &= ~mask;
 	tmp |= val;
-	glamo_reg_write(glamo, reg, tmp);
+	glamomci_reg_write(glamo, reg, tmp);
 }
 
 static void glamo_mci_reset(struct glamo_mci_host *host)
 {
 	glamo_engine_reset(host->core, GLAMO_ENGINE_MMC);
 
-	glamo_reg_write(host, GLAMO_REG_MMC_WDATADS1,
+	glamomci_reg_write(host, GLAMO_REG_MMC_WDATADS1,
 			(uint16_t)(host->data_mem->start));
-	glamo_reg_write(host, GLAMO_REG_MMC_WDATADS2,
+	glamomci_reg_write(host, GLAMO_REG_MMC_WDATADS2,
 			(uint16_t)(host->data_mem->start >> 16));
 
-	glamo_reg_write(host, GLAMO_REG_MMC_RDATADS1,
+	glamomci_reg_write(host, GLAMO_REG_MMC_RDATADS1,
 			(uint16_t)(host->data_mem->start));
-	glamo_reg_write(host, GLAMO_REG_MMC_RDATADS2,
+	glamomci_reg_write(host, GLAMO_REG_MMC_RDATADS2,
 			(uint16_t)(host->data_mem->start >> 16));
 
 }
@@ -226,7 +226,7 @@ static int glamo_mci_wait_idle(struct glamo_mci_host *host,
 {
 	uint16_t status;
 	do {
-		status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
+		status = glamomci_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
 	} while (!(status & GLAMO_STAT1_MMC_IDLE) &&
 		  time_is_after_jiffies(timeout));
 
@@ -257,7 +257,7 @@ static irqreturn_t glamo_mci_irq(int irq, void *data)
 	mrq = host->mrq;
 	cmd = mrq->cmd;
 
-	status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
+	status = glamomci_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
 	dev_dbg(&host->pdev->dev, "status = 0x%04x\n", status);
 
 	/* we ignore a data timeout report if we are also told the data came */
@@ -320,7 +320,7 @@ static void glamo_mci_read_worker(struct work_struct *work)
 		 * But the question is: what happens between the moment
 		 * the error occurs, and the moment the IRQ handler handles it?
 		 */
-		status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
+		status = glamomci_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
 
 		if (status & (GLAMO_STAT1_MMC_RTOUT | GLAMO_STAT1_MMC_DTOUT))
 			cmd->error = -ETIMEDOUT;
@@ -332,7 +332,7 @@ static void glamo_mci_read_worker(struct work_struct *work)
 			return;
 		}
 
-		blocks_ready = glamo_reg_read(host, GLAMO_REG_MMC_RB_BLKCNT);
+		blocks_ready = glamomci_reg_read(host, GLAMO_REG_MMC_RB_BLKCNT);
 		data_ready = blocks_ready * cmd->data->blksz;
 
 		if (data_ready == data_read)
@@ -364,7 +364,7 @@ static void glamo_mci_send_command(struct glamo_mci_host *host,
 	int triggers_int = 1;
 
 	/* if we can't do it, reject as busy */
-	if (!(glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1) &
+	if (!(glamomci_reg_read(host, GLAMO_REG_MMC_RB_STAT1) &
 		 GLAMO_STAT1_MMC_IDLE)) {
 		cmd->error = -EBUSY;
 		return;
@@ -379,9 +379,9 @@ static void glamo_mci_send_command(struct glamo_mci_host *host,
 	u8a[5] = (crc7(0, u8a, 5) << 1) | 0x01;
 
 	/* issue the wire-order array including CRC in register order */
-	glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG1, ((u8a[4] << 8) | u8a[5]));
-	glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG2, ((u8a[2] << 8) | u8a[3]));
-	glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG3, ((u8a[0] << 8) | u8a[1]));
+	glamomci_reg_write(host, GLAMO_REG_MMC_CMD_REG1, ((u8a[4] << 8) | u8a[5]));
+	glamomci_reg_write(host, GLAMO_REG_MMC_CMD_REG2, ((u8a[2] << 8) | u8a[3]));
+	glamomci_reg_write(host, GLAMO_REG_MMC_CMD_REG3, ((u8a[0] << 8) | u8a[1]));
 
 	/* command index toggle */
 	fire |= (host->request_counter & 1) << 12;
@@ -478,10 +478,10 @@ static void glamo_mci_send_command(struct glamo_mci_host *host,
 		host->mrq = cmd->mrq;
 
 	/* always largest timeout */
-	glamo_reg_write(host, GLAMO_REG_MMC_TIMEOUT, 0xfff);
+	glamomci_reg_write(host, GLAMO_REG_MMC_TIMEOUT, 0xfff);
 
 	/* Generate interrupt on txfer */
-	glamo_reg_set_bit_mask(host, GLAMO_REG_MMC_BASIC, 0xff36,
+	glamomci_reg_set_bit_mask(host, GLAMO_REG_MMC_BASIC, 0xff36,
 			0x0800 |
 			GLAMO_BASIC_MMC_NO_CLK_RD_WAIT |
 			GLAMO_BASIC_MMC_EN_COMPL_INT |
@@ -490,7 +490,7 @@ static void glamo_mci_send_command(struct glamo_mci_host *host,
 
 	/* send the command out on the wire */
 	/* dev_info(&host->pdev->dev, "Using FIRE %04X\n", fire); */
-	glamo_reg_write(host, GLAMO_REG_MMC_CMD_FIRE, fire);
+	glamomci_reg_write(host, GLAMO_REG_MMC_CMD_FIRE, fire);
 
 	/* we are deselecting card?  because it isn't going to ack then... */
 	if ((cmd->opcode == 7) && (cmd->arg == 0))
@@ -501,7 +501,7 @@ static void glamo_mci_send_command(struct glamo_mci_host *host,
 	 * -- we don't get interrupts unless there is a bulk rx
 	 */
 	do
-		status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
+		status = glamomci_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
 	while (((((status >> 15) & 1) != (host->request_counter & 1)) ||
 		(!(status & (GLAMO_STAT1_MMC_RB_RRDY |
 			     GLAMO_STAT1_MMC_RTOUT |
@@ -547,8 +547,8 @@ static int glamo_mci_prepare_pio(struct glamo_mci_host *host,
 				 struct mmc_data *data)
 {
 	/* set up the block info */
-	glamo_reg_write(host, GLAMO_REG_MMC_DATBLKLEN, data->blksz);
-	glamo_reg_write(host, GLAMO_REG_MMC_DATBLKCNT, data->blocks);
+	glamomci_reg_write(host, GLAMO_REG_MMC_DATBLKLEN, data->blksz);
+	glamomci_reg_write(host, GLAMO_REG_MMC_DATBLKCNT, data->blocks);
 
 	data->bytes_xfered = 0;
 
@@ -678,7 +678,7 @@ static void glamo_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 	if (sd_drive > 3)
 		sd_drive = 3;
 
-	glamo_reg_set_bit_mask(host, GLAMO_REG_MMC_BASIC,
+	glamomci_reg_set_bit_mask(host, GLAMO_REG_MMC_BASIC,
 				GLAMO_BASIC_MMC_EN_4BIT_DATA | 0xc0,
 						   bus_width | sd_drive << 6);
 
diff --git a/drivers/video/glamo-fb.c b/drivers/video/glamo-fb.c
index 517cc5c711e..3f8ec8d466a 100644
--- a/drivers/video/glamo-fb.c
+++ b/drivers/video/glamo-fb.c
@@ -95,12 +95,12 @@ static void glamo_output_disable(struct glamofb_handle *gfb)
 }
 
 
-static inline int reg_read(struct glamofb_handle *glamo, uint16_t reg)
+static inline int glamofb_reg_read(struct glamofb_handle *glamo, uint16_t reg)
 {
 	return readw(glamo->base + reg);
 }
 
-static inline void reg_write(struct glamofb_handle *glamo, uint16_t reg,
+static inline void glamofb_reg_write(struct glamofb_handle *glamo, uint16_t reg,
 	uint16_t val)
 {
 	writew(val, glamo->base + reg);
@@ -146,7 +146,7 @@ static int glamofb_run_script(struct glamofb_handle *glamo,
 		else if (line->reg == 0xfffe)
 			msleep(line->val);
 		else
-			reg_write(glamo, script[i].reg, script[i].val);
+			glamofb_reg_write(glamo, script[i].reg, script[i].val);
 	}
 
 	return 0;
@@ -166,7 +166,7 @@ static int glamofb_check_var(struct fb_var_screeninfo *var,
 	/* FIXME: set rgb positions */
 	switch (var->bits_per_pixel) {
 	case 16:
-		switch (reg_read(glamo, GLAMO_REG_LCD_MODE3) & 0xc000) {
+		switch (glamofb_reg_read(glamo, GLAMO_REG_LCD_MODE3) & 0xc000) {
 		case GLAMO_LCD_SRC_RGB565:
 			var->red.offset		= 11;
 			var->green.offset	= 5;
@@ -208,17 +208,17 @@ static int glamofb_check_var(struct fb_var_screeninfo *var,
 	return 0;
 }
 
-static void reg_set_bit_mask(struct glamofb_handle *glamo, uint16_t reg,
+static void glamofb_reg_set_bit_mask(struct glamofb_handle *glamo, uint16_t reg,
 	uint16_t mask, uint16_t val)
 {
 	uint16_t tmp;
 
 	val &= mask;
 
-	tmp = reg_read(glamo, reg);
+	tmp = glamofb_reg_read(glamo, reg);
 	tmp &= ~mask;
 	tmp |= val;
-	reg_write(glamo, reg, tmp);
+	glamofb_reg_write(glamo, reg, tmp);
 }
 
 #define GLAMO_LCD_WIDTH_MASK 0x03FF
@@ -250,11 +250,11 @@ static void __rotate_lcd(struct glamofb_handle *glamo, uint32_t rotation)
 		break;
 	}
 
-	reg_set_bit_mask(glamo,
+	glamofb_reg_set_bit_mask(glamo,
 			 GLAMO_REG_LCD_WIDTH,
 			 GLAMO_LCD_ROT_MODE_MASK,
 			 glamo_rot);
-	reg_set_bit_mask(glamo,
+	glamofb_reg_set_bit_mask(glamo,
 			 GLAMO_REG_LCD_MODE1,
 			 GLAMO_LCD_MODE1_ROTATE_EN,
 			 (glamo_rot != GLAMO_LCD_ROT_MODE_0) ?
@@ -264,7 +264,7 @@ static void __rotate_lcd(struct glamofb_handle *glamo, uint32_t rotation)
 static inline int glamofb_cmdq_empty(struct glamofb_handle *gfb)
 {
 	/* DGCMdQempty -- 1 == command queue is empty */
-	return reg_read(gfb, GLAMO_REG_LCD_STATUS1) & (1 << 15);
+	return glamofb_reg_read(gfb, GLAMO_REG_LCD_STATUS1) & (1 << 15);
 }
 
 /* call holding gfb->lock_cmd  when locking, until you unlock */
@@ -285,14 +285,14 @@ static int glamofb_cmd_mode(struct glamofb_handle *gfb, int on)
 		dev_dbg(gfb->dev, "empty!\n");
 
 		/* display the entire frame then switch to command */
-		reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
+		glamofb_reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
 			  GLAMO_LCD_CMD_TYPE_DISP |
 			  GLAMO_LCD_CMD_DATA_FIRE_VSYNC);
 
 		/* wait until lcd idle */
 		dev_dbg(gfb->dev, "waiting for lcd idle: ");
 		timeout = 2000000;
-		while (!(reg_read(gfb, GLAMO_REG_LCD_STATUS2) & (1 << 12)) &&
+		while (!(glamofb_reg_read(gfb, GLAMO_REG_LCD_STATUS2) & (1 << 12)) &&
 		      (timeout--))
 			cpu_relax();
 		if (timeout < 0) {
@@ -308,12 +308,12 @@ static int glamofb_cmd_mode(struct glamofb_handle *gfb, int on)
 
 	} else {
 		/* RGB interface needs vsync/hsync */
-		if (reg_read(gfb, GLAMO_REG_LCD_MODE3) & GLAMO_LCD_MODE3_RGB)
-			reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
+		if (glamofb_reg_read(gfb, GLAMO_REG_LCD_MODE3) & GLAMO_LCD_MODE3_RGB)
+			glamofb_reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
 				  GLAMO_LCD_CMD_TYPE_DISP |
 				  GLAMO_LCD_CMD_DATA_DISP_SYNC);
 
-		reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
+		glamofb_reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
 			  GLAMO_LCD_CMD_TYPE_DISP |
 			  GLAMO_LCD_CMD_DATA_DISP_FIRE);
 	}
@@ -339,15 +339,15 @@ static void glamofb_program_mode(struct glamofb_handle *gfb)
 		glamo_engine_reclock(gcore, GLAMO_ENGINE_LCD,
 				 (1000000000UL / gfb->fb->var.pixclock) * 1000);
 
-	reg_set_bit_mask(gfb,
+	glamofb_reg_set_bit_mask(gfb,
 			 GLAMO_REG_LCD_WIDTH,
 			 GLAMO_LCD_WIDTH_MASK,
 			 var->xres);
-	reg_set_bit_mask(gfb,
+	glamofb_reg_set_bit_mask(gfb,
 			 GLAMO_REG_LCD_HEIGHT,
 			 GLAMO_LCD_HEIGHT_MASK,
 			 var->yres);
-	reg_set_bit_mask(gfb,
+	glamofb_reg_set_bit_mask(gfb,
 			 GLAMO_REG_LCD_PITCH,
 			 GLAMO_LCD_PITCH_MASK,
 			 gfb->fb->fix.line_length);
@@ -362,15 +362,15 @@ static void glamofb_program_mode(struct glamofb_handle *gfb)
 	fp = disp + var->xres;
 	total = fp + var->right_margin;
 
-	reg_set_bit_mask(gfb, GLAMO_REG_LCD_HORIZ_TOTAL,
+	glamofb_reg_set_bit_mask(gfb, GLAMO_REG_LCD_HORIZ_TOTAL,
 			 GLAMO_LCD_HV_TOTAL_MASK, total);
-	reg_set_bit_mask(gfb, GLAMO_REG_LCD_HORIZ_RETR_START,
+	glamofb_reg_set_bit_mask(gfb, GLAMO_REG_LCD_HORIZ_RETR_START,
 			 GLAMO_LCD_HV_RETR_START_MASK, sync);
-	reg_set_bit_mask(gfb, GLAMO_REG_LCD_HORIZ_RETR_END,
+	glamofb_reg_set_bit_mask(gfb, GLAMO_REG_LCD_HORIZ_RETR_END,
 			 GLAMO_LCD_HV_RETR_END_MASK, bp);
-	reg_set_bit_mask(gfb, GLAMO_REG_LCD_HORIZ_DISP_START,
+	glamofb_reg_set_bit_mask(gfb, GLAMO_REG_LCD_HORIZ_DISP_START,
 			  GLAMO_LCD_HV_RETR_DISP_START_MASK, disp);
-	reg_set_bit_mask(gfb, GLAMO_REG_LCD_HORIZ_DISP_END,
+	glamofb_reg_set_bit_mask(gfb, GLAMO_REG_LCD_HORIZ_DISP_END,
 			 GLAMO_LCD_HV_RETR_DISP_END_MASK, fp);
 
 	sync = 0;
@@ -379,15 +379,15 @@ static void glamofb_program_mode(struct glamofb_handle *gfb)
 	fp = disp + var->yres;
 	total = fp + var->lower_margin;
 
-	reg_set_bit_mask(gfb, GLAMO_REG_LCD_VERT_TOTAL,
+	glamofb_reg_set_bit_mask(gfb, GLAMO_REG_LCD_VERT_TOTAL,
 			 GLAMO_LCD_HV_TOTAL_MASK, total);
-	reg_set_bit_mask(gfb, GLAMO_REG_LCD_VERT_RETR_START,
+	glamofb_reg_set_bit_mask(gfb, GLAMO_REG_LCD_VERT_RETR_START,
 			  GLAMO_LCD_HV_RETR_START_MASK, sync);
-	reg_set_bit_mask(gfb, GLAMO_REG_LCD_VERT_RETR_END,
+	glamofb_reg_set_bit_mask(gfb, GLAMO_REG_LCD_VERT_RETR_END,
 			 GLAMO_LCD_HV_RETR_END_MASK, bp);
-	reg_set_bit_mask(gfb, GLAMO_REG_LCD_VERT_DISP_START,
+	glamofb_reg_set_bit_mask(gfb, GLAMO_REG_LCD_VERT_DISP_START,
 			 GLAMO_LCD_HV_RETR_DISP_START_MASK, disp);
-	reg_set_bit_mask(gfb, GLAMO_REG_LCD_VERT_DISP_END,
+	glamofb_reg_set_bit_mask(gfb, GLAMO_REG_LCD_VERT_DISP_END,
 			 GLAMO_LCD_HV_RETR_DISP_END_MASK, fp);
 
 	glamofb_cmd_mode(gfb, 0);
@@ -550,8 +550,8 @@ static inline void glamofb_vsync_wait(struct glamofb_handle *glamo, int line,
 	int count[2];
 
 	do {
-		count[0] = reg_read(glamo, GLAMO_REG_LCD_STATUS2) & 0x3ff;
-		count[1] = reg_read(glamo, GLAMO_REG_LCD_STATUS2) & 0x3ff;
+		count[0] = glamofb_reg_read(glamo, GLAMO_REG_LCD_STATUS2) & 0x3ff;
+		count[1] = glamofb_reg_read(glamo, GLAMO_REG_LCD_STATUS2) & 0x3ff;
 	} while (count[0] != count[1] ||
 			(line < count[0] + range &&
 			 size > count[0] - range) ||
@@ -567,19 +567,19 @@ static void glamofb_cursor_onoff(struct glamofb_handle *glamo, int on)
 	int y, size;
 
 	if (glamo->cursor_on) {
-		y = reg_read(glamo, GLAMO_REG_LCD_CURSOR_Y_POS);
-		size = reg_read(glamo, GLAMO_REG_LCD_CURSOR_Y_SIZE);
+		y = glamofb_reg_read(glamo, GLAMO_REG_LCD_CURSOR_Y_POS);
+		size = glamofb_reg_read(glamo, GLAMO_REG_LCD_CURSOR_Y_SIZE);
 
 		glamofb_vsync_wait(glamo, y, size, 30);
 	}
 
-	reg_set_bit_mask(glamo, GLAMO_REG_LCD_MODE1,
+	glamofb_reg_set_bit_mask(glamo, GLAMO_REG_LCD_MODE1,
 			GLAMO_LCD_MODE1_CURSOR_EN,
 			on ? GLAMO_LCD_MODE1_CURSOR_EN : 0);
 	glamo->cursor_on = on;
 
 	/* Hide the cursor by default */
-	reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_SIZE, 0);
+	glamofb_reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_SIZE, 0);
 }
 
 static int glamofb_cursor(struct fb_info *info, struct fb_cursor *cursor)
@@ -589,13 +589,13 @@ static int glamofb_cursor(struct fb_info *info, struct fb_cursor *cursor)
 
 	spin_lock_irqsave(&glamo->lock_cmd, flags);
 
-	reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_SIZE,
+	glamofb_reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_SIZE,
 			cursor->enable ? cursor->image.width : 0);
 
 	if (cursor->set & FB_CUR_SETPOS) {
-		reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_POS,
+		glamofb_reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_POS,
 			  cursor->image.dx);
-		reg_write(glamo, GLAMO_REG_LCD_CURSOR_Y_POS,
+		glamofb_reg_write(glamo, GLAMO_REG_LCD_CURSOR_Y_POS,
 			  cursor->image.dy);
 	}
 
@@ -603,13 +603,13 @@ static int glamofb_cursor(struct fb_info *info, struct fb_cursor *cursor)
 		uint16_t fg = glamo->pseudo_pal[cursor->image.fg_color];
 		uint16_t bg = glamo->pseudo_pal[cursor->image.bg_color];
 
-		reg_write(glamo, GLAMO_REG_LCD_CURSOR_FG_COLOR, fg);
-		reg_write(glamo, GLAMO_REG_LCD_CURSOR_BG_COLOR, bg);
-		reg_write(glamo, GLAMO_REG_LCD_CURSOR_DST_COLOR, fg);
+		glamofb_reg_write(glamo, GLAMO_REG_LCD_CURSOR_FG_COLOR, fg);
+		glamofb_reg_write(glamo, GLAMO_REG_LCD_CURSOR_BG_COLOR, bg);
+		glamofb_reg_write(glamo, GLAMO_REG_LCD_CURSOR_DST_COLOR, fg);
 	}
 
 	if (cursor->set & FB_CUR_SETHOT)
-		reg_write(glamo, GLAMO_REG_LCD_CURSOR_PRESET,
+		glamofb_reg_write(glamo, GLAMO_REG_LCD_CURSOR_PRESET,
 				(cursor->hot.x << 8) | cursor->hot.y);
 
 	if ((cursor->set & FB_CUR_SETSIZE) ||
@@ -628,9 +628,9 @@ static int glamofb_cursor(struct fb_info *info, struct fb_cursor *cursor)
 		}
 
 		pitch = ((cursor->image.width + 7) >> 2) & ~1;
-		reg_write(glamo, GLAMO_REG_LCD_CURSOR_PITCH,
+		glamofb_reg_write(glamo, GLAMO_REG_LCD_CURSOR_PITCH,
 			pitch);
-		reg_write(glamo, GLAMO_REG_LCD_CURSOR_Y_SIZE,
+		glamofb_reg_write(glamo, GLAMO_REG_LCD_CURSOR_Y_SIZE,
 			cursor->image.height);
 
 		for (y = 0; y < cursor->image.height; y++) {