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authorTimo Teras <timo.teras@solidboot.com>2006-06-26 16:16:13 -0700
committerTony Lindgren <tony@atomide.com>2006-06-26 16:16:13 -0700
commite32f7ec2e8bf00756c74a5e6a80bc59e949dd81d (patch)
tree1b1e7d588c520ddad11c7ab036c4a50a5e92a49e
parent77900a2fc3bfb1eb6eaa6d43eef4591e1f7c600d (diff)
ARM: OMAP: Fix 32 kHz timer and modify GP timer to use GPT1
The dmtimer framework update broke 32 kHz timer as udelay() does not work before system timer is started (and GPT1 should not be reset). This also makes the GP timer use GPT1. This requires a fix in clock framework. Signed-off-by: Timo Teras <timo.teras@solidboot.com> Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--arch/arm/mach-omap2/clock.c2
-rw-r--r--arch/arm/mach-omap2/timer-gp.c2
-rw-r--r--arch/arm/plat-omap/dmtimer.c9
3 files changed, 7 insertions, 6 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 242d8f925e9..6789dd4029a 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -753,7 +753,7 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
val = 0x2;
break;
case CM_WKUP_SEL1:
- src_reg_addr = (u32)&CM_CLKSEL2_CORE;
+ src_reg_addr = (u32)&CM_CLKSEL_WKUP;
mask = 0x3;
if (src_clk == &func_32k_ck)
val = 0x0;
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 3358c0d47b1..cf78e6c5a27 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -61,7 +61,7 @@ static void __init omap2_gp_timer_init(void)
u32 tick_period;
omap_dm_timer_init();
- gptimer = omap_dm_timer_request_specific(2);
+ gptimer = omap_dm_timer_request_specific(1);
BUG_ON(gptimer == NULL);
omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index c25a1a6d2b0..bfccebc7751 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -147,9 +147,10 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
{
u32 l;
- omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
- omap_dm_timer_wait_for_reset(timer);
-
+ if (timer != &dm_timers[0]) {
+ omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
+ omap_dm_timer_wait_for_reset(timer);
+ }
omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_SYS_CLK);
/* Set to smart-idle mode */
@@ -335,7 +336,7 @@ void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
/* When the functional clock disappears, too quick writes seem to
* cause an abort. */
- udelay(50);
+ __delay(15000);
}
#endif