diff options
| author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-02-07 10:10:09 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-02-07 10:10:09 -0800 |
| commit | e8a82fd030c2e0ba4d4169cc4257ef174ff6f6b4 (patch) | |
| tree | 0515ffe68d9a88eda2d16f45e6391b05475fd9d1 | |
| parent | e1a8e6c9b757c09249ab29fc6da12d9ab64567e1 (diff) | |
| parent | b38c73995f63fe205c0068cb0ce3131895244068 (diff) | |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
79 files changed, 694 insertions, 751 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c3e852e9953..767de847b4a 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -595,6 +595,7 @@ config SGI_IP32 select SYS_HAS_CPU_R5000 select SYS_HAS_CPU_R10000 if BROKEN select SYS_HAS_CPU_RM7000 + select SYS_HAS_CPU_NEVADA select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN help diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 2a9f2ef27b2..6a57407df1b 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -53,14 +53,17 @@ CROSS_COMPILE := $(tool-prefix) endif CHECKFLAGS-y += -D__linux__ -D__mips__ \ + -D_MIPS_SZINT=32 \ -D_ABIO32=1 \ -D_ABIN32=2 \ -D_ABI64=3 CHECKFLAGS-$(CONFIG_32BIT) += -D_MIPS_SIM=_ABIO32 \ -D_MIPS_SZLONG=32 \ + -D_MIPS_SZPTR=32 \ -D__PTRDIFF_TYPE__=int CHECKFLAGS-$(CONFIG_64BIT) += -m64 -D_MIPS_SIM=_ABI64 \ -D_MIPS_SZLONG=64 \ + -D_MIPS_SZPTR=64 \ -D__PTRDIFF_TYPE__="long int" CHECKFLAGS-$(CONFIG_CPU_BIG_ENDIAN) += -D__MIPSEB__ CHECKFLAGS-$(CONFIG_CPU_LITTLE_ENDIAN) += -D__MIPSEL__ @@ -166,79 +169,97 @@ echo $$gcc_abi $$gcc_opt$$gcc_cpu $$gcc_isa $$gas_abi $$gas_opt$$gas_cpu $$gas_i # cflags-$(CONFIG_CPU_R3000) += \ $(call set_gccflags,r3000,mips1,r3000,mips1,mips1) +CHECKFLAGS-$(CONFIG_CPU_R3000) += -D_MIPS_ISA=_MIPS_ISA_MIPS1 cflags-$(CONFIG_CPU_TX39XX) += \ $(call set_gccflags,r3900,mips1,r3000,mips1,mips1) +CHECKFLAGS-$(CONFIG_CPU_TX39XX) += -D_MIPS_ISA=_MIPS_ISA_MIPS1 cflags-$(CONFIG_CPU_R6000) += \ $(call set_gccflags,r6000,mips2,r6000,mips2,mips2) \ -Wa,--trap +CHECKFLAGS-$(CONFIG_CPU_R6000) += -D_MIPS_ISA=_MIPS_ISA_MIPS2 cflags-$(CONFIG_CPU_R4300) += \ $(call set_gccflags,r4300,mips3,r4300,mips3,mips2) \ -Wa,--trap +CHECKFLAGS-$(CONFIG_CPU_R4300) += -D_MIPS_ISA=_MIPS_ISA_MIPS3 cflags-$(CONFIG_CPU_VR41XX) += \ $(call set_gccflags,r4100,mips3,r4600,mips3,mips2) \ -Wa,--trap +CHECKFLAGS-$(CONFIG_CPU_VR41XX) += -D_MIPS_ISA=_MIPS_ISA_MIPS3 cflags-$(CONFIG_CPU_R4X00) += \ $(call set_gccflags,r4600,mips3,r4600,mips3,mips2) \ -Wa,--trap +CHECKFLAGS-$(CONFIG_CPU_R4X00) += -D_MIPS_ISA=_MIPS_ISA_MIPS3 cflags-$(CONFIG_CPU_TX49XX) += \ $(call set_gccflags,r4600,mips3,r4600,mips3,mips2) \ -Wa,--trap +CHECKFLAGS-$(CONFIG_CPU_TX49XX) += -D_MIPS_ISA=_MIPS_ISA_MIPS3 cflags-$(CONFIG_CPU_MIPS32_R1) += \ $(call set_gccflags,mips32,mips32,r4600,mips3,mips2) \ -Wa,--trap +CHECKFLAGS-$(CONFIG_CPU_MIPS32_R1) += -D_MIPS_ISA=_MIPS_ISA_MIPS32 cflags-$(CONFIG_CPU_MIPS32_R2) += \ $(call set_gccflags,mips32r2,mips32r2,r4600,mips3,mips2) \ -Wa,--trap +CHECKFLAGS-$(CONFIG_CPU_MIPS32_R2) += -D_MIPS_ISA=_MIPS_ISA_MIPS32 cflags-$(CONFIG_CPU_MIPS64_R1) += \ $(call set_gccflags,mips64,mips64,r4600,mips3,mips2) \ -Wa,--trap +CHECKFLAGS-$(CONFIG_CPU_MIPS64_R1) += -D_MIPS_ISA=_MIPS_ISA_MIPS64 cflags-$(CONFIG_CPU_MIPS64_R2) += \ $(call set_gccflags,mips64r2,mips64r2,r4600,mips3,mips2) \ -Wa,--trap +CHECKFLAGS-$(CONFIG_CPU_MIPS64_R2) += -D_MIPS_ISA=_MIPS_ISA_MIPS64 cflags-$(CONFIG_CPU_R5000) += \ $(call set_gccflags,r5000,mips4,r5000,mips4,mips2) \ -Wa,--trap +CHECKFLAGS-$(CONFIG_CPU_R5000) += -D_MIPS_ISA=_MIPS_ISA_MIPS4 cflags-$(CONFIG_CPU_R5432) += \ $(call set_gccflags,r5400,mips4,r5000,mips4,mips2) \ -Wa,--trap +CHECKFLAGS-$(CONFIG_CPU_R5432) += -D_MIPS_ISA=_MIPS_ISA_MIPS4 cflags-$(CONFIG_CPU_NEVADA) += \ $(call set_gccflags,rm5200,mips4,r5000,mips4,mips2) \ -Wa,--trap -# $(call cc-option,-mmad) +CHECKFLAGS-$(CONFIG_CPU_NEVADA) += -D_MIPS_ISA=_MIPS_ISA_MIPS4 cflags-$(CONFIG_CPU_RM7000) += \ $(call set_gccflags,rm7000,mips4,r5000,mips4,mips2) \ -Wa,--trap +CHECKFLAGS-$(CONFIG_CPU_RM7000) += -D_MIPS_ISA=_MIPS_ISA_MIPS4 cflags-$(CONFIG_CPU_RM9000) += \ $(call set_gccflags,rm9000,mips4,r5000,mips4,mips2) \ -Wa,--trap +CHECKFLAGS-$(CONFIG_CPU_RM9000) += -D_MIPS_ISA=_MIPS_ISA_MIPS4 cflags-$(CONFIG_CPU_SB1) += \ $(call set_gccflags,sb1,mips64,r5000,mips4,mips2) \ -Wa,--trap +CHECKFLAGS-$(CONFIG_CPU_SB1) += -D_MIPS_ISA=_MIPS_ISA_MIPS64 cflags-$(CONFIG_CPU_R8000) += \ $(call set_gccflags,r8000,mips4,r8000,mips4,mips2) \ -Wa,--trap +CHECKFLAGS-$(CONFIG_CPU_R8000) += -D_MIPS_ISA=_MIPS_ISA_MIPS4 cflags-$(CONFIG_CPU_R10000) += \ $(call set_gccflags,r10000,mips4,r8000,mips4,mips2) \ -Wa,--trap +CHECKFLAGS-$(CONFIG_CPU_R10000) += -D_MIPS_ISA=_MIPS_ISA_MIPS4 ifdef CONFIG_CPU_SB1 ifdef CONFIG_SB1_PASS_1_WORKAROUNDS @@ -369,7 +390,7 @@ load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000 # Cobalt Server # core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/ -cflags-$(CONFIG_MIPS_COBALT) += -Iinclude/asm-mips/cobalt +cflags-$(CONFIG_MIPS_COBALT) += -Iinclude/asm-mips/mach-cobalt load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000 # diff --git a/arch/mips/au1000/common/reset.c b/arch/mips/au1000/common/reset.c index 65b84db800e..4ffccedf596 100644 --- a/arch/mips/au1000/common/reset.c +++ b/arch/mips/au1000/common/reset.c @@ -151,7 +151,7 @@ void au1000_restart(char *command) } set_c0_status(ST0_BEV | ST0_ERL); - set_c0_config(CONF_CM_UNCACHED); + change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); flush_cache_all(); write_c0_wired(0); diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c index 08c8c855cc9..eb155c071aa 100644 --- a/arch/mips/au1000/common/setup.c +++ b/arch/mips/au1000/common/setup.c @@ -33,6 +33,7 @@ #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/module.h> +#include <linux/pm.h> #include <asm/cpu.h> #include <asm/bootinfo.h> @@ -125,7 +126,7 @@ void __init plat_setup(void) #endif _machine_restart = au1000_restart; _machine_halt = au1000_halt; - _machine_power_off = au1000_power_off; + pm_power_off = au1000_power_off; board_time_init = au1xxx_time_init; board_timer_setup = au1xxx_timer_setup; diff --git a/arch/mips/cobalt/int-handler.S b/arch/mips/cobalt/int-handler.S index f92608e8d84..e75d5e3ca86 100644 --- a/arch/mips/cobalt/int-handler.S +++ b/arch/mips/cobalt/int-handler.S @@ -8,7 +8,7 @@ */ #include <asm/asm.h> #include <asm/mipsregs.h> -#include <asm/cobalt/cobalt.h> +#include <asm/mach-cobalt/cobalt.h> #include <asm/regdef.h> #include <asm/stackframe.h> diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c index 0d90851f925..f9a108820d6 100644 --- a/arch/mips/cobalt/irq.c +++ b/arch/mips/cobalt/irq.c @@ -18,7 +18,7 @@ #include <asm/gt64120.h> #include <asm/ptrace.h> -#include <asm/cobalt/cobalt.h> +#include <asm/mach-cobalt/cobalt.h> extern void cobalt_handle_int(void); diff --git a/arch/mips/cobalt/reset.c b/arch/mips/cobalt/reset.c index 805a0e88507..753dfccae6f 100644 --- a/arch/mips/cobalt/reset.c +++ b/arch/mips/cobalt/reset.c @@ -16,7 +16,7 @@ #include <asm/reboot.h> #include <asm/system.h> #include <asm/mipsregs.h> -#include <asm/cobalt/cobalt.h> +#include <asm/mach-cobalt/cobalt.h> void cobalt_machine_halt(void) { diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c index d358a118fa3..050685b87a3 100644 --- a/arch/mips/cobalt/setup.c +++ b/arch/mips/cobalt/setup.c @@ -5,7 +5,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv) * */ @@ -13,6 +13,7 @@ #include <linux/interrupt.h> #include <linux/pci.h> #include <linux/init.h> +#include <linux/pm.h> #include <linux/serial.h> #include <linux/serial_core.h> @@ -25,7 +26,7 @@ #include <asm/gt64120.h> #include <asm/serial.h> -#include <asm/cobalt/cobalt.h> +#include <asm/mach-cobalt/cobalt.h> extern void cobalt_machine_restart(char *command); extern void cobalt_machine_halt(void); @@ -99,7 +100,7 @@ void __init plat_setup(void) _machine_restart = cobalt_machine_restart; _machine_halt = cobalt_machine_halt; - _machine_power_off = cobalt_machine_power_off; + pm_power_off = cobalt_machine_power_off; board_timer_setup = cobalt_timer_setup; diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig index 967e7acd8e1..a34db6e82b2 100644 --- a/arch/mips/configs/ip32_defconfig +++ b/arch/mips/configs/ip32_defconfig @@ -102,6 +102,7 @@ CONFIG_CPU_R5000=y # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set CONFIG_SYS_HAS_CPU_R5000=y +CONFIG_SYS_HAS_CPU_NEVADA=y CONFIG_SYS_HAS_CPU_RM7000=y CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y diff --git a/arch/mips/configs/qemu_defconfig b/arch/mips/configs/qemu_defconfig index dee44606164..c02becab850 100644 --- a/arch/mips/configs/qemu_defconfig +++ b/arch/mips/configs/qemu_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.15-rc2 -# Thu Nov 24 01:07:00 2005 +# Linux kernel version: 2.6.16-rc2 +# Fri Feb 3 17:14:27 2006 # CONFIG_MIPS=y @@ -147,26 +147,27 @@ CONFIG_LOCALVERSION_AUTO=y # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_SYSCTL is not set # CONFIG_AUDIT is not set -# CONFIG_HOTPLUG is not set -CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set CONFIG_INITRAMFS_SOURCE="" CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +# CONFIG_HOTPLUG is not set CONFIG_PRINTK=y # CONFIG_BUG is not set +CONFIG_ELF_CORE=y # CONFIG_BASE_FULL is not set # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set # CONFIG_SHMEM is not set CONFIG_CC_ALIGN_FUNCTIONS=0 CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 +CONFIG_SLAB=y CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=1 +# CONFIG_SLOB is not set # # Loadable module support @@ -266,11 +267,7 @@ CONFIG_TCP_CONG_BIC=y # CONFIG_HAMRADIO is not set # CONFIG_IRDA is not set # CONFIG_BT is not set -CONFIG_IEEE80211=y -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=y -CONFIG_IEEE80211_CRYPT_CCMP=y -CONFIG_IEEE80211_CRYPT_TKIP=y +# CONFIG_IEEE80211 is not set # # Device Drivers @@ -323,7 +320,7 @@ CONFIG_BLK_DEV_RAM_COUNT=16 # # SCSI device support # -CONFIG_RAID_ATTRS=y +# CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set # @@ -366,24 +363,16 @@ CONFIG_NETDEVICES=y # # PHY device support # -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y +# CONFIG_PHYLIB is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y -CONFIG_MII=y +# CONFIG_MII is not set # CONFIG_NET_VENDOR_3COM is not set # CONFIG_NET_VENDOR_SMC is not set +# CONFIG_DM9000 is not set # CONFIG_NET_VENDOR_RACAL is not set # CONFIG_DEPCA is not set # CONFIG_HP100 is not set @@ -479,6 +468,7 @@ CONFIG_HW_CONSOLE=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_8250_EXTENDED is not set # @@ -518,6 +508,12 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_I2C is not set # +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# # Dallas's 1-wire bus # # CONFIG_W1 is not set @@ -592,11 +588,14 @@ CONFIG_DUMMY_CONSOLE=y # # +# EDAC - error detection and reporting (RAS) +# + +# # File systems # # CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set @@ -677,6 +676,7 @@ CONFIG_MSDOS_PARTITION=y # Kernel hacking # # CONFIG_PRINTK_TIME is not set +# CONFIG_MAGIC_SYSRQ is not set # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y @@ -690,31 +690,7 @@ CONFIG_CMDLINE="console=ttyS0 debug ip=172.20.0.2:172.20.0.1::255.255.0.0" # # Cryptographic options # -CONFIG_CRYPTO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_WP512=y -CONFIG_CRYPTO_TGR192=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_SERPENT=y -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_CAST5=y -CONFIG_CRYPTO_CAST6=y -CONFIG_CRYPTO_TEA=y -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_KHAZAD=y -CONFIG_CRYPTO_ANUBIS=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO is not set # # Hardware crypto devices @@ -724,8 +700,6 @@ CONFIG_CRYPTO_CRC32C=y # Library routines # # CONFIG_CRC_CCITT is not set -CONFIG_CRC16=y +# CONFIG_CRC16 is not set CONFIG_CRC32=y -CONFIG_LIBCRC32C=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y +# CONFIG_LIBCRC32C is not set diff --git a/arch/mips/ddb5xxx/ddb5074/setup.c b/arch/mips/ddb5xxx/ddb5074/setup.c index 11535be265b..91456b068c2 100644 --- a/arch/mips/ddb5xxx/ddb5074/setup.c +++ b/arch/mips/ddb5xxx/ddb5074/setup.c @@ -14,6 +14,7 @@ #include <linux/ide.h> #include <linux/ioport.h> #include <linux/irq.h> +#include <linux/pm.h> #include <asm/addrspace.h> #include <asm/bcache.h> @@ -95,7 +96,7 @@ void __init plat_setup(void) _machine_restart = ddb_machine_restart; _machine_halt = ddb_machine_halt; - _machine_power_off = ddb_machine_power_off; + pm_power_off = ddb_machine_power_off; ddb_out32(DDB_BAR0, 0); diff --git a/arch/mips/ddb5xxx/ddb5476/setup.c b/arch/mips/ddb5xxx/ddb5476/setup.c index f4e480a74ed..c902adef594 100644 --- a/arch/mips/ddb5xxx/ddb5476/setup.c +++ b/arch/mips/ddb5xxx/ddb5476/setup.c @@ -11,6 +11,7 @@ #include <linux/types.h> #include <linux/sched.h> #include <linux/pci.h> +#include <linux/pm.h> #include <asm/addrspace.h> #include <asm/bcache.h> @@ -133,7 +134,7 @@ void __init plat_setup(void) _machine_restart = ddb_machine_restart; _machine_halt = ddb_machine_halt; - _machine_power_off = ddb_machine_power_off; + pm_power_off = ddb_machine_power_off; /* request io port/mem resources */ if (request_resource(&ioport_resource, &ddb5476_ioport.dma1) || diff --git a/arch/mips/ddb5xxx/ddb5477/setup.c b/arch/mips/ddb5xxx/ddb5477/setup.c index 81163353c4a..2f566034cc4 100644 --- a/arch/mips/ddb5xxx/ddb5477/setup.c +++ b/arch/mips/ddb5xxx/ddb5477/setup.c @@ -26,6 +26,7 @@ #include <linux/major.h> #include <linux/kdev_t.h> #include <linux/root_dev.h> +#include <linux/pm.h> #include <asm/cpu.h> #include <asm/bootinfo.h> @@ -182,7 +183,7 @@ void __init plat_setup(void) _machine_restart = ddb_machine_restart; _machine_halt = ddb_machine_halt; - _machine_power_off = ddb_machine_power_off; + pm_power_off = ddb_machine_power_off; /* setup resource limits */ ioport_resource.end = DDB_PCI0_IO_SIZE + DDB_PCI1_IO_SIZE - 1; diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c index 9ef54fe1fea..7c1ca8f6330 100644 --- a/arch/mips/dec/setup.c +++ b/arch/mips/dec/setup.c @@ -17,6 +17,7 @@ #include <linux/sched.h> #include <linux/spinlock.h> #include <linux/types.h> +#include <linux/pm.h> #include <asm/bootinfo.h> #include <asm/cpu.h> @@ -158,7 +159,7 @@ void __init plat_setup(void) _machine_restart = dec_machine_restart; _machine_halt = dec_machine_halt; - _machine_power_off = dec_machine_power_off; + pm_power_off = dec_machine_power_off; ioport_resource.start = ~0UL; ioport_resource.end = 0UL; diff --git a/arch/mips/gt64120/ev64120/setup.c b/arch/mips/gt64120/ev64120/setup.c index 98b5a96cc03..6d859d1e7a2 100644 --- a/arch/mips/gt64120/ev64120/setup.c +++ b/arch/mips/gt64120/ev64120/setup.c @@ -34,6 +34,8 @@ #include <linux/interrupt.h> #include <linux/pci.h> #include <linux/timex.h> +#include <linux/pm.h> + #include <asm/bootinfo.h> #include <asm/page.h> #include <asm/io.h> @@ -73,7 +75,7 @@ void __init plat_setup(void) { _machine_restart = galileo_machine_restart; _machine_halt = galileo_machine_halt; - _machine_power_off = galileo_machine_power_off; + pm_power_off = galileo_machine_power_off; board_time_init = gt64120_time_init; set_io_port_base(KSEG1); diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c index 0d07c33112d..20b65d3d215 100644 --- a/arch/mips/gt64120/momenco_ocelot/setup.c +++ b/arch/mips/gt64120/momenco_ocelot/setup.c @@ -4,7 +4,7 @@ * BRIEF MODULE DESCRIPTION * Momentum Computer Ocelot (CP7000) - board dependent boot routines * - * Copyright (C) 1996, 1997, 2001 Ralf Baechle + * Copyright (C) 1996, 1997, 2001, 06 Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 2000 RidgeRun, Inc. * Copyright (C) 2001 Red Hat, Inc. * Copyright (C) 2002 Momentum Computer @@ -47,6 +47,8 @@ #include <linux/pci.h> #include <linux/timex.h> #include <linux/vmalloc.h> +#include <linux/pm.h> + #include <asm/time.h> #include <asm/bootinfo.h> #include <asm/page.h> @@ -159,7 +161,7 @@ void __init plat_setup(void) _machine_restart = momenco_ocelot_restart; _machine_halt = momenco_ocelot_halt; - _machine_power_off = momenco_ocelot_power_off; + pm_power_off = momenco_ocelot_power_off; /* * initrd_start = (ulong)ocelot_initrd_start; diff --git a/arch/mips/ite-boards/generic/it8172_setup.c b/arch/mips/ite-boards/generic/it8172_setup.c index 062429dd7ca..fc73c8d69df 100644 --- a/arch/mips/ite-boards/generic/it8172_setup.c +++ b/arch/mips/ite-boards/generic/it8172_setup.c @@ -34,6 +34,7 @@ #include <linux/major.h> #include <linux/kdev_t.h> #include <linux/root_dev.h> +#include <linux/pm.h> #include <asm/cpu.h> #include <asm/time.h> @@ -125,7 +126,7 @@ void __init plat_setup(void) _machine_restart = it8172_restart; _machine_halt = it8172_halt; - _machine_power_off = it8172_power_off; + pm_power_off = it8172_power_off; /* * IO/MEM resources. diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c index 044df9d4ab7..4036dc43455 100644 --- a/arch/mips/jazz/setup.c +++ b/arch/mips/jazz/setup.c @@ -19,6 +19,8 @@ #include <linux/console.h> #include <linux/fb.h> #include <linux/ide.h> +#include <linux/pm.h> + #include <asm/bootinfo.h> #include <asm/irq.h> #include <asm/jazz.h> @@ -79,7 +81,7 @@ void __init plat_setup(void) _machine_restart = jazz_machine_restart; _machine_halt = jazz_machine_halt; - _machine_power_off = jazz_machine_power_off; + pm_power_off = jazz_machine_power_off; #warning "Somebody should check if screen_info is ok for Jazz." diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c index 4763957df8f..9359cc41349 100644 --- a/arch/mips/jmr3927/rbhma3100/setup.c +++ b/arch/mips/jmr3927/rbhma3100/setup.c @@ -44,6 +44,7 @@ #include <linux/ioport.h> #include <linux/param.h> /* for HZ */ #include <linux/delay.h> +#include <linux/pm.h> #ifdef CONFIG_SERIAL_TXX9 #include <linux/tty.h> #include <linux/serial.h> @@ -211,7 +212,7 @@ void __init plat_setup(void) _machine_restart = jmr3927_machine_restart; _machine_halt = jmr3927_machine_halt; - _machine_power_off = jmr3927_machine_power_off; + pm_power_off = jmr3927_machine_power_off; /* * IO/MEM resources. diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index fac48ad27b3..292f8b243a5 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -2,8 +2,8 @@ * Processor capabilities determination functions. * * Copyright (C) xxxx the Anonymous + * Copyright (C) 1994 - 2006 Ralf Baechle * Copyright (C) 2003, 2004 Maciej W. Rozycki - * Copyright (C) 1994 - 2003 Ralf Baechle * Copyright (C) 2001, 2004 MIPS Inc. * * This program is free software; you can redistribute it and/or @@ -641,10 +641,9 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) switch (c->processor_id & 0xff00) { case PRID_IMP_SB1: c->cputype = CPU_SB1; -#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS /* FPU in pass1 is known to have issues. */ - c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); -#endif + if ((c->processor_id & 0xff) < 0x20) + c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); break; case PRID_IMP_SB1A: c->cputype = CPU_SB1A; diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index aa18a8b7b38..13f22d1d0e8 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -233,11 +233,11 @@ NESTED(except_vec_nmi, 0, sp) NESTED(nmi_handler, PT_SIZE, sp) .set push .set noat - .set mips3 SAVE_ALL move a0, sp jal nmi_exception_handler RESTORE_ALL + .set mips3 eret .set pop END(nmi_handler) diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c index 0c82b25d8c6..0d5cf97af72 100644 --- a/arch/mips/kernel/ptrace32.c +++ b/arch/mips/kernel/ptrace32.c @@ -88,7 +88,7 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) ret = -EIO; if (copied != sizeof(tmp)) break; - ret = put_user(tmp, (unsigned int *) (unsigned long) data); + ret = put_user(tmp, (unsigned int __user *) (unsigned long) data); break; } @@ -174,8 +174,10 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) case FPC_EIR: { /* implementation / version register */ unsigned int flags; - if (!cpu_has_fpu) + if (!cpu_has_fpu) { + tmp = 0; break; + } preempt_disable(); if (cpu_has_mipsmt) { @@ -194,15 +196,18 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) preempt_enable(); break; } - case DSP_BASE ... DSP_BASE + 5: + case DSP_BASE ... DSP_BASE + 5: { + dspreg_t *dregs; + if (!cpu_has_dsp) { tmp = 0; ret = -EIO; goto out_tsk; } - dspreg_t *dregs = __get_dsp_regs(child); + dregs = __get_dsp_regs(child); tmp = (unsigned long) (dregs[addr - DSP_BASE]); break; + } case DSP_CONTROL: if (!cpu_has_dsp) { tmp = 0; @@ -216,7 +221,7 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) ret = -EIO; goto out_tsk; } - ret = put_user(tmp, (unsigned *) (unsigned long) data); + ret = put_user(tmp, (unsigned __user *) (unsigned long) data); break; } @@ -304,15 +309,18 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) else child->thread.fpu.soft.fcr31 = data; break; - case DSP_BASE ... DSP_BASE + 5: + case DSP_BASE ... DSP_BASE + 5: { + dspreg_t *dregs; + if (!cpu_has_dsp) { ret = -EIO; break; } - dspreg_t *dregs = __get_dsp_regs(child); + dregs = __get_dsp_regs(child); dregs[addr - DSP_BASE] = data; break; + } case DSP_CONTROL: if (!cpu_has_dsp) { ret = -EIO; diff --git a/arch/mips/kernel/reset.c b/arch/mips/kernel/reset.c index 5e37df3111a..621037db229 100644 --- a/arch/mips/kernel/reset.c +++ b/arch/mips/kernel/reset.c @@ -3,17 +3,16 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2001 by Ralf Baechle + * Copyright (C) 2001, 06 by Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 2001 MIPS Technologies, Inc. */ #include <linux/kernel.h> #include <linux/module.h> +#include <linux/pm.h> #include <linux/types.h> #include <linux/reboot.h> -#include <asm/reboot.h> -void (*pm_power_off)(void); -EXPORT_SYMBOL(pm_power_off); +#include <asm/reboot.h> /* * Urgs ... Too many MIPS machines to handle this in a generic way. @@ -22,23 +21,22 @@ EXPORT_SYMBOL(pm_power_off); */ void (*_machine_restart)(char *command); void (*_machine_halt)(void); -void (*_machine_power_off)(void); +void (*pm_power_off)(void); void machine_restart(char *command) { - _machine_restart(command); + if (_machine_restart) + _machine_restart(command); } void machine_halt(void) { - _machine_halt(); + if (_machine_halt) + _machine_halt(); } void machine_power_off(void) { if (pm_power_off) pm_power_off(); - - _machine_power_off(); } - diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index 1d855112bac..986a9cf2306 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2005, 06 Ralf Baechle (ralf@linux-mips.org) * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -20,9 +21,12 @@ #include <linux/module.h> #include <linux/fs.h> #include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> #include <linux/poll.h> #include <linux/sched.h> #include <linux/wait.h> + #include <asm/mipsmtregs.h> #include <asm/bitops.h> #include <asm/cpu.h> diff --git a/arch/mips/kernel/signal-common.h b/arch/mips/kernel/signal-common.h index 0f66ae5838b..0fbc492d24b 100644 --- a/arch/mips/kernel/signal-common.h +++ b/arch/mips/kernel/signal-common.h @@ -11,7 +11,7 @@ #include <linux/config.h> static inline int -setup_sigcontext(struct pt_regs *regs, struct sigcontext *sc) +setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) { int err = 0; @@ -82,7 +82,7 @@ out: } static inline int -restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc) +restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) { unsigned int used_math; unsigned long treg; @@ -157,7 +157,7 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc) /* * Determine which stack to use.. */ -static inline void * +static inline void __user * get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size) { unsigned long sp; @@ -176,7 +176,7 @@ get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size) if ((ka->sa.sa_flags & SA_ONSTACK) && (sas_ss_flags (sp) == 0)) sp = current->sas_ss_sp + current->sas_ss_size; - return (void *)((sp - frame_size) & (ICACHE_REFILLS_WORKAROUND_WAR ? 32 : ALMASK)); + return (void __user *)((sp - frame_size) & (ICACHE_REFILLS_WORKAROUND_WAR ? 32 : ALMASK)); } static inline int install_sigtramp(unsigned int __user *tramp, diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index 7d1800fe703..aaec4785e9a 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -199,10 +199,10 @@ save_static_function(sys_sigreturn); __attribute_used__ noinline static void _sys_sigreturn(nabi_no_regargs struct pt_regs regs) { - struct sigframe *frame; + struct sigframe __user *frame; sigset_t blocked; - frame = (struct sigframe *) regs.regs[29]; + frame = (struct sigframe __user *) regs.regs[29]; if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) goto badframe; if (__copy_from_user(&blocked, &frame->sf_mask, sizeof(blocked))) @@ -236,11 +236,11 @@ save_static_function(sys_rt_sigreturn); __attribute_used__ noinline static void _sys_rt_sigreturn(nabi_no_regargs struct pt_regs regs) { - struct rt_sigframe *frame; + struct rt_sigframe __user *frame; sigset_t set; stack_t st; - frame = (struct rt_sigframe *) regs.regs[29]; + frame = (struct rt_sigframe __user *) regs.regs[29]; if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) goto badframe; if (__copy_from_user(&set, &frame->rs_uc.uc_sigmask, sizeof(set))) @@ -259,7 +259,7 @@ _sys_rt_sigreturn(nabi_no_regargs struct pt_regs regs) goto badframe; /* It is more difficult to avoid calling this function than to call it and ignore errors. */ - do_sigaltstack(&st, NULL, regs.regs[29]); + do_sigaltstack((stack_t __user *)&st, NULL, regs.regs[29]); /* * Don't let your children do this ... @@ -279,7 +279,7 @@ badframe: int setup_frame(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *set) { - struct sigframe *frame; + struct sigframe __user *frame; int err = 0; frame = get_sigframe(ka, regs, sizeof(*frame)); @@ -326,7 +326,7 @@ give_sigsegv: int setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info) { - struct rt_sigframe *frame; + struct rt_sigframe __user *frame; int err = 0; frame = get_sigframe(ka, regs, sizeof(*frame)); @@ -340,7 +340,7 @@ int setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, /* Create the ucontext. */ err |= __put_user(0, &frame->rs_uc.uc_flags); - err |= __put_user(0, &frame->rs_uc.uc_link); + err |= __put_user(NULL, &frame->rs_uc.uc_link); err |= __put_user((void *)current->sas_ss_sp, &frame->rs_uc.uc_stack.ss_sp); err |= __put_user(sas_ss_flags(regs->regs[29]), diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index 98b185bbc94..136260c8f75 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -144,7 +144,7 @@ struct ucontext32 { extern void __put_sigset_unknown_nsig(void); extern void __get_sigset_unknown_nsig(void); -static inline int put_sigset(const sigset_t *kbuf, compat_sigset_t *ubuf) +static inline int put_sigset(const sigset_t *kbuf, compat_sigset_t __user *ubuf) { int err = 0; @@ -269,7 +269,7 @@ asmlinkage int sys32_sigaction(int sig, const struct sigaction32 *act, if (!access_ok(VERIFY_READ, act, sizeof(*act))) return -EFAULT; err |= __get_user(handler, &act->sa_handler); - new_ka.sa.sa_handler = (void*)(s64)handler; + new_ka.sa.sa_handler = (void __user *)(s64)handler; err |= __get_user(new_ka.sa.sa_flags, &act->sa_flags); err |= __get_user(mask, &act->sa_mask.sig[0]); if (err) @@ -299,8 +299,8 @@ asmlinkage int sys32_sigaction(int sig, const struct sigaction32 *act, asmlinkage int sys32_sigaltstack(nabi_no_regargs struct pt_regs regs) { - const stack32_t *uss = (const stack32_t *) regs.regs[4]; - stack32_t *uoss = (stack32_t *) regs.regs[5]; + const stack32_t __user *uss = (const stack32_t __user *) regs.regs[4]; + stack32_t __user *uoss = (stack32_t __user *) regs.regs[5]; unsigned long usp = regs.regs[29]; stack_t kss, koss; int ret, err = 0; @@ -319,7 +319,8 @@ asmlinkage int sys32_sigaltstack(nabi_no_regargs struct pt_regs regs) } set_fs (KERNEL_DS); - ret = do_sigaltstack(uss ? &kss : NULL , uoss ? &koss : NULL, usp); + ret = do_sigaltstack(uss ? (stack_t __user *)&kss : NULL, + uoss ? (stack_t __user *)&koss : NULL, usp); set_fs (old_fs); if (!ret && uoss) { @@ -335,7 +336,7 @@ asmlinkage int sys32_sigaltstack(nabi_no_regargs struct pt_regs regs) return ret; } -static int restore_sigcontext32(struct pt_regs *regs, struct sigcontext32 *sc) +static int restore_sigcontext32(struct pt_regs *regs, struct sigcontext32 __user *sc) { u32 used_math; int err = 0; @@ -420,7 +421,7 @@ struct rt_sigframe32 { #endif }; -int copy_siginfo_to_user32(compat_siginfo_t *to, siginfo_t *from) +int copy_siginfo_to_user32(compat_siginfo_t __user *to, siginfo_t *from) { int err; @@ -455,7 +456,7 @@ int copy_siginfo_to_user32(compat_siginfo_t *to, siginfo_t *from) err |= __put_user(from->si_uid, &to->si_uid); break; case __SI_FAULT >> 16: - err |= __put_user((long)from->si_addr, &to->si_addr); + err |= __put_user((unsigned long)from->si_addr, &to->si_addr); break; case __SI_POLL >> 16: err |= __put_user(from->si_band, &to->si_band); @@ -476,10 +477,10 @@ save_static_function(sys32_sigreturn); __attribute_used__ noinline static void _sys32_sigreturn(nabi_no_regargs struct pt_regs regs) { - struct sigframe *frame; + struct sigframe __user *frame; sigset_t blocked; - frame = (struct sigframe *) regs.regs[29]; + frame = (struct sigframe __user *) regs.regs[29]; if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) goto badframe; if (__copy_from_user(&blocked, &frame->sf_mask, sizeof(blocked))) @@ -512,13 +513,13 @@ save_static_function(sys32_rt_sigreturn); __attribute_used__ noinline static void _sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs) { - struct rt_sigframe32 *frame; + struct rt_sigframe32 __user *frame; mm_segment_t old_fs; sigset_t set; stack_t st; s32 sp; - frame = (struct rt_sigframe32 *) regs.regs[29]; + frame = (struct rt_sigframe32 __user *) regs.regs[29]; if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) goto badframe; if (__copy_from_user(&set, &frame->rs_uc.uc_sigmask, sizeof(set))) @@ -546,7 +547,7 @@ _sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs) call it and ignore errors. */ old_fs = get_fs(); set_fs (KERNEL_DS); - do_sigaltstack(&st, NULL, regs.regs[29]); + do_sigaltstack((stack_t __user *)&st, NULL, regs.regs[29]); set_fs (old_fs); /* @@ -564,7 +565,7 @@ badframe: } static inline int setup_sigcontext32(struct pt_regs *regs, - struct sigcontext32 *sc) + struct sigcontext32 __user *sc) { int err = 0; @@ -623,8 +624,9 @@ out: /* * Determine which stack to use.. */ -static inline void *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, - size_t frame_size) +static inline void __user *get_sigframe(struct k_sigaction *ka, + struct pt_regs *regs, + size_t frame_size) { unsigned long sp; @@ -642,13 +644,13 @@ static inline void *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, if ((ka->sa.sa_flags & SA_ONSTACK) && (sas_ss_flags (sp) == 0)) sp = current->sas_ss_sp + current->sas_ss_size; - return (void *)((sp - frame_size) & ALMASK); + return (void __user *)((sp - frame_size) & ALMASK); } int setup_frame_32(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *set) { - struct sigframe *frame; + struct sigframe __user *frame; int err = 0; frame = get_sigframe(ka, regs, sizeof(*frame)); @@ -702,7 +704,7 @@ give_sigsegv: int setup_rt_frame_32(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info) { - struct rt_sigframe32 *frame; + struct rt_sigframe32 __user *frame; int err = 0; s32 sp; @@ -855,7 +857,7 @@ no_signal: } asmlinkage int sys32_rt_sigaction(int sig, const struct sigaction32 *act, - struct sigaction32 *oact, + struct sigaction32 __user *oact, unsigned int sigsetsize) { struct k_sigaction new_sa, old_sa; @@ -872,7 +874,7 @@ asmlinkage int sys32_rt_sigaction(int sig, const struct sigaction32 *act, if (!access_ok(VERIFY_READ, act, sizeof(*act))) return -EFAULT; err |= __get_user(handler, &act->sa_handler); - new_sa.sa.sa_handler = (void*)(s64)handler; + new_sa.sa.sa_handler = (void __user *)(s64)handler; err |= __get_user(new_sa.sa.sa_flags, &act->sa_flags); err |= get_sigset(&new_sa.sa.sa_mask, &act->sa_mask); if (err) @@ -899,7 +901,7 @@ out: } asmlinkage int sys32_rt_sigprocmask(int how, compat_sigset_t *set, - compat_sigset_t *oset, unsigned int sigsetsize) + compat_sigset_t __user *oset, unsigned int sigsetsize) { sigset_t old_set, new_set; int ret; @@ -909,8 +911,9 @@ asmlinkage int sys32_rt_sigprocmask(int how, compat_sigset_t *set, return -EFAULT; set_fs (KERNEL_DS); - ret = sys_rt_sigprocmask(how, set ? &new_set : NULL, - oset ? &old_set : NULL, sigsetsize); + ret = sys_rt_sigprocmask(how, set ? (sigset_t __user *)&new_set : NULL, + oset ? (sigset_t __user *)&old_set : NULL, + sigsetsize); set_fs (old_fs); if (!ret && oset && put_sigset(&old_set, oset)) @@ -919,7 +922,7 @@ asmlinkage int sys32_rt_sigprocmask(int how, compat_sigset_t *set, return ret; } -asmlinkage int sys32_rt_sigpending(compat_sigset_t *uset, +asmlinkage int sys32_rt_sigpending(compat_sigset_t __user *uset, unsigned int sigsetsize) { int ret; @@ -927,7 +930,7 @@ asmlinkage int sys32_rt_sigpending(compat_sigset_t *uset, mm_segment_t old_fs = get_fs(); set_fs (KERNEL_DS); - ret = sys_rt_sigpending(&set, sigsetsize); + ret = sys_rt_sigpending((sigset_t __user *)&set, sigsetsize); set_fs (old_fs); if (!ret && put_sigset(&set, uset)) @@ -936,7 +939,7 @@ asmlinkage int sys32_rt_sigpending(compat_sigset_t *uset, return ret; } -asmlinkage int sys32_rt_sigqueueinfo(int pid, int sig, compat_siginfo_t *uinfo) +asmlinkage int sys32_rt_sigqueueinfo(int pid, int sig, compat_siginfo_t __user *uinfo) { siginfo_t info; int ret; @@ -946,7 +949,7 @@ asmlinkage int sys32_rt_sigqueueinfo(int pid, int sig, compat_siginfo_t *uinfo) copy_from_user (info._sifields._pad, uinfo->_sifields._pad, SI_PAD_SIZE)) return -EFAULT; set_fs (KERNEL_DS); - ret = sys_rt_sigqueueinfo(pid, sig, &info); + ret = sys_rt_sigqueueinfo(pid, sig, (siginfo_t __user *)&info); set_fs (old_fs); return ret; } diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c index ec61b2670ba..9156863c1a5 100644 --- a/arch/mips/kernel/signal_n32.c +++ b/arch/mips/kernel/signal_n32.c @@ -48,6 +48,8 @@ #define __NR_N32_rt_sigreturn 6211 #define __NR_N32_restart_syscall 6214 +#define DEBUG_SIG 0 + #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) /* IRIX compatible stack_t */ @@ -83,12 +85,12 @@ save_static_function(sysn32_rt_sigreturn); __attribute_used__ noinline static void _sysn32_rt_sigreturn(nabi_no_regargs struct pt_regs regs) { - struct rt_sigframe_n32 *frame; + struct rt_sigframe_n32 __user *frame; sigset_t set; stack_t st; s32 sp; - frame = (struct rt_sigframe_n32 *) regs.regs[29]; + frame = (struct rt_sigframe_n32 __user *) regs.regs[29]; if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) goto badframe; if (__copy_from_user(&set, &frame->rs_uc.uc_sigmask, sizeof(set))) @@ -114,7 +116,7 @@ _sysn32_rt_sigreturn(nabi_no_regargs struct pt_regs regs) /* It is more difficult to avoid calling this function than to call it and ignore errors. */ - do_sigaltstack(&st, NULL, regs.regs[29]); + do_sigaltstack((stack_t __user *)&st, NULL, regs.regs[29]); /* * Don't let your children do this ... @@ -133,7 +135,7 @@ badframe: int setup_rt_frame_n32(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info) { - struct rt_sigframe_n32 *frame; + struct rt_sigframe_n32 __user *frame; int err = 0; s32 sp; diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 59a187956de..c9d2b5147ca 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1168,7 +1168,7 @@ void __init per_cpu_trap_init(void) #endif if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) status_set |= ST0_XX; - change_c0_status(ST0_CU|ST0_MX|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, + change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, status_set); if (cpu_has_dsp) diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 25cc856d8e7..ff699dbb99f 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -1,4 +1,5 @@ #include <linux/config.h> +#include <asm/asm-offsets.h> #include <asm-generic/vmlinux.lds.h> #undef mips /* CPP really sucks for this job */ @@ -64,10 +65,10 @@ SECTIONS we can shorten the on-disk segment size. */ .sdata : { *(.sdata) } - . = ALIGN(4096); + . = ALIGN(_PAGE_SIZE); __nosave_begin = .; .data_nosave : { *(.data.nosave) } - . = ALIGN(4096); + . = ALIGN(_PAGE_SIZE); __nosave_end = .; . = ALIGN(32); @@ -76,7 +77,7 @@ SECTIONS _edata = .; /* End of data section */ /* will be freed after init */ - . = ALIGN(4096); /* Init code and data */ + . = ALIGN(_PAGE_SIZE); /* Init code and data */ __init_begin = .; .init.text : { _sinittext = .; @@ -105,7 +106,7 @@ SECTIONS .con_initcall.init : { *(.con_initcall.init) } __con_initcall_end = .; SECURITY_INIT - . = ALIGN(4096); + . = ALIGN(_PAGE_SIZE); __initramfs_start = .; .init.ramfs : { *(.init.ramfs) } __initramfs_end = .; @@ -113,7 +114,7 @@ SECTIONS __per_cpu_start = .; .data.percpu : { *(.data.percpu) } __per_cpu_end = .; - . = ALIGN(4096); + . = ALIGN(_PAGE_SIZE); __init_end = .; /* freed after init ends here */ diff --git a/arch/mips/lasat/reset.c b/arch/mips/lasat/reset.c index 8d7d7a454f9..181bf68175f 100644 --- a/arch/mips/lasat/reset.c +++ b/arch/mips/lasat/reset.c @@ -19,9 +19,12 @@ */ #include <linux/config.h> #include <linux/kernel.h> +#include <linux/pm.h> + #include <asm/reboot.h> #include <asm/system.h> #include <asm/lasat/lasat.h> + #include "picvue.h" #include "prom.h" @@ -63,5 +66,5 @@ void lasat_reboot_setup(void) { _machine_restart = lasat_machine_restart; _machine_halt = lasat_machine_halt; - _machine_power_off = lasat_machine_halt; + pm_power_off = lasat_machine_halt; } diff --git a/arch/mips/lib-32/dump_tlb.c b/arch/mips/lib-32/dump_tlb.c index 46519f4331e..c49a925d016 100644 --- a/arch/mips/lib-32/dump_tlb.c +++ b/arch/mips/lib-32/dump_tlb.c @@ -158,29 +158,26 @@ void dump_list_process(struct task_struct *t, void *address) printk("task->mm == %8p\n", t->mm); //printk("tasks->mm.pgd == %08x\n", (unsigned int) t->mm->pgd); - if (addr > KSEG0) + if (addr > KSEG0) { page_dir = pgd_offset_k(0); - else if (t->mm) { - page_dir = pgd_offset(t->mm, 0); - printk("page_dir == %08x\n", (unsigned int) page_dir); - } else - printk("Current thread has no mm\n"); - - if (addr > KSEG0) pgd = pgd_offset_k(addr); - else if (t->mm) { + } else if (t->mm) { + page_dir = pgd_offset(t->mm, 0); pgd = pgd_offset(t->mm, addr); - printk("pgd == %08x, ", (unsigned int) pgd); - pud = pud_offset(pgd, addr); - printk("pud == %08x, ", (unsigned int) pud); + } else { + printk("Current thread has no mm\n"); + return; + } + printk("page_dir == %08x\n", (unsigned int) page_dir); + printk("pgd == %08x, ", (unsigned int) pgd); + pud = pud_offset(pgd, addr); + printk("pud == %08x, ", (unsigned int) pud); - pmd = pmd_offset(pud, addr); - printk("pmd == %08x, ", (unsigned int) pmd); + pmd = pmd_offset(pud, addr); + printk("pmd == %08x, ", (unsigned int) pmd); - pte = pte_offset(pmd, addr); - printk("pte == %08x, ", (unsigned int) pte); - } else - printk("Current thread has no mm\n"); + pte = pte_offset(pmd, addr); + printk("pte == %08x, ", (unsigned int) pte); page = *pte; #ifdef CONFIG_64BIT_PHYS_ADDR diff --git a/arch/mips/math-emu/dp_simple.c b/arch/mips/math-emu/dp_simple.c index 495c1ac9429..1c555e6c6a9 100644 --- a/arch/mips/math-emu/dp_simple.c +++ b/arch/mips/math-emu/dp_simple.c @@ -48,16 +48,22 @@ ieee754dp ieee754dp_neg(ieee754dp x) CLEARCX; FLUSHXDP; + /* + * Invert the sign ALWAYS to prevent an endless recursion on + * pow() in libc. + */ + /* quick fix up */ + DPSIGN(x) ^= 1; + if (xc == IEEE754_CLASS_SNAN) { + ieee754dp y = ieee754dp_indef(); SETCX(IEEE754_INVALID_OPERATION); - return ieee754dp_nanxcpt(ieee754dp_indef(), "neg"); + DPSIGN(y) = DPSIGN(x); + return ieee754dp_nanxcpt(y, "neg"); } if (ieee754dp_isnan(x)) /* but not infinity */ return ieee754dp_nanxcpt(x, "neg", x); - - /* quick fix up */ - DPSIGN(x) ^= 1; return x; } diff --git a/arch/mips/math-emu/sp_simple.c b/arch/mips/math-emu/sp_simple.c index c809830dffb..770f0f4677c 100644 --- a/arch/mips/math-emu/sp_simple.c +++ b/arch/mips/math-emu/sp_simple.c @@ -48,16 +48,22 @@ ieee754sp ieee754sp_neg(ieee754sp x) CLEARCX; FLUSHXSP; + /* + * Invert the sign ALWAYS to prevent an endless recursion on + * pow() in libc. + */ + /* quick fix up */ + SPSIGN(x) ^= 1; + if (xc == IEEE754_CLASS_SNAN) { + ieee754sp y = ieee754sp_indef(); SETCX(IEEE754_INVALID_OPERATION); - return ieee754sp_nanxcpt(ieee754sp_indef(), "neg"); + SPSIGN(y) = SPSIGN(x); + return ieee754sp_nanxcpt(y, "neg"); } if (ieee754sp_isnan(x)) /* but not infinity */ return ieee754sp_nanxcpt(x, "neg", x); - - /* quick fix up */ - SPSIGN(x) ^= 1; return x; } diff --git a/arch/mips/mips-boards/generic/reset.c b/arch/mips/mips-boards/generic/reset.c index 9fdec743bd9..7213c395fb6 100644 --- a/arch/mips/mips-boards/generic/reset.c +++ b/arch/mips/mips-boards/generic/reset.c @@ -23,6 +23,7 @@ * */ #include <linux/config.h> +#include <linux/pm.h> #include <asm/io.h> #include <asm/reboot.h> @@ -65,9 +66,9 @@ void mips_reboot_setup(void) _machine_restart = mips_machine_restart; _machine_halt = mips_machine_halt; #if defined(CONFIG_MIPS_ATLAS) - _machine_power_off = atlas_machine_power_off; + pm_power_off = atlas_machine_power_off; #endif #if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_SEAD) - _machine_power_off = mips_machine_halt; + pm_power_off = mips_machine_halt; #endif } diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 422b55fab07..e51c38cef88 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -464,8 +464,8 @@ static void r4k_flush_data_cache_page(unsigned long addr) } struct flush_icache_range_args { - unsigned long __user start; - unsigned long __user end; + unsigned long start; + unsigned long end; }; static inline void local_r4k_flush_icache_range(void *args) @@ -528,8 +528,7 @@ static inline void local_r4k_flush_icache_range(void *args) } } -static void r4k_flush_icache_range(unsigned long __user start, - unsigned long __user end) +static void r4k_flush_icache_range(unsigned long start, unsigned long end) { struct flush_icache_range_args args; diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 314701a66b1..591c22b080e 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -25,8 +25,7 @@ void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start, unsigned long end); void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); -void (*flush_icache_range)(unsigned long __user start, - unsigned long __user end); +void (*flush_icache_range)(unsigned long start, unsigned long end); void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page); /* MIPS specific cache operations */ @@ -53,7 +52,7 @@ EXPORT_SYMBOL(_dma_cache_inv); * We could optimize the case where the cache argument is not BCACHE but * that seems very atypical use ... */ -asmlinkage int sys_cacheflush(unsigned long __user addr, +asmlinkage int sys_cacheflush(unsigned long addr, unsigned long bytes, unsigned int cache) { if (bytes == 0) diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 4ee91c9a556..0ff9a348b84 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -24,6 +24,7 @@ #include <linux/bootmem.h> #include <linux/highmem.h> #include <linux/swap.h> +#include <linux/proc_fs.h> #include <asm/bootinfo.h> #include <asm/cachectl.h> @@ -200,6 +201,11 @@ static inline int page_is_ram(unsigned long pagenr) return 0; } +static struct kcore_list kcore_mem, kcore_vmalloc; +#ifdef CONFIG_64BIT +static struct kcore_list kcore_kseg0; +#endif + void __init mem_init(void) { unsigned long codesize, reservedpages, datasize, initsize; @@ -249,6 +255,16 @@ void __init mem_init(void) datasize = (unsigned long) &_edata - (unsigned long) &_etext; initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin; +#ifdef CONFIG_64BIT + if ((unsigned long) &_text > (unsigned long) CKSEG0) + /* The -4 is a hack so that user tools don't have to handle + the overflow. */ + kclist_add(&kcore_kseg0, (void *) CKSEG0, 0x80000000 - 4); +#endif + kclist_add(&kcore_mem, __va(0), max_low_pfn << PAGE_SHIFT); + kclist_add(&kcore_vmalloc, (void *)VMALLOC_START, + VMALLOC_END-VMALLOC_START); + printk(KERN_INFO "Memory: %luk/%luk available (%ldk kernel code, " "%ldk reserved, %ldk data, %ldk init, %ldk highmem)\n", (unsigned long) nr_free_pages() << (PAGE_SHIFT-10), diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c index bab192ddc18..301d67226d7 100644 --- a/arch/mips/momentum/jaguar_atx/setup.c +++ b/arch/mips/momentum/jaguar_atx/setup.c @@ -50,6 +50,7 @@ #include <linux/pci.h> #include <linux/swap.h> #include <linux/ioport.h> +#include <linux/pm.h> #include <linux/sched.h> #include <linux/interrupt.h> #include <linux/timex.h> @@ -365,7 +366,7 @@ void __init plat_setup(void) _machine_restart = momenco_jaguar_restart; _machine_halt = momenco_jaguar_halt; - _machine_power_off = momenco_jaguar_power_off; + pm_power_off = momenco_jaguar_power_off; /* * initrd_start = (ulong)jaguar_initrd_start; diff --git a/arch/mips/momentum/ocelot_3/setup.c b/arch/mips/momentum/ocelot_3/setup.c index c9b7ff8148e..f95677f4f06 100644 --- a/arch/mips/momentum/ocelot_3/setup.c +++ b/arch/mips/momentum/ocelot_3/setup.c @@ -57,6 +57,8 @@ #include <linux/timex.h> #include <linux/bootmem.h> #include <linux/mv643xx.h> +#include <linux/pm.h> + #include <asm/time.h> #include <asm/page.h> #include <asm/bootinfo.h> @@ -321,7 +323,7 @@ void __init plat_setup(void) _machine_restart = momenco_ocelot_restart; _machine_halt = momenco_ocelot_halt; - _machine_power_off = momenco_ocelot_power_off; + pm_power_off = momenco_ocelot_power_off; /* Wired TLB entries */ setup_wired_tlb_entries(); diff --git a/arch/mips/momentum/ocelot_c/setup.c b/arch/mips/momentum/ocelot_c/setup.c index 2755c154747..15998d8a934 100644 --- a/arch/mips/momentum/ocelot_c/setup.c +++ b/arch/mips/momentum/ocelot_c/setup.c @@ -51,8 +51,10 @@ #include <linux/sched.h> #include <linux/interrupt.h> #include <linux/pci.h> +#include <linux/pm.h> #include <linux/timex.h> #include <linux/vmalloc.h> + #include <asm/time.h> #include <asm/bootinfo.h> #include <asm/page.h> @@ -236,7 +238,7 @@ void __init plat_setup(void) _machine_restart = momenco_ocelot_restart; _machine_halt = momenco_ocelot_halt; - _machine_power_off = momenco_ocelot_power_off; + pm_power_off = momenco_ocelot_power_off; /* * initrd_start = (ulong)ocelot_initrd_start; diff --git a/arch/mips/momentum/ocelot_g/setup.c b/arch/mips/momentum/ocelot_g/setup.c index 6336751391c..fed4e8eee11 100644 --- a/arch/mips/momentum/ocelot_g/setup.c +++ b/arch/mips/momentum/ocelot_g/setup.c @@ -47,8 +47,10 @@ #include <linux/sched.h> #include <linux/interrupt.h> #include <linux/pci.h> +#include <linux/pm.h> #include <linux/timex.h> #include <linux/vmalloc.h> + #include <asm/time.h> #include <asm/bootinfo.h> #include <asm/page.h> @@ -169,7 +171,7 @@ void __init plat_setup(void) _machine_restart = momenco_ocelot_restart; _machine_halt = momenco_ocelot_halt; - _machine_power_off = momenco_ocelot_power_off; + pm_power_off = momenco_ocelot_power_off; /* * initrd_start = (ulong)ocelot_initrd_start; diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile index 354261d37d6..0a50aad5bbe 100644 --- a/arch/mips/oprofile/Makefile +++ b/arch/mips/oprofile/Makefile @@ -12,4 +12,5 @@ oprofile-y := $(DRIVER_OBJS) common.o oprofile-$(CONFIG_CPU_MIPS32) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o +oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index 53f9889b30e..935dd851f48 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c @@ -79,6 +79,9 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) case CPU_20KC: case CPU_24K: case CPU_25KF: + case CPU_34K: + case CPU_SB1: + case CPU_SB1A: lmodel = &op_model_mipsxx; break; diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 1d1eee407fa..95d488ca075 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -201,10 +201,21 @@ static int __init mipsxx_init(void) op_model_mipsxx.cpu_type = "mips/25K"; break; +#ifndef CONFIG_SMP + case CPU_34K: + op_model_mipsxx.cpu_type = "mips/34K"; + break; +#endif + case CPU_5KC: op_model_mipsxx.cpu_type = "mips/5K"; break; + case CPU_SB1: + case CPU_SB1A: + op_model_mipsxx.cpu_type = "mips/sb1"; + break; + default: printk(KERN_ERR "Profiling unsupported for this CPU\n"); diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 741e67c9195..16205b58733 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \ obj-$(CONFIG_SGI_IP27) += pci-ip27.o obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o +obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o obj-$(CONFIG_SNI_RM200_PCI) += fixup-sni.o ops-sni.o obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c index 909292f50d0..75a01e76489 100644 --- a/arch/mips/pci/fixup-cobalt.c +++ b/arch/mips/pci/fixup-cobalt.c @@ -17,7 +17,7 @@ #include <asm/io.h> #include <asm/gt64120.h> -#include <asm/cobalt/cobalt.h> +#include <asm/mach-cobalt/cobalt.h> extern int cobalt_board_id; @@ -52,7 +52,7 @@ static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev) pci_read_config_byte(dev, PCI_LATENCY_TIMER, <); if (lt < 64) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); - pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7); + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, @@ -69,7 +69,7 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev) * host bridge. */ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); - pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7); + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); /* * The code described by the comment below has been removed diff --git a/arch/mips/pci/ops-gt64111.c b/arch/mips/pci/ops-gt64111.c index c1807934768..13de45940b1 100644 --- a/arch/mips/pci/ops-gt64111.c +++ b/arch/mips/pci/ops-gt64111.c @@ -15,7 +15,7 @@ #include <asm/io.h> #include <asm/gt64120.h> -#include <asm/cobalt/cobalt.h> +#include <asm/mach-cobalt/cobalt.h> /* * Device 31 on the GT64111 is used to generate PCI special diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c index f194b4e4f86..ca975e7d32f 100644 --- a/arch/mips/pci/pci-bcm1480.c +++ b/arch/mips/pci/pci-bcm1480.c @@ -234,11 +234,9 @@ static int __init bcm1480_pcibios_init(void) /* turn on ExpMemEn */ cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40)); - printk("PCIFeatureCtrl = %x\n", cmdreg); WRITECFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40), cmdreg | 0x10); cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40)); - printk("PCIFeatureCtrl = %x\n", cmdreg); /* * Establish mappings in KSEG2 (kernel virtual) to PCI I/O diff --git a/arch/mips/philips/pnx8550/common/setup.c b/arch/mips/philips/pnx8550/common/setup.c index ee6bf72094f..0d8a7761939 100644 --- a/arch/mips/philips/pnx8550/common/setup.c +++ b/arch/mips/philips/pnx8550/common/setup.c @@ -25,6 +25,7 @@ #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/serial_ip3106.h> +#include <linux/pm.h> #include <asm/cpu.h> #include <asm/bootinfo.h> @@ -90,7 +91,7 @@ void __init plat_setup(void) _machine_restart = pnx8550_machine_restart; _machine_halt = pnx8550_machine_halt; - _machine_power_off = pnx8550_machine_power_off; + pm_power_off = pnx8550_machine_power_off; board_time_init = pnx8550_time_init; board_timer_setup = pnx8550_timer_setup; diff --git a/arch/mips/pmc-sierra/yosemite/prom.c b/arch/mips/pmc-sierra/yosemite/prom.c index 555bfacf764..165275c00cb 100644 --- a/arch/mips/pmc-sierra/yosemite/prom.c +++ b/arch/mips/pmc-sierra/yosemite/prom.c @@ -13,6 +13,7 @@ #include <linux/sched.h> #include <linux/mm.h> #include <linux/delay.h> +#include <linux/pm.h> #include <linux/smp.h> #include <asm/io.h> @@ -92,7 +93,7 @@ void __init prom_init(void) /* Callbacks for halt, restart */ _machine_restart = (void (*)(char *)) prom_exit; _machine_halt = prom_halt; - _machine_power_off = prom_halt; + pm_power_off = prom_halt; debug_vectors = cv; arcs_cmdline[0] = '\0'; diff --git a/arch/mips/sgi-ip22/ip22-reset.c b/arch/mips/sgi-ip22/ip22-reset.c index 214ffd2e98a..92a3b3c15ed 100644 --- a/arch/mips/sgi-ip22/ip22-reset.c +++ b/arch/mips/sgi-ip22/ip22-reset.c @@ -3,8 +3,9 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1997, 1998, 2001, 2003 by Ralf Baechle + * Copyright (C) 1997, 1998, 2001, 03, 05, 06 by Ralf Baechle */ +#include <linux/linkage.h> #include <linux/init.h> #include <linux/ds1286.h> #include <linux/module.h> @@ -12,6 +13,7 @@ #include <linux/kernel.h> #include <linux/sched.h> #include <linux/notifier.h> +#include <linux/pm.h> #include <linux/timer.h> #include <asm/io.h> @@ -41,28 +43,10 @@ static struct timer_list power_timer, blink_timer, debounce_timer, volume_timer; #define MACHINE_PANICED 1 #define MACHINE_SHUTTING_DOWN 2 -static int machine_state = 0; -static void sgi_machine_restart(char *command) __attribute__((noreturn)); -static void sgi_machine_halt(void) __attribute__((noreturn)); -static void sgi_machine_power_off(void) __attribute__((noreturn)); +static int machine_state; -static void sgi_machine_restart(char *command) -{ - if (machine_state & MACHINE_SHUTTING_DOWN) - sgi_machine_power_off(); - sgimc->cpuctrl0 |= SGIMC_CCTRL0_SYSINIT; - while (1); -} - -static void sgi_machine_halt(void) -{ - if (machine_state & MACHINE_SHUTTING_DOWN) - sgi_machine_power_off(); - ArcEnterInteractiveMode(); -} - -static void sgi_machine_power_off(void) +static void ATTRIB_NORET sgi_machine_power_off(void) { unsigned int tmp; @@ -84,6 +68,21 @@ static void sgi_machine_power_off(void) } } +static void ATTRIB_NORET sgi_machine_restart(char *command) +{ + if (machine_state & MACHINE_SHUTTING_DOWN) + sgi_machine_power_off(); + sgimc->cpuctrl0 |= SGIMC_CCTRL0_SYSINIT; + while (1); +} + +static void ATTRIB_NORET sgi_machine_halt(void) +{ + if (machine_state & MACHINE_SHUTTING_DOWN) + sgi_machine_power_off(); + ArcEnterInteractiveMode(); +} + static void power_timeout(unsigned long data) { sgi_machine_power_off(); @@ -95,7 +94,7 @@ static void blink_timeout(unsigned long data) sgi_ioc_reset ^= (SGIOC_RESET_LC0OFF|SGIOC_RESET_LC1OFF); sgioc->reset = sgi_ioc_reset; - mod_timer(&blink_timer, jiffies+data); + mod_timer(&blink_timer, jiffies + data); } static void debounce(unsigned long data) @@ -103,7 +102,7 @@ static void debounce(unsigned long data) del_timer(&debounce_timer); if (sgint->istat1 & SGINT_ISTAT1_PWR) { /* Interrupt still being sent. */ - debounce_timer.expires = jiffies + 5; /* 0.05s */ + debounce_timer.expires = jiffies + (HZ / 20); /* 0.05s */ add_timer(&debounce_timer); sgioc->panel = SGIOC_PANEL_POWERON | SGIOC_PANEL_POWERINTR | @@ -151,7 +150,7 @@ static inline void volume_up_button(unsigned long data) indy_volume_button(1); if (sgint->istat1 & SGINT_ISTAT1_PWR) { - volume_timer.expires = jiffies + 1; + volume_timer.expires = jiffies + (HZ / 100); add_timer(&volume_timer); } } @@ -164,7 +163,7 @@ static inline void volume_down_button(unsigned long data) indy_volume_button(-1); if (sgint->istat1 & SGINT_ISTAT1_PWR) { - volume_timer.expires = jiffies + 1; + volume_timer.expires = jiffies + (HZ / 100); add_timer(&volume_timer); } } @@ -199,14 +198,14 @@ static irqreturn_t panel_int(int irq, void *dev_id, struct pt_regs *regs) if (!(buttons & SGIOC_PANEL_VOLUPINTR)) { init_timer(&volume_timer); volume_timer.function = volume_up_button; - volume_timer.expires = jiffies + 1; + volume_timer.expires = jiffies + (HZ / 100); add_timer(&volume_timer); } /* Volume down button was pressed */ if (!(buttons & SGIOC_PANEL_VOLDNINTR)) { init_timer(&volume_timer); volume_timer.function = volume_down_button; - volume_timer.expires = jiffies + 1; + volume_timer.expires = jiffies + (HZ / 100); add_timer(&volume_timer); } @@ -234,7 +233,7 @@ static int __init reboot_setup(void) { _machine_restart = sgi_machine_restart; _machine_halt = sgi_machine_halt; - _machine_power_off = sgi_machine_power_off; + pm_power_off = sgi_machine_power_off; request_irq(SGI_PANEL_IRQ, panel_int, 0, "Front Panel", NULL); init_timer(&blink_timer); diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c index 5e59b4c8876..7018e1833e8 100644 --- a/arch/mips/sgi-ip22/ip22-setup.c +++ b/arch/mips/sgi-ip22/ip22-setup.c @@ -56,6 +56,7 @@ extern void ip22_time_init(void) __init; void __init plat_setup(void) { char *ctype; + char *cserial; board_be_init = ip22_be_init; ip22_time_init(); @@ -81,9 +82,14 @@ void __init plat_setup(void) /* ARCS console environment variable is set to "g?" for * graphics console, it is set to "d" for the first serial * line and "d2" for the second serial line. + * + * Need to check if the case is 'g' but no keyboard: + * (ConsoleIn/Out = serial) */ ctype = ArcGetEnvironmentVariable("console"); - if (ctype && *ctype == 'd') { + cserial = ArcGetEnvironmentVariable("ConsoleOut"); + + if ((ctype && *ctype == 'd') || (cserial && *cserial == 's')) { static char options[8]; char *baud = ArcGetEnvironmentVariable("dbaud"); if (baud) @@ -91,7 +97,7 @@ void __init plat_setup(void) add_preferred_console("ttyS", *(ctype + 1) == '2' ? 1 : 0, baud ? options : NULL); } else if (!ctype || *ctype != 'g') { - /* Use ARC if we don't want serial ('d') or Newport ('g'). */ + /* Use ARC if we don't want serial ('d') or graphics ('g'). */ prom_flags |= PROM_FLAG_USE_AS_CONSOLE; add_preferred_console("arc", 0, NULL); } diff --git a/arch/mips/sgi-ip27/ip27-reset.c b/arch/mips/sgi-ip27/ip27-reset.c index 2e16be94c78..4322db57d3c 100644 --- a/arch/mips/sgi-ip27/ip27-reset.c +++ b/arch/mips/sgi-ip27/ip27-reset.c @@ -5,7 +5,7 @@ * * Reset an IP27. * - * Copyright (C) 1997, 1998, 1999, 2000 by Ralf Baechle + * Copyright (C) 1997, 1998, 1999, 2000, 06 by Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ #include <linux/config.h> @@ -15,6 +15,7 @@ #include <linux/smp.h> #include <linux/mmzone.h> #include <linux/nodemask.h> +#include <linux/pm.h> #include <asm/io.h> #include <asm/irq.h> @@ -77,5 +78,5 @@ void ip27_reboot_setup(void) { _machine_restart = ip27_machine_restart; _machine_halt = ip27_machine_halt; - _machine_power_off = ip27_machine_power_off; + pm_power_off = ip27_machine_power_off; } diff --git a/arch/mips/sgi-ip32/ip32-reset.c b/arch/mips/sgi-ip32/ip32-reset.c index 88e1f52059f..0c948008b02 100644 --- a/arch/mips/sgi-ip32/ip32-reset.c +++ b/arch/mips/sgi-ip32/ip32-reset.c @@ -15,6 +15,7 @@ #include <linux/delay.h> #include <linux/ds17287rtc.h> #include <linux/interrupt.h> +#include <linux/pm.h> #include <asm/addrspace.h> #include <asm/irq.h> @@ -188,7 +189,7 @@ static __init int ip32_reboot_setup(void) _machine_restart = ip32_machine_restart; _machine_halt = ip32_machine_halt; - _machine_power_off = ip32_machine_power_off; + pm_power_off = ip32_machine_power_off; init_timer(&blink_timer); blink_timer.function = blink_timeout; diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c index 7a2c7a8510d..ea308029450 100644 --- a/arch/mips/sibyte/cfe/setup.c +++ b/arch/mips/sibyte/cfe/setup.c @@ -23,6 +23,7 @@ #include <linux/mm.h> #include <linux/blkdev.h> #include <linux/bootmem.h> +#include <linux/pm.h> #include <linux/smp.h> #include <asm/bootinfo.h> @@ -248,7 +249,7 @@ void __init prom_init(void) _machine_restart = cfe_linux_restart; _machine_halt = cfe_linux_halt; - _machine_power_off = cfe_linux_halt; + pm_power_off = cfe_linux_halt; /* * Check if a loader was used; if NOT, the 4 arguments are diff --git a/arch/mips/sibyte/sb1250/prom.c b/arch/mips/sibyte/sb1250/prom.c index de62ab0f55a..742043f8d75 100644 --- a/arch/mips/sibyte/sb1250/prom.c +++ b/arch/mips/sibyte/sb1250/prom.c @@ -24,6 +24,7 @@ #include <linux/bootmem.h> #include <linux/smp.h> #include <linux/initrd.h> +#include <linux/pm.h> #include <asm/bootinfo.h> #include <asm/reboot.h> @@ -79,7 +80,7 @@ void __init prom_init(void) { _machine_restart = (void (*)(char *))prom_linux_exit; _machine_halt = prom_linux_exit; - _machine_power_off = prom_linux_exit; + pm_power_off = prom_linux_exit; strcpy(arcs_cmdline, "root=/dev/ram0 "); diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c index df2e266c700..fde4751c84f 100644 --- a/arch/mips/sibyte/sb1250/setup.c +++ b/arch/mips/sibyte/sb1250/setup.c @@ -16,6 +16,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include <linux/config.h> +#include <linux/init.h> #include <linux/kernel.h> #include <linux/reboot.h> #include <linux/string.h> @@ -42,7 +43,7 @@ static inline int setup_bcm112x(void); /* Setup code likely to be common to all SiByte platforms */ -static inline int sys_rev_decode(void) +static int __init sys_rev_decode(void) { int ret = 0; @@ -74,7 +75,7 @@ static inline int sys_rev_decode(void) return ret; } -static inline int setup_bcm1250(void) +static int __init setup_bcm1250(void) { int ret = 0; @@ -120,7 +121,7 @@ static inline int setup_bcm1250(void) return ret; } -static inline int setup_bcm112x(void) +static int __init setup_bcm112x(void) { int ret = 0; @@ -146,7 +147,7 @@ static inline int setup_bcm112x(void) return ret; } -void sb1250_setup(void) +void __init sb1250_setup(void) { uint64_t sys_rev; int plldiv; @@ -169,31 +170,42 @@ void sb1250_setup(void) soc_str, pass_str, zbbus_mhz * 2, sb1_pass); prom_printf("Board type: %s\n", get_system_type()); - switch(war_pass) { + switch (war_pass) { case K_SYS_REVISION_BCM1250_PASS1: #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS - prom_printf("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n"); + prom_printf("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, " + "and the kernel doesn't have the proper " + "workarounds compiled in. @@@@\n"); bad_config = 1; #endif break; case K_SYS_REVISION_BCM1250_PASS2: /* Pass 2 - easiest as default for now - so many numbers */ -#if !defined(CONFIG_SB1_PASS_2_WORKAROUNDS) || !defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) - prom_printf("@@@@ This is a BCM1250 A3-A10 board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n"); +#if !defined(CONFIG_SB1_PASS_2_WORKAROUNDS) || \ + !defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) + prom_printf("@@@@ This is a BCM1250 A3-A10 board, and the " + "kernel doesn't have the proper workarounds " + "compiled in. @@@@\n"); bad_config = 1; #endif #ifdef CONFIG_CPU_HAS_PREFETCH - prom_printf("@@@@ Prefetches may be enabled in this kernel, but are buggy on this board. @@@@\n"); + prom_printf("@@@@ Prefetches may be enabled in this kernel, " + "but are buggy on this board. @@@@\n"); bad_config = 1; #endif break; case K_SYS_REVISION_BCM1250_PASS2_2: #ifndef CONFIG_SB1_PASS_2_WORKAROUNDS - prom_printf("@@@@ This is a BCM1250 B1/B2. board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n"); + prom_printf("@@@@ This is a BCM1250 B1/B2. board, and the " + "kernel doesn't have the proper workarounds " + "compiled in. @@@@\n"); bad_config = 1; #endif -#if defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) || !defined(CONFIG_CPU_HAS_PREFETCH) - prom_printf("@@@@ This is a BCM1250 B1/B2, but the kernel is conservatively configured for an 'A' stepping. @@@@\n"); +#if defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) || \ + !defined(CONFIG_CPU_HAS_PREFETCH) + prom_printf("@@@@ This is a BCM1250 B1/B2, but the kernel is " + "conservatively configured for an 'A' stepping. " + "@@@@\n"); #endif break; default: diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c index 262c8568070..1141fcd13a5 100644 --- a/arch/mips/sni/setup.c +++ b/arch/mips/sni/setup.c @@ -5,7 +5,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996, 97, 98, 2000, 03, 04 Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 1996, 97, 98, 2000, 03, 04, 06 Ralf Baechle (ralf@linux-mips.org) */ #include <linux/config.h> #include <linux/eisa.h> @@ -15,6 +15,7 @@ #include <linux/init.h> #include <linux/interrupt.h> #include <linux/mc146818rtc.h> +#include <linux/pm.h> #include <linux/pci.h> #include <linux/console.h> #include <linux/fb.h> @@ -189,7 +190,7 @@ void __init plat_setup(void) _machine_restart = sni_machine_restart; _machine_halt = sni_machine_halt; - _machine_power_off = sni_machine_power_off; + pm_power_off = sni_machine_power_off; sni_display_setup(); diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c index e4d095d3e19..e19e2be70f7 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c @@ -60,7 +60,6 @@ void __init prom_init_cmdline(void) void __init prom_init(void) { - const char* toshiba_name_list[] = GROUP_TOSHIBA_NAMES; extern int tx4927_get_mem_size(void); extern char* toshiba_name; int msize; @@ -69,12 +68,13 @@ void __init prom_init(void) mips_machgroup = MACH_GROUP_TOSHIBA; - if ((read_c0_prid() & 0xff) == PRID_REV_TX4927) + if ((read_c0_prid() & 0xff) == PRID_REV_TX4927) { mips_machtype = MACH_TOSHIBA_RBTX4927; - else + toshiba_name = "TX4927"; + } else { mips_machtype = MACH_TOSHIBA_RBTX4937; - - toshiba_name = toshiba_name_list[mips_machtype]; + toshiba_name = "TX4937"; + } msize = tx4927_get_mem_size(); add_memory_region(0, msize << 20, BOOT_MEM_RAM); diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c index 990fcb294ba..2ad6401d2af 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c @@ -53,6 +53,8 @@ #include <linux/interrupt.h> #include <linux/pci.h> #include <linux/timex.h> +#include <linux/pm.h> + #include <asm/bootinfo.h> #include <asm/page.h> #include <asm/io.h> @@ -537,19 +539,10 @@ void tx4927_pci_setup(void) TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "0x%08lx=mips_io_port_base", mips_io_port_base); - - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "setup pci_io_resource to 0x%08lx 0x%08lx\n", - pci_io_resource.start, - pci_io_resource.end); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, - "setup pci_mem_resource to 0x%08lx 0x%08lx\n", - pci_mem_resource.start, - pci_mem_resource.end); - if (!called) { printk - ("TX4927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", + ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", + toshiba_name, (unsigned short) (tx4927_pcicptr->pciid >> 16), (unsigned short) (tx4927_pcicptr->pciid & 0xffff), (unsigned short) (tx4927_pcicptr->pciccrev & 0xff), @@ -562,21 +555,52 @@ void tx4927_pci_setup(void) (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : ""); if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) { int pciclk = 0; - switch ((unsigned long) tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { - case TX4927_CCFG_PCIDIVMODE_2_5: - pciclk = tx4927_cpu_clock * 2 / 5; - break; - case TX4927_CCFG_PCIDIVMODE_3: - pciclk = tx4927_cpu_clock / 3; - break; - case TX4927_CCFG_PCIDIVMODE_5: - pciclk = tx4927_cpu_clock / 5; - break; - case TX4927_CCFG_PCIDIVMODE_6: - pciclk = tx4927_cpu_clock / 6; - break; - } + if (mips_machtype == MACH_TOSHIBA_RBTX4937) + switch ((unsigned long) tx4927_ccfgptr-> + ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { + case TX4937_CCFG_PCIDIVMODE_4: + pciclk = tx4927_cpu_clock / 4; + break; + case TX4937_CCFG_PCIDIVMODE_4_5: + pciclk = tx4927_cpu_clock * 2 / 9; + break; + case TX4937_CCFG_PCIDIVMODE_5: + pciclk = tx4927_cpu_clock / 5; + break; + case TX4937_CCFG_PCIDIVMODE_5_5: + pciclk = tx4927_cpu_clock * 2 / 11; + break; + case TX4937_CCFG_PCIDIVMODE_8: + pciclk = tx4927_cpu_clock / 8; + break; + case TX4937_CCFG_PCIDIVMODE_9: + pciclk = tx4927_cpu_clock / 9; + break; + case TX4937_CCFG_PCIDIVMODE_10: + pciclk = tx4927_cpu_clock / 10; + break; + case TX4937_CCFG_PCIDIVMODE_11: + pciclk = tx4927_cpu_clock / 11; + break; + } + + else + switch ((unsigned long) tx4927_ccfgptr-> + ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { + case TX4927_CCFG_PCIDIVMODE_2_5: + pciclk = tx4927_cpu_clock * 2 / 5; + break; + case TX4927_CCFG_PCIDIVMODE_3: + pciclk = tx4927_cpu_clock / 3; + break; + case TX4927_CCFG_PCIDIVMODE_5: + pciclk = tx4927_cpu_clock / 5; + break; + case TX4927_CCFG_PCIDIVMODE_6: + pciclk = tx4927_cpu_clock / 6; + break; + } + printk("Internal(%dMHz)", pciclk / 1000000); } else { int pciclk = 0; @@ -814,24 +838,40 @@ void __init toshiba_rbtx4927_setup(void) ":ResetRoutines\n"); _machine_restart = toshiba_rbtx4927_restart; _machine_halt = toshiba_rbtx4927_halt; - _machine_power_off = toshiba_rbtx4927_power_off; + pm_power_off = toshiba_rbtx4927_power_off; #ifdef CONFIG_PCI /* PCIC */ /* * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. - * PCIDIVMODE[12:11]'s initial value are given by S9[4:3] (ON:0, OFF:1). + * + * For TX4927: + * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1). * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) * i.e. S9[3]: ON (83MHz), OFF (100MHz) + * + * For TX4937: + * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1) + * PCIDIVMODE[10] is 0. + * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8) + * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4) + * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9) + * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5) + * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10) + * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5) + * */ TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1, - "ccfg is %lx, DIV is %x\n", - (unsigned long) tx4927_ccfgptr-> - ccfg, TX4927_CCFG_PCIDIVMODE_MASK); + "ccfg is %lx, PCIDIVMODE is %x\n", + (unsigned long) tx4927_ccfgptr->ccfg, + (unsigned long) tx4927_ccfgptr->ccfg & + (mips_machtype == MACH_TOSHIBA_RBTX4937 ? + TX4937_CCFG_PCIDIVMODE_MASK : + TX4927_CCFG_PCIDIVMODE_MASK)); TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1, "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n", @@ -842,20 +882,30 @@ void __init toshiba_rbtx4927_setup(void) (unsigned long) tx4927_ccfgptr-> ccfg & TX4927_CCFG_PCIXARB); - TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1, - "PCIDIVMODE is %lx\n", - (unsigned long) tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIDIVMODE_MASK); - - switch ((unsigned long) tx4927_ccfgptr-> - ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { - case TX4927_CCFG_PCIDIVMODE_2_5: - case TX4927_CCFG_PCIDIVMODE_5: - tx4927_cpu_clock = 166000000; /* 166MHz */ - break; - default: - tx4927_cpu_clock = 200000000; /* 200MHz */ - } + if (mips_machtype == MACH_TOSHIBA_RBTX4937) + switch ((unsigned long)tx4927_ccfgptr-> + ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { + case TX4937_CCFG_PCIDIVMODE_8: + case TX4937_CCFG_PCIDIVMODE_4: + tx4927_cpu_clock = 266666666; /* 266MHz */ + break; + case TX4937_CCFG_PCIDIVMODE_9: + case TX4937_CCFG_PCIDIVMODE_4_5: + tx4927_cpu_clock = 300000000; /* 300MHz */ + break; + default: + tx4927_cpu_clock = 333333333; /* 333MHz */ + } + else + switch ((unsigned long)tx4927_ccfgptr-> + ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { + case TX4927_CCFG_PCIDIVMODE_2_5: + case TX4927_CCFG_PCIDIVMODE_5: + tx4927_cpu_clock = 166666666; /* 166MHz */ + break; + default: + tx4927_cpu_clock = 200000000; /* 200MHz */ + } /* CCFG */ /* enable Timeout BusError */ diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c index 9f1dcc8ca5a..5c7ace982a4 100644 --- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c +++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c @@ -20,6 +20,8 @@ #include <linux/interrupt.h> #include <linux/console.h> #include <linux/pci.h> +#include <linux/pm.h> + #include <asm/wbflush.h> #include <asm/reboot.h> #include <asm/irq.h> @@ -1003,7 +1005,7 @@ void __init toshiba_rbtx4938_setup(void) _machine_restart = rbtx4938_machine_restart; _machine_halt = rbtx4938_machine_halt; - _machine_power_off = rbtx4938_machine_power_off; + pm_power_off = rbtx4938_machine_power_off; *rbtx4938_led_ptr = 0xff; printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr); diff --git a/arch/mips/vr41xx/common/pmu.c b/arch/mips/vr41xx/common/pmu.c index 02bf4f7d06b..5e469796413 100644 --- a/arch/mips/vr41xx/common/pmu.c +++ b/arch/mips/vr41xx/common/pmu.c @@ -21,6 +21,7 @@ #include <linux/init.h> #include <linux/ioport.h> #include <linux/kernel.h> +#include <linux/pm.h> #include <linux/smp.h> #include <linux/types.h> @@ -114,7 +115,7 @@ static int __init vr41xx_pmu_init(void) _machine_restart = vr41xx_restart; _machine_halt = vr41xx_halt; - _machine_power_off = vr41xx_power_off; + pm_power_off = vr41xx_power_off; return 0; } diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 3b0c8aaf6e8..8e802059fe6 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -644,20 +644,26 @@ static inline unsigned long ffz(unsigned long word) } /* - * flz - find last zero in word. + * fls - find last bit set. * @word: The word to search * - * Returns 0..SZLONG-1 - * Undefined if no zero exists, so code should check against ~0UL first. + * Returns 1..SZLONG + * Returns 0 if no bit exists */ -static inline unsigned long flz(unsigned long word) +static inline unsigned long fls(unsigned long word) { -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - return __ilog2(~word); -#else #ifdef CONFIG_32BIT - int r = 31, s; - word = ~word; +#ifdef CONFIG_CPU_MIPS32 + __asm__ ("clz %0, %1" : "=r" (word) : "r" (word)); + + return 32 - word; +#else + { + int r = 32, s; + + if (word == 0) + return 0; + s = 16; if ((word & 0xffff0000)) s = 0; r -= s; word <<= s; s = 8; if ((word & 0xff000000)) s = 0; r -= s; word <<= s; s = 4; if ((word & 0xf0000000)) s = 0; r -= s; word <<= s; @@ -665,10 +671,23 @@ static inline unsigned long flz(unsigned long word) s = 1; if ((word & 0x80000000)) s = 0; r -= s; return r; + } #endif +#endif /* CONFIG_32BIT */ + #ifdef CONFIG_64BIT - int r = 63, s; - word = ~word; +#ifdef CONFIG_CPU_MIPS64 + + __asm__ ("dclz %0, %1" : "=r" (word) : "r" (word)); + + return 64 - word; +#else + { + int r = 64, s; + + if (word == 0) + return 0; + s = 32; if ((word & 0xffffffff00000000UL)) s = 0; r -= s; word <<= s; s = 16; if ((word & 0xffff000000000000UL)) s = 0; r -= s; word <<= s; s = 8; if ((word & 0xff00000000000000UL)) s = 0; r -= s; word <<= s; @@ -677,24 +696,11 @@ static inline unsigned long flz(unsigned long word) s = 1; if ((word & 0x8000000000000000UL)) s = 0; r -= s; return r; + } #endif -#endif +#endif /* CONFIG_64BIT */ } -/* - * fls - find last bit set. - * @word: The word to search - * - * Returns 1..SZLONG - * Returns 0 if no bit exists - */ -static inline unsigned long fls(unsigned long word) -{ - if (word == 0) - return 0; - - return flz(~word) + 1; -} #define fls64(x) generic_fls64(x) /* diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h index d1fe9e5c62e..584f8128fff 100644 --- a/include/asm-mips/byteorder.h +++ b/include/asm-mips/byteorder.h @@ -8,10 +8,39 @@ #ifndef _ASM_BYTEORDER_H #define _ASM_BYTEORDER_H +#include <linux/config.h> +#include <linux/compiler.h> #include <asm/types.h> #ifdef __GNUC__ +#ifdef CONFIG_CPU_MIPSR2 + +static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) +{ + __asm__( + " wsbh %0, %1 \n" + : "=r" (x) + : "r" (x)); + + return x; +} +#define __arch__swab16(x) ___arch__swab16(x) + +static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) +{ + __asm__( + " wsbh %0, %1 \n" + " rotr %0, %0, 16 \n" + : "=r" (x) + : "r" (x)); + + return x; +} +#define __arch__swab32(x) ___arch__swab32(x) + +#endif /* CONFIG_CPU_MIPSR2 */ + #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) # define __BYTEORDER_HAS_U64__ # define __SWAB_64_THRU_32__ diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h index a18ba2edc0b..aeae9fabf4a 100644 --- a/include/asm-mips/cacheflush.h +++ b/include/asm-mips/cacheflush.h @@ -49,8 +49,7 @@ static inline void flush_dcache_page(struct page *page) extern void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page); -extern void (*flush_icache_range)(unsigned long __user start, - unsigned long __user end); +extern void (*flush_icache_range)(unsigned long start, unsigned long end); #define flush_cache_vmap(start, end) flush_cache_all() #define flush_cache_vunmap(start, end) flush_cache_all() diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index 2fc90632f88..6111a0ce58c 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -100,7 +100,7 @@ __asm__( " .macro _ssnop \n\t" - " sll $0, $2, 1 \n\t" + " sll $0, $0, 1 \n\t" " .endm \n\t" " \n\t" " .macro _ehb \n\t" diff --git a/include/asm-mips/interrupt.h b/include/asm-mips/interrupt.h index abdf54ee64c..774348734fa 100644 --- a/include/asm-mips/interrupt.h +++ b/include/asm-mips/interrupt.h @@ -47,6 +47,17 @@ static inline void local_irq_enable(void) * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs * no nops at all. */ +/* + * For TX49, operating only IE bit is not enough. + * + * If mfc0 $12 follows store and the mfc0 is last instruction of a + * page and fetching the next instruction causes TLB miss, the result + * of the mfc0 might wrongly contain EXL bit. + * + * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008 + * + * Workaround: mask EXL bit of the result or place a nop before mfc0. + */ __asm__ ( " .macro local_irq_disable\n" " .set push \n" @@ -55,8 +66,8 @@ __asm__ ( " di \n" #else " mfc0 $1,$12 \n" - " ori $1,1 \n" - " xori $1,1 \n" + " ori $1,0x1f \n" + " xori $1,0x1f \n" " .set noreorder \n" " mtc0 $1,$12 \n" #endif @@ -96,8 +107,8 @@ __asm__ ( " andi \\result, 1 \n" #else " mfc0 \\result, $12 \n" - " ori $1, \\result, 1 \n" - " xori $1, 1 \n" + " ori $1, \\result, 0x1f \n" + " xori $1, 0x1f \n" " .set noreorder \n" " mtc0 $1, $12 \n" #endif @@ -114,6 +125,7 @@ __asm__ __volatile__( \ __asm__ ( " .macro local_irq_restore flags \n" + " .set push \n" " .set noreorder \n" " .set noat \n" #if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) @@ -135,14 +147,13 @@ __asm__ ( #else " mfc0 $1, $12 \n" " andi \\flags, 1 \n" - " ori $1, 1 \n" - " xori $1, 1 \n" + " ori $1, 0x1f \n" + " xori $1, 0x1f \n" " or \\flags, $1 \n" " mtc0 \\flags, $12 \n" #endif " irq_disable_hazard \n" - " .set at \n" - " .set reorder \n" + " .set pop \n" " .endm \n"); #define local_irq_restore(flags) \ diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 8e1d7ed7d8e..4686e17c206 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -1198,7 +1198,11 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; /* UARTS 0-3 */ #define UART_BASE UART0_ADDR +#ifdef CONFIG_SOC_AU1200 +#define UART_DEBUG_BASE UART1_ADDR +#else #define UART_DEBUG_BASE UART3_ADDR +#endif #define UART_RX 0 /* Receive buffer */ #define UART_TX 4 /* Transmit buffer */ diff --git a/include/asm-mips/cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h index 78e1df2095f..78e1df2095f 100644 --- a/include/asm-mips/cobalt/cobalt.h +++ b/include/asm-mips/mach-cobalt/cobalt.h diff --git a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h new file mode 100644 index 00000000000..ace8c5ef970 --- /dev/null +++ b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h @@ -0,0 +1,56 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) + */ +#ifndef __ASM_COBALT_CPU_FEATURE_OVERRIDES_H +#define __ASM_COBALT_CPU_FEATURE_OVERRIDES_H + +#include <linux/config.h> + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 1 +#define cpu_has_32fpr 1 +#define cpu_has_counter 1 +#define cpu_has_watch 0 +#define cpu_has_divec 1 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 0 +#define cpu_has_mcheck 0 +#define cpu_has_ejtag 0 + +#define cpu_has_subset_pcaches 0 +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 +#define cpu_scache_line_size() 0 + +#ifdef CONFIG_64BIT +#define cpu_has_llsc 0 +#else +#define cpu_has_llsc 1 +#endif + +#define cpu_has_mips16 0 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 +#define cpu_has_vtag_icache 0 +#define cpu_has_ic_fills_f_dc 0 +#define cpu_icache_snoops_remote_store 0 +#define cpu_has_dsp 0 + +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#endif /* __ASM_COBALT_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/cobalt/mach-gt64120.h b/include/asm-mips/mach-cobalt/mach-gt64120.h index 587fc4378f4..587fc4378f4 100644 --- a/include/asm-mips/cobalt/mach-gt64120.h +++ b/include/asm-mips/mach-cobalt/mach-gt64120.h diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h index b80c30725cf..36070b5654a 100644 --- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip32/cpu-feature-overrides.h @@ -18,7 +18,7 @@ * so, for 64bit IP32 kernel we just don't use ll/sc. * This does not affect luserland. */ -#if defined(CONFIG_CPU_R5000) && defined(CONFIG_64BIT) +#if (defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_NEVADA)) && defined(CONFIG_64BIT) #define cpu_has_llsc 0 #else #define cpu_has_llsc 1 diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h index a5ea9d828ae..cc53196efa4 100644 --- a/include/asm-mips/r4kcache.h +++ b/include/asm-mips/r4kcache.h @@ -166,123 +166,6 @@ static inline void invalidate_tcache_page(unsigned long addr) : "r" (base), \ "i" (op)); -static inline void blast_dcache16(void) -{ - unsigned long start = INDEX_BASE; - unsigned long end = start + current_cpu_data.dcache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; - unsigned long ws_end = current_cpu_data.dcache.ways << - current_cpu_data.dcache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr|ws,Index_Writeback_Inv_D); -} - -static inline void blast_dcache16_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - - do { - cache16_unroll32(start,Hit_Writeback_Inv_D); - start += 0x200; - } while (start < end); -} - -static inline void blast_dcache16_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; - unsigned long ws_end = current_cpu_data.dcache.ways << - current_cpu_data.dcache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr|ws,Index_Writeback_Inv_D); -} - -static inline void blast_icache16(void) -{ - unsigned long start = INDEX_BASE; - unsigned long end = start + current_cpu_data.icache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; - unsigned long ws_end = current_cpu_data.icache.ways << - current_cpu_data.icache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr|ws,Index_Invalidate_I); -} - -static inline void blast_icache16_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - - do { - cache16_unroll32(start,Hit_Invalidate_I); - start += 0x200; - } while (start < end); -} - -static inline void blast_icache16_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; - unsigned long ws_end = current_cpu_data.icache.ways << - current_cpu_data.icache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr|ws,Index_Invalidate_I); -} - -static inline void blast_scache16(void) -{ - unsigned long start = INDEX_BASE; - unsigned long end = start + current_cpu_data.scache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - -static inline void blast_scache16_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = page + PAGE_SIZE; - - do { - cache16_unroll32(start,Hit_Writeback_Inv_SD); - start += 0x200; - } while (start < end); -} - -static inline void blast_scache16_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - #define cache32_unroll32(base,op) \ __asm__ __volatile__( \ " .set push \n" \ @@ -309,123 +192,6 @@ static inline void blast_scache16_page_indexed(unsigned long page) : "r" (base), \ "i" (op)); -static inline void blast_dcache32(void) -{ - unsigned long start = INDEX_BASE; - unsigned long end = start + current_cpu_data.dcache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; - unsigned long ws_end = current_cpu_data.dcache.ways << - current_cpu_data.dcache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) - cache32_unroll32(addr|ws,Index_Writeback_Inv_D); -} - -static inline void blast_dcache32_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - - do { - cache32_unroll32(start,Hit_Writeback_Inv_D); - start += 0x400; - } while (start < end); -} - -static inline void blast_dcache32_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; - unsigned long ws_end = current_cpu_data.dcache.ways << - current_cpu_data.dcache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) - cache32_unroll32(addr|ws,Index_Writeback_Inv_D); -} - -static inline void blast_icache32(void) -{ - unsigned long start = INDEX_BASE; - unsigned long end = start + current_cpu_data.icache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; - unsigned long ws_end = current_cpu_data.icache.ways << - current_cpu_data.icache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) - cache32_unroll32(addr|ws,Index_Invalidate_I); -} - -static inline void blast_icache32_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - - do { - cache32_unroll32(start,Hit_Invalidate_I); - start += 0x400; - } while (start < end); -} - -static inline void blast_icache32_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; - unsigned long ws_end = current_cpu_data.icache.ways << - current_cpu_data.icache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) - cache32_unroll32(addr|ws,Index_Invalidate_I); -} - -static inline void blast_scache32(void) -{ - unsigned long start = INDEX_BASE; - unsigned long end = start + current_cpu_data.scache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) - cache32_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - -static inline void blast_scache32_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = page + PAGE_SIZE; - - do { - cache32_unroll32(start,Hit_Writeback_Inv_SD); - start += 0x400; - } while (start < end); -} - -static inline void blast_scache32_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400) - cache32_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - #define cache64_unroll32(base,op) \ __asm__ __volatile__( \ " .set push \n" \ @@ -452,84 +218,6 @@ static inline void blast_scache32_page_indexed(unsigned long page) : "r" (base), \ "i" (op)); -static inline void blast_icache64(void) -{ - unsigned long start = INDEX_BASE; - unsigned long end = start + current_cpu_data.icache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; - unsigned long ws_end = current_cpu_data.icache.ways << - current_cpu_data.icache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) - cache64_unroll32(addr|ws,Index_Invalidate_I); -} - -static inline void blast_icache64_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - - do { - cache64_unroll32(start,Hit_Invalidate_I); - start += 0x800; - } while (start < end); -} - -static inline void blast_icache64_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; - unsigned long ws_end = current_cpu_data.icache.ways << - current_cpu_data.icache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) - cache64_unroll32(addr|ws,Index_Invalidate_I); -} - -static inline void blast_scache64(void) -{ - unsigned long start = INDEX_BASE; - unsigned long end = start + current_cpu_data.scache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) - cache64_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - -static inline void blast_scache64_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = page + PAGE_SIZE; - - do { - cache64_unroll32(start,Hit_Writeback_Inv_SD); - start += 0x800; - } while (start < end); -} - -static inline void blast_scache64_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x800) - cache64_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - #define cache128_unroll32(base,op) \ __asm__ __volatile__( \ " .set push \n" \ @@ -556,43 +244,55 @@ static inline void blast_scache64_page_indexed(unsigned long page) : "r" (base), \ "i" (op)); -static inline void blast_scache128(void) -{ - unsigned long start = INDEX_BASE; - unsigned long end = start + current_cpu_data.scache.waysize; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x1000) - cache128_unroll32(addr|ws,Index_Writeback_Inv_SD); -} - -static inline void blast_scache128_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = page + PAGE_SIZE; - - do { - cache128_unroll32(start,Hit_Writeback_Inv_SD); - start += 0x1000; - } while (start < end); -} - -static inline void blast_scache128_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; - unsigned long ws_end = current_cpu_data.scache.ways << - current_cpu_data.scache.waybit; - unsigned long ws, addr; - - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x1000) - cache128_unroll32(addr|ws,Index_Writeback_Inv_SD); -} +/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */ +#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \ +static inline void blast_##pfx##cache##lsize(void) \ +{ \ + unsigned long start = INDEX_BASE; \ + unsigned long end = start + current_cpu_data.desc.waysize; \ + unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ + unsigned long ws_end = current_cpu_data.desc.ways << \ + current_cpu_data.desc.waybit; \ + unsigned long ws, addr; \ + \ + for (ws = 0; ws < ws_end; ws += ws_inc) \ + for (addr = start; addr < end; addr += lsize * 32) \ + cache##lsize##_unroll32(addr|ws,indexop); \ +} \ + \ +static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \ +{ \ + unsigned long start = page; \ + unsigned long end = page + PAGE_SIZE; \ + \ + do { \ + cache##lsize##_unroll32(start,hitop); \ + start += lsize * 32; \ + } while (start < end); \ +} \ + \ +static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \ +{ \ + unsigned long start = page; \ + unsigned long end = start + PAGE_SIZE; \ + unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ + unsigned long ws_end = current_cpu_data.desc.ways << \ + current_cpu_data.desc.waybit; \ + unsigned long ws, addr; \ + \ + for (ws = 0; ws < ws_end; ws += ws_inc) \ + for (addr = start; addr < end; addr += lsize * 32) \ + cache##lsize##_unroll32(addr|ws,indexop); \ +} + +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16) +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16) +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16) +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32) +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32) +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32) +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64) +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128) #endif /* _ASM_R4KCACHE_H */ diff --git a/include/asm-mips/reboot.h b/include/asm-mips/reboot.h index 2f10ebcbe14..e48c0bfab25 100644 --- a/include/asm-mips/reboot.h +++ b/include/asm-mips/reboot.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1997, 1999, 2001 by Ralf Baechle + * Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle * Copyright (C) 2001 MIPS Technologies, Inc. */ #ifndef _ASM_REBOOT_H @@ -11,6 +11,5 @@ extern void (*_machine_restart)(char *command); extern void (*_machine_halt)(void); -extern void (*_machine_power_off)(void); #endif /* _ASM_REBOOT_H */ diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h index 5a06f6d1389..907da600fdd 100644 --- a/include/asm-mips/string.h +++ b/include/asm-mips/string.h @@ -141,26 +141,4 @@ extern void *memcpy(void *__to, __const__ void *__from, size_t __n); #define __HAVE_ARCH_MEMMOVE extern void *memmove(void *__dest, __const__ void *__src, size_t __n); -#ifdef CONFIG_32BIT -#define __HAVE_ARCH_MEMSCAN -static __inline__ void *memscan(void *__addr, int __c, size_t __size) -{ - char *__end = (char *)__addr + __size; - unsigned char __uc = (unsigned char) __c; - - __asm__(".set\tpush\n\t" - ".set\tnoat\n\t" - ".set\treorder\n\t" - "1:\tbeq\t%0,%1,2f\n\t" - "addiu\t%0,1\n\t" - "lbu\t$1,-1(%0)\n\t" - "bne\t$1,%z4,1b\n" - "2:\t.set\tpop" - : "=r" (__addr), "=r" (__end) - : "0" (__addr), "1" (__end), "Jr" (__uc)); - - return __addr; -} -#endif /* CONFIG_32BIT */ - #endif /* _ASM_STRING_H */ diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h index 3bb7f0087d6..de85bd2245f 100644 --- a/include/asm-mips/tx4927/tx4927.h +++ b/include/asm-mips/tx4927/tx4927.h @@ -2,7 +2,7 @@ * Author: MontaVista Software, Inc. * source@mvista.com * - * Copyright 2001-2002 MontaVista Software Inc. + * Copyright 2001-2006 MontaVista Software Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -30,10 +30,10 @@ #include <asm/tx4927/tx4927_mips.h> /* - This register naming came from the intergrate cpu/controoler name TX4927 + This register naming came from the integrated CPU/controller name TX4927 followed by the device name from table 4.2.2 on page 4-3 and then followed by the register name from table 4.2.3 on pages 4-4 to 4-8. The manaul - used is "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001". + used was "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001". */ #define TX4927_SIO_0_BASE @@ -251,8 +251,8 @@ /* TX4927 Timer 0 (32-bit registers) */ #define TX4927_TMR0_BASE 0xf000 -#define TX4927_TMR0_TMTCR0 0xf004 -#define TX4927_TMR0_TMTISR0 0xf008 +#define TX4927_TMR0_TMTCR0 0xf000 +#define TX4927_TMR0_TMTISR0 0xf004 #define TX4927_TMR0_TMCPRA0 0xf008 #define TX4927_TMR0_TMCPRB0 0xf00c #define TX4927_TMR0_TMITMR0 0xf010 @@ -264,8 +264,8 @@ /* TX4927 Timer 1 (32-bit registers) */ #define TX4927_TMR1_BASE 0xf100 -#define TX4927_TMR1_TMTCR1 0xf104 -#define TX4927_TMR1_TMTISR1 0xf108 +#define TX4927_TMR1_TMTCR1 0xf100 +#define TX4927_TMR1_TMTISR1 0xf104 #define TX4927_TMR1_TMCPRA1 0xf108 #define TX4927_TMR1_TMCPRB1 0xf10c #define TX4927_TMR1_TMITMR1 0xf110 @@ -277,13 +277,12 @@ /* TX4927 Timer 2 (32-bit registers) */ #define TX4927_TMR2_BASE 0xf200 -#define TX4927_TMR2_TMTCR2 0xf104 -#define TX4927_TMR2_TMTISR2 0xf208 +#define TX4927_TMR2_TMTCR2 0xf200 +#define TX4927_TMR2_TMTISR2 0xf204 #define TX4927_TMR2_TMCPRA2 0xf208 -#define TX4927_TMR2_TMCPRB2 0xf20c #define TX4927_TMR2_TMITMR2 0xf210 #define TX4927_TMR2_TMCCDR2 0xf220 -#define TX4927_TMR2_TMPGMR2 0xf230 +#define TX4927_TMR2_TMWTMR2 0xf240 #define TX4927_TMR2_TMTRR2 0xf2f0 #define TX4927_TMR2_LIMIT 0xf2ff diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h index 165f6b8b217..66c064690f4 100644 --- a/include/asm-mips/tx4927/tx4927_pci.h +++ b/include/asm-mips/tx4927/tx4927_pci.h @@ -253,6 +253,16 @@ struct tx4927_pcic_reg { #define TX4927_CCFG_PCIDIVMODE_5 0x00001000 #define TX4927_CCFG_PCIDIVMODE_6 0x00001800 +#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00 +#define TX4937_CCFG_PCIDIVMODE_8 0x00000000 +#define TX4937_CCFG_PCIDIVMODE_4 0x00000400 +#define TX4937_CCFG_PCIDIVMODE_9 0x00000800 +#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00 +#define TX4937_CCFG_PCIDIVMODE_10 0x00001000 +#define TX4937_CCFG_PCIDIVMODE_5 0x00001400 +#define TX4937_CCFG_PCIDIVMODE_11 0x00001800 +#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00 + /* PCFG : Pin Configuration */ #define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 #define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h index 41bb96bb212..91d813a3782 100644 --- a/include/asm-mips/uaccess.h +++ b/include/asm-mips/uaccess.h @@ -202,49 +202,49 @@ struct __large_struct { unsigned long buf[100]; }; * Yuck. We need two variants, one for 64bit operation and one * for 32 bit mode and old iron. */ -#ifdef __mips64 -#define __GET_USER_DW(ptr) __get_user_asm("ld", ptr) -#else -#define __GET_USER_DW(ptr) __get_user_asm_ll32(ptr) +#ifdef CONFIG_32BIT +#define __GET_USER_DW(val, ptr) __get_user_asm_ll32(val, ptr) +#endif +#ifdef CONFIG_64BIT +#define __GET_USER_DW(val, ptr) __get_user_asm(val, "ld", ptr) #endif -#define __get_user_nocheck(x,ptr,size) \ -({ \ - __typeof(*(ptr)) __gu_val = (__typeof(*(ptr))) 0; \ - long __gu_err = 0; \ - \ +extern void __get_user_unknown(void); + +#define __get_user_common(val, size, ptr) \ +do { \ switch (size) { \ - case 1: __get_user_asm("lb", ptr); break; \ - case 2: __get_user_asm("lh", ptr); break; \ - case 4: __get_user_asm("lw", ptr); break; \ - case 8: __GET_USER_DW(ptr); break; \ + case 1: __get_user_asm(val, "lb", ptr); break; \ + case 2: __get_user_asm(val, "lh", ptr); break; \ + case 4: __get_user_asm(val, "lw", ptr); break; \ + case 8: __GET_USER_DW(val, ptr); break; \ default: __get_user_unknown(); break; \ } \ - (x) = (__typeof__(*(ptr))) __gu_val; \ +} while (0) + +#define __get_user_nocheck(x,ptr,size) \ +({ \ + long __gu_err; \ + \ + __get_user_common((x), size, ptr); \ __gu_err; \ }) #define __get_user_check(x,ptr,size) \ ({ \ - const __typeof__(*(ptr)) __user * __gu_addr = (ptr); \ - __typeof__(*(ptr)) __gu_val = 0; \ long __gu_err = -EFAULT; \ + const void __user * __gu_ptr = (ptr); \ + \ + if (likely(access_ok(VERIFY_READ, __gu_ptr, size))) \ + __get_user_common((x), size, __gu_ptr); \ \ - if (likely(access_ok(VERIFY_READ, __gu_addr, size))) { \ - switch (size) { \ - case 1: __get_user_asm("lb", __gu_addr); break; \ - case 2: __get_user_asm("lh", __gu_addr); break; \ - case 4: __get_user_asm("lw", __gu_addr); break; \ - case 8: __GET_USER_DW(__gu_addr); break; \ - default: __get_user_unknown(); break; \ - } \ - } \ - (x) = (__typeof__(*(ptr))) __gu_val; \ __gu_err; \ }) -#define __get_user_asm(insn, addr) \ +#define __get_user_asm(val, insn, addr) \ { \ + long __gu_tmp; \ + \ __asm__ __volatile__( \ "1: " insn " %1, %3 \n" \ "2: \n" \ @@ -255,14 +255,16 @@ struct __large_struct { unsigned long buf[100]; }; " .section __ex_table,\"a\" \n" \ " "__UA_ADDR "\t1b, 3b \n" \ " .previous \n" \ - : "=r" (__gu_err), "=r" (__gu_val) \ + : "=r" (__gu_err), "=r" (__gu_tmp) \ : "0" (0), "o" (__m(addr)), "i" (-EFAULT)); \ + \ + (val) = (__typeof__(val)) __gu_tmp; \ } /* * Get a long long 64 using 32 bit registers. */ -#define __get_user_asm_ll32(addr) \ +#define __get_user_asm_ll32(val, addr) \ { \ __asm__ __volatile__( \ "1: lw %1, (%3) \n" \ @@ -278,21 +280,20 @@ struct __large_struct { unsigned long buf[100]; }; " " __UA_ADDR " 1b, 4b \n" \ " " __UA_ADDR " 2b, 4b \n" \ " .previous \n" \ - : "=r" (__gu_err), "=&r" (__gu_val) \ + : "=r" (__gu_err), "=&r" (val) \ : "0" (0), "r" (addr), "i" (-EFAULT)); \ } -extern void __get_user_unknown(void); - /* * Yuck. We need two variants, one for 64bit operation and one * for 32 bit mode and old iron. */ -#ifdef __mips64 -#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr) -#else +#ifdef CONFIG_32BIT #define __PUT_USER_DW(ptr) __put_user_asm_ll32(ptr) #endif +#ifdef CONFIG_64BIT +#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr) +#endif #define __put_user_nocheck(x,ptr,size) \ ({ \ |