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authorJames Bottomley <James.Bottomley@HansenPartnership.com>2009-06-12 10:02:03 -0500
committerJames Bottomley <James.Bottomley@HansenPartnership.com>2009-06-12 10:02:03 -0500
commit82681a318f9f028ea64e61f24bbd9ac535531921 (patch)
tree529b6a5b4fd040fb54b7672b1a224ebd47445876 /Documentation/ABI/testing/sysfs-devices-cache_disable
parent3860c97bd60a4525bb62eb90e3e7d2f02662ac59 (diff)
parent8ebf975608aaebd7feb33d77f07ba21a6380e086 (diff)
[SCSI] Merge branch 'linus'
Conflicts: drivers/message/fusion/mptsas.c fixed up conflict between req->data_len accessors and mptsas driver updates. Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
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+What: /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X
+Date: August 2008
+KernelVersion: 2.6.27
+Contact: mark.langsdorf@amd.com
+Description: These files exist in every cpu's cache index directories.
+ There are currently 2 cache_disable_# files in each
+ directory. Reading from these files on a supported
+ processor will return that cache disable index value
+ for that processor and node. Writing to one of these
+ files will cause the specificed cache index to be disabled.
+
+ Currently, only AMD Family 10h Processors support cache index
+ disable, and only for their L3 caches. See the BIOS and
+ Kernel Developer's Guide at
+ http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116-Public-GH-BKDG_3.20_2-4-09.pdf
+ for formatting information and other details on the
+ cache index disable.
+Users: joachim.deguara@amd.com