aboutsummaryrefslogtreecommitdiff
path: root/Documentation/powerpc/booting-without-of.txt
diff options
context:
space:
mode:
authorAnton Vorontsov <avorontsov@ru.mvista.com>2008-05-19 21:47:05 +0400
committerKumar Gala <galak@kernel.crashing.org>2008-06-10 11:11:10 -0500
commit32def337aafee0bc65eb58d5b1b3617525eb7fb7 (patch)
tree22173ef1c86e1dd6de2eadee2600dbad1e029249 /Documentation/powerpc/booting-without-of.txt
parent9572653ee01a2134ae3a1d7aa29ce9d026a6afe9 (diff)
powerpc/QE: implement support for the GPIO LIB API
This is needed to access QE GPIOs via Linux GPIO API. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-By: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'Documentation/powerpc/booting-without-of.txt')
-rw-r--r--Documentation/powerpc/booting-without-of.txt27
1 files changed, 27 insertions, 0 deletions
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index 8675ebca2cf..b68684d39f9 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -1736,6 +1736,33 @@ platforms are moved over to use the flattened-device-tree model.
......
};
+ Note that "par_io" nodes are obsolete, and should not be used for
+ the new device trees. Instead, each Par I/O bank should be represented
+ via its own gpio-controller node:
+
+ Required properties:
+ - #gpio-cells : should be "2".
+ - compatible : should be "fsl,<chip>-qe-pario-bank",
+ "fsl,mpc8323-qe-pario-bank".
+ - reg : offset to the register set and its length.
+ - gpio-controller : node to identify gpio controllers.
+
+ Example:
+ qe_pio_a: gpio-controller@1400 {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8360-qe-pario-bank",
+ "fsl,mpc8323-qe-pario-bank";
+ reg = <0x1400 0x18>;
+ gpio-controller;
+ };
+
+ qe_pio_e: gpio-controller@1460 {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8360-qe-pario-bank",
+ "fsl,mpc8323-qe-pario-bank";
+ reg = <0x1460 0x18>;
+ gpio-controller;
+ };
vi) Pin configuration nodes