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authorKumar Gala <galak@kernel.crashing.org>2008-07-07 11:28:33 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-07-14 07:55:46 -0500
commitd0fc2eaaf4c56a95f5ed29b6bfb609e19714fc16 (patch)
tree49b2fc779d4d051884d2dbc2c264ef608662312c /Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/brg.txt
parentb93eeba49efb30f88a83fc97ad22c255605654a1 (diff)
powerpc/fsl: Refactor device bindings
Moved Freescale SoC related bindings out of booting-without-of.txt and into their own files. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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+* Baud Rate Generators
+
+Currently defined compatibles:
+fsl,cpm-brg
+fsl,cpm1-brg
+fsl,cpm2-brg
+
+Properties:
+- reg : There may be an arbitrary number of reg resources; BRG
+ numbers are assigned to these in order.
+- clock-frequency : Specifies the base frequency driving
+ the BRG.
+
+Example:
+ brg@119f0 {
+ compatible = "fsl,mpc8272-brg",
+ "fsl,cpm2-brg",
+ "fsl,cpm-brg";
+ reg = <119f0 10 115f0 10>;
+ clock-frequency = <d#25000000>;
+ };