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authorBob Moore <robert.moore@intel.com>2008-12-31 03:06:06 +0800
committerLen Brown <len.brown@intel.com>2008-12-31 01:17:09 -0500
commit06f5541960d02d5e0ddd8fd5c9a1554d85d94fa9 (patch)
tree2a86b61dd4e63d6a74450198c13f8c7430be9e69 /Documentation/sysrq.txt
parent1685bd404dc2ecce2fdae6410e85ded2f2c0136d (diff)
ACPICA: FADT parsing changes and fixes
1) Update the register lengths for the PM1 event blocks. The length must be divided by two in order to use these to access the status registers. 2) Add run-time option to use default register lengths to override a faulty FADT. 3) Add warning message if any of the X64 address structures contain a length that does not match the legacy length earlier in the FADT. 4) Move all FADT warning messages into the ValidateFadt function. Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
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