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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-08-10 18:08:10 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-09-01 12:06:23 +0100
commit0ba8b9b273c45dd23f60ff700e265a0069b33758 (patch)
treecb6aef90464889a27215cf9b7204c11b12e7c628 /arch/arm/kernel
parentb8e6c91c74e9f0279b7c51048779b3d62da60b88 (diff)
[ARM] cputype: separate definitions, use them
Add asm/cputype.h, moving functions and definitions from asm/system.h there. Convert all users of 'processor_id' to the more efficient read_cpuid_id() function. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/kernel')
-rw-r--r--arch/arm/kernel/setup.c45
1 files changed, 23 insertions, 22 deletions
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 2ca7038b67a..fb04703f2a8 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -26,6 +26,7 @@
#include <linux/fs.h>
#include <asm/cpu.h>
+#include <asm/cputype.h>
#include <asm/elf.h>
#include <asm/procinfo.h>
#include <asm/setup.h>
@@ -280,9 +281,9 @@ static inline void dump_cache(const char *prefix, int cpu, unsigned int cache)
static void __init dump_cpu_info(int cpu)
{
- unsigned int info = read_cpuid(CPUID_CACHETYPE);
+ unsigned int info = read_cpuid_cachetype();
- if (info != processor_id) {
+ if (info != read_cpuid_id()) {
printk("CPU%u: D %s %s cache\n", cpu, cache_is_vivt() ? "VIVT" : "VIPT",
cache_types[CACHE_TYPE(info)]);
if (CACHE_S(info)) {
@@ -301,15 +302,15 @@ int cpu_architecture(void)
{
int cpu_arch;
- if ((processor_id & 0x0008f000) == 0) {
+ if ((read_cpuid_id() & 0x0008f000) == 0) {
cpu_arch = CPU_ARCH_UNKNOWN;
- } else if ((processor_id & 0x0008f000) == 0x00007000) {
- cpu_arch = (processor_id & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
- } else if ((processor_id & 0x00080000) == 0x00000000) {
- cpu_arch = (processor_id >> 16) & 7;
+ } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
+ cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
+ } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
+ cpu_arch = (read_cpuid_id() >> 16) & 7;
if (cpu_arch)
cpu_arch += CPU_ARCH_ARMv3;
- } else if ((processor_id & 0x000f0000) == 0x000f0000) {
+ } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
unsigned int mmfr0;
/* Revised CPUID format. Read the Memory Model Feature
@@ -346,10 +347,10 @@ static void __init setup_processor(void)
* types. The linker builds this table for us from the
* entries in arch/arm/mm/proc-*.S
*/
- list = lookup_processor_type(processor_id);
+ list = lookup_processor_type(read_cpuid_id());
if (!list) {
printk("CPU configuration botched (ID %08x), unable "
- "to continue.\n", processor_id);
+ "to continue.\n", read_cpuid_id());
while (1);
}
@@ -369,7 +370,7 @@ static void __init setup_processor(void)
#endif
printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
- cpu_name, processor_id, (int)processor_id & 15,
+ cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
proc_arch[cpu_architecture()], cr_alignment);
sprintf(init_utsname()->machine, "%s%c", list->arch_name, ENDIANNESS);
@@ -922,7 +923,7 @@ static int c_show(struct seq_file *m, void *v)
int i;
seq_printf(m, "Processor\t: %s rev %d (%s)\n",
- cpu_name, (int)processor_id & 15, elf_platform);
+ cpu_name, read_cpuid_id() & 15, elf_platform);
#if defined(CONFIG_SMP)
for_each_online_cpu(i) {
@@ -949,30 +950,30 @@ static int c_show(struct seq_file *m, void *v)
if (elf_hwcap & (1 << i))
seq_printf(m, "%s ", hwcap_str[i]);
- seq_printf(m, "\nCPU implementer\t: 0x%02x\n", processor_id >> 24);
+ seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
seq_printf(m, "CPU architecture: %s\n", proc_arch[cpu_architecture()]);
- if ((processor_id & 0x0008f000) == 0x00000000) {
+ if ((read_cpuid_id() & 0x0008f000) == 0x00000000) {
/* pre-ARM7 */
- seq_printf(m, "CPU part\t: %07x\n", processor_id >> 4);
+ seq_printf(m, "CPU part\t: %07x\n", read_cpuid_id() >> 4);
} else {
- if ((processor_id & 0x0008f000) == 0x00007000) {
+ if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
/* ARM7 */
seq_printf(m, "CPU variant\t: 0x%02x\n",
- (processor_id >> 16) & 127);
+ (read_cpuid_id() >> 16) & 127);
} else {
/* post-ARM7 */
seq_printf(m, "CPU variant\t: 0x%x\n",
- (processor_id >> 20) & 15);
+ (read_cpuid_id() >> 20) & 15);
}
seq_printf(m, "CPU part\t: 0x%03x\n",
- (processor_id >> 4) & 0xfff);
+ (read_cpuid_id() >> 4) & 0xfff);
}
- seq_printf(m, "CPU revision\t: %d\n", processor_id & 15);
+ seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
{
- unsigned int cache_info = read_cpuid(CPUID_CACHETYPE);
- if (cache_info != processor_id) {
+ unsigned int cache_info = read_cpuid_cachetype();
+ if (cache_info != read_cpuid_id()) {
seq_printf(m, "Cache type\t: %s\n"
"Cache clean\t: %s\n"
"Cache lockdown\t: %s\n"