aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/mach-pxa
diff options
context:
space:
mode:
authorEric Miao <eric.miao@marvell.com>2008-06-06 16:34:03 +0800
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-07-09 21:38:33 +0100
commit20072fd0c93349e19527dd2fa9588b4335960e62 (patch)
tree8aa26b382c97b52d4596db1a05ee459ae334b548 /arch/arm/mach-pxa
parent5c9f50e90e8056fb5a8bdd479ab0591d5dad79a0 (diff)
[ARM] pxa: add support for L2 outer cache on XScale3
The initial patch from Lothar, and Lennert make it into a cleaner one, modified and tested on PXA320 by Eric Miao. This patch moves the L2 cache operations out of proc-xsc3.S into dedicated outer cache support code. CACHE_XSC3L2 can be deselected so no L2 cache specific code will be linked in, and that L2 enable bit will not be set, this applies to the following cases: a. _only_ PXA300/PXA310 support included and no L2 cache wanted b. PXA320 support included, but want L2 be disabled So the enabling of L2 depends on two things: - CACHE_XSC3L2 is selected - and L2 cache is present Where the latter is only a safeguard (previous testing shows it works OK even when this bit is turned on). IXP series of processors with XScale3 cannot disable L2 cache for the moment since they depend on the L2 cache for its coherent memory, so IXP may always select CACHE_XSC3L2. Other L2 relevant bits are always turned on (i.e. the original code enclosed by #if L2_CACHE_ENABLED .. #endif), as they showed no side effects. Specifically, these bits are: - OC bits in TTBASE register (table walk outer cache attributes) - LLR Outer Cache Attributes (OC) in Auxiliary Control Register Signed-off-by: Lothar WaÃ<9f>mann <LW@KARO-electronics.de> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-pxa')
0 files changed, 0 insertions, 0 deletions