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authorBen Dooks <ben-linux@fluff.org>2009-03-24 17:25:40 +0000
committerBen Dooks <ben-linux@fluff.org>2009-05-07 11:04:57 +0100
commita6925c1c515513e22b0419e1a41155c88d22b1f4 (patch)
tree4ea28200d35286d215f45ca8d578d9ec19d4953b /arch/arm/mach-s3c6400/s3c6400.c
parent2ab408e8759ad4b2a9bad3647838acd648d2c10c (diff)
[ARM] S3C6400: Core support for S3C6400 SoC
Add the core support files for the Samsung S3C6400 SoC. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s3c6400/s3c6400.c')
-rw-r--r--arch/arm/mach-s3c6400/s3c6400.c83
1 files changed, 83 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c6400/s3c6400.c b/arch/arm/mach-s3c6400/s3c6400.c
new file mode 100644
index 00000000000..d11a4272b94
--- /dev/null
+++ b/arch/arm/mach-s3c6400/s3c6400.c
@@ -0,0 +1,83 @@
+/* linux/arch/arm/mach-s3c6410/cpu.c
+ *
+ * Copyright 2009 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/regs-serial.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+#include <plat/sdhci.h>
+#include <plat/iic-core.h>
+#include <plat/s3c6400.h>
+
+void __init s3c6400_map_io(void)
+{
+ /* the i2c device is directly compatible with s3c2440 */
+ s3c_i2c0_setname("s3c2440-i2c");
+}
+
+void __init s3c6400_init_clocks(int xtal)
+{
+ printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
+ s3c24xx_register_baseclocks(xtal);
+ s3c64xx_register_clocks();
+ s3c6400_register_clocks();
+ s3c6400_setup_clocks();
+}
+
+void __init s3c6400_init_irq(void)
+{
+ /* VIC0 does not have IRQS 5..7,
+ * VIC1 is fully populated. */
+ s3c64xx_init_irq(~0 & ~(0xf << 5), ~0);
+}
+
+struct sysdev_class s3c6400_sysclass = {
+ .name = "s3c6400-core",
+};
+
+static struct sys_device s3c6400_sysdev = {
+ .cls = &s3c6400_sysclass,
+};
+
+static int __init s3c6400_core_init(void)
+{
+ return sysdev_class_register(&s3c6400_sysclass);
+}
+
+core_initcall(s3c6400_core_init);
+
+int __init s3c6400_init(void)
+{
+ printk("S3C6400: Initialising architecture\n");
+
+ return sysdev_register(&s3c6400_sysdev);
+}