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authorDan Williams <dan.j.williams@intel.com>2008-11-06 17:43:55 -0700
committerDan Williams <dan.j.williams@intel.com>2008-11-06 10:48:29 -0700
commitc7cf72dcadbe39c2077b32460f86c9f8167be3be (patch)
tree66984afe9b390596d1ae97e35aaeb4e6f52c412d /arch/arm/mm/copypage-v4wt.S
parent45beca08dd8b6d6a65c5ffd730af2eac7a2c7a03 (diff)
[ARM] xsc3: fix xsc3_l2_inv_range
When 'start' and 'end' are less than a cacheline apart and 'start' is unaligned we are done after cleaning and invalidating the first cacheline. So check for (start < end) which will not walk off into invalid address ranges when (start > end). This issue was caught by drivers/dma/dmatest. 2.6.27 is susceptible. Cc: <stable@kernel.org> Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Cc: Lothar WaÃ<9f>mann <LW@KARO-electronics.de> Cc: Lennert Buytenhek <buytenh@marvell.com> Cc: Eric Miao <eric.miao@marvell.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'arch/arm/mm/copypage-v4wt.S')
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