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authorIngo Molnar <mingo@elte.hu>2009-11-04 11:54:15 +0100
committerIngo Molnar <mingo@elte.hu>2009-11-04 11:59:45 +0100
commita2e71271535fde493c32803b1f34789f97efcb5e (patch)
tree90d7139bea2f49e947f27af92614fa6eca50b64d /arch/arm/mm/mmu.c
parent6d7aa9d721c8c640066142fd9534afcdf68d7f9d (diff)
parentb419148e567728f6af0c3b01965c1cc141e3e13a (diff)
Merge commit 'v2.6.32-rc6' into perf/core
Conflicts: tools/perf/Makefile Merge reason: Resolve the conflict, merge to upstream and merge in perf fixes so we can add a dependent patch. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/arm/mm/mmu.c')
-rw-r--r--arch/arm/mm/mmu.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 02243eeccf5..ea67be0223a 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -117,6 +117,13 @@ static void __init early_cachepolicy(char **p)
}
if (i == ARRAY_SIZE(cache_policies))
printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
+ /*
+ * This restriction is partly to do with the way we boot; it is
+ * unpredictable to have memory mapped using two different sets of
+ * memory attributes (shared, type, and cache attribs). We can not
+ * change these attributes once the initial assembly has setup the
+ * page tables.
+ */
if (cpu_architecture() >= CPU_ARCH_ARMv6) {
printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
cachepolicy = CPOLICY_WRITEBACK;