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authorIngo Molnar <mingo@elte.hu>2010-02-08 08:55:43 +0100
committerIngo Molnar <mingo@elte.hu>2010-02-08 08:55:46 +0100
commit6d3e0907b8b239d16720d144e2675ecf10d3bc3b (patch)
treee0b0743b5f6f82b057cafc4f3687396a6e01a0b4 /arch/arm/mm/proc-arm6_7.S
parent23577256953c870de9b724c3a2611ce7be6a1e4e (diff)
parent50200df462023b187d80a99a52f5f2cfe3c86c26 (diff)
Merge branch 'sched/urgent' into sched/core
Merge reason: Merge dependent fix, update to latest -rc. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/arm/mm/proc-arm6_7.S')
-rw-r--r--arch/arm/mm/proc-arm6_7.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 3f9cd3d8f6d..795dc615f43 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -41,7 +41,7 @@ ENTRY(cpu_arm7_dcache_clean_area)
ENTRY(cpu_arm7_data_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
- ldr r8, [r0] @ read arm instruction
+ ldr r8, [r2] @ read arm instruction
tst r8, #1 << 20 @ L = 0 -> write?
orreq r1, r1, #1 << 11 @ yes.
and r7, r8, #15 << 24