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authorDan Williams <dan.j.williams@intel.com>2006-12-01 19:31:42 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-12-01 23:40:37 +0000
commitf5236225a3858b505221a59233af1f1158be9139 (patch)
tree1d59e171dae730ead66c21cb243d218df4ab457c /arch/arm/mm/proc-xsc3.S
parent0e5fdca7622eb950f42f97a1970670e00a739175 (diff)
[ARM] 3967/1: xsc3: make branch predication configurable on xsc3
Remove BTB_ENABLE from proc-xsc3.S On some early revisions of xsc3 enabling the branch target buffer can cause crashes, see erratum #42. Cc: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-xsc3.S')
-rw-r--r--arch/arm/mm/proc-xsc3.S7
1 files changed, 0 insertions, 7 deletions
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 85c3523d0a9..1ef564d0957 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -57,11 +57,6 @@
#define L2_CACHE_ENABLE 1
/*
- * Enable the Branch Target Buffer (can cause crashes, see erratum #42.)
- */
-#define BTB_ENABLE 0
-
-/*
* This macro is used to wait for a CP15 write and is needed
* when we have to ensure that the last operation to the co-pro
* was completed before continuing with operation.
@@ -434,9 +429,7 @@ __xsc3_setup:
mrc p15, 0, r0, c1, c0, 0 @ get control register
bic r0, r0, r5 @ .... .... .... ..A.
orr r0, r0, r6 @ .... .... .... .C.M
-#if BTB_ENABLE
orr r0, r0, #0x00000800 @ ..VI Z..S .... ....
-#endif
#if L2_CACHE_ENABLE
orr r0, r0, #0x04000000 @ L2 enable
#endif