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authorTimothy Baldwin <T.E.Baldwin99@members.leeds.ac.uk>2005-09-04 10:13:48 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-09-04 10:13:48 +0100
commitca6ca91d8c7498d45e0d35800503699164366f10 (patch)
tree3e340cd984e08f4f1edd7c8f33c4e45cf6ace743 /arch/arm/mm
parent9bed07d0fed01f7c39d128e59e5d35d7d67ff439 (diff)
[ARM] 2875/1: Data Abort fixes
Patch from Timothy Baldwin All data aborts are treated as read accesses. The existing code updates the wrong bit of r1, also the comments are wrong in that the sense of the L bit is inverted. Signed-off-by: Timothy E. Baldwin <T.E.Baldwin99@members.leeds.ac.uk> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/proc-arm6_7.S8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 0ee214b824f..189ef6a71ba 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -38,8 +38,8 @@ ENTRY(cpu_arm7_data_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
ldr r8, [r0] @ read arm instruction
- tst r8, #1 << 20 @ L = 1 -> write?
- orreq r1, r1, #1 << 8 @ yes.
+ tst r8, #1 << 20 @ L = 0 -> write?
+ orreq r1, r1, #1 << 11 @ yes.
and r7, r8, #15 << 24
add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine
nop
@@ -71,8 +71,8 @@ ENTRY(cpu_arm6_data_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
ldr r8, [r2] @ read arm instruction
- tst r8, #1 << 20 @ L = 1 -> write?
- orreq r1, r1, #1 << 8 @ yes.
+ tst r8, #1 << 20 @ L = 0 -> write?
+ orreq r1, r1, #1 << 11 @ yes.
and r7, r8, #14 << 24
teq r7, #8 << 24 @ was it ldm/stm
movne pc, lr