diff options
| author | Ben Dooks <ben-linux@fluff.org> | 2008-10-21 14:06:20 +0100 |
|---|---|---|
| committer | Ben Dooks <ben-linux@fluff.org> | 2008-10-21 14:12:07 +0100 |
| commit | de3d896e70555275f57d8cf30ff65c9a73c67ddb (patch) | |
| tree | 84a31ea876b6f815c191a0400385f5b872636d66 /arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c | |
| parent | c3380942e6699ed5b3e3f37b49ceb724b7699813 (diff) | |
[ARM] S3C24XX: Default SPI pin configuration for SPI
Add a set of default pin configuration routines for
setting up the SPI gpio configuration when using the
hardware SPI driver.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c')
| -rw-r--r-- | arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c new file mode 100644 index 00000000000..8b403cbb53d --- /dev/null +++ b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c @@ -0,0 +1,37 @@ +/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c + * + * Copyright (c) 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C24XX SPI - gpio configuration for bus 0 on gpe11,12,13 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. +*/ + +#include <linux/kernel.h> + +#include <mach/hardware.h> + +#include <mach/spi.h> +#include <mach/regs-gpio.h> + +void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi, + int enable) +{ + if (enable) { + s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPE13_SPICLK0); + s3c2410_gpio_cfgpin(S3C2410_GPE12, S3C2410_GPE12_SPIMOSI0); + s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPE11_SPIMISO0); + s3c2410_gpio_pullup(S3C2410_GPE11, 0); + s3c2410_gpio_pullup(S3C2410_GPE13, 0); + } else { + s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPIO_INPUT); + s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPIO_INPUT); + s3c2410_gpio_pullup(S3C2410_GPE11, 1); + s3c2410_gpio_pullup(S3C2410_GPE12, 1); + s3c2410_gpio_pullup(S3C2410_GPE13, 1); + } +} |