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authorWerner Almesberger <werner@openmoko.org>2009-03-05 14:39:30 +0000
committerAndy Green <agreen@octopus.localdomain>2009-03-05 14:39:30 +0000
commitb0345baf86a811059177e6fc493d1c7d4086f7b7 (patch)
treee2715742666fd47189176eefcb7499b9ad7cbbcd /arch/arm
parent21813b7cbfbc7d2c5f9b1afad48639acddbd888d (diff)
Fix s3c64xx_setrate_clksrc
Note: this patch is already on the way upstream but is currently missing in the Openmoko kernel. Some of the rate selection logic in s3c64xx_setrate_clksrc uses what appears to be parent clock selection logic. This patch corrects it. I also added a check for overly large dividers to prevent them from changing unrelated clocks. Signed-off-by: Werner Almesberger <werner@openmoko.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/plat-s3c64xx/s3c6400-clock.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index a6f6b91b732..6699b5736f0 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -239,10 +239,12 @@ static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate)
rate = clk_round_rate(clk, rate);
div = clk_get_rate(clk->parent) / rate;
+ if (div > 16)
+ return -EINVAL;
val = __raw_readl(reg);
- val &= ~sclk->mask;
- val |= (rate - 1) << sclk->shift;
+ val &= ~(0xf << sclk->shift);
+ val |= (div - 1) << sclk->shift;
__raw_writel(val, reg);
return 0;