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authorMike Frysinger <vapier.adi@gmail.com>2008-04-25 02:04:05 +0800
committerBryan Wu <cooloney@kernel.org>2008-04-25 02:04:05 +0800
commita086ee2268abcfcbf80a114f4602e5b26aa80bf0 (patch)
treefe027181ea37e00e85040977788cad82aa3faea5 /arch/blackfin/kernel
parenta81501af19830ff43688781edad7e9c0cbd668af (diff)
[Blackfin] arch: detect the memory available in the system on the fly by default
detect the memory available in the system on the fly by default rather than forcing people to set this manually in the kconfig Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/kernel')
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinit.c10
-rw-r--r--arch/blackfin/kernel/setup.c45
2 files changed, 52 insertions, 3 deletions
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index f271f39d565..917325bfbd8 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -26,6 +26,12 @@
#include <asm/cplb.h>
#include <asm/cplbinit.h>
+#ifdef CONFIG_MAX_MEM_SIZE
+# define CPLB_MEM CONFIG_MAX_MEM_SIZE
+#else
+# define CPLB_MEM CONFIG_MEM_SIZE
+#endif
+
/*
* Number of required data CPLB switchtable entries
* MEMSIZE / 4 (we mostly install 4M page size CPLBs
@@ -35,7 +41,7 @@
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
* 1 for ASYNC Memory
*/
-#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \
+#define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \
+ ASYNC_MEMORY_CPLB_COVERAGE) * 2)
/*
@@ -46,7 +52,7 @@
* possibly 1 for L2 Instruction Memory
* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
*/
-#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
+#define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2)
u_long icplb_table[MAX_CPLBS + 1];
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index c2f3e73ba25..d6668328be7 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -649,6 +649,49 @@ static __init void setup_bootmem_allocator(void)
BOOTMEM_DEFAULT);
}
+#define EBSZ_TO_MEG(ebsz) \
+({ \
+ int meg = 0; \
+ switch (ebsz & 0xf) { \
+ case 0x1: meg = 16; break; \
+ case 0x3: meg = 32; break; \
+ case 0x5: meg = 64; break; \
+ case 0x7: meg = 128; break; \
+ case 0x9: meg = 256; break; \
+ case 0xb: meg = 512; break; \
+ } \
+ meg; \
+})
+static inline int __init get_mem_size(void)
+{
+#ifdef CONFIG_MEM_SIZE
+ return CONFIG_MEM_SIZE;
+#else
+# if defined(EBIU_SDBCTL)
+# if defined(BF561_FAMILY)
+ int ret = 0;
+ u32 sdbctl = bfin_read_EBIU_SDBCTL();
+ ret += EBSZ_TO_MEG(sdbctl >> 0);
+ ret += EBSZ_TO_MEG(sdbctl >> 8);
+ ret += EBSZ_TO_MEG(sdbctl >> 16);
+ ret += EBSZ_TO_MEG(sdbctl >> 24);
+ return ret;
+# else
+ return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL());
+# endif
+# elif defined(EBIU_DDRCTL1)
+ switch (bfin_read_EBIU_DDRCTL1() & 0xc0000) {
+ case DEVSZ_64: return 64;
+ case DEVSZ_128: return 128;
+ case DEVSZ_256: return 256;
+ case DEVSZ_512: return 512;
+ default: return 0;
+ }
+# endif
+#endif
+ BUG();
+}
+
void __init setup_arch(char **cmdline_p)
{
unsigned long sclk, cclk;
@@ -669,7 +712,7 @@ void __init setup_arch(char **cmdline_p)
/* setup memory defaults from the user config */
physical_mem_end = 0;
- _ramend = CONFIG_MEM_SIZE * 1024 * 1024;
+ _ramend = get_mem_size() * 1024 * 1024;
memset(&bfin_memmap, 0, sizeof(bfin_memmap));