diff options
| author | merge <null@invalid> | 2009-01-22 13:55:32 +0000 |
|---|---|---|
| committer | Andy Green <agreen@octopus.localdomain> | 2009-01-22 13:55:32 +0000 |
| commit | aa6f5ffbdba45aa8e19e5048648fc6c7b25376d3 (patch) | |
| tree | fbb786d0ac6f8a774fd834e9ce951197e60fbffa /arch/blackfin/mach-bf561/include/mach/blackfin.h | |
| parent | f2d78193eae5dccd3d588d2c8ea0866efc368332 (diff) | |
MERGE-via-pending-tracking-hist-MERGE-via-stable-tracking-MERGE-via-mokopatches-tracking-fix-stray-endmenu-patch-1232632040-1232632141
pending-tracking-hist top was MERGE-via-stable-tracking-MERGE-via-mokopatches-tracking-fix-stray-endmenu-patch-1232632040-1232632141 / fdf777a63bcb59e0dfd78bfe2c6242e01f6d4eb9 ... parent commitmessage:
From: merge <null@invalid>
MERGE-via-stable-tracking-hist-MERGE-via-mokopatches-tracking-fix-stray-endmenu-patch-1232632040
stable-tracking-hist top was MERGE-via-mokopatches-tracking-fix-stray-endmenu-patch-1232632040 / 90463bfd2d5a3c8b52f6e6d71024a00e052b0ced ... parent commitmessage:
From: merge <null@invalid>
MERGE-via-mokopatches-tracking-hist-fix-stray-endmenu-patch
mokopatches-tracking-hist top was fix-stray-endmenu-patch / 3630e0be570de8057e7f8d2fe501ed353cdf34e6 ... parent commitmessage:
From: Andy Green <andy@openmoko.com>
fix-stray-endmenu.patch
Signed-off-by: Andy Green <andy@openmoko.com>
Diffstat (limited to 'arch/blackfin/mach-bf561/include/mach/blackfin.h')
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/blackfin.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h index 0ea8666e676..f79f6626b7e 100644 --- a/arch/blackfin/mach-bf561/include/mach/blackfin.h +++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h @@ -66,8 +66,12 @@ #define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2)) #define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val) +#define bfin_read_SICB_IMASK(x) bfin_read32(SICB_IMASK0 + (x << 2)) +#define bfin_write_SICB_IMASK(x, val) bfin_write32((SICB_IMASK0 + (x << 2)), val) #define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2)) #define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val) +#define bfin_read_SICB_ISR(x) bfin_read32(SICB_ISR0 + (x << 2)) +#define bfin_write_SICB_ISR(x, val) bfin_write32((SICB_ISR0 + (x << 2)), val) #define BFIN_UART_NR_PORTS 1 |