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author | Nicolas Pitre <nico@cam.org> | 2008-09-18 22:55:47 -0400 |
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committer | Nicolas Pitre <nico@cam.org> | 2009-03-15 21:01:21 -0400 |
commit | 3902a15e784e9b1efa8e6ad246489c609e0ef880 (patch) | |
tree | 8b674544cc2b3381fa9481d2e1e60eb99ef62a71 /arch/m32r | |
parent | 1bb772679ffb0ba1ff1d40d8c6b855ab029f177d (diff) |
[ARM] xsc3: add highmem support to L2 cache handling code
On xsc3, L2 cache ops are possible only on virtual addresses. The code
is rearranged so to have a linear progression requiring the least amount
of pte setups in the highmem case. To protect the virtual mapping so
created, interrupts must be disabled currently up to a page worth of
address range.
The interrupt disabling is done in a way to minimize the overhead within
the inner loop. The alternative would consist in separate code for
the highmem and non highmem compilation which is less preferable.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/m32r')
0 files changed, 0 insertions, 0 deletions