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authorGreg Ungerer <gerg@uclinux.org>2009-05-19 14:08:47 +1000
committerGreg Ungerer <gerg@uclinux.org>2009-09-16 09:43:50 +1000
commit5187995f0a9253e915dfee83684eae7b692213e6 (patch)
treee2dffc82a6c4906a6a8304fc210f7e8f93fdc15b /arch/m68knommu/platform/coldfire
parent5938084bd8843490a4493d19fb108df70d87df2d (diff)
m68knommu: remove duplicate ColdFire mcf_autovector() code
Each of the ColdFire CPU platform code that used the old style interrupt controller had its own copy of the mcf_autovector() function. They are all the same, remove them all and create a single function in the common coldfire/intc.c code. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68knommu/platform/coldfire')
-rw-r--r--arch/m68knommu/platform/coldfire/intc.c27
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/m68knommu/platform/coldfire/intc.c b/arch/m68knommu/platform/coldfire/intc.c
index c81ab6e5cf2..f7a61346ee2 100644
--- a/arch/m68knommu/platform/coldfire/intc.c
+++ b/arch/m68knommu/platform/coldfire/intc.c
@@ -18,6 +18,33 @@
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
+/*
+ * Define the vector numbers for the basic 7 interrupt sources.
+ * These are often referred to as the "external" interrupts in
+ * the ColdFire documentation (for the early ColdFire cores at least).
+ */
+#define EIRQ1 25
+#define EIRQ7 31
+
+/*
+ * Interrupts can be "vectored" on the ColdFire cores that support this old
+ * interrupt controller. That is, the device raising the interrupt can also
+ * supply the vector number to interrupt through. The AVR register of the
+ * interrupt controller enables or disables this for each external interrupt,
+ * so provide generic support for this. Setting this up is out-of-band for
+ * the interrupt system API's, and needs to be done by the driver that
+ * supports this device. Very few devices actually use this.
+ */
+void mcf_autovector(int irq)
+{
+ if ((irq >= EIRQ1) && (irq <= EIRQ7)) {
+ u8 avec;
+ avec = __raw_readb(MCF_MBAR + MCFSIM_AVR);
+ avec |= (0x1 << (irq - EIRQ1 + 1));
+ __raw_writeb(avec, MCF_MBAR + MCFSIM_AVR);
+ }
+}
+
static void intc_irq_mask(unsigned int irq)
{
}