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authorAurelien Jarno <aurelien@aurel32.net>2007-09-05 08:59:34 +0200
committerRalf Baechle <ralf@linux-mips.org>2007-10-11 23:46:06 +0100
commit2f56cfdd812a17623483d3dfa3370a2e6282b245 (patch)
tree624e2bfccf0b0ee02cd94343acdf5d3364cb002e /arch/mips/arc/promlib.c
parentdf78b5c8faa72b3c04f82faab126de93af178348 (diff)
[MIPS] Move ARC code into arch/mips/fw/arc
Move the ARC code to arch/mips/fw/arc from arch/mips/arc. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/arc/promlib.c')
-rw-r--r--arch/mips/arc/promlib.c43
1 files changed, 0 insertions, 43 deletions
diff --git a/arch/mips/arc/promlib.c b/arch/mips/arc/promlib.c
deleted file mode 100644
index c508c00dbb6..00000000000
--- a/arch/mips/arc/promlib.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996 David S. Miller (dm@sgi.com)
- * Compability with board caches, Ulf Carlsson
- */
-#include <linux/kernel.h>
-#include <asm/sgialib.h>
-#include <asm/bcache.h>
-
-/*
- * IP22 boardcache is not compatible with board caches. Thus we disable it
- * during romvec action. Since r4xx0.c is always compiled and linked with your
- * kernel, this shouldn't cause any harm regardless what MIPS processor you
- * have.
- *
- * The ARC write and read functions seem to interfere with the serial lines
- * in some way. You should be careful with them.
- */
-
-void prom_putchar(char c)
-{
- ULONG cnt;
- CHAR it = c;
-
- bc_disable();
- ArcWrite(1, &it, 1, &cnt);
- bc_enable();
-}
-
-char prom_getchar(void)
-{
- ULONG cnt;
- CHAR c;
-
- bc_disable();
- ArcRead(0, &c, 1, &cnt);
- bc_enable();
-
- return c;
-}