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authorRalf Baechle <ralf@linux-mips.org>2007-08-01 19:42:37 +0100
committerRalf Baechle <ralf@linux-mips.org>2007-08-27 02:16:49 +0100
commitdc0366bf3cd35e4be89f715ff834a06c590fff7a (patch)
treeab2b0b9e614d10947895656d39ae44dfc8f025a6 /arch/mips/mips-boards
parent99e480d81ca98c25918c460fdb5ca876d7df6178 (diff)
[MIPS] SMTC: Fix secondary VPE interrupt mask initialization.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mips-boards')
-rw-r--r--arch/mips/mips-boards/malta/malta_smtc.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/mips/mips-boards/malta/malta_smtc.c b/arch/mips/mips-boards/malta/malta_smtc.c
index 0fb4c269901..ea8f3bb8ed8 100644
--- a/arch/mips/mips-boards/malta/malta_smtc.c
+++ b/arch/mips/mips-boards/malta/malta_smtc.c
@@ -42,10 +42,11 @@ void prom_init_secondary(void)
myvpe = read_c0_tcbind() & TCBIND_CURVPE;
if (myvpe != 0) {
/* Ideally, this should be done only once per VPE, but... */
- clear_c0_status(STATUSF_IP2);
- set_c0_status(STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP3
- | STATUSF_IP4 | STATUSF_IP5 | STATUSF_IP6
- | STATUSF_IP7);
+ clear_c0_status(ST0_IM);
+ set_c0_status((0x100 << cp0_compare_irq)
+ | (0x100 << MIPS_CPU_IPI_IRQ));
+ if (cp0_perfcount_irq >= 0)
+ set_c0_status(0x100 << cp0_perfcount_irq);
}
smtc_init_secondary();