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authorChris Dearman <chris@mips.com>2006-08-07 15:08:01 +0100
committerRalf Baechle <ralf@linux-mips.org>2006-09-27 13:37:33 +0100
commit847b9dfccad7dd34b2e44b1c6ceeb1c4cb88084a (patch)
tree46374a118b2f42c17aef00ec478021043e56e38b /arch/mips
parentbca70d24c09b740d6fd96b972011644cba8383d6 (diff)
[MIPS] MT: Initialise all writable bits in Cause register to zero.
Recent 34Ks come out of reset with WP enabled on VPE 1 so we take an immediate exception when starting the second VPE. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/kernel/smp-mt.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 93429a4d301..766253c44f3 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -203,7 +203,7 @@ void plat_smp_setup(void)
write_vpe_c0_config( read_c0_config());
/* make sure there are no software interrupts pending */
- write_vpe_c0_cause(read_vpe_c0_cause() & ~(C_SW1|C_SW0));
+ write_vpe_c0_cause(0);
/* Propagate Config7 */
write_vpe_c0_config7(read_c0_config7());