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authorTakashi Iwai <tiwai@suse.de>2009-06-10 07:26:18 +0200
committerTakashi Iwai <tiwai@suse.de>2009-06-10 07:26:18 +0200
commitba252af8d60f543a2a2c03f5574f64007ae9c2f3 (patch)
treea37b2723f0c4ea10447600f321f4df261e45bde6 /arch/powerpc/include
parent07a2039b8eb0af4ff464efd3dfd95de5c02648c6 (diff)
parent74b8f955a73d20b1e22403fd1ef85834fbf38d98 (diff)
Merge branch 'topic/asoc' into for-linus
* topic/asoc: (135 commits) ASoC: Apostrophe patrol ASoC: codec tlv320aic23 fix bogus divide by 0 message ASoC: fix NULL pointer dereference in soc_suspend() ASoC: Fix build error in twl4030.c ASoC: SSM2602: assign last substream to the master when shutting down ASoC: Blackfin: document how anomaly 05000250 is handled ASoC: Blackfin: set the transfer size according the ac97_frame size ASoC: SSM2602: remove unsupported sample rates ASoC: TWL4030: Check the interface format for 4 channel mode ASoC: TWL4030: Use reg_cache in twl4030_init_chip ASoC: Initialise dev for the dummy S/PDIF DAI ASoC: Add dummy S/PDIF codec support ASoC: correct print specifiers for unsigneds ASoC: Modify mpc5200 AC97 driver to use V9 of spin_event_timeout() ASoC: Switch FSL SSI DAI over to symmetric_rates ASoC: Mark MPC5200 AC97 as BROKEN until PowerPC merge issues are resolved ASoC: Fabric bindings for STAC9766 on the Efika ASoC: Support for AC97 on Phytec pmc030 base board. ASoC: AC97 driver for mpc5200 ASoC: Main rewite of the mpc5200 audio DMA code ...
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/mpc52xx_psc.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/mpc52xx_psc.h b/arch/powerpc/include/asm/mpc52xx_psc.h
index a218da6bec7..fb841205745 100644
--- a/arch/powerpc/include/asm/mpc52xx_psc.h
+++ b/arch/powerpc/include/asm/mpc52xx_psc.h
@@ -28,6 +28,10 @@
#define MPC52xx_PSC_MAXNUM 6
/* Programmable Serial Controller (PSC) status register bits */
+#define MPC52xx_PSC_SR_UNEX_RX 0x0001
+#define MPC52xx_PSC_SR_DATA_VAL 0x0002
+#define MPC52xx_PSC_SR_DATA_OVR 0x0004
+#define MPC52xx_PSC_SR_CMDSEND 0x0008
#define MPC52xx_PSC_SR_CDE 0x0080
#define MPC52xx_PSC_SR_RXRDY 0x0100
#define MPC52xx_PSC_SR_RXFULL 0x0200
@@ -61,6 +65,12 @@
#define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001
/* PSC interrupt status/mask bits */
+#define MPC52xx_PSC_IMR_UNEX_RX_SLOT 0x0001
+#define MPC52xx_PSC_IMR_DATA_VALID 0x0002
+#define MPC52xx_PSC_IMR_DATA_OVR 0x0004
+#define MPC52xx_PSC_IMR_CMD_SEND 0x0008
+#define MPC52xx_PSC_IMR_ERROR 0x0040
+#define MPC52xx_PSC_IMR_DEOF 0x0080
#define MPC52xx_PSC_IMR_TXRDY 0x0100
#define MPC52xx_PSC_IMR_RXRDY 0x0200
#define MPC52xx_PSC_IMR_DB 0x0400
@@ -117,6 +127,7 @@
#define MPC52xx_PSC_SICR_SIM_FIR (0x6 << 24)
#define MPC52xx_PSC_SICR_SIM_CODEC_24 (0x7 << 24)
#define MPC52xx_PSC_SICR_SIM_CODEC_32 (0xf << 24)
+#define MPC52xx_PSC_SICR_AWR (1 << 30)
#define MPC52xx_PSC_SICR_GENCLK (1 << 23)
#define MPC52xx_PSC_SICR_I2S (1 << 22)
#define MPC52xx_PSC_SICR_CLKPOL (1 << 21)