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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2008-10-07 11:15:07 +1100
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2008-10-07 11:15:07 +1100
commitfa6428ebfa2197841902b89cbc25334707e2f6eb (patch)
treed139b822bc5447198528defb29f0c0e90d89651c /arch/powerpc/include
parentc9b59da130b4430910e02a80816f317534cd5e53 (diff)
parent3d5fa877bdf65451c78c3b3d581355deea403b80 (diff)
Merge commit 'jwb/jwb-next'
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/dcr-regs.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/dcr-regs.h b/arch/powerpc/include/asm/dcr-regs.h
index 29b0ecef980..828e3aa1f2f 100644
--- a/arch/powerpc/include/asm/dcr-regs.h
+++ b/arch/powerpc/include/asm/dcr-regs.h
@@ -68,6 +68,17 @@
#define SDR0_UART3 0x0123
#define SDR0_CUST0 0x4000
+/* SDR for 405EZ */
+#define DCRN_SDR_ICINTSTAT 0x4510
+#define ICINTSTAT_ICRX 0x80000000
+#define ICINTSTAT_ICTX0 0x40000000
+#define ICINTSTAT_ICTX1 0x20000000
+#define ICINTSTAT_ICTX 0x60000000
+
+/* SDRs (460EX/460GT) */
+#define SDR0_ETH_CFG 0x4103
+#define SDR0_ETH_CFG_ECS 0x00000100 /* EMAC int clk source */
+
/*
* All those DCR register addresses are offsets from the base address
* for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is