diff options
| author | Mike Mason <mmlnx@us.ibm.com> | 2009-07-30 15:42:39 -0700 |
|---|---|---|
| committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2009-09-09 13:29:41 -0700 |
| commit | 6e19314cc98ab9ccc22c30d1c414984ac6de5ce2 (patch) | |
| tree | 2e83662e5e8cc1a0c30bba06008fe1b955c94cd5 /arch/powerpc/platforms/pseries/eeh.c | |
| parent | fe14acd4e7c8178dfb172c1e7a88356657378128 (diff) | |
PCI/powerpc: support PCIe fundamental reset
By default, the EEH framework on powerpc does what's known as a "hot
reset" during recovery of a PCI Express device. We've found a case
where the device needs a "fundamental reset" to recover properly. The
current PCI error recovery and EEH frameworks do not support this
distinction.
The attached patch makes changes to EEH to utilize the new bit field.
Signed-off-by: Mike Mason <mmlnx@us.ibm.com>
Signed-off-by: Richard Lary <rlary@us.ibm.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'arch/powerpc/platforms/pseries/eeh.c')
| -rw-r--r-- | arch/powerpc/platforms/pseries/eeh.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/powerpc/platforms/pseries/eeh.c b/arch/powerpc/platforms/pseries/eeh.c index 989d6462c15..ccd8dd03b8c 100644 --- a/arch/powerpc/platforms/pseries/eeh.c +++ b/arch/powerpc/platforms/pseries/eeh.c @@ -744,7 +744,15 @@ int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state stat static void __rtas_set_slot_reset(struct pci_dn *pdn) { - rtas_pci_slot_reset (pdn, 1); + struct pci_dev *dev = pdn->pcidev; + + /* Determine type of EEH reset required by device, + * default hot reset or fundamental reset + */ + if (dev->needs_freset) + rtas_pci_slot_reset(pdn, 3); + else + rtas_pci_slot_reset(pdn, 1); /* The PCI bus requires that the reset be held high for at least * a 100 milliseconds. We wait a bit longer 'just in case'. */ |