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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-07-24 20:26:25 -0700
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-07-24 20:26:25 -0700
commit0de085bb474f64e4fdb2f1ff3268590792648c7b (patch)
tree67c88c8215b85e01430531dba7d7c8ad73173b67 /arch/powerpc/platforms
parent3836df6b520a2f93033bf53200b12a2cb5137395 (diff)
parente58712111fe6eb7573fd6dd12d80de3bec13f277 (diff)
Merge branch 'for_paulus' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc
* 'for_paulus' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc: (25 commits) [POWERPC] 85xx: Added needed MPC85xx PCI device IDs [POWERPC] Add Freescale PCI VENDOR ID and 8641 device IDs [POWERPC] 85xxCDS: MPC8548 DTS cleanup. [POWERPC] 85xxCDS: Misc 8548 PCI Corrections. [POWERPC] 85xxCDS: Delay 8259 cascade hookup. [POWERPC] 85xxCDS: Make sure restart resets the PCI bus. [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line. [POWERPC] FSL: Add support for PCI-X controllers [POWERPC] Make sure virtual P2P bridge registers are setup on PCIe PHB [POWERPC] Provide ability to setup P2P bridge registers from struct resource [POWERPC] Add basic PCI/PCI Express support for 8544DS board [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime [POWERPC] Removed setup_indirect_pci_nomap [POWERPC] 85xx: Add quirk to ignore bogus FPGA on CDS [POWERPC] 85xx: Added 8568 PCIe support [POWERPC] Fixup resources on pci_bus for PCIe PHB when no device is connected [POWERPC] Add basic PCI node for mpc8568mds board [POWERPC] Use Freescale pci/pcie common code for 85xx boards [POWERPC] Update PCI nodes in the 83xx/85xx boards device tree [POWERPC] Add 8548 CDS PCI express controller node and PCI-X device node ...
Diffstat (limited to 'arch/powerpc/platforms')
-rw-r--r--arch/powerpc/platforms/82xx/mpc82xx_ads.c3
-rw-r--r--arch/powerpc/platforms/83xx/pci.c4
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig6
-rw-r--r--arch/powerpc/platforms/85xx/Makefile2
-rw-r--r--arch/powerpc/platforms/85xx/mpc8544_ds.c241
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx.h1
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_ads.c3
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_cds.c125
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_mds.c7
-rw-r--r--arch/powerpc/platforms/85xx/pci.c91
-rw-r--r--arch/powerpc/platforms/86xx/Kconfig3
-rw-r--r--arch/powerpc/platforms/86xx/Makefile1
-rw-r--r--arch/powerpc/platforms/86xx/mpc86xx.h5
-rw-r--r--arch/powerpc/platforms/86xx/mpc86xx_hpcn.c13
-rw-r--r--arch/powerpc/platforms/86xx/pci.c238
-rw-r--r--arch/powerpc/platforms/chrp/pci.c7
-rw-r--r--arch/powerpc/platforms/embedded6xx/linkstation.c2
17 files changed, 378 insertions, 374 deletions
diff --git a/arch/powerpc/platforms/82xx/mpc82xx_ads.c b/arch/powerpc/platforms/82xx/mpc82xx_ads.c
index da20832b27f..2d1b05b9f8e 100644
--- a/arch/powerpc/platforms/82xx/mpc82xx_ads.c
+++ b/arch/powerpc/platforms/82xx/mpc82xx_ads.c
@@ -553,7 +553,8 @@ static void __init mpc82xx_add_bridge(struct device_node *np)
setup_indirect_pci(hose,
r.start + offsetof(pci_cpm2_t, pci_cfg_addr),
- r.start + offsetof(pci_cpm2_t, pci_cfg_data));
+ r.start + offsetof(pci_cpm2_t, pci_cfg_data),
+ 0);
pci_process_bridge_OF_ranges(hose, np, 1);
}
diff --git a/arch/powerpc/platforms/83xx/pci.c b/arch/powerpc/platforms/83xx/pci.c
index c0e2b89154e..92069469de2 100644
--- a/arch/powerpc/platforms/83xx/pci.c
+++ b/arch/powerpc/platforms/83xx/pci.c
@@ -74,11 +74,11 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
*/
/* PCI 1 */
if ((rsrc.start & 0xfffff) == 0x8500) {
- setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304);
+ setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304, 0);
}
/* PCI 2 */
if ((rsrc.start & 0xfffff) == 0x8600) {
- setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384);
+ setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384, 0);
primary = 0;
}
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 629926e01e9..f58184086c8 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -18,6 +18,7 @@ config MPC8560_ADS
config MPC85xx_CDS
bool "Freescale MPC85xx CDS"
select DEFAULT_UIMAGE
+ select PPC_I8259
help
This option enables support for the MPC85xx CDS board
@@ -30,6 +31,7 @@ config MPC85xx_MDS
config MPC8544_DS
bool "Freescale MPC8544 DS"
+ select PPC_I8259
select DEFAULT_UIMAGE
help
This option enables support for the MPC8544 DS board
@@ -50,9 +52,9 @@ config MPC8560
config MPC85xx
bool
select PPC_UDBG_16550
- select PPC_INDIRECT_PCI
- select PPC_INDIRECT_PCI_BE
+ select PPC_INDIRECT_PCI if PCI
select MPIC
+ select FSL_PCI if PCI
select SERIAL_8250_SHARE_IRQ if SERIAL_8250
default y if MPC8540_ADS || MPC85xx_CDS || MPC8560_ADS \
|| MPC85xx_MDS || MPC8544_DS
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 4e02cbb14cf..d70f2d0f9d3 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -1,7 +1,7 @@
#
# Makefile for the PowerPC 85xx linux kernel.
#
-obj-$(CONFIG_PPC_85xx) += misc.o pci.o
+obj-$(CONFIG_PPC_85xx) += misc.o
obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
diff --git a/arch/powerpc/platforms/85xx/mpc8544_ds.c b/arch/powerpc/platforms/85xx/mpc8544_ds.c
index 6fb90aab879..4905f6f8903 100644
--- a/arch/powerpc/platforms/85xx/mpc8544_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8544_ds.c
@@ -2,6 +2,8 @@
* MPC8544 DS Board Setup
*
* Author Xianghua Xiao (x.xiao@freescale.com)
+ * Roy Zang <tie-fei.zang@freescale.com>
+ * - Add PCI/PCI Exprees support
* Copyright 2007 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
@@ -12,13 +14,16 @@
#include <linux/stddef.h>
#include <linux/kernel.h>
+#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
+#include <linux/interrupt.h>
#include <asm/system.h>
#include <asm/time.h>
#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
#include <asm/mpc85xx.h>
#include <mm/mmu_decl.h>
#include <asm/prom.h>
@@ -27,6 +32,7 @@
#include <asm/i8259.h>
#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
#include "mpc85xx.h"
#undef DEBUG
@@ -37,6 +43,17 @@
#define DBG(fmt, args...)
#endif
+#ifdef CONFIG_PPC_I8259
+static void mpc8544_8259_cascade(unsigned int irq, struct irq_desc *desc)
+{
+ unsigned int cascade_irq = i8259_irq();
+
+ if (cascade_irq != NO_IRQ) {
+ generic_handle_irq(cascade_irq);
+ }
+ desc->chip->eoi(irq);
+}
+#endif /* CONFIG_PPC_I8259 */
void __init mpc8544_ds_pic_init(void)
{
@@ -96,19 +113,240 @@ void __init mpc8544_ds_pic_init(void)
#endif /* CONFIG_PPC_I8259 */
}
+#ifdef CONFIG_PCI
+enum pirq { PIRQA = 8, PIRQB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH };
+
+/*
+ * Value in table -- IRQ number
+ */
+const unsigned char uli1575_irq_route_table[16] = {
+ 0, /* 0: Reserved */
+ 0x8,
+ 0, /* 2: Reserved */
+ 0x2,
+ 0x4,
+ 0x5,
+ 0x7,
+ 0x6,
+ 0, /* 8: Reserved */
+ 0x1,
+ 0x3,
+ 0x9,
+ 0xb,
+ 0, /* 13: Reserved */
+ 0xd,
+ 0xf,
+};
+
+static int __devinit
+get_pci_irq_from_of(struct pci_controller *hose, int slot, int pin)
+{
+ struct of_irq oirq;
+ u32 laddr[3];
+ struct device_node *hosenode = hose ? hose->arch_data : NULL;
+
+ if (!hosenode)
+ return -EINVAL;
+
+ laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(slot, 0) << 8);
+ laddr[1] = laddr[2] = 0;
+ of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
+ DBG("mpc8544_ds: pci irq addr %x, slot %d, pin %d, irq %d\n",
+ laddr[0], slot, pin, oirq.specifier[0]);
+ return oirq.specifier[0];
+}
+
+/*8259*/
+static void __devinit quirk_uli1575(struct pci_dev *dev)
+{
+ unsigned short temp;
+ struct pci_controller *hose = pci_bus_to_host(dev->bus);
+ unsigned char irq2pin[16];
+ unsigned long pirq_map_word = 0;
+ u32 irq;
+ int i;
+
+ /*
+ * ULI1575 interrupts route setup
+ */
+ memset(irq2pin, 0, 16); /* Initialize default value 0 */
+
+ irq2pin[6]=PIRQA+3; /* enabled mapping for IRQ6 to PIRQD, used by SATA */
+
+ /*
+ * PIRQE -> PIRQF mapping set manually
+ *
+ * IRQ pin IRQ#
+ * PIRQE ---- 9
+ * PIRQF ---- 10
+ * PIRQG ---- 11
+ * PIRQH ---- 12
+ */
+ for (i = 0; i < 4; i++)
+ irq2pin[i + 9] = PIRQE + i;
+
+ /* Set IRQ-PIRQ Mapping to ULI1575 */
+ for (i = 0; i < 16; i++)
+ if (irq2pin[i])
+ pirq_map_word |= (uli1575_irq_route_table[i] & 0xf)
+ << ((irq2pin[i] - PIRQA) * 4);
+
+ pirq_map_word |= 1<<26; /* disable INTx in EP mode*/
+
+ /* ULI1575 IRQ mapping conf register default value is 0xb9317542 */
+ DBG("Setup ULI1575 IRQ mapping configuration register value = 0x%x\n",
+ (int)pirq_map_word);
+ pci_write_config_dword(dev, 0x48, pirq_map_word);
+
+#define ULI1575_SET_DEV_IRQ(slot, pin, reg) \
+ do { \
+ int irq; \
+ irq = get_pci_irq_from_of(hose, slot, pin); \
+ if (irq > 0 && irq < 16) \
+ pci_write_config_byte(dev, reg, irq2pin[irq]); \
+ else \
+ printk(KERN_WARNING "ULI1575 device" \
+ "(slot %d, pin %d) irq %d is invalid.\n", \
+ slot, pin, irq); \
+ } while(0)
+
+ /* USB 1.1 OHCI controller 1, slot 28, pin 1 */
+ ULI1575_SET_DEV_IRQ(28, 1, 0x86);
+
+ /* USB 1.1 OHCI controller 2, slot 28, pin 2 */
+ ULI1575_SET_DEV_IRQ(28, 2, 0x87);
+
+ /* USB 1.1 OHCI controller 3, slot 28, pin 3 */
+ ULI1575_SET_DEV_IRQ(28, 3, 0x88);
+
+ /* USB 2.0 controller, slot 28, pin 4 */
+ irq = get_pci_irq_from_of(hose, 28, 4);
+ if (irq >= 0 && irq <= 15)
+ pci_write_config_dword(dev, 0x74, uli1575_irq_route_table[irq]);
+
+ /* Audio controller, slot 29, pin 1 */
+ ULI1575_SET_DEV_IRQ(29, 1, 0x8a);
+
+ /* Modem controller, slot 29, pin 2 */
+ ULI1575_SET_DEV_IRQ(29, 2, 0x8b);
+
+ /* HD audio controller, slot 29, pin 3 */
+ ULI1575_SET_DEV_IRQ(29, 3, 0x8c);
+
+ /* SMB interrupt: slot 30, pin 1 */
+ ULI1575_SET_DEV_IRQ(30, 1, 0x8e);
+
+ /* PMU ACPI SCI interrupt: slot 30, pin 2 */
+ ULI1575_SET_DEV_IRQ(30, 2, 0x8f);
+
+ /* Serial ATA interrupt: slot 31, pin 1 */
+ ULI1575_SET_DEV_IRQ(31, 1, 0x8d);
+
+ /* Primary PATA IDE IRQ: 14
+ * Secondary PATA IDE IRQ: 15
+ */
+ pci_write_config_byte(dev, 0x44, 0x30 | uli1575_irq_route_table[14]);
+ pci_write_config_byte(dev, 0x75, uli1575_irq_route_table[15]);
+
+ /* Set IRQ14 and IRQ15 to legacy IRQs */
+ pci_read_config_word(dev, 0x46, &temp);
+ temp |= 0xc000;
+ pci_write_config_word(dev, 0x46, temp);
+
+ /* Set i8259 interrupt trigger
+ * IRQ 3: Level
+ * IRQ 4: Level
+ * IRQ 5: Level
+ * IRQ 6: Level
+ * IRQ 7: Level
+ * IRQ 9: Level
+ * IRQ 10: Level
+ * IRQ 11: Level
+ * IRQ 12: Level
+ * IRQ 14: Edge
+ * IRQ 15: Edge
+ */
+ outb(0xfa, 0x4d0);
+ outb(0x1e, 0x4d1);
+
+#undef ULI1575_SET_DEV_IRQ
+}
+
+/* SATA */
+static void __devinit quirk_uli5288(struct pci_dev *dev)
+{
+ unsigned char c;
+
+ pci_read_config_byte(dev, 0x83, &c);
+ c |= 0x80; /* read/write lock */
+ pci_write_config_byte(dev, 0x83, c);
+
+ pci_write_config_byte(dev, 0x09, 0x01); /* Base class code: storage */
+ pci_write_config_byte(dev, 0x0a, 0x06); /* IDE disk */
+
+ pci_read_config_byte(dev, 0x83, &c);
+ c &= 0x7f;
+ pci_write_config_byte(dev, 0x83, c);
+
+ pci_read_config_byte(dev, 0x84, &c);
+ c |= 0x01; /* emulated PATA mode enabled */
+ pci_write_config_byte(dev, 0x84, c);
+}
+
+/* PATA */
+static void __devinit quirk_uli5229(struct pci_dev *dev)
+{
+ unsigned short temp;
+ pci_write_config_word(dev, 0x04, 0x0405); /* MEM IO MSI */
+ pci_read_config_word(dev, 0x4a, &temp);
+ temp |= 0x1000; /* Enable Native IRQ 14/15 */
+ pci_write_config_word(dev, 0x4a, temp);
+}
+
+/*Bridge*/
+static void __devinit early_uli5249(struct pci_dev *dev)
+{
+ unsigned char temp;
+ pci_write_config_word(dev, 0x04, 0x0007); /* mem access */
+ pci_read_config_byte(dev, 0x7c, &temp);
+ pci_write_config_byte(dev, 0x7c, 0x80); /* R/W lock control */
+ pci_write_config_byte(dev, 0x09, 0x01); /* set as pci-pci bridge */
+ pci_write_config_byte(dev, 0x7c, temp); /* restore pci bus debug control */
+ dev->class |= 0x1;
+}
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
+#endif /* CONFIG_PCI */
/*
* Setup the architecture
*/
static void __init mpc8544_ds_setup_arch(void)
{
+#ifdef CONFIG_PCI
+ struct device_node *np;
+#endif
+
if (ppc_md.progress)
ppc_md.progress("mpc8544_ds_setup_arch()", 0);
+#ifdef CONFIG_PCI
+ for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
+ struct resource rsrc;
+ of_address_to_resource(np, 0, &rsrc);
+ if ((rsrc.start & 0xfffff) == 0xb000)
+ fsl_add_bridge(np, 1);
+ else
+ fsl_add_bridge(np, 0);
+ }
+#endif
+
printk("MPC8544 DS board from Freescale Semiconductor\n");
}
-
/*
* Called very early, device-tree isn't unflattened
*/
@@ -124,6 +362,7 @@ define_machine(mpc8544_ds) {
.probe = mpc8544_ds_probe,
.setup_arch = mpc8544_ds_setup_arch,
.init_IRQ = mpc8544_ds_pic_init,
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
.get_irq = mpic_get_irq,
.restart = mpc85xx_restart,
.calibrate_decr = generic_calibrate_decr,
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h b/arch/powerpc/platforms/85xx/mpc85xx.h
index 7286ffac2c1..5b34deef12b 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx.h
+++ b/arch/powerpc/platforms/85xx/mpc85xx.h
@@ -15,4 +15,3 @@
*/
extern void mpc85xx_restart(char *);
-extern int mpc85xx_add_bridge(struct device_node *dev);
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index 7235f702394..40a828675c7 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -29,6 +29,7 @@
#include <asm/udbg.h>
#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
#include "mpc85xx.h"
#ifdef CONFIG_CPM2
@@ -217,7 +218,7 @@ static void __init mpc85xx_ads_setup_arch(void)
#ifdef CONFIG_PCI
for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
- mpc85xx_add_bridge(np);
+ fsl_add_bridge(np, 1);
ppc_md.pci_exclude_device = mpc85xx_exclude_device;
#endif
}
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 50c8d645836..6a171e9abf7 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -24,6 +24,7 @@
#include <linux/seq_file.h>
#include <linux/initrd.h>
#include <linux/module.h>
+#include <linux/interrupt.h>
#include <linux/fsl_devices.h>
#include <asm/system.h>
@@ -45,6 +46,7 @@
#include <asm/i8259.h>
#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
#include "mpc85xx.h"
static int cds_pci_slot = 2;
@@ -58,8 +60,6 @@ static volatile u8 *cadmus;
static int mpc85xx_exclude_device(struct pci_controller *hose,
u_char bus, u_char devfn)
{
- if ((bus == hose->first_busno) && PCI_SLOT(devfn) == 0)
- return PCIBIOS_DEVICE_NOT_FOUND;
/* We explicitly do not go past the Tundra 320 Bridge */
if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
return PCIBIOS_DEVICE_NOT_FOUND;
@@ -69,6 +69,37 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
return PCIBIOS_SUCCESSFUL;
}
+static void mpc85xx_cds_restart(char *cmd)
+{
+ struct pci_dev *dev;
+ u_char tmp;
+
+ if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
+ NULL))) {
+
+ /* Use the VIA Super Southbridge to force a PCI reset */
+ pci_read_config_byte(dev, 0x47, &tmp);
+ pci_write_config_byte(dev, 0x47, tmp | 1);
+
+ /* Flush the outbound PCI write queues */
+ pci_read_config_byte(dev, 0x47, &tmp);
+
+ /*
+ * At this point, the harware reset should have triggered.
+ * However, if it doesn't work for some mysterious reason,
+ * just fall through to the default reset below.
+ */
+
+ pci_dev_put(dev);
+ }
+
+ /*
+ * If we can't find the VIA chip (maybe the P2P bridge is disabled)
+ * or the VIA chip reset didn't work, just use the default reset.
+ */
+ mpc85xx_restart(NULL);
+}
+
static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
{
u_char c;
@@ -98,7 +129,7 @@ static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
/* There are two USB controllers.
* Identify them by functon number
*/
- if (PCI_FUNC(dev->devfn))
+ if (PCI_FUNC(dev->devfn) == 3)
dev->irq = 11;
else
dev->irq = 10;
@@ -109,17 +140,41 @@ static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
}
}
+static void __devinit skip_fake_bridge(struct pci_dev *dev)
+{
+ /* Make it an error to skip the fake bridge
+ * in pci_setup_device() in probe.c */
+ dev->hdr_type = 0x7f;
+}
+DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
+DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
+DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
+
#ifdef CONFIG_PPC_I8259
-#warning The i8259 PIC support is currently broken
-static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
+static void mpc85xx_8259_cascade_handler(unsigned int irq,
+ struct irq_desc *desc)
{
unsigned int cascade_irq = i8259_irq();
if (cascade_irq != NO_IRQ)
+ /* handle an interrupt from the 8259 */
generic_handle_irq(cascade_irq);
- desc->chip->eoi(irq);
+ /* check for any interrupts from the shared IRQ line */
+ handle_fasteoi_irq(irq, desc);
+}
+
+static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
+{
+ return IRQ_HANDLED;
}
+
+static struct irqaction mpc85xxcds_8259_irqaction = {
+ .handler = mpc85xx_8259_cascade_action,
+ .flags = IRQF_SHARED,
+ .mask = CPU_MASK_NONE,
+ .name = "8259 cascade",
+};
#endif /* PPC_I8259 */
#endif /* CONFIG_PCI */
@@ -128,10 +183,6 @@ static void __init mpc85xx_cds_pic_init(void)
struct mpic *mpic;
struct resource r;
struct device_node *np = NULL;
-#ifdef CONFIG_PPC_I8259
- struct device_node *cascade_node = NULL;
- int cascade_irq;
-#endif
np = of_find_node_by_type(np, "open-pic");
@@ -155,8 +206,19 @@ static void __init mpc85xx_cds_pic_init(void)
of_node_put(np);
mpic_init(mpic);
+}
+
+#if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI)
+static int mpc85xx_cds_8259_attach(void)
+{
+ int ret;
+ struct device_node *np = NULL;
+ struct device_node *cascade_node = NULL;
+ int cascade_irq;
+
+ if (!machine_is(mpc85xx_cds))
+ return 0;
-#ifdef CONFIG_PPC_I8259
/* Initialize the i8259 controller */
for_each_node_by_type(np, "interrupt-controller")
if (of_device_is_compatible(np, "chrp,iic")) {
@@ -166,22 +228,39 @@ static void __init mpc85xx_cds_pic_init(void)
if (cascade_node == NULL) {
printk(KERN_DEBUG "Could not find i8259 PIC\n");
- return;
+ return -ENODEV;
}
cascade_irq = irq_of_parse_and_map(cascade_node, 0);
if (cascade_irq == NO_IRQ) {
printk(KERN_ERR "Failed to map cascade interrupt\n");
- return;
+ return -ENXIO;
}
i8259_init(cascade_node, 0);
of_node_put(cascade_node);
- set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade);
-#endif /* CONFIG_PPC_I8259 */
+ /*
+ * Hook the interrupt to make sure desc->action is never NULL.
+ * This is required to ensure that the interrupt does not get
+ * disabled when the last user of the shared IRQ line frees their
+ * interrupt.
+ */
+ if ((ret = setup_irq(cascade_irq, &mpc85xxcds_8259_irqaction))) {
+ printk(KERN_ERR "Failed to setup cascade interrupt\n");
+ return ret;
+ }
+
+ /* Success. Connect our low-level cascade handler. */
+ set_irq_handler(cascade_irq, mpc85xx_8259_cascade_handler);
+
+ return 0;
}
+device_initcall(mpc85xx_cds_8259_attach);
+
+#endif /* CONFIG_PPC_I8259 */
+
/*
* Setup the architecture
*/
@@ -218,9 +297,14 @@ static void __init mpc85xx_cds_setup_arch(void)
}
#ifdef CONFIG_PCI
- for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
- mpc85xx_add_bridge(np);
-
+ for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
+ struct resource rsrc;
+ of_address_to_resource(np, 0, &rsrc);
+ if ((rsrc.start & 0xfffff) == 0x8000)
+ fsl_add_bridge(np, 1);
+ else
+ fsl_add_bridge(np, 0);
+ }
ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
ppc_md.pci_exclude_device = mpc85xx_exclude_device;
#endif
@@ -265,7 +349,12 @@ define_machine(mpc85xx_cds) {
.init_IRQ = mpc85xx_cds_pic_init,
.show_cpuinfo = mpc85xx_cds_show_cpuinfo,
.get_irq = mpic_get_irq,
+#ifdef CONFIG_PCI
+ .restart = mpc85xx_cds_restart,
+#else
.restart = mpc85xx_restart,
+#endif
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
};
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 004b80bd0b8..e8003bf00c9 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -46,6 +46,7 @@
#include <asm/prom.h>
#include <asm/udbg.h>
#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
#include <asm/qe.h>
#include <asm/qe_ic.h>
#include <asm/mpic.h>
@@ -94,9 +95,8 @@ static void __init mpc85xx_mds_setup_arch(void)
}
#ifdef CONFIG_PCI
- for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
- mpc85xx_add_bridge(np);
- }
+ for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
+ fsl_add_bridge(np, 1);
of_node_put(np);
#endif
@@ -208,4 +208,5 @@ define_machine(mpc85xx_mds) {
.restart = mpc85xx_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
};
diff --git a/arch/powerpc/platforms/85xx/pci.c b/arch/powerpc/platforms/85xx/pci.c
deleted file mode 100644
index 8118417b736..00000000000
--- a/arch/powerpc/platforms/85xx/pci.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * FSL SoC setup code
- *
- * Maintained by Kumar Gala (see MAINTAINERS for contact information)
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/pci.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/module.h>
-
-#include <asm/system.h>
-#include <asm/atomic.h>
-#include <asm/io.h>
-#include <asm/pci-bridge.h>
-#include <asm/prom.h>
-#include <sysdev/fsl_soc.h>
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...)
-#endif
-
-#ifdef CONFIG_PCI
-int __init mpc85xx_add_bridge(struct device_node *dev)
-{
- int len;
- struct pci_controller *hose;
- struct resource rsrc;
- const int *bus_range;
- int primary = 1, has_address = 0;
- phys_addr_t immr = get_immrbase();
-
- DBG("Adding PCI host bridge %s\n", dev->full_name);
-
- /* Fetch host bridge registers address */
- has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
-
- /* Get bus range if any */
- bus_range = of_get_property(dev, "bus-range", &len);
- if (bus_range == NULL || len < 2 * sizeof(int)) {
- printk(KERN_WARNING "Can't get bus-range for %s, assume"
- " bus 0\n", dev->full_name);
- }
-
- pci_assign_all_buses = 1;
- hose = pcibios_alloc_controller(dev);
- if (!hose)
- return -ENOMEM;
-
- hose->first_busno = bus_range ? bus_range[0] : 0;
- hose->last_busno = bus_range ? bus_range[1] : 0xff;
-
- /* PCI 1 */
- if ((rsrc.start & 0xfffff) == 0x8000) {
- setup_indirect_pci(hose, immr + 0x8000, immr + 0x8004);
- }
- /* PCI 2 */
- if ((rsrc.start & 0xfffff) == 0x9000) {
- setup_indirect_pci(hose, immr + 0x9000, immr + 0x9004);
- primary = 0;
- }
-
- printk(KERN_INFO "Found MPC85xx PCI host bridge at 0x%016llx. "
- "Firmware bus number: %d->%d\n",
- (unsigned long long)rsrc.start, hose->first_busno,
- hose->last_busno);
-
- DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
- hose, hose->cfg_addr, hose->cfg_data);
-
- /* Interpret the "ranges" property */
- /* This also maps the I/O region and sets isa_io/mem_base */
- pci_process_bridge_OF_ranges(hose, dev, primary);
-
- return 0;
-}
-
-#endif
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
index 0faebfdc159..343b76d0d79 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -14,8 +14,7 @@ endchoice
config MPC8641
bool
- select PPC_INDIRECT_PCI
- select PPC_INDIRECT_PCI_BE
+ select FSL_PCI if PCI
select PPC_UDBG_16550
select MPIC
default y if MPC8641_HPCN
diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile
index 418fd8f4d26..3376c7767f2 100644
--- a/arch/powerpc/platforms/86xx/Makefile
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -4,4 +4,3 @@
obj-$(CONFIG_SMP) += mpc86xx_smp.o
obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/powerpc/platforms/86xx/mpc86xx.h b/arch/powerpc/platforms/86xx/mpc86xx.h
index 23f7ed2a7f8..525ffa1904f 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx.h
+++ b/arch/powerpc/platforms/86xx/mpc86xx.h
@@ -15,11 +15,6 @@
* mpc86xx_* files. Mostly for use by mpc86xx_setup().
*/
-extern int mpc86xx_add_bridge(struct device_node *dev);
-
-extern int mpc86xx_exclude_device(struct pci_controller *hose,
- u_char bus, u_char devfn);
-
extern void __init mpc86xx_smp_init(void);
#endif /* __MPC86XX_H__ */
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index 5b01ec7c13d..e9eaa0749ae 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -31,6 +31,7 @@
#include <asm/mpic.h>
+#include <sysdev/fsl_pci.h>
#include <sysdev/fsl_soc.h>
#include "mpc86xx.h"
@@ -344,8 +345,14 @@ mpc86xx_hpcn_setup_arch(void)
}
#ifdef CONFIG_PCI
- for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
- mpc86xx_add_bridge(np);
+ for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
+ struct resource rsrc;
+ of_address_to_resource(np, 0, &rsrc);
+ if ((rsrc.start & 0xfffff) == 0x8000)
+ fsl_add_bridge(np, 1);
+ else
+ fsl_add_bridge(np, 0);
+ }
#endif
printk("MPC86xx HPCN board from Freescale Semiconductor\n");
@@ -424,7 +431,6 @@ mpc86xx_time_init(void)
return 0;
}
-
define_machine(mpc86xx_hpcn) {
.name = "MPC86xx HPCN",
.probe = mpc86xx_hpcn_probe,
@@ -436,4 +442,5 @@ define_machine(mpc86xx_hpcn) {
.time_init = mpc86xx_time_init,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
};
diff --git a/arch/powerpc/platforms/86xx/pci.c b/arch/powerpc/platforms/86xx/pci.c
deleted file mode 100644
index 73cd5b05a84..00000000000
--- a/arch/powerpc/platforms/86xx/pci.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * MPC86XX pci setup code
- *
- * Recode: ZHANG WEI <wei.zhang@freescale.com>
- * Initial author: Xianghua Xiao <x.xiao@freescale.com>
- *
- * Copyright 2006 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/types.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/serial.h>
-
-#include <asm/system.h>
-#include <asm/atomic.h>
-#include <asm/io.h>
-#include <asm/prom.h>
-#include <asm/pci-bridge.h>
-#include <sysdev/fsl_soc.h>
-#include <sysdev/fsl_pcie.h>
-
-#include "mpc86xx.h"
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
-#else
-#define DBG(fmt, args...)
-#endif
-
-struct pcie_outbound_window_regs {
- uint pexotar; /* 0x.0 - PCI Express outbound translation address register */
- uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */
- uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */
- char res1[4];
- uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */
- char res2[12];
-};
-
-struct pcie_inbound_window_regs {
- uint pexitar; /* 0x.0 - PCI Express inbound translation address register */
- char res1[4];
- uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */
- uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */
- uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */
- char res2[12];
-};
-
-static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc)
-{
- volatile struct ccsr_pex *pcie;
- volatile struct pcie_outbound_window_regs *pcieow;
- volatile struct pcie_inbound_window_regs *pcieiw;
- int i = 0;
-
- DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start,
- rsrc->end - rsrc->start + 1);
- pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
-
- /* Disable all windows (except pexowar0 since its ignored) */
- pcie->pexowar1 = 0;
- pcie->pexowar2 = 0;
- pcie->pexowar3 = 0;
- pcie->pexowar4 = 0;
- pcie->pexiwar1 = 0;
- pcie->pexiwar2 = 0;
- pcie->pexiwar3 = 0;
-
- pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1;
- pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1;
-
- /* Setup outbound MEM window */
- for(i = 0; i < 3; i++)
- if (hose->mem_resources[i].flags & IORESOURCE_MEM){
- DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n",
- hose->mem_resources[i].start,
- hose->mem_resources[i].end
- - hose->mem_resources[i].start + 1);
- pcieow->pexotar = (hose->mem_resources[i].start) >> 12
- & 0x000fffff;
- pcieow->pexotear = 0;
- pcieow->pexowbar = (hose->mem_resources[i].start) >> 12
- & 0x000fffff;
- /* Enable, Mem R/W */
- pcieow->pexowar = 0x80044000 |
- (__ilog2(hose->mem_resources[i].end
- - hose->mem_resources[i].start + 1)
- - 1);
- pcieow++;
- }
-
- /* Setup outbound IO window */
- if (hose->io_resource.flags & IORESOURCE_IO){
- DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
- hose->io_resource.start,
- hose->io_resource.end - hose->io_resource.start + 1,
- hose->io_base_phys);
- pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff;
- pcieow->pexotear = 0;
- pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff;
- /* Enable, IO R/W */
- pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end
- - hose->io_resource.start + 1) - 1);
- }
-
- /* Setup 2G inbound Memory Window @ 0 */
- pcieiw->pexitar = 0x00000000;
- pcieiw->pexiwbar = 0x00000000;
- /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
- pcieiw->pexiwar = 0xa0f5501e;
-}
-
-static void __init
-mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
-{
- u16 cmd;
-
- DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
- pcie_offset, pcie_size);
-
- early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
- cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
- | PCI_COMMAND_IO;
- early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
-
- early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
-}
-
-static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev)
-{
- struct resource *res;
- int i, res_idx = PCI_BRIDGE_RESOURCES;
- struct pci_controller *hose;
-
- /*
- * Make the bridge be transparent.
- */
- dev->transparent = 1;
-
- hose = pci_bus_to_host(dev->bus);
- if (!hose) {
- printk(KERN_ERR "Can't find hose for bus %d\n",
- dev->bus->number);
- return;
- }
-
- if (hose->io_resource.flags) {
- res = &dev->resource[res_idx++];
- res->start = hose->io_resource.start;
- res->end = hose->io_resource.end;
- res->flags = hose->io_resource.flags;
- }
-
- for (i = 0; i < 3; i++) {
- res = &dev->resource[res_idx + i];
- res->start = hose->mem_resources[i].start;
- res->end = hose->mem_resources[i].end;
- res->flags = hose->mem_resources[i].flags;
- }
-}
-
-
-DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent);
-DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);
-
-#define PCIE_LTSSM 0x404 /* PCIe Link Training and Status */
-#define PCIE_LTSSM_L0 0x16 /* L0 state */
-
-int __init mpc86xx_add_bridge(struct device_node *dev)
-{
- int len;
- struct pci_controller *hose;
- struct resource rsrc;
- const int *bus_range;
- int has_address = 0;
- int primary = 0;
- u16 val;
-
- DBG("Adding PCIE host bridge %s\n", dev->full_name);
-
- /* Fetch host bridge registers address */
- has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
-
- /* Get bus range if any */
- bus_range = of_get_property(dev, "bus-range", &len);
- if (bus_range == NULL || len < 2 * sizeof(int))
- printk(KERN_WARNING "Can't get bus-range for %s, assume"
- " bus 0\n", dev->full_name);
-
- pci_assign_all_buses = 1;
- hose = pcibios_alloc_controller(dev);
- if (!hose)
- return -ENOMEM;
-
- hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
- PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
-
- hose->first_busno = bus_range ? bus_range[0] : 0x0;
- hose->last_busno = bus_range ? bus_range[1] : 0xff;
-
- setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4);
-
- /* Probe the hose link training status */
- early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
- if (val < PCIE_LTSSM_L0)
- return -ENXIO;
-
- /* Setup the PCIE host controller. */
- mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1);
-
- if ((rsrc.start & 0xfffff) == 0x8000)
- primary = 1;
-
- printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. "
- "Firmware bus number: %d->%d\n",
- (unsigned long) rsrc.start,
- hose->first_busno, hose->last_busno);
-
- DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
- hose, hose->cfg_addr, hose->cfg_data);
-
- /* Interpret the "ranges" property */
- /* This also maps the I/O region and sets isa_io/mem_base */
- pci_process_bridge_OF_ranges(hose, dev, primary);
-
- /* Setup PEX window registers */
- setup_pcie_atmu(hose, &rsrc);
-
- return 0;
-}
diff --git a/arch/powerpc/platforms/chrp/pci.c b/arch/powerpc/platforms/chrp/pci.c
index 3690624e49d..28d1647b204 100644
--- a/arch/powerpc/platforms/chrp/pci.c
+++ b/arch/powerpc/platforms/chrp/pci.c
@@ -181,7 +181,7 @@ setup_python(struct pci_controller *hose, struct device_node *dev)
}
iounmap(reg);
- setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010);
+ setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010, 0);
}
/* Marvell Discovery II based Pegasos 2 */
@@ -277,13 +277,14 @@ chrp_find_bridges(void)
hose->cfg_data = p;
gg2_pci_config_base = p;
} else if (is_pegasos == 1) {
- setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
+ setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc, 0);
} else if (is_pegasos == 2) {
setup_peg2(hose, dev);
} else if (!strncmp(model, "IBM,CPC710", 10)) {
setup_indirect_pci(hose,
r.start + 0x000f8000,
- r.start + 0x000f8010);
+ r.start + 0x000f8010,
+ 0);
if (index == 0) {
dma = of_get_property(dev, "system-dma-base",
&len);
diff --git a/arch/powerpc/platforms/embedded6xx/linkstation.c b/arch/powerpc/platforms/embedded6xx/linkstation.c
index f4d0a7a603f..bd5ca58345a 100644
--- a/arch/powerpc/platforms/embedded6xx/linkstation.c
+++ b/arch/powerpc/platforms/embedded6xx/linkstation.c
@@ -73,7 +73,7 @@ static int __init linkstation_add_bridge(struct device_node *dev)
return -ENOMEM;
hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
- setup_indirect_pci(hose, 0xfec00000, 0xfee00000);
+ setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0);
/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */