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authorMasato Noguchi <Masato.Noguchi@jp.sony.com>2007-09-07 18:28:27 +1000
committerPaul Mackerras <paulus@samba.org>2007-09-11 04:30:36 +1000
commitb7f90a406ff72d6698b619210c205e3375dd099a (patch)
tree04897cefacd9589699f99dcd50f6469a9cab687f /arch/powerpc/platforms
parentb21010ed6498391c0f359f2a89c907533fe07fec (diff)
[POWERPC] cell/PS3: Fix a bug that causes the PS3 to hang on the SPU Class 0 interrupt.
The Cell BE Architecture spec states that the SPU MFC Class 0 interrupt is edge-triggered. The current spu interrupt handler assumes this behavior and does not clear the interrupt status. The PS3 hypervisor visualizes all SPU interrupts as level, and on return from the interrupt handler the hypervisor will deliver a new virtual interrupt for any unmasked interrupts which for which the status has not been cleared. This fix clears the interrupt status in the interrupt handler. Signed-off-by: Masato Noguchi <Masato.Noguchi@jp.sony.com> Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Acked-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/platforms')
-rw-r--r--arch/powerpc/platforms/cell/spu_base.c24
1 files changed, 15 insertions, 9 deletions
diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c
index 095a30304c5..106d2921e2d 100644
--- a/arch/powerpc/platforms/cell/spu_base.c
+++ b/arch/powerpc/platforms/cell/spu_base.c
@@ -236,27 +236,34 @@ static irqreturn_t
spu_irq_class_0(int irq, void *data)
{
struct spu *spu;
+ unsigned long stat, mask;
spu = data;
- spu->class_0_pending = 1;
+
+ mask = spu_int_mask_get(spu, 0);
+ stat = spu_int_stat_get(spu, 0);
+ stat &= mask;
+
+ spin_lock(&spu->register_lock);
+ spu->class_0_pending |= stat;
+ spin_unlock(&spu->register_lock);
+
spu->stop_callback(spu);
+ spu_int_stat_clear(spu, 0, stat);
+
return IRQ_HANDLED;
}
int
spu_irq_class_0_bottom(struct spu *spu)
{
- unsigned long stat, mask;
unsigned long flags;
-
- spu->class_0_pending = 0;
+ unsigned long stat;
spin_lock_irqsave(&spu->register_lock, flags);
- mask = spu_int_mask_get(spu, 0);
- stat = spu_int_stat_get(spu, 0);
-
- stat &= mask;
+ stat = spu->class_0_pending;
+ spu->class_0_pending = 0;
if (stat & 1) /* invalid DMA alignment */
__spu_trap_dma_align(spu);
@@ -267,7 +274,6 @@ spu_irq_class_0_bottom(struct spu *spu)
if (stat & 4) /* error on SPU */
__spu_trap_error(spu);
- spu_int_stat_clear(spu, 0, stat);
spin_unlock_irqrestore(&spu->register_lock, flags);
return (stat & 0x7) ? -EIO : 0;