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authorVictor Gallardo <vgallardo@amcc.com>2008-10-01 23:37:57 -0700
committerJosh Boyer <jwboyer@linux.vnet.ibm.com>2008-10-02 13:06:42 -0400
commit9e3cb29497561c846d0e7efc445731764d93c749 (patch)
treefec0caf2a561850074bfcb29013603d2fde9b056 /arch/powerpc
parent5a013fc7bb48acefe94011f4b83fef95b381f875 (diff)
ibm_newemac: Add support for GPCS, SGMII and M88E1112 PHY
Add support for the phy types found on the Arches and other PowerPC 460 based boards. Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/include/asm/dcr-regs.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/dcr-regs.h b/arch/powerpc/include/asm/dcr-regs.h
index 7b833ff9c14..828e3aa1f2f 100644
--- a/arch/powerpc/include/asm/dcr-regs.h
+++ b/arch/powerpc/include/asm/dcr-regs.h
@@ -75,6 +75,10 @@
#define ICINTSTAT_ICTX1 0x20000000
#define ICINTSTAT_ICTX 0x60000000
+/* SDRs (460EX/460GT) */
+#define SDR0_ETH_CFG 0x4103
+#define SDR0_ETH_CFG_ECS 0x00000100 /* EMAC int clk source */
+
/*
* All those DCR register addresses are offsets from the base address
* for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is